sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵	Robert Norton
	and tests.
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur
	This is now split into instructions, regs, memory and platform, each controlled individually. Currently all are enabled and not connected to any command-line options, so a recompile is needed for trace tuning.
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ↵	Prashanth Mundkur
	faults.
2018-10-13	Adapt checked_mem_read to have acquire/release/reserve arguments so	Christopher Pulte
	that this information propagates from the instruction definition to the memory accesses. Necessary for Promising RISC-V concurrency model.
2018-09-10	RISC-V: move the PC and minstret updates into the step function, to better ↵	Prashanth Mundkur
	localize them, making loop() purely a platform function.
2018-07-20	Add assorted comments, consistency fixes and cleanup.	Prashanth Mundkur

2018-07-08	Make the riscv fetch-execute loop return instead of exiting when done.	Prashanth Mundkur

2018-07-03	Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ↵	Prashanth Mundkur
	port.
2018-06-25	Increment the riscv trace step counter only when instructions are executed.	Prashanth Mundkur

2018-06-25	Fix riscv interrupt pending check to handle implicit enabling at lower ↵	Prashanth Mundkur
	privileges. Also fix timer threshold comparison to be <= instead of <.
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur
	Fix a redundant clock tick.
2018-06-22	Some more riscv trace log tweaking for spike compatibility.	Prashanth Mundkur

2018-06-22	More trace log tweaks.	Prashanth Mundkur

2018-06-19	Add more detail to riscv execution trace log.	Prashanth Mundkur

2018-06-11	Use riscv platform insns_per_tick to tick the clock.	Prashanth Mundkur

2018-06-09	Increment minstret on instruction retires, and handle the case when the ↵	Prashanth Mundkur
	minstret CSR is explicitly written to.
2018-06-08	Slightly condense execution trace log.	Prashanth Mundkur

2018-06-08	Make the simulation loop use the platform interface to detect exits via htif.	Prashanth Mundkur

2018-05-21	Move the top-level loop from main to riscv_step, but remove elf bits.	Prashanth Mundkur

2018-05-04	Tweak the execution log.	Prashanth Mundkur

2018-05-03	Fix interrupt dispatch, improve execution logs, cleanup unused bits.	Prashanth Mundkur

2018-05-03	Simplify the top-level execute loop using the step function.	Prashanth Mundkur

2018-05-03	Fix up interrupt and exception dispatch.	Prashanth Mundkur

2018-05-03	Implement fetch to properly handle RVC and address translation, and add a ↵	Prashanth Mundkur
	step function for execution.