| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-06-19 | Add more detail to riscv execution trace log. | Prashanth Mundkur |
| 2018-06-11 | Use riscv platform insns_per_tick to tick the clock. | Prashanth Mundkur |
| 2018-06-09 | Increment minstret on instruction retires, and handle the case when the minst... | Prashanth Mundkur |
| 2018-06-08 | Slightly condense execution trace log. | Prashanth Mundkur |
| 2018-06-08 | Make the simulation loop use the platform interface to detect exits via htif. | Prashanth Mundkur |
| 2018-05-21 | Move the top-level loop from main to riscv_step, but remove elf bits. | Prashanth Mundkur |
| 2018-05-04 | Tweak the execution log. | Prashanth Mundkur |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur |
| 2018-05-03 | Simplify the top-level execute loop using the step function. | Prashanth Mundkur |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur |
| 2018-05-03 | Implement fetch to properly handle RVC and address translation, and add a ste... | Prashanth Mundkur |
 |
index : sail | |
| Formal specification language for ISAs |
| summaryrefslogtreecommitdiff |