sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵	Robert Norton
	and tests.
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ↵	Prashanth Mundkur
	faults.
2018-10-23	RISC-V: implement terminal output for C platform.	Prashanth Mundkur

2018-10-23	RISC-V: fix up platform bits for lr/sc.	Prashanth Mundkur

2018-10-23	RISC-V: set htif tohost port address using ELF symbol.	Prashanth Mundkur

2018-10-23	Fix typo in plat_ram_size	Alasdair Armstrong

2018-10-23	RISC-V: Add some debug logs for within_phys_mem.	Prashanth Mundkur

2018-10-23	RISC-V: Refactor c platform bits.	Prashanth Mundkur

2018-09-07	RISCV: Run RISC-V tests using version compiled to C	Alasdair Armstrong
	Current pass rate is 170 out of 181. Looks like there are some issues with rv64ua-p-lrsc.elf, rv64ua-v-lrsc.elf, and rv64uc-p-rvc.elf which I think are caused by me not implementing parts of the RISC-V platform correctly in C. Some of the div and mod tests also fail, which is probably an issue with using the correct rounding.
2018-09-06	RISCV: Get enough of the RISCV platform into C to run some tests	Alasdair Armstrong

2018-09-04	C: Tweaks to RISC-V to get compiling to C	Alasdair Armstrong
	Revert a change to string_of_bits because it broke all the RISC-V tests in OCaml. string_of_int (int_of_string x) is not valid because x may not fit within an integer.
2018-08-31	Some C stubs for platform bits for RISC-V.	Prashanth Mundkur