| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-07-11 | RISC-V model fixes for RMEM | Jon French | |
| 2018-07-10 | RISCV load-acquire in Lem (-> rmem) | Jon French | |
| 2018-07-07 | An initial fix to riscv lr/sc, needs a review. | Prashanth Mundkur | |
| This uses a stronger model than the version in Sail-1 in order to perform address alignment checks. The reservation is kept on virtual addresses, and maintained in the platform model, but now the lr/sc definitions need calls to externs to update this state. An alternative was to reserve physical addresses, but that appeared to be more complicated without a lot more changes. Ideally, the model should be parameterizable over both options. | |||
| 2018-07-05 | print to stdout not stderr to stop upsetting rmem regression tests | Jon French | |
| 2018-07-05 | restore missing RISC-V fence types in sail2; ignore io bits in fences more ↵ | Jon French | |
| cleanly | |||
| 2018-06-28 | further changes to support rmem | Jon French | |
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index : sail | |
| Formal specification language for ISAs |
| summaryrefslogtreecommitdiff |