| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-05-10 | more mapping | Jon French | |
| 2018-05-10 | load-type riscv assembly | Jon French | |
| 2018-05-10 | rtype mapping clauses | Jon French | |
| 2018-05-10 | move common mappings to riscv_types.sail | Jon French | |
| 2018-05-10 | hacky monomorphic bits-string-parser for now | Jon French | |
| 2018-05-10 | Merge branch 'sail2' into mappings | Jon French | |
| 2018-05-10 | refining spaces mappings | Jon French | |
| 2018-05-09 | Remove unused definitions. | Prashanth Mundkur | |
| 2018-05-09 | start of riscv assembly mappings | Jon French | |
| 2018-05-07 | Add a register indicating no trigger/breakpoint support, which allows the ↵ | Prashanth Mundkur | |
| breakpoint test to pass. | |||
| 2018-05-07 | Fix a missed csr read. | Prashanth Mundkur | |
| 2018-05-04 | Fix printing of ld. | Prashanth Mundkur | |
| 2018-05-03 | Fix a typo in sret decode and privilege checks in xret. | Prashanth Mundkur | |
| 2018-05-03 | Add implementation of sfence with a fixme note. | Prashanth Mundkur | |
| 2018-05-03 | Implement wfi, and cleanup handling illegal operations. | Prashanth Mundkur | |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur | |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur | |
| 2018-05-03 | Hook in address translation for stores and atomics. | Prashanth Mundkur | |
| 2018-05-03 | Log csr writes in the execution log. | Prashanth Mundkur | |
| 2018-05-02 | Hook in address translation for loads. | Prashanth Mundkur | |
| 2018-05-02 | Fix printing of csr immediates. | Prashanth Mundkur | |
| 2018-04-26 | Initial support for faults of writes to physical addresses. | Prashanth Mundkur | |
| 2018-04-26 | Initial support for faults of reads to physical addresses. | Prashanth Mundkur | |
| 2018-04-20 | Fix a typo. | Prashanth Mundkur | |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur | |
| 2018-04-20 | Some cleanup and comments. | Prashanth Mundkur | |
| 2018-04-17 | Implement sret. | Prashanth Mundkur | |
| 2018-04-16 | Implement the s-mode views of mie/mip, and their legalizers. | Prashanth Mundkur | |
| 2018-04-16 | Add the satp legalizer. | Prashanth Mundkur | |
| 2018-04-13 | Add some checks of current state, and use for the xepc write legalizer. | Prashanth Mundkur | |
| 2018-04-13 | Some initial legalizers for writes to S-mode CSRs. | Prashanth Mundkur | |
| 2018-04-13 | Define legalizers for writes to M-mode CSRs, and hook these writes to use them. | Prashanth Mundkur | |
| 2018-04-13 | Fix access checks to riscv CSRs. | Prashanth Mundkur | |
| 2018-04-11 | Initial bits of supervisor state. | Prashanth Mundkur | |
| 2018-04-11 | Add some misc informational m-mode registers that are used in a test. | Prashanth Mundkur | |
| 2018-04-11 | More structured riscv trap vector handling. | Prashanth Mundkur | |
| 2018-04-09 | Update riscv to use the new system definitions, remove duplicates. | Prashanth Mundkur | |
| 2018-03-07 | Make union types consistent in the AST | Alasdair Armstrong | |
| Previously union types could have no-argument constructors, for example the option type was previously: union option ('a : Type) = { Some : 'a, None } Now every union constructor must have a type, so option becomes: union option ('a : Type) = { Some : 'a, None : unit } The reason for this is because previously these two different types of constructors where very different in the AST, constructors with arguments were used the E_app AST node, and no-argument constructors used the E_id node. This was particularly awkward, because it meant that E_id nodes could have polymorphic types, i.e. every E_id node that was also a union constructor had to be annotated with a type quantifier, in constrast with all other identifiers that have unquantified types. This became an issue when monomorphising types, because the machinery for figuring out function instantiations can't be applied to identifier nodes. The same story occurs in patterns, where previously unions were split across P_id and P_app nodes - now the P_app node alone is used solely for unions. This is a breaking change because it changes the syntax for union constructors - where as previously option was matched as: function is_none opt = match opt { Some(_) => false, None => true } it is now matched as function is_none opt = match opt { Some(_) => false, None() => true } note that constructor() is syntactic sugar for constructor(()), i.e. a one argument constructor with unit as it's value. This is exactly the same as for functions where a unit-function can be called as f() and not as f(()). (This commit also makes exit() work consistently in the same way) An attempt to pattern match a variable with the same name as a union-constructor now gives an error as a way to guard against mistakes made because of this change. There is probably an argument for supporting the old syntax via some syntactic sugar, as it is slightly prettier that way, but for now I have chosen to keep the implementation as simple as possible. The RISCV spec, ARM spec, and tests have been updated to account for this change. Furthermore the option type can now be included from $SAIL_DIR/lib/ using $include <option.sail> | |||
| 2018-02-06 | Fixed some bugs in the RVC spec; the rvc test now passes. | Prashanth Mundkur | |
| - fixed mapping of cregs to regs - fixed interpretation of NOP - fixed sign-extension for C.LW - added C.LD - fixed cut-paste errors in C.XOR, C.AND - fixed interpretations of C.ADDW, C.SUBW - fixed decode of C.LDSP | |||
| 2018-02-06 | some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ↵ | Robert Norton | |
| overloaded accessor functions for X registers. | |||
| 2018-02-06 | Add remaining RVC instructions. | Prashanth Mundkur | |
| 2018-02-02 | Added remaining compressed instructions in Quadrant 0 and 1, Quadrant 2 remains. | Prashanth Mundkur | |
| 2018-02-02 | Add M extension to RISCV. Slightly inelegant implementation for now but ↵ | Robert Norton | |
| passing tests. | |||
| 2018-02-02 | Add some more compressed instruction specs, and slightly clean up previous ones. | Prashanth Mundkur | |
| 2018-02-01 | Use the recursive execute for c.addi4spn. | Prashanth Mundkur | |
| Conversations with Alexandre/Jon indicate that a BSV generator should be able to deal with this recursion, and Thomas has fixed the Lem generator. | |||
| 2018-02-01 | badaddr is a misleading name, since it could contain what the PC points to ↵ | Prashanth Mundkur | |
| for illegal-instruction exceptions. changed to excinfo. | |||
| 2018-02-01 | riscv: avoid name clash with global function 'unsigned'. | Robert Norton | |
| 2018-02-01 | Add c.addi4spn. | Prashanth Mundkur | |
| 2018-02-01 | Fix encoding for compressed ILLEGAL. | Prashanth Mundkur | |
| 2018-02-01 | Initial top-level support for compression instructions. | Prashanth Mundkur | |
| - introduce the misa register - check the appropriate instruction bits to decide whether it is compressed - check misa.C to decide whether we can execute compressed instructions - add a decodeCompressed function - add two of the most basic RVC instructions: NOP and ILLEGAL | |||
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index : sail | |
| Formal specification language for ISAs |
| summaryrefslogtreecommitdiff |