sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵	Robert Norton
	and tests.
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur

2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ↵	Prashanth Mundkur
	faults.
2018-07-10	Add an option to specify the dtc to use for the riscv platform.	Prashanth Mundkur

2018-07-09	Log some timing info at the end of riscv execution.	Prashanth Mundkur

2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ↵	Prashanth Mundkur
	access, and a cli option to control it.
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur
	Fix a redundant clock tick.
2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur

2018-06-22	More trace log tweaks.	Prashanth Mundkur

2018-06-11	Put the riscv model's output on stderr, leaving stdout for the platform ↵	Prashanth Mundkur
	terminal.
2018-06-04	Add the htif exit command, a top-level function to initialize the riscv ↵	Prashanth Mundkur
	platform, and document the artificial wreg effect due to using registers for device state.
2018-05-21	Start platform execution at the reset-vector in the rom.	Prashanth Mundkur

2018-05-21	Add in the platform files and update the ocaml build. Disable the isabelle ↵	Prashanth Mundkur
	build until we add suitable platform definitions/stubs. The platform bits are not yet hooked into the model, but only into the build, so are untested.