sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵	Robert Norton
	and tests.
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur

2018-10-23	RISC-V: use stderr for terminal output in OCaml backend.	Prashanth Mundkur
	Also add a brief README for booting Linux on the C and OCaml backends.
2018-07-10	Add an option to specify the dtc to use for the riscv platform.	Prashanth Mundkur

2018-07-03	Allow the riscv htif_tohost mmio port to be readable, and ack writes to that ↵	Prashanth Mundkur
	port.
2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur

2018-06-13	Tracing instrumentation for C backend	Alasdair Armstrong

2018-06-07	Add terminal output to riscv platform, with incomplete handling of input.	Prashanth Mundkur

2018-05-23	Fix incorrect channel in dtc i/o.	Prashanth Mundkur

2018-05-21	Start platform execution at the reset-vector in the rom.	Prashanth Mundkur

2018-05-21	Add in the platform files and update the ocaml build. Disable the isabelle ↵	Prashanth Mundkur
	build until we add suitable platform definitions/stubs. The platform bits are not yet hooked into the model, but only into the build, so are untested.