sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ↵	Robert Norton
	and tests.
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur
	This is now split into instructions, regs, memory and platform, each controlled individually. Currently all are enabled and not connected to any command-line options, so a recompile is needed for trace tuning.
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur

2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ↵	Prashanth Mundkur
	faults.
2018-07-07	Cancel riscv reservation before i/o scheduling, tweak reservation tracing.	Prashanth Mundkur

2018-07-07	An initial fix to riscv lr/sc, needs a review.	Prashanth Mundkur
	This uses a stronger model than the version in Sail-1 in order to perform address alignment checks. The reservation is kept on virtual addresses, and maintained in the platform model, but now the lr/sc definitions need calls to externs to update this state. An alternative was to reserve physical addresses, but that appeared to be more complicated without a lot more changes. Ideally, the model should be parameterizable over both options.
2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ↵	Prashanth Mundkur
	access, and a cli option to control it.
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur
	Fix a redundant clock tick.
2018-06-22	Add cli options to riscv simulator to dump platform device-tree info.	Prashanth Mundkur

2018-06-11	Use riscv platform insns_per_tick to tick the clock.	Prashanth Mundkur

2018-06-11	Put the riscv model's output on stderr, leaving stdout for the platform ↵	Prashanth Mundkur
	terminal.
2018-06-08	Make the simulation loop use the platform interface to detect exits via htif.	Prashanth Mundkur

2018-06-07	More definitions for the physical memory map.	Prashanth Mundkur

2018-06-07	Add terminal output to riscv platform, with incomplete handling of input.	Prashanth Mundkur

2018-05-21	Add in the platform files and update the ocaml build. Disable the isabelle ↵	Prashanth Mundkur
	build until we add suitable platform definitions/stubs. The platform bits are not yet hooked into the model, but only into the build, so are untested.