sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-01-03	Updates to interpreter	Alasdair Armstrong
	Experimenting with porting riscv model to new typechecker
2017-11-23	renaming	Shaked Flur

2017-11-23	added RISCV_ prefix to some values to stop Lem from renaming them	Shaked Flur

2017-11-01	added RISC-V "fence r,r"	Shaked Flur

2017-10-26	fixed release acquire semantics of AMOs	Shaked Flur

2017-10-01	fixed JALR: do the register write first to allow po-later reads	Shaked Flur

2017-09-27	split RISC-V to two Sail files to make it more readable	Shaked Flur

2017-09-27	oops	Shaked Flur

2017-09-26	RISC-V: check alignment of atomic memory accesses (and escape when misaligned)	Shaked Flur

2017-09-03	added RISC-V strong-acquire/release	Shaked Flur

2017-09-02	check the status of SC before doing the memory write	Shaked Flur

2017-08-31	added RISC-V AMOs	Shaked Flur

2017-08-22	added RISC-V "fence w,w" and "fence.i";	Shaked Flur
	fixed the interpreter nias analysis;
2017-08-21	RISC-V load-reserved and store-conditional	Shaked Flur

2017-08-19	RISC-V store-release	Shaked Flur

2017-08-17	added RISC-V load-acquire	Shaked Flur

2017-08-17	fixed the RISC-V fences (3 types: "rw,rw"/"r,rw"/"rw,w")	Shaked Flur

2017-08-15	riscv: store the decoded branch immediate in the ast type -- this simplifies ↵	Robert Norton
	translation to and from herdtools ast.
2017-08-15	riscv: fix word/half backwards in load.	Robert Norton

2017-08-15	riscv: limit stores to only relevant bytes.	Robert Norton

2017-08-14	add risc-v fence instruction as re-using MIPS sync for now. Also place ↵	Robert Norton
	holders for FENCE.I and ECALL.
2017-08-11	further riscv rmem integration.	Robert Norton

2017-08-08	work on integrating risc-v model with rmem (incomplete).	Robert Norton