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instruction exception behaviour but sequential model does (for test suite).
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sail_impl_base, add sail_impl_base.outcome, add interp_inter_imp auxiliary functions, make prompt use sail_impl_base.outcome
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byte of value for capability writes. Still need TAGw for now but should kill eventually.
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function. There is a plan to replace this syntax with something more understandable. Should make no functional difference using sequential interpretor but will need to do some work on exception functions when integrating with ppcmem so that it know register writes are exceptional etc.
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boot time by reducing TLB misses but an apparent reduction in IPS counteracts this. Makes use of foreach and return to implement tlbSearch.
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accesses, for compatibility with clang.
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writes this register also needs software irq, which isn't implemented, so effectively this was untested although it happens quite early in kernel boot.
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kcc.base is non-zero.
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no functional change.
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want indexing of pfn to be reset to 23..0). Kathy to investigate why this was not caught by type checker.
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halt instructions decode statements are a special case of mtc0 so clauses must appear first.
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in comments. No functional change.
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Interp: trying to add some debugging to isolate bug
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to non-existent mips.sail in top level README.
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-- this could be varied but useful for compatibility with BERI test suite.
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during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set.
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