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now write registers hence call SignalException instead of returning option<err> .
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shuffling function names and adding a hook in ERET.
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implementation for now and exceptions not properly handled.
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loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
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non-capability writes on cheri.
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writes atomic)
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Note to self: consider removing this cast after fixing overload resolution
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preparation for adding cheri support in separate files.
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Improve printing for asl to sail readability;
Add -o option for selecting the name of file generation;
Add additional initial check module for turning generated ast nodes into ready-to-type-check ast nodes
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overloading of '^^'
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exception as per ISA.
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properly implemented as this allows tests to fail gracefully rather than crashing.
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quot and mod. mod still not quite doing what we want in signed case.
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they were, allowing us to pass another test.
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remove temporary hack in TranslateAddr.
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missing psuedo-registers in run_with_elf.
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correct state on exception. branchPending does not work because it is cleared before executing the branch delay.
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work (NB hack in TranslateAddress until interpreter translates instuction fetches)
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manual so emulate unsigned comparisons by prepending a zero bit, as in mips spec.
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but test still does not pass, apparently because sail is doing signed comparison for <
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used by ml to translate fetch address.
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of word to store (probably a bug that it does not complain at runtime).
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config registers in mfc0.
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spec. as the overflow flag provided by +_s builtin doesn't seem to do what we want.
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but this is not the fix...
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