summaryrefslogtreecommitdiff
path: root/mips
AgeCommit message (Collapse)Author
2016-06-28Munge exception destination PC so we hit the correct address even when ↵Robert Norton
kcc.base is non-zero.
2016-06-27Don't blow up when test suite writes to K0 field of Config0 register.Robert Norton
2016-06-07remove workarounds for sail unable to read fields during PC fetch. Should be ↵Robert Norton
no functional change.
2016-06-07Fix issue in accessing fields and slices of registers during translate addressKathy Gray
2016-06-06Add explicit type cast required because of the way sail does slicing (we ↵Robert Norton
want indexing of pfn to be reset to 23..0). Kathy to investigate why this was not caught by type checker.
2016-06-06revert accidental functional change introduced when formatting -- simulator ↵Robert Norton
halt instructions decode statements are a special case of mtc0 so clauses must appear first.
2016-06-03Improve formatting of latex export of mips spec: wrap lines, remove dollars ↵Robert Norton
in comments. No functional change.
2016-06-03Merge branch 'master' of bitbucket.org:Peter_Sewell/l2Peter Sewell
2016-06-03plumbing to make a pdf version of MIPS Sail spec, using LaTeX lstlistingsPeter Sewell
2016-06-03Mips file: removed some unnecessary parenthesisKathy Gray
Interp: trying to add some debugging to isolate bug
2016-06-03Reduce fill width of header to align closing comments nicely.Robert Norton
2016-06-02Get widening right now that it mattersKathy Gray
2016-06-02Apply headache to mips/cheri model.Robert Norton
2016-06-01Tweak wording of mips README.Robert Norton
2016-05-31delete obsolete Makefile (src/Makefile currently hanldes mips build).Robert Norton
2016-05-31Add README in mips directory describing file breakdown and remove reference ↵Robert Norton
to non-existent mips.sail in top level README.
2016-05-25add support for capability load/store bits in TLBRobert Norton
2016-05-24restrict virtual and physical address sizes to 40 and 36 bits respectively ↵Robert Norton
-- this could be varied but useful for compatibility with BERI test suite.
2016-05-19workaround unable to read fields in PC translation bug.Robert Norton
2016-05-19correctly report TLB size and type in config reg.Robert Norton
2016-05-18Make TLB address error exception save BadVAddr.Robert Norton
2016-05-18Implement 8-entry software-managed TLB.Robert Norton
2016-05-13implement config registers.Robert Norton
2016-05-13do something a bit more interesting with WAIT.Robert Norton
2016-05-13fixes to make counter interrupt work: don't attempt to read register fields ↵Robert Norton
during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set.
2016-05-13don't write 33-bit value to hwrena (suprised that this type checked).Robert Norton
2016-05-12allow writing hwrena 29 (UserLocal)Robert Norton
2016-05-12Implement count/compare registers for timer interrupts and rdhwr instruction.Robert Norton
2016-05-12update/add some commentsRobert Norton
2016-05-12remove redundant wrapper function 'TranslateOrExit' and rename uses.Robert Norton
2016-05-12Enforce kernel only access to kernel address space. Doesn't really make any ↵Robert Norton
difference as without TLB we cannot run any non-kernel mode code anyway.
2016-05-10Clear LLbit on ERET regardless of ERL value.Robert Norton
2016-05-10Implement mfc0/mtc0 ErrorEPC.Robert Norton
2016-05-10calculate signed modulus using quot as ocaml and mips disagree about what ↵Robert Norton
the result should be (specifically for x mod y, x<0 & y<0).
2016-05-09explicitly give result value for slti to workaround probable sail bug ↵Robert Norton
producing '?'
2016-05-09work around problem with <_s using signedRobert Norton
2016-05-04check for PC alignment on instruction fetch.Robert Norton
2016-05-03fix cheri and mips sail following change to type of TranslateAddress -- can ↵Robert Norton
now write registers hence call SignalException instead of returning option<err> .
2016-04-29use the correct exception vector for ccall/creturn.Robert Norton
2016-04-28implement (hopefully) correct exception behaviour wrt PCC/EPCC. Required ↵Robert Norton
shuffling function names and adding a hook in ERET.
2016-04-27mips: fix error caused by TranslateAddress having wrong name.Robert Norton
2016-04-27cheri: add translation and bounds checking of PC via PCC. Slightly clunky ↵Robert Norton
implementation for now and exceptions not properly handled.
2016-04-22Add address calculation wrapper to constrain and translate standard mips ↵Robert Norton
loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
2016-04-21Introduce wrapper function around MEMw* so that we can clear tags on ↵Robert Norton
non-capability writes on cheri.
2016-04-13add tagr and tagw in mips_extras (will need to change these to make tag ↵Robert Norton
writes atomic)
2016-04-13Put in a cast into sltiKathy Gray
Note to self: consider removing this cast after fixing overload resolution
2016-03-07Split mips.sail into three file and make use of the new -o option in ↵Robert Norton
preparation for adding cheri support in separate files.
2016-02-23Several fixesKathy Gray
Improve printing for asl to sail readability; Add -o option for selecting the name of file generation; Add additional initial check module for turning generated ast nodes into ready-to-type-check ast nodes
2016-02-11mips.sail: add cast to bit to work around type error recently introduced by ↵Robert Norton
overloading of '^^'
2016-02-10mips.sail: make unimplemented/non-existent throw a reserved instruction ↵Robert Norton
exception as per ISA.