| Age | Commit message (Collapse) | Author |
|---|
|
boot time by reducing TLB misses but an apparent reduction in IPS counteracts this. Makes use of foreach and return to implement tlbSearch.
|
|
accesses, for compatibility with clang.
|
|
|
|
writes this register also needs software irq, which isn't implemented, so effectively this was untested although it happens quite early in kernel boot.
|
|
|
|
kcc.base is non-zero.
|
|
|
|
no functional change.
|
|
|
|
want indexing of pfn to be reset to 23..0). Kathy to investigate why this was not caught by type checker.
|
|
halt instructions decode statements are a special case of mtc0 so clauses must appear first.
|
|
in comments. No functional change.
|
|
|
|
|
|
Interp: trying to add some debugging to isolate bug
|
|
|
|
|
|
|
|
|
|
|
|
to non-existent mips.sail in top level README.
|
|
|
|
-- this could be varied but useful for compatibility with BERI test suite.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set.
|
|
|
|
|
|
|
|
|
|
|
|
difference as without TLB we cannot run any non-kernel mode code anyway.
|
|
|
|
|
|
the result should be (specifically for x mod y, x<0 & y<0).
|
|
producing '?'
|
|
|
|
|
|
now write registers hence call SignalException instead of returning option<err> .
|
|
|
|
shuffling function names and adding a hook in ERET.
|
|
|
|
implementation for now and exceptions not properly handled.
|
|
loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
|
|
non-capability writes on cheri.
|
|
writes atomic)
|
