sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2018-09-21	Remove cheri and mips specs -- they now have their own repository.	Robert Norton

2018-07-03	cheri: refine lwl/lwr cap length checks to be exact. They were previously a ↵	Robert Norton
	bit loose, but conservative.
2018-05-17	changes to for testing FreeBSD boot on MIPS: allowing loading raw file in ↵	Robert Norton
	ocaml main so that we can have simboot + kernel. Support UART output only.
2018-03-08	rename mips_new_tc to mips	Robert Norton

2018-03-08	Remove files in mips directory prior to copying in files from mips_new_tc. ↵	Robert Norton
	Hopefully thiis will help git to spot the rename and hence preserve history.
2017-04-27	reverse endianness of data when writing UART. Altera jtag uart is ↵	Robert Norton
	little-endian and this change allows it to work when writing using store word (as done by FreeBSD driver) or sb (as done by cheri helloworld program).
2017-04-25	Add support for uart terminal. Also add read_bit_reg function for faster and ↵	Robert Norton
	neater access to registers of single bit.
2017-04-03	Rename TranslateAddress to TranslatePC and remove the accessType argument -- ↵	Robert Norton
	it is only ever used for translating the PC.
2017-03-29	change reqiured to work with little endian interpreter.	Robert Norton

2017-02-03	fix headers	Peter Sewell

2016-09-14	Switch mips/cheri over to using memory ea/val for writes. Tag is now first ↵	Robert Norton
	byte of value for capability writes. Still need TAGw for now but should kill eventually.
2016-07-28	Banish exit from the mips/cheri sail except at end of SignalException ↵	Robert Norton
	function. There is a plan to replace this syntax with something more understandable. Should make no functional difference using sequential interpretor but will need to do some work on exception functions when integrating with ppcmem so that it know register writes are exceptional etc.
2016-07-26	Add minimal support for emulated Altera JTAG UART.	Robert Norton

2016-06-28	Munge exception destination PC so we hit the correct address even when ↵	Robert Norton
	kcc.base is non-zero.
2016-06-03	Improve formatting of latex export of mips spec: wrap lines, remove dollars ↵	Robert Norton
	in comments. No functional change.
2016-06-03	Reduce fill width of header to align closing comments nicely.	Robert Norton

2016-06-02	Apply headache to mips/cheri model.	Robert Norton

2016-05-13	implement config registers.	Robert Norton

2016-05-12	Implement count/compare registers for timer interrupts and rdhwr instruction.	Robert Norton

2016-05-04	check for PC alignment on instruction fetch.	Robert Norton

2016-05-03	fix cheri and mips sail following change to type of TranslateAddress -- can ↵	Robert Norton
	now write registers hence call SignalException instead of returning option<err> .
2016-04-28	implement (hopefully) correct exception behaviour wrt PCC/EPCC. Required ↵	Robert Norton
	shuffling function names and adding a hook in ERET.
2016-04-27	mips: fix error caused by TranslateAddress having wrong name.	Robert Norton

2016-04-27	cheri: add translation and bounds checking of PC via PCC. Slightly clunky ↵	Robert Norton
	implementation for now and exceptions not properly handled.
2016-04-22	Add address calculation wrapper to constrain and translate standard mips ↵	Robert Norton
	loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
2016-04-21	Introduce wrapper function around MEMw* so that we can clear tags on ↵	Robert Norton
	non-capability writes on cheri.