| Age | Commit message (Collapse) | Author |
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will be reflected in short hand type syntax, inc is still the default if undeclared
So:
default order dec
register bit[32] t (* Declares t as a decreasing vector, starting at 31 on the left and decreasing to 0 *)
default order inc
register bit[32] o (* Declares o as an increasing vector, starting at 0 on the left and increasing to 31 *)
It is presently possible to change the default mid-file; this is almost certainly bad and I will turn it into an error soon.
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and the like.
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Also begining to add support for nondeterministic blocks and cleaning up some of the Many warnings on pattern matches
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Reduce the number of implicit coercions we're doing, expanding overloading and fixing up types of functions.
Warning: test_power does not run as not all overloaded funcitons are implemented
Warning: vector concatenation does not pretty print to sail source yet
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functions for connecting the interpreter to a memory model)
Also adding default values to index vectors for supporting sparse vectors/maps
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assigned to in assignments.
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ast, and extending the interpreter to expect annotations.
Annotations and locations are still not used by the interpreter.
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Could not at this time return lists to [| |] from [|| ||] as the parser cannot distinguish a cast with enum’s syntactic sugar from the start of a parenthesised list (i.e. ( [|3|] ) And there are still conflicts with moving enums to [3], so those changes can’t be pushed in with current parser technology.
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First pass parser to identify type names is in progress (current test files fail, will correct once pre-parser is in place)
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Added val extern specification to language, parser, printer, and interpreter
Added various def level type system support, expressions type system in place Except for assignment
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only match simple patterns (until type information is available).
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actually parses
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