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AgeCommit message (Expand)Author
2018-12-22Added RISC-V fence.tsoShaked Flur
2018-07-10Tweak to anonymous copyright header.Robert Norton
2018-07-10further anonymisation work.Robert Norton
2018-07-09Changes for anonymisation. Ensure headers are in correct format. Remove some ...Robert Norton
2018-05-09Add targets for counting lines in mips, cheri and riscv. Can use either slocc...Robert Norton
2018-02-22wipRobert Norton
2018-02-17Merge master branch into sail2 for OCaml 4.06 compatibilityThomas Bauereiss
2018-02-08Some perl for automating some of sail->sail2 porting. Does not even attempt t...Robert Norton
2018-02-08replaced NIA_LR/CTR/register with NIA_indirect;Shaked Flur
2017-12-04added the Power modelShaked Flur
2017-12-04renamed hgen to genShaked Flur
2017-11-01added RISC-V "fence r,r"Shaked Flur
2017-09-20add support for x86 lock prefix (also remove unused Read/Write_tag kind in et...Robert Norton
2017-09-15x86: implement regfp analysis function (no control flow yet)Robert Norton
2017-09-03added RISC-V strong-acquire/releaseShaked Flur
2017-08-31added RISC-V AMOsShaked Flur
2017-08-22added RISC-V "fence w,w" and "fence.i";Shaked Flur
2017-08-19RISC-V store-releaseShaked Flur
2017-08-17added RISC-V load-acquireShaked Flur
2017-04-18added transactional memory supportShaked Flur
2017-02-03fix headersPeter Sewell
2017-02-03licensingPeter Sewell
2016-11-30add new barrier kind for MIPS (only one for now).Robert Norton
2016-11-07factor out regfp analysis types into etc/regfp.sailChristopher Pulte
2016-06-03added ARMv8Shaked Flur
2016-06-03Reduce fill width of header to align closing comments nicely.Robert Norton
2016-06-02Add rule in Makefile that uses headache to add copyright header to mips/cheri...Robert Norton
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