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AgeCommit message (Expand)Author
2016-05-25add support for capability load/store bits in TLBRobert Norton
2016-05-16Implement the simulator dump cap registers instruction as a NOP since we dump...Robert Norton
2016-05-13implement config registers.Robert Norton
2016-05-12Implement count/compare registers for timer interrupts and rdhwr instruction.Robert Norton
2016-05-12rename ephemeral/non_ephemeral to global/local in accordance with current usage.Robert Norton
2016-05-12remove redundant wrapper function 'TranslateOrExit' and rename uses.Robert Norton
2016-05-11Fix XXX missing register accessible check in ClearRegs, also only do CP2Usabl...Robert Norton
2016-05-04fix incorrect exception code used on clc alignment check.Robert Norton
2016-05-04check for PC alignment on instruction fetch.Robert Norton
2016-05-03cheri: check value of co-processor enable bit before all cheri instructions.Robert Norton
2016-05-03fix cheri and mips sail following change to type of TranslateAddress -- can n...Robert Norton
2016-05-03immediate offset of load/store via capability is scaled by word size (ISA cha...Robert Norton
2016-04-29implement cgetpccsetoffset (new instruction)Robert Norton
2016-04-29new encoding for cgetpcc (ISA change).Robert Norton
2016-04-29implement 'big immediates' for CSC and CLC (ISA change).Robert Norton
2016-04-29use the correct exception vector for ccall/creturn.Robert Norton
2016-04-28implement (hopefully) correct exception behaviour wrt PCC/EPCC. Required shuf...Robert Norton
2016-04-27cheri: add translation and bounds checking of PC via PCC. Slightly clunky imp...Robert Norton
2016-04-22Add address calculation wrapper to constrain and translate standard mips load...Robert Norton
2016-04-21Introduce wrapper function around MEMw* so that we can clear tags on non-capa...Robert Norton
2016-04-19cheri: be sure to use unsigned comparison in CUnsealRobert Norton
2016-04-19use unsigned for register offset and signed for immediate offset when computi...Robert Norton
2016-04-18cheri: use signed() rather than casting to int as advised by kathy. This has ...Robert Norton
2016-04-18cheri: explicitly specify vector for comparison in cincoffset to work around ...Robert Norton
2016-04-18cheri: swap use of MEMr_tagged and MEMr_tagged_reserved in CLC which were swa...Robert Norton
2016-04-18cheri: fix encoding of CSCC which was short one bit (kathy investigating why ...Robert Norton
2016-04-18cheri: add support for ll/sc of data via capability instructions.Robert Norton
2016-04-18cheri: fix inverted tag check for cptrcmp.Robert Norton
2016-04-15signed comparison between nats is not sensible. cast to bit vector instead.Robert Norton
2016-04-15cseal: perform arithmetic using nats to avoid signed comparison. Should maybe...Robert Norton
2016-04-15cheri: explicitly zero extend regno when writing to cap cause because implici...Robert Norton
2016-04-14cheri: implement ll/sc of capabilities using placeholder functions to emulate...Robert Norton
2016-04-14cheri: use correct destination register for loads via capability.Robert Norton
2016-04-13Further CHERI implementation. Rename cursor to offset in line with ISA. Imple...Robert Norton
2016-03-09cheri sail: introduce functions for casting from cap. register to cap. struct...Robert Norton
2016-03-08add beginnings of cheri sail for kathy to do some debugging.Robert Norton
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