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now write registers hence call SignalException instead of returning option<err> .
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change).
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shuffling function names and adding a hook in ERET.
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implementation for now and exceptions not properly handled.
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loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
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non-capability writes on cheri.
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computing capability relative address. This is a little counter-intuitive but seems to be what is written in the spec. and passes more tests. Will consult with mroe to check logic here and possibly extract into a function for clarity.
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the advantage of actually doing what I want.
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unexpected sail behaviour with implicit cast form literal 0.
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swapped.
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this didn't cause an error).
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maybe do this in readCapReg
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implicit cast does not work as expected (appends zeros at bottom).
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emulate atomic tag access.
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Implement reserved cap. perms (bits 8 and 9) because a test uses them even though they have no defined meaning (historically they did I think).
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struct and use cap structs for easier syntax to ensure atomic writes of cap regs.
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