| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-10-26 | fixed release acquire semantics of AMOs | Shaked Flur | |
| 2017-10-24 | fix default cap value on cheri128 following previous changes -- E stored in ↵ | Robert Norton | |
| registers is no longer xored with 48 so need to initialise it. Also use E and T values used by CHERI hw and adjust decoding functions appropriately. Fix shift functions for ocaml shallow embedding which failed to handle shifts greater than vector length. | |||
| 2017-10-23 | cheri: Null capability should have maximum length, because in cheri128 we ↵ | Robert Norton | |
| want all offsets to be representable. To maintain all-zeros as the in-memory representation of the null capability we xor memory bits with null capability when loading and storing. | |||
| 2017-10-16 | add CTestSubset instruction. | Robert Norton | |
| 2017-10-16 | add missing new encodings for CJR and CJALR. | Robert Norton | |
| 2017-10-16 | implement CMove as an alias for cmovz with zero register. | Robert Norton | |
| 2017-10-16 | add support for CIncOffsetImmediate and CSetBoundsImmediate. | Robert Norton | |
| 2017-10-16 | add support for capability branch null instructions. | Robert Norton | |
| 2017-10-13 | Add support for new cheri instruction encodings. The order of pattern ↵ | Robert Norton | |
| matching is now significant because register no. fields are re-used as additional function codes in operations with fewer operands so I pulled out all decode clauses to the beginning of file for easier rearranging. Old encodings can co-exist with new encodings as the only overlap is for recently added instructions which already use the new scheme. Eventually the old encodings will go away, however, and the opcode space may be reclaimed." | |||
| 2017-10-12 | Work around warning in ocaml shallow embedding of mips caused by buggy code ↵ | Robert Norton | |
| generation for dubious casting enumeration to int. | |||
| 2017-10-09 | add translations for missing read/write kinds. | Robert Norton | |
| 2017-10-09 | add translation of IK_mem_rmw interp_inter_imp. TODO: could we get rid of ↵ | Robert Norton | |
| this and use shallow embedding conversion? | |||
| 2017-10-09 | X86: Fix bug in register footprint caused by imperative variable update with ↵ | Robert Norton | |
| wrong variable name (iK vs. ik). Spotted via compare_analyses. | |||
| 2017-10-06 | move nias_of_instruction into RMEM so that it can use shallow embedding ast ↵ | Robert Norton | |
| and not obsolete interp_interface one. | |||
| 2017-10-02 | cheri: fix swapped cmovz and cmovn. | Robert Norton | |
| 2017-10-01 | fixed JALR: do the register write first to allow po-later reads | Shaked Flur | |
| 2017-09-29 | fix those build errors | Christopher Pulte | |
| 2017-09-29 | Merge branch 'master' of https://bitbucket.org/Peter_Sewell/sail | Christopher Pulte | |
| 2017-09-29 | fix deep_shallow_convert, stop using interp_interface.instruction for most ↵ | Christopher Pulte | |
| things, SF and CP bugfixing | |||
| 2017-09-29 | x86: add bit set, reset, complement operations. | Robert Norton | |
| 2017-09-27 | fixed the RISC-V Makefile | Shaked Flur | |
| 2017-09-27 | split RISC-V to two Sail files to make it more readable | Shaked Flur | |
| 2017-09-27 | oops | Shaked Flur | |
| 2017-09-26 | fixes | Christopher Pulte | |
| 2017-09-26 | RISC-V: check alignment of atomic memory accesses (and escape when misaligned) | Shaked Flur | |
| 2017-09-25 | x86: always perform write for cmpxchg by writing back original value if ↵ | Robert Norton | |
| comparison fails. This is specified in manual and also helps RMEM with locked writes. | |||
| 2017-09-22 | x86: implement get_ea_address function. | Robert Norton | |
| 2017-09-22 | x86: remove unnecessary? read modify write of registers. | Robert Norton | |
| 2017-09-22 | fix typo where Sz16 write to register was only writing 8 bits. | Robert Norton | |
| 2017-09-21 | wib | Shaked Flur | |
| 2017-09-21 | added a comment to the x86 lock'd read and write | Shaked Flur | |
| 2017-09-20 | add support for x86 lock prefix (also remove unused Read/Write_tag kind in ↵ | Robert Norton | |
| etc/regfp.sail. | |||
| 2017-09-19 | fix | Christopher Pulte | |
| 2017-09-19 | According to Shaked NIAFP_register can be used to indicate that we don't ↵ | Robert Norton | |
| know the possible destination of an instruction for memory indirect jumps (the register name is not used). | |||
| 2017-09-18 | add regfp for x86 control flow instrucitons. Need more support for memory ↵ | Robert Norton | |
| indirect jumps. | |||
| 2017-09-15 | x86: implement regfp analysis function (no control flow yet) | Robert Norton | |
| 2017-09-15 | reinstate deep/shallow conversion | Christopher Pulte | |
| 2017-09-13 | add HLT instruction for RMEM integration. | Robert Norton | |
| 2017-09-11 | added xml pp | Shaked Flur | |
| 2017-09-07 | add MFENCE | Robert Norton | |
| 2017-09-06 | power is builtin in old tc so use it. | Robert Norton | |
| 2017-09-03 | added RISC-V strong-acquire/release | Shaked Flur | |
| 2017-09-02 | fix for parsing diy generated tests | Shaked Flur | |
| 2017-09-02 | check the status of SC before doing the memory write | Shaked Flur | |
| 2017-08-31 | add EnumerationType type class: if a type is a member you get Ord membership ↵ | Christopher Pulte | |
| and Set membership for free | |||
| 2017-08-31 | added RISC-V AMOs | Shaked Flur | |
| 2017-08-30 | typeclass instance Ord(opcode) | Christopher Pulte | |
| 2017-08-24 | typo | Shaked Flur | |
| 2017-08-24 | typo | Shaked Flur | |
| 2017-08-24 | added barrier-kind for x86 MFENCE; | Shaked Flur | |
| fixed some compare functions; | |||
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index : sail | |
| Formal specification language for ISAs |
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