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2018-07-24Now builds mips spec again.Alasdair
Some more testing needed to make sure it runs FreeBSD properly and CHERI before merging
2018-07-05Passes all tests and now builds mips and cheri againAlasdair
2018-06-29Try to fix some tricky C compilation bugs, break everything insteadAlasdair Armstrong
2018-06-28RTS: Fix utterly broken command line parsingAlastair Reid
2018-06-28RTS: Add --verbosity flag to C modelAlastair Reid
This is interpreted as a set of bits that control various bits of output. Bit 0 is print the PC on every cycle. (It would probably be useful to standardise a few of these flags across all models. Other candidates are accesses to physical memory, throwing SAIL exceptions, current privilege level, ...)
2018-06-28Add tagged memory to C rts to cheri can be compiled to CAlasdair Armstrong
2018-06-28Fix warning in rts.cRobert Norton
2018-06-28further changes to support rmemJon French
2018-06-28Fix build of Aarch64_mono.thyThomas Bauereiss
2018-06-28Add patches to (monomorphised) AArch64Thomas Bauereiss
- Initialise fault typ field of result record to avoid an unitialised read that can lead to an early return with a fault. This looks like a bug in the ASL specification (the ASL tests probably assume that this field is initialised with Fault_None). - In ZeroExtend_slice_append (one of the helper functions for monomorphisation rewrites), use extzv instead of ZeroExtend. It allows not only extension, but also truncation, and in AArch64_TranslationTableWalk the ZeroExtend_slice_append function is used to construct a 52 bit physical address using parts of the 64 bit input address. - Use the Lem library function for reversing endianness
2018-06-28Add option to build ocaml with bisect_ppx coverage support. Add cheri ↵Robert Norton
targets using this.
2018-06-28RTS: Add missing #includeAlastair Reid
Every Unix is subtly different.
2018-06-28Deduplicate arguments for different constructors in undefined fnsBrian Campbell
Makes the generated undefined functions smaller, easier to read, and avoids excessive memory usage in Coq (e.g., for large AST types).
2018-06-28Main: exit if you hit IMPDEF behaviourAlastair Reid
If you don't exit immediately, the test will probably just jump off into the weeds and stay there until it times out. So better to exit early. But note that this is not all IMPDEF behaviour. Most IMPDEF such as 'Are SHA3 crypto instructions available?' are already being handled and either TRUE or FALSE is being returned. So this is just for the stuff where we don't have a good answer at all.
2018-06-27RTS/Main: tweaking cycle counter handlingAlastair Reid
2018-06-27Actually fix real literals, and add a test for various propertiesAlasdair Armstrong
2018-06-27Fix reading reals from strings in C libAlasdair Armstrong
2018-06-27libsail: optimise real_powerAlastair Reid
The Arm spec uses the value 2.0^1000000 to represent infinity so it is worth making real_power take logarithmic time.
2018-06-27Add a mips_c_gcov target that builds mips_c model with coverage reporting.Robert Norton
2018-06-27Add a new function cycle_limit_reached that returns bool, allowing for ↵Robert Norton
graceful exit on reaching cycle limit. This aids coverage and valgrind instrumentation.
2018-06-27Fix real implementation in C to use GMP rationalsAlasdair Armstrong
Implement square root function for rationals up to an arbitrary precision, currently 30 decimal places. May need to increase this for ARM tests.
2018-06-27Main: refactor fetch_and_executeAlastair Reid
No functional change
2018-06-27RTS: __SetConfig support is off by defaultAlastair Reid
Use -DHAVE_SETCONFIG to enable __SetConfig support
2018-06-27RTS: Add support for __ListConfigAlastair Reid
2018-06-27RTS: Delete __SetConfig stub functionAlastair Reid
This is now directly supported from SAIL so we can call the SAIL __SetConfig function instead.
2018-06-27Make sure __SetConfig gets included in generated codeAlasdair Armstrong
2018-06-27Main: fix PC advance after HINT and other EndOfInstructionAlastair Reid
2018-06-26Fix duplicate riscv mem-ea, spotted by Jon French.Prashanth Mundkur
2018-06-26Add configuration registers so __SetConfig ASL can be translatedAlasdair Armstrong
Registers can now be marked as configuration registers, for example: register configuration CFG_RVBAR = 0x1300000 They work like ordinary registers except they can only be set by functions with the 'configuration' effect and have no effect when read. They also have an initialiser, like a let-binding. Internally there is a new reg_dec constructor DEC_config. They are intended to represent configuration parameters for the model, which can change between runs, but don't change during execution. Currently they'll only work when compiled to C. Internally registers can now have custom effects for reads and writes rather than just rreg and wreg, so the type signatures of Env.add_register and Env.get_register have changed, as well as the Register lvar, so in the type checker we now write: Env.add_register id read_effect write_effect typ rather than Env.add_register id typ For the corresponding change to ASL parser there's a function is_config in asl_to_sail.ml which controls what becomes a configuration register for ARM. Some things we have to keep as let-bindings because Sail can't handle them changing at runtime - e.g. the length of vectors in other top-level definitions. Luckily __SetConfig doesn't (yet) try to change those options. Together these changes allow us to translate the ASL __SetConfig function, which means we should get command-line option compatibility with ArchEx for running the ARM conformance tests.
2018-06-26Main: further refinement of execution cycleAlastair Reid
Mostly improving error messages
2018-06-26Prelude: as received from AlasdairAlastair Reid
2018-06-26Main: attempt to capture AArch64 execution cycleAlastair Reid
2018-06-26mips: fix duplication of cycle_count call that arose due to git merge.Robert Norton
2018-06-26mips: comment out printing of EXCEPTION on every ISA exception.Robert Norton
2018-06-26turn on warnings when compiling mips c then dial back ones that are ↵Robert Norton
triggered by generated code (probably false positives). Fix some warnings in rts.c
2018-06-26RTS: implement sleep primitivesAlastair Reid
Note that an alternative implementation choice is just to implement them as SAIL functions manipulating a global variable. Not sure which is better.
2018-06-26RTS: stub support for -C command line optionAlastair Reid
2018-06-26ELF: Restore error messages in ELF readerAlastair Reid
2018-06-26In guarded pattern rewriting, irrefutable patterns subsume wildcardsBrian Campbell
Necessary to prevent redundant clauses that Coq will reject (There's still a problem if you use a variable rather than a wildcard, see the test)
2018-06-26In elf_loader don't attempt to convert paddr to int64 because on MIPS it is ↵Robert Norton
quite likely to exceed representable range of signed 64-bit integer (e.g. address starting 0x9...). Also make clear which values are displayed in hex vs. decimal.
2018-06-25Add a riscv platform parameter to control trapping to M-mode on misaligned ↵Prashanth Mundkur
access, and a cli option to control it.
2018-06-25Increment the riscv trace step counter only when instructions are executed.Prashanth Mundkur
2018-06-25Hook in the missed misa legalizer.Prashanth Mundkur
2018-06-25Fix riscv interrupt pending check to handle implicit enabling at lower ↵Prashanth Mundkur
privileges. Also fix timer threshold comparison to be <= instead of <.
2018-06-25Make sstatus.UXL legalization match spike for now. Leave a fixme to make ↵Prashanth Mundkur
this a platform setting.
2018-06-25Fix a missed fixme for the sstatus view of mstatus.Prashanth Mundkur
2018-06-25Fix tracecmp for spike's recursive calls for sie/sip/sstatus csr writes.Prashanth Mundkur
2018-06-25Check for variables in disjointness checkThomas Bauereiss
2018-06-25Support bitlist representation in Sail2_stringThomas Bauereiss
2018-06-25Fix a bug in pattern guard rewritingThomas Bauereiss
Remember and use fallthrough clauses instead of dropping them when the last clause in a group has a guard