| Age | Commit message (Collapse) | Author |
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Note: this support is rather mips centric at the moment
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work (NB hack in TranslateAddress until interpreter translates instuction fetches)
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manual so emulate unsigned comparisons by prepending a zero bit, as in mips spec.
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but test still does not pass, apparently because sail is doing signed comparison for <
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used by ml to translate fetch address.
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of word to store (probably a bug that it does not complain at runtime).
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interpreter interface
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instructions run
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Could later add the ability to run to a particular instruction form (like we had in ppcmem2) or address
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config registers in mfc0.
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Make quiet mode for sequential interpreter not print
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constraints and thus causing inequality checks to be missed
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them sensibly at last
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execution.
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as increasing, and updated ranges accordingly, and mistakenly were using the wrong range values for register slicing.
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distinction between prog_mem and data_mem at least for now as data_mem was not being populated correctly (wrong elf flags?).
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spec. as the overflow flag provided by +_s builtin doesn't seem to do what we want.
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but this is not the fix...
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