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during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set.
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difference as without TLB we cannot run any non-kernel mode code anyway.
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CP2Usable check if for cap. regsets.
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the result should be (specifically for x mod y, x<0 & y<0).
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producing '?'
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requires some clean up (currently one huge function).
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decode/translate_address/exhaustive. (Was previously correct for full register reads)
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Attempt to get correct behaviour wrt nextpC on instruction fetch exception (prob. still wrong).
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fix bug in interp_to_value_helper
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now write registers hence call SignalException instead of returning option<err> .
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(although decode isn't pushed through yet).
Note: this will break all builds
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change).
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shuffling function names and adding a hook in ERET.
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then reconvert delayedPC
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implementation for now and exceptions not properly handled.
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This is not yet connected to any model and not yet tested.
Also, reduce the number of parentheses needed by the parser. Namely, register declarations should no longer need parens around the types and let expressions should need fewer instances of parens around the expression (i.e. let a = exp ).
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loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
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non-capability writes on cheri.
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undefined unless we actually access memory which is uninitialised.
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assignment expression
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