sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-11-13	add linenoise to .merlin	Jon French
2018-11-01	Merge branch 'sail2' into rmem_interpreter	Jon French
2018-11-01	Interpreter: last couple of builtins to get RISC-V working	Jon French
2018-10-29	Merge pull request #21 from rems-project/riscv_c_platform	Alasdair Armstrong
2018-10-24	Add constraint synonyms	Alasdair Armstrong
2018-10-24	Interpreter, RISC-V: move memory actions to parts of the interpreter response...	Jon French
2018-10-24	RISC-V: add Sail implementations of just enough platform for interpreter to work	Jon French
2018-10-24	add a couple things to gitignore	Jon French
2018-10-24	Interpreter: add handling of undefs and sizeofs, and initialize registers to ...	Jon French
2018-10-24	Interpreter: improve error handling/messages	Jon French
2018-10-24	src/Makefile: add isail.byte target for debugging interpreter	Jon French
2018-10-24	Interpreter: don't silently use OCaml externs, only interpreter externs	Jon French
2018-10-23	RISC-V: switch c tests to use the C platform simulator; update .gitignore.	Prashanth Mundkur
2018-10-23	RISC-V: use stderr for terminal output in OCaml backend.	Prashanth Mundkur
2018-10-23	RISC-V: separate jalr execute clause for seq model and rmem.	Prashanth Mundkur
2018-10-23	RISC-V: Initial splitting of instructions across multiple files.	Prashanth Mundkur
2018-10-23	RISC-V: Allow the C platform to get the DTB from a file, so that OS boot is p...	Prashanth Mundkur
2018-10-23	RISC-V: add cli option to dump the platform device-tree.	Prashanth Mundkur
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur
2018-10-23	RISC-V: various fixes	Prashanth Mundkur
2018-10-23	RISC-V: fix: sstatus.SD depends on .XS and .FS.	Prashanth Mundkur
2018-10-23	RISC-V: adjust main loop for the non-spike case.	Prashanth Mundkur
2018-10-23	RISC-V: implement terminal output for C platform.	Prashanth Mundkur
2018-10-23	RISC-V: tick the clock in the C platform.	Prashanth Mundkur
2018-10-23	RISC-V: Add device tree blob into rom, currently only when linked against spike.	Prashanth Mundkur
2018-10-23	RISC-V: add default reset vector.	Prashanth Mundkur
2018-10-23	RISC-V: fix up platform bits for lr/sc.	Prashanth Mundkur
2018-10-23	RISC-V: set htif tohost port address using ELF symbol.	Prashanth Mundkur
2018-10-23	RTS: Add elf symbol lookup support.	Prashanth Mundkur
2018-10-23	Fix typo in plat_ram_size	Alasdair Armstrong
2018-10-23	RISC-V: Add some debug logs for within_phys_mem.	Prashanth Mundkur
2018-10-23	RISC-V: Allow Spike linkage to be conditionally enabled.	Prashanth Mundkur
2018-10-23	RISC-V: flush logs at each step.	Prashanth Mundkur
2018-10-23	RISC-V: Flesh out more of the tandem checks in the C platform simulator.	Prashanth Mundkur
2018-10-23	RISC-V: An initial C Sail model linked against Spike for testing.	Prashanth Mundkur
2018-10-23	RTS: allow elf-loader to provide entry info.	Prashanth Mundkur
2018-10-23	RISC-V: Refactor c platform bits.	Prashanth Mundkur
2018-10-22	Coq: use function type more carefully in untupling	Brian Campbell
2018-10-22	Update Coq patch for RISC-V, add string_take to Coq library	Brian Campbell
2018-10-22	Coq: work around constructors with tupled arguments	Brian Campbell
2018-10-22	Fix lem arguments for functions with tuple arguments	Alasdair Armstrong
2018-10-22	Merge branch 'sail2' into rmem_interpreter	Jon French
2018-10-22	Pretty_print_lem.untuple_args_pat: temporary hack to allow functions that act...	Jon French
2018-10-16	Merge branch 'sail2' into rmem_interpreter	Jon French
2018-10-16	add a couple more RISC-V things to gitignore	Jon French
2018-10-16	Re-implement space-related mapping functions in Sail rather than backends	Jon French
2018-10-16	rewrites: remove now-unnecessary temporary string hack from rewrite_defs_pat_...	Jon French
2018-10-15	Update manual snapshot	Alasdair Armstrong
2018-10-15	Ocaml backend: omit function definitions for externs	Jon French
2018-10-15	Add interpreted RISC-V model to test suite	Jon French