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2018-06-08Coq: add destructuring of atom existentials in patternsBrian Campbell
Plus test case, broken builtin name
2018-06-08Coq: track add_typquant changeBrian Campbell
2018-06-08Correct dependencies of bytecode sailBrian Campbell
2018-06-08Coq: existential and constraint solving workBrian Campbell
- add existential unpacking for function arguments - add mechanism for using properties for existentially typed top-level values (useful for the typechecking tests) - support for length_list and In in Coq constraint solving
2018-06-08Coq: some very basic existential supportBrian Campbell
Only single variable in places, only packed at literals and variables, no unpacking
2018-06-08Coq: fix axiom generationBrian Campbell
2018-06-08Coq: ignore some currently unsupported testsBrian Campbell
2018-06-08Coq: update foreach handling, correct field accessesBrian Campbell
2018-06-08Fill in most Coq built-insBrian Campbell
2018-06-08Coq: skip two tests with redundant pattern matchesBrian Campbell
2018-06-08Coq: correct failure on unsupported undefined valuesBrian Campbell
2018-06-08Coq: use record update syntax (only single fields work for now)Brian Campbell
2018-06-08Coq: correct implicitness of type arguments in unionsBrian Campbell
2018-06-08Add missing Coq builtin info to vector_incBrian Campbell
2018-06-08add sail as dependency of mips targets.Robert Norton
2018-06-07Slight refactor to keep platform handling localized to the _platform file.Prashanth Mundkur
2018-06-07Fix width guards on htif accesses.Prashanth Mundkur
2018-06-07Update physical memory and address translation for MMIO.Prashanth Mundkur
- Assume for now that atomic accesses are only to memory regions, to leave their effects unchanged. - The top-level mem_read and mem_write functions for physical memory now have rreg and wreg effects due to MMIO (due to reads/writes to device registers). It would be nice to have a separate construct for non-CPU-register state to avoid polluting the footprint. - Assume for now that page-table walks access physical memory regions only, and not MMIO regions. Leave a fixme note there to address this later, perhaps when PMP/PMA is added.
2018-06-07More definitions for the physical memory map.Prashanth Mundkur
2018-06-07Remove unused file.Prashanth Mundkur
2018-06-07Add terminal output to riscv platform, with incomplete handling of input.Prashanth Mundkur
2018-06-07Fix bug in add_bits optimizationAlasdair Armstrong
2018-06-07Refactor mips main a little to work around apparent bug in c generation. ↵Robert Norton
Generated c Works with no gcc optimisation but fails when optimisation is on, implying undefined behaviour. Probably due to control reaching end of non-void function in exception case.
2018-06-07Use the vector_dec standard library for mips. This means we get all the c ↵Robert Norton
functions ready to go.
2018-06-07add mips_c target.Robert Norton
2018-06-07Rename some functions in vector_dec library file to avoid clashes with ↵Robert Norton
functions in mips spec in prepartion for using this file in mips prelude. Also modify tests that use this header. We should consider prefixing library builtins to avoid name clashes. overload can then be used to provide aliases if desired.
2018-06-07Fixes and additions to c builtins needed to pass mips test suite. bv_ts ↵Robert Norton
should be kept in normal form i.e. a positive mpz_t with no bits higher than len set.
2018-06-07Fix a small bug in monomorphisationThomas Bauereiss
2018-06-07Fix Lem build of RISC-VThomas Bauereiss
2018-06-07Merge pull request #14 from lastland/sail2Alasdair Armstrong
Fix a typo.
2018-06-06Fix a typo.Yao Li
2018-06-07Add a constant folding optimization passAlasdair
2018-06-06Factor utility functions for IR into separate file and struct update ↵Alasdair Armstrong
optimizations. Move the utility functions for graph generation and pretty printing of intermediate representation instructions into a separate file, bytecode_util.ml, by analogy with ast_util.ml. Add an optimization pass that searches for specific patterns of struct updates and removes uncessary copying of the structs involved. With this optimisation pass the time taken for u-boot to run approx 57,000,000 instructions goes down from about 11-12 minutes to 8 minutes (about 120,000 IPS).
2018-06-06Some additional fixes to C backend. Re-enable primitive optimizations.Alasdair Armstrong
Also add an additional -Oz3 flag that uses z3 to optimize some additional types. This is currently very experimental and doesn't fully work yet.
2018-06-06Some work on improving error messagesAlasdair Armstrong
We now store the location where type variables were bound, so we can use this information when printing error messages. Factor type errors out into type_error.ml. This means that Type_check.check is now Type_error.check, as it previously it handled wrapping the type_errors into reporting_basic errors. Type_check.check' has therefore been renamed to Type_check.check.
2018-06-04Add the htif exit command, a top-level function to initialize the riscv ↵Prashanth Mundkur
platform, and document the artificial wreg effect due to using registers for device state.
2018-06-04Uncomment the clint implementation in riscv_platform.Prashanth Mundkur
2018-06-04Update sail C libraryAlasdair Armstrong
2018-06-04Fix an issue with riscv_platform involving flow typingAlasdair Armstrong
- Refactor the flow typing implementation in the type-checker. This should fix an issue involving riscv_platform. Specifically it should now work better when an if statement contains multiple conditions combined with and/or, only some of which imply constraints at the type level. This change also simplifies the implementation of flow typing, and removes some obscure features that were hardly used - specifically, flow typing could modify types, but this was fairly obscure and doesn't seem to affect any of our specifications. More testing is needed to ensure that this change hasn't inadvertantly broken anything, but it does pass all our tests and continue to typecheck arm, riscv and cheri. - Also adds a option for generating faster undefined functions for enum and variant types. Previously I tried to optimise away such functions in the C backend, because they could be slow and cause considerable uneccessary allocation, however this was error prone and it turns out a much simpler solution is to simply make the functions themselves much faster, at the cost of hard-coding certain decisions about what undefined means for these types at compile tile (which is fine for fast emulation). This almost doubles the performance of the generated C code. - Add a wrapper for right shift to avoid UB when shifting by 64 or more places.
2018-06-04Fix bug with function return types in C backendAlasdair Armstrong
2018-06-04Add mips.c target in Makefile. Currently triggers assertion failure in ↵Robert Norton
c_backend. still need to merge changes to prelude.sail.
2018-06-04switch to using a Map data structure for cheri tags in ocaml backend. This ↵Robert Norton
solves a problem where the Hashtbl module was encountering a stack overflow booting CheriBSD. There seems to be little or no performance impact.
2018-06-04cheri: print debug trace info to stderr to keep it separate from uart output.Robert Norton
2018-06-04Re-generate aarch64 spec, fixing an issue with ReplicateAlasdair Armstrong
2018-06-04Use Util.split_on_char in sail_lib.mlAlasdair Armstrong
2018-06-04Merge branch 'arichardson-patch-1' into sail2Robert Norton
2018-06-04add missing semi colon in arichardsons patch.Robert Norton
2018-06-04Merge branch 'patch-1' of https://github.com/arichardson/sail into ↵Robert Norton
arichardson-patch-1
2018-05-31Fix for Jenkins buildAlasdair Armstrong
Looks like Jenkins is still on OCaml 4.02.3. We should probably upgrade to 4.05 at some point.
2018-05-31Fixes to get ARM u-boot working in Sail.Alasdair Armstrong
Also fixes to C backend for compiling MIPS spec to C - Fix an issue with const correctness in internal_vector_update functions generated by C backend - Add builtins for MIPS to sail.h - Fix an issue where reg_deref didn't work when called on pointers to large bitvectors, i.e. vectors containing references to large bitfields as in the MIPS TLB code - Various bug fixes and changes for running U-boot on ARM model, including for interpreter and OCaml compilation. - Fix memory leak issues and incorrect shadowing for foreach loops - Update C header file. Fixes memory leak in memory read/write builtins. - Add aux constructor to ANF representation to hold environment information. - Fix undefined behavior caused by optimisation left shifting uint64_t vectors 64 or more times. Unfortunately there's more issues because the same happens for X >> 64 right shifts. It would make sense for this to be zero, because that would guarantee the property that ((X >> n) >> m) == (X >> (n + m)) but we probably need to do (X >> (n - 1) >> 1) in the optimisation to ensure that we don't cause UB. Shifting by 63 and then by 1 is well-defined, but shifting by 64 in one go isn't according to the C standard. This issue with right-shifts only occurs for zero-length vectors, so it's not a huge deal, but it's still annoying. - Add versions of print_bits and print_int that print to stderr. Follows OCaml convention of print/prerr. Should make things more explicit. Different backends had different ideas about where print should output to, not every backend needs to have this (e.g. theorem prover backends don't need to print) but having both stderr and stdout seperate and clear is useful for executable models (UART needs to be stdout, debug messages should be stderr).