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Attempt to get correct behaviour wrt nextpC on instruction fetch exception (prob. still wrong).
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fix bug in interp_to_value_helper
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now write registers hence call SignalException instead of returning option<err> .
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(although decode isn't pushed through yet).
Note: this will break all builds
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change).
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shuffling function names and adding a hook in ERET.
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then reconvert delayedPC
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implementation for now and exceptions not properly handled.
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This is not yet connected to any model and not yet tested.
Also, reduce the number of parentheses needed by the parser. Namely, register declarations should no longer need parens around the types and let expressions should need fewer instances of parens around the expression (i.e. let a = exp ).
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loads/stores via c0 under cheri. Length checks for unaligned loads/stores are not correct and there seems to be no tests...
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non-capability writes on cheri.
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undefined unless we actually access memory which is uninitialised.
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assignment expression
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computing capability relative address. This is a little counter-intuitive but seems to be what is written in the spec. and passes more tests. Will consult with mroe to check logic here and possibly extract into a function for clarity.
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the advantage of actually doing what I want.
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unexpected sail behaviour with implicit cast form literal 0.
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swapped.
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this didn't cause an error).
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maybe do this in readCapReg
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implicit cast does not work as expected (appends zeros at bottom).
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emulate atomic tag access.
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version. Temporary 'solution' to building mips and cheri builds until proper factorising can take place.
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writes atomic)
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Implement reserved cap. perms (bits 8 and 9) because a test uses them even though they have no defined meaning (historically they did I think).
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Note to self: consider removing this cast after fixing overload resolution
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