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AgeCommit message (Expand)Author
2017-12-04added the Power modelShaked Flur
2017-12-04match what rmem expects from sail/armShaked Flur
2017-12-04renamed hgen to genShaked Flur
2017-11-30match what rmem (ppcmem2) expects from ISA MakefilesShaked Flur
2017-11-23renamingShaked Flur
2017-11-23added RISCV_ prefix to some values to stop Lem from renaming themShaked Flur
2017-11-07RISC-V parser checksShaked Flur
2017-11-02remove a lot of dead code form run_with_elf_cheri*Robert Norton
2017-11-02reset inCCallDelay in code that is not dead.Robert Norton
2017-11-01workaound for another odd interpreter error where top level let variable got ...Robert Norton
2017-11-01added RISC-V "fence r,r"Shaked Flur
2017-10-31work around interpreter crash by adding cast. Likely this kind of thing will ...Robert Norton
2017-10-31cheri: throw an exception if there is an attempt to access C26/IDC in the del...Robert Norton
2017-10-31cheri: ccall selector 1 should have a branch delay slot. TODO we need to thro...Robert Norton
2017-10-26fixed release acquire semantics of AMOsShaked Flur
2017-10-24fix default cap value on cheri128 following previous changes -- E stored in r...Robert Norton
2017-10-23cheri: Null capability should have maximum length, because in cheri128 we wan...Robert Norton
2017-10-16add CTestSubset instruction.Robert Norton
2017-10-16add missing new encodings for CJR and CJALR.Robert Norton
2017-10-16implement CMove as an alias for cmovz with zero register.Robert Norton
2017-10-16add support for CIncOffsetImmediate and CSetBoundsImmediate.Robert Norton
2017-10-16add support for capability branch null instructions.Robert Norton
2017-10-13Add support for new cheri instruction encodings. The order of pattern matchin...Robert Norton
2017-10-12Work around warning in ocaml shallow embedding of mips caused by buggy code g...Robert Norton
2017-10-09add translations for missing read/write kinds.Robert Norton
2017-10-09add translation of IK_mem_rmw interp_inter_imp. TODO: could we get rid of thi...Robert Norton
2017-10-09X86: Fix bug in register footprint caused by imperative variable update with ...Robert Norton
2017-10-06move nias_of_instruction into RMEM so that it can use shallow embedding ast a...Robert Norton
2017-10-02cheri: fix swapped cmovz and cmovn.Robert Norton
2017-10-01fixed JALR: do the register write first to allow po-later readsShaked Flur
2017-09-29fix those build errorsChristopher Pulte
2017-09-29Merge branch 'master' of https://bitbucket.org/Peter_Sewell/sailChristopher Pulte
2017-09-29fix deep_shallow_convert, stop using interp_interface.instruction for most th...Christopher Pulte
2017-09-29x86: add bit set, reset, complement operations.Robert Norton
2017-09-27fixed the RISC-V MakefileShaked Flur
2017-09-27split RISC-V to two Sail files to make it more readableShaked Flur
2017-09-27oopsShaked Flur
2017-09-26fixesChristopher Pulte
2017-09-26RISC-V: check alignment of atomic memory accesses (and escape when misaligned)Shaked Flur
2017-09-25x86: always perform write for cmpxchg by writing back original value if compa...Robert Norton
2017-09-22x86: implement get_ea_address function.Robert Norton
2017-09-22x86: remove unnecessary? read modify write of registers.Robert Norton
2017-09-22fix typo where Sz16 write to register was only writing 8 bits.Robert Norton
2017-09-21wibShaked Flur
2017-09-21added a comment to the x86 lock'd read and writeShaked Flur
2017-09-20add support for x86 lock prefix (also remove unused Read/Write_tag kind in et...Robert Norton
2017-09-19fixChristopher Pulte
2017-09-19According to Shaked NIAFP_register can be used to indicate that we don't know...Robert Norton
2017-09-18add regfp for x86 control flow instrucitons. Need more support for memory ind...Robert Norton
2017-09-15x86: implement regfp analysis function (no control flow yet)Robert Norton
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