sail - Formal specification language for ISAs

Age	Commit message (Collapse)	Author
2017-09-15	x86: implement regfp analysis function (no control flow yet)	Robert Norton

2017-09-15	reinstate deep/shallow conversion	Christopher Pulte

2017-09-13	add HLT instruction for RMEM integration.	Robert Norton

2017-09-11	added xml pp	Shaked Flur

2017-09-07	add MFENCE	Robert Norton

2017-09-06	power is builtin in old tc so use it.	Robert Norton

2017-09-03	added RISC-V strong-acquire/release	Shaked Flur

2017-09-02	fix for parsing diy generated tests	Shaked Flur

2017-09-02	check the status of SC before doing the memory write	Shaked Flur

2017-08-31	add EnumerationType type class: if a type is a member you get Ord membership ↵	Christopher Pulte
	and Set membership for free
2017-08-31	added RISC-V AMOs	Shaked Flur

2017-08-30	typeclass instance Ord(opcode)	Christopher Pulte

2017-08-24	typo	Shaked Flur

2017-08-24	typo	Shaked Flur

2017-08-24	added barrier-kind for x86 MFENCE;	Shaked Flur
	fixed some compare functions;
2017-08-22	x86: rename size type to avoid name clash in RMEM.	Robert Norton

2017-08-22	Merge branch 'master' of https://bitbucket.org/Peter_Sewell/sail	Christopher Pulte

2017-08-22	and fix that other places	Christopher Pulte

2017-08-22	added RISC-V "fence w,w" and "fence.i";	Shaked Flur
	fixed the interpreter nias analysis;
2017-08-22	adapt state.lem to RISCV additions	Christopher Pulte

2017-08-21	port x86 model to old type checker.	Robert Norton

2017-08-21	RISC-V load-reserved and store-conditional	Shaked Flur

2017-08-19	RISC-V store-release	Shaked Flur

2017-08-17	Merge branch 'master' of bitbucket.org:Peter_Sewell/sail	Shaked Flur
	# Conflicts: # risc-v/hgen/types.hgen
2017-08-17	added RISC-V load-acquire	Shaked Flur

2017-08-17	riscv: fix warnings because of unneeded catch-all cases in types.hgen.	Robert Norton

2017-08-17	fixed the RISC-V fences (3 types: "rw,rw"/"r,rw"/"rw,w")	Shaked Flur

2017-08-16	lem_interp: remove broken val_to_string_internal functions, replace with ↵	Jon French
	string_of_value as used everywhere else
2017-08-16	riscv: fix back to front args in store pretty print.	Robert Norton

2017-08-15	riscv: store the decoded branch immediate in the ast type -- this simplifies ↵	Robert Norton
	translation to and from herdtools ast.
2017-08-15	remove unneeded regs_out_in.hgen files.	Robert Norton

2017-08-15	riscv: include pred and succ fields in translation of FENCE (currently hard ↵	Robert Norton
	coded to zero
2017-08-15	better names for store parameters.	Robert Norton

2017-08-15	riscv: fix incorrect argument order for store parser.	Robert Norton

2017-08-15	fix incorrect mnemonic for lui	Robert Norton

2017-08-15	riscv: fix word/half backwards in load.	Robert Norton

2017-08-15	riscv: limit stores to only relevant bytes.	Robert Norton

2017-08-14	add risc-v fence instruction as re-using MIPS sync for now. Also place ↵	Robert Norton
	holders for FENCE.I and ECALL.
2017-08-12	Resolve ambiguity between negation of integers and bools	Thomas Bauereiss

2017-08-12	Fix compilation issue for 32-bit systems	Thomas Bauereiss

2017-08-11	further riscv rmem integration.	Robert Norton

2017-08-08	work on integrating risc-v model with rmem (incomplete).	Robert Norton

2017-08-08	work around missing >=_u in sail.	Robert Norton

2017-08-02	fix sail library test interpreter glue for API change. Also fix ↵	Robert Norton
	build_context val spec which was out of dated although lem did not complain for some reason...
2017-08-02	add .merlin file	Jon French

2017-08-02	fix run_with_elf*.ml with changed lem_interp api	Jon French

2017-07-27	implement RV64I based on version 2.0 user spec.	Robert Norton

2017-07-26	mips_extras.lem: fix references to Interp.V_foo	Jon French

2017-07-26	Merged in ojno/sail (pull request #1)	Jonathan French
	Footprint exhaustive evaluation fixes Approved-by: Jonathan French <me@jonathanfrench.net>
2017-07-24	interpreter: optionally print debugging traces	Jon French