| Age | Commit message (Collapse) | Author |
|
Interp: trying to add some debugging to isolate bug
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mips/cheri model.
|
|
|
|
|
|
|
|
to non-existent mips.sail in top level README.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
-- this could be varied but useful for compatibility with BERI test suite.
|
|
|
|
|
|
|
|
|
|
|
|
dump registers on terminating simulator anyway but we don't want tests to crash before the end."
|
|
|
|
|
|
during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
difference as without TLB we cannot run any non-kernel mode code anyway.
|
|
CP2Usable check if for cap. regsets.
|
|
|
|
|
|
|
|
the result should be (specifically for x mod y, x<0 & y<0).
|
|
producing '?'
|
|
|
|
|
|
|
|
|
|
|
|
requires some clean up (currently one huge function).
|
|
|
|
decode/translate_address/exhaustive. (Was previously correct for full register reads)
|