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AgeCommit message (Expand)Author
2016-05-27Fix parsing of sizeof and some printing issues with letKathy Gray
2016-05-27small change to comment printingKathy Gray
2016-05-27Also add to ottKathy Gray
2016-05-27Add sizeof to sail. Documentation to followKathy Gray
2016-05-26add makery for mips/cheir LOC count.Robert Norton
2016-05-25add support for capability load/store bits in TLBRobert Norton
2016-05-24restrict virtual and physical address sizes to 40 and 36 bits respectively --...Robert Norton
2016-05-20Add missing CP0BadVaddr in run_with_elfs.Robert Norton
2016-05-19workaround unable to read fields in PC translation bug.Robert Norton
2016-05-19correctly report TLB size and type in config reg.Robert Norton
2016-05-18Make TLB address error exception save BadVAddr.Robert Norton
2016-05-18Implement 8-entry software-managed TLB.Robert Norton
2016-05-16Implement the simulator dump cap registers instruction as a NOP since we dump...Robert Norton
2016-05-13implement config registers.Robert Norton
2016-05-13do something a bit more interesting with WAIT.Robert Norton
2016-05-13fixes to make counter interrupt work: don't attempt to read register fields d...Robert Norton
2016-05-13don't write 33-bit value to hwrena (suprised that this type checked).Robert Norton
2016-05-12allow writing hwrena 29 (UserLocal)Robert Norton
2016-05-12Implement count/compare registers for timer interrupts and rdhwr instruction.Robert Norton
2016-05-12rename ephemeral/non_ephemeral to global/local in accordance with current usage.Robert Norton
2016-05-12update/add some commentsRobert Norton
2016-05-12remove redundant wrapper function 'TranslateOrExit' and rename uses.Robert Norton
2016-05-12Enforce kernel only access to kernel address space. Doesn't really make any d...Robert Norton
2016-05-11Fix XXX missing register accessible check in ClearRegs, also only do CP2Usabl...Robert Norton
2016-05-10Initialise CP0Status BEV bit.Robert Norton
2016-05-10Clear LLbit on ERET regardless of ERL value.Robert Norton
2016-05-10Implement mfc0/mtc0 ErrorEPC.Robert Norton
2016-05-10calculate signed modulus using quot as ocaml and mips disagree about what the...Robert Norton
2016-05-09explicitly give result value for slti to workaround probable sail bug produci...Robert Norton
2016-05-09fix mips build by copying across run_with_elf_cheri.ml and removing cheri parts.Robert Norton
2016-05-09work around problem with <_s using signedRobert Norton
2016-05-09Reverse the list of events to respect their orderKathy Gray
2016-05-09commit test which fails due to not writing C31.offset in TranslateAddress.Robert Norton
2016-05-09Add more debugging information for vector concatenationKathy Gray
2016-05-06rewrite fde_loop to make it easier to understand and fix some tests. still re...Robert Norton
2016-05-05Factor out get_opcodeRobert Norton
2016-05-04Correct register field/slice reading for decreasing reads for decode/translat...Kathy Gray
2016-05-04fix incorrect exception code used on clc alignment check.Robert Norton
2016-05-04check for PC alignment on instruction fetch.Robert Norton
2016-05-03List registers required to handle exception during instruction fetch. Attempt...Robert Norton
2016-05-03actually read next_pc twice when handling a translate_address exceptionKathy Gray
2016-05-03write all or part of fields out of translate_address (instead of just all)Kathy Gray
2016-05-03cheri: check value of co-processor enable bit before all cheri instructions.Robert Norton
2016-05-03fix cheri and mips sail following change to type of TranslateAddress -- can n...Robert Norton
2016-05-03Change decode and translate_address to support writing register events (altho...Kathy Gray
2016-05-03immediate offset of load/store via capability is scaled by word size (ISA cha...Robert Norton
2016-04-29implement cgetpccsetoffset (new instruction)Robert Norton
2016-04-29new encoding for cgetpcc (ISA change).Robert Norton
2016-04-29implement 'big immediates' for CSC and CLC (ISA change).Robert Norton
2016-04-29use the correct exception vector for ccall/creturn.Robert Norton
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