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2016-07-01Add missing case to arith_op_no0Kathy Gray
Add type refinement to arm spec
2016-06-28Munge exception destination PC so we hit the correct address even when ↵Robert Norton
kcc.base is non-zero.
2016-06-27Don't blow up when test suite writes to K0 field of Config0 register.Robert Norton
2016-06-20Fix error in type checker that put some constraints wrongly into conditional ↵Kathy Gray
constraints, breaking power. Also improve reporting of contract constraints, but then turn them off :( to allow power to compile.
2016-06-10Make in-memory format of capabilities conform with that of CHERI which ↵Robert Norton
stores an absolute cursor instead of offset relative to base as a uarch optimisation. This is now part of the ISA and there is a test for it.
2016-06-07remove workarounds for sail unable to read fields during PC fetch. Should be ↵Robert Norton
no functional change.
2016-06-07Merge register access violation exception codes. ISA is evolving and is a ↵Robert Norton
little loose at the moment (does not specify what to do with deprecated permission bits).
2016-06-07Preserve padding in capability registers when converting to struct form -- ↵Robert Norton
this is required for copying data via (untagged) capabilities.
2016-06-07Fix issue in accessing fields and slices of registers during translate addressKathy Gray
2016-06-07cheri: implement the csub instruciton (new instruction)Robert Norton
2016-06-07add a test for failing TLB translation during instruction fetch.Robert Norton
2016-06-06remove mips test elf files no longer expected to work due to having ↵Robert Norton
incorrect LMA values (since sail interpreter now translates PC addresses).
2016-06-06Add explicit type cast required because of the way sail does slicing (we ↵Robert Norton
want indexing of pfn to be reset to 23..0). Kathy to investigate why this was not caught by type checker.
2016-06-06add test for failing tlb translation using current sail.Robert Norton
2016-06-06revert accidental functional change introduced when formatting -- simulator ↵Robert Norton
halt instructions decode statements are a special case of mtc0 so clauses must appear first.
2016-06-03Fix bug exposed/introduced by properly handling vector starts in the type ↵Kathy Gray
checker
2016-06-03Change path inside sail Makefile to look for sail directory instead of l2Kathy Gray
2016-06-03Improve formatting of latex export of mips spec: wrap lines, remove dollars ↵Robert Norton
in comments. No functional change.
2016-06-03update README re l2->sailPeter Sewell
2016-06-03Merge branch 'master' of bitbucket.org:Peter_Sewell/l2Peter Sewell
2016-06-03plumbing to make a pdf version of MIPS Sail spec, using LaTeX lstlistingsPeter Sewell
2016-06-03turn off debug print statementsKathy Gray
2016-06-03Mips file: removed some unnecessary parenthesisKathy Gray
Interp: trying to add some debugging to isolate bug
2016-06-03Add test demonstrating recently introduced regression where tlb match fail.Robert Norton
2016-06-03added ARMv8Shaked Flur
2016-06-03Reduce fill width of header to align closing comments nicely.Robert Norton
2016-06-02Fix most_significant case omissionKathy Gray
2016-06-02Get widening right now that it mattersKathy Gray
2016-06-02improve constraint range checkingKathy Gray
2016-06-02Apply headache to mips/cheri model.Robert Norton
2016-06-02Add rule in Makefile that uses headache to add copyright header to ↵Robert Norton
mips/cheri model.
2016-06-01Tweak wording of mips README.Robert Norton
2016-06-01Remove outdated XXXRobert Norton
2016-05-31delete obsolete Makefile (src/Makefile currently hanldes mips build).Robert Norton
2016-05-31Add README in mips directory describing file breakdown and remove reference ↵Robert Norton
to non-existent mips.sail in top level README.
2016-05-27Fix parsing of sizeof and some printing issues with letKathy Gray
2016-05-27small change to comment printingKathy Gray
2016-05-27Also add to ottKathy Gray
2016-05-27Add sizeof to sail. Documentation to followKathy Gray
2016-05-26add makery for mips/cheir LOC count.Robert Norton
2016-05-25add support for capability load/store bits in TLBRobert Norton
2016-05-24restrict virtual and physical address sizes to 40 and 36 bits respectively ↵Robert Norton
-- this could be varied but useful for compatibility with BERI test suite.
2016-05-20Add missing CP0BadVaddr in run_with_elfs.Robert Norton
2016-05-19workaround unable to read fields in PC translation bug.Robert Norton
2016-05-19correctly report TLB size and type in config reg.Robert Norton
2016-05-18Make TLB address error exception save BadVAddr.Robert Norton
2016-05-18Implement 8-entry software-managed TLB.Robert Norton
2016-05-16Implement the simulator dump cap registers instruction as a NOP since we ↵Robert Norton
dump registers on terminating simulator anyway but we don't want tests to crash before the end."
2016-05-13implement config registers.Robert Norton
2016-05-13do something a bit more interesting with WAIT.Robert Norton