diff options
Diffstat (limited to 'test')
25 files changed, 2334 insertions, 31 deletions
diff --git a/test/arm/run_tests.sh b/test/arm/run_tests.sh index f758d634..30f955b0 100755 --- a/test/arm/run_tests.sh +++ b/test/arm/run_tests.sh @@ -51,7 +51,7 @@ cd $SAILDIR/aarch64 printf "Compiling specification...\n" -if $SAILDIR/sail -no_lexp_bounds_check -o aarch64_test -ocaml prelude.sail no_vector/spec.sail decode_start.sail no_vector/decode.sail decode_end.sail main.sail 1> /dev/null 2> /dev/null; +if $SAILDIR/sail -no_lexp_bounds_check -o aarch64_test -ocaml no_vector.sail 1> /dev/null 2> /dev/null; then green "compiled no_vector specification" "ok"; mv aarch64_test $DIR/; @@ -83,7 +83,7 @@ printf "\nLoading specification into interpreter...\n" cd $SAILDIR/aarch64 -if $SAILDIR/sail -no_lexp_bounds_check -is $DIR/test.isail prelude.sail no_vector/spec.sail decode_start.sail no_vector/decode.sail decode_end.sail main.sail 1> /dev/null 2> /dev/null; +if $SAILDIR/sail -no_lexp_bounds_check -is $DIR/test.isail no_vector.sail 1> /dev/null 2> /dev/null; then green "loaded no_vector specification" "ok"; diff --git a/test/builtins/test_extras.lem b/test/builtins/test_extras.lem index 136f680e..ae3ed1ba 100644 --- a/test/builtins/test_extras.lem +++ b/test/builtins/test_extras.lem @@ -17,6 +17,3 @@ let undefined_bitvector len = return (zeros(len)) val undefined_unit : forall 'rv 'e. unit -> monad 'rv unit 'e let undefined_unit () = return () - -val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e -let internal_pick xs = return (List_extra.head xs) diff --git a/test/c/cheri_capreg.expect b/test/c/cheri_capreg.expect new file mode 100644 index 00000000..6e46a0e8 --- /dev/null +++ b/test/c/cheri_capreg.expect @@ -0,0 +1,10 @@ +default_cap = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +null_cap = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +C03 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +C02 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +C01 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +DDC = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +C03 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +C02 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +C01 = 0b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 +DDC = 0b10000000000000000000000000000000011111111111111110000111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111 diff --git a/test/c/cheri_capreg.sail b/test/c/cheri_capreg.sail new file mode 100644 index 00000000..e8890a4a --- /dev/null +++ b/test/c/cheri_capreg.sail @@ -0,0 +1,254 @@ +default Order dec + +/* this is here because if we don't have it before including vector_dec + we get infinite loops caused by interaction with bool/bit casts */ +val eq_bit2 = "eq_bit" : (bit, bit) -> bool +overload operator == = {eq_bit2} + +$include <vector_dec.sail> + +val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg} +/* sneaky deref with no effect necessary for bitfield writes */ +val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a + +val zeros_0 = "zeros" : forall 'n. int('n) -> bits('n) + +val zeros : forall 'n. unit -> bits('n) +function zeros() = zeros_0('n) + +val ones : forall 'n, 'n >= 0 . unit -> bits('n) +function ones() = replicate_bits (0b1,'n) + +val xor_vec = {c: "xor_bits" , _: "xor_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) + +val int_power = {ocaml: "int_power", lem: "pow", coq: "Z.pow"} : (int, int) -> int + +overload operator ^ = {xor_vec, int_power} + +val cast bool_to_bits : bool -> bits(1) +function bool_to_bits x = if x then 0b1 else 0b0 + +val cast bit_to_bool : bit -> bool +function bit_to_bool b = match b { + bitone => true, + bitzero => false +} + +val to_bits : forall 'l, 'l >= 0 .(atom('l), int) -> bits('l) +function to_bits (l, n) = get_slice_int(l, n, 0) + +/* 256 bit cap + tag */ +type CapReg = bits(257) + +struct CapStruct = { + tag : bool , + padding : bits(8) , + otype : bits(24), + uperms : bits(16), + perm_reserved11_14 : bits(4) , + access_system_regs : bool , + permit_unseal : bool , + permit_ccall : bool , + permit_seal : bool , + permit_store_local_cap : bool , + permit_store_cap : bool , + permit_load_cap : bool , + permit_store : bool , + permit_load : bool , + permit_execute : bool , + global : bool , + sealed : bool , + address : bits(64), + base : bits(64), + length : bits(64), +} + +let null_cap : CapStruct = struct { + tag = false, + padding = zeros(), + otype = zeros(), + uperms = zeros(), + perm_reserved11_14 = zeros(), + access_system_regs = false, + permit_unseal = false, + permit_ccall = false, + permit_seal = false, + permit_store_local_cap = false, + permit_store_cap = false, + permit_load_cap = false, + permit_store = false, + permit_load = false, + permit_execute = false, + global = false, + sealed = false, + address = zeros(), + base = zeros(), + length = 0xffffffffffffffff +} + +let default_cap : CapStruct = struct { + tag = true, + padding = zeros(), + otype = zeros(), + uperms = ones(), + perm_reserved11_14 = zeros(), + access_system_regs = true, + permit_unseal = true, + permit_ccall = true, + permit_seal = true, + permit_store_local_cap = true, + permit_store_cap = true, + permit_load_cap = true, + permit_store = true, + permit_load = true, + permit_execute = true, + global = true, + sealed = false, + address = zeros(), + base = zeros(), + length = 0xffffffffffffffff +} + +let null_cap : CapStruct = struct { + tag = false, + padding = zeros(), + otype = zeros(), + uperms = zeros(), + perm_reserved11_14 = zeros(), + access_system_regs = false, + permit_unseal = false, + permit_ccall = false, + permit_seal = false, + permit_store_local_cap = false, + permit_store_cap = false, + permit_load_cap = false, + permit_store = false, + permit_load = false, + permit_execute = false, + global = false, + sealed = false, + address = zeros(), + base = zeros(), + length = 0xffffffffffffffff +} + +let 'cap_size = 32 + +function capRegToCapStruct(capReg) : CapReg -> CapStruct = + struct { + tag = capReg[256], + padding = capReg[255..248], + otype = capReg[247..224], + uperms = capReg[223..208], + perm_reserved11_14 = capReg[207..204], + access_system_regs = capReg[203], + permit_unseal = capReg[202], + permit_ccall = capReg[201], + permit_seal = capReg[200], + permit_store_local_cap = capReg[199], + permit_store_cap = capReg[198], + permit_load_cap = capReg[197], + permit_store = capReg[196], + permit_load = capReg[195], + permit_execute = capReg[194], + global = capReg[193], + sealed = capReg[192], + address = capReg[191..128], + base = capReg[127..64], + length = capReg[63..0] + } + +function getCapPerms(cap) : CapStruct -> bits(31) = + ( + cap.uperms + @ cap.perm_reserved11_14 + @ cap.access_system_regs + @ cap.permit_unseal + @ cap.permit_ccall + @ cap.permit_seal + @ cap.permit_store_local_cap + @ cap.permit_store_cap + @ cap.permit_load_cap + @ cap.permit_store + @ cap.permit_load + @ cap.permit_execute + @ cap.global + ) + + +/* Function to convert capabilities to in-memory format. */ +function capStructToMemBits256(cap) : CapStruct -> bits(256) = + ( + cap.padding + @ cap.otype + @ getCapPerms(cap) + @ cap.sealed + @ cap.address + @ cap.base + @ cap.length + ) + + +/* When saving/restoring capabilities xor them with bits of null_cap -- + this ensures that canonical null_cap is always all-zeros in memory + even though it may have bits set logically (e.g. length or exponent) */ + +let null_cap_bits : bits(256) = capStructToMemBits256(null_cap) + +function capStructToMemBits(cap) : CapStruct -> bits(256)= + capStructToMemBits256(cap) ^ null_cap_bits + +function memBitsToCapBits(tag, b) : (bool, bits(256)) -> bits(257) = + tag @ (b ^ null_cap_bits) + +function capStructToCapReg(cap) : CapStruct -> CapReg = cap.tag @ capStructToMemBits256(cap) + +register DDC : CapReg +register C01 : CapReg +register C02 : CapReg +register C03 : CapReg + +let CapRegs : vector(4, dec, register(CapReg)) = + [ + ref C03, + ref C02, + ref C01, + ref DDC + ] + +val readCapReg : bits(2) -> CapStruct effect {rreg} +function readCapReg(n) = + if (n == 0b00) then + default_cap + else + let i = unsigned(n) in + capRegToCapStruct(reg_deref(CapRegs[i])) + +function writeCapReg(n, cap) : (bits(2), CapStruct) -> unit = + if (n == 0b00) then + () + else + let i = unsigned(n) in + (*CapRegs[i]) = capStructToCapReg(cap) + +val "print_bits" : forall 'n. (string, bits('n)) -> unit + +val main : unit -> unit effect {rreg, wreg} + +function main() = { + print_bits("default_cap = ", capStructToCapReg(default_cap)); + print_bits("null_cap = ", capStructToCapReg(null_cap)); + DDC = capStructToCapReg(default_cap); + print_bits("C03 = ", C03); + print_bits("C02 = ", C02); + print_bits("C01 = ", C01); + print_bits("DDC = ", DDC); + foreach(i from 1 to 3) { + let idx = to_bits(2, i); + writeCapReg(idx, null_cap) + }; + print_bits("C03 = ", C03); + print_bits("C02 = ", C02); + print_bits("C01 = ", C01); + print_bits("DDC = ", DDC); +}
\ No newline at end of file diff --git a/test/c/eq_struct.expect b/test/c/eq_struct.expect new file mode 100644 index 00000000..9766475a --- /dev/null +++ b/test/c/eq_struct.expect @@ -0,0 +1 @@ +ok diff --git a/test/c/eq_struct.sail b/test/c/eq_struct.sail new file mode 100644 index 00000000..b4258569 --- /dev/null +++ b/test/c/eq_struct.sail @@ -0,0 +1,38 @@ +default Order dec + +$include <flow.sail> +$include <exception_basic.sail> + +val eq = "eq_anything" : forall ('a : Type). ('a, 'a) -> bool + +overload operator == = {eq} + +val neq : forall ('a : Type). ('a, 'a) -> bool + +overload operator != = {neq} + +overload ~ = {not_bool} + +function neq(x, y) = ~(eq(x, y)) + +struct S = { + field1: int, + field2: vector(8, dec, bit) +} + +val "print" : string -> unit + +val main : unit -> unit effect {escape} + +function main() = { + let s : S = struct { + field1 = 4, + field2 = 0xFF + }; + assert(s == s, "1"); + assert(~(s == { s with field2 = 0xAB }), "2"); + assert(s != { s with field1 = 5}, "3"); + assert(s == { s with field2 = 0xFF }); + assert({ s with field1 = 0} == {s with field1 = 0}); + print("ok\n") +}
\ No newline at end of file diff --git a/test/c/foreach_none.expect b/test/c/foreach_none.expect new file mode 100644 index 00000000..9766475a --- /dev/null +++ b/test/c/foreach_none.expect @@ -0,0 +1 @@ +ok diff --git a/test/c/foreach_none.sail b/test/c/foreach_none.sail new file mode 100644 index 00000000..bc960b85 --- /dev/null +++ b/test/c/foreach_none.sail @@ -0,0 +1,11 @@ + +val "print" : string -> unit + +val main : unit -> unit + +function main() = { + foreach (i from 0 to -1 by 1 in inc) { + print("unreachable\n"); + }; + print("ok\n") +}
\ No newline at end of file diff --git a/test/c/gvectorlit.expect b/test/c/gvectorlit.expect index d3a1e9ab..9328600c 100644 --- a/test/c/gvectorlit.expect +++ b/test/c/gvectorlit.expect @@ -1,2 +1,2 @@ -x[0] = 0xAB -x[1] = 0xCD +x[0] = 0xCD +x[1] = 0xAB diff --git a/test/c/large_bitvector.expect b/test/c/large_bitvector.expect new file mode 100644 index 00000000..f67ec84a --- /dev/null +++ b/test/c/large_bitvector.expect @@ -0,0 +1,12 @@ +x = 0x1FFFF0000FFFFFFFF +length(x) = 68 +y = 0x1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF +length(y) = 204 +z = 0x1FFFF0000FFFFFFFF1FFFF0000FFFFFFFF1CAFE0000FFFFFFFF +length(z) = 204 +q = 0xFF0000FFFFFFFF1FFFF0000FFFFFFFF1CAFE0000FFFFFFFF +w = -24519554509435141245919758063389544641259977658452672513 +length(q) = 192 +0x8000 +0b1 @ zeros(64 * 3 - 1) = 0x800000000000000000000000000000000000000000000000 +q = 0x800000000000000000000000000000000000000000000000 diff --git a/test/c/large_bitvector.sail b/test/c/large_bitvector.sail new file mode 100644 index 00000000..78189d7d --- /dev/null +++ b/test/c/large_bitvector.sail @@ -0,0 +1,30 @@ +default Order dec + +$include <arith.sail> +$include <vector_dec.sail> + +val "zeros" : forall 'n. int('n) -> bits('n) + +val main : unit -> unit + +function main() = { + let x = [0x1FFFF0000FFFF0000 with 15 .. 0 = 0xFFFF]; + print_bits("x = ", x); + print_int("length(x) = ", length(x)); + let y = replicate_bits(x, 3); + print_bits("y = ", y); + print_int("length(y) = ", length(y)); + let z = [y with 63 .. (63 - 15) = 0xCAFE]; + print_bits("z = ", z); + print_int("length(z) = ", length(z)); + q = slice(z, 0, 64 * 3); + print_bits("q = ", q); + w = signed(q); + print_int("w = ", w); + print_int("length(q) = ", length(q)); + print_bits("", [0xFFFF with 14 .. 0 = zeros(15)]); + print_bits("0b1 @ zeros(64 * 3 - 1) = ", 0b1 @ zeros(64 * 3 - 1)); + q[64 * 3 - 2 .. 0] = zeros(64 * 3 - 1); + print_bits("q = ", q); + () +} diff --git a/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 b/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 Binary files differnew file mode 100644 index 00000000..61954cd3 --- /dev/null +++ b/test/cheri/cheribsd-cheri-sim-mdroot-smoketest-kernel.bz2 diff --git a/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 b/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 Binary files differnew file mode 100644 index 00000000..33794547 --- /dev/null +++ b/test/cheri/freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 diff --git a/test/cheri/run_tests.sh b/test/cheri/run_tests.sh index 4e1550f4..337974d7 100755 --- a/test/cheri/run_tests.sh +++ b/test/cheri/run_tests.sh @@ -65,6 +65,17 @@ else red "Building MIPS_C specification" "fail" fi +printf "Booting FreeBSD-MIPS...\n" + +bunzip2 -fk freebsd-beri-sim-mdroot-smoketest_bootonly-kernel.bz2 +time $SAILDIR/mips/mips_c --cyclelimit 85000000 --binary 0x100000,freebsd-beri-sim-mdroot-smoketest_bootonly-kernel --binary 0x7f010000,sim.dtb --image simboot_128m.sailbin > freebsd_out.txt +if grep -q 'Done booting' freebsd_out.txt; +then + green "Booting FreeBSD MIPS" "ok" +else + red "Booting FreeBSD MIPS" "fail" +fi + printf "Building CHERI 256 specification...\n" if make -C $SAILDIR/cheri cheri ; diff --git a/test/cheri/sim.dtb b/test/cheri/sim.dtb Binary files differnew file mode 100644 index 00000000..2561f997 --- /dev/null +++ b/test/cheri/sim.dtb diff --git a/test/cheri/simboot_128m.sailbin b/test/cheri/simboot_128m.sailbin new file mode 100644 index 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+elf_entry +10376293542535364608 diff --git a/test/coq/pass/allpats.sail b/test/coq/pass/allpats.sail new file mode 100644 index 00000000..c6e111e9 --- /dev/null +++ b/test/coq/pass/allpats.sail @@ -0,0 +1,100 @@ +/* Not really *all* of the patterns, but enough to exercise the exhaustiveness + checker for Coq output */ + +default Order dec +$include <prelude.sail> + +enum anenum = {Athing, Bthing, Cthing} + +union aunion = {Dthing: unit, Ething: anenum, Fthing: (anenum,int)} + +struct arecord = {elone: anenum, eltwo: aunion} + +val f : (anenum, aunion, arecord, vector(5,dec,int), bits(4),list(anenum)) -> unit + +function f(a,b,c,d,e,g) = { + match a { + Athing => (), + Bthing => (), + Cthing => () + }; + match a { + Athing => (), + _ => () + }; + match a { + Athing => (), + Bthing => () + }; + match b { + Dthing(()) => (), + Ething(Athing) => (), + Ething(Bthing) => (), + Ething(Cthing) => (), + Fthing(Athing,_) => (), + Fthing(Bthing,_) => (), + Fthing(Cthing,_) => () + }; + match b { + Dthing(()) => (), + Ething(Athing) => (), + Ething(Bthing) => (), + Ething(Cthing) => (), + Fthing(Athing,_) => (), + Fthing(Cthing,_) => () + }; + match b { + Dthing(()) => (), + Ething(Athing) => (), + Ething(Bthing) => (), + Ething(Cthing) => (), + Fthing(Athing,_) => (), + Fthing(_ as x,_) => () + }; + /* Um, no syntax for record patterns? */ + /* Vector patterns must be bits? */ + match e { + [_,_,_,bitzero] => (), + [_,_,_,_] => () + }; + match e { + [_,_,_,bitzero] => () + }; + match e { + [_,bitzero] @ (_ : bits(2)) => (), + _ => () + }; + match e { + [_,bitzero] @ (_ : bits(2)) => () + }; + match (a,b) { + (Athing,Ething(Bthing)) => (), + (_,Fthing(_,_)) => (), + (_,Dthing(())) => (), + (Bthing,_) => (), + (Cthing,_) => () + }; + match (a,b) { + (Athing,Ething(Bthing)) => (), + (Athing,Ething(_)) => (), + (_,Fthing(_,_)) => (), + (_,Dthing(())) => (), + (Bthing,_) => (), + (Cthing,_) => () + }; + match g { + [| |] => (), + [| Athing, Bthing |] => (), + _::_::_ => () + }; + match g { + [| |] => (), + [| Athing, _, Bthing |] => (), + _::_::_::_ => () + }; + match g { + [| |] => (), + [| Athing, _, Bthing |] => (), + _::_ => () + } +}
\ No newline at end of file diff --git a/test/coq/pass/atom.sail b/test/coq/pass/atom.sail new file mode 100644 index 00000000..c9c27b5d --- /dev/null +++ b/test/coq/pass/atom.sail @@ -0,0 +1,21 @@ +default Order dec +$include <flow.sail> +$include <arith.sail> + +val f : forall 'n, 'n >= 0. atom(8 * 'n) -> int + +function f(x) = x+1 + +val g : forall 'n, 'n > 0. atom('n) -> atom(2*'n) +val h : forall 'n, 'n > 1. atom('n) -> int + +function h(x) = x + +val test : unit -> bool + +function test() = { + /* Using f with Coq would need us to provide/infer witnesses for 'n + f(0) == 1 & f(8) == 9 + */ + h(g(1)) == 2 +}
\ No newline at end of file diff --git a/test/coq/run_tests.sh b/test/coq/run_tests.sh index 2be5e535..5a723a06 100755 --- a/test/coq/run_tests.sh +++ b/test/coq/run_tests.sh @@ -5,7 +5,7 @@ DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )" SAILDIR="$DIR/../.." TYPECHECKTESTSDIR="$DIR/../typecheck/pass" EXTRATESTSDIR="$DIR/pass" -BBVDIR="$DIR/../../../bbv" +BBVDIR="$DIR/../../../bbv/theories" RED='\033[0;31m' GREEN='\033[0;32m' diff --git a/test/hol/test_raw_addScript.sml b/test/hol/test_raw_addScript.sml index 1eb90ef8..20465eb2 100644 --- a/test/hol/test_raw_addScript.sml +++ b/test/hol/test_raw_addScript.sml @@ -783,7 +783,7 @@ val () = computeLib.extend_compset [ ] ] cs; -val empty_state = ``init_state initial_regstate bool_oracle seed``; +val empty_state = ``init_state initial_regstate``; val init_registers_result = ``init_registers vinitPC s`` @@ -927,7 +927,7 @@ install_code_result val test_raw_add_thm = Q.store_thm("test_raw_add_thm", `PrePost - (λs. s = init_state initial_regstate bool_oracle seed) + (λs. s = init_state initial_regstate) (install_and_run test_raw_add_insts 40) (λ_ s. test_raw_add_post s)`, rw[PrePost_def] @@ -1378,7 +1378,7 @@ computeLib.CBV_CONV cs ``decode (EL 1 test_raw_add_insts)`` val th1 = EVAL ``THE (decode (EL 1 test_raw_add_insts))`` -val s1 = EVAL ``init_cp0_state () (init_state (regs:regstate) o1 seed)`` +val s1 = EVAL ``init_cp0_state () (init_state (regs:regstate))`` val th2 = ``execute ^(rhs(concl th1)) ^s1`` |> SIMP_CONV(srw_ss())[execute_def] diff --git a/test/isabelle/Aarch64_code.thy b/test/isabelle/Aarch64_code.thy index 05e5bb2e..8a0e1795 100644 --- a/test/isabelle/Aarch64_code.thy +++ b/test/isabelle/Aarch64_code.thy @@ -52,7 +52,7 @@ fun write_char_mem :: "int \<Rightarrow> char \<Rightarrow> (regstate, unit, exc bindS (write_mem_valS BC_bitU_list (bits_of_nat 8 (nat_of_char c))) (\<lambda>_. returnS ()))" -definition "initial_state \<equiv> init_state initial_regstate (\<lambda>seed. (False, seed)) 0" +definition "initial_state \<equiv> init_state initial_regstate" code_printing constant elf_entry \<rightharpoonup> (OCaml) "(Int'_of'_integer (Elf'_loader.elf'_entry _))" termination BigEndianReverse sorry diff --git a/test/isabelle/Cheri_code.thy b/test/isabelle/Cheri_code.thy index cfd01413..c0e8f9a7 100644 --- a/test/isabelle/Cheri_code.thy +++ b/test/isabelle/Cheri_code.thy @@ -5,32 +5,55 @@ begin declare [[code abort: failwith]] code_datatype - DADDIU DADDU DADDI DADD ADD ADDI ADDU ADDIU DSUBU DSUB SUB SUBU AND0 ANDI OR0 + DADDIU DADDU DADDI DADD ADD ADDI ADDU ADDIU DSUBU DSUB SUB SUBU AND0 ANDI OR0 ORI NOR XOR0 XORI LUI DSLL DSLL32 DSLLV DSRA DSRA32 DSRAV DSRL DSRL32 DSRLV SLL SLLV SRA SRAV SRL SRLV SLT SLTI SLTU SLTIU MOVN MOVZ MFHI MFLO MTHI MTLO MUL MULT MULTU DMULT DMULTU MADD MADDU MSUB MSUBU DIV DIVU DDIV DDIVU J JAL JR JALR - BEQ BCMPZ SYSCALL_THREAD_START ImplementationDefinedStopFetching SYSCALL BREAK - WAIT TRAPREG TRAPIMM Load Store LWL LWR SWL SWR LDL LDR SDL SDR CACHE PREF SYNC - MFC0 HCF MTC0 TLBWI TLBWR TLBR TLBP RDHWR ERET CGetPerm CGetType CGetBase - CGetLen CGetTag CGetSealed CGetOffset CGetPCC CGetPCCSetOffset CGetCause - CSetCause CReadHwr CWriteHwr CAndPerm CToPtr CSub CPtrCmp CIncOffset - CIncOffsetImmediate CSetOffset CSetBounds CSetBoundsImmediate CSetBoundsExact - CClearTag CMOVX ClearRegs CFromPtr CBuildCap CCopyType CCheckPerm CCheckType - CTestSubset CSeal CCSeal CUnseal CCall CReturn CBX CBZ CJALR CLoad CStore CSC - CLC C2Dump RI CGetAddr - -termination whileM sorry + BEQ BCMPZ SYSCALL BREAK WAIT TRAPREG TRAPIMM Load Store LWL LWR SWL SWR LDL LDR + SDL SDR CACHE SYNC MFC0 HCF MTC0 TLBWI TLBWR TLBR TLBP RDHWR ERET CGetPerm + CGetType CGetBase CGetLen CGetTag CGetSealed CGetOffset CGetPCC + CGetPCCSetOffset CGetCause CSetCause CReadHwr CWriteHwr CAndPerm CToPtr CSub + CPtrCmp CIncOffset CIncOffsetImmediate CSetOffset CSetBounds + CSetBoundsImmediate CSetBoundsExact CClearTag CMOVX ClearRegs CFromPtr + CBuildCap CCopyType CCheckPerm CCheckType CTestSubset CSeal CCSeal CUnseal + CCall CReturn CBX CBZ CJALR CLoad CStore CSC CLC C2Dump RI CGetAddr + +(* Fake termination proofs of loops for code generation *) +lemma whileM_dom: "whileM_dom (vars, cond, body)" sorry +termination whileM using whileM_dom by auto +lemma whileS_dom: "whileS_dom (vars, cond, body, s)" sorry +termination whileS using whileS_dom by auto + +lemma liftS_whileM: "\<lbrakk>whileM vars cond body\<rbrakk>\<^sub>S = whileS vars (liftS \<circ> cond) (liftS \<circ> body)" + by (intro ext liftState_whileM[OF whileS_dom whileM_dom]) + +(* Pre-lift main loop to state monad to gain some performance *) +fun mainS :: "unit \<Rightarrow> (regstate, unit, exception) monadS" where + "mainS () = \<lbrakk>main ()\<rbrakk>\<^sub>S" + +schematic_goal liftS_main[symmetric, code]: "?m = mainS" + by (intro ext) + (simp add: main_def liftState_simp liftS_whileM comp_def del: whileM.simps whileS.simps + cong: bindS_cong if_cong) + +fun print_endline' :: "String.literal \<Rightarrow> unit" where "print_endline' _ = ()" +lemma [code]: "print_endline s = print_endline' (String.implode s)" by auto fun prerr_endline' :: "String.literal \<Rightarrow> unit" where "prerr_endline' _ = ()" lemma [code]: "prerr_endline s = prerr_endline' (String.implode s)" by auto +fun prerr_string' :: "String.literal \<Rightarrow> unit" where "prerr_string' _ = ()" +lemma [code]: "prerr_string s = prerr_string' (String.implode s)" by auto + fun putchar' :: "char \<Rightarrow> unit" where "putchar' _ = ()" lemma [code]: "putchar c = putchar' (char_of_nat (nat c))" by auto code_identifier code_module List \<rightharpoonup> (OCaml) "List0" code_printing constant String.implode \<rightharpoonup> (OCaml) "!(let l = _ in let res = Bytes.create (List.length l) in let rec imp i = function | [] -> res | c :: l -> Bytes.set res i c; imp (i + 1) l in imp 0 l)" +code_printing constant print_endline' \<rightharpoonup> (OCaml) "Pervasives.print'_endline" code_printing constant prerr_endline' \<rightharpoonup> (OCaml) "Pervasives.prerr'_endline" +code_printing constant prerr_string' \<rightharpoonup> (OCaml) "Pervasives.prerr'_string" code_printing constant putchar' \<rightharpoonup> (OCaml) "Pervasives.print'_char" declare insert_code[code del] @@ -50,12 +73,12 @@ fun write_char_mem :: "int \<Rightarrow> char \<Rightarrow> (regstate, unit, exc bindS (write_mem_valS BC_bitU_list (bits_of_nat 8 (nat_of_char c))) (\<lambda>_. returnS ()))" -definition "initial_state \<equiv> init_state initial_regstate (\<lambda>seed. (False, seed)) 0" +definition "initial_state \<equiv> init_state initial_regstate\<lparr>memstate := (\<lambda>_. Some [B0, B0, B0, B0, B0, B0, B0, B0])\<rparr>" code_printing constant elf_entry \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Elf'_loader.elf'_entry _))" code_printing constant get_time_ns \<rightharpoonup> (OCaml) "(Arith.Int'_of'_integer (Big'_int.big'_int'_of'_int (Pervasives.int'_of'_float (1e9 *. Unix.gettimeofday _))))" -export_code main initial_state liftState get_regval set_regval bindS returnS iteriS iterS +export_code mainS initial_state liftState get_regval set_regval bindS returnS iteriS iterS write_char_mem integer_of_int int_of_integer "op + :: int \<Rightarrow> int \<Rightarrow> int" prerr_results in OCaml file "cheri_export.ml" diff --git a/test/isabelle/run_cheri.ml b/test/isabelle/run_cheri.ml index f51ef4dd..c50d525d 100644 --- a/test/isabelle/run_cheri.ml +++ b/test/isabelle/run_cheri.ml @@ -63,8 +63,8 @@ let usage_msg = "Sail OCaml RTS options:" let () = Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s]) usage_msg -let (>>) = State_monad.bindS -let liftS = State_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval) +let (>>) = Sail2_state_monad.bindS +(*let liftS = Sail2_state_lifting.liftState (Cheri_types.get_regval, Cheri_types.set_regval)*) let load_elf_segment seg = let open Elf_interpreted_segment in @@ -78,7 +78,7 @@ let load_elf_segment seg = prerr_endline ("Segment base address: " ^ Big_int.string_of_big_int base); prerr_endline ("Segment physical address: " ^ Big_int.string_of_big_int paddr); print_segment seg; - State.iteriS writer (Byte_sequence.char_list_of_byte_sequence bs) + Sail2_state.iteriS writer (Byte_sequence.char_list_of_byte_sequence bs) let _ = Random.self_init (); @@ -88,5 +88,5 @@ let _ = in (* State_monad.prerr_results *) (Cheri_code.initial_state |> - (State.iterS load_elf_segment elf_segments >> (fun _ -> - liftS (Cheri.main ())))); + (Sail2_state.iterS load_elf_segment elf_segments >> (fun _ -> + (Cheri_code.mainS ())))); diff --git a/test/riscv/tests/rv64ua-p-lrsc.elf b/test/riscv/tests/rv64ua-p-lrsc.elf Binary files differnew file mode 100755 index 00000000..0fb5b44e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-lrsc.elf diff --git a/test/riscv/tests/rv64ua-v-lrsc.elf b/test/riscv/tests/rv64ua-v-lrsc.elf Binary files differnew file mode 100755 index 00000000..3f49c87c --- /dev/null +++ b/test/riscv/tests/rv64ua-v-lrsc.elf |
