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-rw-r--r--test/typecheck/pass/arm_types.sail2
-rw-r--r--test/typecheck/pass/exist_tlb.sail2
-rw-r--r--test/typecheck/pass/simple_record_access.sail2
3 files changed, 6 insertions, 0 deletions
diff --git a/test/typecheck/pass/arm_types.sail b/test/typecheck/pass/arm_types.sail
index 83cc8687..af0bcba9 100644
--- a/test/typecheck/pass/arm_types.sail
+++ b/test/typecheck/pass/arm_types.sail
@@ -1,3 +1,5 @@
+$include <flow.sail>
+
enum boolean = {FALSE, TRUE}
enum signal = {LOW, HIGH}
diff --git a/test/typecheck/pass/exist_tlb.sail b/test/typecheck/pass/exist_tlb.sail
index f1b79b3d..de15edf8 100644
--- a/test/typecheck/pass/exist_tlb.sail
+++ b/test/typecheck/pass/exist_tlb.sail
@@ -1,3 +1,5 @@
+$include <flow.sail>
+
val extz : forall ('n : Int) ('m : Int) ('ord : Order).
vector('n, 'ord, bit) -> vector('m, 'ord, bit)
diff --git a/test/typecheck/pass/simple_record_access.sail b/test/typecheck/pass/simple_record_access.sail
index b1eab652..a6e34c8b 100644
--- a/test/typecheck/pass/simple_record_access.sail
+++ b/test/typecheck/pass/simple_record_access.sail
@@ -1,3 +1,5 @@
+$include <flow.sail>
+
enum signal = {LOW, HIGH}
type Bit32 = vector(32, inc, bit)