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-rw-r--r--src/test/power.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/power.sail b/src/test/power.sail
index 9cf49dc3..02b4555f 100644
--- a/src/test/power.sail
+++ b/src/test/power.sail
@@ -91,7 +91,7 @@ register (vector <0, 64, inc, bit>) DCR1
let (vector <0, 2, inc, (register<(vector<0, 64, inc, bit>)>) >) DCR =
[ DCR0, DCR1 ]
-val extern ( nat , nat ) -> (bit[64]) effect { wmem , rmem } MEM
+val extern forall Nat 'n. ( nat , [|'n|] ) -> (bit[8 * 'n]) effect { wmem , rmem } MEM
(* XXX effect for trap? *)
val extern unit -> unit effect pure trap