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-rw-r--r--src/test/test1.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/test1.sail b/src/test/test1.sail
index 8143bf5d..0c08324c 100644
--- a/src/test/test1.sail
+++ b/src/test/test1.sail
@@ -12,7 +12,7 @@ typedef creg = register bits [5:10] { 5 : h ; 6..7 : j}
let (bool) e = true
val forall Nat 'a, Nat 'b. bit['a:'b] sliced
let (bit) v = bitzero
-let ( bit [ 32 ] ) v1 = 0b101
+let ( bit [ 3 ] ) v1 = 0b101
let ( bit [32] ) v2 = 0xABCDEF01