summaryrefslogtreecommitdiff
path: root/src/lem_interp
diff options
context:
space:
mode:
Diffstat (limited to 'src/lem_interp')
-rw-r--r--src/lem_interp/interp_interface.lem7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/lem_interp/interp_interface.lem b/src/lem_interp/interp_interface.lem
index 4d8cc82c..3d4b2e6d 100644
--- a/src/lem_interp/interp_interface.lem
+++ b/src/lem_interp/interp_interface.lem
@@ -52,3 +52,10 @@ val interp : interp_mode -> instruction_state -> outcome
val interp_exhaustive : instruction_state -> list event
+val mem_read_analysis : instruction_state -> list event (*Should record all rreg events where the registers are involved in memory reads to compute the addressses in is*)
+
+val mem_write_analysis : instruction_state -> list event (*Should record all rreg events where the registers are involved in memory writes to compute the address (and value?, in a separate list?)*)
+
+
+(*Questions : isync? any other special instructions that we need to inform the memory model etc. about
+ : let's look again at conditional memory instructions, based on the book *)