19 files changed, 12008 insertions, 0 deletions

diff --git a/snapshots/coq/README b/snapshots/coq/README
new file mode 100644
index 00000000..bd7f12d0
--- /dev/null
+++ b/snapshots/coq/README
@@ -0,0 +1,2 @@
+Check out a copy of https://github.com/mit-plv/bbv in the parent directory and
+build it.  Then run ./build.
diff --git a/snapshots/coq/build b/snapshots/coq/build
new file mode 100755
index 00000000..e672912e
--- /dev/null
+++ b/snapshots/coq/build
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+if [ ! -d mips ]; then
+  echo Run clean from the coq directory
+  exit 1
+fi
+
+if [ ! -d ../bbv ]; then
+  echo 'Check out a copy of https://github.com/mit-plv/bbv in the parent directory and build it.'
+  exit 1
+fi
+
+set -ex
+cd lib/coq
+make
+cd ../../mips
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_extras.v
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_types.v
+coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips.v
diff --git a/snapshots/coq/clean b/snapshots/coq/clean
new file mode 100755
index 00000000..0d6f8785
--- /dev/null
+++ b/snapshots/coq/clean
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+if [ ! -d mips ]; then
+  echo Run clean from the coq directory
+  exit 1
+fi
+
+set -ex 
+rm -f mips/*.vo
+cd lib/coq
+make clean
diff --git a/snapshots/coq/lib/coq/Makefile b/snapshots/coq/lib/coq/Makefile
new file mode 100644
index 00000000..97869e3c
--- /dev/null
+++ b/snapshots/coq/lib/coq/Makefile
@@ -0,0 +1,24 @@
+BBV_DIR=../../../bbv/theories
+
+SRC=Sail2_prompt_monad.v  Sail2_prompt.v  Sail2_impl_base.v  Sail2_instr_kinds.v  Sail2_operators_bitlists.v  Sail2_operators_mwords.v  Sail2_operators.v  Sail2_values.v  Sail2_state_monad.v  Sail2_state.v
+
+COQ_LIBS = -R . Sail -R "$(BBV_DIR)" bbv
+
+TARGETS=$(SRC:.v=.vo)
+
+.PHONY: all clean *.ide
+
+all: $(TARGETS)
+clean:
+	rm -f -- $(TARGETS) $(TARGETS:.vo=.glob) $(TARGETS:%.vo=.%.aux) deps
+
+%.vo: %.v
+	coqc $(COQ_LIBS) $<
+
+%.ide: %.v
+	coqide $(COQ_LIBS) $<
+
+deps: $(SRC)
+	coqdep $(COQ_LIBS) $(SRC) > deps
+
+-include deps
diff --git a/snapshots/coq/lib/coq/Sail2_impl_base.v b/snapshots/coq/lib/coq/Sail2_impl_base.v
new file mode 100644
index 00000000..639083f6
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_impl_base.v
@@ -0,0 +1,1058 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_instr_kinds.
+
+(*
+class ( EnumerationType 'a ) 
+  val toNat : 'a -> nat
+end
+
+
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 =
+  compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare = defaultCompare
+
+ 
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+  let compare = enumeration_typeCompare
+  let (<)  r1 r2 = (enumeration_typeCompare r1 r2) = LT
+  let (<=) r1 r2 = (enumeration_typeCompare r1 r2) <> GT
+  let (>)  r1 r2 = (enumeration_typeCompare r1 r2) = GT
+  let (>=) r1 r2 = (enumeration_typeCompare r1 r2) <> LT
+end
+
+
+
+(* maybe isn't a member of type Ord - this should be in the Lem standard library*)
+instance forall 'a. Ord 'a => (Ord (maybe 'a))
+  let compare = maybeCompare compare
+  let (<)  r1 r2 = (maybeCompare compare r1 r2) = LT
+  let (<=) r1 r2 = (maybeCompare compare r1 r2) <> GT
+  let (>)  r1 r2 = (maybeCompare compare r1 r2) = GT
+  let (>=) r1 r2 = (maybeCompare compare r1 r2) <> LT
+end
+
+type word8 = nat (* bounded at a byte, for when lem supports it*)
+
+type end_flag =
+  | E_big_endian
+  | E_little_endian
+
+type bit =
+  | Bitc_zero
+  | Bitc_one
+
+type bit_lifted = 
+  | Bitl_zero
+  | Bitl_one
+  | Bitl_undef    (* used for modelling h/w arch unspecified bits *)
+  | Bitl_unknown  (* used for interpreter analysis exhaustive execution *)
+
+type direction = 
+  | D_increasing
+  | D_decreasing
+
+let dir_of_bool is_inc = if is_inc then D_increasing else D_decreasing
+let bool_of_dir = function
+  | D_increasing -> true
+  | D_decreasing -> false
+  end
+
+(* at some point this should probably not mention bit_lifted anymore *)
+type register_value = <| 
+    rv_bits: list bit_lifted (* MSB first, smallest index number *); 
+    rv_dir: direction; 
+    rv_start: nat ;
+    rv_start_internal: nat; 
+    (*when dir is increasing, rv_start = rv_start_internal. 
+      Otherwise, tells interpreter how to reconstruct a proper decreasing value*)
+    |>
+
+type byte_lifted = Byte_lifted of list bit_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type instruction_field_value = list bit
+
+type byte = Byte of list bit (* of length 8 *)  (*MSB first everywhere*) 
+
+type address_lifted = Address_lifted of list byte_lifted (* of length 8 for 64bit machines*) * maybe integer
+(* for both values of end_flag, MSBy first *)
+
+type memory_byte = byte_lifted (* of length 8 *) (*MSB first everywhere*)
+
+type memory_value = list memory_byte
+(* the list is of length >=1 *)
+(* the head of the list is the byte stored at the lowest address;
+when calling a Sail function with a wmv effect, the least significant 8
+bits of the bit vector passed to the function will be interpreted as
+the lowest address byte; similarly, when calling a Sail function with
+rmem effect, the lowest address byte will be placed in the least
+significant 8 bits of the bit vector returned by the function; this
+behaviour is consistent with little-endian. *)
+
+
+(* not sure which of these is more handy yet *)
+type address = Address of list byte (* of length 8 *) * integer
+(* type address = Address of integer *)
+
+type opcode = Opcode of list byte (* of length 4 *)
+
+(** typeclass instantiations *)
+
+instance (EnumerationType bit)
+  let toNat = function
+    | Bitc_zero -> 0
+    | Bitc_one -> 1
+  end
+end
+
+instance (EnumerationType bit_lifted)
+  let toNat = function
+    | Bitl_zero -> 0
+    | Bitl_one -> 1
+    | Bitl_undef -> 2
+    | Bitl_unknown -> 3
+  end
+end
+
+let ~{ocaml} byte_liftedCompare (Byte_lifted b1) (Byte_lifted b2) = compare b1 b2
+let inline {ocaml} byte_liftedCompare = defaultCompare
+
+let ~{ocaml} byte_liftedLess b1 b2      = byte_liftedCompare b1 b2 =  LT
+let ~{ocaml} byte_liftedLessEq b1 b2    = byte_liftedCompare b1 b2 <> GT
+let ~{ocaml} byte_liftedGreater b1 b2   = byte_liftedCompare b1 b2 =  GT
+let ~{ocaml} byte_liftedGreaterEq b1 b2 = byte_liftedCompare b1 b2 <> LT
+
+let inline {ocaml} byte_liftedLess      = defaultLess
+let inline {ocaml} byte_liftedLessEq    = defaultLessEq
+let inline {ocaml} byte_liftedGreater   = defaultGreater
+let inline {ocaml} byte_liftedGreaterEq = defaultGreaterEq
+
+instance (Ord byte_lifted)
+  let compare = byte_liftedCompare
+  let (<)  = byte_liftedLess
+  let (<=) = byte_liftedLessEq
+  let (>)  = byte_liftedGreater
+  let (>=) = byte_liftedGreaterEq
+end
+
+let ~{ocaml} byteCompare (Byte b1) (Byte b2) = compare b1 b2
+let inline {ocaml} byteCompare = defaultCompare
+
+let ~{ocaml} byteLess b1 b2      = byteCompare b1 b2 =  LT
+let ~{ocaml} byteLessEq b1 b2    = byteCompare b1 b2 <> GT
+let ~{ocaml} byteGreater b1 b2   = byteCompare b1 b2 =  GT
+let ~{ocaml} byteGreaterEq b1 b2 = byteCompare b1 b2 <> LT
+
+let inline {ocaml} byteLess      = defaultLess
+let inline {ocaml} byteLessEq    = defaultLessEq
+let inline {ocaml} byteGreater   = defaultGreater
+let inline {ocaml} byteGreaterEq = defaultGreaterEq
+
+instance (Ord byte)
+  let compare = byteCompare
+  let (<)  = byteLess
+  let (<=) = byteLessEq
+  let (>)  = byteGreater
+  let (>=) = byteGreaterEq
+end
+
+
+
+
+
+let ~{ocaml} opcodeCompare (Opcode o1) (Opcode o2) =
+  compare o1 o2
+let {ocaml} opcodeCompare = defaultCompare
+
+let ~{ocaml} opcodeLess b1 b2      = opcodeCompare b1 b2 =  LT
+let ~{ocaml} opcodeLessEq b1 b2    = opcodeCompare b1 b2 <> GT
+let ~{ocaml} opcodeGreater b1 b2   = opcodeCompare b1 b2 =  GT
+let ~{ocaml} opcodeGreaterEq b1 b2 = opcodeCompare b1 b2 <> LT
+
+let inline {ocaml} opcodeLess      = defaultLess
+let inline {ocaml} opcodeLessEq    = defaultLessEq
+let inline {ocaml} opcodeGreater   = defaultGreater
+let inline {ocaml} opcodeGreaterEq = defaultGreaterEq
+
+instance (Ord opcode)
+  let compare = opcodeCompare
+  let (<)  = opcodeLess
+  let (<=) = opcodeLessEq
+  let (>)  = opcodeGreater
+  let (>=) = opcodeGreaterEq
+end
+
+let addressCompare (Address b1 i1) (Address b2 i2) = compare i1 i2
+(* this cannot be defaultCompare for OCaml because addresses contain big ints *)
+
+let addressLess b1 b2      = addressCompare b1 b2 =  LT
+let addressLessEq b1 b2    = addressCompare b1 b2 <> GT
+let addressGreater b1 b2   = addressCompare b1 b2 =  GT
+let addressGreaterEq b1 b2 = addressCompare b1 b2 <> LT
+
+instance (SetType address)
+  let setElemCompare = addressCompare
+end
+
+instance (Ord address)
+  let compare = addressCompare
+  let (<)  = addressLess
+  let (<=) = addressLessEq
+  let (>)  = addressGreater
+  let (>=) = addressGreaterEq
+end
+
+let {coq; ocaml} addressEqual a1 a2 = (addressCompare a1 a2) = EQ
+let inline {hol; isabelle} addressEqual = unsafe_structural_equality
+
+let {coq; ocaml} addressInequal a1 a2 = not (addressEqual a1 a2)
+let inline {hol; isabelle} addressInequal = unsafe_structural_inequality
+
+instance  (Eq address)
+  let (=)  = addressEqual
+  let (<>) = addressInequal
+end
+
+let ~{ocaml} directionCompare d1 d2 =
+  match (d1, d2) with
+  | (D_decreasing, D_increasing) -> GT
+  | (D_increasing, D_decreasing) -> LT
+  | _ -> EQ
+  end
+let inline {ocaml} directionCompare = defaultCompare
+
+let ~{ocaml} directionLess b1 b2      = directionCompare b1 b2 =  LT
+let ~{ocaml} directionLessEq b1 b2    = directionCompare b1 b2 <> GT
+let ~{ocaml} directionGreater b1 b2   = directionCompare b1 b2 =  GT
+let ~{ocaml} directionGreaterEq b1 b2 = directionCompare b1 b2 <> LT
+
+let inline {ocaml} directionLess      = defaultLess
+let inline {ocaml} directionLessEq    = defaultLessEq
+let inline {ocaml} directionGreater   = defaultGreater
+let inline {ocaml} directionGreaterEq = defaultGreaterEq
+
+instance (Ord direction)
+  let compare = directionCompare
+  let (<)  = directionLess
+  let (<=) = directionLessEq
+  let (>)  = directionGreater
+  let (>=) = directionGreaterEq
+end
+
+instance (Show direction)
+  let show = function D_increasing -> "D_increasing" | D_decreasing  -> "D_decreasing" end
+end
+
+let ~{ocaml} register_valueCompare rv1 rv2 =
+  compare (rv1.rv_bits, rv1.rv_dir, rv1.rv_start, rv1.rv_start_internal)
+          (rv2.rv_bits, rv2.rv_dir, rv2.rv_start, rv2.rv_start_internal)
+let inline {ocaml} register_valueCompare = defaultCompare
+
+let ~{ocaml} register_valueLess b1 b2      = register_valueCompare b1 b2 =  LT
+let ~{ocaml} register_valueLessEq b1 b2    = register_valueCompare b1 b2 <> GT
+let ~{ocaml} register_valueGreater b1 b2   = register_valueCompare b1 b2 =  GT
+let ~{ocaml} register_valueGreaterEq b1 b2 = register_valueCompare b1 b2 <> LT
+
+let inline {ocaml} register_valueLess      = defaultLess
+let inline {ocaml} register_valueLessEq    = defaultLessEq
+let inline {ocaml} register_valueGreater   = defaultGreater
+let inline {ocaml} register_valueGreaterEq = defaultGreaterEq
+
+instance (Ord register_value)
+  let compare = register_valueCompare
+  let (<)  = register_valueLess
+  let (<=) = register_valueLessEq
+  let (>)  = register_valueGreater
+  let (>=) = register_valueGreaterEq
+end
+
+let address_liftedCompare (Address_lifted b1 i1) (Address_lifted b2 i2) =
+  compare (i1,b1) (i2,b2)
+(* this cannot be defaultCompare for OCaml because address_lifteds contain big
+   ints *)
+
+let address_liftedLess b1 b2      = address_liftedCompare b1 b2 =  LT
+let address_liftedLessEq b1 b2    = address_liftedCompare b1 b2 <> GT
+let address_liftedGreater b1 b2   = address_liftedCompare b1 b2 =  GT
+let address_liftedGreaterEq b1 b2 = address_liftedCompare b1 b2 <> LT
+
+instance (Ord address_lifted)
+  let compare = address_liftedCompare
+  let (<)  = address_liftedLess
+  let (<=) = address_liftedLessEq
+  let (>)  = address_liftedGreater
+  let (>=) = address_liftedGreaterEq
+end
+
+(* Registers *)
+type slice = (nat * nat)
+
+type reg_name = 
+  (* do we really need this here if ppcmem already has this information by itself? *)
+| Reg of string * nat * nat * direction
+(*Name of the register, accessing the entire register, the start and size of this register, and its direction *)
+
+| Reg_slice of string * nat * direction * slice 
+(* Name of the register, accessing from the bit indexed by the first
+to the bit indexed by the second integer of the slice, inclusive. For
+machineDef* the first is a smaller number or equal to the second, adjusted
+to reflect the correct span direction in the interpreter side.  *)
+
+| Reg_field of string * nat * direction * string * slice 
+(*Name of the register, start and direction, and name of the field of the register
+accessed. The slice specifies where this field is in the register*)
+
+| Reg_f_slice of string * nat * direction * string * slice * slice 
+(* The first four components are as in Reg_field; the final slice
+specifies a part of the field, indexed w.r.t. the register as a whole *)
+
+let register_base_name : reg_name -> string = function
+  | Reg s _ _ _             -> s
+  | Reg_slice s _ _ _       -> s
+  | Reg_field s _ _ _ _     -> s
+  | Reg_f_slice s _ _ _ _ _ -> s
+  end
+
+let slice_of_reg_name : reg_name -> slice = function
+  | Reg _ start width D_increasing -> (start, start + width -1)
+  | Reg _ start width D_decreasing -> (start - width - 1, start)
+  | Reg_slice _ _ _ sl             -> sl
+  | Reg_field _ _ _ _ sl           -> sl
+  | Reg_f_slice _ _ _ _ _ sl       -> sl
+  end
+
+let width_of_reg_name (r: reg_name) : nat =
+  let width_of_slice (i, j) = (* j - i + 1 in *)
+
+    (integerFromNat j) - (integerFromNat i) + 1
+    $> abs $> natFromInteger
+  in
+  match r with
+  | Reg _ _ width _          -> width
+  | Reg_slice _ _ _ sl       -> width_of_slice sl
+  | Reg_field _ _ _ _ sl     -> width_of_slice sl
+  | Reg_f_slice _ _ _ _ _ sl -> width_of_slice sl
+  end
+
+let reg_name_non_empty_intersection (r: reg_name) (r': reg_name) : bool = 
+  register_base_name r = register_base_name r' &&
+  let (i1,  i2)  = slice_of_reg_name r in
+  let (i1', i2') = slice_of_reg_name r' in
+  i1' <= i2 && i2' >= i1
+
+let reg_nameCompare r1 r2 = 
+  compare (register_base_name r1,slice_of_reg_name r1)
+          (register_base_name r2,slice_of_reg_name r2)
+
+let reg_nameLess b1 b2      = reg_nameCompare b1 b2 =  LT
+let reg_nameLessEq b1 b2    = reg_nameCompare b1 b2 <> GT
+let reg_nameGreater b1 b2   = reg_nameCompare b1 b2 =  GT
+let reg_nameGreaterEq b1 b2 = reg_nameCompare b1 b2 <> LT
+
+instance (Ord reg_name)
+  let compare = reg_nameCompare
+  let (<)  = reg_nameLess
+  let (<=) = reg_nameLessEq
+  let (>)  = reg_nameGreater
+  let (>=) = reg_nameGreaterEq
+end
+
+let {coq;ocaml} reg_nameEqual a1 a2 = (reg_nameCompare a1 a2) = EQ
+let {hol;isabelle} reg_nameEqual = unsafe_structural_equality
+let {coq;ocaml} reg_nameInequal a1 a2 = not (reg_nameEqual a1 a2)
+let {hol;isabelle} reg_nameInequal = unsafe_structural_inequality
+
+instance (Eq reg_name)
+  let (=)  = reg_nameEqual
+  let (<>) = reg_nameInequal
+end
+
+instance (SetType reg_name)
+  let setElemCompare = reg_nameCompare
+end
+
+let direction_of_reg_name r = match r with
+  | Reg _ _ _ d -> d
+  | Reg_slice _ _ d _ -> d
+  | Reg_field _ _ d _ _ -> d
+  | Reg_f_slice _ _ d _ _ _ -> d
+ end
+
+let start_of_reg_name r = match r with
+  | Reg _ start _ _ -> start
+  | Reg_slice _ start _ _ -> start
+  | Reg_field _ start _ _ _ -> start
+  | Reg_f_slice _ start _ _ _ _ -> start
+end
+
+(* Data structures for building up instructions *)
+
+(* read_kind, write_kind, barrier_kind, trans_kind and instruction_kind have
+   been moved to sail_instr_kinds.lem.  This removes the dependency of the
+   shallow embedding on the rest of sail_impl_base.lem, and helps avoid name
+   clashes between the different monad types. *)
+
+type event = 
+  | E_read_mem of read_kind * address_lifted * nat * maybe (list reg_name)
+  | E_read_memt of read_kind * address_lifted * nat * maybe (list reg_name)
+  | E_write_mem of write_kind * address_lifted * nat * maybe (list reg_name) * memory_value * maybe (list reg_name)
+  | E_write_ea of write_kind * address_lifted * nat * maybe (list reg_name)
+  | E_excl_res
+  | E_write_memv of maybe address_lifted * memory_value * maybe (list reg_name)
+  | E_write_memvt of maybe address_lifted * (bit_lifted * memory_value) * maybe (list reg_name)
+  | E_barrier of barrier_kind
+  | E_footprint 
+  | E_read_reg of reg_name
+  | E_write_reg of reg_name * register_value
+  | E_escape
+  | E_error of string 
+
+
+let eventCompare e1 e2 = 
+  match (e1,e2) with
+  | (E_read_mem rk1 v1 i1 tr1, E_read_mem rk2 v2 i2 tr2) ->
+     compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) 
+  | (E_read_memt rk1 v1 i1 tr1, E_read_memt rk2 v2 i2 tr2) ->
+     compare (rk1, (v1,i1,tr1)) (rk2,(v2, i2, tr2)) 
+  | (E_write_mem wk1 v1 i1 tr1 v1' tr1', E_write_mem wk2 v2 i2 tr2 v2' tr2') -> 
+    compare ((wk1,v1,i1),(tr1,v1',tr1'))  ((wk2,v2,i2),(tr2,v2',tr2')) 
+  | (E_write_ea wk1 a1 i1 tr1, E_write_ea wk2 a2 i2 tr2) ->
+    compare (wk1, (a1, i1, tr1)) (wk2, (a2, i2, tr2))
+  | (E_excl_res, E_excl_res) -> EQ
+  | (E_write_memv _ mv1 tr1, E_write_memv _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+  | (E_write_memvt _ mv1 tr1, E_write_memvt _ mv2 tr2) -> compare (mv1,tr1) (mv2,tr2)
+  | (E_barrier bk1, E_barrier bk2) -> compare bk1 bk2
+  | (E_read_reg r1, E_read_reg r2) -> compare r1 r2
+  | (E_write_reg r1 v1, E_write_reg r2 v2) -> compare (r1,v1) (r2,v2)
+  | (E_error s1, E_error s2) -> compare s1 s2
+  | (E_escape,E_escape) -> EQ
+  | (E_read_mem _ _ _ _, _) -> LT
+  | (E_write_mem _ _ _ _ _ _, _) -> LT
+  | (E_write_ea _ _ _ _, _) -> LT
+  | (E_excl_res, _) -> LT
+  | (E_write_memv _ _ _, _) -> LT
+  | (E_barrier _, _) -> LT
+  | (E_read_reg _, _) -> LT
+  | (E_write_reg _ _, _) -> LT
+  | _ -> GT
+  end
+
+let eventLess b1 b2      = eventCompare b1 b2 =  LT
+let eventLessEq b1 b2    = eventCompare b1 b2 <> GT
+let eventGreater b1 b2   = eventCompare b1 b2 =  GT
+let eventGreaterEq b1 b2 = eventCompare b1 b2 <> LT
+
+instance (Ord event)
+  let compare = eventCompare
+  let (<)  = eventLess
+  let (<=) = eventLessEq
+  let (>)  = eventGreater
+  let (>=) = eventGreaterEq
+end
+
+instance (SetType event)
+  let setElemCompare = compare
+end
+
+
+(* the address_lifted types should go away here and be replaced by address *)
+type with_aux 'o = 'o * maybe ((unit -> (string * string)) * ((list (reg_name * register_value)) -> list event))
+type outcome 'a 'e =
+  (* Request to read memory, value is location to read, integer is size to read,
+     followed by registers that were used in computing that size *)
+  | Read_mem of (read_kind * address_lifted * nat) * (memory_value -> with_aux (outcome 'a 'e))
+  (* Tell the system a write is imminent, at address lifted, of size nat *)
+  | Write_ea of (write_kind * address_lifted * nat) * (with_aux (outcome 'a 'e))
+  (* Request the result of store-exclusive *)
+  | Excl_res of (bool -> with_aux (outcome 'a 'e))
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal *)
+  | Write_memv of memory_value * (bool -> with_aux (outcome 'a 'e))
+  (* Request a memory barrier *)
+  | Barrier of barrier_kind * with_aux (outcome 'a 'e)
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | Footprint of with_aux (outcome 'a 'e)
+  (* Request to read register, will track dependency when mode.track_values *)
+  | Read_reg of reg_name * (register_value -> with_aux (outcome 'a 'e))
+  (* Request to write register *)
+  | Write_reg of (reg_name * register_value) * with_aux (outcome 'a 'e)
+  | Escape of maybe string
+  (*Result of a failed assert with possible error message to report*)
+  | Fail of maybe string
+  (* Exception of type 'e *)
+  | Exception of 'e
+  | Internal of (maybe string * maybe (unit -> string)) * with_aux (outcome 'a 'e)
+  | Done of 'a
+  | Error of string
+
+type outcome_s 'a 'e = with_aux (outcome 'a 'e)
+(* first string : output of instruction_stack_to_string
+   second string: output of local_variables_to_string *)
+
+(** operations and coercions on basic values *)
+
+val word8_to_bitls : word8 -> list bit_lifted
+val bitls_to_word8 : list bit_lifted -> word8
+
+val integer_of_word8_list : list word8 -> integer
+val word8_list_of_integer : integer -> integer -> list word8 
+
+val concretizable_bitl : bit_lifted -> bool
+val concretizable_bytl : byte_lifted -> bool
+val concretizable_bytls : list byte_lifted -> bool
+
+let concretizable_bitl = function
+  | Bitl_zero -> true
+  | Bitl_one -> true
+  | Bitl_undef -> false
+  | Bitl_unknown -> false
+end 
+
+let concretizable_bytl (Byte_lifted bs) = List.all concretizable_bitl bs
+let concretizable_bytls = List.all concretizable_bytl
+
+(* constructing values *)
+
+val build_register_value : list bit_lifted -> direction -> nat -> nat -> register_value
+let build_register_value bs dir width start_index =
+  <| rv_bits = bs;
+     rv_dir = dir; (* D_increasing for Power, D_decreasing for ARM *)
+     rv_start_internal = start_index; 
+     rv_start = if dir = D_increasing
+       then start_index
+       else (start_index+1) - width; (* Smaller index, as in Power, for external interaction *)
+  |>
+
+val register_value : bit_lifted -> direction -> nat -> nat -> register_value
+let register_value b dir width start_index = 
+  build_register_value (List.replicate width b) dir width start_index
+
+val register_value_zeros : direction -> nat -> nat -> register_value
+let register_value_zeros dir width start_index = 
+  register_value Bitl_zero dir width start_index
+
+val register_value_ones : direction -> nat -> nat -> register_value
+let register_value_ones dir width start_index = 
+  register_value Bitl_one dir width start_index
+
+val register_value_for_reg : reg_name -> list bit_lifted -> register_value
+let register_value_for_reg r bs : register_value =
+  let () = ensure (width_of_reg_name r = List.length bs)
+      ("register_value_for_reg (\"" ^ show (register_base_name r) ^ "\") length mismatch: "
+          ^ show (width_of_reg_name r) ^ " vs " ^ show (List.length bs))
+  in
+  let (j1, j2) = slice_of_reg_name r in
+  let d = direction_of_reg_name r in
+  <|  rv_bits = bs;
+      rv_dir = d;
+      rv_start_internal = if d = D_increasing then j1 else (start_of_reg_name r) - j1;
+      rv_start = j1;
+  |>
+
+val byte_lifted_undef : byte_lifted
+let byte_lifted_undef = Byte_lifted (List.replicate 8 Bitl_undef)
+
+val byte_lifted_unknown : byte_lifted
+let byte_lifted_unknown = Byte_lifted (List.replicate 8 Bitl_unknown)
+  
+val memory_value_unknown : nat (*the number of bytes*) -> memory_value
+let memory_value_unknown (width:nat) : memory_value = 
+  List.replicate width byte_lifted_unknown 
+
+val memory_value_undef : nat (*the number of bytes*) -> memory_value
+let memory_value_undef (width:nat) : memory_value = 
+  List.replicate width byte_lifted_undef 
+
+val match_endianness : forall 'a. end_flag -> list 'a -> list 'a
+let match_endianness endian l =
+  match endian with
+  | E_little_endian -> List.reverse l
+  | E_big_endian    -> l
+  end
+
+(* lengths *)  
+
+val memory_value_length : memory_value -> nat
+let memory_value_length (mv:memory_value) = List.length mv
+
+
+(* aux fns *)
+
+val maybe_all : forall 'a.  list (maybe 'a) -> maybe (list 'a)
+let rec maybe_all' xs acc = 
+  match xs with
+  | [] -> Just (List.reverse acc)
+  | Nothing :: _ -> Nothing
+  | (Just y)::xs' -> maybe_all' xs' (y::acc)
+  end
+let maybe_all xs = maybe_all' xs [] 
+
+(** coercions *)
+
+(* bits and bytes *)
+
+let bit_to_bool = function (* TODO: rename bool_of_bit *)
+  | Bitc_zero -> false
+  | Bitc_one -> true
+end
+
+
+val bit_lifted_of_bit : bit -> bit_lifted
+let bit_lifted_of_bit b = 
+  match b with
+  | Bitc_zero -> Bitl_zero
+  | Bitc_one -> Bitl_one
+  end
+
+val bit_of_bit_lifted : bit_lifted -> maybe bit
+let bit_of_bit_lifted bl =
+  match bl with
+  | Bitl_zero -> Just Bitc_zero
+  | Bitl_one -> Just Bitc_one
+  | Bitl_undef -> Nothing
+  | Bitl_unknown -> Nothing
+  end
+
+
+val byte_lifted_of_byte : byte -> byte_lifted
+let byte_lifted_of_byte (Byte bs) : byte_lifted = Byte_lifted (List.map bit_lifted_of_bit bs)
+
+val byte_of_byte_lifted : byte_lifted -> maybe byte
+let byte_of_byte_lifted bl = 
+  match bl with
+  | Byte_lifted bls -> 
+      match maybe_all (List.map bit_of_bit_lifted bls) with
+      | Nothing -> Nothing
+      | Just bs -> Just (Byte bs)
+      end
+  end
+
+
+val bytes_of_bits : list bit -> list byte (*assumes (length bits) mod 8 = 0*)
+let rec bytes_of_bits bits = match bits with
+  | [] -> []
+  | b0::b1::b2::b3::b4::b5::b6::b7::bits -> 
+    (Byte [b0;b1;b2;b3;b4;b5;b6;b7])::(bytes_of_bits bits)
+  | _ -> failwith "bytes_of_bits not given bits divisible by 8"
+end
+
+val byte_lifteds_of_bit_lifteds : list bit_lifted -> list byte_lifted (*assumes (length bits) mod 8 = 0*)
+let rec byte_lifteds_of_bit_lifteds bits = match bits with
+  | [] -> []
+  | b0::b1::b2::b3::b4::b5::b6::b7::bits -> 
+    (Byte_lifted [b0;b1;b2;b3;b4;b5;b6;b7])::(byte_lifteds_of_bit_lifteds bits)
+  | _ -> failwith "byte_lifteds of bit_lifteds not given bits divisible by 8"
+end
+
+
+val byte_of_memory_byte : memory_byte -> maybe byte
+let byte_of_memory_byte = byte_of_byte_lifted
+
+val memory_byte_of_byte : byte -> memory_byte
+let memory_byte_of_byte = byte_lifted_of_byte
+
+
+(* to and from nat *)
+
+(* this natFromBoolList could move to the Lem word.lem library *)
+val natFromBoolList : list bool -> nat
+let rec natFromBoolListAux (acc : nat) (bl : list bool) = 
+  match bl with 
+    | [] -> acc
+    | (true :: bl') -> natFromBoolListAux ((acc * 2) + 1) bl'
+    | (false :: bl') -> natFromBoolListAux (acc * 2) bl'
+  end
+let natFromBoolList bl = 
+  natFromBoolListAux 0 (List.reverse bl)
+
+
+val nat_of_bit_list : list bit -> nat 
+let nat_of_bit_list b =
+  natFromBoolList (List.reverse (List.map bit_to_bool b))
+  (* natFromBoolList takes a list with LSB first, for consistency with rest of Lem word library, so we reverse it. twice. *)
+
+
+(* to and from integer *)
+
+val integer_of_bit_list : list bit -> integer 
+let integer_of_bit_list b =
+  integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+  (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+
+val bit_list_of_integer : nat -> integer -> list bit 
+let bit_list_of_integer len b = 
+  List.map (fun b -> if b then Bitc_one else Bitc_zero) 
+    (reverse (boolListFrombitSeq len (bitSeqFromInteger Nothing b)))
+
+val integer_of_byte_list : list byte -> integer 
+let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes)
+
+val byte_list_of_integer : nat -> integer -> list byte 
+let byte_list_of_integer (len:nat) (a:integer):list byte = 
+  let bits = bit_list_of_integer (len * 8) a in bytes_of_bits bits
+
+
+val integer_of_address : address -> integer 
+let integer_of_address (a:address):integer = 
+  match a with
+  | Address bs i -> i 
+  end
+
+val address_of_integer : integer -> address 
+let address_of_integer (i:integer):address =
+  Address (byte_list_of_integer 8 i) i
+
+(* to and from signed-integer *)
+
+val signed_integer_of_bit_list : list bit -> integer
+let signed_integer_of_bit_list b =
+  match b with
+  | [] -> failwith "empty bit list"
+  | Bitc_zero :: b' ->
+      integerFromBoolList (false,(List.reverse (List.map bit_to_bool b)))
+  | Bitc_one :: b' ->
+      let b'_val = integerFromBoolList (false,(List.reverse (List.map bit_to_bool b'))) in
+      (* integerFromBoolList takes a list with LSB first, so we reverse it *)
+      let msb_val = integerPow 2 ((List.length b) - 1) in
+      b'_val - msb_val
+  end
+
+
+(* regarding a list of int as a list of bytes in memory, MSB lowest-address first, convert to an integer *)
+val integer_address_of_int_list : list int -> integer
+let rec integerFromIntListAux (acc: integer) (is: list int) = 
+  match is with 
+  | [] -> acc
+  | (i :: is') -> integerFromIntListAux ((acc * 256) + integerFromInt i) is'
+  end
+let integer_address_of_int_list (is: list int) =
+  integerFromIntListAux 0 is
+
+val address_of_byte_list : list byte -> address 
+let address_of_byte_list bs = 
+  if List.length bs <> 8 then failwith "address_of_byte_list given list not of length 8" else 
+  Address bs (integer_of_byte_list bs)
+
+let address_of_byte_lifted_list bls =
+  match maybe_all (List.map byte_of_byte_lifted bls) with
+  | Nothing -> Nothing
+  | Just bs -> Just (address_of_byte_list bs)
+  end
+
+(* operations on addresses *)
+
+val add_address_nat : address -> nat -> address 
+let add_address_nat (a:address) (i:nat) : address = 
+  address_of_integer ((integer_of_address a) + (integerFromNat i))
+
+val clear_low_order_bits_of_address : address -> address 
+let clear_low_order_bits_of_address a = 
+  match a with 
+  | Address [b0;b1;b2;b3;b4;b5;b6;b7] i -> 
+      match b7 with
+      | Byte [bt0;bt1;bt2;bt3;bt4;bt5;bt6;bt7] -> 
+          let b7' = Byte [bt0;bt1;bt2;bt3;bt4;bt5;Bitc_zero;Bitc_zero] in
+	  let bytes = [b0;b1;b2;b3;b4;b5;b6;b7'] in
+          Address bytes (integer_of_byte_list bytes)
+      | _ -> failwith "Byte does not contain 8 bits"
+      end
+  | _ -> failwith "Address does not contain 8 bytes"
+  end
+
+
+
+val byte_list_of_memory_value : end_flag -> memory_value -> maybe (list byte)
+let byte_list_of_memory_value endian mv =
+  match_endianness endian mv
+  $> List.map byte_of_memory_byte
+  $> maybe_all
+
+
+val integer_of_memory_value : end_flag -> memory_value -> maybe integer
+let integer_of_memory_value endian (mv:memory_value):maybe integer =
+  match byte_list_of_memory_value endian mv with
+  | Just bs -> Just (integer_of_byte_list bs)
+  | Nothing -> Nothing 
+  end
+
+val memory_value_of_integer : end_flag  -> nat -> integer -> memory_value
+let memory_value_of_integer endian (len:nat) (i:integer):memory_value =
+  List.map byte_lifted_of_byte (byte_list_of_integer len i)
+  $> match_endianness endian
+
+
+val integer_of_register_value : register_value -> maybe integer 
+let integer_of_register_value (rv:register_value):maybe integer = 
+  match maybe_all (List.map bit_of_bit_lifted rv.rv_bits) with
+  | Nothing -> Nothing
+  | Just bs -> Just (integer_of_bit_list bs)
+  end
+
+(* NOTE: register_value_for_reg_of_integer might be easier to use *)
+val register_value_of_integer : nat -> nat -> direction -> integer -> register_value 
+let register_value_of_integer (len:nat) (start:nat) (dir:direction) (i:integer):register_value =
+  let bs = bit_list_of_integer len i in
+  build_register_value (List.map bit_lifted_of_bit bs) dir len start
+
+val register_value_for_reg_of_integer : reg_name -> integer -> register_value
+let register_value_for_reg_of_integer (r: reg_name) (i:integer) : register_value =
+  register_value_of_integer (width_of_reg_name r) (start_of_reg_name r) (direction_of_reg_name r) i
+
+(* *)
+
+val opcode_of_bytes : byte -> byte -> byte -> byte -> opcode
+let opcode_of_bytes b0 b1 b2 b3 : opcode = Opcode [b0;b1;b2;b3]
+
+val register_value_of_address : address -> direction -> register_value   
+let register_value_of_address (Address bytes _) dir : register_value = 
+  let bits = List.concatMap (fun (Byte bs) -> List.map bit_lifted_of_bit bs) bytes in
+   <| rv_bits = bits;
+      rv_dir = dir;
+      rv_start = 0; 
+      rv_start_internal = if dir = D_increasing then 0 else (List.length bits) - 1
+   |>
+
+val register_value_of_memory_value : memory_value -> direction -> register_value
+let register_value_of_memory_value bytes dir : register_value =
+  let bitls = List.concatMap (fun (Byte_lifted bs) -> bs) bytes in
+  <| rv_bits = bitls;
+     rv_dir = dir;
+     rv_start = 0;
+     rv_start_internal = if dir = D_increasing then 0 else (List.length bitls) - 1
+   |>                                                     
+
+val memory_value_of_register_value: register_value -> memory_value
+let memory_value_of_register_value r =
+  (byte_lifteds_of_bit_lifteds r.rv_bits)
+   
+val address_lifted_of_register_value : register_value -> maybe address_lifted
+(* returning Nothing iff the register value is not 64 bits wide, but
+allowing Bitl_undef and Bitl_unknown *)
+let address_lifted_of_register_value (rv:register_value) : maybe address_lifted = 
+  if List.length rv.rv_bits <> 64 then Nothing
+  else 
+    Just (Address_lifted (byte_lifteds_of_bit_lifteds rv.rv_bits)
+                         (if List.all concretizable_bitl rv.rv_bits 
+			  then match (maybe_all (List.map bit_of_bit_lifted rv.rv_bits)) with
+                              | (Just(bits)) -> Just (integer_of_bit_list bits)
+                              | Nothing -> Nothing end
+			  else Nothing))
+
+val address_of_address_lifted : address_lifted -> maybe address
+(* returning Nothing iff the address contains any Bitl_undef or Bitl_unknown *)
+let address_of_address_lifted (al:address_lifted): maybe address =
+  match al with
+  | Address_lifted bls (Just i)-> 
+      match maybe_all ((List.map byte_of_byte_lifted) bls) with
+      | Nothing -> Nothing
+      | Just bs -> Just (Address bs i)
+      end
+  | _ -> Nothing
+end
+
+val address_of_register_value : register_value -> maybe address
+(* returning Nothing iff the register value is not 64 bits wide, or contains Bitl_undef or Bitl_unknown *)
+let address_of_register_value (rv:register_value) : maybe address = 
+  match address_lifted_of_register_value rv with
+  | Nothing -> Nothing
+  | Just al -> 
+      match address_of_address_lifted al with
+      | Nothing -> Nothing
+      | Just a -> Just a
+      end
+  end
+
+let address_of_memory_value (endian: end_flag) (mv:memory_value) : maybe address =
+  match byte_list_of_memory_value endian mv with
+  | Nothing -> Nothing
+  | Just bs -> 
+      if List.length bs <> 8 then Nothing else
+      Just (address_of_byte_list bs)
+  end 
+
+val byte_of_int : int -> byte
+let byte_of_int (i:int) : byte = 
+  Byte (bit_list_of_integer 8 (integerFromInt i))
+
+val memory_byte_of_int : int -> memory_byte
+let memory_byte_of_int (i:int) : memory_byte = 
+  memory_byte_of_byte (byte_of_int i)
+
+(*
+val int_of_memory_byte : int -> maybe memory_byte
+let int_of_memory_byte (mb:memory_byte) : int = 
+  failwith "TODO"
+*)
+
+
+
+val memory_value_of_address_lifted : end_flag -> address_lifted -> memory_value
+let memory_value_of_address_lifted endian (Address_lifted bs _ :address_lifted) =
+  match_endianness endian bs
+
+val byte_list_of_address : address -> list byte
+let byte_list_of_address (Address bs _) : list byte = bs
+
+val memory_value_of_address : end_flag -> address -> memory_value
+let memory_value_of_address endian (Address bs _) =
+  match_endianness endian bs
+  $> List.map byte_lifted_of_byte
+
+val byte_list_of_opcode : opcode -> list byte
+let byte_list_of_opcode (Opcode bs) : list byte = bs
+
+(** ****************************************** *)
+(** show type class instantiations             *)
+(** ****************************************** *)
+
+(* matching printing_functions.ml *)
+val stringFromReg_name : reg_name -> string
+let stringFromReg_name r =
+  let norm_sl start dir (first,second) = (first,second)
+    (* match dir with
+      | D_increasing -> (first,second)
+      | D_decreasing -> (start - first, start - second)
+    end *)
+  in
+  match r with
+  | Reg s start size dir -> s
+  | Reg_slice s start dir sl ->
+      let (first,second) = norm_sl start dir sl in
+      s ^ "[" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+  | Reg_field s start dir f sl ->
+      let (first,second) = norm_sl start dir sl in
+      s ^ "." ^ f ^ " (" ^ (show start) ^ ", " ^ (show dir) ^ ", " ^ (show first) ^ ", " ^ (show second) ^ ")"
+  | Reg_f_slice s start dir f (first1,second1) (first,second) ->
+      let (first,second) =
+        match dir with
+        | D_increasing -> (first,second)
+        | D_decreasing -> (start - first, start - second)
+        end in
+      s ^ "." ^ f ^ "]" ^ show first ^ (if (first = second) then "" else ".." ^ (show second)) ^ "]"
+  end
+
+instance (Show reg_name)
+  let show = stringFromReg_name
+end
+
+
+(* hex pp of integers, adapting the Lem string_extra.lem code *)
+val stringFromNaturalHexHelper : natural -> list char -> list char
+let rec stringFromNaturalHexHelper n acc =
+  if n = 0 then
+    acc
+  else
+    stringFromNaturalHexHelper (n / 16) (String_extra.chr (natFromNatural (let nd = n mod 16 in if nd <=9 then nd + 48 else nd - 10 + 97)) :: acc)
+
+val stringFromNaturalHex : natural -> string
+let (*~{ocaml;hol}*) stringFromNaturalHex n = 
+  if n = 0 then "0" else toString (stringFromNaturalHexHelper n [])
+
+val stringFromIntegerHex : integer -> string
+let (*~{ocaml}*) stringFromIntegerHex i = 
+  if i < 0 then 
+    "-" ^ stringFromNaturalHex (naturalFromInteger i)
+  else
+    stringFromNaturalHex (naturalFromInteger i)
+
+
+let stringFromAddress (Address bs i) = 
+  let i' = integer_of_byte_list bs in
+  if i=i' then
+(*TODO: ideally this should be made to match the src/pp.ml pp_address; the following very roughly matches what's used in the ppcmem UI, enough to make exceptions readable *)
+    if i < 65535 then 
+      show i 
+    else
+      stringFromIntegerHex i
+  else
+    "stringFromAddress bytes and integer mismatch"
+
+instance (Show address)
+  let show = stringFromAddress
+end
+
+let stringFromByte_lifted bl =
+  match byte_of_byte_lifted bl with
+  | Nothing -> "u?"  
+  | Just (Byte bits) -> 
+      let i = integer_of_bit_list bits in
+      show i
+  end
+
+instance (Show byte_lifted)
+  let show = stringFromByte_lifted
+end
+
+(* possible next instruction address options *)
+type nia = 
+  | NIA_successor
+  | NIA_concrete_address of address
+  | NIA_indirect_address
+
+let niaCompare n1 n2 = match (n1,n2) with
+  | (NIA_successor, NIA_successor) -> EQ
+  | (NIA_successor, _) -> LT
+  | (_, NIA_successor) -> GT
+  | (NIA_concrete_address a1, NIA_concrete_address a2) -> compare a1 a2
+  | (NIA_concrete_address _, _) -> LT
+  | (_, NIA_concrete_address _) -> GT
+  | (NIA_indirect_address, NIA_indirect_address) -> EQ
+  (* | (NIA_indirect_address, _) -> LT
+  | (_, NIA_indirect_address) -> GT *)
+  end
+
+instance (Ord nia)
+  let compare = niaCompare
+  let (<)  n1 n2 = (niaCompare n1 n2) = LT
+  let (<=) n1 n2 = (niaCompare n1 n2) <> GT
+  let (>)  n1 n2 = (niaCompare n1 n2) = GT
+  let (>=) n1 n2 = (niaCompare n1 n2) <> LT
+end
+
+let stringFromNia = function
+  | NIA_successor          -> "NIA_successor"
+  | NIA_concrete_address a -> "NIA_concrete_address " ^ show a
+  | NIA_indirect_address   -> "NIA_indirect_address"
+end
+
+instance (Show nia)
+  let show = stringFromNia
+end
+
+type dia =
+  | DIA_none
+  | DIA_concrete_address of address
+  | DIA_register of reg_name
+
+let diaCompare d1 d2 = match (d1, d2) with
+  | (DIA_none, DIA_none) -> EQ
+  | (DIA_none, _) -> LT
+  | (DIA_concrete_address a1, DIA_none) -> GT
+  | (DIA_concrete_address a1, DIA_concrete_address a2) -> compare a1 a2
+  | (DIA_concrete_address a1, _) -> LT
+  | (DIA_register r1, DIA_register r2) -> compare r1 r2
+  | (DIA_register _, _) -> GT
+end
+
+instance (Ord dia)
+  let compare = diaCompare
+  let (<)  n1 n2 = (diaCompare n1 n2) = LT
+  let (<=) n1 n2 = (diaCompare n1 n2) <> GT
+  let (>)  n1 n2 = (diaCompare n1 n2) = GT
+  let (>=) n1 n2 = (diaCompare n1 n2) <> LT
+end
+
+let stringFromDia = function
+  | DIA_none               ->  "DIA_none"
+  | DIA_concrete_address a ->  "DIA_concrete_address " ^ show a
+  | DIA_register r ->  "DIA_delayed_register " ^ show r
+end
+
+instance (Show dia)
+  let show = stringFromDia
+end
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_instr_kinds.v b/snapshots/coq/lib/coq/Sail2_instr_kinds.v
new file mode 100644
index 00000000..0145d8b3
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_instr_kinds.v
@@ -0,0 +1,253 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+
+(*
+
+class ( EnumerationType 'a )
+  val toNat : 'a -> nat
+end
+
+
+val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering
+let ~{ocaml} enumeration_typeCompare e1 e2 :=
+  compare (toNat e1) (toNat e2)
+let inline {ocaml} enumeration_typeCompare := defaultCompare
+
+
+default_instance forall 'a. EnumerationType 'a => (Ord 'a)
+  let compare := enumeration_typeCompare
+  let (<)  r1 r2 := (enumeration_typeCompare r1 r2) = LT
+  let (<=) r1 r2 := (enumeration_typeCompare r1 r2) <> GT
+  let (>)  r1 r2 := (enumeration_typeCompare r1 r2) = GT
+  let (>=) r1 r2 := (enumeration_typeCompare r1 r2) <> LT
+end
+*)
+
+(* Data structures for building up instructions *)
+
+(* careful: changes in the read/write/barrier kinds have to be
+   reflected in deep_shallow_convert *)
+Inductive read_kind :=
+  (* common reads *)
+  | Read_plain
+  (* Power reads *)
+  | Read_reserve
+  (* AArch64 reads *)
+  | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream
+  (* RISC-V reads *)
+  | Read_RISCV_acquire  | Read_RISCV_strong_acquire
+  | Read_RISCV_reserved | Read_RISCV_reserved_acquire
+  | Read_RISCV_reserved_strong_acquire
+  (* x86 reads *)
+  | Read_X86_locked (* the read part of a lock'd instruction (rmw) *)
+.
+(*
+instance (Show read_kind)
+  let show := function
+    | Read_plain -> "Read_plain"
+    | Read_reserve -> "Read_reserve"
+    | Read_acquire -> "Read_acquire"
+    | Read_exclusive -> "Read_exclusive"
+    | Read_exclusive_acquire -> "Read_exclusive_acquire"
+    | Read_stream -> "Read_stream"
+    | Read_RISCV_acquire -> "Read_RISCV_acquire"
+    | Read_RISCV_strong_acquire -> "Read_RISCV_strong_acquire"
+    | Read_RISCV_reserved -> "Read_RISCV_reserved"
+    | Read_RISCV_reserved_acquire -> "Read_RISCV_reserved_acquire"
+    | Read_RISCV_reserved_strong_acquire -> "Read_RISCV_reserved_strong_acquire"
+    | Read_X86_locked -> "Read_X86_locked"
+  end
+end
+*)
+Inductive write_kind :=
+  (* common writes *)
+  | Write_plain
+  (* Power writes *)
+  | Write_conditional
+  (* AArch64 writes *)
+  | Write_release | Write_exclusive | Write_exclusive_release
+  (* RISC-V *)
+  | Write_RISCV_release     | Write_RISCV_strong_release
+  | Write_RISCV_conditional | Write_RISCV_conditional_release
+  | Write_RISCV_conditional_strong_release
+  (* x86 writes *)
+  | Write_X86_locked (* the write part of a lock'd instruction (rmw) *)
+.
+(*
+instance (Show write_kind)
+  let show := function
+    | Write_plain -> "Write_plain"
+    | Write_conditional -> "Write_conditional"
+    | Write_release -> "Write_release"
+    | Write_exclusive -> "Write_exclusive"
+    | Write_exclusive_release -> "Write_exclusive_release"
+    | Write_RISCV_release -> "Write_RISCV_release"
+    | Write_RISCV_strong_release -> "Write_RISCV_strong_release"
+    | Write_RISCV_conditional -> "Write_RISCV_conditional"
+    | Write_RISCV_conditional_release -> "Write_RISCV_conditional_release"
+    | Write_RISCV_conditional_strong_release -> "Write_RISCV_conditional_strong_release"
+    | Write_X86_locked -> "Write_X86_locked"
+  end
+end
+*)
+Inductive barrier_kind :=
+  (* Power barriers *)
+  Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync
+  (* AArch64 barriers *)
+  | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB
+  | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB
+  | Barrier_TM_COMMIT
+  (* MIPS barriers *)
+  | Barrier_MIPS_SYNC
+  (* RISC-V barriers *)
+  | Barrier_RISCV_rw_rw
+  | Barrier_RISCV_r_rw
+  | Barrier_RISCV_r_r
+  | Barrier_RISCV_rw_w
+  | Barrier_RISCV_w_w
+  | Barrier_RISCV_i
+  (* X86 *)
+  | Barrier_x86_MFENCE.
+
+(*
+instance (Show barrier_kind)
+  let show := function
+    | Barrier_Sync -> "Barrier_Sync"
+    | Barrier_LwSync -> "Barrier_LwSync"
+    | Barrier_Eieio -> "Barrier_Eieio"
+    | Barrier_Isync -> "Barrier_Isync"
+    | Barrier_DMB -> "Barrier_DMB"
+    | Barrier_DMB_ST -> "Barrier_DMB_ST"
+    | Barrier_DMB_LD -> "Barrier_DMB_LD"
+    | Barrier_DSB -> "Barrier_DSB"
+    | Barrier_DSB_ST -> "Barrier_DSB_ST"
+    | Barrier_DSB_LD -> "Barrier_DSB_LD"
+    | Barrier_ISB -> "Barrier_ISB"
+    | Barrier_TM_COMMIT -> "Barrier_TM_COMMIT"
+    | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC"
+    | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw"
+    | Barrier_RISCV_r_rw  -> "Barrier_RISCV_r_rw"
+    | Barrier_RISCV_r_r   -> "Barrier_RISCV_r_r"
+    | Barrier_RISCV_rw_w  -> "Barrier_RISCV_rw_w"
+    | Barrier_RISCV_w_w   -> "Barrier_RISCV_w_w"
+    | Barrier_RISCV_i     -> "Barrier_RISCV_i"
+    | Barrier_x86_MFENCE  -> "Barrier_x86_MFENCE"
+  end
+end*)
+
+Inductive trans_kind :=
+  (* AArch64 *)
+  | Transaction_start | Transaction_commit | Transaction_abort.
+(*
+instance (Show trans_kind)
+  let show := function
+  | Transaction_start  -> "Transaction_start"
+  | Transaction_commit -> "Transaction_commit"
+  | Transaction_abort  -> "Transaction_abort"
+  end
+end*)
+
+Inductive instruction_kind :=
+  | IK_barrier   : barrier_kind -> instruction_kind
+  | IK_mem_read  : read_kind -> instruction_kind
+  | IK_mem_write : write_kind -> instruction_kind
+  | IK_mem_rmw   : (read_kind * write_kind) -> instruction_kind
+  | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address),
+  indirect/computed-branch (single nia of kind NIA_indirect_address)
+  and branch/jump (single nia of kind NIA_concrete_address) *)
+  | IK_trans     : trans_kind -> instruction_kind
+  | IK_simple    : instruction_kind.
+
+(*
+instance (Show instruction_kind)
+  let show := function
+    | IK_barrier barrier_kind -> "IK_barrier " ^ (show barrier_kind)
+    | IK_mem_read read_kind   -> "IK_mem_read " ^ (show read_kind)
+    | IK_mem_write write_kind -> "IK_mem_write " ^ (show write_kind)
+    | IK_mem_rmw (r, w)       -> "IK_mem_rmw " ^ (show r) ^ " " ^ (show w)
+    | IK_branch               -> "IK_branch"
+    | IK_trans trans_kind     -> "IK_trans " ^ (show trans_kind)
+    | IK_simple               -> "IK_simple"
+  end
+end
+*)
+
+Definition read_is_exclusive r :=
+match r with
+  | Read_plain => false
+  | Read_reserve => true
+  | Read_acquire => false
+  | Read_exclusive => true
+  | Read_exclusive_acquire => true
+  | Read_stream => false
+  | Read_RISCV_acquire => false
+  | Read_RISCV_strong_acquire => false
+  | Read_RISCV_reserved => true
+  | Read_RISCV_reserved_acquire => true
+  | Read_RISCV_reserved_strong_acquire => true
+  | Read_X86_locked => true
+end.
+
+
+(*
+instance (EnumerationType read_kind)
+  let toNat := function
+    | Read_plain -> 0
+    | Read_reserve -> 1
+    | Read_acquire -> 2
+    | Read_exclusive -> 3
+    | Read_exclusive_acquire -> 4
+    | Read_stream -> 5
+    | Read_RISCV_acquire -> 6
+    | Read_RISCV_strong_acquire -> 7
+    | Read_RISCV_reserved -> 8
+    | Read_RISCV_reserved_acquire -> 9
+    | Read_RISCV_reserved_strong_acquire -> 10
+    | Read_X86_locked -> 11
+  end
+end
+
+instance (EnumerationType write_kind)
+  let toNat := function
+    | Write_plain -> 0
+    | Write_conditional -> 1
+    | Write_release -> 2
+    | Write_exclusive -> 3
+    | Write_exclusive_release -> 4
+    | Write_RISCV_release -> 5
+    | Write_RISCV_strong_release -> 6
+    | Write_RISCV_conditional -> 7
+    | Write_RISCV_conditional_release -> 8
+    | Write_RISCV_conditional_strong_release -> 9
+    | Write_X86_locked -> 10
+  end
+end
+
+instance (EnumerationType barrier_kind)
+  let toNat := function
+    | Barrier_Sync -> 0
+    | Barrier_LwSync -> 1
+    | Barrier_Eieio ->2
+    | Barrier_Isync -> 3
+    | Barrier_DMB -> 4
+    | Barrier_DMB_ST -> 5
+    | Barrier_DMB_LD -> 6
+    | Barrier_DSB -> 7
+    | Barrier_DSB_ST -> 8
+    | Barrier_DSB_LD -> 9
+    | Barrier_ISB -> 10
+    | Barrier_TM_COMMIT -> 11
+    | Barrier_MIPS_SYNC -> 12
+    | Barrier_RISCV_rw_rw -> 13
+    | Barrier_RISCV_r_rw -> 14
+    | Barrier_RISCV_r_r -> 15
+    | Barrier_RISCV_rw_w -> 16
+    | Barrier_RISCV_w_w -> 17
+    | Barrier_RISCV_i -> 18
+    | Barrier_x86_MFENCE -> 19
+  end
+end
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_operators.v b/snapshots/coq/lib/coq/Sail2_operators.v
new file mode 100644
index 00000000..5a8b1119
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators.v
@@ -0,0 +1,237 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require List.
+Import List.ListNotations.
+
+(*** Bit vector operations *)
+
+Section Bitvectors.
+Context {a b c} `{Bitvector a} `{Bitvector b} `{Bitvector c}.
+
+(*val concat_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c*)
+Definition concat_bv (l : a) (r : b) : list bitU := bits_of l ++ bits_of r.
+
+(*val cons_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b*)
+Definition cons_bv b' (v : a) : list bitU := b' :: bits_of v.
+
+Definition cast_unit_bv b : list bitU := [b].
+Definition bv_of_bit len b : list bitU := extz_bits len [b].
+
+(*Definition most_significant v := match bits_of v with
+  | cons b _ => b
+  | _ => failwith "most_significant applied to empty vector"
+  end.
+
+Definition get_max_representable_in sign (n : integer) : integer :=
+  if (n = 64) then match sign with | true -> max_64 | false -> max_64u end
+  else if (n=32) then match sign with | true -> max_32 | false -> max_32u end
+  else if (n=8) then max_8
+  else if (n=5) then max_5
+  else match sign with | true -> integerPow 2 ((natFromInteger n) -1)
+                       | false -> integerPow 2 (natFromInteger n)
+       end
+
+Definition get_min_representable_in _ (n : integer) : integer :=
+  if n = 64 then min_64
+  else if n = 32 then min_32
+  else if n = 8 then min_8
+  else if n = 5 then min_5
+  else 0 - (integerPow 2 (natFromInteger n))
+
+val arith_op_bv_int : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*)
+Definition arith_op_bv_int {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : a) (r : Z) : a :=
+  let r' := of_int (length l) r in
+  arith_op_bv op sign l r'.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*)
+Definition arith_op_int_bv {a} `{Bitvector a} (op : Z -> Z -> Z) (sign : bool) (l : Z) (r : a) : a :=
+  let l' := of_int (length r) l in
+  arith_op_bv op sign l' r.
+(*
+Definition add_bv_int := arith_op_bv_int Zplus false 1.
+Definition sadd_bv_int := arith_op_bv_int Zplus true 1.
+Definition sub_bv_int := arith_op_bv_int Zminus false 1.
+Definition mult_bv_int := arith_op_bv_int Zmult false 2.
+Definition smult_bv_int := arith_op_bv_int Zmult true 2.
+
+(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> integer -> 'a -> 'b
+Definition arith_op_int_bv op sign size l r :=
+  let r' = int_of_bv sign r in
+  let n = op l r' in
+  of_int (size * length r) n
+
+Definition add_int_bv = arith_op_int_bv integerAdd false 1
+Definition sadd_int_bv = arith_op_int_bv integerAdd true 1
+Definition sub_int_bv = arith_op_int_bv integerMinus false 1
+Definition mult_int_bv = arith_op_int_bv integerMult false 2
+Definition smult_int_bv = arith_op_int_bv integerMult true 2
+
+Definition arith_op_bv_bit op sign (size : integer) l r :=
+  let l' = int_of_bv sign l in
+  let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in
+  of_int (size * length l) n
+
+Definition add_bv_bit := arith_op_bv_bit integerAdd false 1
+Definition sadd_bv_bit := arith_op_bv_bit integerAdd true 1
+Definition sub_bv_bit := arith_op_bv_bit integerMinus true 1
+
+val arith_op_overflow_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv op sign size l r :=
+  let len := length l in
+  let act_size := len * size in
+  let (l_sign,r_sign) := (int_of_bv sign l,int_of_bv sign r) in
+  let (l_unsign,r_unsign) := (int_of_bv false l,int_of_bv false r) in
+  let n := op l_sign r_sign in
+  let n_unsign := op l_unsign r_unsign in
+  let correct_size := of_int act_size n in
+  let one_more_size_u := bits_of_int (act_size + 1) n_unsign in
+  let overflow :=
+    if n <= get_max_representable_in sign len &&
+         n >= get_min_representable_in sign len
+    then B0 else B1 in
+  let c_out := most_significant one_more_size_u in
+  (correct_size,overflow,c_out)
+
+Definition add_overflow_bv := arith_op_overflow_bv integerAdd false 1
+Definition add_overflow_bv_signed := arith_op_overflow_bv integerAdd true 1
+Definition sub_overflow_bv := arith_op_overflow_bv integerMinus false 1
+Definition sub_overflow_bv_signed := arith_op_overflow_bv integerMinus true 1
+Definition mult_overflow_bv := arith_op_overflow_bv integerMult false 2
+Definition mult_overflow_bv_signed := arith_op_overflow_bv integerMult true 2
+
+val arith_op_overflow_bv_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> ('b * bitU * bitU)
+Definition arith_op_overflow_bv_bit op sign size l r_bit :=
+  let act_size := length l * size in
+  let l' := int_of_bv sign l in
+  let l_u := int_of_bv false l in
+  let (n,nu,changed) := match r_bit with
+    | B1 -> (op l' 1, op l_u 1, true)
+    | B0 -> (l',l_u,false)
+    | BU -> failwith "arith_op_overflow_bv_bit applied to undefined bit"
+    end in
+  let correct_size := of_int act_size n in
+  let one_larger := bits_of_int (act_size + 1) nu in
+  let overflow :=
+    if changed
+    then
+      if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size
+      then B0 else B1
+    else B0 in
+  (correct_size,overflow,most_significant one_larger)
+
+Definition add_overflow_bv_bit := arith_op_overflow_bv_bit integerAdd false 1
+Definition add_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerAdd true 1
+Definition sub_overflow_bv_bit := arith_op_overflow_bv_bit integerMinus false 1
+Definition sub_overflow_bv_bit_signed := arith_op_overflow_bv_bit integerMinus true 1
+
+type shift := LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot
+
+val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a
+Definition shift_op_bv op v n :=
+  match op with
+  | LL_shift ->
+     of_bits (get_bits true v n (length v - 1) ++ repeat [B0] n)
+  | RR_shift ->
+     of_bits (repeat [B0] n ++ get_bits true v 0 (length v - n - 1))
+  | RR_shift_arith ->
+     of_bits (repeat [most_significant v] n ++ get_bits true v 0 (length v - n - 1))
+  | LL_rot ->
+     of_bits (get_bits true v n (length v - 1) ++ get_bits true v 0 (n - 1))
+  | RR_rot ->
+     of_bits (get_bits false v 0 (n - 1) ++ get_bits false v n (length v - 1))
+  end
+
+Definition shiftl_bv := shift_op_bv LL_shift (*"<<"*)
+Definition shiftr_bv := shift_op_bv RR_shift (*">>"*)
+Definition arith_shiftr_bv := shift_op_bv RR_shift_arith
+Definition rotl_bv := shift_op_bv LL_rot (*"<<<"*)
+Definition rotr_bv := shift_op_bv LL_rot (*">>>"*)
+
+Definition shiftl_mword w n := Machine_word.shiftLeft w (natFromInteger n)
+Definition shiftr_mword w n := Machine_word.shiftRight w (natFromInteger n)
+Definition rotl_mword w n := Machine_word.rotateLeft (natFromInteger n) w
+Definition rotr_mword w n := Machine_word.rotateRight (natFromInteger n) w
+
+Definition rec arith_op_no0 (op : integer -> integer -> integer) l r :=
+  if r = 0
+  then Nothing
+  else Just (op l r)
+
+val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b =>
+  (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b
+Definition arith_op_bv_no0 op sign size l r :=
+  let act_size := length l * size in
+  let (l',r') := (int_of_bv sign l,int_of_bv sign r) in
+  let n := arith_op_no0 op l' r' in
+  let (representable,n') :=
+    match n with
+    | Just n' ->
+      (n' <= get_max_representable_in sign act_size &&
+         n' >= get_min_representable_in sign act_size, n')
+    | _ -> (false,0)
+    end in
+  if representable then (of_int act_size n') else (of_bits (repeat [BU] act_size))
+
+Definition mod_bv := arith_op_bv_no0 hardware_mod false 1
+Definition quot_bv := arith_op_bv_no0 hardware_quot false 1
+Definition quot_bv_signed := arith_op_bv_no0 hardware_quot true 1
+
+Definition mod_mword := Machine_word.modulo
+Definition quot_mword := Machine_word.unsignedDivide
+Definition quot_mword_signed := Machine_word.signedDivide
+
+Definition arith_op_bv_int_no0 op sign size l r :=
+  arith_op_bv_no0 op sign size l (of_int (length l) r)
+
+Definition quot_bv_int := arith_op_bv_int_no0 hardware_quot false 1
+Definition mod_bv_int := arith_op_bv_int_no0 hardware_mod false 1
+*)
+Definition replicate_bits_bv {a b} `{Bitvector a} `{Bitvector b} (v : a) count : b := of_bits (repeat (bits_of v) count).
+Import List.
+Import ListNotations.
+Definition duplicate_bit_bv {a} `{Bitvector a} bit len : a := replicate_bits_bv [bit] len.
+
+(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition eq_bv {A} `{Bitvector A} (l : A) r := (unsigned l =? unsigned r).
+
+(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*)
+Definition neq_bv (l : a) (r :a) : bool := (negb (unsigned l =? unsigned r)).
+(*
+val ucmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition ucmp_bv cmp l r := cmp (unsigned l) (unsigned r)
+
+val scmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool
+Definition scmp_bv cmp l r := cmp (signed l) (signed r)
+
+Definition ult_bv := ucmp_bv (<)
+Definition slt_bv := scmp_bv (<)
+Definition ugt_bv := ucmp_bv (>)
+Definition sgt_bv := scmp_bv (>)
+Definition ulteq_bv := ucmp_bv (<=)
+Definition slteq_bv := scmp_bv (<=)
+Definition ugteq_bv := ucmp_bv (>=)
+Definition sgteq_bv := scmp_bv (>=)
+*)
+
+(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*)*)
+Definition get_slice_int_bv {a} `{Bitvector a} len n lo : a :=
+  let hi := lo + len - 1 in
+  let bs := bools_of_int (hi + 1) n in
+  of_bools (subrange_list false bs hi lo).
+
+(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer
+Definition set_slice_int_bv {a} `{Bitvector a} len n lo (v : a) :=
+  let hi := lo + len - 1 in
+  let bs := bits_of_int (hi + 1) n in
+  maybe_failwith (signed_of_bits (update_subrange_list false bs hi lo (bits_of v))).*)
+
+End Bitvectors.
diff --git a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v
new file mode 100644
index 00000000..b0240c4e
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v
@@ -0,0 +1,187 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require Import Sail2_operators.
+
+(*
+
+(* Specialisation of operators to bit lists *)
+
+val access_vec_inc : list bitU -> integer -> bitU
+let access_vec_inc = access_bv_inc
+
+val access_vec_dec : list bitU -> integer -> bitU
+let access_vec_dec = access_bv_dec
+
+val update_vec_inc : list bitU -> integer -> bitU -> list bitU
+let update_vec_inc = update_bv_inc
+
+val update_vec_dec : list bitU -> integer -> bitU -> list bitU
+let update_vec_dec = update_bv_dec
+
+val subrange_vec_inc : list bitU -> integer -> integer -> list bitU
+let subrange_vec_inc = subrange_bv_inc
+
+val subrange_vec_dec : list bitU -> integer -> integer -> list bitU
+let subrange_vec_dec = subrange_bv_dec
+
+val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_inc = update_subrange_bv_inc
+
+val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU
+let update_subrange_vec_dec = update_subrange_bv_dec
+
+val extz_vec : integer -> list bitU -> list bitU
+let extz_vec = extz_bv
+
+val exts_vec : integer -> list bitU -> list bitU
+let exts_vec = exts_bv
+
+val concat_vec : list bitU -> list bitU -> list bitU
+let concat_vec = concat_bv
+
+val cons_vec : bitU -> list bitU -> list bitU
+let cons_vec = cons_bv
+
+val bool_of_vec : mword ty1 -> bitU
+let bool_of_vec = bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+let cast_unit_vec = cast_unit_bv
+
+val vec_of_bit : integer -> bitU -> list bitU
+let vec_of_bit = bv_of_bit
+
+val msb : list bitU -> bitU
+let msb = most_significant
+
+val int_of_vec : bool -> list bitU -> integer
+let int_of_vec = int_of_bv
+
+val string_of_vec : list bitU -> string
+let string_of_vec = string_of_bv
+
+val and_vec : list bitU -> list bitU -> list bitU
+val or_vec  : list bitU -> list bitU -> list bitU
+val xor_vec : list bitU -> list bitU -> list bitU
+val not_vec : list bitU -> list bitU
+let and_vec = and_bv
+let or_vec  = or_bv
+let xor_vec = xor_bv
+let not_vec = not_bv
+
+val add_vec   : list bitU -> list bitU -> list bitU
+val sadd_vec  : list bitU -> list bitU -> list bitU
+val sub_vec   : list bitU -> list bitU -> list bitU
+val mult_vec  : list bitU -> list bitU -> list bitU
+val smult_vec : list bitU -> list bitU -> list bitU
+let add_vec   = add_bv
+let sadd_vec  = sadd_bv
+let sub_vec   = sub_bv
+let mult_vec  = mult_bv
+let smult_vec = smult_bv
+
+val add_vec_int   : list bitU -> integer -> list bitU
+val sadd_vec_int  : list bitU -> integer -> list bitU
+val sub_vec_int   : list bitU -> integer -> list bitU
+val mult_vec_int  : list bitU -> integer -> list bitU
+val smult_vec_int : list bitU -> integer -> list bitU
+let add_vec_int   = add_bv_int
+let sadd_vec_int  = sadd_bv_int
+let sub_vec_int   = sub_bv_int
+let mult_vec_int  = mult_bv_int
+let smult_vec_int = smult_bv_int
+
+val add_int_vec   : integer -> list bitU -> list bitU
+val sadd_int_vec  : integer -> list bitU -> list bitU
+val sub_int_vec   : integer -> list bitU -> list bitU
+val mult_int_vec  : integer -> list bitU -> list bitU
+val smult_int_vec : integer -> list bitU -> list bitU
+let add_int_vec   = add_int_bv
+let sadd_int_vec  = sadd_int_bv
+let sub_int_vec   = sub_int_bv
+let mult_int_vec  = mult_int_bv
+let smult_int_vec = smult_int_bv
+
+val add_vec_bit  : list bitU -> bitU -> list bitU
+val sadd_vec_bit : list bitU -> bitU -> list bitU
+val sub_vec_bit  : list bitU -> bitU -> list bitU
+let add_vec_bit  = add_bv_bit
+let sadd_vec_bit = sadd_bv_bit
+let sub_vec_bit  = sub_bv_bit
+
+val add_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec         : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_signed  : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec        : list bitU -> list bitU -> (list bitU * bitU * bitU)
+val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec         = add_overflow_bv
+let add_overflow_vec_signed  = add_overflow_bv_signed
+let sub_overflow_vec         = sub_overflow_bv
+let sub_overflow_vec_signed  = sub_overflow_bv_signed
+let mult_overflow_vec        = mult_overflow_bv
+let mult_overflow_vec_signed = mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val add_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit         : list bitU -> bitU -> (list bitU * bitU * bitU)
+val sub_overflow_vec_bit_signed  : list bitU -> bitU -> (list bitU * bitU * bitU)
+let add_overflow_vec_bit         = add_overflow_bv_bit
+let add_overflow_vec_bit_signed  = add_overflow_bv_bit_signed
+let sub_overflow_vec_bit         = sub_overflow_bv_bit
+let sub_overflow_vec_bit_signed  = sub_overflow_bv_bit_signed
+
+val shiftl       : list bitU -> integer -> list bitU
+val shiftr       : list bitU -> integer -> list bitU
+val arith_shiftr : list bitU -> integer -> list bitU
+val rotl         : list bitU -> integer -> list bitU
+val rotr         : list bitU -> integer -> list bitU
+let shiftl       = shiftl_bv
+let shiftr       = shiftr_bv
+let arith_shiftr = arith_shiftr_bv
+let rotl         = rotl_bv
+let rotr         = rotr_bv
+
+val mod_vec         : list bitU -> list bitU -> list bitU
+val quot_vec        : list bitU -> list bitU -> list bitU
+val quot_vec_signed : list bitU -> list bitU -> list bitU
+let mod_vec         = mod_bv
+let quot_vec        = quot_bv
+let quot_vec_signed = quot_bv_signed
+
+val mod_vec_int  : list bitU -> integer -> list bitU
+val quot_vec_int : list bitU -> integer -> list bitU
+let mod_vec_int  = mod_bv_int
+let quot_vec_int = quot_bv_int
+
+val replicate_bits : list bitU -> integer -> list bitU
+let replicate_bits = replicate_bits_bv
+
+val duplicate : bitU -> integer -> list bitU
+let duplicate = duplicate_bit_bv
+
+val eq_vec    : list bitU -> list bitU -> bool
+val neq_vec   : list bitU -> list bitU -> bool
+val ult_vec   : list bitU -> list bitU -> bool
+val slt_vec   : list bitU -> list bitU -> bool
+val ugt_vec   : list bitU -> list bitU -> bool
+val sgt_vec   : list bitU -> list bitU -> bool
+val ulteq_vec : list bitU -> list bitU -> bool
+val slteq_vec : list bitU -> list bitU -> bool
+val ugteq_vec : list bitU -> list bitU -> bool
+val sgteq_vec : list bitU -> list bitU -> bool
+let eq_vec    = eq_bv
+let neq_vec   = neq_bv
+let ult_vec   = ult_bv
+let slt_vec   = slt_bv
+let ugt_vec   = ugt_bv
+let sgt_vec   = sgt_bv
+let ulteq_vec = ulteq_bv
+let slteq_vec = slteq_bv
+let ugteq_vec = ugteq_bv
+let sgteq_vec = sgteq_bv
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_operators_mwords.v b/snapshots/coq/lib/coq/Sail2_operators_mwords.v
new file mode 100644
index 00000000..fba23071
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_operators_mwords.v
@@ -0,0 +1,438 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_values.
+Require Import Sail2_operators.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import bbv.Word.
+Require bbv.BinNotation.
+Require Import Arith.
+Require Import ZArith.
+Require Import Omega.
+Require Import Eqdep_dec.
+
+Module Z_eq_dec.
+Definition U := Z.
+Definition eq_dec := Z.eq_dec.
+End Z_eq_dec.
+Module ZEqdep := DecidableEqDep (Z_eq_dec).
+
+Definition cast_mword {m n} (x : mword m) (eq : m = n) : mword n.
+rewrite <- eq.
+exact x.
+Defined.
+
+Lemma cast_mword_refl {m} {H:m = m} (x : mword m) : cast_mword x H = x.
+rewrite (ZEqdep.UIP _ _ H eq_refl).
+reflexivity.
+Qed.
+
+Definition autocast {m n} (x : mword m) `{H:ArithFact (m = n)} : mword n :=
+  cast_mword x (use_ArithFact H).
+
+Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e :=
+  x >>= fun x => returnm (cast_mword x (use_ArithFact H)).
+
+Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n.
+rewrite <- eq.
+exact x.
+Defined.
+
+Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x.
+rewrite (UIP_refl_nat _ H).
+reflexivity.
+Qed.
+
+Definition mword_of_nat {m} (x : Word.word m) : mword (Z.of_nat m).
+destruct m.
+- exact x.
+- simpl. rewrite SuccNat2Pos.id_succ. exact x.
+Defined.
+
+Definition cast_to_mword {m n} (x : Word.word m) (eq : Z.of_nat m = n) : mword n.
+destruct n.
+- constructor.
+- rewrite <- eq. exact (mword_of_nat x).
+- exfalso. destruct m; simpl in *; congruence.
+Defined.
+
+(*
+(* Specialisation of operators to machine words *)
+
+val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_inc {a} : mword a -> Z -> bitU := access_mword_inc.
+
+(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*)
+Definition access_vec_dec {a} : mword a -> Z -> bitU := access_mword_dec.
+
+(*val update_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+(* TODO: probably ought to use a monadic version instead, but using bad default for
+   type compatibility just now *)
+Definition update_vec_inc {a} (w : mword a) i b : mword a :=
+ opt_def w (update_mword_inc w i b).
+
+(*val update_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a*)
+Definition update_vec_dec {a} (w : mword a) i b : mword a := opt_def w (update_mword_dec w i b).
+
+Lemma subrange_lemma0 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : (Z.to_nat o <= Z.to_nat m < Z.to_nat n)%nat.
+intros.
+unwrap_ArithFacts.
+split.
++ apply Z2Nat.inj_le; omega.
++ apply Z2Nat.inj_lt; omega.
+Qed.
+Lemma subrange_lemma1 {n m o} : (o <= m < n -> n = m + 1 + (n - (m + 1)))%nat.
+intros. omega.
+Qed.
+Lemma subrange_lemma2 {n m o} : (o <= m < n -> m+1 = o+(m-o+1))%nat.
+omega.
+Qed.
+Lemma subrange_lemma3 {n m o} `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} :
+  Z.of_nat (Z.to_nat m - Z.to_nat o + 1)%nat = m - o + 1.
+unwrap_ArithFacts.
+rewrite Nat2Z.inj_add.
+rewrite Nat2Z.inj_sub.
+repeat rewrite Z2Nat.id; try omega.
+reflexivity.
+apply Z2Nat.inj_le; omega.
+Qed.
+
+Definition subrange_vec_dec {n} (v : mword n) m o `{ArithFact (0 <= o)} `{ArithFact (o <= m < n)} : mword (m - o + 1) :=
+  let n := Z.to_nat n in
+  let m := Z.to_nat m in
+  let o := Z.to_nat o in
+  let prf : (o <= m < n)%nat := subrange_lemma0 in
+  let w := get_word v in
+  cast_to_mword (split2 o (m-o+1)
+                        (cast_word (split1 (m+1) (n-(m+1)) (cast_word w (subrange_lemma1 prf)))
+                                   (subrange_lemma2 prf))) subrange_lemma3.
+
+Definition subrange_vec_inc {n} (v : mword n) m o `{ArithFact (0 <= m)} `{ArithFact (m <= o < n)} : mword (o - m + 1) := autocast (subrange_vec_dec v (n-1-m) (n-1-o)).
+
+(* TODO: get rid of bogus default *)
+Parameter dummy_vector : forall {n} `{ArithFact (n >= 0)}, mword n.
+
+(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_inc {a b} (v : mword a) i j (w : mword b) : mword a :=
+  opt_def dummy_vector (of_bits (update_subrange_bv_inc v i j w)).
+
+(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*)
+Definition update_subrange_vec_dec {a b} (v : mword a) i j (w : mword b) : mword a :=
+  opt_def dummy_vector (of_bits (update_subrange_bv_dec v i j w)).
+
+Lemma mword_nonneg {a} : mword a -> a >= 0.
+destruct a;
+auto using Z.le_ge, Zle_0_pos with zarith.
+destruct 1.
+Qed.
+
+(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition extz_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.zext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*)
+Definition exts_vec {a b} `{ArithFact (b >= a)} (n : Z) (v : mword a) : mword b.
+refine (cast_to_mword (Word.sext (get_word v) (Z.to_nat (b - a))) _).
+unwrap_ArithFacts.
+assert (a >= 0). { apply mword_nonneg. assumption. }
+rewrite <- Z2Nat.inj_add; try omega.
+rewrite Zplus_minus.
+apply Z2Nat.id.
+auto with zarith.
+Defined.
+
+Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := extz_vec n v.
+
+Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v.
+
+Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat.
+intros.
+assert ((Z.to_nat m <= Z.to_nat n)%nat).
+{ apply Z2Nat.inj_le; omega. }
+omega.
+Qed.
+
+Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m :=
+  cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m).
+
+Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b.
+intros.
+rewrite Nat2Z.inj_add.
+rewrite Z2Nat.id; auto with zarith.
+rewrite Z2Nat.id; auto with zarith.
+Qed.
+
+
+(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*)
+Definition concat_vec {a b} (v : mword a) (w : mword b) : mword (a + b) :=
+ cast_to_mword (Word.combine (get_word w) (get_word v)) (ltac:(solve [auto using concat_eq, mword_nonneg with zarith]) : Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b).
+
+(*val cons_vec : forall 'a 'b 'c. Size 'a, Size 'b => bitU -> mword 'a -> mword 'b*)
+(*Definition cons_vec {a b} : bitU -> mword a -> mword b := cons_bv.*)
+
+(*val bool_of_vec : mword ty1 -> bitU
+Definition bool_of_vec := bool_of_bv
+
+val cast_unit_vec : bitU -> mword ty1
+Definition cast_unit_vec := cast_unit_bv
+
+val vec_of_bit : forall 'a. Size 'a => integer -> bitU -> mword 'a
+Definition vec_of_bit := bv_of_bit*)
+
+Require Import bbv.NatLib.
+
+Lemma Npow2_pow {n} : (2 ^ (N.of_nat n) = Npow2 n)%N.
+induction n.
+* reflexivity.
+* rewrite Nnat.Nat2N.inj_succ.
+  rewrite N.pow_succ_r'.
+  rewrite IHn.
+  rewrite Npow2_S.
+  rewrite Word.Nmul_two.
+  reflexivity.
+Qed.
+
+Program Definition uint {a} (x : mword a) : {z : Z & ArithFact (0 <= z /\ z <= 2 ^ a - 1)} :=
+ existT _ (Z.of_N (Word.wordToN (get_word x))) _.
+Next Obligation.
+constructor.
+constructor.
+* apply N2Z.is_nonneg.
+* assert (2 ^ a - 1 = Z.of_N (2 ^ (Z.to_N a) - 1)). {
+    rewrite N2Z.inj_sub.
+    * rewrite N2Z.inj_pow.
+      rewrite Z2N.id; auto.
+      destruct a; auto with zarith. destruct x.
+    * apply N.le_trans with (m := (2^0)%N); auto using N.le_refl.
+      apply N.pow_le_mono_r.
+      inversion 1.
+      apply N.le_0_l.
+  }
+  rewrite H.
+  apply N2Z.inj_le.
+  rewrite N.sub_1_r.
+  apply N.lt_le_pred.
+  rewrite <- Z_nat_N.
+  rewrite Npow2_pow.
+  apply Word.wordToN_bound.
+Defined.
+
+Lemma Zpow_pow2 {n} : 2 ^ Z.of_nat n = Z.of_nat (pow2 n).
+induction n.
+* reflexivity.
+* rewrite pow2_S_z.
+  rewrite Nat2Z.inj_succ.
+  rewrite Z.pow_succ_r; auto with zarith.
+Qed.
+
+Program Definition sint {a} `{ArithFact (a > 0)} (x : mword a) : {z : Z & ArithFact (-(2^(a-1)) <= z /\ z <= 2 ^ (a-1) - 1)} :=
+  existT _ (Word.wordToZ (get_word x)) _.
+Next Obligation.
+destruct H.
+destruct a; try inversion fact.
+constructor.
+generalize (get_word x).
+rewrite <- positive_nat_Z.
+destruct (Pos2Nat.is_succ p) as [n eq].
+rewrite eq.
+rewrite Nat2Z.id.
+intro w.
+destruct (Word.wordToZ_size' w) as [LO HI].
+replace 1 with (Z.of_nat 1); auto.
+rewrite <- Nat2Z.inj_sub; auto with arith.
+simpl.
+rewrite <- minus_n_O.
+rewrite Zpow_pow2.
+rewrite Z.sub_1_r.
+rewrite <- Z.lt_le_pred.
+auto.
+Defined.
+
+Lemma length_list_pos : forall {A} {l:list A}, length_list l >= 0.
+unfold length_list.
+auto with zarith.
+Qed.
+Hint Resolve length_list_pos : sail.
+
+Definition vec_of_bits (l:list bitU) : mword (length_list l) := opt_def dummy_vector (of_bits l).
+(*
+
+val msb : forall 'a. Size 'a => mword 'a -> bitU
+Definition msb := most_significant
+
+val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer
+Definition int_of_vec := int_of_bv
+
+val string_of_vec : forall 'a. Size 'a => mword 'a -> string*)
+Definition string_of_bits {n} (w : mword n) : string := string_of_bv w.
+Definition with_word' {n} (P : Type -> Type) : (forall n, Word.word n -> P (Word.word n)) -> mword n -> P (mword n) := fun f w => @with_word n _ (f (Z.to_nat n)) w.
+Definition word_binop {n} (f : forall n, Word.word n -> Word.word n -> Word.word n) : mword n -> mword n -> mword n := with_word' (fun x => x -> x) f.
+Definition word_unop {n} (f : forall n, Word.word n -> Word.word n) : mword n -> mword n := with_word' (fun x => x) f.
+
+
+(*
+val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val or_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*)
+Definition and_vec {n} : mword n -> mword n -> mword n := word_binop Word.wand.
+Definition or_vec  {n} : mword n -> mword n -> mword n := word_binop Word.wor.
+Definition xor_vec {n} : mword n -> mword n -> mword n := word_binop Word.wxor.
+Definition not_vec {n} : mword n -> mword n := word_unop Word.wnot.
+
+(*val add_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sadd_vec  : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val sub_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val mult_vec  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b
+val smult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*)
+Definition add_vec   {n} : mword n -> mword n -> mword n := word_binop Word.wplus.
+(*Definition sadd_vec  {n} : mword n -> mword n -> mword n := sadd_bv w.*)
+Definition sub_vec   {n} : mword n -> mword n -> mword n := word_binop Word.wminus.
+Definition mult_vec  {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+  word_binop Word.wmult (zero_extend l _) (zero_extend r _).
+Definition mults_vec  {n m} `{ArithFact (m >= n)} (l : mword n) (r : mword n) : mword m :=
+  word_binop Word.wmult (sign_extend l _) (sign_extend r _).
+
+(*val add_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sadd_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val sub_vec_int   : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val mult_vec_int  : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b
+val smult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Definition add_vec_int   {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add   false l r.
+Definition sadd_vec_int  {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.add   true  l r.
+Definition sub_vec_int   {a} (l : mword a) (r : Z) : mword a := arith_op_bv_int Z.sub   false l r.
+(*Definition mult_vec_int  {a b} : mword a -> Z -> mword b := mult_bv_int.
+Definition smult_vec_int {a b} : mword a -> Z -> mword b := smult_bv_int.*)
+
+(*val add_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sadd_int_vec  : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val sub_int_vec   : forall 'a. Size 'a => integer -> mword 'a -> mword 'a
+val mult_int_vec  : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+val smult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b
+Definition add_int_vec   := add_int_bv
+Definition sadd_int_vec  := sadd_int_bv
+Definition sub_int_vec   := sub_int_bv
+Definition mult_int_vec  := mult_int_bv
+Definition smult_int_vec := smult_int_bv
+
+val add_vec_bit  : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sadd_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+val sub_vec_bit  : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a
+Definition add_vec_bit  := add_bv_bit
+Definition sadd_vec_bit := sadd_bv_bit
+Definition sub_vec_bit  := sub_bv_bit
+
+val add_overflow_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val add_overflow_vec_signed  : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_signed  : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+val mult_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec         := add_overflow_bv
+Definition add_overflow_vec_signed  := add_overflow_bv_signed
+Definition sub_overflow_vec         := sub_overflow_bv
+Definition sub_overflow_vec_signed  := sub_overflow_bv_signed
+Definition mult_overflow_vec        := mult_overflow_bv
+Definition mult_overflow_vec_signed := mult_overflow_bv_signed
+
+val add_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val add_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit         : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+val sub_overflow_vec_bit_signed  : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU)
+Definition add_overflow_vec_bit         := add_overflow_bv_bit
+Definition add_overflow_vec_bit_signed  := add_overflow_bv_bit_signed
+Definition sub_overflow_vec_bit         := sub_overflow_bv_bit
+Definition sub_overflow_vec_bit_signed  := sub_overflow_bv_bit_signed
+
+val shiftl       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val shiftr       : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotl         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val rotr         : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*)
+(* TODO: check/redefine behaviour on out-of-range n *)
+Definition shiftl       {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wlshift w (Z.to_nat n)) v.
+Definition shiftr       {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshift w (Z.to_nat n)) v.
+Definition arith_shiftr {a} (v : mword a) n : mword a := with_word (P := id) (fun w => Word.wrshifta w (Z.to_nat n)) v.
+(*
+Definition rotl         := rotl_bv
+Definition rotr         := rotr_bv
+
+val mod_vec         : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec        : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+val quot_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a
+Definition mod_vec         := mod_bv
+Definition quot_vec        := quot_bv
+Definition quot_vec_signed := quot_bv_signed
+
+val mod_vec_int  : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a
+Definition mod_vec_int  := mod_bv_int
+Definition quot_vec_int := quot_bv_int
+
+val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*)
+Fixpoint replicate_bits_aux {a} (w : Word.word a) (n : nat) : Word.word (n * a) :=
+match n with
+| O => Word.WO
+| S m => Word.combine w (replicate_bits_aux w m)
+end.
+Lemma replicate_ok {n a} `{ArithFact (n >= 0)} `{ArithFact (a >= 0)} :
+   Z.of_nat (Z.to_nat n * Z.to_nat a) = a * n.
+destruct H. destruct H0.
+rewrite <- Z2Nat.id; auto with zarith.
+rewrite Z2Nat.inj_mul; auto with zarith.
+rewrite Nat.mul_comm. reflexivity.
+Qed.
+Definition replicate_bits {a} (w : mword a) (n : Z) `{ArithFact (n >= 0)} : mword (a * n) :=
+ cast_to_mword (replicate_bits_aux (get_word w) (Z.to_nat n)) replicate_ok.
+
+(*val duplicate : forall 'a. Size 'a => bitU -> integer -> mword 'a
+Definition duplicate := duplicate_bit_bv
+
+val eq_vec    : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val neq_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ult_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgt_vec   : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool
+val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*)
+Definition eq_vec  {n} (x : mword n) (y : mword n) : bool := Word.weqb (get_word x) (get_word y).
+Definition neq_vec {n} (x : mword n) (y : mword n) : bool := negb (eq_vec x y).
+(*Definition ult_vec   := ult_bv.
+Definition slt_vec   := slt_bv.
+Definition ugt_vec   := ugt_bv.
+Definition sgt_vec   := sgt_bv.
+Definition ulteq_vec := ulteq_bv.
+Definition slteq_vec := slteq_bv.
+Definition ugteq_vec := ugteq_bv.
+Definition sgteq_vec := sgteq_bv.
+
+*)
+
+Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n :=
+  match n with
+  | S (S (S (S (S (S (S (S m))))))) =>
+    combine
+      (reverse_endianness_word (split2 8 m bits))
+      (split1 8 m bits)
+  | _ => bits
+  end.
+Next Obligation.
+omega.
+Qed.
+
+Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits.
+
+Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv.
diff --git a/snapshots/coq/lib/coq/Sail2_prompt.v b/snapshots/coq/lib/coq/Sail2_prompt.v
new file mode 100644
index 00000000..ab7d5bac
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_prompt.v
@@ -0,0 +1,122 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+
+Require Import List.
+Import ListNotations.
+(*
+
+val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let rec iter_aux i f xs = match xs with
+  | x :: xs -> f i x >> iter_aux (i + 1) f xs
+  | [] -> return ()
+  end
+
+declare {isabelle} termination_argument iter_aux = automatic
+
+val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iteri f xs = iter_aux 0 f xs
+
+val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e
+let iter f xs = iteri (fun _ x -> f x) xs
+
+val foreachM : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*)
+Fixpoint foreachM {a rv Vars e} (l : list a) (vars : Vars) (body : a -> Vars -> monad rv Vars e) : monad rv Vars e :=
+match l with
+| [] => returnm vars
+| (x :: xs) =>
+  body x vars >>= fun vars =>
+  foreachM xs vars body
+end.
+
+Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_up' from to step (off + step) n vars body
+    end
+  else returnm vars.
+
+Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => returnm vars
+    | S n => body (from + off) _ vars >>= fun vars => foreach_ZM_down' from to step (off - step) n vars body
+    end
+  else returnm vars.
+
+Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*declare {isabelle} termination_argument foreachM = automatic*)
+
+(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition and_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then r else returnm false).
+
+(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*)
+Definition or_boolM {rv E} (l : monad rv bool E) (r : monad rv bool E) : monad rv bool E :=
+ l >>= (fun l => if l then returnm true else r).
+
+(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_fail {rv E} (b : bitU) : monad rv bool E :=
+match b with
+  | B0 => returnm false
+  | B1 => returnm true
+  | BU => Fail "bool_of_bitU"
+end.
+
+(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*)
+Definition bool_of_bitU_oracle {rv E} (b : bitU) : monad rv bool E :=
+match b with
+  | B0 => returnm false
+  | B1 => returnm true
+  | BU => undefined_bool tt
+end.
+
+
+(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e
+let rec whileM vars cond body =
+  cond vars >>= fun cond_val ->
+  if cond_val then
+    body vars >>= fun vars -> whileM vars cond body
+  else return vars
+
+val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) ->
+                ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e
+let rec untilM vars cond body =
+  body vars >>= fun vars ->
+  cond vars >>= fun cond_val ->
+  if cond_val then return vars else untilM vars cond body
+
+(*let write_two_regs r1 r2 vec =
+  let is_inc =
+    let is_inc_r1 = is_inc_of_reg r1 in
+    let is_inc_r2 = is_inc_of_reg r2 in
+    let () = ensure (is_inc_r1 = is_inc_r2)
+                    "write_two_regs called with vectors of different direction" in
+    is_inc_r1 in
+
+  let (size_r1 : integer) = size_of_reg r1 in
+  let (start_vec : integer) = get_start vec in
+  let size_vec = length vec in
+  let r1_v =
+    if is_inc
+    then slice vec start_vec (size_r1 - start_vec - 1)
+    else slice vec start_vec (start_vec - size_r1 - 1) in
+  let r2_v =
+    if is_inc
+    then slice vec (size_r1 - start_vec) (size_vec - start_vec)
+    else slice vec (start_vec - size_r1) (start_vec - size_vec) in
+  write_reg r1 r1_v >> write_reg r2 r2_v*)
+
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_prompt_monad.v b/snapshots/coq/lib/coq/Sail2_prompt_monad.v
new file mode 100644
index 00000000..43e873f7
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_prompt_monad.v
@@ -0,0 +1,252 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import String.
+(*Require Import Sail_impl_base*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+
+
+
+Definition register_name := string.
+Definition address := list bitU.
+
+Inductive monad regval a e :=
+  | Done : a -> monad regval a e
+  (* Read a number : bytes from memory, returned in little endian order *)
+  | Read_mem : read_kind -> address -> nat -> (list memory_byte -> monad regval a e) -> monad regval a e
+  (* Read the tag : a memory address *)
+  | Read_tag : address -> (bitU -> monad regval a e) -> monad regval a e
+  (* Tell the system a write is imminent, at address lifted, : size nat *)
+  | Write_ea : write_kind -> address -> nat -> monad regval a e -> monad regval a e
+  (* Request the result : store-exclusive *)
+  | Excl_res : (bool -> monad regval a e) -> monad regval a e
+  (* Request to write memory at last signalled address. Memory value should be 8
+     times the size given in ea signal, given in little endian order *)
+  | Write_memv : list memory_byte -> (bool -> monad regval a e) -> monad regval a e
+  (* Request to write the tag at last signalled address. *)
+  | Write_tag : address -> bitU -> (bool -> monad regval a e) -> monad regval a e
+  (* Tell the system to dynamically recalculate dependency footprint *)
+  | Footprint : monad regval a e -> monad regval a e
+  (* Request a memory barrier *)
+  | Barrier : barrier_kind -> monad regval a e -> monad regval a e
+  (* Request to read register, will track dependency when mode.track_values *)
+  | Read_reg : register_name -> (regval -> monad regval a e) -> monad regval a e
+  (* Request to write register *)
+  | Write_reg : register_name -> regval -> monad regval a e -> monad regval a e
+  | Undefined : (bool -> monad regval a e) -> monad regval a e
+  (*Result : a failed assert with possible error message to report*)
+  | Fail : string -> monad regval a e
+  | Error : string -> monad regval a e
+  (* Exception : type e *)
+  | Exception : e -> monad regval a e.
+  (* TODO: Reading/writing tags *)
+
+Arguments Done [_ _ _].
+Arguments Read_mem [_ _ _].
+Arguments Read_tag [_ _ _].
+Arguments Write_ea [_ _ _].
+Arguments Excl_res [_ _ _].
+Arguments Write_memv [_ _ _].
+Arguments Write_tag [_ _ _].
+Arguments Footprint [_ _ _].
+Arguments Barrier [_ _ _].
+Arguments Read_reg [_ _ _].
+Arguments Write_reg [_ _ _].
+Arguments Undefined [_ _ _].
+Arguments Fail [_ _ _].
+Arguments Error [_ _ _].
+Arguments Exception [_ _ _].
+
+(*val return : forall rv a e. a -> monad rv a e*)
+Definition returnm {rv A E} (a : A) : monad rv A E := Done a.
+
+(*val bind : forall rv a b e. monad rv a e -> (a -> monad rv b e) -> monad rv b e*)
+Fixpoint bind {rv A B E} (m : monad rv A E) (f : A -> monad rv B E) := match m with
+  | Done a => f a
+  | Read_mem rk a sz k => Read_mem rk a sz (fun v => bind (k v) f)
+  | Read_tag a k =>       Read_tag a       (fun v => bind (k v) f)
+  | Write_memv descr k => Write_memv descr (fun v => bind (k v) f)
+  | Write_tag a t k =>    Write_tag a t    (fun v => bind (k v) f)
+  | Read_reg descr k =>   Read_reg descr   (fun v => bind (k v) f)
+  | Excl_res k =>         Excl_res         (fun v => bind (k v) f)
+  | Undefined k =>        Undefined        (fun v => bind (k v) f)
+  | Write_ea wk a sz k => Write_ea wk a sz (bind k f)
+  | Footprint k =>        Footprint        (bind k f)
+  | Barrier bk k =>       Barrier bk       (bind k f)
+  | Write_reg r v k =>    Write_reg r v    (bind k f)
+  | Fail descr =>         Fail descr
+  | Error descr =>        Error descr
+  | Exception e =>        Exception e
+end.
+
+Notation "m >>= f" := (bind m f) (at level 50, left associativity).
+(*val (>>) : forall rv b e. monad rv unit e -> monad rv b e -> monad rv b e*)
+Definition bind0 {rv A E} (m : monad rv unit E) (n : monad rv A E) :=
+  m >>= fun (_ : unit) => n.
+Notation "m >> n" := (bind0 m n) (at level 50, left associativity).
+
+(*val exit : forall rv a e. unit -> monad rv a e*)
+Definition exit {rv A E} (_ : unit) : monad rv A E := Fail "exit".
+
+(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*)
+Definition undefined_bool {rv e} (_:unit) : monad rv bool e := Undefined returnm.
+
+(*val assert_exp : forall rv e. bool -> string -> monad rv unit e*)
+Definition assert_exp {rv E} (exp :bool) msg : monad rv unit E :=
+ if exp then Done tt else Fail msg.
+
+Definition assert_exp' {rv E} (exp :bool) msg : monad rv (exp = true) E :=
+ if exp return monad rv (exp = true) E then Done eq_refl else Fail msg.
+Definition bindH {rv A P E} (m : monad rv P E) (n : monad rv A E) :=
+  m >>= fun (H : P) => n.
+Notation "m >>> n" := (bindH m n) (at level 50, left associativity).
+
+(*val throw : forall rv a e. e -> monad rv a e*)
+Definition throw {rv A E} e : monad rv A E := Exception e.
+
+(*val try_catch : forall rv a e1 e2. monad rv a e1 -> (e1 -> monad rv a e2) -> monad rv a e2*)
+Fixpoint try_catch {rv A E1 E2} (m : monad rv A E1) (h : E1 -> monad rv A E2) := match m with
+  | Done a =>             Done a
+  | Read_mem rk a sz k => Read_mem rk a sz (fun v => try_catch (k v) h)
+  | Read_tag a k =>       Read_tag a       (fun v => try_catch (k v) h)
+  | Write_memv descr k => Write_memv descr (fun v => try_catch (k v) h)
+  | Write_tag a t k =>    Write_tag a t     (fun v => try_catch (k v) h)
+  | Read_reg descr k =>   Read_reg descr   (fun v => try_catch (k v) h)
+  | Excl_res k =>         Excl_res         (fun v => try_catch (k v) h)
+  | Undefined k =>        Undefined        (fun v => try_catch (k v) h)
+  | Write_ea wk a sz k => Write_ea wk a sz (try_catch k h)
+  | Footprint k =>        Footprint        (try_catch k h)
+  | Barrier bk k =>       Barrier bk       (try_catch k h)
+  | Write_reg r v k =>    Write_reg r v    (try_catch k h)
+  | Fail descr =>         Fail descr
+  | Error descr =>        Error descr
+  | Exception e =>        h e
+end.
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is "either r e", where "inr e"
+   represents a proper exception and "inl r" an early return : value "r". *)
+Definition monadR rv a r e := monad rv a (sum r e).
+
+(*val early_return : forall rv a r e. r -> monadR rv a r e*)
+Definition early_return {rv A R E} (r : R) : monadR rv A R E := throw (inl r).
+
+(*val catch_early_return : forall rv a e. monadR rv a a e -> monad rv a e*)
+Definition catch_early_return {rv A E} (m : monadR rv A A E) :=
+  try_catch m
+    (fun r => match r with
+      | inl a => returnm a
+      | inr e => throw e
+     end).
+
+(* Lift to monad with early return by wrapping exceptions *)
+(*val liftR : forall rv a r e. monad rv a e -> monadR rv a r e*)
+Definition liftR {rv A R E} (m : monad rv A E) : monadR rv A R E :=
+ try_catch m (fun e => throw (inr e)).
+
+(* Catch exceptions in the presence : early returns *)
+(*val try_catchR : forall rv a r e1 e2. monadR rv a r e1 -> (e1 -> monadR rv a r e2) ->  monadR rv a r e2*)
+Definition try_catchR {rv A R E1 E2} (m : monadR rv A R E1) (h : E1 -> monadR rv A R E2) :=
+  try_catch m
+    (fun r => match r with
+      | inl r => throw (inl r)
+      | inr e => h e
+     end).
+
+(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*)
+Definition maybe_fail {rv A E} msg (x : option A) : monad rv A E :=
+match x with
+  | Some a => returnm a
+  | None => Fail msg
+end.
+
+(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*)
+Definition read_mem_bytes {rv A E} rk (addr : mword A) sz : monad rv (list memory_byte) E :=
+  Read_mem rk (bits_of addr) (Z.to_nat sz) returnm.
+
+(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*)
+Definition read_mem {rv A B E} `{ArithFact (B >= 0)} rk (addr : mword A) sz : monad rv (mword B) E :=
+  bind
+    (read_mem_bytes rk addr sz)
+    (fun bytes =>
+       maybe_fail "bits_of_mem_bytes" (of_bits (bits_of_mem_bytes bytes))).
+
+(*val read_tag : forall rv a e. Bitvector a => a -> monad rv bitU e*)
+Definition read_tag {rv a e} `{Bitvector a} (addr : a) : monad rv bitU e :=
+ Read_tag (bits_of addr) returnm.
+
+(*val excl_result : forall rv e. unit -> monad rv bool e*)
+Definition excl_result {rv e} (_:unit) : monad rv bool e :=
+  let k successful := (returnm successful) in
+  Excl_res k.
+
+Definition write_mem_ea {rv a E} `{Bitvector a} wk (addr: a) sz : monad rv unit E :=
+ Write_ea wk (bits_of addr) (Z.to_nat sz) (Done tt).
+
+Definition write_mem_val {rv a e} `{Bitvector a} (v : a) : monad rv bool e := match mem_bytes_of_bits v with
+  | Some v => Write_memv v returnm
+  | None => Fail "write_mem_val"
+end.
+
+(*val write_tag : forall rv a e. Bitvector 'a => 'a -> bitU -> monad rv bool e*)
+Definition write_tag {rv a e} (addr : mword a) (b : bitU) : monad rv bool e := Write_tag (bits_of addr) b returnm.
+
+Definition read_reg {s rv a e} (reg : register_ref s rv a) : monad rv a e :=
+  let k v :=
+    match reg.(of_regval) v with
+      | Some v => Done v
+      | None => Error "read_reg: unrecognised value"
+    end
+  in
+  Read_reg reg.(name) k.
+
+(* TODO
+val read_reg_range : forall s r rv a e. Bitvector a => register_ref s rv r -> integer -> integer -> monad rv a e
+Definition read_reg_range reg i j :=
+  read_reg_aux of_bits (external_reg_slice reg (natFromInteger i,natFromInteger j))
+
+Definition read_reg_bit reg i :=
+  read_reg_aux (fun v -> v) (external_reg_slice reg (natFromInteger i,natFromInteger i)) >>= fun v ->
+  returnm (extract_only_element v)
+
+Definition read_reg_field reg regfield :=
+  read_reg_aux (external_reg_field_whole reg regfield)
+
+Definition read_reg_bitfield reg regfield :=
+  read_reg_aux (external_reg_field_whole reg regfield) >>= fun v ->
+  returnm (extract_only_element v)*)
+
+Definition reg_deref {s rv a e} := @read_reg s rv a e.
+
+(*Parameter write_reg : forall {s rv a e}, register_ref s rv a -> a -> monad rv unit e.*)
+Definition write_reg {s rv a e} (reg : register_ref s rv a) (v : a) : monad rv unit e :=
+ Write_reg reg.(name) (reg.(regval_of) v) (Done tt).
+
+(* TODO
+Definition write_reg reg v :=
+  write_reg_aux (external_reg_whole reg) v
+Definition write_reg_range reg i j v :=
+  write_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) v
+Definition write_reg_pos reg i v :=
+  let iN := natFromInteger i in
+  write_reg_aux (external_reg_slice reg (iN,iN)) [v]
+Definition write_reg_bit := write_reg_pos
+Definition write_reg_field reg regfield v :=
+  write_reg_aux (external_reg_field_whole reg regfield.field_name) v
+Definition write_reg_field_bit reg regfield bit :=
+  write_reg_aux (external_reg_field_whole reg regfield.field_name)
+                (Vector [bit] 0 (is_inc_of_reg reg))
+Definition write_reg_field_range reg regfield i j v :=
+  write_reg_aux (external_reg_field_slice reg regfield.field_name (natFromInteger i,natFromInteger j)) v
+Definition write_reg_field_pos reg regfield i v :=
+  write_reg_field_range reg regfield i i [v]
+Definition write_reg_field_bit := write_reg_field_pos*)
+
+(*val barrier : forall rv e. barrier_kind -> monad rv unit e*)
+Definition barrier {rv e} bk : monad rv unit e := Barrier bk (Done tt).
+
+(*val footprint : forall rv e. unit -> monad rv unit e*)
+Definition footprint {rv e} (_ : unit) : monad rv unit e := Footprint (Done tt).
diff --git a/snapshots/coq/lib/coq/Sail2_state.v b/snapshots/coq/lib/coq/Sail2_state.v
new file mode 100644
index 00000000..404309e0
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_state.v
@@ -0,0 +1,74 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(*Require Import Sail_impl_base*)
+Require Import Sail2_values.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state_monad.
+(*
+(* State monad wrapper around prompt monad *)
+
+val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e
+let rec liftState ra s = match s with
+  | (Done a)             -> returnS a
+  | (Read_mem rk a sz k) -> bindS (read_mem_bytesS rk a sz) (fun v -> liftState ra (k v))
+  | (Read_tag t k)       -> bindS (read_tagS t)             (fun v -> liftState ra (k v))
+  | (Write_memv a k)     -> bindS (write_mem_bytesS a)      (fun v -> liftState ra (k v))
+  | (Write_tagv t k)     -> bindS (write_tagS t)            (fun v -> liftState ra (k v))
+  | (Read_reg r k)       -> bindS (read_regvalS ra r)       (fun v -> liftState ra (k v))
+  | (Excl_res k)         -> bindS (excl_resultS ())         (fun v -> liftState ra (k v))
+  | (Undefined k)        -> bindS (undefined_boolS ())      (fun v -> liftState ra (k v))
+  | (Write_ea wk a sz k) -> seqS (write_mem_eaS wk a sz)    (liftState ra k)
+  | (Write_reg r v k)    -> seqS (write_regvalS ra r v)     (liftState ra k)
+  | (Footprint k)        -> liftState ra k
+  | (Barrier _ k)        -> liftState ra k
+  | (Fail descr)         -> failS descr
+  | (Error descr)        -> failS descr
+  | (Exception e)        -> throwS e
+end
+
+
+val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let rec iterS_aux i f xs = match xs with
+  | x :: xs -> f i x >>$ iterS_aux (i + 1) f xs
+  | [] -> returnS ()
+  end
+
+declare {isabelle} termination_argument iterS_aux = automatic
+
+val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let iteriS f xs = iterS_aux 0 f xs
+
+val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e
+let iterS f xs = iteriS (fun _ x -> f x) xs
+
+val foreachS : forall 'a 'rv 'vars 'e.
+  list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec foreachS xs vars body = match xs with
+  | [] -> returnS vars
+  | x :: xs ->
+     body x vars >>$= fun vars ->
+     foreachS xs vars body
+end
+
+declare {isabelle} termination_argument foreachS = automatic
+
+
+val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec whileS vars cond body s =
+  (cond vars >>$= (fun cond_val s' ->
+  if cond_val then
+    (body vars >>$= (fun vars s'' -> whileS vars cond body s'')) s'
+  else returnS vars s')) s
+
+val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) ->
+                ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e
+let rec untilS vars cond body s =
+  (body vars >>$= (fun vars s' ->
+  (cond vars >>$= (fun cond_val s'' ->
+  if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_state_monad.v b/snapshots/coq/lib/coq/Sail2_state_monad.v
new file mode 100644
index 00000000..5258c37a
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_state_monad.v
@@ -0,0 +1,258 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+(*
+(* 'a is result type *)
+
+type memstate = map integer memory_byte
+type tagstate = map integer bitU
+(* type regstate = map string (vector bitU) *)
+
+type sequential_state 'regs =
+  <| regstate : 'regs;
+     memstate : memstate;
+     tagstate : tagstate;
+     write_ea : maybe (write_kind * integer * integer);
+     last_exclusive_operation_was_load : bool|>
+
+val init_state : forall 'regs. 'regs -> sequential_state 'regs
+let init_state regs =
+  <| regstate = regs;
+     memstate = Map.empty;
+     tagstate = Map.empty;
+     write_ea = Nothing;
+     last_exclusive_operation_was_load = false |>
+
+type ex 'e =
+  | Failure of string
+  | Throw of 'e
+
+type result 'a 'e =
+  | Value of 'a
+  | Ex of (ex 'e)
+
+(* State, nondeterminism and exception monad with result value type 'a
+   and exception type 'e. *)
+type monadS 'regs 'a 'e = sequential_state 'regs -> list (result 'a 'e * sequential_state 'regs)
+
+val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e
+let returnS a s = [(Value a,s)]
+
+val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e
+let bindS m f (s : sequential_state 'regs) =
+  List.concatMap (function
+                  | (Value a, s') -> f a s'
+                  | (Ex e, s') -> [(Ex e, s')]
+                  end) (m s)
+
+val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e
+let seqS m n = bindS m (fun (_ : unit) -> n)
+
+let inline (>>$=) = bindS
+let inline (>>$) = seqS
+
+val chooseS : forall 'regs 'a 'e. list 'a -> monadS 'regs 'a 'e
+let chooseS xs s = List.map (fun x -> (Value x, s)) xs
+
+val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e
+let readS f = (fun s -> returnS (f s) s)
+
+val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e
+let updateS f = (fun s -> returnS () (f s))
+
+val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e
+let failS msg s = [(Ex (Failure msg), s)]
+
+val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e
+let exitS () = failS "exit"
+
+val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e
+let throwS e s = [(Ex (Throw e), s)]
+
+val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) ->  monadS 'regs 'a 'e2
+let try_catchS m h s =
+  List.concatMap (function
+                  | (Value a, s') -> returnS a s'
+                  | (Ex (Throw e), s') -> h e s'
+                  | (Ex (Failure msg), s') -> [(Ex (Failure msg), s')]
+                  end) (m s)
+
+val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e
+let assert_expS exp msg = if exp then returnS () else failS msg
+
+(* For early return, we abuse exceptions by throwing and catching
+   the return value. The exception type is "either 'r 'e", where "Right e"
+   represents a proper exception and "Left r" an early return of value "r". *)
+type monadSR 'regs 'a 'r 'e = monadS 'regs 'a (either 'r 'e)
+
+val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e
+let early_returnS r = throwS (Left r)
+
+val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e
+let catch_early_returnS m =
+  try_catchS m
+    (function
+      | Left a -> returnS a
+      | Right e -> throwS e
+     end)
+
+(* Lift to monad with early return by wrapping exceptions *)
+val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e
+let liftSR m = try_catchS m (fun e -> throwS (Right e))
+
+(* Catch exceptions in the presence of early returns *)
+val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) ->  monadSR 'regs 'a 'r 'e2
+let try_catchSR m h =
+  try_catchS m
+    (function
+      | Left r -> throwS (Left r)
+      | Right e -> h e
+     end)
+
+val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e
+let read_tagS addr =
+  readS (fun s -> fromMaybe B0 (Map.lookup (unsigned addr) s.tagstate))
+
+(* Read bytes from memory and return in little endian order *)
+val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e
+let read_mem_bytesS read_kind addr sz =
+  let addr = unsigned addr in
+  let sz = integerFromNat sz in
+  let addrs = index_list addr (addr+sz-1) 1 in
+  let read_byte s addr = Map.lookup addr s.memstate in
+  readS (fun s -> just_list (List.map (read_byte s) addrs)) >>$= (function
+    | Just mem_val ->
+       updateS (fun s ->
+         if read_is_exclusive read_kind
+         then <| s with last_exclusive_operation_was_load = true |>
+         else s) >>$
+       returnS mem_val
+    | Nothing -> failS "read_memS"
+  end)
+
+val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e
+let read_memS rk a sz =
+  read_mem_bytesS rk a (natFromInteger sz) >>$= (fun bytes ->
+  returnS (bits_of_mem_bytes bytes))
+
+val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e
+let excl_resultS () =
+  readS (fun s -> s.last_exclusive_operation_was_load) >>$= (fun excl_load ->
+  updateS (fun s -> <| s with last_exclusive_operation_was_load = false |>) >>$
+  chooseS (if excl_load then [false; true] else [false]))
+
+val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e
+let write_mem_eaS write_kind addr sz =
+  let addr = unsigned addr in
+  let sz = integerFromNat sz in
+  updateS (fun s -> <| s with write_ea = Just (write_kind, addr, sz) |>)
+
+(* Write little-endian list of bytes to previously announced address *)
+val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e
+let write_mem_bytesS v =
+  readS (fun s -> s.write_ea) >>$= (function
+      | Nothing -> failS "write ea has not been announced yet"
+      | Just (_, addr, sz) ->
+         let addrs = index_list addr (addr+sz-1) 1 in
+         (*let v = external_mem_value (bits_of v) in*)
+         let a_v = List.zip addrs v in
+         let write_byte mem (addr, v) = Map.insert addr v mem in
+         updateS (fun s ->
+           <| s with memstate = List.foldl write_byte s.memstate a_v |>) >>$
+         returnS true
+    end)
+
+val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e
+let write_mem_valS v = match mem_bytes_of_bits v with
+  | Just v -> write_mem_bytesS v
+  | Nothing -> failS "write_mem_val"
+end
+
+val write_tagS : forall 'regs 'e. bitU -> monadS 'regs bool 'e
+let write_tagS t =
+  readS (fun s -> s.write_ea) >>$= (function
+      | Nothing -> failS "write ea has not been announced yet"
+      | Just (_, addr, _) ->
+         (*let taddr = addr / cap_alignment in*)
+         updateS (fun s -> <| s with tagstate = Map.insert addr t s.tagstate |>) >>$
+         returnS true
+    end)
+
+val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e
+let read_regS reg = readS (fun s -> reg.read_from s.regstate)
+
+(* TODO
+let read_reg_range reg i j state =
+  let v = slice (get_reg state (name_of_reg reg)) i j in
+  [(Value (vec_to_bvec v),state)]
+let read_reg_bit reg i state =
+  let v = access (get_reg state (name_of_reg reg)) i in
+  [(Value v,state)]
+let read_reg_field reg regfield =
+  let (i,j) = register_field_indices reg regfield in
+  read_reg_range reg i j
+let read_reg_bitfield reg regfield =
+  let (i,_) = register_field_indices reg regfield in
+  read_reg_bit reg i *)
+
+val read_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e
+let read_regvalS (read, _) reg =
+  readS (fun s -> read reg s.regstate) >>$= (function
+      | Just v ->  returnS v
+      | Nothing -> failS ("read_regvalS " ^ reg)
+    end)
+
+val write_regvalS : forall 'regs 'rv 'e.
+  register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e
+let write_regvalS (_, write) reg v =
+  readS (fun s -> write reg v s.regstate) >>$= (function
+      | Just rs' -> updateS (fun s -> <| s with regstate = rs' |>)
+      | Nothing ->  failS ("write_regvalS " ^ reg)
+    end)
+
+val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e
+let write_regS reg v =
+  updateS (fun s -> <| s with regstate = reg.write_to v s.regstate |>)
+
+(* TODO
+val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e
+let update_reg reg f v state =
+  let current_value = get_reg state reg in
+  let new_value = f current_value v in
+  [(Value (), set_reg state reg new_value)]
+
+let write_reg_field reg regfield = update_reg reg regfield.set_field
+
+val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a
+let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val)
+let write_reg_range reg i j = update_reg reg (update_reg_range reg i j)
+
+let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x
+let write_reg_pos reg i = update_reg reg (update_reg_pos reg i)
+
+let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit)
+let write_reg_bit reg i = update_reg reg (update_reg_bit reg i)
+
+let update_reg_field_range regfield i j reg_val new_val =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j)
+
+let update_reg_field_pos regfield i reg_val x =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = update_list regfield.field_is_inc current_field_value i x in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i)
+
+let update_reg_field_bit regfield i reg_val bit =
+  let current_field_value = regfield.get_field reg_val in
+  let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in
+  regfield.set_field reg_val new_field_value
+let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*)
+*)
diff --git a/snapshots/coq/lib/coq/Sail2_values.v b/snapshots/coq/lib/coq/Sail2_values.v
new file mode 100644
index 00000000..f1f5f1de
--- /dev/null
+++ b/snapshots/coq/lib/coq/Sail2_values.v
@@ -0,0 +1,1576 @@
+(*========================================================================*)
+(*  Copyright (c) 2018 Sail contributors.                                 *)
+(*  This material is provided for anonymous review purposes only.         *)
+(*========================================================================*)
+
+(* Version of sail_values.lem that uses Lems machine words library *)
+
+(*Require Import Sail_impl_base*)
+Require Export ZArith.
+Require Import Ascii.
+Require Export String.
+Require Import bbv.Word.
+Require Export List.
+Require Export Sumbool.
+Require Export DecidableClass.
+Import ListNotations.
+
+Open Scope Z.
+
+(* Constraint solving basics.  A HintDb which unfolding hints and lemmata
+   can be added to, and a typeclass to wrap constraint arguments in to
+   trigger automatic solving. *)
+Create HintDb sail.
+Class ArithFact (P : Prop) := { fact : P }.
+Lemma use_ArithFact {P} `(ArithFact P) : P.
+apply fact.
+Defined.
+
+Definition build_ex (n:Z) {P:Z -> Prop} `{H:ArithFact (P n)} : {x : Z & ArithFact (P x)} :=
+  existT _ n H.
+
+Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness.
+Definition generic_neq {T:Type} (x y:T) `{Decidable (x = y)} := negb Decidable_witness.
+Lemma generic_eq_true {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = true -> x = y.
+apply Decidable_spec.
+Qed.
+Lemma generic_eq_false {T} {x y:T} `{Decidable (x = y)} : generic_eq x y = false -> x <> y.
+unfold generic_eq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+congruence.
+Qed.
+Lemma generic_neq_true {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = true -> x <> y.
+unfold generic_neq.
+intros H1 H2.
+rewrite <- Decidable_spec in H2.
+destruct Decidable_witness; simpl in *; 
+congruence.
+Qed.
+Lemma generic_neq_false {T} {x y:T} `{Decidable (x = y)} : generic_neq x y = false -> x = y.
+unfold generic_neq.
+intro H1.
+rewrite <- Decidable_spec.
+destruct Decidable_witness; simpl in *; 
+congruence.
+Qed.
+Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> y}) : 
+  forall (x y : T), Decidable (eq x y) := {
+  Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y))
+}.
+destruct (eqdec x y); simpl; split; congruence.
+Qed.
+
+
+(* Project away range constraints in comparisons *)
+Definition ltb_range_l {P} (l : sigT P) r := Z.ltb (projT1 l) r.
+Definition leb_range_l {P} (l : sigT P) r := Z.leb (projT1 l) r.
+Definition gtb_range_l {P} (l : sigT P) r := Z.gtb (projT1 l) r.
+Definition geb_range_l {P} (l : sigT P) r := Z.geb (projT1 l) r.
+Definition ltb_range_r {P} l (r : sigT P) := Z.ltb l (projT1 r).
+Definition leb_range_r {P} l (r : sigT P) := Z.leb l (projT1 r).
+Definition gtb_range_r {P} l (r : sigT P) := Z.gtb l (projT1 r).
+Definition geb_range_r {P} l (r : sigT P) := Z.geb l (projT1 r).
+
+Definition ii := Z.
+Definition nn := nat.
+
+(*val pow : Z -> Z -> Z*)
+Definition pow m n := m ^ n.
+
+Definition pow2 n := pow 2 n.
+(*
+Definition inline lt := (<)
+Definition inline gt := (>)
+Definition inline lteq := (<=)
+Definition inline gteq := (>=)
+
+val eq : forall a. Eq a => a -> a -> bool
+Definition inline eq l r := (l = r)
+
+val neq : forall a. Eq a => a -> a -> bool*)
+Definition neq l r := (negb (l =? r)). (* Z only *)
+
+(*let add_int l r := integerAdd l r
+Definition add_signed l r := integerAdd l r
+Definition sub_int l r := integerMinus l r
+Definition mult_int l r := integerMult l r
+Definition div_int l r := integerDiv l r
+Definition div_nat l r := natDiv l r
+Definition power_int_nat l r := integerPow l r
+Definition power_int_int l r := integerPow l (Z.to_nat r)
+Definition negate_int i := integerNegate i
+Definition min_int l r := integerMin l r
+Definition max_int l r := integerMax l r
+
+Definition add_real l r := realAdd l r
+Definition sub_real l r := realMinus l r
+Definition mult_real l r := realMult l r
+Definition div_real l r := realDiv l r
+Definition negate_real r := realNegate r
+Definition abs_real r := realAbs r
+Definition power_real b e := realPowInteger b e*)
+
+Definition print_int (_ : string) (_ : Z) : unit := tt.
+
+(*
+Definition or_bool l r := (l || r)
+Definition and_bool l r := (l && r)
+Definition xor_bool l r := xor l r
+*)
+Definition append_list {A:Type} (l : list A) r := l ++ r.
+Definition length_list {A:Type} (xs : list A) := Z.of_nat (List.length xs).
+Definition take_list {A:Type} n (xs : list A) := firstn (Z.to_nat n) xs.
+Definition drop_list {A:Type} n (xs : list A) := skipn (Z.to_nat n) xs.
+(*
+val repeat : forall a. list a -> Z -> list a*)
+Fixpoint repeat' {a} (xs : list a) n :=
+  match n with
+  | O => []
+  | S n => xs ++ repeat' xs n
+  end.
+Lemma repeat'_length {a} {xs : list a} {n : nat} : List.length (repeat' xs n) = (n * List.length xs)%nat.
+induction n.
+* reflexivity.
+* simpl.
+  rewrite app_length.
+  auto with arith.
+Qed.
+Definition repeat {a} (xs : list a) (n : Z) :=
+  if n <=? 0 then []
+  else repeat' xs (Z.to_nat n).
+Lemma repeat_length {a} {xs : list a} {n : Z} (H : n >= 0) : length_list (repeat xs n) = n * length_list xs.
+unfold length_list, repeat.
+destruct n.
++ reflexivity. 
++ simpl (List.length _).
+  rewrite repeat'_length.
+  rewrite Nat2Z.inj_mul.
+  rewrite positive_nat_Z.
+  reflexivity.  
++ exfalso.
+  auto with zarith.
+Qed.
+
+(*declare {isabelle} termination_argument repeat = automatic
+
+Definition duplicate_to_list bit length := repeat [bit] length
+
+Fixpoint replace bs (n : Z) b' := match bs with
+  | [] => []
+  | b :: bs =>
+     if n = 0 then b' :: bs
+              else b :: replace bs (n - 1) b'
+  end
+declare {isabelle} termination_argument replace = automatic
+
+Definition upper n := n
+
+(* Modulus operation corresponding to quot below -- result
+   has sign of dividend. *)
+Definition hardware_mod (a: Z) (b:Z) : Z :=
+  let m := (abs a) mod (abs b) in
+  if a < 0 then ~m else m
+
+(* There are different possible answers for integer divide regarding
+rounding behaviour on negative operands. Positive operands always
+round down so derive the one we want (trucation towards zero) from
+that *)
+Definition hardware_quot (a:Z) (b:Z) : Z :=
+  let q := (abs a) / (abs b) in
+  if ((a<0) = (b<0)) then
+    q  (* same sign -- result positive *)
+  else
+    ~q (* different sign -- result negative *)
+
+Definition max_64u := (integerPow 2 64) - 1
+Definition max_64  := (integerPow 2 63) - 1
+Definition min_64  := 0 - (integerPow 2 63)
+Definition max_32u := (4294967295 : Z)
+Definition max_32  := (2147483647 : Z)
+Definition min_32  := (0 - 2147483648 : Z)
+Definition max_8   := (127 : Z)
+Definition min_8   := (0 - 128 : Z)
+Definition max_5   := (31 : Z)
+Definition min_5   := (0 - 32 : Z)
+*)
+
+(* just_list takes a list of maybes and returns Some xs if all elements have
+   a value, and None if one of the elements is None. *)
+(*val just_list : forall a. list (option a) -> option (list a)*)
+Fixpoint just_list {A} (l : list (option A)) := match l with
+  | [] => Some []
+  | (x :: xs) =>
+    match (x, just_list xs) with
+      | (Some x, Some xs) => Some (x :: xs)
+      | (_, _) => None
+    end
+  end.
+(*declare {isabelle} termination_argument just_list = automatic
+
+lemma just_list_spec:
+  ((forall xs. (just_list xs = None) <-> List.elem None xs) &&
+   (forall xs es. (just_list xs = Some es) <-> (xs = List.map Some es)))*)
+
+Lemma just_list_length {A} : forall (l : list (option A)) (l' : list A),
+  Some l' = just_list l -> List.length l = List.length l'.
+induction l.
+* intros.
+  simpl in H.
+  inversion H.
+  reflexivity.
+* intros.
+  destruct a; simplify_eq H.
+  simpl in *.
+  destruct (just_list l); simplify_eq H.
+  intros.
+  subst.
+  simpl.
+  f_equal.
+  apply IHl.
+  reflexivity.
+Qed.
+
+Lemma just_list_length_Z {A} : forall (l : list (option A)) l', Some l' = just_list l -> length_list l = length_list l'.
+unfold length_list.
+intros.
+f_equal.
+auto using just_list_length.
+Qed.
+
+(*** Bits *)
+Inductive bitU := B0 | B1 | BU.
+
+Definition showBitU b :=
+match b with
+  | B0 => "O"
+  | B1 => "I"
+  | BU => "U"
+end%string.
+
+Definition bitU_char b :=
+match b with
+| B0 => "0"
+| B1 => "1"
+| BU => "?"
+end%char.
+
+(*instance (Show bitU)
+  let show := showBitU
+end*)
+
+Class BitU (a : Type) : Type := {
+  to_bitU : a -> bitU;
+  of_bitU : bitU -> a
+}.
+
+Instance bitU_BitU : (BitU bitU) := {
+  to_bitU b := b;
+  of_bitU b := b
+}.
+
+Definition bool_of_bitU bu := match bu with
+  | B0 => Some false
+  | B1 => Some true
+  | BU => None
+  end.
+
+Definition bitU_of_bool (b : bool) := if b then B1 else B0.
+
+(*Instance bool_BitU : (BitU bool) := {
+  to_bitU := bitU_of_bool;
+  of_bitU := bool_of_bitU
+}.*)
+
+Definition cast_bit_bool := bool_of_bitU.
+(*
+Definition bit_lifted_of_bitU bu := match bu with
+  | B0 => Bitl_zero
+  | B1 => Bitl_one
+  | BU => Bitl_undef
+  end.
+
+Definition bitU_of_bit := function
+  | Bitc_zero => B0
+  | Bitc_one  => B1
+  end.
+
+Definition bit_of_bitU := function
+  | B0 => Bitc_zero
+  | B1 => Bitc_one
+  | BU => failwith "bit_of_bitU: BU"
+  end.
+
+Definition bitU_of_bit_lifted := function
+  | Bitl_zero => B0
+  | Bitl_one  => B1
+  | Bitl_undef => BU
+  | Bitl_unknown => failwith "bitU_of_bit_lifted Bitl_unknown"
+  end.
+*)
+Definition not_bit b :=
+match b with
+  | B1 => B0
+  | B0 => B1
+  | BU => BU
+  end.
+
+(*val is_one : Z -> bitU*)
+Definition is_one (i : Z) :=
+  if i =? 1 then B1 else B0.
+
+Definition binop_bit op x y :=
+  match (x, y) with
+  | (BU,_) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+  | (_,BU) => BU (*Do we want to do this or to respect | of I and & of B0 rules?*)
+  | (x,y) => bitU_of_bool (op (bool_of_bitU x) (bool_of_bitU y))
+  end.
+
+(*val and_bit : bitU -> bitU -> bitU
+Definition and_bit := binop_bit (&&)
+
+val or_bit : bitU -> bitU -> bitU
+Definition or_bit := binop_bit (||)
+
+val xor_bit : bitU -> bitU -> bitU
+Definition xor_bit := binop_bit xor
+
+val (&.) : bitU -> bitU -> bitU
+Definition inline (&.) x y := and_bit x y
+
+val (|.) : bitU -> bitU -> bitU
+Definition inline (|.) x y := or_bit x y
+
+val (+.) : bitU -> bitU -> bitU
+Definition inline (+.) x y := xor_bit x y
+*)
+
+(*** Bool lists ***)
+
+(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*)
+Fixpoint bools_of_nat_aux len (x : nat) (acc : list bool) : list bool :=
+  match len with
+  | O => acc
+  | S len' => bools_of_nat_aux len' (x / 2) ((if x mod 2 =? 1 then true else false) :: acc)
+  end %nat.
+  (*else (if x mod 2 = 1 then true else false) :: bools_of_nat_aux (x / 2)*)
+(*declare {isabelle} termination_argument bools_of_nat_aux = automatic*)
+Definition bools_of_nat len n := bools_of_nat_aux (Z.to_nat len) n [] (*List.reverse (bools_of_nat_aux n)*).
+
+(*val nat_of_bools_aux : natural -> list bool -> natural*)
+Fixpoint nat_of_bools_aux (acc : nat) (bs : list bool) : nat :=
+  match bs with
+  | [] => acc
+  | true :: bs => nat_of_bools_aux ((2 * acc) + 1) bs
+  | false :: bs => nat_of_bools_aux (2 * acc) bs
+end.
+(*declare {isabelle; hol} termination_argument nat_of_bools_aux = automatic*)
+Definition nat_of_bools bs := nat_of_bools_aux 0 bs.
+
+(*val unsigned_of_bools : list bool -> integer*)
+Definition unsigned_of_bools bs := Z.of_nat (nat_of_bools bs).
+
+(*val signed_of_bools : list bool -> integer*)
+Definition signed_of_bools bs :=
+  match bs with
+    | true :: _  => 0 - (1 + (unsigned_of_bools (List.map negb bs)))
+    | false :: _ => unsigned_of_bools bs
+    | [] => 0 (* Treat empty list as all zeros *)
+  end.
+
+(*val int_of_bools : bool -> list bool -> integer*)
+Definition int_of_bools (sign : bool) bs := if sign then signed_of_bools bs else unsigned_of_bools bs.
+
+(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*)
+Fixpoint pad_list_nat {a} (x : a) (xs : list a) n :=
+  match n with
+  | O => xs
+  | S n' => pad_list_nat x (x :: xs) n'
+  end.
+(*declare {isabelle} termination_argument pad_list = automatic*)
+Definition pad_list {a} x xs n := @pad_list_nat a x xs (Z.to_nat n).
+
+Definition ext_list {a} pad len (xs : list a) :=
+  let longer := len - (Z.of_nat (List.length xs)) in
+  if longer <? 0 then skipn (Z.abs_nat (longer)) xs
+  else pad_list pad xs longer.
+
+(*let extz_bools len bs = ext_list false len bs*)
+Definition exts_bools len bs :=
+  match bs with
+    | true :: _ => ext_list true len bs
+    | _ => ext_list false len bs
+  end.
+
+Fixpoint add_one_bool_ignore_overflow_aux bits := match bits with
+  | [] => []
+  | false :: bits => true :: bits
+  | true :: bits => false :: add_one_bool_ignore_overflow_aux bits
+end.
+(*declare {isabelle; hol} termination_argument add_one_bool_ignore_overflow_aux = automatic*)
+
+Definition add_one_bool_ignore_overflow bits :=
+  List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)).
+
+(*let bool_list_of_int n =
+  let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in
+  if n >= (0 : integer) then bs_abs
+  else add_one_bool_ignore_overflow (List.map not bs_abs)
+let bools_of_int len n = exts_bools len (bool_list_of_int n)*)
+Definition bools_of_int len n :=
+  let bs_abs := bools_of_nat len (Z.abs_nat n) in
+  if n >=? 0 then bs_abs
+  else add_one_bool_ignore_overflow (List.map negb bs_abs).
+
+(*** Bit lists ***)
+
+(*val bits_of_nat_aux : natural -> list bitU*)
+Fixpoint bits_of_nat_aux n x :=
+  match n,x with
+  | O,_ => []
+  | _,O => []
+  | S n, S _ => (if x mod 2 =? 1 then B1 else B0) :: bits_of_nat_aux n (x / 2)
+  end%nat.
+(**declare {isabelle} termination_argument bits_of_nat_aux = automatic*)
+Definition bits_of_nat n := List.rev (bits_of_nat_aux n n).
+
+(*val nat_of_bits_aux : natural -> list bitU -> natural*)
+Fixpoint nat_of_bits_aux acc bs := match bs with
+  | [] => Some acc
+  | B1 :: bs => nat_of_bits_aux ((2 * acc) + 1) bs
+  | B0 :: bs => nat_of_bits_aux (2 * acc) bs
+  | BU :: bs => None
+end%nat.
+(*declare {isabelle} termination_argument nat_of_bits_aux = automatic*)
+Definition nat_of_bits bits := nat_of_bits_aux 0 bits.
+
+Definition not_bits := List.map not_bit.
+
+Definition binop_bits op bsl bsr :=
+  List.fold_right (fun '(bl, br) acc => binop_bit op bl br :: acc) [] (List.combine bsl bsr).
+(*
+Definition and_bits := binop_bits (&&)
+Definition or_bits := binop_bits (||)
+Definition xor_bits := binop_bits xor
+
+val unsigned_of_bits : list bitU -> Z*)
+Definition unsigned_of_bits bits :=
+match just_list (List.map bool_of_bitU bits) with
+| Some bs => Some (unsigned_of_bools bs)
+| None => None
+end.
+
+(*val signed_of_bits : list bitU -> Z*)
+Definition signed_of_bits bits :=
+  match just_list (List.map bool_of_bitU bits) with
+  | Some bs => Some (signed_of_bools bs)
+  | None => None
+  end.
+
+(*val int_of_bits : bool -> list bitU -> maybe integer*)
+Definition int_of_bits (sign : bool) bs :=
+ if sign then signed_of_bits bs else unsigned_of_bits bs.
+
+(*val pad_bitlist : bitU -> list bitU -> Z -> list bitU*)
+Fixpoint pad_bitlist_nat (b : bitU) bits n :=
+match n with
+| O => bits
+| S n' => pad_bitlist_nat b (b :: bits) n'
+end.
+Definition pad_bitlist b bits n := pad_bitlist_nat b bits (Z.to_nat n). (* Negative n will come out as 0 *)
+(*  if n <= 0 then bits else pad_bitlist b (b :: bits) (n - 1).
+declare {isabelle} termination_argument pad_bitlist = automatic*)
+
+Definition ext_bits pad len bits :=
+  let longer := len - (Z.of_nat (List.length bits)) in
+  if longer <? 0 then skipn (Z.abs_nat longer) bits
+  else pad_bitlist pad bits longer.
+
+Definition extz_bits len bits := ext_bits B0 len bits.
+Parameter undefined_list_bitU : list bitU.
+Definition exts_bits len bits :=
+  match bits with
+  | BU :: _ => undefined_list_bitU (*failwith "exts_bits: undefined bit"*)
+  | B1 :: _ => ext_bits B1 len bits
+  | _ => ext_bits B0 len bits
+  end.
+
+Fixpoint add_one_bit_ignore_overflow_aux bits := match bits with
+  | [] => []
+  | B0 :: bits => B1 :: bits
+  | B1 :: bits => B0 :: add_one_bit_ignore_overflow_aux bits
+  | BU :: _ => undefined_list_bitU (*failwith "add_one_bit_ignore_overflow: undefined bit"*)
+end.
+(*declare {isabelle} termination_argument add_one_bit_ignore_overflow_aux = automatic*)
+
+Definition add_one_bit_ignore_overflow bits :=
+  rev (add_one_bit_ignore_overflow_aux (rev bits)).
+
+Definition bitlist_of_int n :=
+  let bits_abs := B0 :: bits_of_nat (Z.abs_nat n) in
+  if n >=? 0 then bits_abs
+  else add_one_bit_ignore_overflow (not_bits bits_abs).
+
+Definition bits_of_int len n := exts_bits len (bitlist_of_int n).
+
+(*val arith_op_bits :
+  (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*)
+Definition arith_op_bits (op : Z -> Z -> Z) (sign : bool) l r :=
+  match (int_of_bits sign l, int_of_bits sign r) with
+    | (Some li, Some ri) => bits_of_int (length_list l) (op li ri)
+    | (_, _) => repeat [BU] (length_list l)
+  end.
+
+
+Definition char_of_nibble x :=
+  match x with
+  | (B0, B0, B0, B0) => Some "0"%char
+  | (B0, B0, B0, B1) => Some "1"%char
+  | (B0, B0, B1, B0) => Some "2"%char
+  | (B0, B0, B1, B1) => Some "3"%char
+  | (B0, B1, B0, B0) => Some "4"%char
+  | (B0, B1, B0, B1) => Some "5"%char
+  | (B0, B1, B1, B0) => Some "6"%char
+  | (B0, B1, B1, B1) => Some "7"%char
+  | (B1, B0, B0, B0) => Some "8"%char
+  | (B1, B0, B0, B1) => Some "9"%char
+  | (B1, B0, B1, B0) => Some "A"%char
+  | (B1, B0, B1, B1) => Some "B"%char
+  | (B1, B1, B0, B0) => Some "C"%char
+  | (B1, B1, B0, B1) => Some "D"%char
+  | (B1, B1, B1, B0) => Some "E"%char
+  | (B1, B1, B1, B1) => Some "F"%char
+  | _ => None
+  end.
+
+Fixpoint hexstring_of_bits bs := match bs with
+  | b1 :: b2 :: b3 :: b4 :: bs =>
+     let n := char_of_nibble (b1, b2, b3, b4) in
+     let s := hexstring_of_bits bs in
+     match (n, s) with
+     | (Some n, Some s) => Some (String n s)
+     | _ => None
+     end
+  | [] => Some EmptyString
+  | _ => None
+  end%string.
+
+Fixpoint binstring_of_bits bs := match bs with
+  | b :: bs => String (bitU_char b) (binstring_of_bits bs)
+  | [] => EmptyString
+  end.
+
+Definition show_bitlist bs :=
+  match hexstring_of_bits bs with
+  | Some s => String "0" (String "x" s)
+  | None => String "0" (String "b" (binstring_of_bits bs))
+  end.
+
+(*** List operations *)
+(*
+Definition inline (^^) := append_list
+
+val subrange_list_inc : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_inc {A} (xs : list A) i j :=
+  let toJ := firstn (Z.to_nat j + 1) xs in
+  let fromItoJ := skipn (Z.to_nat i) toJ in
+  fromItoJ.
+
+(*val subrange_list_dec : forall a. list a -> Z -> Z -> list a*)
+Definition subrange_list_dec {A} (xs : list A) i j :=
+  let top := (length_list xs) - 1 in
+  subrange_list_inc xs (top - i) (top - j).
+
+(*val subrange_list : forall a. bool -> list a -> Z -> Z -> list a*)
+Definition subrange_list {A} (is_inc : bool) (xs : list A) i j :=
+ if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j.
+
+Definition splitAt {A} n (l : list A) := (firstn n l, skipn n l).
+
+(*val update_subrange_list_inc : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_inc {A} (xs : list A) i j xs' :=
+  let (toJ,suffix) := splitAt (Z.to_nat j + 1) xs in
+  let (prefix,_fromItoJ) := splitAt (Z.to_nat i) toJ in
+  prefix ++ xs' ++ suffix.
+
+(*val update_subrange_list_dec : forall a. list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list_dec {A} (xs : list A) i j xs' :=
+  let top := (length_list xs) - 1 in
+  update_subrange_list_inc xs (top - i) (top - j) xs'.
+
+(*val update_subrange_list : forall a. bool -> list a -> Z -> Z -> list a -> list a*)
+Definition update_subrange_list {A} (is_inc : bool) (xs : list A) i j xs' :=
+  if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'.
+
+Open Scope nat.
+Fixpoint nth_in_range {A} (n:nat) (l:list A) : n < length l -> A.
+refine 
+  (match n, l with
+  | O, h::_ => fun _ => h
+  | S m, _::t => fun H => nth_in_range A m t _
+  | _,_ => fun H => _
+  end).
+exfalso. inversion H.
+exfalso. inversion H.
+simpl in H. omega.
+Defined.
+
+Lemma nth_in_range_is_nth : forall A n (l : list A) d (H : n < length l),
+  nth_in_range n l H = nth n l d.
+intros until d. revert n.
+induction l; intros n H.
+* inversion H.
+* destruct n.
+  + reflexivity.
+  + apply IHl.
+Qed.
+
+Lemma nth_Z_nat {A} {n} {xs : list A} :
+  (0 <= n)%Z -> (n < length_list xs)%Z -> Z.to_nat n < length xs.
+unfold length_list.
+intros nonneg bounded.
+rewrite Z2Nat.inj_lt in bounded; auto using Zle_0_nat.
+rewrite Nat2Z.id in bounded.
+assumption.
+Qed.
+
+(*
+Lemma nth_top_aux {A} {n} {xs : list A} : Z.to_nat n < length xs -> let top := ((length_list xs) - 1)%Z in Z.to_nat (top - n)%Z < length xs.
+unfold length_list.
+generalize (length xs).
+intro n0.
+rewrite <- (Nat2Z.id n0).
+intro H.
+apply Z2Nat.inj_lt.
+* omega. 
+*)
+
+Close Scope nat.
+
+(*val access_list_inc : forall a. list a -> Z -> a*)
+Definition access_list_inc {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} := nth_in_range (Z.to_nat n) xs (nth_Z_nat (use_ArithFact _) (use_ArithFact _)).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_dec {A} (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} : A.
+refine (
+  let top := (length_list xs) - 1 in
+  @access_list_inc A xs (top - n) _ _).
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+constructor. apply use_ArithFact in H. apply use_ArithFact in H0. omega.
+Defined.
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list {A} (is_inc : bool) (xs : list A) n `{ArithFact (0 <= n)} `{ArithFact (n < length_list xs)} :=
+  if is_inc then access_list_inc xs n else access_list_dec xs n.
+
+Definition access_list_opt_inc {A} (xs : list A) n := nth_error xs (Z.to_nat n).
+
+(*val access_list_dec : forall a. list a -> Z -> a*)
+Definition access_list_opt_dec {A} (xs : list A) n :=
+  let top := (length_list xs) - 1 in
+  access_list_opt_inc xs (top - n).
+
+(*val access_list : forall a. bool -> list a -> Z -> a*)
+Definition access_list_opt {A} (is_inc : bool) (xs : list A) n :=
+  if is_inc then access_list_opt_inc xs n else access_list_opt_dec xs n.
+
+Definition list_update {A} (xs : list A) n x := firstn n xs ++ x :: skipn (S n) xs.
+
+(*val update_list_inc : forall a. list a -> Z -> a -> list a*)
+Definition update_list_inc {A} (xs : list A) n x := list_update xs (Z.to_nat n) x.
+
+(*val update_list_dec : forall a. list a -> Z -> a -> list a*)
+Definition update_list_dec {A} (xs : list A) n x :=
+  let top := (length_list xs) - 1 in
+  update_list_inc xs (top - n) x.
+
+(*val update_list : forall a. bool -> list a -> Z -> a -> list a*)
+Definition update_list {A} (is_inc : bool) (xs : list A) n x :=
+  if is_inc then update_list_inc xs n x else update_list_dec xs n x.
+
+(*Definition extract_only_element := function
+  | [] => failwith "extract_only_element called for empty list"
+  | [e] => e
+  | _ => failwith "extract_only_element called for list with more elements"
+end*)
+
+(*** Machine words *)
+
+Definition mword (n : Z) :=
+  match n with
+  | Zneg _ => False
+  | Z0 => word 0
+  | Zpos p => word (Pos.to_nat p)
+  end.
+
+Definition get_word {n} : mword n -> word (Z.to_nat n) :=
+  match n with
+  | Zneg _ => fun x => match x with end
+  | Z0 => fun x => x
+  | Zpos p => fun x => x
+  end.
+
+Definition with_word {n} {P : Type -> Type} : (word (Z.to_nat n) -> P (word (Z.to_nat n))) -> mword n -> P (mword n) :=
+match n with
+| Zneg _ => fun f w => match w with end
+| Z0 => fun f w => f w
+| Zpos _ => fun f w => f w
+end.
+
+Program Definition to_word {n} : n >= 0 -> word (Z.to_nat n) -> mword n :=
+  match n with
+  | Zneg _ => fun H _ => _
+  | Z0 => fun _ w => w
+  | Zpos _ => fun _ w => w
+  end.
+
+(*val length_mword : forall a. mword a -> Z*)
+Definition length_mword {n} (w : mword n) := n.
+
+(*val slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b*)
+(*Definition slice_mword_dec w i j := word_extract (Z.to_nat i) (Z.to_nat j) w.
+
+val slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b
+Definition slice_mword_inc w i j :=
+  let top := (length_mword w) - 1 in
+  slice_mword_dec w (top - i) (top - j)
+
+val slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b
+Definition slice_mword is_inc w i j := if is_inc then slice_mword_inc w i j else slice_mword_dec w i j
+
+val update_slice_mword_dec : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_dec w i j w' := word_update w (Z.to_nat i) (Z.to_nat j) w'
+
+val update_slice_mword_inc : forall a b. mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword_inc w i j w' :=
+  let top := (length_mword w) - 1 in
+  update_slice_mword_dec w (top - i) (top - j) w'
+
+val update_slice_mword : forall a b. bool -> mword a -> Z -> Z -> mword b -> mword a
+Definition update_slice_mword is_inc w i j w' :=
+  if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'
+
+val access_mword_dec : forall a. mword a -> Z -> bitU*)
+Parameter undefined_bit : bool.
+Definition getBit {n} :=
+match n with
+| O => fun (w : word O) i => undefined_bit
+| S n => fun (w : word (S n)) i => wlsb (wrshift w i)
+end.
+
+Definition access_mword_dec {m} (w : mword m) n := bitU_of_bool (getBit (get_word w) (Z.to_nat n)).
+
+(*val access_mword_inc : forall a. mword a -> Z -> bitU*)
+Definition access_mword_inc {m} (w : mword m) n :=
+  let top := (length_mword w) - 1 in
+  access_mword_dec w (top - n).
+
+(*Parameter access_mword : forall {a}, bool -> mword a -> Z -> bitU.*)
+Definition access_mword {a} (is_inc : bool) (w : mword a) n :=
+  if is_inc then access_mword_inc w n else access_mword_dec w n.
+
+Definition setBit {n} :=
+match n with
+| O => fun (w : word O) i b => w
+| S n => fun (w : word (S n)) i (b : bool) =>
+  let bit : word (S n) := wlshift (natToWord _ 1) i in
+  let mask : word (S n) := wnot bit in
+  let masked := wand mask w in
+  if b then masked else wor masked bit
+end.
+
+(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*)
+Definition update_mword_bool_dec {a} (w : mword a) n b : mword a :=
+  with_word (P := id) (fun w => setBit w (Z.to_nat n) b) w.
+Definition update_mword_dec {a} (w : mword a) n b :=
+ match bool_of_bitU b with
+ | Some bl => Some (update_mword_bool_dec w n bl)
+ | None => None
+ end.
+
+(*val update_mword_inc : forall a. mword a -> Z -> bitU -> mword a*)
+Definition update_mword_inc {a} (w : mword a) n b :=
+  let top := (length_mword w) - 1 in
+  update_mword_dec w (top - n) b.
+
+(*Parameter update_mword : forall {a}, bool -> mword a -> Z -> bitU -> mword a.*)
+Definition update_mword {a} (is_inc : bool) (w : mword a) n b :=
+  if is_inc then update_mword_inc w n b else update_mword_dec w n b.
+
+(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*)
+Definition int_of_mword {a} `{ArithFact (a >= 0)} (sign : bool) (w : mword a) :=
+  if sign then wordToZ (get_word w) else Z.of_N (wordToN (get_word w)).
+
+
+(*val mword_of_int : forall a. Size a => Z -> Z -> mword a
+Definition mword_of_int len n :=
+  let w := wordFromInteger n in
+  if (length_mword w = len) then w else failwith "unexpected word length"
+*)
+Program Definition mword_of_int {len} `{H:ArithFact (len >= 0)} n : mword len :=
+match len with
+| Zneg _ => _
+| Z0 => ZToWord 0 n
+| Zpos p => ZToWord (Pos.to_nat p) n
+end.
+Next Obligation.
+destruct H.
+auto.
+Defined.
+(*
+(* Translating between a type level number (itself n) and an integer *)
+
+Definition size_itself_int x := Z.of_nat (size_itself x)
+
+(* NB: the corresponding sail type is forall n. atom(n) -> itself(n),
+   the actual integer is ignored. *)
+
+val make_the_value : forall n. Z -> itself n
+Definition inline make_the_value x := the_value
+*)
+
+Fixpoint bitlistFromWord {n} w :=
+match w with
+| WO => []
+| WS b w => b :: bitlistFromWord w
+end.
+
+Fixpoint wordFromBitlist l : word (length l) :=
+match l with
+| [] => WO
+| b::t => WS b (wordFromBitlist t)
+end.
+
+Local Open Scope nat.
+Program Definition fit_bbv_word {n m} (w : word n) : word m :=
+match Nat.compare m n with
+| Gt => extz w (m - n)
+| Eq => w
+| Lt => split2 (n - m) m w
+end.
+Next Obligation.
+symmetry in Heq_anonymous.
+apply nat_compare_gt in Heq_anonymous.
+omega.
+Defined.
+Next Obligation.
+
+symmetry in Heq_anonymous.
+apply nat_compare_eq in Heq_anonymous.
+omega.
+Defined.
+Next Obligation.
+
+symmetry in Heq_anonymous.
+apply nat_compare_lt in Heq_anonymous.
+omega.
+Defined.
+Local Close Scope nat.
+
+(*** Bitvectors *)
+
+Class Bitvector (a:Type) : Type := {
+  bits_of : a -> list bitU;
+  of_bits : list bitU -> option a;
+  of_bools : list bool -> a;
+  (* The first parameter specifies the desired length of the bitvector *)
+  of_int : Z -> Z -> a;
+  length : a -> Z;
+  unsigned : a -> option Z;
+  signed : a -> option Z;
+  arith_op_bv : (Z -> Z -> Z) -> bool -> a -> a -> a
+}.
+
+Instance bitlist_Bitvector {a : Type} `{BitU a} : (Bitvector (list a)) := {
+  bits_of v := List.map to_bitU v;
+  of_bits v := Some (List.map of_bitU v);
+  of_bools v := List.map of_bitU (List.map bitU_of_bool v);
+  of_int len n := List.map of_bitU (bits_of_int len n);
+  length := length_list;
+  unsigned v := unsigned_of_bits (List.map to_bitU v);
+  signed v := signed_of_bits (List.map to_bitU v);
+  arith_op_bv op sign l r := List.map of_bitU (arith_op_bits op sign (List.map to_bitU l) (List.map to_bitU r))
+}.
+
+Class ReasonableSize (a : Z) : Prop := {
+  isPositive : a >= 0
+}.
+
+Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool.
+Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool.
+
+(* Omega doesn't know about In, but can handle disjunctions. *)
+Ltac unfold_In :=
+repeat match goal with
+| H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H
+| H:context [In ?x []] |- _ => change (In x []) with False in H
+end.
+
+(* Definitions in the context that involve proof for other constraints can
+   break some of the constraint solving tactics, so prune definition bodies
+   down to integer types. *)
+Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end.
+Ltac clear_non_Z_defns := 
+  repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end.
+
+Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0).
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+Ltac unwrap_ArithFacts :=
+  repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H'] end.
+Ltac unbool_comparisons :=
+  repeat match goal with
+  | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H
+  | H:context [Z.gtb _ _] |- _ => rewrite Z.gtb_ltb in H
+  | H:context [Z.leb _ _ = true] |- _ => rewrite Z.leb_le in H
+  | H:context [Z.ltb _ _ = true] |- _ => rewrite Z.ltb_lt in H
+  | H:context [Z.eqb _ _ = true] |- _ => rewrite Z.eqb_eq in H
+  | H:context [Z.leb _ _ = false] |- _ => rewrite Z.leb_gt in H
+  | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H
+  | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H
+  | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H
+  | H:context [andb _ _ = true] |- _ => apply andb_prop in H
+  | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H
+  | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H
+  | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H
+  | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H
+  end.
+(* Split up dependent pairs to get at proofs of properties *)
+Ltac extract_properties :=
+  repeat match goal with H := (projT1 ?X) |- _ =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in *; unfold H in * end;
+  repeat match goal with |- context [projT1 ?X] =>
+    let x := fresh "x" in
+    let Hx := fresh "Hx" in
+    destruct X as [x Hx] in *;
+    change (projT1 (existT _ x Hx)) with x in * end.
+(* TODO: hyps, too? *)
+Ltac reduce_list_lengths :=
+  repeat match goal with |- context [length_list ?X] => 
+    let r := (eval cbn in (length_list X)) in
+    change (length_list X) with r
+  end.
+(* TODO: can we restrict this to concrete terms? *)
+Ltac reduce_pow :=
+  repeat match goal with H:context [Z.pow ?X ?Y] |- _ => 
+    let r := (eval cbn in (Z.pow X Y)) in
+    change (Z.pow X Y) with r in H
+  end;
+  repeat match goal with |- context [Z.pow ?X ?Y] => 
+    let r := (eval cbn in (Z.pow X Y)) in
+    change (Z.pow X Y) with r
+  end.
+Ltac dump_context :=
+  repeat match goal with
+  | H:=?X |- _ => idtac H ":=" X; fail
+  | H:?X |- _ => idtac H ":" X; fail end;
+  match goal with |- ?X => idtac "Goal:" X end.
+Ltac solve_arithfact :=
+(*dump_context;*)
+ clear_non_Z_defns;
+ extract_properties;
+ repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end;
+ unwrap_ArithFacts;
+ unfold_In;
+ autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *)
+ unbool_comparisons;
+ reduce_list_lengths;
+ reduce_pow;
+(*dump_context;*)
+ solve [apply ArithFact_mword; assumption
+       | constructor; omega with Z
+         (* The datatypes hints give us some list handling, esp In *)
+       | constructor; auto with datatypes zbool zarith sail].
+Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances.
+
+Hint Unfold length_mword : sail.
+
+Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a.
+constructor.
+destruct a.
+auto with zarith.
+auto using Z.le_ge, Zle_0_pos.
+destruct w.
+Qed.
+
+Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances.
+
+Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := {
+  bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v));
+  of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v));
+  of_bools v := to_word isPositive (fit_bbv_word (wordFromBitlist v));
+  of_int len z := mword_of_int z; (* cheat a little *)
+  length v := a;
+  unsigned v := Some (Z.of_N (wordToN (get_word v)));
+  signed v := Some (wordToZ (get_word v));
+  arith_op_bv op sign l r := mword_of_int (op (int_of_mword sign l) (int_of_mword sign r))
+}.
+
+Section Bitvector_defs.
+Context {a b} `{Bitvector a} `{Bitvector b}.
+
+Definition opt_def {a} (def:a) (v:option a) :=
+match v with
+| Some x => x
+| None => def
+end.
+
+(* The Lem version is partial, but lets go with BU here to avoid constraints for now *)
+Definition access_bv_inc (v : a) n := opt_def BU (access_list_opt_inc (bits_of v) n).
+Definition access_bv_dec (v : a) n := opt_def BU (access_list_opt_dec (bits_of v) n).
+
+Definition update_bv_inc (v : a) n b := update_list true  (bits_of v) n b.
+Definition update_bv_dec (v : a) n b := update_list false (bits_of v) n b.
+
+Definition subrange_bv_inc (v : a) i j := subrange_list true  (bits_of v) i j.
+Definition subrange_bv_dec (v : a) i j := subrange_list true  (bits_of v) i j.
+
+Definition update_subrange_bv_inc (v : a) i j (v' : b) := update_subrange_list true  (bits_of v) i j (bits_of v').
+Definition update_subrange_bv_dec (v : a) i j (v' : b) := update_subrange_list false (bits_of v) i j (bits_of v').
+
+(*val extz_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition extz_bv n (v : a) : option b := of_bits (extz_bits n (bits_of v)).
+
+(*val exts_bv : forall a b. Bitvector a, Bitvector b => Z -> a -> b*)
+Definition exts_bv n (v : a) : option b := of_bits (exts_bits n (bits_of v)).
+
+(*val string_of_bv : forall a. Bitvector a => a -> string *)
+Definition string_of_bv v := show_bitlist (bits_of v).
+
+End Bitvector_defs.
+
+(*** Bytes and addresses *)
+
+Definition memory_byte := list bitU.
+
+(*val byte_chunks : forall a. list a -> option (list (list a))*)
+Fixpoint byte_chunks {a} (bs : list a) := match bs with
+  | [] => Some []
+  | a::b::c::d::e::f::g::h::rest =>
+     match byte_chunks rest with
+     | None => None
+     | Some rest => Some ([a;b;c;d;e;f;g;h] :: rest)
+     end
+  | _ => None
+end.
+(*declare {isabelle} termination_argument byte_chunks = automatic*)
+
+Section BytesBits.
+Context {a} `{Bitvector a}.
+
+(*val bytes_of_bits : forall a. Bitvector a => a -> option (list memory_byte)*)
+Definition bytes_of_bits (bs : a) := byte_chunks (bits_of bs).
+
+(*val bits_of_bytes : forall a. Bitvector a => list memory_byte -> a*)
+Definition bits_of_bytes (bs : list memory_byte) : list bitU := List.concat (List.map bits_of bs).
+
+Definition mem_bytes_of_bits (bs : a) := option_map (@rev (list bitU)) (bytes_of_bits bs).
+Definition bits_of_mem_bytes (bs : list memory_byte) := bits_of_bytes (List.rev bs).
+
+End BytesBits.
+
+(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU
+Definition bitv_of_byte_lifteds v :=
+  foldl (fun x (Byte_lifted y) => x ++ (List.map bitU_of_bit_lifted y)) [] v
+
+val bitv_of_bytes : list Sail_impl_base.byte -> list bitU
+Definition bitv_of_bytes v :=
+  foldl (fun x (Byte y) => x ++ (List.map bitU_of_bit y)) [] v
+
+val byte_lifteds_of_bitv : list bitU -> list byte_lifted
+Definition byte_lifteds_of_bitv bits :=
+  let bits := List.map bit_lifted_of_bitU bits in
+  byte_lifteds_of_bit_lifteds bits
+
+val bytes_of_bitv : list bitU -> list byte
+Definition bytes_of_bitv bits :=
+  let bits := List.map bit_of_bitU bits in
+  bytes_of_bits bits
+
+val bit_lifteds_of_bitUs : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitUs bits := List.map bit_lifted_of_bitU bits
+
+val bit_lifteds_of_bitv : list bitU -> list bit_lifted
+Definition bit_lifteds_of_bitv v := bit_lifteds_of_bitUs v
+
+
+val address_lifted_of_bitv : list bitU -> address_lifted
+Definition address_lifted_of_bitv v :=
+  let byte_lifteds := byte_lifteds_of_bitv v in
+  let maybe_address_integer :=
+    match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with
+    | Some bs => Some (integer_of_byte_list bs)
+    | _ => None
+    end in
+  Address_lifted byte_lifteds maybe_address_integer
+
+val bitv_of_address_lifted : address_lifted -> list bitU
+Definition bitv_of_address_lifted (Address_lifted bs _) := bitv_of_byte_lifteds bs
+
+val address_of_bitv : list bitU -> address
+Definition address_of_bitv v :=
+  let bytes := bytes_of_bitv v in
+  address_of_byte_list bytes*)
+
+Fixpoint reverse_endianness_list (bits : list bitU) :=
+  match bits with
+  | _ :: _ :: _ :: _ :: _ :: _ :: _ :: _ :: t =>
+    reverse_endianness_list t ++ firstn 8 bits
+  | _ => bits
+  end.
+
+(*** Registers *)
+
+Definition register_field := string.
+Definition register_field_index : Type := string * (Z * Z). (* name, start and end *)
+
+Inductive register :=
+  | Register : string * (* name *)
+               Z * (* length *)
+               Z * (* start index *)
+               bool * (* is increasing *)
+               list register_field_index
+               -> register
+  | UndefinedRegister : Z -> register (* length *)
+  | RegisterPair : register * register -> register.
+
+Record register_ref regstate regval a :=
+   { name : string;
+     (*is_inc : bool;*)
+     read_from : regstate -> a;
+     write_to : a -> regstate -> regstate;
+     of_regval : regval -> option a;
+     regval_of : a -> regval }.
+Notation "{[ r 'with' 'name' := e ]}" := ({| name := e; read_from := read_from r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'read_from' := e ]}" := ({| read_from := e; name := name r; write_to := write_to r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'write_to' := e ]}" := ({| write_to := e; name := name r; read_from := read_from r; of_regval := of_regval r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'of_regval' := e ]}" := ({| of_regval := e; name := name r; read_from := read_from r; write_to := write_to r; regval_of := regval_of r |}).
+Notation "{[ r 'with' 'regval_of' := e ]}" := ({| regval_of := e; name := name r; read_from := read_from r; write_to := write_to r; of_regval := of_regval r |}).
+Arguments name [_ _ _].
+Arguments read_from [_ _ _].
+Arguments write_to [_ _ _].
+Arguments of_regval [_ _ _].
+Arguments regval_of [_ _ _].
+
+(* Register accessors: pair of functions for reading and writing register values *)
+Definition register_accessors regstate regval : Type :=
+  ((string -> regstate -> option regval) *
+   (string -> regval -> regstate -> option regstate)).
+
+Record field_ref regtype a :=
+   { field_name : string;
+     field_start : Z;
+     field_is_inc : bool;
+     get_field : regtype -> a;
+     set_field : regtype -> a -> regtype }.
+Arguments field_name [_ _].
+Arguments field_start [_ _].
+Arguments field_is_inc [_ _].
+Arguments get_field [_ _].
+Arguments set_field [_ _].
+
+(*
+(*let name_of_reg := function
+  | Register name _ _ _ _ => name
+  | UndefinedRegister _ => failwith "name_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "name_of_reg RegisterPair"
+end
+
+Definition size_of_reg := function
+  | Register _ size _ _ _ => size
+  | UndefinedRegister size => size
+  | RegisterPair _ _ => failwith "size_of_reg RegisterPair"
+end
+
+Definition start_of_reg := function
+  | Register _ _ start _ _ => start
+  | UndefinedRegister _ => failwith "start_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "start_of_reg RegisterPair"
+end
+
+Definition is_inc_of_reg := function
+  | Register _ _ _ is_inc _ => is_inc
+  | UndefinedRegister _ => failwith "is_inc_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "in_inc_of_reg RegisterPair"
+end
+
+Definition dir_of_reg := function
+  | Register _ _ _ is_inc _ => dir_of_bool is_inc
+  | UndefinedRegister _ => failwith "dir_of_reg UndefinedRegister"
+  | RegisterPair _ _ => failwith "dir_of_reg RegisterPair"
+end
+
+Definition size_of_reg_nat reg := Z.to_nat (size_of_reg reg)
+Definition start_of_reg_nat reg := Z.to_nat (start_of_reg reg)
+
+val register_field_indices_aux : register -> register_field -> option (Z * Z)
+Fixpoint register_field_indices_aux register rfield :=
+  match register with
+  | Register _ _ _ _ rfields => List.lookup rfield rfields
+  | RegisterPair r1 r2 =>
+      let m_indices := register_field_indices_aux r1 rfield in
+      if isSome m_indices then m_indices else register_field_indices_aux r2 rfield
+  | UndefinedRegister _ => None
+  end
+
+val register_field_indices : register -> register_field -> Z * Z
+Definition register_field_indices register rfield :=
+  match register_field_indices_aux register rfield with
+  | Some indices => indices
+  | None => failwith "Invalid register/register-field combination"
+  end
+
+Definition register_field_indices_nat reg regfield=
+  let (i,j) := register_field_indices reg regfield in
+  (Z.to_nat i,Z.to_nat j)*)
+
+(*let rec external_reg_value reg_name v :=
+  let (internal_start, external_start, direction) :=
+    match reg_name with
+     | Reg _ start size dir =>
+        (start, (if dir = D_increasing then start else (start - (size +1))), dir)
+     | Reg_slice _ reg_start dir (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_field _ reg_start dir _ (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     | Reg_f_slice _ reg_start dir _ _ (slice_start, _) =>
+        ((if dir = D_increasing then slice_start else (reg_start - slice_start)),
+         slice_start, dir)
+     end in
+  let bits := bit_lifteds_of_bitv v in
+  <| rv_bits           := bits;
+     rv_dir            := direction;
+     rv_start          := external_start;
+     rv_start_internal := internal_start |>
+
+val internal_reg_value : register_value -> list bitU
+Definition internal_reg_value v :=
+  List.map bitU_of_bit_lifted v.rv_bits
+         (*(Z.of_nat v.rv_start_internal)
+         (v.rv_dir = D_increasing)*)
+
+
+Definition external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) :=
+  match d with
+  (*This is the case the thread/concurrecny model expects, so no change needed*)
+  | D_increasing => (i,j)
+  | D_decreasing => let slice_i = start - i in
+                    let slice_j = (i - j) + slice_i in
+                    (slice_i,slice_j)
+  end *)
+
+(* TODO
+Definition external_reg_whole r :=
+  Reg (r.name) (Z.to_nat r.start) (Z.to_nat r.size) (dir_of_bool r.is_inc)
+
+Definition external_reg_slice r (i,j) :=
+  let start := Z.to_nat r.start in
+  let dir := dir_of_bool r.is_inc in
+  Reg_slice (r.name) start dir (external_slice dir start (i,j))
+
+Definition external_reg_field_whole reg rfield :=
+  let (m,n) := register_field_indices_nat reg rfield in
+  let start := start_of_reg_nat reg in
+  let dir := dir_of_reg reg in
+  Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n))
+
+Definition external_reg_field_slice reg rfield (i,j) :=
+  let (m,n) := register_field_indices_nat reg rfield in
+  let start := start_of_reg_nat reg in
+  let dir := dir_of_reg reg in
+  Reg_f_slice (name_of_reg reg) start dir rfield
+              (external_slice dir start (m,n))
+              (external_slice dir start (i,j))*)
+
+(*val external_mem_value : list bitU -> memory_value
+Definition external_mem_value v :=
+  byte_lifteds_of_bitv v $> List.reverse
+
+val internal_mem_value : memory_value -> list bitU
+Definition internal_mem_value bytes :=
+  List.reverse bytes $> bitv_of_byte_lifteds*)
+
+
+val foreach : forall a vars.
+  (list a) -> vars -> (a -> vars -> vars) -> vars*)
+Fixpoint foreach {a Vars} (l : list a) (vars : Vars) (body : a -> Vars -> Vars) : Vars :=
+match l with
+| [] => vars
+| (x :: xs) => foreach xs (body x vars) body
+end.
+
+(*declare {isabelle} termination_argument foreach = automatic
+
+val index_list : Z -> Z -> Z -> list Z*)
+Fixpoint index_list' from to step n :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => []
+    | S n => from :: index_list' (from + step) to step n
+    end
+  else [].
+
+Definition index_list from to step :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    index_list' from to step (S (Z.abs_nat (from - to)))
+  else [].
+
+Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Vars) : Vars :=
+  if orb (andb (step >? 0) (from <=? to)) (andb (step <? 0) (to <=? from)) then
+    match n with
+    | O => vars
+    | S n => let vars := body from vars in foreach_Z' (from + step) to step n vars body
+    end
+  else vars.
+
+Definition foreach_Z {Vars} from to step vars body :=
+  foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body.
+
+Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (from + off <=? to) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_up' from to step (off + step) n vars body
+    end
+  else vars.
+
+Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars :=
+  if sumbool_of_bool (to <=? from + off) then
+    match n with
+    | O => vars
+    | S n => let vars := body (from + off) _ vars in foreach_Z_down' from to step (off - step) n vars body
+    end
+  else vars.
+
+Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} :=
+    foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} :=
+    foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body.
+
+(*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint while vars cond body :=
+  if cond vars then while (body vars) cond body else vars
+
+val until : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars
+Fixpoint until vars cond body :=
+  let vars := body vars in
+  if cond vars then vars else until (body vars) cond body
+
+
+Definition assert' b msg_opt :=
+  let msg := match msg_opt with
+  | Some msg => msg
+  | None  => "unspecified error"
+  end in
+  if b then () else failwith msg
+
+(* convert numbers unsafely to naturals *)
+
+class (ToNatural a) val toNatural : a -> natural end
+(* eta-expanded for Isabelle output, otherwise it breaks *)
+instance (ToNatural Z) let toNatural := (fun n => naturalFromInteger n) end
+instance (ToNatural int)     let toNatural := (fun n => naturalFromInt n)     end
+instance (ToNatural nat)     let toNatural := (fun n => naturalFromNat n)     end
+instance (ToNatural natural) let toNatural := (fun n => n)                    end
+
+Definition toNaturalFiveTup (n1,n2,n3,n4,n5) :=
+  (toNatural n1,
+   toNatural n2,
+   toNatural n3,
+   toNatural n4,
+   toNatural n5)
+
+(* Let the following types be generated by Sail per spec, using either bitlists
+   or machine words as bitvector representation *)
+(*type regfp :=
+  | RFull of (string)
+  | RSlice of (string * Z * Z)
+  | RSliceBit of (string * Z)
+  | RField of (string * string)
+
+type niafp :=
+  | NIAFP_successor
+  | NIAFP_concrete_address of vector bitU
+  | NIAFP_indirect_address
+
+(* only for MIPS *)
+type diafp :=
+  | DIAFP_none
+  | DIAFP_concrete of vector bitU
+  | DIAFP_reg of regfp
+
+Definition regfp_to_reg (reg_info : string -> option string -> (nat * nat * direction * (nat * nat))) := function
+  | RFull name =>
+     let (start,length,direction,_) := reg_info name None in
+     Reg name start length direction
+  | RSlice (name,i,j) =>
+     let i = Z.to_nat i in
+     let j = Z.to_nat j in
+     let (start,length,direction,_) = reg_info name None in
+     let slice = external_slice direction start (i,j) in
+     Reg_slice name start direction slice
+  | RSliceBit (name,i) =>
+     let i = Z.to_nat i in
+     let (start,length,direction,_) = reg_info name None in
+     let slice = external_slice direction start (i,i) in
+     Reg_slice name start direction slice
+  | RField (name,field_name) =>
+     let (start,length,direction,span) = reg_info name (Some field_name) in
+     let slice = external_slice direction start span in
+     Reg_field name start direction field_name slice
+end
+
+Definition niafp_to_nia reginfo = function
+  | NIAFP_successor => NIA_successor
+  | NIAFP_concrete_address v => NIA_concrete_address (address_of_bitv v)
+  | NIAFP_indirect_address => NIA_indirect_address
+end
+
+Definition diafp_to_dia reginfo = function
+  | DIAFP_none => DIA_none
+  | DIAFP_concrete v => DIA_concrete_address (address_of_bitv v)
+  | DIAFP_reg r => DIA_register (regfp_to_reg reginfo r)
+end
+*)
+*)
+
+(* Arithmetic functions which return proofs that match the expected Sail
+   types in smt.sail. *)
+
+Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m).
+Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m).
+Definition abs_with_eq n   : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n).
+
+(* Similarly, for ranges (currently in MIPS) *)
+
+Definition eq_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)}) : bool :=
+  (projT1 l) =? (projT1 r).
+Definition add_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+  : {x & ArithFact (n+o <= x <= m+p)} :=
+  build_ex ((projT1 l) + (projT1 r)).
+Definition sub_range {n m o p} (l : {l & ArithFact (n <= l <= m)}) (r : {r & ArithFact (o <= r <= p)})
+  : {x & ArithFact (n-p <= x <= m-o)} :=
+  build_ex ((projT1 l) - (projT1 r)).
+Definition negate_range {n m} (l : {l : Z & ArithFact (n <= l <= m)})
+  : {x : Z & ArithFact ((- m) <= x <= (- n))} :=
+  build_ex (- (projT1 l)).
+
+Definition min_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c <= a /\ c <= b)} :=
+  build_ex (Z.min a b).
+Definition max_atom (a : Z) (b : Z) : {c : Z & ArithFact (c = a \/ c = b /\ c >= a /\ c >= b)} :=
+  build_ex (Z.max a b).
+
+
+(*** Generic vectors *)
+
+Definition vec (T:Type) (n:Z) := { l : list T & length_list l = n }.
+Definition vec_length {T n} (v : vec T n) := n.
+Definition vec_access_dec {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_dec (projT1 v) m.
+Definition vec_access_inc {T n} (v : vec T n) m `{ArithFact (0 <= m < n)} : T :=
+  access_list_inc (projT1 v) m.
+
+Program Definition vec_init {T} (t : T) (n : Z) `{ArithFact (n >= 0)} : vec T n :=
+  existT _ (repeat [t] n) _.
+Next Obligation.
+rewrite repeat_length; auto using fact.
+unfold length_list.
+simpl.
+auto with zarith.
+Qed.
+
+Lemma skipn_length {A n} {l: list A} : (n <= List.length l -> List.length (skipn n l) = List.length l - n)%nat.
+revert l.
+induction n.
+* simpl. auto with arith.
+* intros l H.
+  destruct l.
+  + inversion H.
+  + simpl in H.
+    simpl.
+    rewrite IHn; auto with arith.
+Qed.
+Lemma update_list_inc_length {T} {l:list T} {m x} : 0 <= m < length_list l -> length_list (update_list_inc l m x) = length_list l.
+unfold update_list_inc, list_update, length_list.
+intro H.
+f_equal.
+assert ((0 <= Z.to_nat m < Datatypes.length l)%nat).
+{ destruct H as [H1 H2].
+  split.
+  + change 0%nat with (Z.to_nat 0).
+    apply Z2Nat.inj_le; auto with zarith.
+  + rewrite <- Nat2Z.id.
+    apply Z2Nat.inj_lt; auto with zarith.
+}
+rewrite app_length.
+rewrite firstn_length_le; only 2:omega.
+cbn -[skipn].
+rewrite skipn_length;
+omega.
+Qed.
+
+Program Definition vec_update_dec {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_dec (projT1 v) m t) _.
+Next Obligation.
+unfold update_list_dec.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_update_inc {T n} (v : vec T n) m t `{ArithFact (0 <= m < n)} : vec T n := existT _ (update_list_inc (projT1 v) m t) _.
+Next Obligation.
+rewrite update_list_inc_length.
++ destruct v. apply e.
++ destruct H.
+  destruct v. simpl (projT1 _). rewrite e.
+  omega.
+Qed.
+
+Program Definition vec_map {S T} (f : S -> T) {n} (v : vec S n) : vec T n := existT _ (List.map f (projT1 v)) _.
+Next Obligation.
+destruct v as [l H].
+cbn.
+unfold length_list.
+rewrite map_length.
+apply H.
+Qed.
+
+Program Definition just_vec {A n} (v : vec (option A) n) : option (vec A n) :=
+  match just_list (projT1 v) with
+  | None => None
+  | Some v' => Some (existT _ v' _)
+  end.
+Next Obligation.
+rewrite <- (just_list_length_Z _ _ Heq_anonymous).
+destruct v.
+assumption.
+Qed.
+
+Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v.
+
+Program Definition vec_of_list {A} n (l : list A) : option (vec A n) :=
+  if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None.
+Next Obligation.
+symmetry.
+apply Z.eqb_eq.
+assumption.
+Qed.
+
+Definition vec_of_list_len {A} (l : list A) : vec A (length_list l) := existT _ l (eq_refl _).
+
+Definition map_bind {A B} (f : A -> option B) (a : option A) : option B :=
+match a with
+| Some a' => f a'
+| None => None
+end.
\ No newline at end of file
diff --git a/snapshots/coq/lib/coq/_CoqProject b/snapshots/coq/lib/coq/_CoqProject
new file mode 100644
index 00000000..9f5d26b8
--- /dev/null
+++ b/snapshots/coq/lib/coq/_CoqProject
@@ -0,0 +1,2 @@
+-R . Sail
+-R ../../../bbv/theories bbv
diff --git a/snapshots/coq/mips/_CoqProject b/snapshots/coq/mips/_CoqProject
new file mode 100644
index 00000000..ad38d28d
--- /dev/null
+++ b/snapshots/coq/mips/_CoqProject
@@ -0,0 +1,2 @@
+-R ../../bbv/theories bbv
+-R ../lib/coq Sail
\ No newline at end of file
diff --git a/snapshots/coq/mips/mips.v b/snapshots/coq/mips/mips.v
new file mode 100644
index 00000000..8d43a6e2
--- /dev/null
+++ b/snapshots/coq/mips/mips.v
@@ -0,0 +1,5890 @@
+(*Generated by Sail from mips.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Require Import mips_types.
+Require Import mips_extras.
+Import ListNotations.
+Open Scope string.
+Section Content.
+
+Definition neq_atom (x : Z) (y : Z) `{ArithFact (x = x)} `{ArithFact (y = y)}
+: bool :=
+   negb (Z.eqb x y).
+
+Definition neq_range {n : Z} {m : Z} {o : Z} {p : Z} '((existT _ x _) : {rangevar : Z & ArithFact (n <=
+  rangevar /\
+  rangevar <= m)}) '((existT _ y _) : {rangevar : Z & ArithFact (o <= rangevar /\ rangevar <= p)}) 
+: bool :=
+   negb (eq_range (build_ex x) (build_ex y)).
+
+Definition neq_int (x : Z) (y : Z)  : bool := negb (Z.eqb x y).
+
+Definition neq_bool (x : bool) (y : bool)  : bool := negb (Bool.eqb x y).
+
+Definition undefined_option {a : Type} (typ_a : a) 
+: M (option a) :=
+   undefined_unit tt >>= fun u_0 =>
+   let u_1 : a := typ_a in
+   (internal_pick [Some u_1;None])
+    : M (option a).
+
+Definition is_none {a : Type} (opt : option a) 
+: bool :=
+   match opt with | Some (_) => false | None => true end.
+
+Definition is_some {a : Type} (opt : option a) 
+: bool :=
+   match opt with | Some (_) => true | None => false end.
+
+Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} `{ArithFact (len =
+  len)}
+: mword len :=
+   if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len
+   else zero_extend v len.
+
+Definition neq_vec {n : Z} (x : mword n) (y : mword n)  : bool := negb (eq_vec x y).
+
+
+
+Definition cast_unit_vec (b : bitU) 
+: mword 1 :=
+   match b with | B0 => (vec_of_bits [B0]  : mword 1) | _ => (vec_of_bits [B1]  : mword 1) end.
+
+Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width =
+  width)}
+: M (unit) :=
+   (write_ram 64 width
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        : mword 64) addr data)
+    : M (unit).
+
+Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} `{ArithFact (width =
+  width)}
+: M (mword (8 * width)) :=
+   (autocast_m (read_ram 64 width
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64) addr))
+    : M (mword (8 * width)).
+
+Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} `{ArithFact (n = n)}
+: mword (n0 * n) :=
+   replicate_bits bs n.
+
+Definition undefined_exception '(tt : unit) 
+: M (exception) :=
+   undefined_string tt >>= fun u_0 =>
+   undefined_unit tt >>= fun u_1 =>
+   (internal_pick
+      [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1])
+    : M (exception).
+
+Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} 
+: mword m__tv :=
+   sign_extend v m__tv.
+
+Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} 
+: mword m__tv :=
+   zero_extend v m__tv.
+
+Definition zeros (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} 
+: mword n__tv :=
+   autocast (replicate_bits (vec_of_bits [B0]  : mword 1) n__tv).
+Arguments zeros _ _ {_}.
+
+Definition ones (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} 
+: mword n__tv :=
+   autocast (replicate_bits (vec_of_bits [B1]  : mword 1) n__tv).
+Arguments ones _ _ {_}.
+
+Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} 
+: bool :=
+   Z.ltb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} 
+: bool :=
+   Z.geb (projT1 (sint x)) (projT1 (sint y)).
+
+Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} 
+: bool :=
+   Z.ltb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} 
+: bool :=
+   Z.geb (projT1 (uint x)) (projT1 (uint y)).
+
+Definition bool_to_bits (x : bool) 
+: mword 1 :=
+   if (x) then (vec_of_bits [B1]  : mword 1)
+   else (vec_of_bits [B0]  : mword 1).
+
+Definition bit_to_bool (b : bitU)  : bool := match b with | B1 => true | _ => false end.
+
+Definition bits_to_bool (x : mword 1)  : bool := bit_to_bool (access_vec_dec x 0).
+
+Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} `{ArithFact (l = l)}
+: mword l :=
+   get_slice_int l n 0.
+
+Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= 1)} 
+: mword n__tv :=
+   autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0).
+
+Definition undefined_CauseReg '(tt : unit) 
+: M (CauseReg) :=
+   undefined_bitvector 32 >>= fun w__0 =>
+   returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |})
+    : CauseReg).
+
+Definition Mk_CauseReg (v : mword 32) 
+: CauseReg :=
+   {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_CauseReg_bits (v : CauseReg) 
+: mword 32 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0.
+
+Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_CauseReg_BD (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31.
+
+Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_CE (v : CauseReg) 
+: mword 2 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28.
+
+Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_CauseReg_IV (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23.
+
+Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_WP (v : CauseReg) 
+: mword 1 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22.
+
+Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_CauseReg_IP (v : CauseReg) 
+: mword 8 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8.
+
+Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_CauseReg_ExcCode (v : CauseReg) 
+: mword 5 :=
+   subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2.
+
+Definition _set_CauseReg_ExcCode (r_ref : register_ref regstate register_value CauseReg) (v : mword 5) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       CauseReg_CauseReg_chunk_0 :=
+         (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]}
+      : CauseReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) 
+: CauseReg :=
+   {[ v with
+     CauseReg_CauseReg_chunk_0 :=
+       (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}.
+
+Definition undefined_TLBEntryLoReg '(tt : unit) 
+: M (TLBEntryLoReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |})
+    : TLBEntryLoReg).
+
+Definition Mk_TLBEntryLoReg (v : mword 64) 
+: TLBEntryLoReg :=
+   {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) 
+: mword 64 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0.
+
+Definition _set_TLBEntryLoReg_bits (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0
+            (subrange_vec_dec v 63 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0
+          (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63.
+
+Definition _set_TLBEntryLoReg_CapS (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63
+          (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62.
+
+Definition _set_TLBEntryLoReg_CapL (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62
+          (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6.
+
+Definition _set_TLBEntryLoReg_PFN (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6
+            (subrange_vec_dec v 23 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6
+          (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3.
+
+Definition _set_TLBEntryLoReg_C (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3
+            (subrange_vec_dec v 2 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2.
+
+Definition _set_TLBEntryLoReg_D (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1.
+
+Definition _set_TLBEntryLoReg_V (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0.
+
+Definition _set_TLBEntryLoReg_G (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0
+            (subrange_vec_dec v 0 0)) ]}
+      : TLBEntryLoReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) 
+: TLBEntryLoReg :=
+   {[ v with
+     TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition undefined_TLBEntryHiReg '(tt : unit) 
+: M (TLBEntryHiReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |})
+    : TLBEntryHiReg).
+
+Definition Mk_TLBEntryHiReg (v : mword 64) 
+: TLBEntryHiReg :=
+   {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) 
+: mword 64 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0.
+
+Definition _set_TLBEntryHiReg_bits (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0
+            (subrange_vec_dec v 63 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0
+          (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) 
+: mword 2 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62.
+
+Definition _set_TLBEntryHiReg_R (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62
+            (subrange_vec_dec v 1 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62
+          (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) 
+: mword 27 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13.
+
+Definition _set_TLBEntryHiReg_VPN2 (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13
+            (subrange_vec_dec v 26 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13
+          (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) 
+: mword 8 :=
+   subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0.
+
+Definition _set_TLBEntryHiReg_ASID (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0
+            (subrange_vec_dec v 7 0)) ]}
+      : TLBEntryHiReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) 
+: TLBEntryHiReg :=
+   {[ v with
+     TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition undefined_ContextReg '(tt : unit) 
+: M (ContextReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |})
+    : ContextReg).
+
+Definition Mk_ContextReg (v : mword 64) 
+: ContextReg :=
+   {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_ContextReg_bits (v : ContextReg) 
+: mword 64 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0.
+
+Definition _set_ContextReg_bits (r_ref : register_ref regstate register_value ContextReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_ContextReg_PTEBase (v : ContextReg) 
+: mword 41 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23.
+
+Definition _set_ContextReg_PTEBase (r_ref : register_ref regstate register_value ContextReg) (v : mword 41) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}.
+
+Definition _get_ContextReg_BadVPN2 (v : ContextReg) 
+: mword 19 :=
+   subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4.
+
+Definition _set_ContextReg_BadVPN2 (r_ref : register_ref regstate register_value ContextReg) (v : mword 19) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       ContextReg_ContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]}
+      : ContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) 
+: ContextReg :=
+   {[ v with
+     ContextReg_ContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}.
+
+Definition undefined_XContextReg '(tt : unit) 
+: M (XContextReg) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |})
+    : XContextReg).
+
+Definition Mk_XContextReg (v : mword 64) 
+: XContextReg :=
+   {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_XContextReg_bits (v : XContextReg) 
+: mword 64 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0.
+
+Definition _set_XContextReg_bits (r_ref : register_ref regstate register_value XContextReg) (v : mword 64) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_XContextReg_XPTEBase (v : XContextReg) 
+: mword 31 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33.
+
+Definition _set_XContextReg_XPTEBase (r_ref : register_ref regstate register_value XContextReg) (v : mword 31) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33
+            (subrange_vec_dec v 30 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}.
+
+Definition _get_XContextReg_XR (v : XContextReg) 
+: mword 2 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31.
+
+Definition _set_XContextReg_XR (r_ref : register_ref regstate register_value XContextReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_XContextReg_XBadVPN2 (v : XContextReg) 
+: mword 27 :=
+   subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4.
+
+Definition _set_XContextReg_XBadVPN2 (r_ref : register_ref regstate register_value XContextReg) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       XContextReg_XContextReg_chunk_0 :=
+         (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]}
+      : XContextReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) 
+: XContextReg :=
+   {[ v with
+     XContextReg_XContextReg_chunk_0 :=
+       (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}.
+
+Definition TLBNumEntries := 64.
+
+Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6).
+
+Definition MAX (n : Z) `{ArithFact (n = n)} : Z := Z.sub (pow2 n) 1.
+
+Definition MAX_U64 := MAX 64.
+
+Definition MAX_VA := MAX 40.
+
+Definition MAX_PA := MAX 36.
+
+Definition undefined_TLBEntry '(tt : unit) 
+: M (TLBEntry) :=
+   undefined_bitvector 53 >>= fun w__0 =>
+   undefined_bitvector 64 >>= fun w__1 =>
+   returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; 
+                TLBEntry_TLBEntry_chunk_0 := w__1 |})
+    : TLBEntry).
+
+Definition Mk_TLBEntry (v : mword 117) 
+: TLBEntry :=
+   {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); 
+      TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}.
+
+Definition _get_TLBEntry_bits (v : TLBEntry) 
+: mword 117 :=
+   concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0)
+     (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0).
+
+Definition _set_TLBEntry_bits (r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]}
+      : TLBEntry in
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) 
+: TLBEntry :=
+   let v :=
+     {[ v with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}.
+
+Definition _get_TLBEntry_pagemask (v : TLBEntry) 
+: mword 16 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37.
+
+Definition _set_TLBEntry_pagemask (r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}.
+
+Definition _get_TLBEntry_r (v : TLBEntry) 
+: mword 2 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35.
+
+Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_TLBEntry_vpn2 (v : TLBEntry) 
+: mword 27 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8.
+
+Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}.
+
+Definition _get_TLBEntry_asid (v : TLBEntry) 
+: mword 8 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0.
+
+Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_1 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_1 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_TLBEntry_g (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63.
+
+Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_valid (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62.
+
+Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_caps1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61.
+
+Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_capl1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60.
+
+Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_pfn1 (v : TLBEntry) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36.
+
+Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntry_c1 (v : TLBEntry) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33.
+
+Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntry_d1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32.
+
+Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_v1 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31.
+
+Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_caps0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30.
+
+Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_capl0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29.
+
+Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_pfn0 (v : TLBEntry) 
+: mword 24 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5.
+
+Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}.
+
+Definition _get_TLBEntry_c0 (v : TLBEntry) 
+: mword 3 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2.
+
+Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}.
+
+Definition _get_TLBEntry_d0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1.
+
+Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_TLBEntry_v0 (v : TLBEntry) 
+: mword 1 :=
+   subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0.
+
+Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       TLBEntry_TLBEntry_chunk_0 :=
+         (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+      : TLBEntry in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) 
+: TLBEntry :=
+   {[ v with
+     TLBEntry_TLBEntry_chunk_0 :=
+       (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 :=
+vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;
+                 TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref;
+                 TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;
+                 TLBEntry00_ref].
+
+Definition undefined_StatusReg '(tt : unit) 
+: M (StatusReg) :=
+   undefined_bitvector 32 >>= fun w__0 =>
+   returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |})
+    : StatusReg).
+
+Definition Mk_StatusReg (v : mword 32) 
+: StatusReg :=
+   {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}.
+
+Definition _get_StatusReg_bits (v : StatusReg) 
+: mword 32 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0.
+
+Definition _set_StatusReg_bits (r_ref : register_ref regstate register_value StatusReg) (v : mword 32) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}.
+
+Definition _get_StatusReg_CU (v : StatusReg) 
+: mword 4 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28.
+
+Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}.
+
+Definition _get_StatusReg_BEV (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22.
+
+Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_IM (v : StatusReg) 
+: mword 8 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8.
+
+Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}.
+
+Definition _get_StatusReg_KX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7.
+
+Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_SX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6.
+
+Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_UX (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5.
+
+Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_KSU (v : StatusReg) 
+: mword 2 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3.
+
+Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}.
+
+Definition _get_StatusReg_ERL (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2.
+
+Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_EXL (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1.
+
+Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}.
+
+Definition _get_StatusReg_IE (v : StatusReg) 
+: mword 1 :=
+   subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0.
+
+Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) 
+: M (unit) :=
+   reg_deref r_ref >>= fun r =>
+   let r :=
+     {[ r with
+       StatusReg_StatusReg_chunk_0 :=
+         (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]}
+      : StatusReg in
+   write_reg r_ref r
+    : M (unit).
+
+Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) 
+: StatusReg :=
+   {[ v with
+     StatusReg_StatusReg_chunk_0 :=
+       (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}.
+
+Definition execute_branch (pc : mword 64) 
+: M (unit) :=
+   write_reg delayedPC_ref pc >>
+   write_reg branchPending_ref (vec_of_bits [B1]  : mword 1)
+    : M (unit).
+
+Definition NotWordVal (word : mword 64) 
+: bool :=
+   neq_vec (zopz0zQzQ ((cast_unit_vec (access_vec_dec word 31))  : mword 1) 32)
+     (subrange_vec_dec word 63 32).
+
+Definition rGPR (idx : mword 5) 
+: M (mword 64) :=
+   let '(existT _ i _) := uint idx in
+   (if sumbool_of_bool ((Z.eqb i 0)) then
+      returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0]
+                 : mword 64)
+       : mword 64)
+    else read_reg GPR_ref >>= fun w__0 => returnm ((vec_access_dec w__0 i)  : mword 64))
+    : M (mword 64).
+
+Definition wGPR (idx : mword 5) (v : mword 64) 
+: M (unit) :=
+   let '(existT _ i _) := uint idx in
+   (if ((neq_atom i 0)) then
+      read_reg GPR_ref >>= fun w__0 => write_reg GPR_ref (vec_update_dec w__0 i v)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = size)}
+: M (mword (8 * size)) :=
+   (autocast_m (__MIPS_read addr size))
+    : M (mword (8 * size)).
+
+Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   (autocast_m (__MIPS_read addr size))
+    : M (mword (8 * size)).
+
+Definition MEM_sync '(tt : unit)  : M (unit) := (skip tt)  : M (unit).
+
+Definition MEMea (addr : mword 64) (size : Z) `{ArithFact (size = size)}
+: M (unit) :=
+   (skip tt)
+    : M (unit).
+
+Definition MEMea_conditional (addr : mword 64) (size : Z) `{ArithFact (size = size)}
+: M (unit) :=
+   (skip tt)
+    : M (unit).
+
+Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = size)}
+: M (unit) :=
+   (__MIPS_write addr size data)
+    : M (unit).
+
+Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size =
+  size)}
+: M (bool) :=
+   __MIPS_write addr size data >> returnm (true  : bool).
+
+Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} `{ArithFact (arg_ =
+  arg_)}
+: Exception :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL
+   else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS
+   else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL
+   else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES
+   else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys
+   else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp
+   else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI
+   else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU
+   else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov
+   else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr
+   else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E
+   else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap
+   else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL
+   else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS
+   else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL
+   else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS
+   else MCheck.
+
+Definition num_of_Exception (arg_ : Exception) 
+: {e : Z & ArithFact (0 <= e /\ e <= 18)} :=
+   match arg_ with
+   | Interrupt => build_ex 0
+   | TLBMod => build_ex 1
+   | TLBL => build_ex 2
+   | TLBS => build_ex 3
+   | AdEL => build_ex 4
+   | AdES => build_ex 5
+   | Sys => build_ex 6
+   | Bp => build_ex 7
+   | ResI => build_ex 8
+   | CpU => build_ex 9
+   | Ov => build_ex 10
+   | Tr => build_ex 11
+   | C2E => build_ex 12
+   | C2Trap => build_ex 13
+   | XTLBRefillL => build_ex 14
+   | XTLBRefillS => build_ex 15
+   | XTLBInvL => build_ex 16
+   | XTLBInvS => build_ex 17
+   | MCheck => build_ex 18
+   end.
+
+Definition undefined_Exception '(tt : unit) 
+: M (Exception) :=
+   (internal_pick
+      [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck])
+    : M (Exception).
+
+Definition ExceptionCode (ex : Exception) 
+: mword 5 :=
+   let x : bits 8 :=
+     match ex with
+     | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)
+     | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  : mword 8)
+     | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0]  : mword 8)
+     | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1]  : mword 8)
+     | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0]  : mword 8)
+     | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1]  : mword 8)
+     | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0]  : mword 8)
+     | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1]  : mword 8)
+     | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0]  : mword 8)
+     | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1]  : mword 8)
+     | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  : mword 8)
+     | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  : mword 8)
+     | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  : mword 8)
+     | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  : mword 8)
+     | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0]  : mword 8)
+     end in
+   subrange_vec_dec x 4 0.
+
+Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) 
+: M (o) :=
+   read_reg CP0Status_ref >>= fun w__0 =>
+   (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0))  : bool))) then
+      (read_reg inBranchDelay_ref  : M (mword 1)) >>= fun w__1 =>
+      (if (((bit_to_bool (access_vec_dec w__1 0))  : bool)) then
+         (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+         write_reg CP0EPC_ref (sub_vec_int w__2 4) >>
+         (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1]  : mword 1))
+          : M (unit)
+       else
+         (read_reg PC_ref  : M (mword 64)) >>= fun w__3 =>
+         write_reg CP0EPC_ref w__3 >>
+         (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  : mword 1))
+          : M (unit))
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   read_reg CP0Status_ref >>= fun w__4 =>
+   let vectorOffset :=
+     if (((bits_to_bool (_get_StatusReg_EXL w__4))  : bool)) then
+       (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then
+       (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else if ((generic_eq ex C2Trap)) then
+       (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12)
+     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  : mword 12) in
+   read_reg CP0Status_ref >>= fun w__5 =>
+   let vectorBase : bits 64 :=
+     if (((bits_to_bool (_get_StatusReg_BEV w__5))  : bool)) then
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         : mword 64)
+     else
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         : mword 64) in
+   write_reg nextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >>
+   _set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex) >>
+   _set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  : mword 1) >>
+   (throw (ISAException tt))
+    : M (o).
+
+Definition SignalException {o : Type} (ex : Exception) 
+: M (o) :=
+   (SignalExceptionMIPS ex
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        : mword 64))
+    : M (o).
+
+Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) 
+: M (o) :=
+   write_reg CP0BadVAddr_ref badAddr >> (SignalException ex)  : M (o).
+
+Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) 
+: M (o) :=
+   write_reg CP0BadVAddr_ref badAddr >>
+   _set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13) >>
+   _set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13) >>
+   _set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62) >>
+   _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62) >>
+   _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13) >>
+   (SignalException ex)
+    : M (o).
+
+Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ =
+  arg_)}
+: MemAccessType :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData
+   else StoreData.
+
+Definition num_of_MemAccessType (arg_ : MemAccessType) 
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+   match arg_ with
+   | Instruction => build_ex 0
+   | LoadData => build_ex 1
+   | StoreData => build_ex 2
+   end.
+
+Definition undefined_MemAccessType '(tt : unit) 
+: M (MemAccessType) :=
+   (internal_pick [Instruction;LoadData;StoreData])
+    : M (MemAccessType).
+
+Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ =
+  arg_)}
+: AccessLevel :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then User
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor
+   else Kernel.
+
+Definition num_of_AccessLevel (arg_ : AccessLevel) 
+: {e : Z & ArithFact (0 <= e /\ e <= 2)} :=
+   match arg_ with | User => build_ex 0 | Supervisor => build_ex 1 | Kernel => build_ex 2 end.
+
+Definition undefined_AccessLevel '(tt : unit) 
+: M (AccessLevel) :=
+   (internal_pick [User;Supervisor;Kernel])
+    : M (AccessLevel).
+
+Definition int_of_AccessLevel (level : AccessLevel) 
+: Z :=
+   match level with | User => 0 | Supervisor => 1 | Kernel => 2 end.
+
+Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) 
+: bool :=
+   Z.geb (int_of_AccessLevel currentLevel) (int_of_AccessLevel requiredLevel).
+
+Definition getAccessLevel '(tt : unit) 
+: M (AccessLevel) :=
+   or_boolM
+     (read_reg CP0Status_ref >>= fun w__0 =>
+      returnm ((bits_to_bool (_get_StatusReg_EXL w__0))
+       : bool))
+     (read_reg CP0Status_ref >>= fun w__1 =>
+      returnm ((bits_to_bool (_get_StatusReg_ERL w__1))
+       : bool)) >>= fun w__2 =>
+   (if (w__2) then returnm (Kernel  : AccessLevel)
+    else
+      read_reg CP0Status_ref >>= fun w__3 =>
+      let p__27 := _get_StatusReg_KSU w__3 in
+      let b__0 := p__27 in
+      returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0]  : mword 2))) then Kernel
+                else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then Supervisor
+                else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then User
+                else User)
+       : AccessLevel))
+    : M (AccessLevel).
+
+Definition checkCP0Access '(tt : unit) 
+: M (unit) :=
+   getAccessLevel tt >>= fun accessLevel =>
+   and_boolM (returnm ((generic_neq accessLevel Kernel)  : bool))
+     (read_reg CP0Status_ref >>= fun w__0 =>
+      returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0))  : bool))
+       : bool)) >>= fun w__1 =>
+   (if (w__1) then
+      _set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0]  : mword 2) >>
+      (SignalException CpU)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition incrementCP0Count '(tt : unit) 
+: M (unit) :=
+   (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__0 =>
+   (read_reg TLBWired_ref  : M (mword 6)) >>= fun w__1 =>
+   (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax  : TLBIndexT)
+    else
+      (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__2 =>
+      returnm ((sub_vec_int w__2 1)
+       : TLBIndexT)) >>= fun w__3 =>
+   write_reg TLBRandom_ref w__3 >>
+   (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__4 =>
+   write_reg CP0Count_ref (add_vec_int w__4 1) >>
+   (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__5 =>
+   (read_reg CP0Compare_ref  : M (mword 32)) >>= fun w__6 =>
+   (if ((eq_vec w__5 w__6)) then
+      read_reg CP0Cause_ref >>= fun w__7 =>
+      (_set_CauseReg_IP CP0Cause_ref
+         (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   read_reg CP0Status_ref >>= fun w__8 =>
+   let ims := _get_StatusReg_IM w__8 in
+   read_reg CP0Cause_ref >>= fun w__9 =>
+   let ips := _get_CauseReg_IP w__9 in
+   read_reg CP0Status_ref >>= fun w__10 =>
+   let ie := _get_StatusReg_IE w__10 in
+   read_reg CP0Status_ref >>= fun w__11 =>
+   let exl := _get_StatusReg_EXL w__11 in
+   read_reg CP0Status_ref >>= fun w__12 =>
+   let erl := _get_StatusReg_ERL w__12 in
+   (if ((andb (negb ((bits_to_bool exl)  : bool))
+           (andb (negb ((bits_to_bool erl)  : bool))
+              (andb ((bits_to_bool ie)  : bool)
+                 (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8))))))
+    then
+      (SignalException Interrupt)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ =
+  arg_)}
+: decode_failure :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction
+   else internal_error.
+
+Definition num_of_decode_failure (arg_ : decode_failure) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with
+   | no_matching_pattern => build_ex 0
+   | unsupported_instruction => build_ex 1
+   | illegal_instruction => build_ex 2
+   | internal_error => build_ex 3
+   end.
+
+Definition undefined_decode_failure '(tt : unit) 
+: M (decode_failure) :=
+   (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error])
+    : M (decode_failure).
+
+Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} `{ArithFact (arg_ =
+  arg_)}
+: Comparison :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ'
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE
+   else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU
+   else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT'
+   else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE
+   else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT'
+   else LTU.
+
+Definition num_of_Comparison (arg_ : Comparison) 
+: {e : Z & ArithFact (0 <= e /\ e <= 7)} :=
+   match arg_ with
+   | EQ' => build_ex 0
+   | NE => build_ex 1
+   | GE => build_ex 2
+   | GEU => build_ex 3
+   | GT' => build_ex 4
+   | LE => build_ex 5
+   | LT' => build_ex 6
+   | LTU => build_ex 7
+   end.
+
+Definition undefined_Comparison '(tt : unit) 
+: M (Comparison) :=
+   (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU])
+    : M (Comparison).
+
+Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) 
+: bool :=
+   match cmp with
+   | EQ' => eq_vec valA valB
+   | NE => neq_vec valA valB
+   | GE => zopz0zKzJ_s valA valB
+   | GEU => zopz0zKzJ_u valA valB
+   | GT' => zopz0zI_s valB valA
+   | LE => zopz0zKzJ_s valB valA
+   | LT' => zopz0zI_s valA valB
+   | LTU => zopz0zI_u valA valB
+   end.
+
+Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = arg_)}
+: WordType :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then B
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then H
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then W
+   else D.
+
+Definition num_of_WordType (arg_ : WordType) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with | B => build_ex 0 | H => build_ex 1 | W => build_ex 2 | D => build_ex 3 end.
+
+Definition undefined_WordType '(tt : unit) 
+: M (WordType) :=
+   (internal_pick [B;H;W;D])
+    : M (WordType).
+
+Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ =
+  arg_)}
+: WordTypeUnaligned :=
+   let p0_ := arg_ in
+   if sumbool_of_bool ((Z.eqb p0_ 0)) then WL
+   else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR
+   else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL
+   else DR.
+
+Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) 
+: {e : Z & ArithFact (0 <= e /\ e <= 3)} :=
+   match arg_ with | WL => build_ex 0 | WR => build_ex 1 | DL => build_ex 2 | DR => build_ex 3 end.
+
+Definition undefined_WordTypeUnaligned '(tt : unit) 
+: M (WordTypeUnaligned) :=
+   (internal_pick [WL;WR;DL;DR])
+    : M (WordTypeUnaligned).
+
+Definition wordWidthBytes (w : WordType) 
+: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} :=
+   match w with | B => build_ex 1 | H => build_ex 2 | W => build_ex 4 | D => build_ex 8 end.
+
+Definition alignment_width := 16.
+
+Definition isAddressAligned (addr : mword 64) (wordType : WordType) 
+: bool :=
+   let '(existT _ a _) := uint addr in
+   Z.eqb (projT1 (div_with_eq a alignment_width))
+     (Z.quot (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width).
+
+Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   (if ((eq_vec addr
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      (read_reg UART_RVALID_ref  : M (mword 1)) >>= fun rvalid =>
+      write_reg UART_RVALID_ref (vec_of_bits [B0]  : mword 1) >>
+      (read_reg UART_RDATA_ref  : M (mword 8)) >>= fun w__0 =>
+      returnm ((mask (Z.mul 8 size)
+                  (concat_vec
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32)
+                     (concat_vec w__0
+                        (concat_vec rvalid
+                           (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  : mword 7)
+                              (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                : mword 16))))))
+       : mword (8 * size))
+    else if ((eq_vec addr
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                              B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+                              B0]
+                  : mword 64))) then
+      returnm ((mask (Z.mul 8 size)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                                B1]
+                    : mword 64))
+       : mword (8 * size))
+    else
+      autocast_m (MEMr addr size) >>= fun w__1 =>
+      returnm ((autocast (reverse_endianness w__1))
+       : mword (8 * size)))
+    : M (mword (8 * size)).
+
+Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size =
+  size)}
+: M (mword (8 * size)) :=
+   autocast_m (MEMr_reserve addr size) >>= fun w__0 =>
+   returnm ((autocast (reverse_endianness w__0))
+    : mword (8 * size)).
+
+Definition init_cp0_state '(tt : unit) 
+: M (unit) :=
+   (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1)  : mword 1))
+    : M (unit).
+
+Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) 
+: bool :=
+   let entryValid := _get_TLBEntry_valid entry in
+   let entryR := _get_TLBEntry_r entry in
+   let entryMask := _get_TLBEntry_pagemask entry in
+   let entryVPN := _get_TLBEntry_vpn2 entry in
+   let entryASID := _get_TLBEntry_asid entry in
+   let entryG := _get_TLBEntry_g entry in
+   let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in
+   andb ((bits_to_bool entryValid)  : bool)
+     (andb (eq_vec r entryR)
+        (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask))
+           (orb (eq_vec asid entryASID) ((bits_to_bool entryG)  : bool)))).
+
+Definition tlbSearch (VAddr : mword 64) 
+: M (option (mword 6)) :=
+   catch_early_return
+     (let r := subrange_vec_dec VAddr 63 62 in
+     let vpn2 := subrange_vec_dec VAddr 39 13 in
+     liftR (read_reg TLBEntryHi_ref) >>= fun w__0 =>
+     let asid := _get_TLBEntryHiReg_ASID w__0 in
+     (foreach_ZM_up 0 63 1 tt
+       (fun idx _ unit_var =>
+         liftR (reg_deref (vec_access_dec TLBEntries idx)) >>= fun w__1 =>
+         (if ((tlbEntryMatch r vpn2 asid w__1)) then
+            (early_return ((Some (to_bits 6 idx))  : option (mword 6)) : MR unit (option (mword 6)))
+             : MR (unit) _
+          else returnm (tt  : unit))
+          : MR (unit) _)) >>
+     returnm (None
+      : option (mword 6))).
+
+Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) 
+: M ((mword 64 * bool)) :=
+   tlbSearch vAddr >>= fun idx =>
+   (match idx with
+    | Some (idx) =>
+       let '(existT _ i _) := uint idx in
+       reg_deref (vec_access_dec TLBEntries i) >>= fun entry =>
+       let entryMask := _get_TLBEntry_pagemask entry in
+       let b__0 := entryMask in
+       (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16)))
+        then
+          returnm ((build_ex
+          12)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          14)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          16)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          18)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          20)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          22)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          24)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          26)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else if ((eq_vec b__0
+                    (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16)))
+        then
+          returnm ((build_ex
+          28)
+           : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})
+        else
+          (undefined_range 12 28)
+           : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _) =>
+       let isOdd := access_vec_dec vAddr evenOddBit in
+       let '(caps, capl, pfn, d, v) :=
+         if (((bit_to_bool isOdd)  : bool)) then
+           (_get_TLBEntry_caps1 entry,
+            _get_TLBEntry_capl1 entry,
+            _get_TLBEntry_pfn1 entry,
+            _get_TLBEntry_d1 entry,
+            _get_TLBEntry_v1 entry)
+         else
+           (_get_TLBEntry_caps0 entry,
+            _get_TLBEntry_capl0 entry,
+            _get_TLBEntry_pfn0 entry,
+            _get_TLBEntry_d0 entry,
+            _get_TLBEntry_v0 entry) in
+       (if ((negb ((bits_to_bool v)  : bool))) then
+          (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL)
+             vAddr)
+           : M ((mword 64 * bool))
+        else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d)  : bool)))) then
+          (SignalExceptionTLB TLBMod vAddr)
+           : M ((mword 64 * bool))
+        else
+          let res : bits 64 :=
+            mips_zero_extend 64
+              (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12))
+                 (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in
+          returnm ((res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))
+           : (mword 64 * bool)))
+        : M ((mword 64 * bool))
+    | None =>
+       (SignalExceptionTLB
+          (if ((generic_eq accessType StoreData)) then XTLBRefillS
+           else XTLBRefillL) vAddr)
+        : M ((mword 64 * bool))
+    end)
+    : M ((mword 64 * bool)).
+
+Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) 
+: M ((mword 64 * bool)) :=
+   getAccessLevel tt >>= fun currentAccessLevel =>
+   let compat32 :=
+     eq_vec (subrange_vec_dec vAddr 61 31)
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
+         : mword 31) in
+   let b__0 := subrange_vec_dec vAddr 63 62 in
+   let '(requiredLevel, addr) :=
+     (if ((eq_vec b__0 (vec_of_bits [B1;B1]  : mword 2))) then
+        match (compat32, subrange_vec_dec vAddr 30 29) with
+        | (true, b__1) =>
+           if ((eq_vec b__1 (vec_of_bits [B1;B1]  : mword 2))) then
+             (Kernel, None  : option (bits 64))
+           else if ((eq_vec b__1 (vec_of_bits [B1;B0]  : mword 2))) then
+             (Supervisor, None  : option (bits 64))
+           else if ((eq_vec b__1 (vec_of_bits [B0;B1]  : mword 2))) then
+             (Kernel,
+              Some (concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        : mword 32)
+                      (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3) (subrange_vec_dec vAddr 28 0))))
+           else if ((eq_vec b__1 (vec_of_bits [B0;B0]  : mword 2))) then
+             (Kernel,
+              Some (concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        : mword 32)
+                      (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3) (subrange_vec_dec vAddr 28 0))))
+           else match (true, b__1) with | (g__25, g__26) => (Kernel, None  : option (bits 64)) end
+        | (g__25, g__26) => (Kernel, None  : option (bits 64))
+        end
+      else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then
+        (Kernel,
+         Some (concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5) (subrange_vec_dec vAddr 58 0)))
+      else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then
+        (Supervisor, None  : option (bits 64))
+      else (User, None  : option (bits 64)))
+      : (AccessLevel * option (bits 64)) in
+   (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then
+      (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr)
+       : M ((mword 64 * bool))
+    else
+      match addr with
+      | Some (a) => returnm ((a, false)  : (mword 64 * bool))
+      | None =>
+         (if ((andb (negb compat32) (gtb_range_l (uint (subrange_vec_dec vAddr 61 0)) MAX_VA))) then
+            (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL)
+               vAddr)
+             : M ((bits 64 * bool))
+          else (TLBTranslate2 vAddr accessType)  : M ((bits 64 * bool)))
+          : M ((mword 64 * bool))
+      end >>= fun '(pa, c) =>
+      (if ((gtb_range_l (uint pa) MAX_PA)) then
+         (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr)
+          : M ((mword 64 * bool))
+       else returnm ((pa, c)  : (mword 64 * bool)))
+       : M ((mword 64 * bool)))
+    : M ((mword 64 * bool)).
+
+Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) 
+: M (mword 64) :=
+   TLBTranslateC vAddr accessType >>= fun '(addr, c) => returnm (addr  : mword 64).
+
+Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <=
+  size /\
+  size <= 8)} `{ArithFact (size = size)}
+: M (unit) :=
+   let ledata := autocast (reverse_endianness data) in
+   (if ((eq_vec addr
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >>
+      write_reg UART_WRITTEN_ref ((cast_unit_vec B1)  : bits 1)
+       : M (unit)
+    else MEMea addr size >> (MEMval addr size ledata)  : M (unit))
+    : M (unit).
+
+Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <=
+  size /\
+  size <= 8)} `{ArithFact (size = size)}
+: M (bool) :=
+   MEMea_conditional addr size >>
+   (MEMval_conditional addr size (autocast (reverse_endianness data)))
+    : M (bool).
+
+Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) 
+: mword 64 :=
+   addr.
+
+Definition addrWrapperUnaligned (addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) 
+: mword 64 :=
+   addr.
+
+Definition TranslatePC (vAddr : mword 64) 
+: M (mword 64) :=
+   incrementCP0Count tt >>
+   (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0]  : mword 2))) then
+      (SignalExceptionBadAddr AdEL vAddr)
+       : M (mword 64)
+    else (TLBTranslate vAddr Instruction)  : M (mword 64))
+    : M (mword 64).
+
+Definition have_cp2 := false.
+
+Definition ERETHook '(tt : unit)  : unit := tt.
+
+Definition init_cp2_state '(tt : unit)  : M (unit) := (skip tt)  : M (unit).
+
+Definition cp2_next_pc '(tt : unit)  : M (unit) := skip tt >> (skip tt)  : M (unit).
+
+Definition dump_cp2_state '(tt : unit)  : M (unit) := skip tt >> (skip tt)  : M (unit).
+
+Definition undefined_ast '(tt : unit) 
+: M (ast) :=
+   undefined_Comparison tt >>= fun u_0 =>
+   undefined_WordType tt >>= fun u_1 =>
+   undefined_bool tt >>= fun u_3 =>
+   undefined_bool tt >>= fun u_2 =>
+   undefined_bitvector 16 >>= fun u_4 =>
+   undefined_bitvector 5 >>= fun u_7 =>
+   undefined_bitvector 5 >>= fun u_6 =>
+   undefined_bitvector 5 >>= fun u_5 =>
+   undefined_unit tt >>= fun u_8 =>
+   undefined_bitvector 3 >>= fun u_9 =>
+   undefined_bitvector 16 >>= fun u_10 =>
+   undefined_bitvector 26 >>= fun u_11 =>
+   (internal_pick
+      [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8])
+    : M (ast).
+
+Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} 
+: mword 64 :=
+   if (sign) then mips_sign_extend 64 memResult
+   else mips_zero_extend 64 memResult.
+
+Definition TLBWriteEntry (idx : mword 6) 
+: M (unit) :=
+   (read_reg TLBPageMask_ref  : M (mword 16)) >>= fun pagemask =>
+   let b__0 := pagemask in
+   (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16)))
+    then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else if ((eq_vec b__0
+                (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  : mword 16))) then
+      returnm (tt
+       : unit)
+    else (SignalException MCheck)  : M (unit)) >>
+   let '(existT _ i _) := uint idx in
+   let entry := vec_access_dec TLBEntries i in
+   _set_TLBEntry_pagemask entry pagemask >>
+   read_reg TLBEntryHi_ref >>= fun w__0 =>
+   _set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0) >>
+   read_reg TLBEntryHi_ref >>= fun w__1 =>
+   _set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1) >>
+   read_reg TLBEntryHi_ref >>= fun w__2 =>
+   _set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2) >>
+   and_boolM
+     (read_reg TLBEntryLo0_ref >>= fun w__3 =>
+      returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3))
+       : bool))
+     (read_reg TLBEntryLo1_ref >>= fun w__4 =>
+      returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4))
+       : bool)) >>= fun w__5 =>
+   _set_TLBEntry_g entry ((bool_to_bits w__5)  : mword 1) >>
+   _set_TLBEntry_valid entry ((cast_unit_vec B1)  : mword 1) >>
+   read_reg TLBEntryLo0_ref >>= fun w__6 =>
+   _set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6) >>
+   read_reg TLBEntryLo0_ref >>= fun w__7 =>
+   _set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7) >>
+   read_reg TLBEntryLo0_ref >>= fun w__8 =>
+   _set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8) >>
+   read_reg TLBEntryLo0_ref >>= fun w__9 =>
+   _set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9) >>
+   read_reg TLBEntryLo0_ref >>= fun w__10 =>
+   _set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10) >>
+   read_reg TLBEntryLo0_ref >>= fun w__11 =>
+   _set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11) >>
+   read_reg TLBEntryLo1_ref >>= fun w__12 =>
+   _set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12) >>
+   read_reg TLBEntryLo1_ref >>= fun w__13 =>
+   _set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13) >>
+   read_reg TLBEntryLo1_ref >>= fun w__14 =>
+   _set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14) >>
+   read_reg TLBEntryLo1_ref >>= fun w__15 =>
+   _set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15) >>
+   read_reg TLBEntryLo1_ref >>= fun w__16 =>
+   _set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16) >>
+   read_reg TLBEntryLo1_ref >>= fun w__17 =>
+   (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17))
+    : M (unit).
+
+Definition decode (v__0 : mword 32) 
+: option ast :=
+   if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B1]  : mword 6))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (DADDIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DADDU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (DADDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DADD (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (ADD (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ADDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (ADDU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ADDIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSUBU (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSUB (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SUB (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SUBU (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (AND (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ANDI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (OR (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (ORI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (NOR (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (XOR (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B1;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (XORI (rs,rt,imm))
+   else if ((eq_vec (subrange_vec_dec v__0 31 21)
+               (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0]  : mword 11))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LUI (rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSLL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSLL32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSLLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRA (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRA32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSRAV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : bits 5 := subrange_vec_dec v__0 10 6 in
+     Some (DSRL32 (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (DSRLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SLL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B1]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SRA (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SRAV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B0]  : mword 6))))
+   then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sa : regno := subrange_vec_dec v__0 10 6 in
+     Some (SRL (rt,rd,sa))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SRLV (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLT (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SLTI (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (SLTU (rs,rt,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SLTIU (rs,rt,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MOVN (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MOVZ (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 16)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0]  : mword 11)))) then
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MFHI rd)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 16)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0]  : mword 11)))) then
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MFLO rd)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1]
+                    : mword 21)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (MTHI rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1]
+                    : mword 21)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (MTLO rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  : mword 11)))) then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (MUL (rs,rt,rd))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MULT (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MULTU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DMULT (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DMULTU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MADD (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MADDU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MSUB (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (MSUBU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DIV (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DIVU (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DDIV (rs,rt))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  : mword 16))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (DDIVU (rs,rt))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B0]  : mword 6)))
+   then
+     let offset : bits 26 := subrange_vec_dec v__0 25 0 in
+     Some (J offset)
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B1]  : mword 6)))
+   then
+     let offset : bits 26 := subrange_vec_dec v__0 25 0 in
+     Some (JAL offset)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (andb
+                  (eq_vec (subrange_vec_dec v__0 20 11)
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 10))
+                  (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B0]  : mword 6)))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     Some (JR rs)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (andb
+                  (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+                  (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B1]  : mword 6)))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (JALR (rs,rd))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,false,false))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B0]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,false,true))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,true,false))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B1]  : mword 6)))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BEQ (rs,rt,imm,true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',true,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LT',true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,true,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GE,true,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GT',false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,GT',false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LE,false,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (BCMPZ (rs,imm,LE,false,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B0]  : mword 6))))
+   then
+     Some (SYSCALL tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B1]  : mword 6))))
+   then
+     Some (BREAK tt)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]
+                 : mword 32))) then
+     Some (WAIT tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,GE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B1]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,GEU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,LT'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B1]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,LTU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B0;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,EQ'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B1;B0]  : mword 6))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     Some (TRAPREG (rs,rt,NE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,EQ'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,NE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,GE))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,GEU))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,LT'))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1]  : mword 6))
+               (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))))
+   then
+     let rs : regno := subrange_vec_dec v__0 25 21 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (TRAPIMM (rs,imm,LTU))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (B,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (B,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (H,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (H,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,true,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (D,false,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (W,true,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Load (D,false,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (B,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (H,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (W,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (D,false,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B0;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (W,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (Store (D,true,base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LWL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LWR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SWL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SWR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LDL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (LDR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B0]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SDL (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let offset : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (SDR (base,rt,offset))
+   else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B1]  : mword 6)))
+   then
+     let base : regno := subrange_vec_dec v__0 25 21 in
+     let op : regno := subrange_vec_dec v__0 20 16 in
+     let imm : imm16 := subrange_vec_dec v__0 15 0 in
+     Some (CACHE (base,op,imm))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 11)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                    : mword 21))
+               (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B1;B1]  : mword 6))))
+   then
+     Some (SYNC tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MFC0 (rt,rd,sel,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MFC0 (rt,rd,sel,true))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     Some (HCF tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 15 0)
+                  (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+   then
+     Some (HCF tt)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MTC0 (rt,rd,sel,false))
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 3)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     let sel : bits 3 := subrange_vec_dec v__0 2 0 in
+     Some (MTC0 (rt,rd,sel,true))
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]
+                 : mword 32))) then
+     Some ((TLBWI tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]
+                 : mword 32))) then
+     Some ((TLBWR tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]
+                 : mword 32))) then
+     Some ((TLBR tt)
+      : ast)
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0]
+                 : mword 32))) then
+     Some ((TLBP tt)
+      : ast)
+   else if ((andb
+               (eq_vec (subrange_vec_dec v__0 31 21)
+                  (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0]  : mword 11))
+               (eq_vec (subrange_vec_dec v__0 10 0)
+                  (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1]  : mword 11)))) then
+     let rt : regno := subrange_vec_dec v__0 20 16 in
+     let rd : regno := subrange_vec_dec v__0 15 11 in
+     Some (RDHWR (rt,rd))
+   else if ((eq_vec v__0
+               (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]
+                 : mword 32))) then
+     Some (ERET tt)
+   else Some (RI tt).
+
+Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (xor_vec w__0 w__1))  : M (unit).
+
+Definition execute_WAIT (g__16 : unit) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 => write_reg nextPC_ref w__0  : M (unit).
+
+Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   rGPR rt >>= fun rt_val =>
+   let condition := compare cmp rs_val rt_val in
+   (if (condition) then (SignalException Tr)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   let imm_val : bits 64 := mips_sign_extend 64 imm in
+   let condition := compare cmp rs_val imm_val in
+   (if (condition) then (SignalException Tr)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_TLBWR (g__20 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0)  : M (unit).
+
+Definition execute_TLBWI (g__19 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0)  : M (unit).
+
+Definition execute_TLBR (g__21 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 =>
+   let '(existT _ i _) := uint w__0 in
+   reg_deref (vec_access_dec TLBEntries i) >>= fun entry =>
+   write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >>
+   _set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry) >>
+   _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry) >>
+   _set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry) >>
+   _set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry) >>
+   _set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry) >>
+   _set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry) >>
+   _set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry) >>
+   _set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry) >>
+   _set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry) >>
+   _set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry) >>
+   _set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry) >>
+   _set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry) >>
+   _set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry) >>
+   _set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry) >>
+   _set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry) >>
+   _set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry) >>
+   (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry))
+    : M (unit).
+
+Definition execute_TLBP (g__22 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   read_reg TLBEntryHi_ref >>= fun w__0 =>
+   tlbSearch (_get_TLBEntryHiReg_bits w__0) >>= fun result =>
+   (match result with
+    | Some (idx) =>
+       write_reg TLBProbe_ref (vec_of_bits [B0]  : mword 1) >>
+       write_reg TLBIndex_ref idx
+        : M (unit)
+    | None =>
+       write_reg TLBProbe_ref (vec_of_bits [B1]  : mword 1) >>
+       write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6)
+        : M (unit)
+    end)
+    : M (unit).
+
+Definition execute_Store (width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width in
+   rGPR rt >>= fun rt_val =>
+   (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr)  : M (unit)
+    else
+      TLBTranslate vAddr StoreData >>= fun pAddr =>
+      (if (conditional) then
+         (read_reg CP0LLBit_ref  : M (mword 1)) >>= fun w__1 =>
+         (if (((bit_to_bool (access_vec_dec w__1 0))  : bool)) then
+            (match width with
+             | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0))  : M (bool)
+             | D => (MEMw_conditional_wrapper pAddr 8 rt_val)  : M (bool)
+             | _ => (throw (Error_internal_error tt))  : M (bool)
+             end)
+             : M (bool)
+          else returnm (false  : bool)) >>= fun success =>
+         (wGPR rt (mips_zero_extend 64 ((bool_to_bits success)  : mword 1)))
+          : M (unit)
+       else
+         (match width with
+          | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0))  : M (unit)
+          | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0))  : M (unit)
+          | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0))  : M (unit)
+          | D => (MEMw_wrapper pAddr 8 rt_val)  : M (unit)
+          end)
+          : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SYSCALL (g__14 : unit)  : M (unit) := (SignalException Sys)  : M (unit).
+
+Definition execute_SYNC (g__17 : unit)  : M (unit) := (MEM_sync tt)  : M (unit).
+
+Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2) in
+   rGPR rt >>= fun reg_val =>
+   let b__12 := subrange_vec_dec vAddr 1 0 in
+   (if ((eq_vec b__12 (vec_of_bits [B0;B0]  : mword 2))) then
+      (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0))
+       : M (unit)
+    else if ((eq_vec b__12 (vec_of_bits [B0;B1]  : mword 2))) then
+      (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0))
+       : M (unit)
+    else if ((eq_vec b__12 (vec_of_bits [B1;B0]  : mword 2))) then
+      (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0))
+       : M (unit)
+    else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0))  : M (unit))
+    : M (unit).
+
+Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let b__8 := subrange_vec_dec vAddr 1 0 in
+   (if ((eq_vec b__8 (vec_of_bits [B0;B0]  : mword 2))) then
+      (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0))
+       : M (unit)
+    else if ((eq_vec b__8 (vec_of_bits [B0;B1]  : mword 2))) then
+      (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8))
+       : M (unit)
+    else if ((eq_vec b__8 (vec_of_bits [B1;B0]  : mword 2))) then
+      (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16))
+       : M (unit)
+    else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24))  : M (unit))
+    : M (unit).
+
+Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      (wGPR rd
+         (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let temp33 : bits 33 :=
+        sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0))
+          (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32))  : bool)
+              ((bit_to_bool (access_vec_dec temp33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2))  : M (unit))
+    : M (unit).
+
+Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1))  : M (unit))
+    : M (unit).
+
+Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right_arith rt32 sa >>= fun w__2 =>
+      (wGPR rd (mips_sign_extend 64 w__2))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let rt32 := subrange_vec_dec temp 31 0 in
+      shift_bits_right_arith rt32 sa >>= fun w__1 =>
+      (wGPR rd (mips_sign_extend 64 w__1))
+       : M (unit))
+    : M (unit).
+
+Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   rGPR rt >>= fun rt_val =>
+   (wGPR rd
+      (mips_zero_extend 64
+         (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun rs_val =>
+   let immext : bits 64 := mips_sign_extend 64 imm in
+   (wGPR rt
+      (mips_zero_extend 64
+         (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   let '(existT _ imm_val _) := sint imm in
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rs_val _) := sint w__0 in
+   (wGPR rt
+      (mips_zero_extend 64
+         (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   (wGPR rd
+      (mips_zero_extend 64
+         (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1]  : mword 1)
+          else (vec_of_bits [B0]  : mword 1))))
+    : M (unit).
+
+Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 4 0 in
+   rGPR rt >>= fun w__1 =>
+   let rt32 := subrange_vec_dec w__1 31 0 in
+   shift_bits_left rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2))  : M (unit).
+
+Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   let rt32 := subrange_vec_dec w__0 31 0 in
+   shift_bits_left rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1))  : M (unit).
+
+Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3) in
+   let b__40 := subrange_vec_dec vAddr 2 0 in
+   (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+      (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0))
+       : M (unit)
+    else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+      (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0))
+       : M (unit)
+    else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL in
+   TLBTranslate vAddr StoreData >>= fun pAddr =>
+   rGPR rt >>= fun reg_val =>
+   let b__32 := subrange_vec_dec vAddr 2 0 in
+   (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+      (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40))
+       : M (unit)
+    else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+      (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48))
+       : M (unit)
+    else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56))  : M (unit))
+    : M (unit).
+
+Definition execute_RI (g__24 : unit)  : M (unit) := (SignalException ResI)  : M (unit).
+
+Definition execute_RDHWR (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   getAccessLevel tt >>= fun accessLevel =>
+   let haveAccessLevel : bool := generic_eq accessLevel Kernel in
+   read_reg CP0Status_ref >>= fun w__0 =>
+   let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in
+   let '(existT _ rdi _) := uint rd in
+   (read_reg CP0HWREna_ref  : M (mword 32)) >>= fun w__1 =>
+   let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in
+   (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then
+      (SignalException ResI)
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   let b__146 := rd in
+   (if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))) then
+      (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__2 =>
+      returnm ((mips_zero_extend 64 w__2)
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))) then
+      returnm ((mips_zero_extend 64 (vec_of_bits [B1]  : mword 1))
+       : bits 64)
+    else if ((eq_vec b__146 (vec_of_bits [B1;B1;B1;B0;B1]  : mword 5))) then
+      (read_reg CP0UserLocal_ref  : M (mword 64))
+       : M (bits 64)
+    else (SignalException ResI)  : M (bits 64)) >>= fun temp =>
+   (wGPR rt temp)
+    : M (unit).
+
+Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (or_vec w__0 w__1))  : M (unit).
+
+Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 => (wGPR rd (not_vec (or_vec w__0 w__1)))  : M (unit).
+
+Definition execute_MULTU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun result =>
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MULT (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun result =>
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   let result : bits 64 :=
+     mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (mword 64)
+    else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0))  : mword 64)) >>= fun w__1 =>
+   (wGPR rd w__1)
+    : M (unit).
+
+Definition execute_MTLO (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => write_reg LO_ref w__0  : M (unit).
+
+Definition execute_MTHI (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => write_reg HI_ref w__0  : M (unit).
+
+Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) 
+: M (unit) :=
+   checkCP0Access tt >>
+   rGPR rt >>= fun reg_val =>
+   (match (rd, sel) with
+    | (b__108, b__109) =>
+       (if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+               (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBIndex_ref (mask 6 reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          returnm (tt
+           : unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+          write_reg CP0UserLocal_ref reg_val
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax  : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg
+            CP0HWREna_ref
+            (concat_vec (subrange_vec_dec reg_val 31 29)
+               (concat_vec
+                  (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0]
+                    : mword 25) (subrange_vec_dec reg_val 3 0)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          returnm (tt
+           : unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62) >>
+          _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13) >>
+          (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >>
+          read_reg CP0Cause_ref >>= fun w__0 =>
+          (_set_CauseReg_IP CP0Cause_ref
+             (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1]  : mword 8)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_StatusReg_CU CP0Status_ref (subrange_vec_dec reg_val 31 28) >>
+          _set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22))  : mword 1) >>
+          _set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8) >>
+          _set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7))  : mword 1) >>
+          _set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6))  : mword 1) >>
+          _set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5))  : mword 1) >>
+          _set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3) >>
+          _set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2))  : mword 1) >>
+          _set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1))  : mword 1) >>
+          (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0))  : mword 1))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B1]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          _set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23))  : mword 1) >>
+          read_reg CP0Cause_ref >>= fun w__1 =>
+          let ip := _get_CauseReg_IP w__1 in
+          (_set_CauseReg_IP CP0Cause_ref
+             (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8)))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0EPC_ref reg_val
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0)
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B1;B0;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33))
+           : M (unit)
+        else if ((andb (eq_vec b__108 (vec_of_bits [B1;B1;B1;B1;B0]  : mword 5))
+                    (eq_vec b__109 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+          write_reg CP0ErrorEPC_ref reg_val
+           : M (unit)
+        else (SignalException ResI)  : M (unit))
+        : M (unit)
+    end)
+    : M (unit).
+
+Definition execute_MSUBU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MSUB (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   (if ((eq_vec w__0
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      rGPR rs >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   (if ((neq_vec w__0
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64))) then
+      rGPR rs >>= fun w__1 => (wGPR rd w__1)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_MFLO (rd : mword 5) 
+: M (unit) :=
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_MFHI (rd : mword 5) 
+: M (unit) :=
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) 
+: M (unit) :=
+   checkCP0Access tt >>
+   match (rd, sel) with
+   | (b__48, b__49) =>
+      (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0]  : mword 5))
+              (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBIndex_ref  : M (mword 6)) >>= fun w__0 =>
+         let idx : bits 31 := mips_zero_extend 31 w__0 in
+         (read_reg TLBProbe_ref  : M (mword 1)) >>= fun w__1 =>
+         returnm ((concat_vec
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32) (concat_vec w__1 idx))
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBRandom_ref  : M (mword 6)) >>= fun w__2 =>
+         returnm ((mips_zero_extend 64 w__2)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryLo0_ref >>= fun w__3 =>
+         returnm ((_get_TLBEntryLoReg_bits w__3)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryLo1_ref >>= fun w__4 =>
+         returnm ((_get_TLBEntryLoReg_bits w__4)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBContext_ref >>= fun w__5 => returnm ((_get_ContextReg_bits w__5)  : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+         (read_reg CP0UserLocal_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBPageMask_ref  : M (mword 16)) >>= fun w__7 =>
+         returnm ((mips_zero_extend 64
+                     (concat_vec w__7
+                        (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 12)))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg TLBWired_ref  : M (mword 6)) >>= fun w__8 =>
+         returnm ((mips_zero_extend 64 w__8)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0HWREna_ref  : M (mword 32)) >>= fun w__9 =>
+         returnm ((mips_zero_extend 64 w__9)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0BadVAddr_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0Count_ref  : M (mword 32)) >>= fun w__11 =>
+         returnm ((mips_zero_extend 64 w__11)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBEntryHi_ref >>= fun w__12 =>
+         returnm ((_get_TLBEntryHiReg_bits w__12)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0Compare_ref  : M (mword 32)) >>= fun w__13 =>
+         returnm ((mips_zero_extend 64 w__13)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg CP0Status_ref >>= fun w__14 =>
+         returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__14))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg CP0Cause_ref >>= fun w__15 =>
+         returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__15))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0EPC_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                   B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                       : mword 32))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B1;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B1;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0ConfigK0_ref  : M (mword 3)) >>= fun w__17 =>
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec
+                           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 15)
+                           (concat_vec (vec_of_bits [B1]  : mword 1)
+                              (concat_vec (vec_of_bits [B1;B0]  : mword 2)
+                                 (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                    (concat_vec (vec_of_bits [B0;B0;B1]  : mword 3)
+                                       (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4) w__17))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B1]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec TLBIndexMax
+                           (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                              (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                 (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                    (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                       (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                          (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                                             (concat_vec (bool_to_bits have_cp2)
+                                                (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                   (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                      (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                         (concat_vec (vec_of_bits [B0]  : mword 1)
+                                                            (concat_vec
+                                                               (vec_of_bits [B0]  : mword 1)
+                                                               (vec_of_bits [B0]  : mword 1))))))))))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64
+                     (concat_vec (vec_of_bits [B1]  : mword 1)
+                        (concat_vec (vec_of_bits [B0;B0;B0]  : mword 3)
+                           (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                              (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                 (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                    (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                       (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                          (concat_vec (vec_of_bits [B0;B0;B0;B0]  : mword 4)
+                                             (vec_of_bits [B0;B0;B0;B0]  : mword 4))))))))))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B1;B1]  : mword 3)))) then
+         returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64)
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B1;B0;B1]  : mword 3)))) then
+         returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                B0]
+                    : mword 64)
+          : mword 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0LLAddr_ref  : M (mword 64))
+          : M (bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         returnm ((mips_zero_extend 64 (vec_of_bits [B0]  : mword 1))
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         read_reg TLBXContext_ref >>= fun w__19 =>
+         returnm ((_get_XContextReg_bits w__19)
+          : bits 64)
+       else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0]  : mword 5))
+                   (eq_vec b__49 (vec_of_bits [B0;B0;B0]  : mword 3)))) then
+         (read_reg CP0ErrorEPC_ref  : M (mword 64))
+          : M (bits 64)
+       else (SignalException ResI)  : M (bits 64))
+       : M (mword 64)
+   end >>= fun result =>
+   (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0)))
+    : M (unit).
+
+Definition execute_MADDU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))  : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_MADD (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64)  : M (bits 64)
+    else
+      returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0))
+       : bits 64)) >>= fun mul_result =>
+   (read_reg HI_ref  : M (mword 64)) >>= fun w__1 =>
+   (read_reg LO_ref  : M (mword 64)) >>= fun w__2 =>
+   let result :=
+     add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in
+   write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >>
+   write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0))
+    : M (unit).
+
+Definition execute_Load (width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width in
+   (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr)  : M (unit)
+    else
+      TLBTranslate vAddr LoadData >>= fun pAddr =>
+      (if (linked) then
+         write_reg CP0LLBit_ref (vec_of_bits [B1]  : mword 1) >>
+         write_reg CP0LLAddr_ref pAddr >>
+         (match width with
+          | W =>
+             MEMr_reserve_wrapper pAddr 4 >>= fun w__1 =>
+             returnm ((extendLoad w__1 sign)
+              : bits 64)
+          | D =>
+             MEMr_reserve_wrapper pAddr 8 >>= fun w__2 =>
+             returnm ((extendLoad w__2 sign)
+              : bits 64)
+          | _ => (throw (Error_internal_error tt))  : M (mword 64)
+          end)
+          : M (mword 64)
+       else
+         (match width with
+          | B => MEMr_wrapper pAddr 1 >>= fun w__5 => returnm ((extendLoad w__5 sign)  : bits 64)
+          | H => MEMr_wrapper pAddr 2 >>= fun w__6 => returnm ((extendLoad w__6 sign)  : bits 64)
+          | W => MEMr_wrapper pAddr 4 >>= fun w__7 => returnm ((extendLoad w__7 sign)  : bits 64)
+          | D => MEMr_wrapper pAddr 8 >>= fun w__8 => returnm ((extendLoad w__8 sign)  : bits 64)
+          end)
+          : M (mword 64)) >>= fun memResult =>
+      (wGPR rt memResult)
+       : M (unit))
+    : M (unit).
+
+Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2)) 4 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__4 := subrange_vec_dec vAddr 1 0 in
+   let result : bits 32 :=
+     if ((eq_vec b__4 (vec_of_bits [B0;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24)
+     else if ((eq_vec b__4 (vec_of_bits [B0;B1]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16)
+     else if ((eq_vec b__4 (vec_of_bits [B1;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8)
+     else mem_val in
+   (wGPR rt (mips_sign_extend 64 result))
+    : M (unit).
+
+Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0]  : mword 2)) 4 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__0 := subrange_vec_dec vAddr 1 0 in
+   let result : bits 32 :=
+     if ((eq_vec b__0 (vec_of_bits [B0;B0]  : mword 2))) then mem_val
+     else if ((eq_vec b__0 (vec_of_bits [B0;B1]  : mword 2))) then
+       concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0)
+     else if ((eq_vec b__0 (vec_of_bits [B1;B0]  : mword 2))) then
+       concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0)
+     else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in
+   (wGPR rt (mips_sign_extend 64 result))
+    : M (unit).
+
+Definition execute_LUI (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   (wGPR rt
+      (mips_sign_extend 64
+         (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16))))
+    : M (unit).
+
+Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3)) 8 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__24 := subrange_vec_dec vAddr 2 0 in
+   (wGPR rt
+      (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40)
+       else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16)
+       else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8)
+       else mem_val))
+    : M (unit).
+
+Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) 
+: M (unit) :=
+   rGPR base >>= fun w__0 =>
+   let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL in
+   TLBTranslate vAddr LoadData >>= fun pAddr =>
+   MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0]  : mword 3)) 8 >>= fun mem_val =>
+   rGPR rt >>= fun reg_val =>
+   let b__16 := subrange_vec_dec vAddr 2 0 in
+   (wGPR rt
+      (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0]  : mword 3))) then mem_val
+       else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0)
+       else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0)
+       else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0)
+       else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0]  : mword 3))) then
+         concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0)
+       else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0)))
+    : M (unit).
+
+Definition execute_JR (rs : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (execute_branch w__0)  : M (unit).
+
+Definition execute_JALR (rs : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   execute_branch w__0 >>
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__1 => (wGPR rd (add_vec_int w__1 8))  : M (unit).
+
+Definition execute_JAL (offset : mword 26) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   execute_branch
+     (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28)
+        (concat_vec offset (vec_of_bits [B0;B0]  : mword 2))) >>
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__1 =>
+   (wGPR (vec_of_bits [B1;B1;B1;B1;B1]  : mword 5) (add_vec_int w__1 8))
+    : M (unit).
+
+Definition execute_J (offset : mword 26) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   (execute_branch
+      (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28)
+         (concat_vec offset (vec_of_bits [B0;B0]  : mword 2))))
+    : M (unit).
+
+Definition execute_HCF (g__18 : unit)  : unit := tt.
+
+Definition execute_ERET (g__23 : unit) 
+: M (unit) :=
+   checkCP0Access tt >>
+   let '_ := (ERETHook tt)  : unit in
+   write_reg CP0LLBit_ref (vec_of_bits [B0]  : mword 1) >>
+   read_reg CP0Status_ref >>= fun w__0 =>
+   (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0))  : bool) ((bit_to_bool B1)  : bool)))
+    then
+      (read_reg CP0ErrorEPC_ref  : M (mword 64)) >>= fun w__1 =>
+      write_reg nextPC_ref w__1 >>
+      (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  : mword 1))
+       : M (unit)
+    else
+      (read_reg CP0EPC_ref  : M (mword 64)) >>= fun w__2 =>
+      write_reg nextPC_ref w__2 >>
+      (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  : mword 1))
+       : M (unit))
+    : M (unit).
+
+Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (sub_vec w__0 w__1))  : M (unit).
+
+Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64))  : bool)
+           ((bit_to_bool (access_vec_dec temp65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rd (subrange_vec_dec temp65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 5 0 in
+   shift_bits_right temp sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   let sa32 := concat_vec (vec_of_bits [B1]  : mword 1) sa in
+   shift_bits_right temp sa32 >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp => shift_bits_right temp sa >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   rGPR rs >>= fun w__0 =>
+   let sa := subrange_vec_dec w__0 5 0 in
+   shift_bits_right_arith temp sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp =>
+   let sa32 := concat_vec (vec_of_bits [B1]  : mword 1) sa in
+   shift_bits_right_arith temp sa32 >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun temp => shift_bits_right_arith temp sa >>= fun w__0 => (wGPR rd w__0)  : M (unit).
+
+Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   rGPR rs >>= fun w__1 =>
+   shift_bits_left w__0 (subrange_vec_dec w__1 5 0) >>= fun w__2 => (wGPR rd w__2)  : M (unit).
+
+Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 =>
+   shift_bits_left w__0 (concat_vec (vec_of_bits [B1]  : mword 1) sa) >>= fun w__1 =>
+   (wGPR rd w__1)
+    : M (unit).
+
+Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) 
+: M (unit) :=
+   rGPR rt >>= fun w__0 => shift_bits_left w__0 sa >>= fun w__1 => (wGPR rd w__1)  : M (unit).
+
+Definition execute_DMULTU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let result := mult_vec w__0 w__1 in
+   write_reg HI_ref (subrange_vec_dec result 127 64) >>
+   write_reg LO_ref (subrange_vec_dec result 63 0)
+    : M (unit).
+
+Definition execute_DMULT (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let result := mults_vec w__0 w__1 in
+   write_reg HI_ref (subrange_vec_dec result 127 64) >>
+   write_reg LO_ref (subrange_vec_dec result 63 0)
+    : M (unit).
+
+Definition execute_DIVU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal)
+           (orb (NotWordVal rtVal)
+              (eq_vec rtVal
+                 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0]
+                   : mword 64))))) then
+      undefined_bitvector 32 >>= fun w__0 =>
+      undefined_bitvector 32 >>= fun w__1 =>
+      returnm ((w__0  : bits 32, w__1  : bits 32)
+       : (bits 32 * bits 32))
+    else
+      let '(existT _ si _) := uint (subrange_vec_dec rsVal 31 0) in
+      let '(existT _ ti _) := uint (subrange_vec_dec rtVal 31 0) in
+      let qi := Z.quot si ti in
+      let ri := Z.rem si ti in
+      returnm ((to_bits 32 qi, to_bits 32 ri)
+       : (mword 32 * mword 32))) >>= fun '(q, r) =>
+   write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q)  : M (unit).
+
+Definition execute_DIV (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun rsVal =>
+   rGPR rt >>= fun rtVal =>
+   (if ((orb (NotWordVal rsVal)
+           (orb (NotWordVal rtVal)
+              (eq_vec rtVal
+                 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                               B0]
+                   : mword 64))))) then
+      undefined_bitvector 32 >>= fun w__0 =>
+      undefined_bitvector 32 >>= fun w__1 =>
+      returnm ((w__0  : bits 32, w__1  : bits 32)
+       : (bits 32 * bits 32))
+    else
+      let '(existT _ si _) := sint (subrange_vec_dec rsVal 31 0) in
+      let '(existT _ ti _) := sint (subrange_vec_dec rtVal 31 0) in
+      let qi := Z.quot si ti in
+      let ri := Z.sub si (Z.mul ti qi) in
+      returnm ((to_bits 32 qi, to_bits 32 ri)
+       : (mword 32 * mword 32))) >>= fun '(q, r) =>
+   write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q)  : M (unit).
+
+Definition execute_DDIVU (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rsVal _) := uint w__0 in
+   rGPR rt >>= fun w__1 =>
+   let '(existT _ rtVal _) := uint w__1 in
+   (if ((eq_range (build_ex rtVal) (build_ex 0))) then
+      undefined_bitvector 64 >>= fun w__2 =>
+      undefined_bitvector 64 >>= fun w__3 =>
+      returnm ((w__2  : bits 64, w__3  : bits 64)
+       : (bits 64 * bits 64))
+    else
+      let qi := Z.quot rsVal rtVal in
+      let ri := Z.rem rsVal rtVal in
+      returnm ((to_bits 64 qi, to_bits 64 ri)
+       : (mword 64 * mword 64))) >>= fun '(q, r) =>
+   write_reg LO_ref q >> write_reg HI_ref r  : M (unit).
+
+Definition execute_DDIV (rs : mword 5) (rt : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let '(existT _ rsVal _) := sint w__0 in
+   rGPR rt >>= fun w__1 =>
+   let '(existT _ rtVal _) := sint w__1 in
+   (if ((eq_range (build_ex rtVal) (build_ex 0))) then
+      undefined_bitvector 64 >>= fun w__2 =>
+      undefined_bitvector 64 >>= fun w__3 =>
+      returnm ((w__2  : bits 64, w__3  : bits 64)
+       : (bits 64 * bits 64))
+    else
+      let qi := Z.quot rsVal rtVal in
+      let ri := Z.sub rsVal (Z.mul qi rtVal) in
+      returnm ((to_bits 64 qi, to_bits 64 ri)
+       : (mword 64 * mword 64))) >>= fun '(q, r) =>
+   write_reg LO_ref q >> write_reg HI_ref r  : M (unit).
+
+Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (add_vec w__0 w__1))  : M (unit).
+
+Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm)))  : M (unit).
+
+Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64))  : bool)
+           ((bit_to_bool (access_vec_dec sum65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rt (subrange_vec_dec sum65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rt >>= fun w__1 =>
+   let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in
+   (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64))  : bool)
+           ((bit_to_bool (access_vec_dec sum65 63))
+            : bool))) then
+      (SignalException Ov)
+       : M (unit)
+    else (wGPR rd (subrange_vec_dec sum65 63 0))  : M (unit))
+    : M (unit).
+
+Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) 
+: M (unit) :=
+   (checkCP0Access tt)
+    : M (unit).
+
+Definition execute_BREAK (g__15 : unit)  : M (unit) := (SignalException Bp)  : M (unit).
+
+Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 =>
+   rGPR rd >>= fun w__1 =>
+   (if (((bits_to_bool
+            (xor_vec ((bool_to_bits (eq_vec w__0 w__1))  : mword 1) ((bool_to_bits ne)  : mword 1)))
+       : bool)) then
+      let offset : bits 64 :=
+        add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0]  : mword 2))) 4 in
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+      (execute_branch (add_vec w__2 offset))
+       : M (unit)
+    else if (likely) then
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__3 =>
+      write_reg nextPC_ref (add_vec_int w__3 8)
+       : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_BCMPZ (rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) 
+: M (unit) :=
+   (read_reg PC_ref  : M (mword 64)) >>= fun w__0 =>
+   let linkVal := add_vec_int w__0 8 in
+   rGPR rs >>= fun regVal =>
+   let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0]  : mword 1)) in
+   (if (condition) then
+      let offset : bits 64 :=
+        add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0]  : mword 2))) 4 in
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__1 =>
+      (execute_branch (add_vec w__1 offset))
+       : M (unit)
+    else if (likely) then
+      (read_reg PC_ref  : M (mword 64)) >>= fun w__2 =>
+      write_reg nextPC_ref (add_vec_int w__2 8)
+       : M (unit)
+    else returnm (tt  : unit)) >>
+   (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1]  : mword 5) linkVal)  : M (unit)
+    else returnm (tt  : unit))
+    : M (unit).
+
+Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm)))  : M (unit).
+
+Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (and_vec w__0 w__1))  : M (unit).
+
+Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      (wGPR rd
+         (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0)  : M (unit)
+    else
+      (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm))))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0)  : M (unit)
+    else
+      let sum33 : bits 33 :=
+        add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32))  : bool)
+              ((bit_to_bool (access_vec_dec sum33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) 
+: M (unit) :=
+   rGPR rs >>= fun opA =>
+   rGPR rt >>= fun opB =>
+   (if ((orb (NotWordVal opA) (NotWordVal opB))) then
+      undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0)  : M (unit)
+    else
+      let sum33 : bits 33 :=
+        add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0))
+          (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in
+      (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32))  : bool)
+              ((bit_to_bool (access_vec_dec sum33 31))
+               : bool))) then
+         (SignalException Ov)
+          : M (unit)
+       else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0)))  : M (unit))
+       : M (unit))
+    : M (unit).
+
+Definition execute (merge_var : ast) 
+: M (unit) :=
+   match merge_var with
+   | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm)  : M (unit)
+   | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd)  : M (unit)
+   | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm)  : M (unit)
+   | DADD (rs,rt,rd) => (execute_DADD rs rt rd)  : M (unit)
+   | ADD (rs,rt,rd) => (execute_ADD rs rt rd)  : M (unit)
+   | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm)  : M (unit)
+   | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd)  : M (unit)
+   | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm)  : M (unit)
+   | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd)  : M (unit)
+   | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd)  : M (unit)
+   | SUB (rs,rt,rd) => (execute_SUB rs rt rd)  : M (unit)
+   | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd)  : M (unit)
+   | AND (rs,rt,rd) => (execute_AND rs rt rd)  : M (unit)
+   | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm)  : M (unit)
+   | OR (rs,rt,rd) => (execute_OR rs rt rd)  : M (unit)
+   | ORI (rs,rt,imm) => (execute_ORI rs rt imm)  : M (unit)
+   | NOR (rs,rt,rd) => (execute_NOR rs rt rd)  : M (unit)
+   | XOR (rs,rt,rd) => (execute_XOR rs rt rd)  : M (unit)
+   | XORI (rs,rt,imm) => (execute_XORI rs rt imm)  : M (unit)
+   | LUI (rt,imm) => (execute_LUI rt imm)  : M (unit)
+   | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa)  : M (unit)
+   | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa)  : M (unit)
+   | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd)  : M (unit)
+   | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa)  : M (unit)
+   | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa)  : M (unit)
+   | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd)  : M (unit)
+   | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa)  : M (unit)
+   | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa)  : M (unit)
+   | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd)  : M (unit)
+   | SLL (rt,rd,sa) => (execute_SLL rt rd sa)  : M (unit)
+   | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd)  : M (unit)
+   | SRA (rt,rd,sa) => (execute_SRA rt rd sa)  : M (unit)
+   | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd)  : M (unit)
+   | SRL (rt,rd,sa) => (execute_SRL rt rd sa)  : M (unit)
+   | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd)  : M (unit)
+   | SLT (rs,rt,rd) => (execute_SLT rs rt rd)  : M (unit)
+   | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm)  : M (unit)
+   | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd)  : M (unit)
+   | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm)  : M (unit)
+   | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd)  : M (unit)
+   | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd)  : M (unit)
+   | MFHI (rd) => (execute_MFHI rd)  : M (unit)
+   | MFLO (rd) => (execute_MFLO rd)  : M (unit)
+   | MTHI (rs) => (execute_MTHI rs)  : M (unit)
+   | MTLO (rs) => (execute_MTLO rs)  : M (unit)
+   | MUL (rs,rt,rd) => (execute_MUL rs rt rd)  : M (unit)
+   | MULT (rs,rt) => (execute_MULT rs rt)  : M (unit)
+   | MULTU (rs,rt) => (execute_MULTU rs rt)  : M (unit)
+   | DMULT (rs,rt) => (execute_DMULT rs rt)  : M (unit)
+   | DMULTU (rs,rt) => (execute_DMULTU rs rt)  : M (unit)
+   | MADD (rs,rt) => (execute_MADD rs rt)  : M (unit)
+   | MADDU (rs,rt) => (execute_MADDU rs rt)  : M (unit)
+   | MSUB (rs,rt) => (execute_MSUB rs rt)  : M (unit)
+   | MSUBU (rs,rt) => (execute_MSUBU rs rt)  : M (unit)
+   | DIV (rs,rt) => (execute_DIV rs rt)  : M (unit)
+   | DIVU (rs,rt) => (execute_DIVU rs rt)  : M (unit)
+   | DDIV (rs,rt) => (execute_DDIV rs rt)  : M (unit)
+   | DDIVU (rs,rt) => (execute_DDIVU rs rt)  : M (unit)
+   | J (offset) => (execute_J offset)  : M (unit)
+   | JAL (offset) => (execute_JAL offset)  : M (unit)
+   | JR (rs) => (execute_JR rs)  : M (unit)
+   | JALR (rs,rd) => (execute_JALR rs rd)  : M (unit)
+   | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely)  : M (unit)
+   | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely)  : M (unit)
+   | SYSCALL (g__14) => (execute_SYSCALL g__14)  : M (unit)
+   | BREAK (g__15) => (execute_BREAK g__15)  : M (unit)
+   | WAIT (g__16) => (execute_WAIT g__16)  : M (unit)
+   | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp)  : M (unit)
+   | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp)  : M (unit)
+   | Load (width,sign,linked,base,rt,offset) =>
+      (execute_Load width sign linked base rt offset)  : M (unit)
+   | Store (width,conditional,base,rt,offset) =>
+      (execute_Store width conditional base rt offset)  : M (unit)
+   | LWL (base,rt,offset) => (execute_LWL base rt offset)  : M (unit)
+   | LWR (base,rt,offset) => (execute_LWR base rt offset)  : M (unit)
+   | SWL (base,rt,offset) => (execute_SWL base rt offset)  : M (unit)
+   | SWR (base,rt,offset) => (execute_SWR base rt offset)  : M (unit)
+   | LDL (base,rt,offset) => (execute_LDL base rt offset)  : M (unit)
+   | LDR (base,rt,offset) => (execute_LDR base rt offset)  : M (unit)
+   | SDL (base,rt,offset) => (execute_SDL base rt offset)  : M (unit)
+   | SDR (base,rt,offset) => (execute_SDR base rt offset)  : M (unit)
+   | CACHE (base,op,imm) => (execute_CACHE base op imm)  : M (unit)
+   | SYNC (g__17) => (execute_SYNC g__17)  : M (unit)
+   | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double)  : M (unit)
+   | HCF (g__18) => returnm ((execute_HCF g__18)  : unit)
+   | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double)  : M (unit)
+   | TLBWI (g__19) => (execute_TLBWI g__19)  : M (unit)
+   | TLBWR (g__20) => (execute_TLBWR g__20)  : M (unit)
+   | TLBR (g__21) => (execute_TLBR g__21)  : M (unit)
+   | TLBP (g__22) => (execute_TLBP g__22)  : M (unit)
+   | RDHWR (rt,rd) => (execute_RDHWR rt rd)  : M (unit)
+   | ERET (g__23) => (execute_ERET g__23)  : M (unit)
+   | RI (g__24) => (execute_RI g__24)  : M (unit)
+   end.
+
+Definition supported_instructions (instr : ast)  : option ast := Some instr.
+
+Definition initialize_registers '(tt : unit) 
+: M (unit) :=
+   undefined_bitvector 64 >>= fun w__0 =>
+   write_reg PC_ref w__0 >>
+   undefined_bitvector 64 >>= fun w__1 =>
+   write_reg nextPC_ref w__1 >>
+   undefined_bitvector 1 >>= fun w__2 =>
+   write_reg TLBProbe_ref w__2 >>
+   undefined_bitvector 6 >>= fun w__3 =>
+   write_reg TLBIndex_ref w__3 >>
+   undefined_bitvector 6 >>= fun w__4 =>
+   write_reg TLBRandom_ref w__4 >>
+   undefined_TLBEntryLoReg tt >>= fun w__5 =>
+   write_reg TLBEntryLo0_ref w__5 >>
+   undefined_TLBEntryLoReg tt >>= fun w__6 =>
+   write_reg TLBEntryLo1_ref w__6 >>
+   undefined_ContextReg tt >>= fun w__7 =>
+   write_reg TLBContext_ref w__7 >>
+   undefined_bitvector 16 >>= fun w__8 =>
+   write_reg TLBPageMask_ref w__8 >>
+   undefined_bitvector 6 >>= fun w__9 =>
+   write_reg TLBWired_ref w__9 >>
+   undefined_TLBEntryHiReg tt >>= fun w__10 =>
+   write_reg TLBEntryHi_ref w__10 >>
+   undefined_XContextReg tt >>= fun w__11 =>
+   write_reg TLBXContext_ref w__11 >>
+   undefined_TLBEntry tt >>= fun w__12 =>
+   write_reg TLBEntry00_ref w__12 >>
+   undefined_TLBEntry tt >>= fun w__13 =>
+   write_reg TLBEntry01_ref w__13 >>
+   undefined_TLBEntry tt >>= fun w__14 =>
+   write_reg TLBEntry02_ref w__14 >>
+   undefined_TLBEntry tt >>= fun w__15 =>
+   write_reg TLBEntry03_ref w__15 >>
+   undefined_TLBEntry tt >>= fun w__16 =>
+   write_reg TLBEntry04_ref w__16 >>
+   undefined_TLBEntry tt >>= fun w__17 =>
+   write_reg TLBEntry05_ref w__17 >>
+   undefined_TLBEntry tt >>= fun w__18 =>
+   write_reg TLBEntry06_ref w__18 >>
+   undefined_TLBEntry tt >>= fun w__19 =>
+   write_reg TLBEntry07_ref w__19 >>
+   undefined_TLBEntry tt >>= fun w__20 =>
+   write_reg TLBEntry08_ref w__20 >>
+   undefined_TLBEntry tt >>= fun w__21 =>
+   write_reg TLBEntry09_ref w__21 >>
+   undefined_TLBEntry tt >>= fun w__22 =>
+   write_reg TLBEntry10_ref w__22 >>
+   undefined_TLBEntry tt >>= fun w__23 =>
+   write_reg TLBEntry11_ref w__23 >>
+   undefined_TLBEntry tt >>= fun w__24 =>
+   write_reg TLBEntry12_ref w__24 >>
+   undefined_TLBEntry tt >>= fun w__25 =>
+   write_reg TLBEntry13_ref w__25 >>
+   undefined_TLBEntry tt >>= fun w__26 =>
+   write_reg TLBEntry14_ref w__26 >>
+   undefined_TLBEntry tt >>= fun w__27 =>
+   write_reg TLBEntry15_ref w__27 >>
+   undefined_TLBEntry tt >>= fun w__28 =>
+   write_reg TLBEntry16_ref w__28 >>
+   undefined_TLBEntry tt >>= fun w__29 =>
+   write_reg TLBEntry17_ref w__29 >>
+   undefined_TLBEntry tt >>= fun w__30 =>
+   write_reg TLBEntry18_ref w__30 >>
+   undefined_TLBEntry tt >>= fun w__31 =>
+   write_reg TLBEntry19_ref w__31 >>
+   undefined_TLBEntry tt >>= fun w__32 =>
+   write_reg TLBEntry20_ref w__32 >>
+   undefined_TLBEntry tt >>= fun w__33 =>
+   write_reg TLBEntry21_ref w__33 >>
+   undefined_TLBEntry tt >>= fun w__34 =>
+   write_reg TLBEntry22_ref w__34 >>
+   undefined_TLBEntry tt >>= fun w__35 =>
+   write_reg TLBEntry23_ref w__35 >>
+   undefined_TLBEntry tt >>= fun w__36 =>
+   write_reg TLBEntry24_ref w__36 >>
+   undefined_TLBEntry tt >>= fun w__37 =>
+   write_reg TLBEntry25_ref w__37 >>
+   undefined_TLBEntry tt >>= fun w__38 =>
+   write_reg TLBEntry26_ref w__38 >>
+   undefined_TLBEntry tt >>= fun w__39 =>
+   write_reg TLBEntry27_ref w__39 >>
+   undefined_TLBEntry tt >>= fun w__40 =>
+   write_reg TLBEntry28_ref w__40 >>
+   undefined_TLBEntry tt >>= fun w__41 =>
+   write_reg TLBEntry29_ref w__41 >>
+   undefined_TLBEntry tt >>= fun w__42 =>
+   write_reg TLBEntry30_ref w__42 >>
+   undefined_TLBEntry tt >>= fun w__43 =>
+   write_reg TLBEntry31_ref w__43 >>
+   undefined_TLBEntry tt >>= fun w__44 =>
+   write_reg TLBEntry32_ref w__44 >>
+   undefined_TLBEntry tt >>= fun w__45 =>
+   write_reg TLBEntry33_ref w__45 >>
+   undefined_TLBEntry tt >>= fun w__46 =>
+   write_reg TLBEntry34_ref w__46 >>
+   undefined_TLBEntry tt >>= fun w__47 =>
+   write_reg TLBEntry35_ref w__47 >>
+   undefined_TLBEntry tt >>= fun w__48 =>
+   write_reg TLBEntry36_ref w__48 >>
+   undefined_TLBEntry tt >>= fun w__49 =>
+   write_reg TLBEntry37_ref w__49 >>
+   undefined_TLBEntry tt >>= fun w__50 =>
+   write_reg TLBEntry38_ref w__50 >>
+   undefined_TLBEntry tt >>= fun w__51 =>
+   write_reg TLBEntry39_ref w__51 >>
+   undefined_TLBEntry tt >>= fun w__52 =>
+   write_reg TLBEntry40_ref w__52 >>
+   undefined_TLBEntry tt >>= fun w__53 =>
+   write_reg TLBEntry41_ref w__53 >>
+   undefined_TLBEntry tt >>= fun w__54 =>
+   write_reg TLBEntry42_ref w__54 >>
+   undefined_TLBEntry tt >>= fun w__55 =>
+   write_reg TLBEntry43_ref w__55 >>
+   undefined_TLBEntry tt >>= fun w__56 =>
+   write_reg TLBEntry44_ref w__56 >>
+   undefined_TLBEntry tt >>= fun w__57 =>
+   write_reg TLBEntry45_ref w__57 >>
+   undefined_TLBEntry tt >>= fun w__58 =>
+   write_reg TLBEntry46_ref w__58 >>
+   undefined_TLBEntry tt >>= fun w__59 =>
+   write_reg TLBEntry47_ref w__59 >>
+   undefined_TLBEntry tt >>= fun w__60 =>
+   write_reg TLBEntry48_ref w__60 >>
+   undefined_TLBEntry tt >>= fun w__61 =>
+   write_reg TLBEntry49_ref w__61 >>
+   undefined_TLBEntry tt >>= fun w__62 =>
+   write_reg TLBEntry50_ref w__62 >>
+   undefined_TLBEntry tt >>= fun w__63 =>
+   write_reg TLBEntry51_ref w__63 >>
+   undefined_TLBEntry tt >>= fun w__64 =>
+   write_reg TLBEntry52_ref w__64 >>
+   undefined_TLBEntry tt >>= fun w__65 =>
+   write_reg TLBEntry53_ref w__65 >>
+   undefined_TLBEntry tt >>= fun w__66 =>
+   write_reg TLBEntry54_ref w__66 >>
+   undefined_TLBEntry tt >>= fun w__67 =>
+   write_reg TLBEntry55_ref w__67 >>
+   undefined_TLBEntry tt >>= fun w__68 =>
+   write_reg TLBEntry56_ref w__68 >>
+   undefined_TLBEntry tt >>= fun w__69 =>
+   write_reg TLBEntry57_ref w__69 >>
+   undefined_TLBEntry tt >>= fun w__70 =>
+   write_reg TLBEntry58_ref w__70 >>
+   undefined_TLBEntry tt >>= fun w__71 =>
+   write_reg TLBEntry59_ref w__71 >>
+   undefined_TLBEntry tt >>= fun w__72 =>
+   write_reg TLBEntry60_ref w__72 >>
+   undefined_TLBEntry tt >>= fun w__73 =>
+   write_reg TLBEntry61_ref w__73 >>
+   undefined_TLBEntry tt >>= fun w__74 =>
+   write_reg TLBEntry62_ref w__74 >>
+   undefined_TLBEntry tt >>= fun w__75 =>
+   write_reg TLBEntry63_ref w__75 >>
+   undefined_bitvector 32 >>= fun w__76 =>
+   write_reg CP0Compare_ref w__76 >>
+   undefined_CauseReg tt >>= fun w__77 =>
+   write_reg CP0Cause_ref w__77 >>
+   undefined_bitvector 64 >>= fun w__78 =>
+   write_reg CP0EPC_ref w__78 >>
+   undefined_bitvector 64 >>= fun w__79 =>
+   write_reg CP0ErrorEPC_ref w__79 >>
+   undefined_bitvector 1 >>= fun w__80 =>
+   write_reg CP0LLBit_ref w__80 >>
+   undefined_bitvector 64 >>= fun w__81 =>
+   write_reg CP0LLAddr_ref w__81 >>
+   undefined_bitvector 64 >>= fun w__82 =>
+   write_reg CP0BadVAddr_ref w__82 >>
+   undefined_bitvector 32 >>= fun w__83 =>
+   write_reg CP0Count_ref w__83 >>
+   undefined_bitvector 32 >>= fun w__84 =>
+   write_reg CP0HWREna_ref w__84 >>
+   undefined_bitvector 64 >>= fun w__85 =>
+   write_reg CP0UserLocal_ref w__85 >>
+   undefined_bitvector 3 >>= fun w__86 =>
+   write_reg CP0ConfigK0_ref w__86 >>
+   undefined_StatusReg tt >>= fun w__87 =>
+   write_reg CP0Status_ref w__87 >>
+   undefined_bitvector 1 >>= fun w__88 =>
+   write_reg branchPending_ref w__88 >>
+   undefined_bitvector 1 >>= fun w__89 =>
+   write_reg inBranchDelay_ref w__89 >>
+   undefined_bitvector 64 >>= fun w__90 =>
+   write_reg delayedPC_ref w__90 >>
+   undefined_bitvector 64 >>= fun w__91 =>
+   write_reg HI_ref w__91 >>
+   undefined_bitvector 64 >>= fun w__92 =>
+   write_reg LO_ref w__92 >>
+   undefined_bitvector 64 >>= fun w__93 =>
+   undefined_vector 32 w__93 >>= fun w__94 =>
+   write_reg GPR_ref w__94 >>
+   undefined_bitvector 8 >>= fun w__95 =>
+   write_reg UART_WDATA_ref w__95 >>
+   undefined_bitvector 1 >>= fun w__96 =>
+   write_reg UART_WRITTEN_ref w__96 >>
+   undefined_bitvector 8 >>= fun w__97 =>
+   write_reg UART_RDATA_ref w__97 >>
+   undefined_bitvector 1 >>= fun w__98 => write_reg UART_RVALID_ref w__98  : M (unit).
+
+Definition initial_regstate : regstate :=
+{| UART_RVALID := (vec_of_bits [B0]  : mword 1); 
+   UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8); 
+   UART_WRITTEN := (vec_of_bits [B0]  : mword 1); 
+   UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  : mword 8); 
+   GPR :=
+     (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0]
+                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0]
+                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0]
+                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0]
+                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0]
+                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0]
+                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0]
+                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0]
+                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0]
+                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0]
+                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0]
+                                                                                                                                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                               B0]
+                                                                                                                                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                             B0]
+                                                                                                                                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                           B0]
+                                                                                                                                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                         B0]
+                                                                                                                                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                       B0]
+                                                                                                                                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                     B0]
+                                                                                                                                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                   B0]
+                                                                                                                                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                 B0]
+                                                                                                                                                                                                                                                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                               B0]
+                                                                                                                                                                                                                                                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                                                                                                                                                             B0]
+                                                                                                                                                                                                                                                                                                                 : mword 64);
+                       (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                     B0]
+                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                   B0]
+                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                 B0]
+                                                     : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                               B0]
+                                                                   : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                             B0]
+                                                                                 : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                           B0]
+                                                                                               : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                         B0]
+                                                                                                             : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                       B0]
+                                                                                                                           : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                     B0]
+                                                                                                                                         : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                   B0]
+                                                                                                                                                       : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                                                                                                                                                 B0]
+                                                                                                                                                                     : mword 64)]); 
+   LO :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   HI :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   delayedPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   inBranchDelay := (vec_of_bits [B0]  : mword 1); 
+   branchPending := (vec_of_bits [B0]  : mword 1); 
+   CP0Status :=
+     ({| StatusReg_StatusReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 32) |}); 
+   CP0ConfigK0 := (vec_of_bits [B0;B0;B0]  : mword 3); 
+   CP0UserLocal :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0HWREna :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   CP0Count :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   CP0BadVAddr :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0LLAddr :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0LLBit := (vec_of_bits [B0]  : mword 1); 
+   CP0ErrorEPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0EPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   CP0Cause :=
+     ({| CauseReg_CauseReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 32) |}); 
+   CP0Compare :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+       : mword 32); 
+   TLBEntry63 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry62 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry61 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry60 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry59 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry58 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry57 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry56 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry55 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry54 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry53 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry52 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry51 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry50 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry49 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry48 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry47 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry46 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry45 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry44 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry43 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry42 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry41 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry40 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry39 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry38 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry37 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry36 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry35 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry34 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry33 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry32 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry31 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry30 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry29 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry28 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry27 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry26 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry25 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry24 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry23 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry22 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry21 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry20 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry19 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry18 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry17 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry16 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry15 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry14 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry13 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry12 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry11 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry10 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry09 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry08 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry07 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry06 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry05 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry04 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry03 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry02 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry01 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntry00 :=
+     ({| TLBEntry_TLBEntry_chunk_1 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+             : mword 53); 
+         TLBEntry_TLBEntry_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBXContext :=
+     ({| XContextReg_XContextReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryHi :=
+     ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  : mword 16); 
+   TLBContext :=
+     ({| ContextReg_ContextReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryLo1 :=
+     ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBEntryLo0 :=
+     ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 :=
+           (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                         B0]
+             : mword 64) |}); 
+   TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0]  : mword 6); 
+   TLBProbe := (vec_of_bits [B0]  : mword 1); 
+   nextPC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64); 
+   PC :=
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       : mword 64) |}.
+
+
+End Content.
diff --git a/snapshots/coq/mips/mips_extras.v b/snapshots/coq/mips/mips_extras.v
new file mode 100644
index 00000000..cc905f11
--- /dev/null
+++ b/snapshots/coq/mips/mips_extras.v
@@ -0,0 +1,162 @@
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import String.
+Require Import List.
+Import List.ListNotations.
+(*
+val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
+val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e
+val MEMr_tag         : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
+val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e
+*)
+Definition MEMr {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size            : monad regval (mword b) e := read_mem Read_plain addr size.
+Definition MEMr_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size    : monad regval (mword b) e := read_mem Read_reserve addr size.
+
+(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*)
+Definition read_tag_bool {regval a e} (addr : mword a) : monad regval bool e :=
+  read_tag addr >>= fun t =>
+  maybe_fail "read_tag_bool" (bool_of_bitU t).
+
+(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*)
+Definition write_tag_bool {regval a e} (addr : mword a) t : monad regval unit e :=
+ write_tag addr (bitU_of_bool t) >>= fun _ => returnm tt.
+
+Definition MEMr_tag {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e :=
+  read_mem Read_plain addr size >>= fun v =>
+  read_tag_bool addr >>= fun t =>
+  returnm (t, v).
+
+Definition MEMr_tag_reserve {regval a b e} `{ArithFact (b >= 0)} (addr : mword a) size : monad regval (bool * mword b) e :=
+  read_mem Read_plain addr size >>= fun v =>
+  read_tag_bool addr >>= fun t =>
+  returnm (t, v).
+
+(*
+val MEMea                 : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_conditional     : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_tag             : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e
+*)
+Definition MEMea {regval a e} (addr : mword a) size                : monad regval unit e := write_mem_ea Write_plain addr size.
+Definition MEMea_conditional {regval a e} (addr : mword a) size    : monad regval unit e := write_mem_ea Write_conditional addr size.
+
+Definition MEMea_tag {regval a e} (addr : mword a) size            : monad regval unit e := write_mem_ea Write_plain addr size.
+Definition MEMea_tag_conditional {regval a e} (addr : mword a) size : monad regval unit e := write_mem_ea Write_conditional addr size.
+
+(*
+val MEMval                 : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e
+val MEMval_conditional     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e
+val MEMval_tag             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e
+val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e
+*)
+Definition MEMval {regval a b e} (_ : mword a) (size : Z) (v : mword b)                      : monad regval unit e := write_mem_val v >>= fun _ => returnm tt.
+Definition MEMval_conditional {regval a b e} (_ : mword a) (size : Z) (v : mword b)          : monad regval bool e := write_mem_val v >>= fun b => returnm (if b then true else false).
+Definition MEMval_tag {regval a b e} (addr : mword a) (size : Z) t (v : mword b)             : monad regval unit e := write_mem_val v >>= fun _ => write_tag_bool addr t >>= fun _ => returnm tt.
+Definition MEMval_tag_conditional {regval a b e} (addr : mword a) (size : Z) t (v : mword b) : monad regval bool e := write_mem_val v >>= fun b => write_tag_bool addr t >>= fun _ => returnm (if b then true else false).
+
+(*val MEM_sync  : forall 'regval 'e. unit -> monad 'regval unit 'e*)
+
+Definition MEM_sync {regval e} (_:unit) : monad regval unit e := barrier Barrier_MIPS_SYNC.
+
+(* Some wrappers copied from aarch64_extras *)
+(* TODO: Harmonise into a common library *)
+(*
+Definition get_slice_int_bl len n lo :=
+  (* TODO: Is this the intended behaviour? *)
+  let hi := lo + len - 1 in
+  let bs := bools_of_int (hi + 1) n in
+  subrange_list false bs hi lo
+
+val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a
+Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo)
+*)
+Definition write_ram {rv e} m size (_ : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv unit e :=
+  MEMea addr size >>
+  MEMval addr size data.
+
+Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := MEMr addr size.
+(*
+Definition string_of_bits bs := string_of_bv (bits_of bs).
+Definition string_of_int := show
+
+Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits))
+Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits))
+*)
+Definition shift_bits_left {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_left" (unsigned n) >>= fun n =>
+  returnm (shiftl v n).
+
+Definition shift_bits_right {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_right" (unsigned n) >>= fun n =>
+  returnm (shiftr v n).
+
+Definition shift_bits_right_arith {rv e a b} (v : mword a) (n : mword b) : monad rv (mword a) e :=
+  maybe_fail "shift_bits_right" (unsigned n) >>= fun n =>
+  returnm (arith_shiftr v n).
+
+(* Use constants for undefined values for now *)
+Definition internal_pick {rv a e} (vs : list a) : monad rv a e :=
+match vs with
+| (h::_) => returnm h
+| _ => Fail "empty list in internal_pick"
+end.
+Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string.
+Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt.
+Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*)
+Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len).
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0).
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*)
+Definition undefined_bits {rv e} := @undefined_bitvector rv e.
+Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU.
+(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*)
+Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i).
+Definition undefined_atom {rv e} i : monad rv Z e := returnm i.
+Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii).
+
+Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt.
+
+(*val elf_entry : unit -> integer*)
+Definition elf_entry (_:unit) : Z := 0.
+(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*)
+
+(*Definition print_bits msg bs := prerr_endline (msg ^ (string_of_bits bs))
+
+val get_time_ns : unit -> integer*)
+Definition get_time_ns (_:unit) : Z := 0.
+(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*)
+
+Definition eq_bit (x : bitU) (y : bitU) : bool :=
+  match x, y with
+  | B0, B0 => true
+  | B1, B1 => true
+  | BU, BU => true
+  | _,_ => false
+  end.
+
+Require Import Zeuclid.
+Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}.
+refine (build_ex (ZEuclid.modulo m n)).
+constructor.
+destruct H.
+assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. }
+rewrite <- H at 3.
+lapply (ZEuclid.mod_always_pos m n); omega.
+Qed.
+
+(* Override the more general version *)
+
+Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r.
+Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r.
+
+
+Definition print_endline (_:string) : unit := tt.
+Definition prerr_endline (_:string) : unit := tt.
+Definition prerr_string (_:string) : unit := tt.
+Definition putchar {T} (_:T) : unit := tt.
+Require DecimalString.
+Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z).
diff --git a/snapshots/coq/mips/mips_types.v b/snapshots/coq/mips/mips_types.v
new file mode 100644
index 00000000..12d7d6cd
--- /dev/null
+++ b/snapshots/coq/mips/mips_types.v
@@ -0,0 +1,1441 @@
+(*Generated by Sail from mips.*)
+Require Import Sail2_instr_kinds.
+Require Import Sail2_values.
+Require Import Sail2_operators_mwords.
+Require Import Sail2_prompt_monad.
+Require Import Sail2_prompt.
+Require Import Sail2_state.
+Definition bits (n : Z) : Type := mword n.
+
+
+
+Inductive exception  :=
+  ISAException : unit -> exception
+  | Error_not_implemented : string -> exception
+  | Error_misaligned_access : unit -> exception
+  | Error_EBREAK : unit -> exception
+  | Error_internal_error : unit -> exception.
+Arguments exception : clear implicits.
+
+
+
+Record CauseReg  := { CauseReg_CauseReg_chunk_0 : mword 32; }.
+Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}).
+
+Record StatusReg  := { StatusReg_StatusReg_chunk_0 : mword 32; }.
+Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}).
+
+Record TLBEntryLoReg  := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}).
+
+Record TLBEntryHiReg  := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}).
+
+Record ContextReg  := { ContextReg_ContextReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}).
+
+Record XContextReg  := { XContextReg_XContextReg_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}).
+
+Definition TLBIndexT  : Type := bits 6.
+
+Record TLBEntry  := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }.
+Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}).
+Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}).
+
+Inductive Exception :=
+  Interrupt
+  | TLBMod
+  | TLBL
+  | TLBS
+  | AdEL
+  | AdES
+  | Sys
+  | Bp
+  | ResI
+  | CpU
+  | Ov
+  | Tr
+  | C2E
+  | C2Trap
+  | XTLBRefillL
+  | XTLBRefillS
+  | XTLBInvL
+  | XTLBInvS
+  | MCheck.
+Scheme Equality for Exception.
+Instance Decidable_eq_Exception : forall (x y : Exception), Decidable (x = y) :=
+Decidable_eq_from_dec Exception_eq_dec.
+
+
+Inductive MemAccessType := Instruction | LoadData | StoreData.
+Scheme Equality for MemAccessType.
+Instance Decidable_eq_MemAccessType : forall (x y : MemAccessType), Decidable (x = y) :=
+Decidable_eq_from_dec MemAccessType_eq_dec.
+
+
+Inductive AccessLevel := User | Supervisor | Kernel.
+Scheme Equality for AccessLevel.
+Instance Decidable_eq_AccessLevel : forall (x y : AccessLevel), Decidable (x = y) :=
+Decidable_eq_from_dec AccessLevel_eq_dec.
+
+
+Definition regno  : Type := bits 5.
+
+Definition imm16  : Type := bits 16.
+
+Definition regregreg  : Type := (regno * regno * regno).
+
+Definition regregimm16  : Type := (regno * regno * imm16).
+
+Inductive decode_failure :=
+  no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error.
+Scheme Equality for decode_failure.
+Instance Decidable_eq_decode_failure : forall (x y : decode_failure), Decidable (x = y) :=
+Decidable_eq_from_dec decode_failure_eq_dec.
+
+
+Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU.
+Scheme Equality for Comparison.
+Instance Decidable_eq_Comparison : forall (x y : Comparison), Decidable (x = y) :=
+Decidable_eq_from_dec Comparison_eq_dec.
+
+
+Inductive WordType := B | H | W | D.
+Scheme Equality for WordType.
+Instance Decidable_eq_WordType : forall (x y : WordType), Decidable (x = y) :=
+Decidable_eq_from_dec WordType_eq_dec.
+
+
+Inductive WordTypeUnaligned := WL | WR | DL | DR.
+Scheme Equality for WordTypeUnaligned.
+Instance Decidable_eq_WordTypeUnaligned : forall (x y : WordTypeUnaligned), Decidable (x = y) :=
+Decidable_eq_from_dec WordTypeUnaligned_eq_dec.
+
+
+Inductive ast  :=
+  DADDIU : (regno * regno * imm16) -> ast
+  | DADDU : (regno * regno * regno) -> ast
+  | DADDI : (regno * regno * bits 16) -> ast
+  | DADD : (regno * regno * regno) -> ast
+  | ADD : (regno * regno * regno) -> ast
+  | ADDI : (regno * regno * bits 16) -> ast
+  | ADDU : (regno * regno * regno) -> ast
+  | ADDIU : (regno * regno * bits 16) -> ast
+  | DSUBU : (regno * regno * regno) -> ast
+  | DSUB : (regno * regno * regno) -> ast
+  | SUB : (regno * regno * regno) -> ast
+  | SUBU : (regno * regno * regno) -> ast
+  | AND : (regno * regno * regno) -> ast
+  | ANDI : (regno * regno * bits 16) -> ast
+  | OR : (regno * regno * regno) -> ast
+  | ORI : (regno * regno * bits 16) -> ast
+  | NOR : (regno * regno * regno) -> ast
+  | XOR : (regno * regno * regno) -> ast
+  | XORI : (regno * regno * bits 16) -> ast
+  | LUI : (regno * imm16) -> ast
+  | DSLL : (regno * regno * regno) -> ast
+  | DSLL32 : (regno * regno * regno) -> ast
+  | DSLLV : (regno * regno * regno) -> ast
+  | DSRA : (regno * regno * regno) -> ast
+  | DSRA32 : (regno * regno * regno) -> ast
+  | DSRAV : (regno * regno * regno) -> ast
+  | DSRL : (regno * regno * regno) -> ast
+  | DSRL32 : (regno * regno * regno) -> ast
+  | DSRLV : (regno * regno * regno) -> ast
+  | SLL : (regno * regno * regno) -> ast
+  | SLLV : (regno * regno * regno) -> ast
+  | SRA : (regno * regno * regno) -> ast
+  | SRAV : (regno * regno * regno) -> ast
+  | SRL : (regno * regno * regno) -> ast
+  | SRLV : (regno * regno * regno) -> ast
+  | SLT : (regno * regno * regno) -> ast
+  | SLTI : (regno * regno * bits 16) -> ast
+  | SLTU : (regno * regno * regno) -> ast
+  | SLTIU : (regno * regno * bits 16) -> ast
+  | MOVN : (regno * regno * regno) -> ast
+  | MOVZ : (regno * regno * regno) -> ast
+  | MFHI : regno -> ast
+  | MFLO : regno -> ast
+  | MTHI : regno -> ast
+  | MTLO : regno -> ast
+  | MUL : (regno * regno * regno) -> ast
+  | MULT : (regno * regno) -> ast
+  | MULTU : (regno * regno) -> ast
+  | DMULT : (regno * regno) -> ast
+  | DMULTU : (regno * regno) -> ast
+  | MADD : (regno * regno) -> ast
+  | MADDU : (regno * regno) -> ast
+  | MSUB : (regno * regno) -> ast
+  | MSUBU : (regno * regno) -> ast
+  | DIV : (regno * regno) -> ast
+  | DIVU : (regno * regno) -> ast
+  | DDIV : (regno * regno) -> ast
+  | DDIVU : (regno * regno) -> ast
+  | J : bits 26 -> ast
+  | JAL : bits 26 -> ast
+  | JR : regno -> ast
+  | JALR : (regno * regno) -> ast
+  | BEQ : (regno * regno * imm16 * bool * bool) -> ast
+  | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast
+  | SYSCALL : unit -> ast
+  | BREAK : unit -> ast
+  | WAIT : unit -> ast
+  | TRAPREG : (regno * regno * Comparison) -> ast
+  | TRAPIMM : (regno * imm16 * Comparison) -> ast
+  | Load : (WordType * bool * bool * regno * regno * imm16) -> ast
+  | Store : (WordType * bool * regno * regno * imm16) -> ast
+  | LWL : (regno * regno * bits 16) -> ast
+  | LWR : (regno * regno * bits 16) -> ast
+  | SWL : (regno * regno * bits 16) -> ast
+  | SWR : (regno * regno * bits 16) -> ast
+  | LDL : (regno * regno * bits 16) -> ast
+  | LDR : (regno * regno * bits 16) -> ast
+  | SDL : (regno * regno * bits 16) -> ast
+  | SDR : (regno * regno * bits 16) -> ast
+  | CACHE : (regno * regno * bits 16) -> ast
+  | SYNC : unit -> ast
+  | MFC0 : (regno * regno * bits 3 * bool) -> ast
+  | HCF : unit -> ast
+  | MTC0 : (regno * regno * bits 3 * bool) -> ast
+  | TLBWI : unit -> ast
+  | TLBWR : unit -> ast
+  | TLBR : unit -> ast
+  | TLBP : unit -> ast
+  | RDHWR : (regno * regno) -> ast
+  | ERET : unit -> ast
+  | RI : unit -> ast.
+Arguments ast : clear implicits.
+
+
+
+Inductive register_value  :=
+  Regval_vector : (Z * bool * list register_value) -> register_value
+  | Regval_list : list register_value -> register_value
+  | Regval_option : option register_value -> register_value
+  | Regval_CauseReg : CauseReg -> register_value
+  | Regval_ContextReg : ContextReg -> register_value
+  | Regval_StatusReg : StatusReg -> register_value
+  | Regval_TLBEntry : TLBEntry -> register_value
+  | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value
+  | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value
+  | Regval_XContextReg : XContextReg -> register_value
+  | Regval_vector_16_dec_bit : mword 16 -> register_value
+  | Regval_vector_1_dec_bit : mword 1 -> register_value
+  | Regval_vector_32_dec_bit : mword 32 -> register_value
+  | Regval_vector_3_dec_bit : mword 3 -> register_value
+  | Regval_vector_64_dec_bit : mword 64 -> register_value
+  | Regval_vector_6_dec_bit : mword 6 -> register_value
+  | Regval_vector_8_dec_bit : mword 8 -> register_value.
+Arguments register_value : clear implicits.
+
+
+
+Record regstate  :=
+  { UART_RVALID : mword 1;
+    UART_RDATA : mword 8;
+    UART_WRITTEN : mword 1;
+    UART_WDATA : mword 8;
+    GPR : vec (mword 64) 32;
+    LO : mword 64;
+    HI : mword 64;
+    delayedPC : mword 64;
+    inBranchDelay : mword 1;
+    branchPending : mword 1;
+    CP0Status : StatusReg;
+    CP0ConfigK0 : mword 3;
+    CP0UserLocal : mword 64;
+    CP0HWREna : mword 32;
+    CP0Count : mword 32;
+    CP0BadVAddr : mword 64;
+    CP0LLAddr : mword 64;
+    CP0LLBit : mword 1;
+    CP0ErrorEPC : mword 64;
+    CP0EPC : mword 64;
+    CP0Cause : CauseReg;
+    CP0Compare : mword 32;
+    TLBEntry63 : TLBEntry;
+    TLBEntry62 : TLBEntry;
+    TLBEntry61 : TLBEntry;
+    TLBEntry60 : TLBEntry;
+    TLBEntry59 : TLBEntry;
+    TLBEntry58 : TLBEntry;
+    TLBEntry57 : TLBEntry;
+    TLBEntry56 : TLBEntry;
+    TLBEntry55 : TLBEntry;
+    TLBEntry54 : TLBEntry;
+    TLBEntry53 : TLBEntry;
+    TLBEntry52 : TLBEntry;
+    TLBEntry51 : TLBEntry;
+    TLBEntry50 : TLBEntry;
+    TLBEntry49 : TLBEntry;
+    TLBEntry48 : TLBEntry;
+    TLBEntry47 : TLBEntry;
+    TLBEntry46 : TLBEntry;
+    TLBEntry45 : TLBEntry;
+    TLBEntry44 : TLBEntry;
+    TLBEntry43 : TLBEntry;
+    TLBEntry42 : TLBEntry;
+    TLBEntry41 : TLBEntry;
+    TLBEntry40 : TLBEntry;
+    TLBEntry39 : TLBEntry;
+    TLBEntry38 : TLBEntry;
+    TLBEntry37 : TLBEntry;
+    TLBEntry36 : TLBEntry;
+    TLBEntry35 : TLBEntry;
+    TLBEntry34 : TLBEntry;
+    TLBEntry33 : TLBEntry;
+    TLBEntry32 : TLBEntry;
+    TLBEntry31 : TLBEntry;
+    TLBEntry30 : TLBEntry;
+    TLBEntry29 : TLBEntry;
+    TLBEntry28 : TLBEntry;
+    TLBEntry27 : TLBEntry;
+    TLBEntry26 : TLBEntry;
+    TLBEntry25 : TLBEntry;
+    TLBEntry24 : TLBEntry;
+    TLBEntry23 : TLBEntry;
+    TLBEntry22 : TLBEntry;
+    TLBEntry21 : TLBEntry;
+    TLBEntry20 : TLBEntry;
+    TLBEntry19 : TLBEntry;
+    TLBEntry18 : TLBEntry;
+    TLBEntry17 : TLBEntry;
+    TLBEntry16 : TLBEntry;
+    TLBEntry15 : TLBEntry;
+    TLBEntry14 : TLBEntry;
+    TLBEntry13 : TLBEntry;
+    TLBEntry12 : TLBEntry;
+    TLBEntry11 : TLBEntry;
+    TLBEntry10 : TLBEntry;
+    TLBEntry09 : TLBEntry;
+    TLBEntry08 : TLBEntry;
+    TLBEntry07 : TLBEntry;
+    TLBEntry06 : TLBEntry;
+    TLBEntry05 : TLBEntry;
+    TLBEntry04 : TLBEntry;
+    TLBEntry03 : TLBEntry;
+    TLBEntry02 : TLBEntry;
+    TLBEntry01 : TLBEntry;
+    TLBEntry00 : TLBEntry;
+    TLBXContext : XContextReg;
+    TLBEntryHi : TLBEntryHiReg;
+    TLBWired : mword 6;
+    TLBPageMask : mword 16;
+    TLBContext : ContextReg;
+    TLBEntryLo1 : TLBEntryLoReg;
+    TLBEntryLo0 : TLBEntryLoReg;
+    TLBRandom : mword 6;
+    TLBIndex : mword 6;
+    TLBProbe : mword 1;
+    nextPC : mword 64;
+    PC : mword 64; }.
+Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'delayedPC' := e ]}" := ({| delayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'inBranchDelay' := e ]}" := ({| inBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'branchPending' := e ]}" := ({| branchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; nextPC := nextPC r; PC := PC r |}).
+Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}).
+Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r |}).
+
+
+
+Definition CauseReg_of_regval (merge_var : register_value) 
+: option CauseReg :=
+   match merge_var with | Regval_CauseReg (v) => Some v | g__13 => None end.
+
+Definition regval_of_CauseReg (v : CauseReg)  : register_value := Regval_CauseReg v.
+
+Definition ContextReg_of_regval (merge_var : register_value) 
+: option ContextReg :=
+   match merge_var with | Regval_ContextReg (v) => Some v | g__12 => None end.
+
+Definition regval_of_ContextReg (v : ContextReg)  : register_value := Regval_ContextReg v.
+
+Definition StatusReg_of_regval (merge_var : register_value) 
+: option StatusReg :=
+   match merge_var with | Regval_StatusReg (v) => Some v | g__11 => None end.
+
+Definition regval_of_StatusReg (v : StatusReg)  : register_value := Regval_StatusReg v.
+
+Definition TLBEntry_of_regval (merge_var : register_value) 
+: option TLBEntry :=
+   match merge_var with | Regval_TLBEntry (v) => Some v | g__10 => None end.
+
+Definition regval_of_TLBEntry (v : TLBEntry)  : register_value := Regval_TLBEntry v.
+
+Definition TLBEntryHiReg_of_regval (merge_var : register_value) 
+: option TLBEntryHiReg :=
+   match merge_var with | Regval_TLBEntryHiReg (v) => Some v | g__9 => None end.
+
+Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg)  : register_value := Regval_TLBEntryHiReg v.
+
+Definition TLBEntryLoReg_of_regval (merge_var : register_value) 
+: option TLBEntryLoReg :=
+   match merge_var with | Regval_TLBEntryLoReg (v) => Some v | g__8 => None end.
+
+Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg)  : register_value := Regval_TLBEntryLoReg v.
+
+Definition XContextReg_of_regval (merge_var : register_value) 
+: option XContextReg :=
+   match merge_var with | Regval_XContextReg (v) => Some v | g__7 => None end.
+
+Definition regval_of_XContextReg (v : XContextReg)  : register_value := Regval_XContextReg v.
+
+Definition vector_16_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 16) :=
+   match merge_var with | Regval_vector_16_dec_bit (v) => Some v | g__6 => None end.
+
+Definition regval_of_vector_16_dec_bit (v : mword 16) 
+: register_value :=
+   Regval_vector_16_dec_bit v.
+
+Definition vector_1_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 1) :=
+   match merge_var with | Regval_vector_1_dec_bit (v) => Some v | g__5 => None end.
+
+Definition regval_of_vector_1_dec_bit (v : mword 1)  : register_value := Regval_vector_1_dec_bit v.
+
+Definition vector_32_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 32) :=
+   match merge_var with | Regval_vector_32_dec_bit (v) => Some v | g__4 => None end.
+
+Definition regval_of_vector_32_dec_bit (v : mword 32) 
+: register_value :=
+   Regval_vector_32_dec_bit v.
+
+Definition vector_3_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 3) :=
+   match merge_var with | Regval_vector_3_dec_bit (v) => Some v | g__3 => None end.
+
+Definition regval_of_vector_3_dec_bit (v : mword 3)  : register_value := Regval_vector_3_dec_bit v.
+
+Definition vector_64_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 64) :=
+   match merge_var with | Regval_vector_64_dec_bit (v) => Some v | g__2 => None end.
+
+Definition regval_of_vector_64_dec_bit (v : mword 64) 
+: register_value :=
+   Regval_vector_64_dec_bit v.
+
+Definition vector_6_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 6) :=
+   match merge_var with | Regval_vector_6_dec_bit (v) => Some v | g__1 => None end.
+
+Definition regval_of_vector_6_dec_bit (v : mword 6)  : register_value := Regval_vector_6_dec_bit v.
+
+Definition vector_8_dec_bit_of_regval (merge_var : register_value) 
+: option (mword 8) :=
+   match merge_var with | Regval_vector_8_dec_bit (v) => Some v | g__0 => None end.
+
+Definition regval_of_vector_8_dec_bit (v : mword 8)  : register_value := Regval_vector_8_dec_bit v.
+
+
+
+Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with
+  | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None
+  | _ => None
+end.
+
+Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)).
+
+Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with
+  | Regval_list v => just_list (List.map of_regval v)
+  | _ => None
+end.
+
+Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs).
+
+Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with
+  | Regval_option v => option_map of_regval v
+  | _ => None
+end.
+
+Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v).
+
+
+Definition UART_RVALID_ref := {|
+  name := "UART_RVALID";
+  read_from := (fun s => s.(UART_RVALID));
+  write_to := (fun v s => ({[ s with UART_RVALID := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition UART_RDATA_ref := {|
+  name := "UART_RDATA";
+  read_from := (fun s => s.(UART_RDATA));
+  write_to := (fun v s => ({[ s with UART_RDATA := v ]}));
+  of_regval := (fun v => vector_8_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_8_dec_bit v) |}.
+
+Definition UART_WRITTEN_ref := {|
+  name := "UART_WRITTEN";
+  read_from := (fun s => s.(UART_WRITTEN));
+  write_to := (fun v s => ({[ s with UART_WRITTEN := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition UART_WDATA_ref := {|
+  name := "UART_WDATA";
+  read_from := (fun s => s.(UART_WDATA));
+  write_to := (fun v s => ({[ s with UART_WDATA := v ]}));
+  of_regval := (fun v => vector_8_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_8_dec_bit v) |}.
+
+Definition GPR_ref := {|
+  name := "GPR";
+  read_from := (fun s => s.(GPR));
+  write_to := (fun v s => ({[ s with GPR := v ]}));
+  of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v);
+  regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}.
+
+Definition LO_ref := {|
+  name := "LO";
+  read_from := (fun s => s.(LO));
+  write_to := (fun v s => ({[ s with LO := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition HI_ref := {|
+  name := "HI";
+  read_from := (fun s => s.(HI));
+  write_to := (fun v s => ({[ s with HI := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition delayedPC_ref := {|
+  name := "delayedPC";
+  read_from := (fun s => s.(delayedPC));
+  write_to := (fun v s => ({[ s with delayedPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition inBranchDelay_ref := {|
+  name := "inBranchDelay";
+  read_from := (fun s => s.(inBranchDelay));
+  write_to := (fun v s => ({[ s with inBranchDelay := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition branchPending_ref := {|
+  name := "branchPending";
+  read_from := (fun s => s.(branchPending));
+  write_to := (fun v s => ({[ s with branchPending := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition CP0Status_ref := {|
+  name := "CP0Status";
+  read_from := (fun s => s.(CP0Status));
+  write_to := (fun v s => ({[ s with CP0Status := v ]}));
+  of_regval := (fun v => StatusReg_of_regval v);
+  regval_of := (fun v => regval_of_StatusReg v) |}.
+
+Definition CP0ConfigK0_ref := {|
+  name := "CP0ConfigK0";
+  read_from := (fun s => s.(CP0ConfigK0));
+  write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]}));
+  of_regval := (fun v => vector_3_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_3_dec_bit v) |}.
+
+Definition CP0UserLocal_ref := {|
+  name := "CP0UserLocal";
+  read_from := (fun s => s.(CP0UserLocal));
+  write_to := (fun v s => ({[ s with CP0UserLocal := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0HWREna_ref := {|
+  name := "CP0HWREna";
+  read_from := (fun s => s.(CP0HWREna));
+  write_to := (fun v s => ({[ s with CP0HWREna := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition CP0Count_ref := {|
+  name := "CP0Count";
+  read_from := (fun s => s.(CP0Count));
+  write_to := (fun v s => ({[ s with CP0Count := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition CP0BadVAddr_ref := {|
+  name := "CP0BadVAddr";
+  read_from := (fun s => s.(CP0BadVAddr));
+  write_to := (fun v s => ({[ s with CP0BadVAddr := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0LLAddr_ref := {|
+  name := "CP0LLAddr";
+  read_from := (fun s => s.(CP0LLAddr));
+  write_to := (fun v s => ({[ s with CP0LLAddr := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0LLBit_ref := {|
+  name := "CP0LLBit";
+  read_from := (fun s => s.(CP0LLBit));
+  write_to := (fun v s => ({[ s with CP0LLBit := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition CP0ErrorEPC_ref := {|
+  name := "CP0ErrorEPC";
+  read_from := (fun s => s.(CP0ErrorEPC));
+  write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0EPC_ref := {|
+  name := "CP0EPC";
+  read_from := (fun s => s.(CP0EPC));
+  write_to := (fun v s => ({[ s with CP0EPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition CP0Cause_ref := {|
+  name := "CP0Cause";
+  read_from := (fun s => s.(CP0Cause));
+  write_to := (fun v s => ({[ s with CP0Cause := v ]}));
+  of_regval := (fun v => CauseReg_of_regval v);
+  regval_of := (fun v => regval_of_CauseReg v) |}.
+
+Definition CP0Compare_ref := {|
+  name := "CP0Compare";
+  read_from := (fun s => s.(CP0Compare));
+  write_to := (fun v s => ({[ s with CP0Compare := v ]}));
+  of_regval := (fun v => vector_32_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_32_dec_bit v) |}.
+
+Definition TLBEntry63_ref := {|
+  name := "TLBEntry63";
+  read_from := (fun s => s.(TLBEntry63));
+  write_to := (fun v s => ({[ s with TLBEntry63 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry62_ref := {|
+  name := "TLBEntry62";
+  read_from := (fun s => s.(TLBEntry62));
+  write_to := (fun v s => ({[ s with TLBEntry62 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry61_ref := {|
+  name := "TLBEntry61";
+  read_from := (fun s => s.(TLBEntry61));
+  write_to := (fun v s => ({[ s with TLBEntry61 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry60_ref := {|
+  name := "TLBEntry60";
+  read_from := (fun s => s.(TLBEntry60));
+  write_to := (fun v s => ({[ s with TLBEntry60 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry59_ref := {|
+  name := "TLBEntry59";
+  read_from := (fun s => s.(TLBEntry59));
+  write_to := (fun v s => ({[ s with TLBEntry59 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry58_ref := {|
+  name := "TLBEntry58";
+  read_from := (fun s => s.(TLBEntry58));
+  write_to := (fun v s => ({[ s with TLBEntry58 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry57_ref := {|
+  name := "TLBEntry57";
+  read_from := (fun s => s.(TLBEntry57));
+  write_to := (fun v s => ({[ s with TLBEntry57 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry56_ref := {|
+  name := "TLBEntry56";
+  read_from := (fun s => s.(TLBEntry56));
+  write_to := (fun v s => ({[ s with TLBEntry56 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry55_ref := {|
+  name := "TLBEntry55";
+  read_from := (fun s => s.(TLBEntry55));
+  write_to := (fun v s => ({[ s with TLBEntry55 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry54_ref := {|
+  name := "TLBEntry54";
+  read_from := (fun s => s.(TLBEntry54));
+  write_to := (fun v s => ({[ s with TLBEntry54 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry53_ref := {|
+  name := "TLBEntry53";
+  read_from := (fun s => s.(TLBEntry53));
+  write_to := (fun v s => ({[ s with TLBEntry53 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry52_ref := {|
+  name := "TLBEntry52";
+  read_from := (fun s => s.(TLBEntry52));
+  write_to := (fun v s => ({[ s with TLBEntry52 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry51_ref := {|
+  name := "TLBEntry51";
+  read_from := (fun s => s.(TLBEntry51));
+  write_to := (fun v s => ({[ s with TLBEntry51 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry50_ref := {|
+  name := "TLBEntry50";
+  read_from := (fun s => s.(TLBEntry50));
+  write_to := (fun v s => ({[ s with TLBEntry50 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry49_ref := {|
+  name := "TLBEntry49";
+  read_from := (fun s => s.(TLBEntry49));
+  write_to := (fun v s => ({[ s with TLBEntry49 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry48_ref := {|
+  name := "TLBEntry48";
+  read_from := (fun s => s.(TLBEntry48));
+  write_to := (fun v s => ({[ s with TLBEntry48 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry47_ref := {|
+  name := "TLBEntry47";
+  read_from := (fun s => s.(TLBEntry47));
+  write_to := (fun v s => ({[ s with TLBEntry47 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry46_ref := {|
+  name := "TLBEntry46";
+  read_from := (fun s => s.(TLBEntry46));
+  write_to := (fun v s => ({[ s with TLBEntry46 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry45_ref := {|
+  name := "TLBEntry45";
+  read_from := (fun s => s.(TLBEntry45));
+  write_to := (fun v s => ({[ s with TLBEntry45 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry44_ref := {|
+  name := "TLBEntry44";
+  read_from := (fun s => s.(TLBEntry44));
+  write_to := (fun v s => ({[ s with TLBEntry44 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry43_ref := {|
+  name := "TLBEntry43";
+  read_from := (fun s => s.(TLBEntry43));
+  write_to := (fun v s => ({[ s with TLBEntry43 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry42_ref := {|
+  name := "TLBEntry42";
+  read_from := (fun s => s.(TLBEntry42));
+  write_to := (fun v s => ({[ s with TLBEntry42 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry41_ref := {|
+  name := "TLBEntry41";
+  read_from := (fun s => s.(TLBEntry41));
+  write_to := (fun v s => ({[ s with TLBEntry41 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry40_ref := {|
+  name := "TLBEntry40";
+  read_from := (fun s => s.(TLBEntry40));
+  write_to := (fun v s => ({[ s with TLBEntry40 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry39_ref := {|
+  name := "TLBEntry39";
+  read_from := (fun s => s.(TLBEntry39));
+  write_to := (fun v s => ({[ s with TLBEntry39 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry38_ref := {|
+  name := "TLBEntry38";
+  read_from := (fun s => s.(TLBEntry38));
+  write_to := (fun v s => ({[ s with TLBEntry38 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry37_ref := {|
+  name := "TLBEntry37";
+  read_from := (fun s => s.(TLBEntry37));
+  write_to := (fun v s => ({[ s with TLBEntry37 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry36_ref := {|
+  name := "TLBEntry36";
+  read_from := (fun s => s.(TLBEntry36));
+  write_to := (fun v s => ({[ s with TLBEntry36 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry35_ref := {|
+  name := "TLBEntry35";
+  read_from := (fun s => s.(TLBEntry35));
+  write_to := (fun v s => ({[ s with TLBEntry35 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry34_ref := {|
+  name := "TLBEntry34";
+  read_from := (fun s => s.(TLBEntry34));
+  write_to := (fun v s => ({[ s with TLBEntry34 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry33_ref := {|
+  name := "TLBEntry33";
+  read_from := (fun s => s.(TLBEntry33));
+  write_to := (fun v s => ({[ s with TLBEntry33 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry32_ref := {|
+  name := "TLBEntry32";
+  read_from := (fun s => s.(TLBEntry32));
+  write_to := (fun v s => ({[ s with TLBEntry32 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry31_ref := {|
+  name := "TLBEntry31";
+  read_from := (fun s => s.(TLBEntry31));
+  write_to := (fun v s => ({[ s with TLBEntry31 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry30_ref := {|
+  name := "TLBEntry30";
+  read_from := (fun s => s.(TLBEntry30));
+  write_to := (fun v s => ({[ s with TLBEntry30 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry29_ref := {|
+  name := "TLBEntry29";
+  read_from := (fun s => s.(TLBEntry29));
+  write_to := (fun v s => ({[ s with TLBEntry29 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry28_ref := {|
+  name := "TLBEntry28";
+  read_from := (fun s => s.(TLBEntry28));
+  write_to := (fun v s => ({[ s with TLBEntry28 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry27_ref := {|
+  name := "TLBEntry27";
+  read_from := (fun s => s.(TLBEntry27));
+  write_to := (fun v s => ({[ s with TLBEntry27 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry26_ref := {|
+  name := "TLBEntry26";
+  read_from := (fun s => s.(TLBEntry26));
+  write_to := (fun v s => ({[ s with TLBEntry26 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry25_ref := {|
+  name := "TLBEntry25";
+  read_from := (fun s => s.(TLBEntry25));
+  write_to := (fun v s => ({[ s with TLBEntry25 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry24_ref := {|
+  name := "TLBEntry24";
+  read_from := (fun s => s.(TLBEntry24));
+  write_to := (fun v s => ({[ s with TLBEntry24 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry23_ref := {|
+  name := "TLBEntry23";
+  read_from := (fun s => s.(TLBEntry23));
+  write_to := (fun v s => ({[ s with TLBEntry23 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry22_ref := {|
+  name := "TLBEntry22";
+  read_from := (fun s => s.(TLBEntry22));
+  write_to := (fun v s => ({[ s with TLBEntry22 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry21_ref := {|
+  name := "TLBEntry21";
+  read_from := (fun s => s.(TLBEntry21));
+  write_to := (fun v s => ({[ s with TLBEntry21 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry20_ref := {|
+  name := "TLBEntry20";
+  read_from := (fun s => s.(TLBEntry20));
+  write_to := (fun v s => ({[ s with TLBEntry20 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry19_ref := {|
+  name := "TLBEntry19";
+  read_from := (fun s => s.(TLBEntry19));
+  write_to := (fun v s => ({[ s with TLBEntry19 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry18_ref := {|
+  name := "TLBEntry18";
+  read_from := (fun s => s.(TLBEntry18));
+  write_to := (fun v s => ({[ s with TLBEntry18 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry17_ref := {|
+  name := "TLBEntry17";
+  read_from := (fun s => s.(TLBEntry17));
+  write_to := (fun v s => ({[ s with TLBEntry17 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry16_ref := {|
+  name := "TLBEntry16";
+  read_from := (fun s => s.(TLBEntry16));
+  write_to := (fun v s => ({[ s with TLBEntry16 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry15_ref := {|
+  name := "TLBEntry15";
+  read_from := (fun s => s.(TLBEntry15));
+  write_to := (fun v s => ({[ s with TLBEntry15 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry14_ref := {|
+  name := "TLBEntry14";
+  read_from := (fun s => s.(TLBEntry14));
+  write_to := (fun v s => ({[ s with TLBEntry14 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry13_ref := {|
+  name := "TLBEntry13";
+  read_from := (fun s => s.(TLBEntry13));
+  write_to := (fun v s => ({[ s with TLBEntry13 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry12_ref := {|
+  name := "TLBEntry12";
+  read_from := (fun s => s.(TLBEntry12));
+  write_to := (fun v s => ({[ s with TLBEntry12 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry11_ref := {|
+  name := "TLBEntry11";
+  read_from := (fun s => s.(TLBEntry11));
+  write_to := (fun v s => ({[ s with TLBEntry11 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry10_ref := {|
+  name := "TLBEntry10";
+  read_from := (fun s => s.(TLBEntry10));
+  write_to := (fun v s => ({[ s with TLBEntry10 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry09_ref := {|
+  name := "TLBEntry09";
+  read_from := (fun s => s.(TLBEntry09));
+  write_to := (fun v s => ({[ s with TLBEntry09 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry08_ref := {|
+  name := "TLBEntry08";
+  read_from := (fun s => s.(TLBEntry08));
+  write_to := (fun v s => ({[ s with TLBEntry08 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry07_ref := {|
+  name := "TLBEntry07";
+  read_from := (fun s => s.(TLBEntry07));
+  write_to := (fun v s => ({[ s with TLBEntry07 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry06_ref := {|
+  name := "TLBEntry06";
+  read_from := (fun s => s.(TLBEntry06));
+  write_to := (fun v s => ({[ s with TLBEntry06 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry05_ref := {|
+  name := "TLBEntry05";
+  read_from := (fun s => s.(TLBEntry05));
+  write_to := (fun v s => ({[ s with TLBEntry05 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry04_ref := {|
+  name := "TLBEntry04";
+  read_from := (fun s => s.(TLBEntry04));
+  write_to := (fun v s => ({[ s with TLBEntry04 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry03_ref := {|
+  name := "TLBEntry03";
+  read_from := (fun s => s.(TLBEntry03));
+  write_to := (fun v s => ({[ s with TLBEntry03 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry02_ref := {|
+  name := "TLBEntry02";
+  read_from := (fun s => s.(TLBEntry02));
+  write_to := (fun v s => ({[ s with TLBEntry02 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry01_ref := {|
+  name := "TLBEntry01";
+  read_from := (fun s => s.(TLBEntry01));
+  write_to := (fun v s => ({[ s with TLBEntry01 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBEntry00_ref := {|
+  name := "TLBEntry00";
+  read_from := (fun s => s.(TLBEntry00));
+  write_to := (fun v s => ({[ s with TLBEntry00 := v ]}));
+  of_regval := (fun v => TLBEntry_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntry v) |}.
+
+Definition TLBXContext_ref := {|
+  name := "TLBXContext";
+  read_from := (fun s => s.(TLBXContext));
+  write_to := (fun v s => ({[ s with TLBXContext := v ]}));
+  of_regval := (fun v => XContextReg_of_regval v);
+  regval_of := (fun v => regval_of_XContextReg v) |}.
+
+Definition TLBEntryHi_ref := {|
+  name := "TLBEntryHi";
+  read_from := (fun s => s.(TLBEntryHi));
+  write_to := (fun v s => ({[ s with TLBEntryHi := v ]}));
+  of_regval := (fun v => TLBEntryHiReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryHiReg v) |}.
+
+Definition TLBWired_ref := {|
+  name := "TLBWired";
+  read_from := (fun s => s.(TLBWired));
+  write_to := (fun v s => ({[ s with TLBWired := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBPageMask_ref := {|
+  name := "TLBPageMask";
+  read_from := (fun s => s.(TLBPageMask));
+  write_to := (fun v s => ({[ s with TLBPageMask := v ]}));
+  of_regval := (fun v => vector_16_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_16_dec_bit v) |}.
+
+Definition TLBContext_ref := {|
+  name := "TLBContext";
+  read_from := (fun s => s.(TLBContext));
+  write_to := (fun v s => ({[ s with TLBContext := v ]}));
+  of_regval := (fun v => ContextReg_of_regval v);
+  regval_of := (fun v => regval_of_ContextReg v) |}.
+
+Definition TLBEntryLo1_ref := {|
+  name := "TLBEntryLo1";
+  read_from := (fun s => s.(TLBEntryLo1));
+  write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]}));
+  of_regval := (fun v => TLBEntryLoReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryLoReg v) |}.
+
+Definition TLBEntryLo0_ref := {|
+  name := "TLBEntryLo0";
+  read_from := (fun s => s.(TLBEntryLo0));
+  write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]}));
+  of_regval := (fun v => TLBEntryLoReg_of_regval v);
+  regval_of := (fun v => regval_of_TLBEntryLoReg v) |}.
+
+Definition TLBRandom_ref := {|
+  name := "TLBRandom";
+  read_from := (fun s => s.(TLBRandom));
+  write_to := (fun v s => ({[ s with TLBRandom := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBIndex_ref := {|
+  name := "TLBIndex";
+  read_from := (fun s => s.(TLBIndex));
+  write_to := (fun v s => ({[ s with TLBIndex := v ]}));
+  of_regval := (fun v => vector_6_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_6_dec_bit v) |}.
+
+Definition TLBProbe_ref := {|
+  name := "TLBProbe";
+  read_from := (fun s => s.(TLBProbe));
+  write_to := (fun v s => ({[ s with TLBProbe := v ]}));
+  of_regval := (fun v => vector_1_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_1_dec_bit v) |}.
+
+Definition nextPC_ref := {|
+  name := "nextPC";
+  read_from := (fun s => s.(nextPC));
+  write_to := (fun v s => ({[ s with nextPC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Definition PC_ref := {|
+  name := "PC";
+  read_from := (fun s => s.(PC));
+  write_to := (fun v s => ({[ s with PC := v ]}));
+  of_regval := (fun v => vector_64_dec_bit_of_regval v);
+  regval_of := (fun v => regval_of_vector_64_dec_bit v) |}.
+
+Local Open Scope string.
+Definition get_regval (reg_name : string) (s : regstate) : option register_value :=
+  if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else
+  if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else
+  if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else
+  if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else
+  if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else
+  if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else
+  if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else
+  if string_dec reg_name "delayedPC" then Some (delayedPC_ref.(regval_of) (delayedPC_ref.(read_from) s)) else
+  if string_dec reg_name "inBranchDelay" then Some (inBranchDelay_ref.(regval_of) (inBranchDelay_ref.(read_from) s)) else
+  if string_dec reg_name "branchPending" then Some (branchPending_ref.(regval_of) (branchPending_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else
+  if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else
+  if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else
+  if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else
+  if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else
+  if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else
+  if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else
+  if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else
+  if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else
+  if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else
+  if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else
+  if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else
+  if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else
+  if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else
+  if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else
+  if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else
+  if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else
+  if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else
+  if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else
+  if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else
+  None.
+
+Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate :=
+  if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else
+  if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else
+  if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else
+  if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else
+  if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else
+  if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else
+  if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else
+  if string_dec reg_name "delayedPC" then option_map (fun v => delayedPC_ref.(write_to) v s) (delayedPC_ref.(of_regval) v) else
+  if string_dec reg_name "inBranchDelay" then option_map (fun v => inBranchDelay_ref.(write_to) v s) (inBranchDelay_ref.(of_regval) v) else
+  if string_dec reg_name "branchPending" then option_map (fun v => branchPending_ref.(write_to) v s) (branchPending_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else
+  if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else
+  if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else
+  if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else
+  if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else
+  if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else
+  if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else
+  if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else
+  if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else
+  if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else
+  if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else
+  if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else
+  if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else
+  if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else
+  if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else
+  if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else
+  if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else
+  if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else
+  if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else
+  if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else
+  None.
+
+Definition register_accessors := (get_regval, set_regval).
+
+
+Definition MR a r := monadR register_value a r exception.
+Definition M a := monad register_value a exception.