diff options
Diffstat (limited to 'snapshots')
45 files changed, 20437 insertions, 18512 deletions
diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md index 2a8208c9..5ce3b5cb 100644 --- a/snapshots/hol4/README.md +++ b/snapshots/hol4/README.md @@ -1,13 +1,12 @@ # Snapshot of HOL4 output for Sail CHERI and RISC-V models These theories are a snapshot of the generated files for the Sail -CHERI and RISC-V models, translated to HOL4 via Lem. These are all -accepted by the current source repository version of HOL4 (from -roughly 7th May 2018), although we have not done any further testing -of them yet. +CHERI and RISC-V models, translated to HOL4 via Lem. -They were generated using the `cheri-mono` branch of Sail, and the -`hol-with-extra-types` branch of Lem, which currently contain some -changes that are not yet ready of the main branches of these projects. +Generated using the following repository versions: +HOL4: (master) bb9eaf3448d2c44c84c5d06849d0dc73db23670c, 17 May 2018 +Lem: (master) 55cb119f5b9e9feae8ed02c1b63ef38360eff3a1, 17 May 2018 +Sail: (sail2) b08f0e8538081d8efbbbd6431e739a0b83307678, 17 May 2018 -11th May 2018. +The theories are accepted by HOL4, but we have not done any +further testing of them yet. diff --git a/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml index 7ef74237..79d5eda7 100644 --- a/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml @@ -35,8 +35,8 @@ val _ = Define ` (*val ensure : bool -> string -> unit*) val _ = Define ` - ((ensure:bool -> string -> unit) test msg= - (if test then + ((ensure:bool -> string -> unit) test msg= + (if test then () else failwith msg))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml index eba5f169..4788ee10 100644 --- a/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from basic_classes.lem.*) open HolKernel Parse boolLib bossLib; -open lem_boolTheory; +open lem_boolTheory ternaryComparisonsTheory; val _ = numLib.prefer_num(); @@ -15,6 +15,7 @@ val _ = new_theory "lem_basic_classes" (*open import Bool*) (*open import {coq} `Coq.Strings.Ascii`*) +(*open import {hol} `ternaryComparisonsTheory`*) (* ========================================================================== *) (* Equality *) @@ -65,26 +66,24 @@ lemma eq_equiv: ((forall x. (x = x)) && (* ========================================================================== *) (* The type-class Ord represents total orders (also called linear orders) *) -val _ = Hol_datatype ` - ordering = LT | EQ | GT`; - +(*type ordering = LT | EQ | GT*) val _ = Define ` - ((orderingIsLess:ordering -> bool) LT= T) + ((orderingIsLess:ordering -> bool) LESS= T) /\ ((orderingIsLess:ordering -> bool) _= F)`; val _ = Define ` - ((orderingIsGreater:ordering -> bool) GT= T) + ((orderingIsGreater:ordering -> bool) GREATER= T) /\ ((orderingIsGreater:ordering -> bool) _= F)`; val _ = Define ` - ((orderingIsEqual:ordering -> bool) EQ= T) + ((orderingIsEqual:ordering -> bool) EQUAL= T) /\ ((orderingIsEqual:ordering -> bool) _= F)`; val _ = Define ` - ((ordering_cases:ordering -> 'a -> 'a -> 'a -> 'a) r lt eq gt= - (if orderingIsLess r then lt else + ((ordering_cases:ordering -> 'a -> 'a -> 'a -> 'a) r lt eq gt= + (if orderingIsLess r then lt else if orderingIsEqual r then eq else gt))`; @@ -116,13 +115,13 @@ val _ = Hol_datatype ` val _ = Define ` - ((genericCompare:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a -> 'a -> ordering) (less: 'a -> 'a -> bool) (equal: 'a -> 'a -> bool) (x : 'a) (y : 'a)= - (if less x y then - LT + ((genericCompare:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a -> 'a -> ordering) (less: 'a -> 'a -> bool) (equal: 'a -> 'a -> bool) (x : 'a) (y : 'a)= + (if less x y then + LESS else if equal x y then - EQ + EQUAL else - GT))`; + GREATER))`; @@ -141,9 +140,9 @@ lemma ord_OK_2: ( (* let's derive a compare function from the Ord type-class *) (*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*) val _ = Define ` - ((ordCompare:'a Ord_class -> 'a -> 'a -> ordering)dict_Basic_classes_Ord_a x y= - (if ( dict_Basic_classes_Ord_a.isLess_method x y) then LT else - if (x = y) then EQ else GT))`; + ((ordCompare:'a Ord_class -> 'a -> 'a -> ordering)dict_Basic_classes_Ord_a x y= + (if ( dict_Basic_classes_Ord_a.isLess_method x y) then LESS else + if (x = y) then EQUAL else GREATER))`; val _ = Hol_datatype ` @@ -194,10 +193,10 @@ val _ = Define ` end*) val _ = Define ` - ((boolCompare:bool -> bool -> ordering) T T= EQ) -/\ ((boolCompare:bool -> bool -> ordering) T F= GT) -/\ ((boolCompare:bool -> bool -> ordering) F T= LT) -/\ ((boolCompare:bool -> bool -> ordering) F F= EQ)`; + ((boolCompare:bool -> bool -> ordering) T T= EQUAL) +/\ ((boolCompare:bool -> bool -> ordering) T F= GREATER) +/\ ((boolCompare:bool -> bool -> ordering) F T= LESS) +/\ ((boolCompare:bool -> bool -> ordering) F F= EQUAL)`; (* strings *) @@ -215,11 +214,11 @@ val _ = Define ` (*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*) val _ = Define ` - ((pairCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) -> 'a#'b -> 'a#'b -> ordering) cmpa cmpb (a1, b1) (a2, b2)= - ((case cmpa a1 a2 of - LT => LT - | GT => GT - | EQ => cmpb b1 b2 + ((pairCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) -> 'a#'b -> 'a#'b -> ordering) cmpa cmpb (a1, b1) (a2, b2)= + ((case cmpa a1 a2 of + LESS => LESS + | GREATER => GREATER + | EQUAL => cmpb b1 b2 )))`; @@ -268,8 +267,8 @@ val _ = Define ` (*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*) val _ = Define ` - ((tripleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) -> 'a#'b#'c -> 'a#'b#'c -> ordering) cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2)= - (pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2))))`; + ((tripleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) -> 'a#'b#'c -> 'a#'b#'c -> ordering) cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2)= + (pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2))))`; val _ = Define ` @@ -323,8 +322,8 @@ val _ = Define ` (*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*) val _ = Define ` - ((quadrupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> ordering) cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2)= - (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2)))))`; + ((quadrupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> ordering) cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2)))))`; val _ = Define ` @@ -380,8 +379,8 @@ val _ = Define ` (*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*) val _ = Define ` - ((quintupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> ordering) cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2)= - (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2))))))`; + ((quintupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> ordering) cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2))))))`; val _ = Define ` @@ -444,8 +443,8 @@ val _ = Define ` ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*) val _ = Define ` - ((sextupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) ->('f -> 'f -> ordering) -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> ordering) cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2)= - (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2)))))))`; + ((sextupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) ->('f -> 'f -> ordering) -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> ordering) cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2)= + (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2)))))))`; val _ = Define ` diff --git a/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml index 15437410..cad53888 100644 --- a/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml @@ -27,8 +27,8 @@ val _ = new_theory "lem_either" (*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*) val _ = Define ` - ((eitherEqualBy:('a -> 'a -> bool) ->('b -> 'b -> bool) ->('a,'b)sum ->('a,'b)sum -> bool) eql eqr (left: ('a, 'b) sum) (right: ('a, 'b) sum)= - ((case (left, right) of + ((eitherEqualBy:('a -> 'a -> bool) ->('b -> 'b -> bool) ->('a,'b)sum ->('a,'b)sum -> bool) eql eqr (left: ('a, 'b) sum) (right: ('a, 'b) sum)= + ((case (left, right) of (INL l, INL l') => eql l l' | (INR r, INR r') => eqr r r' | _ => F @@ -37,10 +37,10 @@ val _ = Define ` (*let eitherEqual= eitherEqualBy (=) (=)*) val _ = Define ` - ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL x') (INL y')= (cmpa x' y')) -/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR x') (INR y')= (cmpb x' y')) -/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL _) (INR _)= LT) -/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR _) (INL _)= GT)`; + ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INL x') (INL y')= (cmpa x' y')) +/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INR x') (INR y')= (cmpb x' y')) +/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INL _) (INR _)= LESS) +/\ ((either_setElemCompare:('d -> 'b -> ordering) ->('c -> 'a -> ordering) ->('d,'c)sum ->('b,'a)sum -> ordering) cmpa cmpb (INR _) (INL _)= GREATER)`; diff --git a/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml index 6543ef87..c77c977c 100644 --- a/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml @@ -19,7 +19,7 @@ val _ = new_theory "lem_function_extra" (* getting a unique value *) (* ----------------------- *) -(*val THE : forall 'a. ('a -> bool) -> Maybe.maybe 'a*) +(*val THE : forall 'a. ('a -> bool) -> maybe 'a*) val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_listScript.sml b/snapshots/hol4/lem/hol-lib/lem_listScript.sml index f2ba75d6..1b8f25f3 100644 --- a/snapshots/hol4/lem/hol-lib/lem_listScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_listScript.sml @@ -43,8 +43,8 @@ val _ = new_theory "lem_list" (* ----------------------- *) (*val length : forall 'a. list 'a -> nat*) -(*let rec length l= - match l with +(*let rec length l= + match l with | [] -> 0 | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1 end*) @@ -68,18 +68,18 @@ val _ = new_theory "lem_list" (* compare *) (* ----------------------- *) -(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> Basic_classes.ordering*) -(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a -> Basic_classes.ordering*) +(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> ordering*) +(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a -> ordering*) val _ = Define ` - ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) ([])= EQ) -/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) (_::_)= LT) -/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (_::_) ([])= GT) -/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (x::xs) (y::ys)= (( + ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp ([]) ([])= EQUAL) +/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp ([]) (_::_)= LESS) +/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp (_::_) ([])= GREATER) +/\ ((lexicographic_compare:('a -> 'a -> ordering) -> 'a list -> 'a list -> ordering) cmp (x::xs) (y::ys)= (( (case cmp x y of - LT => LT - | GT => GT - | EQ => lexicographic_compare cmp xs ys + LESS => LESS + | GREATER => GREATER + | EQUAL => lexicographic_compare cmp xs ys ) )))`; @@ -104,7 +104,7 @@ val _ = new_theory "lem_list" val _ = Define ` -((instance_Basic_classes_Ord_list_dict:'a lem_basic_classes$Ord_class ->('a list)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<| +((instance_Basic_classes_Ord_list_dict:'a Ord_class ->('a list)Ord_class)dict_Basic_classes_Ord_a= (<| compare_method := (lexicographic_compare dict_Basic_classes_Ord_a.compare_method); @@ -256,7 +256,7 @@ end*) (* get the initial part and the last element of the list in a safe way *) -(*val dest_init : forall 'a. list 'a -> Maybe.maybe (list 'a * 'a)*) +(*val dest_init : forall 'a. list 'a -> maybe (list 'a * 'a)*) val _ = Define ` ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen ([])= (REVERSE rev_init, last_elem_seen)) @@ -277,7 +277,7 @@ val _ = Define ` (* index / nth with maybe *) (* ------------------------- *) -(*val index : forall 'a. list 'a -> nat -> Maybe.maybe 'a*) +(*val index : forall 'a. list 'a -> nat -> maybe 'a*) val _ = Define ` ((list_index:'a list -> num -> 'a option) ([]) n= NONE) @@ -307,7 +307,7 @@ val _ = Define ` (* ------------------------- *) (* findIndex returns the first index of a list that satisfies a given predicate. *) -(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe nat*) +(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> maybe nat*) val _ = Define ` ((find_index:('a -> bool) -> 'a list ->(num)option) P l= ((case find_indices P l of [] => NONE @@ -325,7 +325,7 @@ val _ = Define ` (* elemIndex *) (* ------------------------- *) -(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> Maybe.maybe nat*) +(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> maybe nat*) (* ========================================================================== *) @@ -340,8 +340,8 @@ val _ = Define ` (*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*) -(*let rec genlist f n= - match n with +(*let rec genlist f n= + match n with | 0 -> [] | n' + 1 -> snoc (f n') (genlist f n') end*) @@ -352,8 +352,8 @@ val _ = Define ` (* ------------------------- *) (*val replicate : forall 'a. nat -> 'a -> list 'a*) -(*let rec replicate n x= - match n with +(*let rec replicate n x= + match n with | 0 -> [] | n' + 1 -> x :: replicate n' x end*) @@ -372,8 +372,8 @@ val _ = Define ` in [xs], the original list and the empty one are returned. *) (*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*) val splitAtAcc_defn = Hol_defn "splitAtAcc" ` - ((splitAtAcc:'a list -> num -> 'a list -> 'a list#'a list) revAcc n l= - ((case l of + ((splitAtAcc:'a list -> num -> 'a list -> 'a list#'a list) revAcc n l= + ((case l of [] => (REVERSE revAcc, []) | x::xs => if n <=( 0 : num) then (REVERSE revAcc, l) else splitAtAcc (x::revAcc) (n -( 1 : num)) xs )))`; @@ -381,8 +381,8 @@ val _ = Define ` val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn splitAtAcc_defn; (*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*) -(*let rec splitAt n l= - splitAtAcc [] n l*) +(*let rec splitAt n l= + splitAtAcc [] n l*) (* ------------------------- *) @@ -407,10 +407,10 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn (*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*) val _ = Define ` - ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p ([]) acc= - (REVERSE acc, [])) -/\ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p (x::xs) acc= - (if p x then + ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p ([]) acc= + (REVERSE acc, [])) +/\ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p (x::xs) acc= + (if p x then splitWhile_tr p xs (x::acc) else (REVERSE acc, (x::xs))))`; @@ -448,8 +448,8 @@ end*) (* update *) (* ------------------------- *) (*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*) -(*let rec update l n e= - match l with +(*let rec update l n e= + match l with | [] -> [] | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e) end*) @@ -492,7 +492,7 @@ val _ = Define ` (* ------------------------- *) (* Find *) (* ------------------------- *) -(*val find : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe 'a*) (* previously not of maybe type *) +(*val find : forall 'a. ('a -> bool) -> list 'a -> maybe 'a*) (* previously not of maybe type *) val _ = Define ` ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P ([])= NONE) /\ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P (x :: xs)= (if P x then SOME x else list_find_opt P xs))`; @@ -502,8 +502,8 @@ val _ = Define ` (* ----------------------------- *) (* Lookup in an associative list *) (* ----------------------------- *) -(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> Maybe.maybe 'b*) -(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> Maybe.maybe 'b*) +(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> maybe 'b*) +(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> maybe 'b*) (* DPM: eta-expansion for Coq backend type-inference. *) val _ = Define ` @@ -536,7 +536,7 @@ val _ = Define ` (* with certain property *) (* ------------------------- *) -(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe (list 'a)*) +(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> maybe (list 'a)*) val _ = Define ` ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P ([])= NONE) /\ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P (x :: xs)= (if (P x) then SOME xs else OPTION_MAP (\ xs' . x :: xs') (list_delete_first P xs)))`; @@ -583,18 +583,18 @@ end*) (* ------------------------- *) (*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*) -(*let rec allDistinct l= - match l with +(*let rec allDistinct l= + match l with | [] -> true | (x::l') -> not (elem x l') && allDistinct l' end*) (* some more useful functions *) -(*val mapMaybe : forall 'a 'b. ('a -> Maybe.maybe 'b) -> list 'a -> list 'b*) +(*val mapMaybe : forall 'a 'b. ('a -> maybe 'b) -> list 'a -> list 'b*) val mapMaybe_defn = Defn.Hol_multi_defns ` ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f ([])= ([])) -/\ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f (x::xs)= - ((case f x of +/\ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f (x::xs)= + ((case f x of NONE => mapMaybe f xs | SOME y => y :: (mapMaybe f xs) )))`; @@ -613,8 +613,8 @@ val _ = Define ` (*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*) val _ = Define ` - ((deletes:'a list -> 'a list -> 'a list) xs ys= - (FOLDL (combin$C (list_delete (=))) xs ys))`; + ((deletes:'a list -> 'a list -> 'a list) xs ys= + (FOLDL (combin$C (list_delete (=))) xs ys))`; (* ========================================================================== *) @@ -762,14 +762,14 @@ val intersect : forall 'a. list 'a -> list 'a -> list 'a *) -(*val catMaybes : forall 'a. list (Maybe.maybe 'a) -> list 'a*) +(*val catMaybes : forall 'a. list (maybe 'a) -> list 'a*) val catMaybes_defn = Defn.Hol_multi_defns ` - ((catMaybes:('a option)list -> 'a list) ([])= - ([])) -/\ ((catMaybes:('a option)list -> 'a list) (NONE :: xs')= - (catMaybes xs')) -/\ ((catMaybes:('a option)list -> 'a list) (SOME x :: xs')= - (x :: catMaybes xs'))`; + ((catMaybes:('a option)list -> 'a list) ([])= + ([])) +/\ ((catMaybes:('a option)list -> 'a list) (NONE :: xs')= + (catMaybes xs')) +/\ ((catMaybes:('a option)list -> 'a list) (SOME x :: xs')= + (x :: catMaybes xs'))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) catMaybes_defn; val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml index b8e452d3..123d8a78 100644 --- a/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml @@ -94,10 +94,10 @@ val _ = Define ` end*) -(*val unfoldr: forall 'a 'b. ('a -> Maybe.maybe ('b * 'a)) -> 'a -> list 'b*) +(*val unfoldr: forall 'a 'b. ('a -> maybe ('b * 'a)) -> 'a -> list 'b*) val unfoldr_defn = Hol_defn "unfoldr" ` - ((unfoldr:('a ->('b#'a)option) -> 'a -> 'b list) f x= - ((case f x of + ((unfoldr:('a ->('b#'a)option) -> 'a -> 'b list) f x= + ((case f x of SOME (y, x') => y :: unfoldr f x' | NONE => diff --git a/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml index c169e9a8..294bf8ca 100644 --- a/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml @@ -23,7 +23,7 @@ end*) (*val native_size : forall 'a. nat*) -(*val ocaml_inject : forall 'a. nat * Num.natural -> mword 'a*) +(*val ocaml_inject : forall 'a. nat * natural -> mword 'a*) (* A singleton type family that can be used to carry a size as the type parameter *) @@ -313,25 +313,25 @@ val _ = Define ` (* Conversions *) (******************************************************************) -(*val signedIntegerFromWord : forall 'a. mword 'a -> Num.integer*) +(*val signedIntegerFromWord : forall 'a. mword 'a -> integer*) -(*val unsignedIntegerFromWord : forall 'a. mword 'a -> Num.integer*) +(*val unsignedIntegerFromWord : forall 'a. mword 'a -> integer*) (* Version without typeclass constraint so that we can derive operations in Lem for one of the theorem provers without requiring it. *) -(*val proverWordFromInteger : forall 'a. Num.integer -> mword 'a*) +(*val proverWordFromInteger : forall 'a. integer -> mword 'a*) -(*val wordFromInteger : forall 'a. Size 'a => Num.integer -> mword 'a*) +(*val wordFromInteger : forall 'a. Size 'a => integer -> mword 'a*) (* The OCaml version is defined after the arithmetic operations, below. *) -(*val naturalFromWord : forall 'a. mword 'a -> Num.natural*) +(*val naturalFromWord : forall 'a. mword 'a -> natural*) -(*val wordFromNatural : forall 'a. Size 'a => Num.natural -> mword 'a*) +(*val wordFromNatural : forall 'a. Size 'a => natural -> mword 'a*) (*val wordToHex : forall 'a. mword 'a -> string*) val _ = Define ` -((instance_Show_Show_Machine_word_mword_dict:('a words$word)lem_show$Show_class)= (<| +((instance_Show_Show_Machine_word_mword_dict:('a words$word)Show_class)= (<| show_method := words$word_to_hex_string|>))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_mapScript.sml b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml index a85a9d67..e05af7f2 100644 --- a/snapshots/hol4/lem/hol-lib/lem_mapScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml @@ -30,7 +30,7 @@ val _ = new_theory "lem_map" (* -------------------------------------------------------------------------- *) (*class ( MapKeyType 'a ) - val {ocaml;coq} mapKeyCompare : 'a -> 'a -> Basic_classes.ordering + val {ocaml;coq} mapKeyCompare : 'a -> 'a -> ordering end*) (* -------------------------------------------------------------------------- *) @@ -38,7 +38,7 @@ end*) (* -------------------------------------------------------------------------- *) (*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*) -(*val emptyBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v*) +(*val emptyBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v*) (* -------------------------------------------------------------------------- *) @@ -67,9 +67,9 @@ end*) (* lookup *) (* -------------------------------------------------------------------------- *) -(*val lookupBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> Maybe.maybe 'v*) +(*val lookupBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> maybe 'v*) -(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> Maybe.maybe 'v*) +(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> maybe 'v*) (* -------------------------------------------------------------------------- *) (* findWithDefault *) @@ -90,15 +90,15 @@ end*) (* -------------------------------------------------------------------------- *) (*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*) -(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> Basic_classes.ordering) -> map 'k 'v -> set ('k * 'v)*) +(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> ordering) -> map 'k 'v -> set ('k * 'v)*) -(*val domainBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v -> set 'k*) +(*val domainBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v -> set 'k*) (*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*) (*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*) -(*val rangeBy : forall 'k 'v. ('v -> 'v -> Basic_classes.ordering) -> map 'k 'v -> set 'v*) +(*val rangeBy : forall 'k 'v. ('v -> 'v -> ordering) -> map 'k 'v -> set 'v*) (* -------------------------------------------------------------------------- *) @@ -122,7 +122,7 @@ end*) (* -------------------------------------------------------------------------- *) (* Set-like operations. *) (* -------------------------------------------------------------------------- *) -(*val deleteBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> map 'k 'v*) +(*val deleteBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> map 'k 'v*) (*val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*) (*val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*) @@ -146,8 +146,8 @@ end*) (* instance of SetType *) val _ = Define ` - ((map_setElemCompare:(('d#'c)set ->('b#'a)set -> 'e) ->('d,'c)fmap ->('b,'a)fmap -> 'e) cmp x y= - (cmp (FMAP_TO_SET x) (FMAP_TO_SET y)))`; + ((map_setElemCompare:(('d#'c)set ->('b#'a)set -> 'e) ->('d,'c)fmap ->('b,'a)fmap -> 'e) cmp x y= + (cmp (FMAP_TO_SET x) (FMAP_TO_SET y)))`; val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml index 57a258f8..7e32efb7 100644 --- a/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml @@ -16,7 +16,7 @@ val _ = new_theory "lem_map_extra" (* find *) (* -------------------------------------------------------------------------- *) -(*val find : forall 'k 'v. MapKeyType 'k => 'k -> Map.map 'k 'v -> 'v*) +(*val find : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> 'v*) (*let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith "Map_extra.find" end*) @@ -26,7 +26,7 @@ val _ = new_theory "lem_map_extra" (* -------------------------------------------------------------------------- *) -(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> Map.map 'k 'v*) +(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> map 'k 'v*) (*let fromSet f s= Set_helpers.fold (fun k m -> Map.insert k (f k) m) s Map.empty*) (* @@ -38,7 +38,7 @@ assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (* fold *) (* -------------------------------------------------------------------------- *) -(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> Map.map 'k 'v -> 'r -> 'r*) +(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> map 'k 'v -> 'r -> 'r*) val _ = Define ` ((fold:('k -> 'v -> 'r -> 'r) ->('k,'v)fmap -> 'r -> 'r) f m v= (ITSET (\ (k, v) r . f k v r) (FMAP_TO_SET m) v))`; @@ -48,17 +48,17 @@ assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12) *) -(*val toList: forall 'k 'v. MapKeyType 'k => Map.map 'k 'v -> list ('k * 'v)*) +(*val toList: forall 'k 'v. MapKeyType 'k => map 'k 'v -> list ('k * 'v)*) (* declare compile_message toList = "Map_extra.toList is only defined for the ocaml, isabelle and coq backend" *) (* more 'map' functions *) (* TODO: this function is in map_extra rather than map just for implementation reasons *) -(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> Maybe.maybe 'c) -> Map.map 'a 'b -> Map.map 'a 'c*) +(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> maybe 'c) -> map 'a 'b -> map 'a 'c*) (* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *) val _ = Define ` - ((option_map:('a -> 'b -> 'c option) ->('a,'b)fmap ->('a,'c)fmap) f m= - (FOLDL + ((option_map:('a -> 'b -> 'c option) ->('a,'b)fmap ->('a,'c)fmap) f m= + (FOLDL (\ m' (k, v) . (case f k v of NONE => m' diff --git a/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml index 29562d66..bcf4348b 100644 --- a/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml @@ -33,29 +33,29 @@ val _ = Define ` val _ = Define ` - ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE NONE= EQ) -/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE (SOME _)= LT) -/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME _) NONE= GT) -/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME x') (SOME y')= (cmp x' y'))`; + ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp NONE NONE= EQUAL) +/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp NONE (SOME _)= LESS) +/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp (SOME _) NONE= GREATER) +/\ ((maybeCompare:('b -> 'a -> ordering) -> 'b option -> 'a option -> ordering) cmp (SOME x') (SOME y')= (cmp x' y'))`; val _ = Define ` -((instance_Basic_classes_Ord_Maybe_maybe_dict:'a lem_basic_classes$Ord_class ->('a option)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<| +((instance_Basic_classes_Ord_Maybe_maybe_dict:'a Ord_class ->('a option)Ord_class)dict_Basic_classes_Ord_a= (<| compare_method := (maybeCompare dict_Basic_classes_Ord_a.compare_method); isLess_method := (\ m1 . (\ m2 . maybeCompare - dict_Basic_classes_Ord_a.compare_method m1 m2 = LT)); + dict_Basic_classes_Ord_a.compare_method m1 m2 = LESS)); isLessEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare - dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = LT) \/ (r = EQ)))); + dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = LESS) \/ (r = EQUAL)))); isGreater_method := (\ m1 . (\ m2 . maybeCompare - dict_Basic_classes_Ord_a.compare_method m1 m2 = GT)); + dict_Basic_classes_Ord_a.compare_method m1 m2 = GREATER)); isGreaterEqual_method := (\ m1 . (\ m2 . (let r = (maybeCompare - dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = GT) \/ (r = EQ))))|>))`; + dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = GREATER) \/ (r = EQUAL))))|>))`; (* ----------------------- *) diff --git a/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml index 6b04d291..22d7e061 100644 --- a/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml @@ -16,7 +16,7 @@ val _ = new_theory "lem_maybe_extra" (* fromJust *) (* ----------------------- *) -(*val fromJust : forall 'a. Maybe.maybe 'a -> 'a*) +(*val fromJust : forall 'a. maybe 'a -> 'a*) (*let fromJust op= match op with | Just v -> v | Nothing -> failwith "fromJust of Nothing" end*) val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_numScript.sml b/snapshots/hol4/lem/hol-lib/lem_numScript.sml index 9dcd0554..6064416b 100644 --- a/snapshots/hol4/lem/hol-lib/lem_numScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_numScript.sml @@ -179,10 +179,10 @@ val _ = Hol_datatype ` (*val natGreater : nat -> nat -> bool*) (*val natGreaterEqual : nat -> nat -> bool*) -(*val natCompare : nat -> nat -> Basic_classes.ordering*) +(*val natCompare : nat -> nat -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_nat_dict:(num)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_nat_dict:(num)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -259,8 +259,8 @@ val _ = Define ` (*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*) val _ = Define ` - ((gen_pow_aux:('a -> 'a -> 'a) -> 'a -> 'a -> num -> 'a) (mul : 'a -> 'a -> 'a) (a : 'a) (b : 'a) (e : num)= - ((case e of + ((gen_pow_aux:('a -> 'a -> 'a) -> 'a -> 'a -> num -> 'a) (mul : 'a -> 'a -> 'a) (a : 'a) (b : 'a) (e : num)= + ((case e of 0 => a (* cannot happen, call discipline guarentees e >= 1 *) | (SUC 0) => mul a b | ( (SUC(SUC e'))) => let e'' = (e DIV( 2 : num)) in @@ -270,8 +270,8 @@ val _ = Define ` val _ = Define ` - ((gen_pow:'a ->('a -> 'a -> 'a) -> 'a -> num -> 'a) (one1 : 'a) (mul : 'a -> 'a -> 'a) (b : 'a) (e : num) : 'a= - (if e <( 0 : num) then one1 else + ((gen_pow:'a ->('a -> 'a -> 'a) -> 'a -> num -> 'a) (one1 : 'a) (mul : 'a -> 'a -> 'a) (b : 'a) (e : num) : 'a= + (if e <( 0 : num) then one1 else if (e =( 0 : num)) then one1 else gen_pow_aux mul one1 b e))`; @@ -288,7 +288,7 @@ val _ = Define ` (*val natMax : nat -> nat -> nat*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_nat_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_nat_dict:(num)OrdMaxMin_class)= (<| max_method := MAX; @@ -309,10 +309,10 @@ val _ = Define ` (*val naturalGreater : natural -> natural -> bool*) (*val naturalGreaterEqual : natural -> natural -> bool*) -(*val naturalCompare : natural -> natural -> Basic_classes.ordering*) +(*val naturalCompare : natural -> natural -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_natural_dict:(num)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_natural_dict:(num)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -400,7 +400,7 @@ val _ = Define ` (*val naturalMax : natural -> natural -> natural*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_natural_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_natural_dict:(num)OrdMaxMin_class)= (<| max_method := MAX; @@ -421,10 +421,10 @@ val _ = Define ` (*val intGreater : int -> int -> bool*) (*val intGreaterEqual : int -> int -> bool*) -(*val intCompare : int -> int -> Basic_classes.ordering*) +(*val intCompare : int -> int -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_int_dict:(int)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_int_dict:(int)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -527,7 +527,7 @@ val _ = Define ` (*val intMax : int -> int -> int*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_int_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_int_dict:(int)OrdMaxMin_class)= (<| max_method := int_max; @@ -546,10 +546,10 @@ val _ = Define ` (*val int32Greater : int32 -> int32 -> bool*) (*val int32GreaterEqual : int32 -> int32 -> bool*) -(*val int32Compare : int32 -> int32 -> Basic_classes.ordering*) +(*val int32Compare : int32 -> int32 -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_int32_dict:(word32)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_int32_dict:(word32)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -660,7 +660,7 @@ val _ = Define ` (*val int32Max : int32 -> int32 -> int32*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_int32_dict:(word32)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_int32_dict:(word32)OrdMaxMin_class)= (<| max_method := word_smax; @@ -681,10 +681,10 @@ val _ = Define ` (*val int64Greater : int64 -> int64 -> bool*) (*val int64GreaterEqual : int64 -> int64 -> bool*) -(*val int64Compare : int64 -> int64 -> Basic_classes.ordering*) +(*val int64Compare : int64 -> int64 -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_int64_dict:(word64)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_int64_dict:(word64)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -795,7 +795,7 @@ val _ = Define ` (*val int64Max : int64 -> int64 -> int64*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_int64_dict:(word64)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_int64_dict:(word64)OrdMaxMin_class)= (<| max_method := word_smax; @@ -818,10 +818,10 @@ val _ = Define ` (*val integerGreater : integer -> integer -> bool*) (*val integerGreaterEqual : integer -> integer -> bool*) -(*val integerCompare : integer -> integer -> Basic_classes.ordering*) +(*val integerCompare : integer -> integer -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_integer_dict:(int)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_integer_dict:(int)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -924,7 +924,7 @@ val _ = Define ` (*val integerMax : integer -> integer -> integer*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_integer_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_integer_dict:(int)OrdMaxMin_class)= (<| max_method := int_max; @@ -948,10 +948,10 @@ val _ = Define ` (*val rationalGreater : rational -> rational -> bool*) (*val rationalGreaterEqual : rational -> rational -> bool*) -(*val rationalCompare : rational -> rational -> Basic_classes.ordering*) +(*val rationalCompare : rational -> rational -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_rational_dict:(rat)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_rational_dict:(rat)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -1031,8 +1031,8 @@ val _ = Define ` (*val rationalPowInteger : rational -> integer -> rational*) val rationalPowInteger_defn = Hol_defn "rationalPowInteger" ` - ((rationalPowInteger:rat -> int -> rat) b e= - (if e =( 0 : int) then( 1 : rat) else + ((rationalPowInteger:rat -> int -> rat) b e= + (if e =( 0 : int) then( 1 : rat) else if e >( 0 : int) then rationalPowInteger b (e -( 1 : int)) * b else rationalPowInteger b (e +( 1 : int)) / b))`; @@ -1054,7 +1054,7 @@ val _ = Define ` (*val rationalMax : rational -> rational -> rational*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_rational_dict:(rat)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_rational_dict:(rat)OrdMaxMin_class)= (<| max_method := (maxByLessEqual (<=)); @@ -1078,10 +1078,10 @@ val _ = Define ` (*val realGreater : real -> real -> bool*) (*val realGreaterEqual : real -> real -> bool*) -(*val realCompare : real -> real -> Basic_classes.ordering*) +(*val realCompare : real -> real -> ordering*) val _ = Define ` -((instance_Basic_classes_Ord_Num_real_dict:(real)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Num_real_dict:(real)Ord_class)= (<| compare_method := (genericCompare (<) (=)); @@ -1163,8 +1163,8 @@ val _ = Define ` (*val realPowInteger : real -> integer -> real*) val realPowInteger_defn = Hol_defn "realPowInteger" ` - ((realPowInteger:real -> int -> real) b e= - (if e =( 0 : int) then(real_of_num 1) else + ((realPowInteger:real -> int -> real) b e= + (if e =( 0 : int) then(real_of_num 1) else if e >( 0 : int) then realPowInteger b (e -( 1 : int)) * b else realPowInteger b (e +( 1 : int)) / b))`; @@ -1186,7 +1186,7 @@ val _ = Define ` (*val realMax : real -> real -> real*) val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Num_real_dict:(real)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Num_real_dict:(real)OrdMaxMin_class)= (<| max_method := max; diff --git a/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml index 69644f94..40356448 100644 --- a/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml @@ -17,18 +17,18 @@ val _ = new_theory "lem_num_extra" (*open import Num*) (*open import String*) -(*val naturalOfString : string -> Num.natural*) +(*val naturalOfString : string -> natural*) -(*val integerOfString : string -> Num.integer*) +(*val integerOfString : string -> integer*) (* Truncation integer division (round toward zero) *) -(*val integerDiv_t: Num.integer -> Num.integer -> Num.integer*) +(*val integerDiv_t: integer -> integer -> integer*) (* Truncation modulo *) -(*val integerRem_t: Num.integer -> Num.integer -> Num.integer*) +(*val integerRem_t: integer -> integer -> integer*) (* Flooring modulo *) -(*val integerRem_f: Num.integer -> Num.integer -> Num.integer*) +(*val integerRem_f: integer -> integer -> integer*) val _ = export_theory() diff --git a/snapshots/hol4/lem/hol-lib/lem_relationScript.sml b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml index e73b66ce..7d019b21 100644 --- a/snapshots/hol4/lem/hol-lib/lem_relationScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml @@ -393,7 +393,7 @@ val _ = Define ` (*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) (*val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*) -(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> Basic_classes.ordering) -> rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> ordering) -> rel 'a 'a -> rel 'a 'a*) (* ----------------------- *) @@ -403,8 +403,8 @@ val _ = Define ` (*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*) val _ = Define ` - ((tc_insert:'a -> 'a ->('a#'a)set ->('a#'a)set) x y r= - ((((((x,y) INSERT (r)))) UNION ((((({(x, z) | z | + ((tc_insert:'a -> 'a ->('a#'a)set ->('a#'a)set) x y r= + ((((((x,y) INSERT (r)))) UNION ((((({(x, z) | z | (z IN range r) /\ ((y, z) IN r)})) UNION (({(z, y) | z | (z IN domain r) /\ ((z, x) IN r)}))))))))`; @@ -437,8 +437,8 @@ val _ = Define ` (*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) val _ = Define ` - ((withoutTransitiveEdges:('a#'a)set ->('a#'a)set) r= - (let tc1 = (tc r) in + ((withoutTransitiveEdges:('a#'a)set ->('a#'a)set) r= + (let tc1 = (tc r) in {(a, c) | a, c | ((a, c) IN r) /\ (! (b :: range r). diff --git a/snapshots/hol4/lem/hol-lib/lem_setScript.sml b/snapshots/hol4/lem/hol-lib/lem_setScript.sml index 7f553a68..c03aec5f 100644 --- a/snapshots/hol4/lem/hol-lib/lem_setScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_setScript.sml @@ -49,7 +49,7 @@ val _ = new_theory "lem_set" (* Equality check *) (* ----------------------- *) -(*val setEqualBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) +(*val setEqualBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) (*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) @@ -58,7 +58,7 @@ val _ = new_theory "lem_set" (* ----------------------- *) (*val empty : forall 'a. SetType 'a => set 'a*) -(*val emptyBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a*) +(*val emptyBy : forall 'a. ('a -> 'a -> ordering) -> set 'a*) (* ----------------------- *) (* any / all *) @@ -74,7 +74,7 @@ val _ = new_theory "lem_set" (* ----------------------- *) (*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) -(*val memberBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a -> bool*) +(*val memberBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a -> bool*) (* ----------------------- *) (* not (IN) *) @@ -95,7 +95,7 @@ val _ = new_theory "lem_set" (* singleton *) (* ------------------------ *) -(*val singletonBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a*) +(*val singletonBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a*) (*val singleton : forall 'a. SetType 'a => 'a -> set 'a*) @@ -117,7 +117,7 @@ val _ = new_theory "lem_set" (* union *) (* ------------------------ *) -(*val unionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) +(*val unionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) (*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) (* ----------------------- *) @@ -150,13 +150,13 @@ val _ = Define ` (*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*) val _ = Define ` - ((SET_SPLIT:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( + ((SET_SPLIT:'a Ord_class -> 'a -> 'a set -> 'a set#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( dict_Basic_classes_Ord_a.isGreater_method p) s, SET_FILTER (dict_Basic_classes_Ord_a.isLess_method p) s))`; (*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*) val _ = Define ` - ((splitMember:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#bool#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( + ((splitMember:'a Ord_class -> 'a -> 'a set -> 'a set#bool#'a set)dict_Basic_classes_Ord_a p s= (SET_FILTER ( dict_Basic_classes_Ord_a.isLess_method p) s, (p IN s), SET_FILTER ( dict_Basic_classes_Ord_a.isGreater_method p) s))`; @@ -165,8 +165,8 @@ val _ = Define ` (* subset and proper subset *) (* ------------------------ *) -(*val isSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) -(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*) +(*val isSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) +(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) (*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) (*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) @@ -185,7 +185,7 @@ val _ = Define ` (* ------------------------ *) (*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*) -(*val bigunionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set (set 'a) -> set 'a*) +(*val bigunionBy : forall 'a. ('a -> 'a -> ordering) -> set (set 'a) -> set 'a*) (*let bigunion bs= {x | forall (s IN bs) (x IN s) | true}*) @@ -206,7 +206,7 @@ val _ = Define ` (* difference *) (* ------------------------ *) -(*val differenceBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) +(*val differenceBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) (*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) (* ------------------------ *) @@ -214,7 +214,7 @@ val _ = Define ` (* ------------------------ *) (*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) -(*val intersectionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*) +(*val intersectionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) (* ------------------------ *) @@ -224,7 +224,7 @@ val _ = Define ` (*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *) (*let map f s= { f e | forall (e IN s) | true }*) -(*val mapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> 'b) -> set 'a -> set 'b*) +(*val mapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> 'b) -> set 'a -> set 'b*) (* ------------------------ *) @@ -235,7 +235,7 @@ val _ = Define ` it might be better to combine bigunion and map sometimes into a single operation. *) (*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*) -(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> set 'b) -> set 'a -> set 'b*) +(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> set 'b) -> set 'a -> set 'b*) (* ------------------------ *) (* mapMaybe and fromMaybe *) @@ -244,16 +244,16 @@ val _ = Define ` (* If the mapping function returns Just x, x is added to the result set. If it returns Nothing, no element is added. *) -(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> Maybe.maybe 'b) -> set 'a -> set 'b*) +(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> maybe 'b) -> set 'a -> set 'b*) val _ = Define ` - ((setMapMaybe:('a -> 'b option) -> 'a set -> 'b set) f s= - (BIGUNION (IMAGE (\ x . (case f x of + ((setMapMaybe:('a -> 'b option) -> 'a set -> 'b set) f s= + (BIGUNION (IMAGE (\ x . (case f x of SOME y => {y} | NONE => EMPTY )) s)))`; -(*val removeMaybe : forall 'a. SetType 'a => set (Maybe.maybe 'a) -> set 'a*) +(*val removeMaybe : forall 'a. SetType 'a => set (maybe 'a) -> set 'a*) val _ = Define ` ((removeMaybe:('a option)set -> 'a set) s= (setMapMaybe (\ x . x) s))`; @@ -262,15 +262,15 @@ val _ = Define ` (* min and max *) (* ------------------------ *) -(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*) -(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*) +(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) +(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) (* ------------------------ *) (* fromList *) (* ------------------------ *) (*val fromList : forall 'a. SetType 'a => list 'a -> set 'a*) (* before from_list *) -(*val fromListBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> set 'a*) +(*val fromListBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> set 'a*) (* ------------------------ *) @@ -278,7 +278,7 @@ val _ = Define ` (* ------------------------ *) (*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*) -(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*) +(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*) (*let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }*) @@ -288,7 +288,7 @@ val _ = Define ` (* ------------------------ *) (*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*) -(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> set 'b -> set ('a * 'b)*) +(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> set 'b -> set ('a * 'b)*) (*let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*) diff --git a/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml index 5409a408..1e51c142 100644 --- a/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml @@ -44,10 +44,10 @@ val _ = new_theory "lem_set_extra" * search criterion, and we avoid baking in the tree representation (although that * is the obvious choice). *) -(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> Maybe.maybe (set 'a * 'a * set 'a)*) +(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> maybe (set 'a * 'a * set 'a)*) val _ = Define ` - ((chooseAndSplit:'a lem_basic_classes$Ord_class -> 'a set ->('a set#'a#'a set)option)dict_Basic_classes_Ord_a s= - (if s = EMPTY then + ((chooseAndSplit:'a Ord_class -> 'a set ->('a set#'a#'a set)option)dict_Basic_classes_Ord_a s= + (if s = EMPTY then NONE else let element1 = (CHOICE s) in @@ -87,17 +87,17 @@ val _ = Define ` (* compare *) (* ----------------------- *) -(*val setCompareBy: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> Basic_classes.ordering*) +(*val setCompareBy: forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> ordering*) val _ = Define ` - ((setCompareBy:('a -> 'a -> lem_basic_classes$ordering) -> 'a set -> 'a set -> lem_basic_classes$ordering) cmp ss ts= - (let ss' = (ARB (\ x y . cmp x y = LT) ss) in - let ts' = (ARB (\ x y . cmp x y = LT) ts) in + ((setCompareBy:('a -> 'a -> ordering) -> 'a set -> 'a set -> ordering) cmp ss ts= + (let ss' = (ARB (\ x y . cmp x y = LESS) ss) in + let ts' = (ARB (\ x y . cmp x y = LESS) ts) in lexicographic_compare cmp ss' ts'))`; -(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> Basic_classes.ordering*) +(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> ordering*) val _ = Define ` - ((setCompare:'a lem_basic_classes$Ord_class -> 'a set -> 'a set -> lem_basic_classes$ordering)dict_Basic_classes_Ord_a= (setCompareBy + ((setCompare:'a Ord_class -> 'a set -> 'a set -> ordering)dict_Basic_classes_Ord_a= (setCompareBy dict_Basic_classes_Ord_a.compare_method))`; @@ -108,8 +108,8 @@ val _ = Define ` (* Is NOT supported by the coq backend! *) (*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*) val leastFixedPointUnbounded_defn = Hol_defn "leastFixedPointUnbounded" ` - ((leastFixedPointUnbounded:('a set -> 'a set) -> 'a set -> 'a set) f x= - (let fx = (f x) in + ((leastFixedPointUnbounded:('a set -> 'a set) -> 'a set -> 'a set) f x= + (let fx = (f x) in if fx SUBSET x then x else leastFixedPointUnbounded f (fx UNION x)))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_showScript.sml b/snapshots/hol4/lem/hol-lib/lem_showScript.sml index 1852c219..eef2c93e 100644 --- a/snapshots/hol4/lem/hol-lib/lem_showScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_showScript.sml @@ -26,7 +26,7 @@ val _ = Define ` show_method := (\ s. STRCAT"\"" (STRCAT s "\""))|>))`; -(*val stringFromMaybe : forall 'a. ('a -> string) -> Maybe.maybe 'a -> string*) +(*val stringFromMaybe : forall 'a. ('a -> string) -> maybe 'a -> string*) val _ = Define ` ((stringFromMaybe:('a -> string) -> 'a option -> string) showX (SOME x)= (STRCAT"Just (" (STRCAT(showX x) ")"))) /\ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX NONE= "Nothing")`; @@ -42,8 +42,8 @@ val _ = Define ` (*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*) val stringFromListAux_defn = Defn.Hol_multi_defns ` ((stringFromListAux:('a -> string) -> 'a list -> string) showX ([])= "") -/\ ((stringFromListAux:('a -> string) -> 'a list -> string) showX (x::xs')= - ((case xs' of +/\ ((stringFromListAux:('a -> string) -> 'a list -> string) showX (x::xs')= + ((case xs' of [] => showX x | _ => STRCAT(showX x) (STRCAT"; " (stringFromListAux showX xs')) )))`; @@ -52,8 +52,8 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn (*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*) val _ = Define ` - ((stringFromList:('a -> string) -> 'a list -> string) showX xs= - (STRCAT"[" (STRCAT(stringFromListAux showX xs) "]")))`; + ((stringFromList:('a -> string) -> 'a list -> string) showX xs= + (STRCAT"[" (STRCAT(stringFromListAux showX xs) "]")))`; val _ = Define ` @@ -65,8 +65,8 @@ val _ = Define ` (*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*) val _ = Define ` - ((stringFromPair:('a -> string) ->('b -> string) -> 'a#'b -> string) showX showY (x,y)= - (STRCAT"(" (STRCAT(showX x) (STRCAT", " (STRCAT(showY y) ")")))))`; + ((stringFromPair:('a -> string) ->('b -> string) -> 'a#'b -> string) showX showY (x,y)= + (STRCAT"(" (STRCAT(showX x) (STRCAT", " (STRCAT(showY y) ")")))))`; val _ = Define ` diff --git a/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml index d8e50e16..6be94271 100644 --- a/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml @@ -14,51 +14,51 @@ val _ = new_theory "lem_show_extra" (*import Set_extra String_extra*) val _ = Define ` -((instance_Show_Show_nat_dict:(num)lem_show$Show_class)= (<| +((instance_Show_Show_nat_dict:(num)Show_class)= (<| show_method := num_to_dec_string|>))`; val _ = Define ` -((instance_Show_Show_Num_natural_dict:(num)lem_show$Show_class)= (<| +((instance_Show_Show_Num_natural_dict:(num)Show_class)= (<| show_method := num_to_dec_string|>))`; val _ = Define ` -((instance_Show_Show_Num_int_dict:(int)lem_show$Show_class)= (<| +((instance_Show_Show_Num_int_dict:(int)Show_class)= (<| show_method := lem_string_extra$stringFromInt|>))`; val _ = Define ` -((instance_Show_Show_Num_integer_dict:(int)lem_show$Show_class)= (<| +((instance_Show_Show_Num_integer_dict:(int)Show_class)= (<| show_method := lem_string_extra$stringFromInteger|>))`; val _ = Define ` - ((stringFromSet:('a -> string) -> 'a set -> string) showX xs= - (STRCAT"{" (STRCAT(lem_show$stringFromListAux showX (SET_TO_LIST xs)) "}")))`; + ((stringFromSet:('a -> string) -> 'a set -> string) showX xs= + (STRCAT"{" (STRCAT(lem_show$stringFromListAux showX (SET_TO_LIST xs)) "}")))`; (* Abbreviates the representation if the relation is transitive. *) val _ = Define ` - ((stringFromRelation:('a#'a -> string) ->('a#'a)set -> string) showX rel= - (if transitive rel then + ((stringFromRelation:('a#'a -> string) ->('a#'a)set -> string) showX rel= + (if transitive rel then let pruned_rel = (withoutTransitiveEdges rel) in if (! (e :: rel). (e IN pruned_rel)) then (* The relations are the same (there are no transitive edges), so we can just as well print the original one. *) stringFromSet showX rel - else - STRCAT"trancl of " (stringFromSet showX pruned_rel) + else + STRCAT"trancl of " (stringFromSet showX pruned_rel) else stringFromSet showX rel))`; val _ = Define ` -((instance_Show_Show_set_dict:'a lem_show$Show_class ->('a set)lem_show$Show_class)dict_Show_Show_a= (<| +((instance_Show_Show_set_dict:'a Show_class ->('a set)Show_class)dict_Show_Show_a= (<| show_method := (\ xs. stringFromSet dict_Show_Show_a.show_method xs)|>))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml index 30f66e5e..08288d15 100644 --- a/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml @@ -90,15 +90,15 @@ val _ = Define ` (*val sort: forall 'a. Ord 'a => list 'a -> list 'a*) (*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) -(*val sortByOrd: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a*) +(*val sortByOrd: forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a*) -(*val predicate_of_ord : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> 'a -> bool*) +(*val predicate_of_ord : forall 'a. ('a -> 'a -> ordering) -> 'a -> 'a -> bool*) val _ = Define ` - ((predicate_of_ord:('a -> 'a -> lem_basic_classes$ordering) -> 'a -> 'a -> bool) f x y= - ((case f x y of - LT => T - | EQ => T - | GT => F + ((predicate_of_ord:('a -> 'a -> ordering) -> 'a -> 'a -> bool) f x y= + ((case f x y of + LESS => T + | EQUAL => T + | GREATER => F )))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_stringScript.sml b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml index 9dd53778..f91a4cb0 100644 --- a/snapshots/hol4/lem/hol-lib/lem_stringScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml @@ -50,8 +50,8 @@ val _ = new_theory "lem_string" (*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*) -(*let string_case s c_empty c_cons= - match (toCharList s) with +(*let string_case s c_empty c_cons= + match (toCharList s) with | [] -> c_empty | c :: cs -> c_cons c (toString cs) end*) @@ -63,8 +63,8 @@ val _ = new_theory "lem_string" (*val concat : string -> list string -> string*) val concat_defn = Defn.Hol_multi_defns ` ((concat:string ->(string)list -> string) sep ([])= "") -/\ ((concat:string ->(string)list -> string) sep (s :: ss')= - ((case ss' of +/\ ((concat:string ->(string)list -> string) sep (s :: ss')= + ((case ss' of [] => s | _ => STRCAT s (STRCAT sep (concat sep ss')) )))`; diff --git a/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml index 0801601a..33f71ab7 100644 --- a/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml @@ -35,8 +35,8 @@ val _ = new_theory "lem_string_extra" (*val stringFromNatHelper : nat -> list char -> list char*) val stringFromNatHelper_defn = Hol_defn "stringFromNatHelper" ` - ((stringFromNatHelper:num ->(char)list ->(char)list) n acc= - (if n =( 0 : num) then + ((stringFromNatHelper:num ->(char)list ->(char)list) n acc= + (if n =( 0 : num) then acc else stringFromNatHelper (n DIV( 10 : num)) (CHR ((n MOD( 10 : num)) +( 48 : num)) :: acc)))`; @@ -45,32 +45,32 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn (*val stringFromNat : nat -> string*) -(*val stringFromNaturalHelper : Num.natural -> list char -> list char*) +(*val stringFromNaturalHelper : natural -> list char -> list char*) val stringFromNaturalHelper_defn = Hol_defn "stringFromNaturalHelper" ` - ((stringFromNaturalHelper:num ->(char)list ->(char)list) n acc= - (if n =( 0:num) then + ((stringFromNaturalHelper:num ->(char)list ->(char)list) n acc= + (if n =( 0:num) then acc else stringFromNaturalHelper (n DIV( 10:num)) (CHR ((((n MOD( 10:num)) +( 48:num)):num)) :: acc)))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNaturalHelper_defn; -(*val stringFromNatural : Num.natural -> string*) +(*val stringFromNatural : natural -> string*) -(*val stringFromInt : Num.int -> string*) +(*val stringFromInt : int -> string*) val _ = Define ` - ((stringFromInt:int -> string) i= - (if i <( 0 : int) then - STRCAT"-" (num_to_dec_string (Num (ABS i))) + ((stringFromInt:int -> string) i= + (if i <( 0 : int) then + STRCAT"-" (num_to_dec_string (Num (ABS i))) else num_to_dec_string (Num (ABS i))))`; -(*val stringFromInteger : Num.integer -> string*) +(*val stringFromInteger : integer -> string*) val _ = Define ` - ((stringFromInteger:int -> string) i= - (if i <( 0 : int) then - STRCAT"-" (num_to_dec_string (Num (ABS i))) + ((stringFromInteger:int -> string) i= + (if i <( 0 : int) then + STRCAT"-" (num_to_dec_string (Num (ABS i))) else num_to_dec_string (Num (ABS i))))`; @@ -84,20 +84,20 @@ val _ = Define ` (*let nth s n= List_extra.nth (toCharList s) n*) (*val stringConcat : list string -> string*) -(*let stringConcat s= - List.foldr (^) "" s*) +(*let stringConcat s= + List.foldr (^) "" s*) (******************************************************************************) (* String comparison *) (******************************************************************************) -(*val stringCompare : string -> string -> Basic_classes.ordering*) +(*val stringCompare : string -> string -> ordering*) val _ = Define ` - ((stringLess:string -> string -> bool) x y= (orderingIsLess (EQ)))`; + ((stringLess:string -> string -> bool) x y= (orderingIsLess (EQUAL)))`; val _ = Define ` - ((stringLessEq:string -> string -> bool) x y= (~ (orderingIsGreater (EQ))))`; + ((stringLessEq:string -> string -> bool) x y= (~ (orderingIsGreater (EQUAL))))`; val _ = Define ` ((stringGreater:string -> string -> bool) x y= (stringLess y x))`; @@ -107,9 +107,9 @@ val _ = Define ` val _ = Define ` -((instance_Basic_classes_Ord_string_dict:(string)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_string_dict:(string)Ord_class)= (<| - compare_method := (\ x y. EQ); + compare_method := (\ x y. EQUAL); isLess_method := stringLess; diff --git a/snapshots/hol4/lem/hol-lib/lem_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml index 690909a0..a8639e81 100644 --- a/snapshots/hol4/lem/hol-lib/lem_wordScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml @@ -32,8 +32,8 @@ val _ = Hol_datatype ` (*val boolListFrombitSeq : nat -> bitSequence -> list bool*) val _ = Define ` - ((boolListFrombitSeqAux:num -> 'a -> 'a list -> 'a list) n s bl= - (if n =( 0 : num) then [] else + ((boolListFrombitSeqAux:num -> 'a -> 'a list -> 'a list) n s bl= + (if n =( 0 : num) then [] else (case bl of [] => REPLICATE n s | b :: bl' => b :: (boolListFrombitSeqAux (n -( 1 : num)) s bl') @@ -45,10 +45,10 @@ val _ = Define ` -(*val bitSeqFromBoolList : list bool -> Maybe.maybe bitSequence*) +(*val bitSeqFromBoolList : list bool -> maybe bitSequence*) val _ = Define ` - ((bitSeqFromBoolList:(bool)list ->(bitSequence)option) bl= - ((case dest_init bl of + ((bitSeqFromBoolList:(bool)list ->(bitSequence)option) bl= + ((case dest_init bl of NONE => NONE | SOME (bl', s) => SOME (BitSeq (SOME (LENGTH bl)) s bl') )))`; @@ -65,7 +65,7 @@ val _ = Define ` -(*val bitSeqTestBit : bitSequence -> nat -> Maybe.maybe bool*) +(*val bitSeqTestBit : bitSequence -> nat -> maybe bool*) val _ = Define ` ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq NONE s bl) pos= (if pos < LENGTH bl then list_index bl pos else SOME s)) /\ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq(SOME l) s bl) pos= (if (pos >= l) then NONE else @@ -75,15 +75,15 @@ val _ = Define ` (*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*) val _ = Define ` - ((bitSeqSetBit:bitSequence -> num -> bool -> bitSequence) (BitSeq len s bl) pos v= - (let bl' = (if (pos < LENGTH bl) then bl else bl ++ REPLICATE pos s) in + ((bitSeqSetBit:bitSequence -> num -> bool -> bitSequence) (BitSeq len s bl) pos v= + (let bl' = (if (pos < LENGTH bl) then bl else bl ++ REPLICATE pos s) in let bl'' = (LUPDATE v pos bl') in let bs' = (BitSeq len s bl'') in cleanBitSeq bs'))`; -(*val resizeBitSeq : Maybe.maybe nat -> bitSequence -> bitSequence*) +(*val resizeBitSeq : maybe nat -> bitSequence -> bitSequence*) val _ = Define ` ((resizeBitSeq:(num)option -> bitSequence -> bitSequence) new_len bs= ((case cleanBitSeq bs of @@ -165,8 +165,8 @@ val _ = Define ` (*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*) val _ = Define ` - ((bitSeqLogicalShiftRight:bitSequence -> num -> bitSequence) bs n= - (if (n =( 0 : num)) then cleanBitSeq bs else + ((bitSeqLogicalShiftRight:bitSequence -> num -> bitSequence) bs n= + (if (n =( 0 : num)) then cleanBitSeq bs else (case cleanBitSeq bs of (BitSeq len s bl) => (case len of @@ -180,7 +180,7 @@ val _ = Define ` (* integerFromBoolList sign bl creates an integer from a list of bits (least significant bit first) and an explicitly given sign bit. It uses two's complement encoding. *) -(*val integerFromBoolList : (bool * list bool) -> Num.integer*) +(*val integerFromBoolList : (bool * list bool) -> integer*) val _ = Define ` ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) (([]) : bool list)= acc) @@ -189,18 +189,18 @@ val _ = Define ` val _ = Define ` - ((integerFromBoolList:bool#(bool)list -> int) (sign, bl)= - (if sign then + ((integerFromBoolList:bool#(bool)list -> int) (sign, bl)= + (if sign then ~ (integerFromBoolListAux(( 0 : int)) (REVERSE (MAP (\ x. ~ x) bl)) +( 1 : int)) else integerFromBoolListAux(( 0 : int)) (REVERSE bl)))`; (* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*) -(*val boolListFromInteger : Num.integer -> bool * list bool*) +(*val boolListFromInteger : integer -> bool * list bool*) val _ = Define ` - ((boolListFromNatural:(bool)list -> num ->(bool)list) acc (remainder : num)= - (if (remainder >( 0:num)) then + ((boolListFromNatural:(bool)list -> num ->(bool)list) acc (remainder : num)= + (if (remainder >( 0:num)) then (boolListFromNatural (((remainder MOD( 2:num)) =( 1:num)) :: acc) (remainder DIV( 2:num))) else @@ -208,8 +208,8 @@ val _ = Define ` val _ = Define ` - ((boolListFromInteger:int -> bool#(bool)list) (i : int)= - (if (i <( 0 : int)) then + ((boolListFromInteger:int -> bool#(bool)list) (i : int)= + (if (i <( 0 : int)) then (T, MAP (\ x. ~ x) (boolListFromNatural [] (Num (ABS (~ (i +( 1 : int))))))) else (F, boolListFromNatural [] (Num (ABS i)))))`; @@ -218,15 +218,15 @@ val _ = Define ` (* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough bits, truncation happens *) -(*val bitSeqFromInteger : Maybe.maybe nat -> Num.integer -> bitSequence*) +(*val bitSeqFromInteger : maybe nat -> integer -> bitSequence*) val _ = Define ` - ((bitSeqFromInteger:(num)option -> int -> bitSequence) len_opt i= - (let (s, bl) = (boolListFromInteger i) in + ((bitSeqFromInteger:(num)option -> int -> bitSequence) len_opt i= + (let (s, bl) = (boolListFromInteger i) in resizeBitSeq len_opt (BitSeq NONE s bl)))`; -(*val integerFromBitSeq : bitSequence -> Num.integer*) +(*val integerFromBitSeq : bitSequence -> integer*) val _ = Define ` ((integerFromBitSeq:bitSequence -> int) bs= ((case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) )))`; @@ -235,7 +235,7 @@ val _ = Define ` (* Now we can via translation to integers map arithmetic operations to bitSequences *) -(*val bitSeqArithUnaryOp : (Num.integer -> Num.integer) -> bitSequence -> bitSequence*) +(*val bitSeqArithUnaryOp : (integer -> integer) -> bitSequence -> bitSequence*) val _ = Define ` ((bitSeqArithUnaryOp:(int -> int) -> bitSequence -> bitSequence) uop bs= ((case bs of @@ -244,7 +244,7 @@ val _ = Define ` )))`; -(*val bitSeqArithBinOp : (Num.integer -> Num.integer -> Num.integer) -> bitSequence -> bitSequence -> bitSequence*) +(*val bitSeqArithBinOp : (integer -> integer -> integer) -> bitSequence -> bitSequence -> bitSequence*) val _ = Define ` ((bitSeqArithBinOp:(int -> int -> int) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2= ((case bs1 of @@ -261,7 +261,7 @@ val _ = Define ` )))`; -(*val bitSeqArithBinTest : forall 'a. (Num.integer -> Num.integer -> 'a) -> bitSequence -> bitSequence -> 'a*) +(*val bitSeqArithBinTest : forall 'a. (integer -> integer -> 'a) -> bitSequence -> bitSequence -> 'a*) val _ = Define ` ((bitSeqArithBinTest:(int -> int -> 'a) -> bitSequence -> bitSequence -> 'a) binop bs1 bs2= (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)))`; @@ -291,13 +291,13 @@ val _ = Define ` ((bitSeqGreaterEqual:bitSequence -> bitSequence -> bool) bs1 bs2= (bitSeqArithBinTest (>=) bs1 bs2))`; -(*val bitSeqCompare : bitSequence -> bitSequence -> Basic_classes.ordering*) +(*val bitSeqCompare : bitSequence -> bitSequence -> ordering*) val _ = Define ` - ((bitSeqCompare:bitSequence -> bitSequence -> lem_basic_classes$ordering) bs1 bs2= (bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2))`; + ((bitSeqCompare:bitSequence -> bitSequence -> ordering) bs1 bs2= (bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2))`; val _ = Define ` -((instance_Basic_classes_Ord_Word_bitSequence_dict:(bitSequence)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Word_bitSequence_dict:(bitSequence)Ord_class)= (<| compare_method := bitSeqCompare; @@ -317,7 +317,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumNegate_Word_bitSequence_dict:(bitSequence)lem_num$NumNegate_class)= (<| +((instance_Num_NumNegate_Word_bitSequence_dict:(bitSequence)NumNegate_class)= (<| numNegate_method := bitSeqNegate|>))`; @@ -329,7 +329,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumAdd_Word_bitSequence_dict:(bitSequence)lem_num$NumAdd_class)= (<| +((instance_Num_NumAdd_Word_bitSequence_dict:(bitSequence)NumAdd_class)= (<| numAdd_method := bitSeqAdd|>))`; @@ -340,7 +340,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumMinus_Word_bitSequence_dict:(bitSequence)lem_num$NumMinus_class)= (<| +((instance_Num_NumMinus_Word_bitSequence_dict:(bitSequence)NumMinus_class)= (<| numMinus_method := bitSeqMinus|>))`; @@ -351,7 +351,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumSucc_Word_bitSequence_dict:(bitSequence)lem_num$NumSucc_class)= (<| +((instance_Num_NumSucc_Word_bitSequence_dict:(bitSequence)NumSucc_class)= (<| succ_method := bitSeqSucc|>))`; @@ -362,7 +362,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumPred_Word_bitSequence_dict:(bitSequence)lem_num$NumPred_class)= (<| +((instance_Num_NumPred_Word_bitSequence_dict:(bitSequence)NumPred_class)= (<| pred_method := bitSeqPred|>))`; @@ -373,7 +373,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumMult_Word_bitSequence_dict:(bitSequence)lem_num$NumMult_class)= (<| +((instance_Num_NumMult_Word_bitSequence_dict:(bitSequence)NumMult_class)= (<| numMult_method := bitSeqMult|>))`; @@ -385,7 +385,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumPow_Word_bitSequence_dict:(bitSequence)lem_num$NumPow_class)= (<| +((instance_Num_NumPow_Word_bitSequence_dict:(bitSequence)NumPow_class)= (<| numPow_method := bitSeqPow|>))`; @@ -396,13 +396,13 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumIntegerDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumIntegerDivision_class)= (<| +((instance_Num_NumIntegerDivision_Word_bitSequence_dict:(bitSequence)NumIntegerDivision_class)= (<| div_method := bitSeqDiv|>))`; val _ = Define ` -((instance_Num_NumDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumDivision_class)= (<| +((instance_Num_NumDivision_Word_bitSequence_dict:(bitSequence)NumDivision_class)= (<| numDivision_method := bitSeqDiv|>))`; @@ -413,7 +413,7 @@ val _ = Define ` val _ = Define ` -((instance_Num_NumRemainder_Word_bitSequence_dict:(bitSequence)lem_num$NumRemainder_class)= (<| +((instance_Num_NumRemainder_Word_bitSequence_dict:(bitSequence)NumRemainder_class)= (<| mod_method := bitSeqMod|>))`; @@ -429,7 +429,7 @@ val _ = Define ` val _ = Define ` -((instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict:(bitSequence)lem_basic_classes$OrdMaxMin_class)= (<| +((instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict:(bitSequence)OrdMaxMin_class)= (<| max_method := bitSeqMax; @@ -537,7 +537,7 @@ val _ = Define ` (* int32 *) (* ----------------------- *) -(*val int32Lnot : Num.int32 -> Num.int32*) (* XXX: fix *) +(*val int32Lnot : int32 -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordNot_Num_int32_dict:(word32)WordNot_class)= (<| @@ -546,7 +546,7 @@ val _ = Define ` -(*val int32Lor : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) +(*val int32Lor : int32 -> int32 -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordOr_Num_int32_dict:(word32)WordOr_class)= (<| @@ -554,7 +554,7 @@ val _ = Define ` lor_method := word_or|>))`; -(*val int32Lxor : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) +(*val int32Lxor : int32 -> int32 -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordXor_Num_int32_dict:(word32)WordXor_class)= (<| @@ -562,7 +562,7 @@ val _ = Define ` lxor_method := word_xor|>))`; -(*val int32Land : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *) +(*val int32Land : int32 -> int32 -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordAnd_Num_int32_dict:(word32)WordAnd_class)= (<| @@ -570,7 +570,7 @@ val _ = Define ` land_method := word_and|>))`; -(*val int32Lsl : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) +(*val int32Lsl : int32 -> nat -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordLsl_Num_int32_dict:(word32)WordLsl_class)= (<| @@ -578,7 +578,7 @@ val _ = Define ` lsl_method := word_lsl|>))`; -(*val int32Lsr : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) +(*val int32Lsr : int32 -> nat -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordLsr_Num_int32_dict:(word32)WordLsr_class)= (<| @@ -587,7 +587,7 @@ val _ = Define ` -(*val int32Asr : Num.int32 -> nat -> Num.int32*) (* XXX: fix *) +(*val int32Asr : int32 -> nat -> int32*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordAsr_Num_int32_dict:(word32)WordAsr_class)= (<| @@ -600,7 +600,7 @@ val _ = Define ` (* int64 *) (* ----------------------- *) -(*val int64Lnot : Num.int64 -> Num.int64*) (* XXX: fix *) +(*val int64Lnot : int64 -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordNot_Num_int64_dict:(word64)WordNot_class)= (<| @@ -608,7 +608,7 @@ val _ = Define ` lnot_method := (\ w. (~ w))|>))`; -(*val int64Lor : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) +(*val int64Lor : int64 -> int64 -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordOr_Num_int64_dict:(word64)WordOr_class)= (<| @@ -616,7 +616,7 @@ val _ = Define ` lor_method := word_or|>))`; -(*val int64Lxor : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) +(*val int64Lxor : int64 -> int64 -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordXor_Num_int64_dict:(word64)WordXor_class)= (<| @@ -624,7 +624,7 @@ val _ = Define ` lxor_method := word_xor|>))`; -(*val int64Land : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *) +(*val int64Land : int64 -> int64 -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordAnd_Num_int64_dict:(word64)WordAnd_class)= (<| @@ -632,7 +632,7 @@ val _ = Define ` land_method := word_and|>))`; -(*val int64Lsl : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) +(*val int64Lsl : int64 -> nat -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordLsl_Num_int64_dict:(word64)WordLsl_class)= (<| @@ -640,7 +640,7 @@ val _ = Define ` lsl_method := word_lsl|>))`; -(*val int64Lsr : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) +(*val int64Lsr : int64 -> nat -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordLsr_Num_int64_dict:(word64)WordLsr_class)= (<| @@ -648,7 +648,7 @@ val _ = Define ` lsr_method := word_lsr|>))`; -(*val int64Asr : Num.int64 -> nat -> Num.int64*) (* XXX: fix *) +(*val int64Asr : int64 -> nat -> int64*) (* XXX: fix *) val _ = Define ` ((instance_Word_WordAsr_Num_int64_dict:(word64)WordAsr_class)= (<| @@ -700,7 +700,7 @@ val _ = Define ` (* integer *) (* ----------------------- *) -(*val integerLnot : Num.integer -> Num.integer*) +(*val integerLnot : integer -> integer*) val _ = Define ` ((integerLnot:int -> int) i= (~ (i +( 1 : int))))`; @@ -712,7 +712,7 @@ val _ = Define ` -(*val integerLor : Num.integer -> Num.integer -> Num.integer*) +(*val integerLor : integer -> integer -> integer*) val _ = Define ` ((integerLor:int -> int -> int) i1 i2= (defaultLor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; @@ -723,7 +723,7 @@ val _ = Define ` lor_method := integerLor|>))`; -(*val integerLxor : Num.integer -> Num.integer -> Num.integer*) +(*val integerLxor : integer -> integer -> integer*) val _ = Define ` ((integerLxor:int -> int -> int) i1 i2= (defaultLxor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; @@ -734,7 +734,7 @@ val _ = Define ` lxor_method := integerLxor|>))`; -(*val integerLand : Num.integer -> Num.integer -> Num.integer*) +(*val integerLand : integer -> integer -> integer*) val _ = Define ` ((integerLand:int -> int -> int) i1 i2= (defaultLand integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`; @@ -745,7 +745,7 @@ val _ = Define ` land_method := integerLand|>))`; -(*val integerLsl : Num.integer -> nat -> Num.integer*) +(*val integerLsl : integer -> nat -> integer*) val _ = Define ` ((integerLsl:int -> num -> int) i n= (defaultLsl integerFromBitSeq (bitSeqFromInteger NONE) i n))`; @@ -756,7 +756,7 @@ val _ = Define ` lsl_method := integerLsl|>))`; -(*val integerAsr : Num.integer -> nat -> Num.integer*) +(*val integerAsr : integer -> nat -> integer*) val _ = Define ` ((integerAsr:int -> num -> int) i n= (defaultAsr integerFromBitSeq (bitSeqFromInteger NONE) i n))`; @@ -783,19 +783,19 @@ val _ = Define ` it should be used very carefully and only for operations that don't depend on the bitwidth of int *) -(*val intFromBitSeq : bitSequence -> Num.int*) +(*val intFromBitSeq : bitSequence -> int*) val _ = Define ` ((intFromBitSeq:bitSequence -> int) bs= (I (integerFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs))))`; -(*val bitSeqFromInt : Num.int -> bitSequence*) +(*val bitSeqFromInt : int -> bitSequence*) val _ = Define ` ((bitSeqFromInt:int -> bitSequence) i= (bitSeqFromInteger (SOME(( 31 : num))) ( i)))`; -(*val intLnot : Num.int -> Num.int*) +(*val intLnot : int -> int*) val _ = Define ` ((intLnot:int -> int) i= (~ (i +( 1 : int))))`; @@ -806,7 +806,7 @@ val _ = Define ` lnot_method := intLnot|>))`; -(*val intLor : Num.int -> Num.int -> Num.int*) +(*val intLor : int -> int -> int*) val _ = Define ` ((intLor:int -> int -> int) i1 i2= (defaultLor intFromBitSeq bitSeqFromInt i1 i2))`; @@ -817,7 +817,7 @@ val _ = Define ` lor_method := intLor|>))`; -(*val intLxor : Num.int -> Num.int -> Num.int*) +(*val intLxor : int -> int -> int*) val _ = Define ` ((intLxor:int -> int -> int) i1 i2= (defaultLxor intFromBitSeq bitSeqFromInt i1 i2))`; @@ -828,7 +828,7 @@ val _ = Define ` lxor_method := intLxor|>))`; -(*val intLand : Num.int -> Num.int -> Num.int*) +(*val intLand : int -> int -> int*) val _ = Define ` ((intLand:int -> int -> int) i1 i2= (defaultLand intFromBitSeq bitSeqFromInt i1 i2))`; @@ -839,7 +839,7 @@ val _ = Define ` land_method := intLand|>))`; -(*val intLsl : Num.int -> nat -> Num.int*) +(*val intLsl : int -> nat -> int*) val _ = Define ` ((intLsl:int -> num -> int) i n= (defaultLsl intFromBitSeq bitSeqFromInt i n))`; @@ -850,7 +850,7 @@ val _ = Define ` lsl_method := intLsl|>))`; -(*val intAsr : Num.int -> nat -> Num.int*) +(*val intAsr : int -> nat -> int*) val _ = Define ` ((intAsr:int -> num -> int) i n= (defaultAsr intFromBitSeq bitSeqFromInt i n))`; @@ -869,17 +869,17 @@ val _ = Define ` (* some operations work also on positive numbers *) -(*val naturalFromBitSeq : bitSequence -> Num.natural*) +(*val naturalFromBitSeq : bitSequence -> natural*) val _ = Define ` ((naturalFromBitSeq:bitSequence -> num) bs= (Num (ABS (integerFromBitSeq bs))))`; -(*val bitSeqFromNatural : Maybe.maybe nat -> Num.natural -> bitSequence*) +(*val bitSeqFromNatural : maybe nat -> natural -> bitSequence*) val _ = Define ` ((bitSeqFromNatural:(num)option -> num -> bitSequence) len n= (bitSeqFromInteger len (int_of_num n)))`; -(*val naturalLor : Num.natural -> Num.natural -> Num.natural*) +(*val naturalLor : natural -> natural -> natural*) val _ = Define ` ((naturalLor:num -> num -> num) i1 i2= (defaultLor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; @@ -890,7 +890,7 @@ val _ = Define ` lor_method := naturalLor|>))`; -(*val naturalLxor : Num.natural -> Num.natural -> Num.natural*) +(*val naturalLxor : natural -> natural -> natural*) val _ = Define ` ((naturalLxor:num -> num -> num) i1 i2= (defaultLxor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; @@ -901,7 +901,7 @@ val _ = Define ` lxor_method := naturalLxor|>))`; -(*val naturalLand : Num.natural -> Num.natural -> Num.natural*) +(*val naturalLand : natural -> natural -> natural*) val _ = Define ` ((naturalLand:num -> num -> num) i1 i2= (defaultLand naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`; @@ -912,7 +912,7 @@ val _ = Define ` land_method := naturalLand|>))`; -(*val naturalLsl : Num.natural -> nat -> Num.natural*) +(*val naturalLsl : natural -> nat -> natural*) val _ = Define ` ((naturalLsl:num -> num -> num) i n= (defaultLsl naturalFromBitSeq (bitSeqFromNatural NONE) i n))`; @@ -923,7 +923,7 @@ val _ = Define ` lsl_method := naturalLsl|>))`; -(*val naturalAsr : Num.natural -> nat -> Num.natural*) +(*val naturalAsr : natural -> nat -> natural*) val _ = Define ` ((naturalAsr:num -> num -> num) i n= (defaultAsr naturalFromBitSeq (bitSeqFromNatural NONE) i n))`; diff --git a/snapshots/hol4/sail/cheri/Holmakefile b/snapshots/hol4/sail/cheri/Holmakefile index 604555b5..d64fc3fd 100644 --- a/snapshots/hol4/sail/cheri/Holmakefile +++ b/snapshots/hol4/sail/cheri/Holmakefile @@ -2,7 +2,7 @@ LEMDIR=../../lem/hol-lib INCLUDES = $(LEMDIR) ../lib/hol -all: cheri_sequentialTheory.uo +all: cheriTheory.uo .PHONY: all ifdef POLY diff --git a/snapshots/hol4/sail/cheri/cheriScript.sml b/snapshots/hol4/sail/cheri/cheriScript.sml new file mode 100644 index 00000000..d3e724c0 --- /dev/null +++ b/snapshots/hol4/sail/cheri/cheriScript.sml @@ -0,0 +1,10645 @@ +(*Generated by Lem from cheri.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory cheri_typesTheory mips_extrasTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "cheri" + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import Cheri_types*) +(*open import Mips_extras*) + +val _ = Define ` + ((cap_size:int)= ((( 32 : int):ii)))`; + + +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +val _ = Define ` + ((undefined_option:'a ->(regstate)state_monad$sequential_state ->((('a option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) typ_a= (state_monad$seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`; + + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +val _ = Define ` + ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val cast_unit_vec : bitU -> mword ty1*) + +val _ = Define ` + ((cast_unit_vec0:bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +val _ = Define ` + ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= + (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr data))`; + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MIPS_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'p8_times_n_ words$word) M)))`; + + + + +(*val undefined_exception : unit -> M exception*) + +val _ = Define ` + ((undefined_exception:unit ->(regstate)state_monad$sequential_state ->(((exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (state_monad$seqS + (undefined_unit () ) + (undefined_string () )) (\ (w__0 : string) . state_monad$seqS (state_monad$seqS (state_monad$seqS + (undefined_unit () ) + (undefined_unit () )) + (undefined_unit () )) + (internal_pick + [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`; + + +(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + + +val _ = Define ` + ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + + +(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +val _ = Define ` + ((zeros0:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B0] : 1 words$word) n__tv : 'n words$word)))`; + + +(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +val _ = Define ` + ((ones:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B1] : 1 words$word) n__tv : 'n words$word)))`; + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +val _ = Define ` + ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) >= ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) < ((lem$w2ui y))))`; + + +val _ = Define ` + ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) >= ((lem$w2ui y))))`; + + +(*val bool_to_bits : bool -> mword ty1*) + +val _ = Define ` + ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val bit_to_bool : bitU -> bool*) + +val _ = Define ` + ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; + + +(*val bits_to_bool : mword ty1 -> bool*) + +val _ = Define ` + ((bits_to_bool:(1)words$word -> bool) x= (bit_to_bool ((access_vec_dec x (( 0 : int):ii)))))`; + + +(* +\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. +*) +(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) + +val _ = Define ` + ((to_bits:'l itself -> int -> 'l words$word) l n= + (let l = (size_itself_int l) in + (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii) : 'l words$word)))`; + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) + +val _ = Define ` + ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs= + ((subrange_vec_dec bs ((n__tv - (( 1 : int):ii))) (( 0 : int):ii) : 'n words$word)))`; + + +(*val undefined_CauseReg : unit -> M CauseReg*) + +val _ = Define ` + ((undefined_CauseReg:unit ->(regstate)state_monad$sequential_state ->(((CauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + internal_pick [Mk_CauseReg w__0])))`; + + +(*val _get_CauseReg : CauseReg -> mword ty32*) + +val _ = Define ` + ((get_CauseReg:CauseReg ->(32)words$word) (Mk_CauseReg (v))= v)`; + + +(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) + +val _ = Define ` + ((set_CauseReg:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_CauseReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) + +(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) + +(*val _get_CauseReg_BD : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_BD:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_CE : CauseReg -> mword ty2*) + +val _ = Define ` + ((get_CauseReg_CE:CauseReg ->(2)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii) : 2 words$word)))`; + + +(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 28 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_IV : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_IV:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_WP : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_WP:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_IP : CauseReg -> mword ty8*) + +val _ = Define ` + ((get_CauseReg_IP:CauseReg ->(8)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 32 words$word))))`; + + +(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) + +val _ = Define ` + ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)))`; + + +(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) + +val _ = Define ` + ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . + let r = ((get_CauseReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 2 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_CauseReg r))))`; + + +(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) (Mk_CauseReg (v)) x= + (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii) x : 32 words$word))))`; + + +(*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) + +(*val _get_CapCauseReg_ExcCode : CapCauseReg -> mword ty8*) + +(*val _set_CapCauseReg_ExcCode : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) + +val _ = Define ` + ((undefined_TLBEntryLoReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryLoReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_TLBEntryLoReg w__0])))`; + + +(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) + +val _ = Define ` + ((get_TLBEntryLoReg:TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))= v)`; + + +(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_TLBEntryLoReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) + +val _ = Define ` + ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))= + ((subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 6 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) + +val _ = Define ` + ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . + let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + + +(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= + (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) + +val _ = Define ` + ((undefined_TLBEntryHiReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryHiReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_TLBEntryHiReg w__0])))`; + + +(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) + +val _ = Define ` + ((get_TLBEntryHiReg:TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))= v)`; + + +(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_TLBEntryHiReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) + +val _ = Define ` + ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; + + +(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) + +val _ = Define ` + ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))= + ((subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))`; + + +(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 39 : int):ii) (( 13 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + + +(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) + +val _ = Define ` + ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . + let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + + +(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= + (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val undefined_ContextReg : unit -> M ContextReg*) + +val _ = Define ` + ((undefined_ContextReg:unit ->(regstate)state_monad$sequential_state ->(((ContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_ContextReg w__0])))`; + + +(*val _get_ContextReg : ContextReg -> mword ty64*) + +val _ = Define ` + ((get_ContextReg:ContextReg ->(64)words$word) (Mk_ContextReg (v))= v)`; + + +(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_ContextReg:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_ContextReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) + +val _ = Define ` + ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)))`; + + +(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) + +val _ = Define ` + ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . + let r = ((get_ContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 23 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_ContextReg r))))`; + + +(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) (Mk_ContextReg (v)) x= + (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii) x : 64 words$word))))`; + + +(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) + +val _ = Define ` + ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii) : 19 words$word)))`; + + +(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) + +val _ = Define ` + ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . + let r = ((get_ContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_ContextReg r))))`; + + +(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) (Mk_ContextReg (v)) x= + (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +(*val undefined_XContextReg : unit -> M XContextReg*) + +val _ = Define ` + ((undefined_XContextReg:unit ->(regstate)state_monad$sequential_state ->(((XContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + internal_pick [Mk_XContextReg w__0])))`; + + +(*val _get_XContextReg : XContextReg -> mword ty64*) + +val _ = Define ` + ((get_XContextReg:XContextReg ->(64)words$word) (Mk_XContextReg (v))= v)`; + + +(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_XContextReg:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_XContextReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) + +val _ = Define ` + ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) (Mk_XContextReg (v))= + ((subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)))`; + + +(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 33 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii) x : 64 words$word))))`; + + +(*val _get_XContextReg_XR : XContextReg -> mword ty2*) + +val _ = Define ` + ((get_XContextReg_XR:XContextReg ->(2)words$word) (Mk_XContextReg (v))= ((subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii) : 2 words$word)))`; + + +(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 31 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii) x : 64 words$word))))`; + + +(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) + +val _ = Define ` + ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) (Mk_XContextReg (v))= + ((subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii) : 27 words$word)))`; + + +(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . + let r = ((get_XContextReg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_XContextReg r))))`; + + +(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) (Mk_XContextReg (v)) x= + (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((TLBNumEntries:int)= ((( 64 : int):ii)))`; + + +val _ = Define ` +((TLBIndexMax:(6)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))`; + + +(*val MAX : integer -> integer*) + +val _ = Define ` + ((MAX0:int -> int) n= (((pow2 n)) - (( 1 : int):ii)))`; + + +val _ = Define ` + ((MAX_U64:int)= (MAX0 (( 64 : int):ii)))`; + + +val _ = Define ` + ((MAX_VA:int)= (MAX0 (( 40 : int):ii)))`; + + +val _ = Define ` + ((MAX_PA:int)= (MAX0 (( 36 : int):ii)))`; + + +(*val undefined_TLBEntry : unit -> M TLBEntry*) + +val _ = Define ` + ((undefined_TLBEntry:unit ->(regstate)state_monad$sequential_state ->(((TLBEntry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):ii) : ( 117 words$word) M) (\ (w__0 : 117 words$word) . + internal_pick [Mk_TLBEntry w__0])))`; + + +(*val _get_TLBEntry : TLBEntry -> mword ty117*) + +val _ = Define ` + ((get_TLBEntry:TLBEntry ->(117)words$word) (Mk_TLBEntry (v))= v)`; + + +(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +val _ = Define ` + ((set_TLBEntry:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_TLBEntry v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) + +val _ = Define ` + ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii) : 16 words$word)))`; + + +(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 116 : int):ii) (( 101 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_r : TLBEntry -> mword ty2*) + +val _ = Define ` + ((get_TLBEntry_r:TLBEntry ->(2)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii) : 2 words$word)))`; + + +(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 100 : int):ii) (( 99 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) + +val _ = Define ` + ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii) : 27 words$word)))`; + + +(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 98 : int):ii) (( 72 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) + +val _ = Define ` + ((get_TLBEntry_asid:TLBEntry ->(8)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii) : 8 words$word)))`; + + +(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 71 : int):ii) (( 64 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_g : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_g:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_valid:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 61 : int):ii) (( 61 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 60 : int):ii) (( 60 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 36 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) + +val _ = Define ` + ((get_TLBEntry_c1:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 33 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_d1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 32 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_v1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 30 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 29 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 28 : int):ii) (( 5 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) + +val _ = Define ` + ((get_TLBEntry_c0:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 2 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_d0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 117 words$word))))`; + + +(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_v0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . + let r = ((get_TLBEntry w__0 : 117 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 117 words$word)) in + state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + + +(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= + (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 117 words$word))))`; + + +val _ = Define ` +((TLBEntries:(((regstate),(register_value),(TLBEntry))register_ref)list)= + ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref; + TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref; + TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref; + TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref; + TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref; + TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref; + TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref; + TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref; + TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref; + TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;TLBEntry00_ref]))`; + + +(*val undefined_StatusReg : unit -> M StatusReg*) + +val _ = Define ` + ((undefined_StatusReg:unit ->(regstate)state_monad$sequential_state ->(((StatusReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + internal_pick [Mk_StatusReg w__0])))`; + + +(*val _get_StatusReg : StatusReg -> mword ty32*) + +val _ = Define ` + ((get_StatusReg:StatusReg ->(32)words$word) (Mk_StatusReg (v))= v)`; + + +(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) + +val _ = Define ` + ((set_StatusReg:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_StatusReg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_StatusReg_CU : StatusReg -> mword ty4*) + +val _ = Define ` + ((get_StatusReg_CU:StatusReg ->(4)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)))`; + + +(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) + +val _ = Define ` + ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 28 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_BEV : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_BEV:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_IM : StatusReg -> mword ty8*) + +val _ = Define ` + ((get_StatusReg_IM:StatusReg ->(8)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_KX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_KX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_SX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_SX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_UX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_UX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_KSU : StatusReg -> mword ty2*) + +val _ = Define ` + ((get_StatusReg_KSU:StatusReg ->(2)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`; + + +(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 3 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_ERL : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_ERL:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_EXL : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_EXL:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 32 words$word))))`; + + +(*val _get_StatusReg_IE : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_IE:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . + let r = ((get_StatusReg w__0 : 32 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 32 words$word)) in + state_monad$write_regS r_ref (Mk_StatusReg r))))`; + + +(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= + (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 32 words$word))))`; + + +(*val execute_branch : mword ty64 -> M unit*) + +val _ = Define ` + ((execute_branch:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pc= (state_monad$seqS + (state_monad$write_regS delayedPC_ref pc) (state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + + +(*val NotWordVal : mword ty64 -> bool*) + +val _ = Define ` + ((NotWordVal:(64)words$word -> bool) word= + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):ii))) : 1 words$word)) (( 32 : int):ii) + : 32 words$word)) <> ((subrange_vec_dec word (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))))`; + + +(*val rGPR : mword ty5 -> M (mword ty64)*) + +val _ = Define ` + ((rGPR:(5)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx= + (let i = (lem$w2ui idx) in + if (((i = (( 0 : int):ii)))) then + state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else state_monad$bindS + (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . + state_monad$returnS ((access_list_dec w__0 i : 64 words$word)))))`; + + +(*val wGPR : mword ty5 -> mword ty64 -> M unit*) + +val _ = Define ` + ((wGPR:(5)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx v= + (let i = (lem$w2ui idx) in + if (((i = (( 0 : int):ii)))) then state_monad$returnS () + else state_monad$bindS + (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . + state_monad$write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list)))))`; + + + + + + + + + + + + + + + + +(*val Exception_of_num : integer -> Exception*) + +val _ = Define ` + ((Exception_of_num:int -> Exception) arg_= + (let l__81 = arg_ in + if (((l__81 = (( 0 : int):ii)))) then Interrupt + else if (((l__81 = (( 1 : int):ii)))) then TLBMod + else if (((l__81 = (( 2 : int):ii)))) then TLBL + else if (((l__81 = (( 3 : int):ii)))) then TLBS + else if (((l__81 = (( 4 : int):ii)))) then AdEL + else if (((l__81 = (( 5 : int):ii)))) then AdES + else if (((l__81 = (( 6 : int):ii)))) then Sys + else if (((l__81 = (( 7 : int):ii)))) then Bp + else if (((l__81 = (( 8 : int):ii)))) then ResI + else if (((l__81 = (( 9 : int):ii)))) then CpU + else if (((l__81 = (( 10 : int):ii)))) then Ov + else if (((l__81 = (( 11 : int):ii)))) then Tr + else if (((l__81 = (( 12 : int):ii)))) then C2E + else if (((l__81 = (( 13 : int):ii)))) then C2Trap + else if (((l__81 = (( 14 : int):ii)))) then XTLBRefillL + else if (((l__81 = (( 15 : int):ii)))) then XTLBRefillS + else if (((l__81 = (( 16 : int):ii)))) then XTLBInvL + else if (((l__81 = (( 17 : int):ii)))) then XTLBInvS + else MCheck))`; + + +(*val num_of_Exception : Exception -> integer*) + +val _ = Define ` + ((num_of_Exception:Exception -> int) arg_= + ((case arg_ of + Interrupt => (( 0 : int):ii) + | TLBMod => (( 1 : int):ii) + | TLBL => (( 2 : int):ii) + | TLBS => (( 3 : int):ii) + | AdEL => (( 4 : int):ii) + | AdES => (( 5 : int):ii) + | Sys => (( 6 : int):ii) + | Bp => (( 7 : int):ii) + | ResI => (( 8 : int):ii) + | CpU => (( 9 : int):ii) + | Ov => (( 10 : int):ii) + | Tr => (( 11 : int):ii) + | C2E => (( 12 : int):ii) + | C2Trap => (( 13 : int):ii) + | XTLBRefillL => (( 14 : int):ii) + | XTLBRefillS => (( 15 : int):ii) + | XTLBInvL => (( 16 : int):ii) + | XTLBInvS => (( 17 : int):ii) + | MCheck => (( 18 : int):ii) + )))`; + + +(*val undefined_Exception : unit -> M Exception*) + +val _ = Define ` + ((undefined_Exception:unit ->(regstate)state_monad$sequential_state ->(((Exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (internal_pick + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`; + + +(*val ExceptionCode : Exception -> mword ty5*) + +val _ = Define ` + ((ExceptionCode:Exception ->(5)words$word) ex= + (let (x : 8 bits) = + ((case ex of + Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) + )) in + (subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)))`; + + +(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) + +val _ = Define ` + ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex kccBase= (state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . state_monad$bindS (state_monad$seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then state_monad$bindS + (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$seqS + (state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii) : 64 words$word))) + (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : 1 words$word))) + else state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . state_monad$seqS + (state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) + else state_monad$returnS () ) + (state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . + let vectorOffset = + (if ((bits_to_bool ((get_StatusReg_EXL w__4 : 1 words$word)))) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . + let (vectorBase : 64 bits) = + (if ((bits_to_bool ((get_StatusReg_BEV w__5 : 1 words$word)))) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((sign_extend1 (( 64 : int):ii) vectorOffset : 64 words$word)) : 64 words$word)) + kccBase + : 64 words$word))) + (set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex : 5 words$word)))) + (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (state_monad$throwS (ISAException () )))))))`; + + +(*val SignalException : forall 'o. Exception -> M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*) + +(*val capRegToCapStruct : mword ty257 -> CapStruct*) + +val _ = Define ` + ((capRegToCapStruct:(257)words$word -> CapStruct) capReg= + (<| CapStruct_tag := ((bit_to_bool ((access_vec_dec capReg (( 256 : int):ii))))); + CapStruct_padding := ((subrange_vec_dec capReg (( 255 : int):ii) (( 248 : int):ii) : 8 words$word)); + CapStruct_otype := ((subrange_vec_dec capReg (( 247 : int):ii) (( 224 : int):ii) : 24 words$word)); + CapStruct_uperms := ((subrange_vec_dec capReg (( 223 : int):ii) (( 208 : int):ii) : 16 words$word)); + CapStruct_perm_reserved11_14 := ((subrange_vec_dec capReg (( 207 : int):ii) (( 204 : int):ii) : 4 words$word)); + CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec capReg (( 203 : int):ii))))); + CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec capReg (( 202 : int):ii))))); + CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec capReg (( 201 : int):ii))))); + CapStruct_permit_seal := ((bit_to_bool ((access_vec_dec capReg (( 200 : int):ii))))); + CapStruct_permit_store_local_cap := ((bit_to_bool ((access_vec_dec capReg (( 199 : int):ii))))); + CapStruct_permit_store_cap := ((bit_to_bool ((access_vec_dec capReg (( 198 : int):ii))))); + CapStruct_permit_load_cap := ((bit_to_bool ((access_vec_dec capReg (( 197 : int):ii))))); + CapStruct_permit_store := ((bit_to_bool ((access_vec_dec capReg (( 196 : int):ii))))); + CapStruct_permit_load := ((bit_to_bool ((access_vec_dec capReg (( 195 : int):ii))))); + CapStruct_permit_execute := ((bit_to_bool ((access_vec_dec capReg (( 194 : int):ii))))); + CapStruct_global := ((bit_to_bool ((access_vec_dec capReg (( 193 : int):ii))))); + CapStruct_sealed := ((bit_to_bool ((access_vec_dec capReg (( 192 : int):ii))))); + CapStruct_address := ((subrange_vec_dec capReg (( 191 : int):ii) (( 128 : int):ii) : 64 words$word)); + CapStruct_base := ((subrange_vec_dec capReg (( 127 : int):ii) (( 64 : int):ii) : 64 words$word)); + CapStruct_length := ((subrange_vec_dec capReg (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val getCapPerms : CapStruct -> mword ty31*) + +val _ = Define ` + ((getCapPerms:CapStruct ->(31)words$word) cap= + ((concat_vec cap.CapStruct_uperms + ((concat_vec cap.CapStruct_perm_reserved11_14 + ((concat_vec ((bool_to_bits cap.CapStruct_access_system_regs : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_unseal : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_ccall : 1 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_permit_seal : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store_local_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_load_cap : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_store : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_load : 1 words$word)) + ((concat_vec + ((bool_to_bits cap.CapStruct_permit_execute + : 1 words$word)) + ((bool_to_bits cap.CapStruct_global : 1 words$word)) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 8 words$word)) + : 9 words$word)) + : 10 words$word)) + : 11 words$word)) + : 15 words$word)) + : 31 words$word)))`; + + +(*val capStructToMemBits256 : CapStruct -> mword ty256*) + +val _ = Define ` + ((capStructToMemBits256:CapStruct ->(256)words$word) cap= + ((concat_vec cap.CapStruct_padding + ((concat_vec cap.CapStruct_otype + ((concat_vec ((getCapPerms cap : 31 words$word)) + ((concat_vec ((bool_to_bits cap.CapStruct_sealed : 1 words$word)) + ((concat_vec cap.CapStruct_address + ((concat_vec cap.CapStruct_base cap.CapStruct_length : 128 words$word)) + : 192 words$word)) + : 193 words$word)) + : 224 words$word)) + : 248 words$word)) + : 256 words$word)))`; + + +(*val capStructToCapReg : CapStruct -> mword ty257*) + +val _ = Define ` + ((capStructToCapReg:CapStruct ->(257)words$word) cap= + ((concat_vec ((bool_to_bits cap.CapStruct_tag : 1 words$word)) + ((capStructToMemBits256 cap : 256 words$word)) + : 257 words$word)))`; + + +(*val getCapBase : CapStruct -> integer*) + +val _ = Define ` + ((getCapBase:CapStruct -> int) c= (lem$w2ui c.CapStruct_base))`; + + +val _ = Define ` +((null_cap:CapStruct)= + (<| CapStruct_tag := F; + CapStruct_padding := ((zeros0 (( 8 : int):ii) () : 8 words$word)); + CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word)); + CapStruct_uperms := ((zeros0 (( 16 : int):ii) () : 16 words$word)); + CapStruct_perm_reserved11_14 := ((zeros0 (( 4 : int):ii) () : 4 words$word)); + CapStruct_access_system_regs := F; + CapStruct_permit_unseal := F; + CapStruct_permit_ccall := F; + CapStruct_permit_seal := F; + CapStruct_permit_store_local_cap := F; + CapStruct_permit_store_cap := F; + CapStruct_permit_load_cap := F; + CapStruct_permit_store := F; + CapStruct_permit_load := F; + CapStruct_permit_execute := F; + CapStruct_global := F; + CapStruct_sealed := F; + CapStruct_address := ((zeros0 (( 64 : int):ii) () : 64 words$word)); + CapStruct_base := ((zeros0 (( 64 : int):ii) () : 64 words$word)); + CapStruct_length := + ((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 64 words$word)) |>))`; + + +(*val int_to_cap : mword ty64 -> CapStruct*) + +val _ = Define ` + ((int_to_cap:(64)words$word -> CapStruct) address= ((null_cap with<| CapStruct_address := address|>)))`; + + +(* +Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). + *) +(*val setCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +val _ = Define ` + ((setCapOffset:CapStruct ->(64)words$word -> bool#CapStruct) c offset= + (T, (c with<| CapStruct_address := ((add_vec c.CapStruct_base offset : 64 words$word))|>)))`; + + +val _ = Define ` + ((SignalException:Exception ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex= (state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . state_monad$bindS (state_monad$seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ pc . state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in + let (success, epcc) = (setCapOffset pcc pc) in + if success then state_monad$write_regS C31_ref ((capStructToCapReg epcc : 257 words$word)) + else + state_monad$write_regS + C31_ref + ((capStructToCapReg + ((int_to_cap + ((add_vec_int + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase pcc)) + : 64 words$word)) ((lem$w2ui pc)) + : 64 words$word)))) + : 257 words$word)))) + else state_monad$returnS () ) + (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__2 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS nextPCC_ref w__2) + (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__3 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS delayedPCC_ref w__3) + (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__4 : 257 words$word) . + let base = (getCapBase ((capRegToCapStruct w__4))) in + SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) base : 64 words$word))))))))`; + + +val _ = Define ` + ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr= (state_monad$seqS (state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; + + +(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) + +val _ = Define ` + ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr= (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0BadVAddr_ref badAddr) + (set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):ii) (( 13 : int):ii) : 19 words$word)))) + (set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))) + (set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (SignalException ex)))`; + + +(*val MemAccessType_of_num : integer -> MemAccessType*) + +val _ = Define ` + ((MemAccessType_of_num:int -> MemAccessType) arg_= + (let l__79 = arg_ in + if (((l__79 = (( 0 : int):ii)))) then Instruction + else if (((l__79 = (( 1 : int):ii)))) then LoadData + else StoreData))`; + + +(*val num_of_MemAccessType : MemAccessType -> integer*) + +val _ = Define ` + ((num_of_MemAccessType:MemAccessType -> int) arg_= + ((case arg_ of Instruction => (( 0 : int):ii) | LoadData => (( 1 : int):ii) | StoreData => (( 2 : int):ii) )))`; + + +(*val undefined_MemAccessType : unit -> M MemAccessType*) + +val _ = Define ` + ((undefined_MemAccessType:unit ->(regstate)state_monad$sequential_state ->(((MemAccessType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [Instruction;LoadData;StoreData]))`; + + +(*val AccessLevel_of_num : integer -> AccessLevel*) + +val _ = Define ` + ((AccessLevel_of_num:int -> AccessLevel) arg_= + (let l__77 = arg_ in + if (((l__77 = (( 0 : int):ii)))) then User + else if (((l__77 = (( 1 : int):ii)))) then Supervisor + else Kernel))`; + + +(*val num_of_AccessLevel : AccessLevel -> integer*) + +val _ = Define ` + ((num_of_AccessLevel:AccessLevel -> int) arg_= + ((case arg_ of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`; + + +(*val undefined_AccessLevel : unit -> M AccessLevel*) + +val _ = Define ` + ((undefined_AccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [User;Supervisor;Kernel]))`; + + +(*val int_of_AccessLevel : AccessLevel -> ii*) + +val _ = Define ` + ((int_of_AccessLevel:AccessLevel -> int) level= + ((case level of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`; + + +(* +Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + *) +(*val grantsAccess : AccessLevel -> AccessLevel -> bool*) + +val _ = Define ` + ((grantsAccess:AccessLevel -> AccessLevel -> bool) currentLevel requiredLevel= + (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`; + + +(* +Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. + *) +(*val getAccessLevel : unit -> M AccessLevel*) + +val _ = Define ` + ((getAccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state$or_boolS + ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) + ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . + state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) (\ (w__2 : bool) . + if w__2 then state_monad$returnS Kernel + else state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . + let p__133 = ((get_StatusReg_KSU w__3 : 2 words$word)) in + let b__0 = p__133 in + state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then User + else User)))))`; + + +(*val checkCP0Access : unit -> M unit*) + +val _ = Define ` + ((checkCP0Access:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (getAccessLevel () ) (\ accessLevel . state_monad$bindS + (state$and_boolS (state_monad$returnS (((accessLevel <> Kernel)))) + ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 : + bool) . + if w__1 then state_monad$seqS + (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : 2 words$word)) (SignalException CpU) + else state_monad$returnS () ))))`; + + +(*val incrementCP0Count : unit -> M unit*) + +val _ = Define ` + ((incrementCP0Count:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . state_monad$bindS + (state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__1 : 6 words$word) . state_monad$bindS + (if (((w__0 = w__1))) then state_monad$returnS TLBIndexMax + else state_monad$bindS + (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : 6 words$word) . + state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBRandom_ref w__3) + (state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__4 : 32 words$word) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii) : 32 words$word))) + (state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__5 : 32 bits) . state_monad$bindS + (state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . state_monad$bindS (state_monad$seqS + (if (((w__5 = w__6))) then state_monad$bindS + (state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 : 8 words$word)) + (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + : 8 words$word))) + else state_monad$returnS () ) + (state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . + let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in state_monad$bindS + (state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . + let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . + let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . + let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . + let erl = ((get_StatusReg_ERL w__12 : 1 words$word)) in + if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))))))))) then + SignalException Interrupt + else state_monad$returnS () )))))))))))))`; + + +(*val decode_failure_of_num : integer -> decode_failure*) + +val _ = Define ` + ((decode_failure_of_num:int -> decode_failure) arg_= + (let l__74 = arg_ in + if (((l__74 = (( 0 : int):ii)))) then No_matching_pattern + else if (((l__74 = (( 1 : int):ii)))) then Unsupported_instruction + else if (((l__74 = (( 2 : int):ii)))) then Illegal_instruction + else Internal_error))`; + + +(*val num_of_decode_failure : decode_failure -> integer*) + +val _ = Define ` + ((num_of_decode_failure:decode_failure -> int) arg_= + ((case arg_ of no_matching_pattern => (( 0 : int): ii) )))`; + + +(*val undefined_decode_failure : unit -> M decode_failure*) + +val _ = Define ` + ((undefined_decode_failure:unit ->(regstate)state_monad$sequential_state ->(((decode_failure),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; + + +(*val Comparison_of_num : integer -> Comparison*) + +val _ = Define ` + ((Comparison_of_num:int -> Comparison) arg_= + (let l__67 = arg_ in + if (((l__67 = (( 0 : int):ii)))) then EQ' + else if (((l__67 = (( 1 : int):ii)))) then NE + else if (((l__67 = (( 2 : int):ii)))) then GE + else if (((l__67 = (( 3 : int):ii)))) then GEU + else if (((l__67 = (( 4 : int):ii)))) then GT' + else if (((l__67 = (( 5 : int):ii)))) then LE + else if (((l__67 = (( 6 : int):ii)))) then LT' + else LTU))`; + + +(*val num_of_Comparison : Comparison -> integer*) + +val _ = Define ` + ((num_of_Comparison:Comparison -> int) arg_= + ((case arg_ of + EQ' => (( 0 : int):ii) + | NE => (( 1 : int):ii) + | GE => (( 2 : int):ii) + | GEU => (( 3 : int):ii) + | GT' => (( 4 : int):ii) + | LE => (( 5 : int):ii) + | LT' => (( 6 : int):ii) + | LTU => (( 7 : int):ii) + )))`; + + +(*val undefined_Comparison : unit -> M Comparison*) + +val _ = Define ` + ((undefined_Comparison:unit ->(regstate)state_monad$sequential_state ->(((Comparison),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; + + +(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) + +val _ = Define ` + ((compare:Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB= + ((case cmp of + EQ' => (valA = valB) + | NE => (valA <> valB) + | GE => zopz0zKzJ_s valA valB + | GEU => zopz0zKzJ_u valA valB + | GT' => zopz0zI_s valB valA + | LE => zopz0zKzJ_s valB valA + | LT' => zopz0zI_s valA valB + | LTU => zopz0zI_u valA valB + )))`; + + +(*val WordType_of_num : integer -> WordType*) + +val _ = Define ` + ((WordType_of_num:int -> WordType) arg_= + (let l__64 = arg_ in + if (((l__64 = (( 0 : int):ii)))) then B + else if (((l__64 = (( 1 : int):ii)))) then H + else if (((l__64 = (( 2 : int):ii)))) then W0 + else D))`; + + +(*val num_of_WordType : WordType -> integer*) + +val _ = Define ` + ((num_of_WordType:WordType -> int) arg_= + ((case arg_ of B => (( 0 : int):ii) | H => (( 1 : int):ii) | W0 => (( 2 : int):ii) | D => (( 3 : int):ii) )))`; + + +(*val undefined_WordType : unit -> M WordType*) + +val _ = Define ` + ((undefined_WordType:unit ->(regstate)state_monad$sequential_state ->(((WordType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [B;H;W0;D]))`; + + +(*val wordWidthBytes : WordType -> integer*) + +val _ = Define ` + ((wordWidthBytes:WordType -> int) w= ((case w of B => (( 1 : int):ii) | H => (( 2 : int):ii) | W0 => (( 4 : int):ii) | D => (( 8 : int):ii) )))`; + + +val _ = Define ` + ((alignment_width:int)= ((( 16 : int):ii)))`; + + +(*val isAddressAligned : mword ty64 -> WordType -> bool*) + +val _ = Define ` + ((isAddressAligned:(64)words$word -> WordType -> bool) addr wordType= + (let a = (lem$w2ui addr) in + (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):ii))) / + alignment_width)))))`; + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1= + (if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then state_monad$bindS + (state_monad$read_regS UART_RVALID_ref : ( 1 words$word) M) (\ rvalid . state_monad$bindS (state_monad$seqS + (state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0] : 1 words$word)) + (state_monad$read_regS UART_RDATA_ref : ( 8 words$word) M)) (\ (w__0 : 8 bits) . + state_monad$returnS ((mask p8_times_n___tv + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec w__0 + ((concat_vec rvalid + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 16 words$word) + : 23 words$word)) + : 24 words$word)) + : 32 words$word)) + : 64 words$word)) + : 'p8_times_n_ words$word)))) + else if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : 64 words$word)))) then + state_monad$returnS ((mask p8_times_n___tv + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; + B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 64 words$word) + : 'p8_times_n_ words$word)) + else state_monad$bindS + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__1 . + state_monad$returnS ((reverse_endianness w__1 : 'p8_times_n_ words$word)))))`; + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1= (state_monad$bindS + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__0 . + state_monad$returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; + + +(*val init_cp0_state : unit -> M unit*) + +val _ = Define ` + ((init_cp0_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; + + +(*val init_cp2_state : unit -> M unit*) + +(*val cp2_next_pc : unit -> M unit*) + +(*val dump_cp2_state : unit -> M unit*) + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((extz_vec m__tv v : 'm words$word)))`; + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((exts_vec m__tv v : 'm words$word)))`; + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +val _ = Define ` + ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l= + (let (one1 : 'n bits) = ((extzv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`; + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= + (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0] : 1 words$word) : 'n words$word))))`; + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j= + (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i)) : 'n words$word)) in + (((and_vec xs m : 'n words$word)) = m)))`; + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +val _ = Define ` + ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + let ys = + ((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l' : 'm words$word)) : 'm words$word)) i' + : 'm words$word)) in + (or_vec ((shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)) ((extzv r__tv ys : 'r words$word)) + : 'r words$word)))`; + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +val _ = Define ` + ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)))`; + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j')) : 'n words$word)) : 'n words$word)) + j' + : 'n words$word)) in + (xs = ys)))`; + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +val _ = Define ` + ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j')) : 'm words$word)) : 'm words$word)) + j' + : 'm words$word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs : 's words$word)) i' : 's words$word)) + ((j' - (( 1 : int):ii))) + : 's words$word)) ((extzv s__tv ys : 's words$word)) + : 's words$word)))`; + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (extzv m__tv xs : 'm words$word)))`; + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) + ((((((int_of_num (words$word_len xs))) - i)) - l)) + : 'n words$word)) ((((int_of_num (words$word_len xs))) - l)) + : 'n words$word)) in + (extsv m__tv xs : 'm words$word)))`; + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_slice:'n words$word -> int -> int -> int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + lem$w2ui xs))`; + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) i + : 'n words$word)) in + lem$w2ui xs))`; + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +val _ = Define ` + ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m= + (let (v : 'n bits) = ((extsv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftr v ((((int_of_num (words$word_len v))) - m)) : 'n words$word)))`; + + +(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) + +val _ = Define ` + ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> TLBEntry -> bool) r vpn2 asid entry= + (let entryValid = ((get_TLBEntry_valid entry : 1 words$word)) in + let entryR = ((get_TLBEntry_r entry : 2 words$word)) in + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let entryVPN = ((get_TLBEntry_vpn2 entry : 27 words$word)) in + let entryASID = ((get_TLBEntry_asid entry : 8 words$word)) in + let entryG = ((get_TLBEntry_g entry : 1 words$word)) in + let (vpnMask : 27 bits) = + ((not_vec ((zero_extend1 (( 27 : int):ii) entryMask : 27 words$word)) : 27 words$word)) in + (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask : 27 words$word)) = ((and_vec entryVPN vpnMask : 27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`; + + +(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) + +val _ = Define ` + ((tlbSearch:(64)words$word ->(regstate)state_monad$sequential_state ->(((((6)words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) VAddr= + (state_monad$catch_early_returnS + (let r = ((subrange_vec_dec VAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)) in + let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)) in state_monad$bindS + (state_monad$liftRS (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . + let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in state_monad$seqS + (state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () + (\ idx unit_var . state_monad$bindS + (state_monad$liftRS (state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) + MR) + else state_monad$returnS () ))) + (state_monad$returnS NONE)))))`; + + +(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +val _ = Define ` + ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + (tlbSearch vAddr : ( ( 6 words$word)option) M) (\ idx . + (case idx of + SOME (idx) => + let i = (lem$w2ui idx) in state_monad$bindS + (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let b__0 = entryMask in state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + state_monad$returnS (( 12 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 14 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 16 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 18 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 20 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 22 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 24 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 26 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + state_monad$returnS (( 28 : int):ii) + else undefined_range (( 12 : int):ii) (( 28 : int):ii)) (\ (evenOddBit : int) . + let isOdd = (access_vec_dec vAddr evenOddBit) in + let ((caps : 1 bits), (capl : 1 bits), (pfn : 24 bits), (d : 1 bits), (v : 1 bits)) = + (if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry : 1 words$word), + (get_TLBEntry_capl1 entry : 1 words$word), + (get_TLBEntry_pfn1 entry : 24 words$word), + (get_TLBEntry_d1 entry : 1 words$word), + (get_TLBEntry_v1 entry : 1 words$word)) + else + ((get_TLBEntry_caps0 entry : 1 words$word), + (get_TLBEntry_capl0 entry : 1 words$word), + (get_TLBEntry_pfn0 entry : 24 words$word), + (get_TLBEntry_d0 entry : 1 words$word), + (get_TLBEntry_v0 entry : 1 words$word))) in + if ((~ ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + : (( 64 words$word # bool)) M) + else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr : (( 64 words$word # bool)) M) + else + let (res : 64 bits) = + ((zero_extend1 (( 64 : int):ii) + ((subrange_subrange_concat + (((((((( 23 : int):ii) - + ((((evenOddBit - (( 12 : int):ii))) - (( 1 : int):ii))))) + + + ((evenOddBit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) pfn + (( 23 : int):ii) ((evenOddBit - (( 12 : int):ii))) vAddr + ((evenOddBit - (( 1 : int):ii))) (( 0 : int):ii) + : 36 words$word)) + : 64 words$word)) in + state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) + | NONE => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + : (( 64 words$word # bool)) M) + ))))`; + + +(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +val _ = Define ` + ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + (getAccessLevel () ) (\ currentAccessLevel . + let compat32 = + (((subrange_vec_dec vAddr (( 61 : int):ii) (( 31 : int):ii) : 31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1] + : 31 words$word)) in + let b__0 = ((subrange_vec_dec vAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)) in + let ((requiredLevel : AccessLevel), (addr : ( 64 bits)option)) = + (if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) of + (T, b__1) => + if (((b__1 = (vec_of_bits [B1;B1] : 2 words$word)))) then (Kernel, NONE) + else if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then (Supervisor, NONE) + else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + else + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + | (g__131, g__132) => (Kernel, NONE) + ) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((subrange_vec_dec vAddr (( 58 : int):ii) (( 0 : int):ii) : 59 words$word)) + : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then (Supervisor, NONE) + else (User, NONE)) in + if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else state_monad$bindS + (case addr of + SOME (a) => state_monad$returnS (a, F) + | NONE => + if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):ii) (( 0 : int):ii) : 62 words$word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else (TLBTranslate2 vAddr accessType : (( 64 words$word # bool)) M) + ) (\ varstup . let ((pa : 64 bits), (c : bool)) = varstup in + if ((((lem$w2ui pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else state_monad$returnS (pa, c)))))`; + + +(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) + +val _ = Define ` + ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + (TLBTranslateC vAddr accessType : (( 64 words$word # bool)) M) (\ varstup . let (addr, c) = varstup in + state_monad$returnS addr)))`; + + +(*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*) + +val _ = Define ` + ((CPtrCmpOp_of_num:int -> CPtrCmpOp) arg_= + (let l__57 = arg_ in + if (((l__57 = (( 0 : int):ii)))) then CEQ + else if (((l__57 = (( 1 : int):ii)))) then CNE + else if (((l__57 = (( 2 : int):ii)))) then CLT + else if (((l__57 = (( 3 : int):ii)))) then CLE + else if (((l__57 = (( 4 : int):ii)))) then CLTU + else if (((l__57 = (( 5 : int):ii)))) then CLEU + else if (((l__57 = (( 6 : int):ii)))) then CEXEQ + else CNEXEQ))`; + + +(*val num_of_CPtrCmpOp : CPtrCmpOp -> integer*) + +val _ = Define ` + ((num_of_CPtrCmpOp:CPtrCmpOp -> int) arg_= + ((case arg_ of + CEQ => (( 0 : int):ii) + | CNE => (( 1 : int):ii) + | CLT => (( 2 : int):ii) + | CLE => (( 3 : int):ii) + | CLTU => (( 4 : int):ii) + | CLEU => (( 5 : int):ii) + | CEXEQ => (( 6 : int):ii) + | CNEXEQ => (( 7 : int):ii) + )))`; + + +(*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*) + +val _ = Define ` + ((undefined_CPtrCmpOp:unit ->(regstate)state_monad$sequential_state ->(((CPtrCmpOp),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`; + + +(*val ClearRegSet_of_num : integer -> ClearRegSet*) + +val _ = Define ` + ((ClearRegSet_of_num:int -> ClearRegSet) arg_= + (let l__54 = arg_ in + if (((l__54 = (( 0 : int):ii)))) then GPLo + else if (((l__54 = (( 1 : int):ii)))) then GPHi + else if (((l__54 = (( 2 : int):ii)))) then CLo + else CHi))`; + + +(*val num_of_ClearRegSet : ClearRegSet -> integer*) + +val _ = Define ` + ((num_of_ClearRegSet:ClearRegSet -> int) arg_= + ((case arg_ of GPLo => (( 0 : int):ii) | GPHi => (( 1 : int):ii) | CLo => (( 2 : int):ii) | CHi => (( 3 : int):ii) )))`; + + +(*val undefined_ClearRegSet : unit -> M ClearRegSet*) + +val _ = Define ` + ((undefined_ClearRegSet:unit ->(regstate)state_monad$sequential_state ->(((ClearRegSet),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [GPLo;GPHi;CLo;CHi]))`; + + +(*val undefined_CapStruct : unit -> M CapStruct*) + +val _ = Define ` + ((undefined_CapStruct:unit ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__0 : bool) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M) (\ (w__1 : 8 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):ii) : ( 24 words$word) M) (\ (w__2 : 24 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__3 : 16 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):ii) : ( 4 words$word) M) (\ (w__4 : 4 bits) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__5 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__6 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__7 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__8 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__9 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__10 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__11 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__12 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__13 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__14 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__15 : bool) . state_monad$bindS + (state_monad$undefined_boolS () ) (\ (w__16 : bool) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__17 : 64 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__18 : 64 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__19 : 64 bits) . + state_monad$returnS (<| CapStruct_tag := w__0; + CapStruct_padding := w__1; + CapStruct_otype := w__2; + CapStruct_uperms := w__3; + CapStruct_perm_reserved11_14 := w__4; + CapStruct_access_system_regs := w__5; + CapStruct_permit_unseal := w__6; + CapStruct_permit_ccall := w__7; + CapStruct_permit_seal := w__8; + CapStruct_permit_store_local_cap := w__9; + CapStruct_permit_store_cap := w__10; + CapStruct_permit_load_cap := w__11; + CapStruct_permit_store := w__12; + CapStruct_permit_load := w__13; + CapStruct_permit_execute := w__14; + CapStruct_global := w__15; + CapStruct_sealed := w__16; + CapStruct_address := w__17; + CapStruct_base := w__18; + CapStruct_length := w__19 |>)))))))))))))))))))))))`; + + +val _ = Define ` +((default_cap:CapStruct)= + (<| CapStruct_tag := T; + CapStruct_padding := ((zeros0 (( 8 : int):ii) () : 8 words$word)); + CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word)); + CapStruct_uperms := ((ones (( 16 : int):ii) () : 16 words$word)); + CapStruct_perm_reserved11_14 := ((ones (( 4 : int):ii) () : 4 words$word)); + CapStruct_access_system_regs := T; + CapStruct_permit_unseal := T; + CapStruct_permit_ccall := T; + CapStruct_permit_seal := T; + CapStruct_permit_store_local_cap := T; + CapStruct_permit_store_cap := T; + CapStruct_permit_load_cap := T; + CapStruct_permit_store := T; + CapStruct_permit_load := T; + CapStruct_permit_execute := T; + CapStruct_global := T; + CapStruct_sealed := F; + CapStruct_address := ((zeros0 (( 64 : int):ii) () : 64 words$word)); + CapStruct_base := ((zeros0 (( 64 : int):ii) () : 64 words$word)); + CapStruct_length := + ((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 64 words$word)) |>))`; + + +val _ = Define ` +((null_cap_bits:(256)words$word)= ((capStructToMemBits256 null_cap : 256 words$word)))`; + + +(*val capStructToMemBits : CapStruct -> mword ty256*) + +val _ = Define ` + ((capStructToMemBits:CapStruct ->(256)words$word) cap= + ((xor_vec ((capStructToMemBits256 cap : 256 words$word)) null_cap_bits : 256 words$word)))`; + + +(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*) + +val _ = Define ` + ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b= + ((concat_vec ((bool_to_bits tag : 1 words$word)) ((xor_vec b null_cap_bits : 256 words$word)) + : 257 words$word)))`; + + +(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*) + +val _ = Define ` + ((setCapPerms:CapStruct ->(31)words$word -> CapStruct) cap perms= + ((cap with<| + CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):ii) (( 15 : int):ii) : 16 words$word)); CapStruct_perm_reserved11_14 := + ((subrange_vec_dec perms (( 14 : int):ii) (( 11 : int):ii) : 4 words$word)); CapStruct_access_system_regs := + ((bit_to_bool ((access_vec_dec perms (( 10 : int):ii))))); CapStruct_permit_unseal := + ((bit_to_bool ((access_vec_dec perms (( 9 : int):ii))))); CapStruct_permit_ccall := + ((bit_to_bool ((access_vec_dec perms (( 8 : int):ii))))); CapStruct_permit_seal := + ((bit_to_bool ((access_vec_dec perms (( 7 : int):ii))))); CapStruct_permit_store_local_cap := + ((bit_to_bool ((access_vec_dec perms (( 6 : int):ii))))); CapStruct_permit_store_cap := + ((bit_to_bool ((access_vec_dec perms (( 5 : int):ii))))); CapStruct_permit_load_cap := + ((bit_to_bool ((access_vec_dec perms (( 4 : int):ii))))); CapStruct_permit_store := + ((bit_to_bool ((access_vec_dec perms (( 3 : int):ii))))); CapStruct_permit_load := + ((bit_to_bool ((access_vec_dec perms (( 2 : int):ii))))); CapStruct_permit_execute := + ((bit_to_bool ((access_vec_dec perms (( 1 : int):ii))))); CapStruct_global := + ((bit_to_bool ((access_vec_dec perms (( 0 : int):ii)))))|>)))`; + + +(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*) + +val _ = Define ` + ((sealCap:CapStruct ->(24)words$word -> bool#CapStruct) cap otype= (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`; + + +(*val getCapTop : CapStruct -> integer*) + +val _ = Define ` + ((getCapTop:CapStruct -> int) c= (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`; + + +(*val getCapOffset : CapStruct -> integer*) + +val _ = Define ` + ((getCapOffset:CapStruct -> int) c= + (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base)))) + ((pow2 (( 64 : int):ii)))))`; + + +(*val getCapLength : CapStruct -> integer*) + +val _ = Define ` + ((getCapLength:CapStruct -> int) c= (lem$w2ui c.CapStruct_length))`; + + +(*val getCapCursor : CapStruct -> integer*) + +val _ = Define ` + ((getCapCursor:CapStruct -> int) c= (lem$w2ui c.CapStruct_address))`; + + +(* +\function{incCapOffset} is the same as \function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). + *) +(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +val _ = Define ` + ((incCapOffset:CapStruct ->(64)words$word -> bool#CapStruct) c delta= + (let (newAddr : 64 bits) = ((add_vec c.CapStruct_address delta : 64 words$word)) in + (T, (c with<| CapStruct_address := newAddr|>))))`; + + +(* +Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. + *) +(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*) + +val _ = Define ` + ((setCapBounds:CapStruct ->(64)words$word ->(65)words$word -> bool#CapStruct) cap base top= + (let (length : 65 bits) = + ((sub_vec top ((concat_vec (vec_of_bits [B0] : 1 words$word) base : 65 words$word)) : 65 words$word)) in + (T, + (cap with<| + CapStruct_base := base; CapStruct_length := + ((subrange_vec_dec length (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)); CapStruct_address := base|>))))`; + + +(*val undefined_ast : unit -> M ast*) + +val _ = Define ` + ((undefined_ast:unit ->(regstate)state_monad$sequential_state ->(((ast),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__0 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__1 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__2 : 16 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__3 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__4 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__5 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__6 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__7 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__8 : 16 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__9 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__10 : 5 words$word) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__11 : 5 words$word) . state_monad$bindS + (undefined_bitvector + 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(w__317,w__318,w__319);CBZ (w__320,w__321,w__322);CJALR (w__323,w__324,w__325);CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332);CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339);CSC (w__340,w__341,w__342,w__343,w__344,w__345);CLC (w__346,w__347,w__348,w__349,w__350);C2Dump w__351;RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +(*val execute : ast -> M unit*) + +(*val decode : mword ty32 -> maybe ast*) + +val _ = Define ` +((DDC:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((IDC:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((KR1C:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((KR2C:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((KCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))`; + + +val _ = Define ` +((KDC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((EPCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((CapRegs:(((regstate),(register_value),(CapReg))register_ref)list)= + ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref; + C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref;C10_ref;C09_ref;C08_ref; + C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`; + + +val _ = Define ` + ((max_otype:int)= (MAX0 (( 24 : int):ii)))`; + + +val _ = Define ` + ((have_cp2:bool)= T)`; + + +(* +This function reads a given capability register and returns its contents converted to a CapStruct. +*) +(*val readCapReg : mword ty5 -> M CapStruct*) + +val _ = Define ` + ((readCapReg:(5)words$word ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n= + (let i = (lem$w2ui n) in state_monad$bindS + (state_monad$read_regS ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) + : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + state_monad$returnS ((capRegToCapStruct w__0)))))`; + + +(*val writeCapReg : mword ty5 -> CapStruct -> M unit*) + +val _ = Define ` + ((writeCapReg:(5)words$word -> CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n cap= + (let i = (lem$w2ui n) in + state_monad$write_regS + ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) + ((capStructToCapReg cap : 257 words$word))))`; + + +(*val CapEx_of_num : integer -> CapEx*) + +val _ = Define ` + ((CapEx_of_num:int -> CapEx) arg_= + (let l__32 = arg_ in + if (((l__32 = (( 0 : int):ii)))) then CapEx_None + else if (((l__32 = (( 1 : int):ii)))) then CapEx_LengthViolation + else if (((l__32 = (( 2 : int):ii)))) then CapEx_TagViolation + else if (((l__32 = (( 3 : int):ii)))) then CapEx_SealViolation + else if (((l__32 = (( 4 : int):ii)))) then CapEx_TypeViolation + else if (((l__32 = (( 5 : int):ii)))) then CapEx_CallTrap + else if (((l__32 = (( 6 : int):ii)))) then CapEx_ReturnTrap + else if (((l__32 = (( 7 : int):ii)))) then CapEx_TSSUnderFlow + else if (((l__32 = (( 8 : int):ii)))) then CapEx_UserDefViolation + else if (((l__32 = (( 9 : int):ii)))) then CapEx_TLBNoStoreCap + else if (((l__32 = (( 10 : int):ii)))) then CapEx_InexactBounds + else if (((l__32 = (( 11 : int):ii)))) then CapEx_GlobalViolation + else if (((l__32 = (( 12 : int):ii)))) then CapEx_PermitExecuteViolation + else if (((l__32 = (( 13 : int):ii)))) then CapEx_PermitLoadViolation + else if (((l__32 = (( 14 : int):ii)))) then CapEx_PermitStoreViolation + else if (((l__32 = (( 15 : int):ii)))) then CapEx_PermitLoadCapViolation + else if (((l__32 = (( 16 : int):ii)))) then CapEx_PermitStoreCapViolation + else if (((l__32 = (( 17 : int):ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((l__32 = (( 18 : int):ii)))) then CapEx_PermitSealViolation + else if (((l__32 = (( 19 : int):ii)))) then CapEx_AccessSystemRegsViolation + else if (((l__32 = (( 20 : int):ii)))) then CapEx_PermitCCallViolation + else if (((l__32 = (( 21 : int):ii)))) then CapEx_AccessCCallIDCViolation + else CapEx_PermitUnsealViolation))`; + + +(*val num_of_CapEx : CapEx -> integer*) + +val _ = Define ` + ((num_of_CapEx:CapEx -> int) arg_= + ((case arg_ of + CapEx_None => (( 0 : int):ii) + | CapEx_LengthViolation => (( 1 : int):ii) + | CapEx_TagViolation => (( 2 : int):ii) + | CapEx_SealViolation => (( 3 : int):ii) + | CapEx_TypeViolation => (( 4 : int):ii) + | CapEx_CallTrap => (( 5 : int):ii) + | CapEx_ReturnTrap => (( 6 : int):ii) + | CapEx_TSSUnderFlow => (( 7 : int):ii) + | CapEx_UserDefViolation => (( 8 : int):ii) + | CapEx_TLBNoStoreCap => (( 9 : int):ii) + | CapEx_InexactBounds => (( 10 : int):ii) + | CapEx_GlobalViolation => (( 11 : int):ii) + | CapEx_PermitExecuteViolation => (( 12 : int):ii) + | CapEx_PermitLoadViolation => (( 13 : int):ii) + | CapEx_PermitStoreViolation => (( 14 : int):ii) + | CapEx_PermitLoadCapViolation => (( 15 : int):ii) + | CapEx_PermitStoreCapViolation => (( 16 : int):ii) + | CapEx_PermitStoreLocalCapViolation => (( 17 : int):ii) + | CapEx_PermitSealViolation => (( 18 : int):ii) + | CapEx_AccessSystemRegsViolation => (( 19 : int):ii) + | CapEx_PermitCCallViolation => (( 20 : int):ii) + | CapEx_AccessCCallIDCViolation => (( 21 : int):ii) + | CapEx_PermitUnsealViolation => (( 22 : int):ii) + )))`; + + +(*val undefined_CapEx : unit -> M CapEx*) + +val _ = Define ` + ((undefined_CapEx:unit ->(regstate)state_monad$sequential_state ->(((CapEx),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (internal_pick + [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`; + + +(*val CapExCode : CapEx -> mword ty8*) + +val _ = Define ` + ((CapExCode:CapEx ->(8)words$word) ex= + ((case ex of + CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) + | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) + | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) + | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : 8 words$word) + | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word) + | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) + | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) + | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) + | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0] : 8 words$word) + | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1] : 8 words$word) + | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1] : 8 words$word) + | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0] : 8 words$word) + | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1] : 8 words$word) + | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0] : 8 words$word) + | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1] : 8 words$word) + | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) + | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1] : 8 words$word) + | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0] : 8 words$word) + | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1] : 8 words$word) + )))`; + + +(*val undefined_CapCauseReg : unit -> M CapCauseReg*) + +val _ = Define ` + ((undefined_CapCauseReg:unit ->(regstate)state_monad$sequential_state ->(((CapCauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__0 : 16 words$word) . + internal_pick [Mk_CapCauseReg w__0])))`; + + +val _ = Define ` + ((get_CapCauseReg:CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))= v)`; + + +val _ = Define ` + ((set_CapCauseReg:((regstate),(register_value),(CapCauseReg))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_CapCauseReg v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +val _ = Define ` + ((set_CapCauseReg_ExcCode:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . + let r = ((get_CapCauseReg w__0 : 16 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 16 words$word)) in + state_monad$write_regS r_ref (Mk_CapCauseReg r))))`; + + +val _ = Define ` + ((update_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x= + (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 16 words$word))))`; + + +(*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) + +val _ = Define ` + ((get_CapCauseReg_RegNum:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_CapCauseReg_RegNum:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . + let r = ((get_CapCauseReg w__0 : 16 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 16 words$word)) in + state_monad$write_regS r_ref (Mk_CapCauseReg r))))`; + + +(*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) + +val _ = Define ` + ((update_CapCauseReg_RegNum:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x= + (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 16 words$word))))`; + + +(*val execute_branch_pcc : CapStruct -> M unit*) + +val _ = Define ` + ((execute_branch_pcc:CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) newPCC= (state_monad$seqS (state_monad$seqS + (state_monad$write_regS + delayedPC_ref + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapOffset newPCC)) : 64 words$word))) + (state_monad$write_regS delayedPCC_ref ((capStructToCapReg newPCC : 257 words$word)))) + (state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + + +(*val ERETHook : unit -> M unit*) + +val _ = Define ` + ((ERETHook:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS C31_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS nextPCC_ref w__0) + (state_monad$read_regS C31_ref : ( 257 words$word) M)) (\ (w__1 : CapReg) . state_monad$write_regS delayedPCC_ref w__1))))`; + + +(*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) + +val _ = Define ` + ((raise_c2_exception8:CapEx ->(8)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum= (state_monad$seqS (state_monad$seqS + (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx : 8 words$word))) + (set_CapCauseReg_RegNum CapCause_ref regnum)) + (let mipsEx = + (if ((((((capEx = CapEx_CallTrap))) \/ (((capEx = CapEx_ReturnTrap)))))) then C2Trap + else C2E) in + SignalException mipsEx)))`; + + +(*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*) + +val _ = Define ` + ((raise_c2_exception:CapEx ->(5)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum= + (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) regnum : 8 words$word)) in + if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then + raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 + else raise_c2_exception8 capEx reg8))`; + + +(*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*) + +val _ = Define ` + ((raise_c2_exception_noreg:CapEx ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx= + (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)))`; + + +(*val pcc_access_system_regs : unit -> M bool*) + +val _ = Define ` + ((pcc_access_system_regs:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + let pcc = (capRegToCapStruct w__0) in + state_monad$returnS pcc.CapStruct_access_system_regs)))`; + + +(* +The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. + *) +(*val register_inaccessible : mword ty5 -> M bool*) + +val _ = Define ` + ((register_inaccessible:(5)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r= + (state$or_boolS + (state$and_boolS (state_monad$returnS (((r = IDC)))) + ( state_monad$bindS(state_monad$read_regS inCCallDelay_ref : ( 1 words$word) M) (\ (w__0 : 1 words$word) . + state_monad$returnS ((bits_to_bool w__0))))) + (state$and_boolS + (state_monad$returnS ((((((r = KR1C))) \/ ((((((r = KR2C))) \/ ((((((r = KDC))) \/ ((((((r = KCC))) \/ (((r = EPCC)))))))))))))))) + ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__2 : bool) . state_monad$returnS ((~ w__2)))))))`; + + +(*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*) + +val _ = Define ` + ((MEMr_tagged:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr= (state_monad$bindS (state_monad$seqS + (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . state_monad$bindS + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . + state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; + + +(*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) + +val _ = Define ` + ((MEMr_tagged_reserve:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr= (state_monad$bindS (state_monad$seqS + (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . state_monad$bindS + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . + state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; + + +(*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) + +val _ = Define ` + ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data= (state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) + (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`; + + +(*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) + +val _ = Define ` + ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data= (state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (MEMea_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) + (MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (\ success . state_monad$seqS + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else state_monad$returnS () ) (state_monad$returnS success))))`; + + +val _ = Define ` + ((cap_addr_mask:(64)words$word)= + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((((pow2 (( 64 : int):ii))) - cap_size)) + : 64 words$word)))`; + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +val _ = Define ` + ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data= + (let ledata = ((reverse_endianness data : 'p8_times_n_ words$word)) in + if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then state_monad$seqS + (state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) + (state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B1] : 1 words$word)) + else state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) + ((size1 - (( 1 : int):ii))) + : 64 words$word)) + : 64 words$word)) cap_addr_mask + : 64 words$word))))) "") + (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) + (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F)))`; + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) + +val _ = Define ` + ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data= (state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) + ((size1 - (( 1 : int):ii))) + : 64 words$word)) + : 64 words$word)) cap_addr_mask + : 64 words$word))))) "") + (MEMea_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) + (MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))) (\ success . state_monad$seqS + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F + else state_monad$returnS () ) + (state_monad$returnS success))))`; + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +val _ = Define ` + ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr accessType width= + (let capno = ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)) in state_monad$bindS + (readCapReg capno) (\ cap . state_monad$seqS (state_monad$seqS + (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno + else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno + else state_monad$returnS () ) + (case accessType of + Instruction => + if ((~ cap.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation capno + else state_monad$returnS () + | LoadData => + if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno + else state_monad$returnS () + | StoreData => + if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno + else state_monad$returnS () + )) + (let cursor = (getCapCursor cap) in + let vAddr = (((cursor + ((lem$w2ui addr)))) % ((pow2 (( 64 : int):ii)))) in + let size1 = (wordWidthBytes width) in + let base = (getCapBase cap) in + let top = (getCapTop cap) in + if ((((vAddr + size1)) > top)) then + (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) M) + else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) M) + else state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word))))))`; + + +(*val TranslatePC : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((TranslatePC:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr= (state_monad$bindS (state_monad$seqS + (incrementCP0Count () ) + (state_monad$read_regS PCC_ref : ( 257 words$word) M)) (\ (w__0 : 257 words$word) . + let pcc = (capRegToCapStruct w__0) in + let base = (getCapBase pcc) in + let top = (getCapTop pcc) in + let absPC = (base + ((lem$w2ui vAddr))) in + if (((((absPC % (( 4 : int):ii))) <> (( 0 : int):ii)))) then + (SignalExceptionBadAddr AdEL + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) absPC : 64 words$word)) + : ( 64 words$word) M) + else if ((~ pcc.CapStruct_tag)) then + (raise_c2_exception_noreg CapEx_TagViolation : ( 64 words$word) M) + else if ((((absPC + (( 4 : int):ii))) > top)) then + (raise_c2_exception_noreg CapEx_LengthViolation : ( 64 words$word) M) + else + (TLBTranslate ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) absPC : 64 words$word)) + Instruction + : ( 64 words$word) M))))`; + + +(* +All capability instrucitons must first check that the capability +co-processor is enabled using the following function that raises a +co-processor unusable exception if a CP0Status.CU2 is not set. This +allows the operating system to only save and restore the full +capability context for processes that use capabilities. +*) +(*val checkCP2usable : unit -> M unit*) + +val _ = Define ` + ((checkCP2usable:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 2 : int):ii))))))) then state_monad$seqS + (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : 2 words$word)) (SignalException CpU) + else state_monad$returnS () )))`; + + +val _ = Define ` + ((init_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (let defaultBits = ((capStructToCapReg default_cap : 257 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS PCC_ref defaultBits) + (state_monad$write_regS nextPCC_ref defaultBits)) + (state_monad$write_regS delayedPCC_ref defaultBits)) + (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . + let idx = ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) in + writeCapReg idx default_cap))))`; + + +val _ = Define ` + ((cp2_next_pc:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS nextPCC_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS PCC_ref w__0) + (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__1 : 1 words$word) . + if ((bits_to_bool w__1)) then state_monad$bindS + (state_monad$read_regS delayedPCC_ref : ( 257 words$word) M) (\ (w__2 : CapReg) . + state_monad$write_regS nextPCC_ref w__2) + else state_monad$write_regS inCCallDelay_ref (vec_of_bits [B0] : 1 words$word)))))`; + + +(*val capToString : CapStruct -> M string*) + +val _ = Define ` + ((capToString:CapStruct ->(regstate)state_monad$sequential_state ->(((string),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cap= (state_monad$seqS + (skip () ) + (state_monad$returnS ((STRCAT " t:" + ((STRCAT (if cap.CapStruct_tag then "1" else "0") + ((STRCAT " s:" + ((STRCAT (if cap.CapStruct_sealed then "1" else "0") + ((STRCAT " perms:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((getCapPerms cap : 31 words$word)) + : 32 words$word)))) + ((STRCAT " type:" + ((STRCAT ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype)) + ((STRCAT " offset:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):ii) : 64 itself)) + ((getCapOffset cap)) + : 64 words$word)))) + ((STRCAT " base:" + ((STRCAT + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):ii) + : 64 itself)) + ((getCapBase cap)) + : 64 words$word)))) + ((STRCAT " length:" + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 : int):ii) + : 64 itself)) + ((int_min ((getCapLength cap)) + ((MAX0 (( 64 : int):ii))))) + : 64 words$word)))))))))))))))))))))))))))))))))`; + + +val _ = Define ` + ((dump_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . state_monad$bindS + (capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . + let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in + (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . state_monad$bindS + (readCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word))) (\ (w__2 : + CapStruct) . state_monad$bindS + (capToString w__2) (\ (w__3 : string) . + state_monad$returnS (let _ = + (prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int + instance_Show_Show_Num_integer_dict i)) w__3))))) in + () )))))))))`; + + +(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) + +val _ = Define ` + ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign= + (if sign then (sign_extend1 (( 64 : int):ii) memResult : 64 words$word) + else (zero_extend1 (( 64 : int):ii) memResult : 64 words$word)))`; + + +(*val TLBWriteEntry : mword ty6 -> M unit*) + +val _ = Define ` + ((TLBWriteEntry:(6)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx= (state_monad$bindS + (state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ pagemask . + let b__0 = pagemask in state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) + then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + state_monad$returnS () + else SignalException MCheck) + (let i = (lem$w2ui idx) in + let entry = (access_list_dec TLBEntries i) in state_monad$bindS (state_monad$seqS + (set_TLBEntry_pagemask entry pagemask) + (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 : 2 words$word))) + (state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 : 27 words$word))) + (state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 : 8 words$word))) + (state$and_boolS + ( state_monad$bindS(state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . + state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))))) + ( state_monad$bindS(state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . + state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word)))))))) (\ (w__5 : bool) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_TLBEntry_g entry ((bool_to_bits w__5 : 1 words$word))) + (set_TLBEntry_valid entry ((cast_unit_vec0 B1 : 1 words$word)))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 : 1 words$word))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 : 1 words$word))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 : 24 words$word))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 : 3 words$word))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 : 1 words$word))) + (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 : 1 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 : 1 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 : 1 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 : 24 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 : 3 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 : 1 words$word))) + (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 : 1 words$word))))))))))))))))))))))`; + + +val _ = Define ` + ((decode:(32)words$word ->(ast)option) v__0= + (if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (DADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (DADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DADD (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (ADD (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (ADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSUB (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SUB0 (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (AND (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ANDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (OR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ORI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (NOR (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (XOR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (XORI (rs,rt,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LUI (rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSLL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRA32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLT (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SLTI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLTU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SLTIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MOVN (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MOVZ (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MFHI rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MFLO rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : 21 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (MTHI rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : 21 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (MTLO rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MUL (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DMULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DMULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MADD (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MADDU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MSUB (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MSUBU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DIV0 (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DIVU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DDIV (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DDIVU (rs,rt)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii) : 26 words$word)) in + SOME (J offset) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii) : 26 words$word)) in + SOME (JAL offset) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 11 : int):ii) : 10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (JR rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (JALR (rs,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,T)) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B0;B0;B1;B1;B0;B0] + : 32 words$word)))) then + SOME (SYSCALL_THREAD_START () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + SOME (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then + SOME (BREAK () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0] + : 32 words$word)))) then + SOME (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LTU)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (B,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (B,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (H,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (H,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (D,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,T,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (D,F,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (B,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (H,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (W0,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (D,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (W0,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (D,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CACHE (base,op,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (PREF (base,op,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then + SOME (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,T)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B0] + : 32 words$word)))) then + SOME (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B1;B0] + : 32 words$word)))) then + SOME (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1] + : 32 words$word)))) then + SOME (TLBR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : 11 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (RDHWR (rt,rd)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B1;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (ERET () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetPerm (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetType (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetBase (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetLen (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetTag (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetSealed (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) + then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (CGetCause rd) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)))) then + SOME (CReturn () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetOffset (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetCause rt) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CAndPerm (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CToPtr (rd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CNE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CLEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,ct,CNEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CIncOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetBounds (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CClearTag (cd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CFromPtr (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CCheckPerm (cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CCheckType (cs,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CUnseal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CJALR (cd,cb,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (CGetCause rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (CSetCause rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (CGetPCC cd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CCheckPerm (cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CCheckType (cs,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CClearTag (cd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CJALR (cd,cb,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetPerm (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetType (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetBase (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetLen (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetTag (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetSealed (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetOffset (rd,cb)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetPCCSetOffset (cd,rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (sel : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CReadHwr (cd,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (sel : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CWriteHwr (cb,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (sel : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CGetAddr (cb,sel)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CUnseal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CAndPerm (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetOffset (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetBounds (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSetBoundsExact (cd,cs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CIncOffset (cd,cb,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CBuildCap (cd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CCopyType (cd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CCSeal (cd,cs,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CToPtr (rd,cb,ct)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CFromPtr (cd,cb,rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSub (rt,cb,cs)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,rs,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CMOVX (cd,cs,rs,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CNE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CLEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (cs : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CPtrCmp (rd,cb,cs,CNEXEQ)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (ct : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CTestSubset (rd,cb,ct)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CBX (cd,imm,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CBX (cd,imm,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CBZ (cd,imm,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CBZ (cd,imm,T)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1] + : 32 words$word)))) then + SOME (CReturn () ) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1] : 11 words$word)))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (selector : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in + SOME (CCall (cs,cb,selector)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 16 words$word)))) then + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ClearRegs (GPLo,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1] : 16 words$word)))) then + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ClearRegs (GPHi,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0] : 16 words$word)))) then + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ClearRegs (CLo,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1] : 16 words$word)))) then + let (imm : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ClearRegs (CHi,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (imm : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in + SOME (CIncOffsetImmediate (cd,cb,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0] : 11 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (imm : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in + SOME (CSetBoundsImmediate (cd,cb,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,T,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CLoad (rd,cb,rt,offset,F,D,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),F,B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),T,B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),F,H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),T,H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),F,W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),T,W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0] + : 8 words$word),F,D,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,B,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,H,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,W0,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 8 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) in + SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,D,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0; + B0;B0;B0] + : 8 words$word),B,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0; + B0;B0;B0] + : 8 words$word),H,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0; + B0;B0;B0] + : 8 words$word),W0,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0; + B0;B0;B0] + : 8 words$word),D,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word)))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in + SOME (CSC (cs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then + let (cs : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (CSC (cs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 11 words$word),T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (offset : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in + SOME (CLC (cd,cb,rt,offset,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 11 words$word))))))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : 11 words$word),T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 16 words$word))))))) + then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (C2Dump rt) + else SOME (RI () )))`; + + +(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((xor_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_WAIT : unit -> M unit*) + +val _ = Define ` + ((execute_WAIT:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__121= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS nextPC_ref w__0)))`; + + +(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) + +val _ = Define ` + ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt cmp= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else state_monad$returnS () ))))`; + + +(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) + +val _ = Define ` + ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + let (imm_val : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in + let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else state_monad$returnS () )))`; + + +(*val execute_TLBWR : unit -> M unit*) + +val _ = Define ` + ((execute_TLBWR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__125= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBWI : unit -> M unit*) + +val _ = Define ` + ((execute_TLBWI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__124= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBR : unit -> M unit*) + +val _ = Define ` + ((execute_TLBR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__126= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . + let i = (lem$w2ui w__0) in state_monad$bindS + (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) + (set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry : 2 words$word)))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry : 8 words$word)))) + (set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry : 1 words$word)))) + (set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry : 1 words$word)))) + (set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry : 24 words$word)))) + (set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry : 3 words$word)))) + (set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry : 1 words$word)))) + (set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry : 1 words$word)))) + (set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry : 1 words$word)))) + (set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry : 1 words$word)))) + (set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry : 1 words$word)))) + (set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry : 24 words$word)))) + (set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry : 3 words$word)))) + (set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry : 1 words$word)))) + (set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry : 1 words$word)))) + (set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry : 1 words$word)))))))`; + + +(*val execute_TLBP : unit -> M unit*) + +val _ = Define ` + ((execute_TLBP:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__127= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . state_monad$bindS + (tlbSearch ((get_TLBEntryHiReg w__0 : 64 words$word)) : ( ( 6 words$word)option) M) (\ result . + (case result of + SOME (idx) => state_monad$seqS + (state_monad$write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (state_monad$write_regS TLBIndex_ref idx) + | NONE => state_monad$seqS + (state_monad$write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) + )))))`; + + +(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width conditional base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData width + : ( 64 words$word) M) (\ (vAddr : 64 bits) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . + if conditional then state_monad$bindS + (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . state_monad$bindS + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 : int):ii) + ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 : int):ii) + ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + | W0 => + MEMw_conditional_wrapper pAddr (( 4 : int):ii) + ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rt_val + ) + else state_monad$returnS F) (\ (success : bool) . + wGPR rt ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + | H => MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + | W0 => MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_wrapper pAddr (( 8 : int):ii) rt_val + )))))))`; + + +(*val execute_SYSCALL_THREAD_START : unit -> unit*) + +val _ = Define ` + ((execute_SYSCALL_THREAD_START:unit -> unit) g__117= () )`; + + +(*val execute_SYSCALL : unit -> M unit*) + +val _ = Define ` + ((execute_SYSCALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__119= (SignalException Sys))`; + + +(*val execute_SYNC : unit -> M unit*) + +val _ = Define ` + ((execute_SYNC:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__122= (MEM_sync () ))`; + + +(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData W0 + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . + let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__12 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + if (((b__12 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + else if (((b__12 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + else if (((b__12 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + else MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))))))))`; + + +(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData W0 + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__8 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + if (((b__8 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if (((b__8 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + else if (((b__8 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word))))))))`; + + +(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 : int):ii) + ((sub_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (temp33 : 33 bits) = + ((sub_vec + ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + if ((NotWordVal temp)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + if ((NotWordVal temp)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + if ((NotWordVal temp)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + if ((NotWordVal temp)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + wGPR rd + ((zero_extend1 (( 64 : int):ii) + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + let (immext : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in + wGPR rt + ((zero_extend1 (( 64 : int):ii) + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= + (let imm_val = (integer_word$w2i imm) in state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs_val = (integer_word$w2i w__0) in + wGPR rt + ((zero_extend1 (( 64 : int):ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd + ((zero_extend1 (( 64 : int):ii) + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData D + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) in + let b__40 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + if (((b__40 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + else if (((b__40 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + else if (((b__40 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + else MEMw_wrapper wordAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))))))))`; + + +(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData D + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__32 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + if (((b__32 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + else if (((b__32 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + else if (((b__32 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word))))))))`; + + +(*val execute_RI : unit -> M unit*) + +val _ = Define ` + ((execute_RI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__130= (SignalException ResI))`; + + +(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd= (state_monad$bindS + (getAccessLevel () ) (\ accessLevel . + let (haveAccessLevel : bool) = (accessLevel = Kernel) in state_monad$bindS + (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))) in + let rdi = (lem$w2ui rd) in state_monad$bindS + (state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in state_monad$seqS + (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI + else state_monad$returnS () ) + (let b__146 = rd in state_monad$bindS + (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then + state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) then + state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then state_monad$bindS + (state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + state_monad$returnS ((zero_extend1 (( 64 : int):ii) w__2 : 64 words$word))) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) then + state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then + (state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + else (SignalException ResI : ( 64 words$word) M)) (\ (temp : 64 bits) . + wGPR rt temp)))))))`; + + +(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) + +val _ = Define ` + ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm= () )`; + + +(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((or_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 : 64 words$word)) : 64 words$word))))))`; + + +(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 bits) . state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))`; + + +(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 bits) . state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))`; + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . + let (result : 64 bits) = + ((sign_extend1 (( 64 : int):ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (w__1 : 64 words$word) . + wGPR rd w__1)))))`; + + +(*val execute_MTLO : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MTLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS LO_ref w__0)))`; + + +(*val execute_MTHI : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MTHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS HI_ref w__0)))`; + + +(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +val _ = Define ` + ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (rGPR rt : ( 64 words$word) M)) (\ reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$write_regS TLBIndex_ref + ((mask (( 6 : int): ii) reg_val : 6 words$word)) else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS () else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg TLBEntryLo0_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg TLBEntryLo1_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 : int): ii) (( 23 : int): ii) : 41 words$word)) + else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + state_monad$write_regS CP0UserLocal_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$write_regS TLBPageMask_ref + ((subrange_vec_dec reg_val (( 28 : int): ii) + (( 13 : int): ii) : 16 words$word)) else + if ((((((b__108 = + (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$seqS + (state_monad$write_regS TLBWired_ref + ((mask (( 6 : int): ii) reg_val : 6 words$word))) + (state_monad$write_regS TLBRandom_ref TLBIndexMax) else + if ((((((b__108 = + (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) + /\ + (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$write_regS CP0HWREna_ref + ((concat_vec + ((subrange_vec_dec reg_val (( 31 : int): ii) + (( 29 : int): ii) : 3 words$word)) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0] : 25 words$word) + ((subrange_vec_dec reg_val (( 3 : int): ii) + (( 0 : int): ii) : 4 words$word)) + : 29 words$word)) : 32 words$word)) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS () else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$write_regS CP0Count_ref + ((subrange_vec_dec reg_val (( 31 : int): ii) + (( 0 : int): ii) : 32 words$word)) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$seqS + (state_monad$seqS + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val + (( 63 : int): ii) (( 62 : int): ii) : 2 words$word))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val + (( 39 : int): ii) (( 13 : int): ii) : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 : int): ii) + (( 0 : int): ii) : 8 words$word))) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$seqS + (state_monad$write_regS CP0Compare_ref + ((subrange_vec_dec reg_val + (( 31 : int): ii) (( 0 : int): ii) : 32 words$word))) + (state_monad$read_regS CP0Cause_ref)) + (\ (w__0 : CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec + ((get_CauseReg_IP w__0 : 8 words$word)) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) + : 8 words$word))) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (state_monad$seqS + (set_StatusReg_CU + CP0Status_ref + ((subrange_vec_dec + reg_val + (( 31 : int): ii) + (( 28 : int): ii) : 4 words$word))) + (set_StatusReg_BEV + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( + 22 : int): ii))) : 1 words$word)))) + (set_StatusReg_IM + CP0Status_ref + ((subrange_vec_dec + reg_val + (( 15 : int): ii) + (( 8 : int): ii) : 8 words$word)))) + (set_StatusReg_KX + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( 7 : int): ii))) : 1 words$word)))) + (set_StatusReg_SX + CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec + reg_val + (( 6 : int): ii))) : 1 words$word)))) + (set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 5 : int): ii))) : 1 words$word)))) + (set_StatusReg_KSU CP0Status_ref + ((subrange_vec_dec reg_val + (( 4 : int): ii) + (( 3 : int): ii) : 2 words$word)))) + (set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 2 : int): ii))) : 1 words$word)))) + (set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 1 : int): ii))) : 1 words$word)))) + (set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 0 : int): ii))) : 1 words$word))) + else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$seqS + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 23 : int): ii))) : 1 words$word))) + (state_monad$read_regS CP0Cause_ref)) + (\ (w__1 : CauseReg) . + let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec + ((subrange_vec_dec ip + (( 7 : int): ii) + (( 2 : int): ii) : 6 words$word)) + ((subrange_vec_dec reg_val + (( 9 : int): ii) + (( 8 : int): ii) : 2 words$word)) + : 8 words$word))) else + if ((((((b__108 = + (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$write_regS CP0EPC_ref reg_val + else + if ((((((b__108 = + (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS () else + if ((((((b__108 = + (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) + /\ + (((b__109 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_XContextReg_XPTEBase + TLBXContext_ref + ((subrange_vec_dec reg_val + (( 63 : int): ii) + (( 33 : int): ii) : 31 words$word)) + else + state_monad$write_regS CP0ErrorEPC_ref + reg_val + ))))`; + + +(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS + (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS + (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS + (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS + (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else state_monad$returnS () )))`; + + +(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else state_monad$returnS () )))`; + + +(*val execute_MFLO : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MFLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS + (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFHI : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MFHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS + (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +val _ = Define ` + ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double= (state_monad$bindS (state_monad$seqS + (checkCP0Access () ) + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M) + (\ (w__0 : TLBIndexT) . + let (idx : 31 bits) = ((zero_extend1 (( 31 : int): ii) w__0 : 31 words$word)) in + state_monad$bindS + (state_monad$read_regS TLBProbe_ref : ( 1 words$word) M) + (\ (w__1 : 1 bits) . + state_monad$returnS + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word) + ((concat_vec w__1 idx : 32 words$word)) : 64 words$word)))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) + (\ (w__2 : TLBIndexT) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) w__2 : 64 words$word))) else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS (state_monad$read_regS TLBEntryLo0_ref) + (\ (w__3 : TLBEntryLoReg) . + state_monad$returnS ((get_TLBEntryLoReg w__3 : 64 words$word))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS (state_monad$read_regS TLBEntryLo1_ref) + (\ (w__4 : TLBEntryLoReg) . + state_monad$returnS ((get_TLBEntryLoReg w__4 : 64 words$word))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS (state_monad$read_regS TLBContext_ref) + (\ (w__5 : ContextReg) . + state_monad$returnS ((get_ContextReg w__5 : 64 words$word))) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) + /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + (state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + else + if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) + (\ (w__7 : 16 bits) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + ((concat_vec w__7 + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 28 words$word)) : 64 words$word))) else + if ((((((b__48 = + (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS TLBWired_ref : ( 6 words$word) M) + (\ (w__8 : TLBIndexT) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) w__8 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) + (\ (w__9 : 32 bits) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) w__9 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (state_monad$read_regS CP0BadVAddr_ref : ( 64 words$word) M) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS CP0Count_ref : ( 32 words$word) M) + (\ (w__11 : 32 bits) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) w__11 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS TLBEntryHi_ref) + (\ (w__12 : TLBEntryHiReg) . + state_monad$returnS + ((get_TLBEntryHiReg w__12 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) + (\ (w__13 : 32 bits) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) w__13 : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS CP0Status_ref) + (\ (w__14 : StatusReg) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + ((get_StatusReg w__14 : 32 words$word)) : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS CP0Cause_ref) + (\ (w__15 : CauseReg) . + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + ((get_CauseReg w__15 : 32 words$word)) : 64 words$word))) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) + else + if ((((((b__48 = + (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B0;B1;B1;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 (( 64 : int): ii) + (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 + (( 64 : int): ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 15 words$word) + ((concat_vec + (vec_of_bits + [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B1;B0] : 2 words$word) + ((concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B1] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 15 words$word)) + : 16 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B1] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 + (( 64 : int): ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + TLBIndexMax + ((concat_vec + (vec_of_bits + [B0;B0;B0] : 3 words$word) + ((concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0] : 3 words$word) + ( + ( + concat_vec + ( + ( + bool_to_bits + have_cp2 : 1 words$word)) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + : 1 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + : 1 words$word) + ( + vec_of_bits + [B0] + : 1 words$word) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 16 words$word)) + : 19 words$word)) + : 22 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B1;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 + (( 64 : int): ii) + ((concat_vec + (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0] : 3 words$word) + ((concat_vec + (vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ((concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + ( + concat_vec + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + ( + vec_of_bits + [B0;B0;B0;B0] : 4 words$word) + : 8 words$word)) + : 12 words$word)) + : 16 words$word)) + : 20 words$word)) + : 24 words$word)) + : 28 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B1;B1] : 3 words$word))))))) then + state_monad$returnS + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B1;B0;B1] : 3 words$word))))))) then + state_monad$returnS + (vec_of_bits + [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B0;B1] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + (state_monad$read_regS + CP0LLAddr_ref : ( 64 words$word) M) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B1;B0] : 5 words$word)))) + /\ + (((b__49 = + (vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 + (( 64 : int): ii) + (vec_of_bits + [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + (vec_of_bits + [B1;B0;B0;B1;B1] : 5 words$word)))) + /\ + (((b__49 = + ( + vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + state_monad$returnS + ((zero_extend1 + (( 64 : int): ii) + (vec_of_bits + [B0] : 1 words$word) : 64 words$word)) + else + if ((((((b__48 = + ( + vec_of_bits + [B1;B0;B1;B0;B0] : 5 words$word)))) + /\ + ((( + b__49 = + ( + vec_of_bits + [B0;B0;B0] : 3 words$word))))))) then + state_monad$bindS + (state_monad$read_regS + TLBXContext_ref) + (\ (w__18 : XContextReg) . + state_monad$returnS + ((get_XContextReg + w__18 : 64 words$word))) + else + (state_monad$read_regS + CP0ErrorEPC_ref : ( 64 words$word) M) + )) (\ (result : 64 bits) . + wGPR rt + (if double then result + else + (sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + + +(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS + (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS + (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS + (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS + (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in state_monad$seqS + (state_monad$write_regS + HI_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) + (state_monad$write_regS + LO_ref + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + + +(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width sign linked base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + width + : ( 64 words$word) M) (\ (vAddr : 64 bits) . + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (if linked then state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (case width of + B => state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__1 : 8 words$word) . + state_monad$returnS ((extendLoad w__1 sign : 64 words$word))) + | H => state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__2 : 16 words$word) . + state_monad$returnS ((extendLoad w__2 sign : 64 words$word))) + | W0 => state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + state_monad$returnS ((extendLoad w__3 sign : 64 words$word))) + | D => state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + state_monad$returnS ((extendLoad w__4 sign : 64 words$word))) + ) + else + (case width of + B => state_monad$bindS + (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__6 : 8 words$word) . + state_monad$returnS ((extendLoad w__6 sign : 64 words$word))) + | H => state_monad$bindS + (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__7 : 16 words$word) . + state_monad$returnS ((extendLoad w__7 sign : 64 words$word))) + | W0 => state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__8 : 32 words$word) . + state_monad$returnS ((extendLoad w__8 sign : 64 words$word))) + | D => state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__9 : 64 words$word) . + state_monad$returnS ((extendLoad w__9 sign : 64 words$word))) + )) (\ (memResult : 64 bits) . + wGPR rt memResult))))))`; + + +(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + W0 + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):ii) + : ( 32 words$word) M) (\ mem_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__4 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + let (result : 32 bits) = + (if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + : 32 words$word) + else mem_val) in + wGPR rt ((sign_extend1 (( 64 : int):ii) result : 64 words$word)))))))))`; + + +(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + W0 + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):ii) + : ( 32 words$word) M) (\ mem_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__0 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + let (result : 32 bits) = + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 32 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 32 words$word)) in + wGPR rt ((sign_extend1 (( 64 : int):ii) result : 64 words$word)))))))))`; + + +(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt imm= + (wGPR rt + ((sign_extend1 (( 64 : int):ii) + ((concat_vec imm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word) + : 32 words$word)) + : 64 words$word))))`; + + +(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + D + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):ii) + : ( 64 words$word) M) (\ mem_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__24 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + : 64 words$word) + else mem_val))))))))`; + + +(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData + D + : ( 64 words$word) M) (\ vAddr . state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):ii) + : ( 64 words$word) M) (\ mem_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__16 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + : 64 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + : 64 words$word)))))))))`; + + +(*val execute_JR : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_JR:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; + + +(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS (state_monad$seqS + (execute_branch w__0) + (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; + + +(*val execute_JAL : mword ty26 -> M unit*) + +val _ = Define ` + ((execute_JAL:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS + (execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word))) + (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; + + +(*val execute_J : mword ty26 -> M unit*) + +val _ = Define ` + ((execute_J:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word)))))`; + + +(*val execute_ImplementationDefinedStopFetching : unit -> unit*) + +val _ = Define ` + ((execute_ImplementationDefinedStopFetching:unit -> unit) g__118= () )`; + + +(*val execute_HCF : unit -> unit*) + +val _ = Define ` + ((execute_HCF:unit -> unit) g__123= () )`; + + +(*val execute_ERET : unit -> M unit*) + +val _ = Define ` + ((execute_ERET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__128= (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (checkCP0Access () ) + (ERETHook () )) + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word))) + (state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then state_monad$bindS + (state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$seqS + (state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) + else state_monad$bindS + (state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$seqS + (state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word))))))`; + + +(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((sub_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (temp65 : 65 bits) = + ((sub_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))))))`; + + +(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in state_monad$bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in state_monad$bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in state_monad$bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in state_monad$bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . + wGPR rd w__2)))))`; + + +(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) + : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd w__1))))`; + + +(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; + + +(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let result = ((mult_vec w__0 w__1 : 128 words$word)) in state_monad$seqS + (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + + +(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let result = ((mults_vec w__0 w__1 : 128 words$word)) in state_monad$seqS + (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + + +(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))))))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + state_monad$returnS (w__0, w__1))) + else + let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (hardware_mod si ti) in + state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS + (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r : 64 words$word))) + (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q : 64 words$word))))))))`; + + +(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))))))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + state_monad$returnS (w__0, w__1))) + else + let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (si - ((ti * qi))) in + state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS + (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r : 64 words$word))) + (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q : 64 words$word))))))))`; + + +(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rsVal = (lem$w2ui w__0) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rtVal = (lem$w2ui w__1) in state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + state_monad$returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (hardware_mod rsVal rtVal) in + state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS + (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`; + + +(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rsVal = (integer_word$w2i w__0) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rtVal = (integer_word$w2i w__1) in state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + state_monad$returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (rsVal - ((qi * rtVal))) in + state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS + (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`; + + +(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (sum65 : 65 bits) = + ((add_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) imm : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))`; + + +(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (sum65 : 65 bits) = + ((add_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))))))`; + + +(*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ClearRegs:ClearRegSet ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) regset m= (state_monad$seqS (state_monad$seqS + (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () + else state_monad$returnS () ) + (if (((regset = CHi))) then + (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . + let r = + ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) : 5 words$word)) in state_monad$bindS + (state$and_boolS (state_monad$returnS ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r))) (\ (w__1 : + bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r + else state_monad$returnS () ))) + else state_monad$returnS () )) + (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . + if ((bit_to_bool ((access_vec_dec m i)))) then + (case regset of + GPLo => + wGPR ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) + ((zeros0 (( 64 : int):ii) () : 64 words$word)) + | GPHi => + wGPR + ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) + : 5 words$word)) ((zeros0 (( 64 : int):ii) () : 64 words$word)) + | CLo => + writeCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) null_cap + | CHi => + writeCapReg + ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) + : 5 words$word)) null_cap + ) + else state_monad$returnS () ))))`; + + +(*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb sel= (state_monad$seqS + (checkCP2usable () ) + (let l__24 = (lem$w2ui sel) in state_monad$bindS + (if (((l__24 = (( 0 : int):ii)))) then state_monad$returnS (F, F) + else if (((l__24 = (( 1 : int):ii)))) then state_monad$returnS (F, F) + else if (((l__24 = (( 8 : int):ii)))) then state_monad$returnS (F, T) + else if (((l__24 = (( 22 : int):ii)))) then state_monad$returnS (T, F) + else if (((l__24 = (( 23 : int):ii)))) then state_monad$returnS (T, F) + else if (((l__24 = (( 29 : int):ii)))) then state_monad$returnS (T, T) + else if (((l__24 = (( 30 : int):ii)))) then state_monad$returnS (T, T) + else if (((l__24 = (( 31 : int):ii)))) then state_monad$returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS + (register_inaccessible cb) (\ (w__8 : bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (state$and_boolS (state_monad$returnS needAccessSys) + ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . state_monad$returnS ((~ w__9))))) (\ (w__10 : + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else state_monad$bindS + (state$and_boolS (state_monad$returnS needSup) + ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . + state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else state_monad$bindS + (readCapReg cb) (\ capVal . + let l__16 = (lem$w2ui sel) in + if (((l__16 = (( 0 : int):ii)))) then writeCapReg DDC capVal + else if (((l__16 = (( 1 : int):ii)))) then + state_monad$write_regS CTLSU_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((l__16 = (( 8 : int):ii)))) then + state_monad$write_regS CTLSP_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((l__16 = (( 22 : int):ii)))) then writeCapReg KR1C capVal + else if (((l__16 = (( 23 : int):ii)))) then writeCapReg KR2C capVal + else if (((l__16 = (( 29 : int):ii)))) then writeCapReg KCC capVal + else if (((l__16 = (( 30 : int):ii)))) then writeCapReg KDC capVal + else if (((l__16 = (( 31 : int):ii)))) then writeCapReg EPCC capVal + else state_monad$assert_expS F "should be unreachable code"))))))))`; + + +(*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if (((ct_cursor <> ((lem$w2ui cs_val.CapStruct_otype))))) then + raise_c2_exception CapEx_TypeViolation ct + else if ((~ ct_val.CapStruct_permit_unseal)) then + raise_c2_exception CapEx_PermitUnsealViolation ct + else if ((ct_cursor < ((getCapBase ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ((getCapTop ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else + writeCapReg cd + (cs_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word)); CapStruct_global := + (((cs_val.CapStruct_global /\ ct_val.CapStruct_global)))|>))))))))`; + + +(*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg ct)) (\ ct_val . state_monad$bindS + (readCapReg cb) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let cbBase = (getCapBase cb_val) in + let cbTop = (getCapTop cb_val) in + let ctBase = (getCapBase ct_val) in + let ctTop = (getCapTop ct_val) in + wGPR rd + (if (((((~ cb_val.CapStruct_tag)) \/ (((((cbBase < ctBase)) \/ ((cbTop > ctTop)))))))) then + (zeros0 (( 64 : int):ii) () : 64 words$word) + else + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) + ((((getCapCursor cb_val)) - ctBase)) + : 64 words$word))))))))`; + + +(*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in + let ct_perms = ((getCapPerms ct_val : 31 words$word)) in + let cb_top = (getCapTop cb_val) in + let cb_base = (getCapBase cb_val) in + let cb_perms = ((getCapPerms cb_val : 31 words$word)) in state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + let (result : 1 bits) = + (if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then + (vec_of_bits [B0] : 1 words$word) + else if ((ct_base < cb_base)) then (vec_of_bits [B0] : 1 words$word) + else if ((ct_top > cb_top)) then (vec_of_bits [B0] : 1 words$word) + else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then + (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + wGPR rd ((zero_extend1 (( 64 : int):ii) result : 64 words$word))))))))`; + + +(*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg ct)) (\ ct_val . state_monad$bindS + (readCapReg cb) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + wGPR rd + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) + ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) + : 64 words$word))))))))`; + + +(*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*) + +val _ = Define ` + ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_store)) then + raise_c2_exception CapEx_PermitStoreViolation cb + else + let size1 = (wordWidthBytes width) in + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + size1)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 + else state_monad$bindS + (TLBTranslate vAddr64 StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + if conditional then state_monad$bindS + (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__2 : 1 bits) . state_monad$bindS + (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 : int):ii) + ((subrange_vec_dec rs_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 : int):ii) + ((subrange_vec_dec rs_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + | W0 => + MEMw_conditional_wrapper pAddr (( 4 : int):ii) + ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rs_val + ) + else state_monad$returnS F) (\ (success : bool) . + wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rs_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + | H => MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec rs_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + | W0 => MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_wrapper pAddr (( 8 : int):ii) rs_val + ))))))))`; + + +(*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CSetCause : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (pcc_access_system_regs () )) (\ (w__0 : bool) . + if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$seqS + (set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):ii) (( 8 : int):ii) : 8 words$word))) + (set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))))`; + + +(*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +val _ = Define ` + ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . + let immU = (lem$w2ui imm) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + immU) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else (case + setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int): ii) : 64 itself)) cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int): ii) : 65 itself)) newTop : 65 words$word)) of + (_, newCap) => + writeCapReg cd newCap + ))))))`; + + +(*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rt_val = (lem$w2ui w__0) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + rt_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else + let (exact, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int):ii) : 65 itself)) newTop : 65 words$word))) in + if ((~ exact)) then raise_c2_exception CapEx_InexactBounds cb + else writeCapReg cd newCap))))))`; + + +(*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rt_val = (lem$w2ui w__0) in + let cursor = (getCapCursor cb_val) in + let base = (getCapBase cb_val) in + let top = (getCapTop cb_val) in + let newTop = (cursor + rt_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb + else (case + setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int): ii) : 64 itself)) cursor : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int): ii) : 65 itself)) newTop : 65 words$word)) of + (_, newCap) => + writeCapReg cd newCap + )))))))`; + + +(*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct + else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if ((~ ct_val.CapStruct_permit_seal)) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 : int):ii) : 24 itself)) ct_cursor : 24 words$word))) in + if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd newCap)))))))`; + + +(*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +val _ = Define ` + ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cb) (\ cb_val . state_monad$bindS + (register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_store)) then + raise_c2_exception CapEx_PermitStoreViolation cb + else if ((~ cb_val.CapStruct_permit_store_cap)) then + raise_c2_exception CapEx_PermitStoreCapViolation cb + else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then + raise_c2_exception CapEx_PermitStoreLocalCapViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdES vAddr64 + else state_monad$bindS + (TLBTranslateC vAddr64 StoreData : (( 64 words$word # bool)) M) (\ varstup . let (pAddr, noStoreCap) = varstup in + if (((cs_val.CapStruct_tag /\ noStoreCap))) then + raise_c2_exception CapEx_TLBNoStoreCap cs + else if conditional then state_monad$bindS + (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__3 : 1 bits) . state_monad$bindS + (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):ii))))) then + MEMw_tagged_conditional pAddr cs_val.CapStruct_tag + ((capStructToMemBits cs_val : 256 words$word)) + else state_monad$returnS F) (\ success . + wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val : 256 words$word))))))))))`; + + +(*val execute_CReturn : unit -> M unit*) + +val _ = Define ` + ((execute_CReturn:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__129= (state_monad$seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`; + + +(*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CReadHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd sel= (state_monad$seqS + (checkCP2usable () ) + (let l__8 = (lem$w2ui sel) in state_monad$bindS + (if (((l__8 = (( 0 : int):ii)))) then state_monad$returnS (F, F) + else if (((l__8 = (( 1 : int):ii)))) then state_monad$returnS (F, F) + else if (((l__8 = (( 8 : int):ii)))) then state_monad$returnS (F, T) + else if (((l__8 = (( 22 : int):ii)))) then state_monad$returnS (T, F) + else if (((l__8 = (( 23 : int):ii)))) then state_monad$returnS (T, F) + else if (((l__8 = (( 29 : int):ii)))) then state_monad$returnS (T, T) + else if (((l__8 = (( 30 : int):ii)))) then state_monad$returnS (T, T) + else if (((l__8 = (( 31 : int):ii)))) then state_monad$returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS + (register_inaccessible cd) (\ (w__8 : bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (state$and_boolS (state_monad$returnS needAccessSys) + ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . state_monad$returnS ((~ w__9))))) (\ (w__10 : + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else state_monad$bindS + (state$and_boolS (state_monad$returnS needSup) + ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . + state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + let l__0 = (lem$w2ui sel) in state_monad$bindS + (if (((l__0 = (( 0 : int):ii)))) then readCapReg DDC + else if (((l__0 = (( 1 : int):ii)))) then state_monad$bindS + (state_monad$read_regS CTLSU_ref : ( 257 words$word) M) (\ (w__14 : 257 words$word) . + state_monad$returnS ((capRegToCapStruct w__14))) + else if (((l__0 = (( 8 : int):ii)))) then state_monad$bindS + (state_monad$read_regS CTLSP_ref : ( 257 words$word) M) (\ (w__15 : 257 words$word) . + state_monad$returnS ((capRegToCapStruct w__15))) + else if (((l__0 = (( 22 : int):ii)))) then readCapReg KR1C + else if (((l__0 = (( 23 : int):ii)))) then readCapReg KR2C + else if (((l__0 = (( 29 : int):ii)))) then readCapReg KCC + else if (((l__0 = (( 30 : int):ii)))) then readCapReg KDC + else if (((l__0 = (( 31 : int):ii)))) then readCapReg EPCC + else state_monad$seqS (state_monad$assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal : + CapStruct) . + writeCapReg cd capVal))))))))`; + + +(*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*) + +val _ = Define ` + ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> CPtrCmpOp ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct op= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else state_monad$bindS + (readCapReg cb) (\ cb_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let equal = F in + let ltu = F in + let lts = F in + let ((equal : bool), (lts : bool), (ltu : bool)) = + (if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then + let ((lts : bool), (ltu : bool)) = + (if ((~ cb_val.CapStruct_tag)) then + let (ltu : bool) = T in + let (lts : bool) = T in + (lts, ltu) + else (lts, ltu)) in + (equal, lts, ltu) + else + let cursor1 = (getCapCursor cb_val) in + let cursor2 = (getCapCursor ct_val) in + let (equal : bool) = (cursor1 = cursor2) in + let (ltu : bool) = (cursor1 < cursor2) in + let (lts : bool) = + (zopz0zI_s ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) cursor1 : 64 words$word)) + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) cursor2 : 64 words$word))) in + (equal, lts, ltu)) in + let (cmp : bool) = + ((case op of + CEQ => equal + | CNE => ~ equal + | CLT => lts + | CLE => (lts \/ equal) + | CLTU => ltu + | CLEU => (ltu \/ equal) + | CEXEQ => (cb_val = ct_val) + | CNEXEQ => (cb_val <> ct_val) + )) in + wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits cmp : 1 words$word)) : 64 words$word))))))))`; + + +(*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +val _ = Define ` + ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt ismovn= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + if ((bits_to_bool + ((xor_vec + ((bool_to_bits (((w__2 = ((zeros0 (( 64 : int):ii) () : 64 words$word))))) : 1 words$word)) + ((bool_to_bits ismovn : 1 words$word)) + : 1 words$word)))) then state_monad$bindS + (readCapReg cb) (\ (w__3 : CapStruct) . writeCapReg cd w__3) + else state_monad$returnS () )))))`; + + +(*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*) + +val _ = Define ` + ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6= + (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in + (case merge_var of + (rd, cb, rt, offset, signext, B, linked) => state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 1 : int):ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 + else state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 1 : int):ii) : ( 8 words$word) M)) (\ (w__2 : 8 words$word) . + state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else state_monad$bindS + (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__3 : 8 words$word) . + state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, D, linked) => state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 8 : int):ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 + else state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M)) (\ (w__2 : 64 words$word) . + state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, H, linked) => state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 2 : int):ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 + else state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 2 : int):ii) : ( 16 words$word) M)) (\ (w__2 : 16 words$word) . + state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else state_monad$bindS + (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__3 : 16 words$word) . + state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + wGPR rd memResult))))) + | (rd, cb, rt, offset, signext, W0, linked) => state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cb) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + (( 4 : int):ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64 + else state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M)) (\ (w__2 : 32 words$word) . + state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + wGPR rd memResult))))) + )))`; + + +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +val _ = Define ` + ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt offset linked= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + let cursor = (getCapCursor cb_val) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + let vAddr = + (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset)))))) + % + ((pow2 (( 64 : int):ii)))) in + let vAddr64 = ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdEL vAddr64 + else state_monad$bindS + (TLBTranslateC vAddr64 LoadData : (( 64 words$word # bool)) M) (\ varstup . let (pAddr, suppressTag) = varstup in + let cd = (lem$w2ui cd) in + if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (state_monad$write_regS CP0LLAddr_ref pAddr)) + (MEMr_tagged_reserve pAddr : ((bool # 256 words$word)) M)) (\ varstup . let (tag, mem) = varstup in + state_monad$write_regS + ((access_list_dec CapRegs cd : (regstate, register_value, ( 257 words$word)) register_ref)) + ((memBitsToCapBits + (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) + mem + : 257 words$word))) + else state_monad$bindS + (MEMr_tagged pAddr : ((bool # 256 words$word)) M) (\ varstup . let (tag, mem) = varstup in + state_monad$write_regS + ((access_list_dec CapRegs cd : (regstate, register_value, ( 257 words$word)) register_ref)) + ((memBitsToCapBits + (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) + mem + : 257 words$word))))))))))`; + + +(*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*) + +val _ = Define ` + ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb link= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . + let cb_ptr = (getCapCursor cb_val) in + let cb_top = (getCapTop cb_val) in + let cb_base = (getCapBase cb_val) in state_monad$bindS + (state$and_boolS (state_monad$returnS link) ((register_inaccessible cd))) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((~ cb_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((((cb_ptr + (( 4 : int):ii))) > cb_top)) then + raise_c2_exception CapEx_LengthViolation cb + else if (((((cb_ptr % (( 4 : int):ii))) <> (( 0 : int):ii)))) then SignalException AdEL + else state_monad$seqS + (if link then state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__3 : 257 words$word) . + let pcc = (capRegToCapStruct w__3) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 : int):ii) : 64 words$word))) in + if success then writeCapReg cd linkCap + else state_monad$assert_expS F "")) + else state_monad$returnS () ) + (execute_branch_pcc cb_val))))))`; + + +(*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +val _ = Define ` + ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . + let (imm64 : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (incCapOffset cb_val imm64) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) imm64 + : 64 words$word)))))))))`; + + +(*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : 64 words$word)))))))))) then + raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (incCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):ii) capVal.CapStruct_otype : 64 words$word) + else (replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):ii) : 64 words$word))))))`; + + +(*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_tag : 1 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetSealed:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_sealed : 1 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd ((zero_extend1 (( 64 : int):ii) ((getCapPerms capVal : 31 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd rs= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + let (success, newPCC) = (setCapOffset pcc rs_val) in + if success then writeCapReg cd newPCC + else writeCapReg cd ((int_to_cap rs_val)))))))`; + + +(*val execute_CGetPCC : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetPCC:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + let (success, pcc2) = (setCapOffset pcc w__2) in state_monad$seqS + (state_monad$assert_expS success "") (writeCapReg cd pcc2))))))`; + + +(*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapOffset capVal)) : 64 words$word))))))`; + + +(*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetLen:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + let len65 = (getCapLength capVal) in + wGPR rd + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) + (if ((len65 > MAX_U64)) then MAX_U64 + else len65) + : 64 words$word))))))`; + + +(*val execute_CGetCause : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (pcc_access_system_regs () )) (\ (w__0 : bool) . + if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else state_monad$bindS + (state_monad$read_regS CapCause_ref) (\ (w__1 : CapCauseReg) . + wGPR rd ((zero_extend1 (( 64 : int):ii) ((get_CapCauseReg w__1 : 16 words$word)) : 64 words$word))))))`; + + +(*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetBase:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase capVal)) : 64 words$word))))))`; + + +(*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CGetAddr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapCursor capVal)) : 64 words$word))))))`; + + +(*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then writeCapReg cd null_cap + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else + let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd newCap + else + writeCapReg cd + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase cb_val)) + : 64 words$word)) rt_val + : 64 words$word))))))))))`; + + +(*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let cb_base = (getCapBase cb_val) in + let cb_top = (getCapTop cb_val) in + let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ct_val.CapStruct_sealed then + if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_otype >= cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else + let (success, cap) = + (setCapOffset cb_val + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((ct_otype - cb_base)) + : 64 words$word))) in state_monad$seqS + (state_monad$assert_expS success "") (writeCapReg cd cap) + else + writeCapReg cd + ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):ii) : 64 words$word)))))))))))`; + + +(*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CClearTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cd)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS (readCapReg cb) (\ cb_val . writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`; + + +(*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CCheckType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cb) (\ cb_val . state_monad$bindS + (register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else state_monad$returnS () ))))))`; + + +(*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . + let (cs_perms : 64 bits) = + ((zero_extend1 (( 64 : int):ii) ((getCapPerms cs_val : 31 words$word)) : 64 words$word)) in state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_perms . state_monad$bindS + (register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if (((((and_vec cs_perms rt_perms : 64 words$word)) <> rt_perms))) then + raise_c2_exception CapEx_UserDefViolation cs + else state_monad$returnS () )))))`; + + +(*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +val _ = Define ` + ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb b__151= + (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) then state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cb) (\ cb_val . + let cs_cursor = (getCapCursor cs_val) in state_monad$bindS + (register_inaccessible cs) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((~ cs_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if cb_val.CapStruct_permit_execute then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor >= ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else raise_c2_exception CapEx_CallTrap cs)))) + else state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cb) (\ cb_val . + let cs_cursor = (getCapCursor cs_val) in state_monad$bindS + (register_inaccessible cs) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible cb) (\ (w__3 : bool) . + if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs + else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb + else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((~ cs_val.CapStruct_permit_ccall)) then + raise_c2_exception CapEx_PermitCCallViolation cs + else if ((~ cb_val.CapStruct_permit_ccall)) then + raise_c2_exception CapEx_PermitCCallViolation cb + else if ((~ cs_val.CapStruct_permit_execute)) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if cb_val.CapStruct_permit_execute then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor >= ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else state_monad$seqS (state_monad$seqS + (execute_branch_pcc + (cs_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word))|>)) + (state_monad$write_regS inCCallDelay_ref (vec_of_bits [B1] : 1 words$word))) + (state_monad$write_regS + C26_ref + ((capStructToCapReg + (cb_val with<| + CapStruct_sealed := F; CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word))|>) + : 257 words$word)))))))))`; + + +(*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let ct_cursor = (getCapCursor ct_val) in + let ct_top = (getCapTop ct_val) in + let ct_base = (getCapBase ct_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cs) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else state_monad$bindS + (register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs + else if (((((~ ct_val.CapStruct_tag)) \/ (((((getCapCursor ct_val)) = ((lem$w2ui ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):ii) : 64 words$word)))))))))) + then + writeCapReg cd cs_val + else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs + else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct + else if ((~ ct_val.CapStruct_permit_seal)) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 : int):ii) : 24 itself)) ct_cursor : 24 words$word))) in + if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd newCap)))))))`; + + +(*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg ct) (\ ct_val . + let cb_base = (getCapBase cb_val) in + let ct_base = (getCapBase ct_val) in + let cb_top = (getCapTop cb_val) in + let ct_top = (getCapTop ct_val) in + let cb_perms = ((getCapPerms cb_val : 31 words$word)) in + let ct_perms = ((getCapPerms ct_val : 31 words$word)) in + let ct_offset = (getCapOffset ct_val) in state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (register_inaccessible ct) (\ (w__2 : bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then + raise_c2_exception CapEx_UserDefViolation cb + else + let (exact, cd1) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ct_base : 64 words$word)) + ((to_bits ((make_the_value (( 65 : int):ii) : 65 itself)) ct_top : 65 words$word))) in + let (representable, cd2) = + (setCapOffset cd1 + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ct_offset : 64 words$word))) in + let cd3 = (setCapPerms cd2 ct_perms) in state_monad$seqS (state_monad$seqS + (state_monad$assert_expS exact "") (state_monad$assert_expS representable "")) (writeCapReg cd cd3))))))))`; + + +(*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*) + +val _ = Define ` + ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notzero= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ (w__1 : CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__1 = null_cap))) : 1 words$word)) + ((bool_to_bits notzero : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else state_monad$returnS () ))))`; + + +(*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*) + +val _ = Define ` + ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notset= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (register_inaccessible cb)) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else state_monad$bindS + (readCapReg cb) (\ (w__1 : CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits w__1.CapStruct_tag : 1 words$word)) + ((bool_to_bits notset : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else state_monad$returnS () ))))`; + + +(*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + (checkCP2usable () ) + (readCapReg cb)) (\ cb_val . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (register_inaccessible cd) (\ (w__0 : bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd + else state_monad$bindS + (register_inaccessible cb) (\ (w__1 : bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb + else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb + else + let perms = ((getCapPerms cb_val : 31 words$word)) in + let newCap = + (setCapPerms cb_val + ((and_vec perms ((subrange_vec_dec rt_val (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)) : 31 words$word))) in + writeCapReg cd newCap))))))`; + + +(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; + + +(*val execute_C2Dump : mword ty5 -> unit*) + +val _ = Define ` + ((execute_C2Dump:(5)words$word -> unit) rt= () )`; + + +(*val execute_BREAK : unit -> M unit*) + +val _ = Define ` + ((execute_BREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__120= (SignalException Bp))`; + + +(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) + +val _ = Define ` + ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd imm ne likely= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rd : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) : 1 words$word)) + ((bool_to_bits ne : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else if likely then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii) : 64 words$word))) + else state_monad$returnS () ))))`; + + +(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) + +val _ = Define ` + ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp link likely= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let linkVal = ((add_vec_int w__0 (( 8 : int):ii) : 64 words$word)) in state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ regVal . + let condition = + (compare cmp regVal ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in state_monad$seqS + (if condition then + let (offset : 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + execute_branch ((add_vec w__1 offset : 64 words$word))) + else if likely then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii) : 64 words$word))) + else state_monad$returnS () ) + (if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) linkVal + else state_monad$returnS () )))))`; + + +(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((and_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 : int):ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . + if ((NotWordVal opA)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + wGPR rt + ((sign_extend1 (( 64 : int):ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((sign_extend1 (( 32 : int):ii) imm : 32 words$word)) + : 32 words$word)) + : 64 words$word)))))`; + + +(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . + if ((NotWordVal opA)) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + let (sum33 : 33 bits) = + ((add_vec + ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):ii) imm : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rt + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + + +(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (opA : 64 bits) . state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (opB : 64 bits) . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (sum33 : 33 bits) = + ((add_vec + ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))`; + + +val _ = Define ` + ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var= + ((case merge_var of + DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm + | DADDU (rs,rt,rd) => execute_DADDU rs rt rd + | DADDI (rs,rt,imm) => execute_DADDI rs rt imm + | DADD (rs,rt,rd) => execute_DADD rs rt rd + | ADD (rs,rt,rd) => execute_ADD rs rt rd + | ADDI (rs,rt,imm) => execute_ADDI rs rt imm + | ADDU (rs,rt,rd) => execute_ADDU rs rt rd + | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm + | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd + | DSUB (rs,rt,rd) => execute_DSUB rs rt rd + | SUB0 (rs,rt,rd) => execute_SUB rs rt rd + | SUBU (rs,rt,rd) => execute_SUBU rs rt rd + | AND (rs,rt,rd) => execute_AND rs rt rd + | ANDI (rs,rt,imm) => execute_ANDI rs rt imm + | OR (rs,rt,rd) => execute_OR rs rt rd + | ORI (rs,rt,imm) => execute_ORI rs rt imm + | NOR (rs,rt,rd) => execute_NOR rs rt rd + | XOR (rs,rt,rd) => execute_XOR rs rt rd + | XORI (rs,rt,imm) => execute_XORI rs rt imm + | LUI (rt,imm) => execute_LUI rt imm + | DSLL (rt,rd,sa) => execute_DSLL rt rd sa + | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa + | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd + | DSRA (rt,rd,sa) => execute_DSRA rt rd sa + | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa + | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd + | DSRL (rt,rd,sa) => execute_DSRL rt rd sa + | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa + | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd + | SLL (rt,rd,sa) => execute_SLL rt rd sa + | SLLV (rs,rt,rd) => execute_SLLV rs rt rd + | SRA (rt,rd,sa) => execute_SRA rt rd sa + | SRAV (rs,rt,rd) => execute_SRAV rs rt rd + | SRL (rt,rd,sa) => execute_SRL rt rd sa + | SRLV (rs,rt,rd) => execute_SRLV rs rt rd + | SLT (rs,rt,rd) => execute_SLT rs rt rd + | SLTI (rs,rt,imm) => execute_SLTI rs rt imm + | SLTU (rs,rt,rd) => execute_SLTU rs rt rd + | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm + | MOVN (rs,rt,rd) => execute_MOVN rs rt rd + | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd + | MFHI (rd) => execute_MFHI rd + | MFLO (rd) => execute_MFLO rd + | MTHI (rs) => execute_MTHI rs + | MTLO (rs) => execute_MTLO rs + | MUL (rs,rt,rd) => execute_MUL rs rt rd + | MULT (rs,rt) => execute_MULT rs rt + | MULTU (rs,rt) => execute_MULTU rs rt + | DMULT (rs,rt) => execute_DMULT rs rt + | DMULTU (rs,rt) => execute_DMULTU rs rt + | MADD (rs,rt) => execute_MADD rs rt + | MADDU (rs,rt) => execute_MADDU rs rt + | MSUB (rs,rt) => execute_MSUB rs rt + | MSUBU (rs,rt) => execute_MSUBU rs rt + | DIV0 (rs,rt) => execute_DIV rs rt + | DIVU (rs,rt) => execute_DIVU rs rt + | DDIV (rs,rt) => execute_DDIV rs rt + | DDIVU (rs,rt) => execute_DDIVU rs rt + | J (offset) => execute_J offset + | JAL (offset) => execute_JAL offset + | JR (rs) => execute_JR rs + | JALR (rs,rd) => execute_JALR rs rd + | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely + | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely + | SYSCALL_THREAD_START (g__117) => state_monad$returnS ((execute_SYSCALL_THREAD_START g__117)) + | ImplementationDefinedStopFetching (g__118) => + state_monad$returnS ((execute_ImplementationDefinedStopFetching g__118)) + | SYSCALL (g__119) => execute_SYSCALL g__119 + | BREAK (g__120) => execute_BREAK g__120 + | WAIT (g__121) => execute_WAIT g__121 + | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp + | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp + | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset + | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset + | LWL (base,rt,offset) => execute_LWL base rt offset + | LWR (base,rt,offset) => execute_LWR base rt offset + | SWL (base,rt,offset) => execute_SWL base rt offset + | SWR (base,rt,offset) => execute_SWR base rt offset + | LDL (base,rt,offset) => execute_LDL base rt offset + | LDR (base,rt,offset) => execute_LDR base rt offset + | SDL (base,rt,offset) => execute_SDL base rt offset + | SDR (base,rt,offset) => execute_SDR base rt offset + | CACHE (base,op,imm) => execute_CACHE base op imm + | PREF (base,op,imm) => state_monad$returnS ((execute_PREF base op imm)) + | SYNC (g__122) => execute_SYNC g__122 + | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double + | HCF (g__123) => state_monad$returnS ((execute_HCF g__123)) + | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double + | TLBWI (g__124) => execute_TLBWI g__124 + | TLBWR (g__125) => execute_TLBWR g__125 + | TLBR (g__126) => execute_TLBR g__126 + | TLBP (g__127) => execute_TLBP g__127 + | RDHWR (rt,rd) => execute_RDHWR rt rd + | ERET (g__128) => execute_ERET g__128 + | CGetPerm (rd,cb) => execute_CGetPerm rd cb + | CGetType (rd,cb) => execute_CGetType rd cb + | CGetBase (rd,cb) => execute_CGetBase rd cb + | CGetOffset (rd,cb) => execute_CGetOffset rd cb + | CGetLen (rd,cb) => execute_CGetLen rd cb + | CGetTag (rd,cb) => execute_CGetTag rd cb + | CGetSealed (rd,cb) => execute_CGetSealed rd cb + | CGetAddr (rd,cb) => execute_CGetAddr rd cb + | CGetPCC (cd) => execute_CGetPCC cd + | CGetPCCSetOffset (cd,rs) => execute_CGetPCCSetOffset cd rs + | CGetCause (rd) => execute_CGetCause rd + | CSetCause (rt) => execute_CSetCause rt + | CReadHwr (cd,sel) => execute_CReadHwr cd sel + | CWriteHwr (cb,sel) => execute_CWriteHwr cb sel + | CAndPerm (cd,cb,rt) => execute_CAndPerm cd cb rt + | CToPtr (rd,cb,ct) => execute_CToPtr rd cb ct + | CSub (rd,cb,ct) => execute_CSub rd cb ct + | CPtrCmp (rd,cb,ct,op) => execute_CPtrCmp rd cb ct op + | CIncOffset (cd,cb,rt) => execute_CIncOffset cd cb rt + | CIncOffsetImmediate (cd,cb,imm) => execute_CIncOffsetImmediate cd cb imm + | CSetOffset (cd,cb,rt) => execute_CSetOffset cd cb rt + | CSetBounds (cd,cb,rt) => execute_CSetBounds cd cb rt + | CSetBoundsImmediate (cd,cb,imm) => execute_CSetBoundsImmediate cd cb imm + | CSetBoundsExact (cd,cb,rt) => execute_CSetBoundsExact cd cb rt + | CClearTag (cd,cb) => execute_CClearTag cd cb + | CMOVX (cd,cb,rt,ismovn) => execute_CMOVX cd cb rt ismovn + | ClearRegs (regset,m) => execute_ClearRegs regset m + | CFromPtr (cd,cb,rt) => execute_CFromPtr cd cb rt + | CBuildCap (cd,cb,ct) => execute_CBuildCap cd cb ct + | CCopyType (cd,cb,ct) => execute_CCopyType cd cb ct + | CCheckPerm (cs,rt) => execute_CCheckPerm cs rt + | CCheckType (cs,cb) => execute_CCheckType cs cb + | CTestSubset (rd,cb,ct) => execute_CTestSubset rd cb ct + | CSeal (cd,cs,ct) => execute_CSeal cd cs ct + | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct + | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct + | CCall (cs,cb,b__151) => execute_CCall cs cb b__151 + | CReturn (g__129) => execute_CReturn g__129 + | CBX (cb,imm,notset) => execute_CBX cb imm notset + | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero + | CJALR (cd,cb,link) => execute_CJALR cd cb link + | CLoad (rd,cb,rt,offset,signext,arg5,linked) => + execute_CLoad rd cb rt offset signext arg5 linked + | CStore (rs,cb,rt,rd,offset,width,conditional) => + execute_CStore rs cb rt rd offset width conditional + | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional + | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked + | C2Dump (rt) => state_monad$returnS ((execute_C2Dump rt)) + | RI (g__130) => execute_RI g__130 + )))`; + + +(*val supported_instructions : ast -> maybe ast*) + +val _ = Define ` + ((supported_instructions:ast ->(ast)option) instr= (SOME instr))`; + + +(*val fetch_and_execute : unit -> M bool*) + +val _ = Define ` + ((fetch_and_execute:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS PC_ref w__0) + (state_monad$read_regS branchPending_ref : ( 1 words$word) M)) (\ (w__1 : 1 bits) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS inBranchDelay_ref w__1) + (state_monad$write_regS branchPending_ref (vec_of_bits [B0] : 1 words$word))) + (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__2 : 1 words$word) . state_monad$bindS + (if ((bits_to_bool w__2)) then (state_monad$read_regS delayedPC_ref : ( 64 words$word) M) + else state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + state_monad$returnS ((add_vec_int w__4 (( 4 : int):ii) : 64 words$word)))) (\ (w__5 : 64 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS nextPC_ref w__5) + (cp2_next_pc () )) + (state_monad$read_regS instCount_ref)) (\ (w__6 : ii) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS instCount_ref ((w__6 + (( 1 : int):ii)))) + (state_monad$read_regS UART_WRITTEN_ref : ( 1 words$word) M)) (\ (w__7 : 1 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (if ((bits_to_bool w__7)) then state_monad$bindS + (state_monad$read_regS UART_WDATA_ref : ( 8 words$word) M) (\ (w__8 : 8 bits) . + let (_ : unit) = (putchar ((lem$w2ui w__8))) in + state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B0] : 1 words$word)) + else state_monad$returnS () ) + (skip () )) + (skip () )) + (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__9 : 64 bits) . + let (_ : unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict "PC: " w__9) in + state_monad$try_catchS ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . state_monad$bindS + (TranslatePC w__10 : ( 64 words$word) M) (\ pc_pa . state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) pc_pa (( 4 : int):ii) : ( 32 words$word) M) (\ instr . + let instr_ast = (decode instr) in + (case instr_ast of + SOME ((HCF (_))) => + let (_ : unit) = (prerr_endline "simulation stopped due to halt instruction.") in + state_monad$returnS F + | SOME (ast) => state_monad$seqS (execute ast) (state_monad$returnS T) + | NONE => + let (_ : unit) = (prerr_endline "Decode failed") in + state_monad$exitS () + ))))) (\x . + (case x of + ISAException (_) => + let (_ : unit) = (prerr_endline "EXCEPTION") in state_monad$returnS T + )))))))))))`; + + +(*val init_registers : mword ty64 -> M unit*) + +val _ = Define ` + ((init_registers:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) initialPC= (state_monad$seqS (state_monad$seqS + (init_cp0_state () ) (init_cp2_state () )) (state_monad$write_regS nextPC_ref initialPC)))`; + + +(*val dump_mips_state : unit -> M unit*) + +val _ = Define ` + ((dump_mips_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let (_ : unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict "DEBUG MIPS PC " w__0) in + (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ idx unit_var . state_monad$bindS + (rGPR ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) idx : 5 words$word)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . + state_monad$returnS (let _ = + (prerr_endline + ((STRCAT "DEBUG MIPS REG " + ((STRCAT ((string_of_int + instance_Show_Show_Num_integer_dict idx)) ((STRCAT " " ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + () )))))))`; + + +(*val main : unit -> M unit*) + +val _ = Define ` + ((main:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$seqS + (init_registers + ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((elf_entry () )) : 64 words$word))) + (let startTime = (get_time_ns () ) in state_monad$seqS + (state$whileS () (\ unit_var . fetch_and_execute () ) (\ unit_var . state_monad$returnS () )) + (let endTime = (get_time_ns () ) in + let elapsed = (endTime - startTime) in state_monad$bindS + (state_monad$read_regS instCount_ref) (\ (w__1 : ii) . + let inst_1e9 = (w__1 * (( 1000000000 : int):ii)) in + let ips = (inst_1e9 / elapsed) in state_monad$bindS (state_monad$seqS (state_monad$seqS + (dump_mips_state () ) + (dump_cp2_state () )) + (state_monad$read_regS instCount_ref)) (\ (w__2 : ii) . + let (_ : unit) = (print_int "Executed instructions: " w__2) in + let (_ : unit) = (print_int "Nanoseconds elapsed: " elapsed) in + state_monad$returnS ((print_int "Instructions per second: " ips))))))))`; + + +(*val initialize_registers : unit -> M unit*) + +val _ = Define ` + ((initialize_registers:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS PC_ref w__0) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__1 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS nextPC_ref w__1) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__2 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBProbe_ref w__2) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBIndex_ref w__3) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBRandom_ref w__4) + (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntryLo0_ref w__5) + (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntryLo1_ref w__6) + (undefined_ContextReg () )) (\ (w__7 : ContextReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBContext_ref w__7) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M)) (\ (w__8 : 16 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBPageMask_ref w__8) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBWired_ref w__9) + (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntryHi_ref w__10) + (undefined_XContextReg () )) (\ (w__11 : XContextReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBXContext_ref w__11) + (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry00_ref w__12) + (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry01_ref w__13) + (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry02_ref w__14) + (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry03_ref w__15) + (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry04_ref w__16) + (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry05_ref w__17) + (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry06_ref w__18) + (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry07_ref w__19) + (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry08_ref w__20) + (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry09_ref w__21) + (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry10_ref w__22) + (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry11_ref w__23) + (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry12_ref w__24) + (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry13_ref w__25) + (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry14_ref w__26) + (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry15_ref w__27) + (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry16_ref w__28) + (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry17_ref w__29) + (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry18_ref w__30) + (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry19_ref w__31) + (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry20_ref w__32) + (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry21_ref w__33) + (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry22_ref w__34) + (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry23_ref w__35) + (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry24_ref w__36) + (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry25_ref w__37) + (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry26_ref w__38) + (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry27_ref w__39) + (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry28_ref w__40) + (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry29_ref w__41) + (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry30_ref w__42) + (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry31_ref w__43) + (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry32_ref w__44) + (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry33_ref w__45) + (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry34_ref w__46) + (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry35_ref w__47) + (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry36_ref w__48) + (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry37_ref w__49) + (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry38_ref w__50) + (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry39_ref w__51) + (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry40_ref w__52) + (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry41_ref w__53) + (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry42_ref w__54) + (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry43_ref w__55) + (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry44_ref w__56) + (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry45_ref w__57) + (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry46_ref w__58) + (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry47_ref w__59) + (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry48_ref w__60) + (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry49_ref w__61) + (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry50_ref w__62) + (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry51_ref w__63) + (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry52_ref w__64) + (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry53_ref w__65) + (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry54_ref w__66) + (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry55_ref w__67) + (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry56_ref w__68) + (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry57_ref w__69) + (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry58_ref w__70) + (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry59_ref w__71) + (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry60_ref w__72) + (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry61_ref w__73) + (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry62_ref w__74) + (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS TLBEntry63_ref w__75) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__76 : 32 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0Compare_ref w__76) + (undefined_CauseReg () )) (\ (w__77 : CauseReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0Cause_ref w__77) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__78 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0EPC_ref w__78) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__79 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0ErrorEPC_ref w__79) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__80 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0LLBit_ref w__80) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__81 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0LLAddr_ref w__81) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__82 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0BadVAddr_ref w__82) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__83 : 32 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0Count_ref w__83) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__84 : 32 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0HWREna_ref w__84) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__85 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0UserLocal_ref w__85) + (undefined_StatusReg () )) (\ (w__86 : StatusReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CP0Status_ref w__86) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__87 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS branchPending_ref w__87) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__88 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS inBranchDelay_ref w__88) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__89 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS delayedPC_ref w__89) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__90 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS HI_ref w__90) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__91 : 64 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS LO_ref w__91) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__92 : 64 words$word) . state_monad$bindS + (undefined_vector (( 32 : int):ii) w__92 : ( ( 64 words$word)list) M) (\ (w__93 : ( 64 bits) list) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS GPR_ref w__93) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__94 : 8 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS UART_WDATA_ref w__94) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__95 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS UART_WRITTEN_ref w__95) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__96 : 8 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS UART_RDATA_ref w__96) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__97 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS UART_RVALID_ref w__97) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__98 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS PCC_ref w__98) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__99 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS nextPCC_ref w__99) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__100 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS delayedPCC_ref w__100) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__101 : 1 bits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS inCCallDelay_ref w__101) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__102 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C00_ref w__102) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__103 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C01_ref w__103) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__104 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C02_ref w__104) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__105 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C03_ref w__105) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__106 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C04_ref w__106) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__107 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C05_ref w__107) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__108 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C06_ref w__108) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__109 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C07_ref w__109) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__110 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C08_ref w__110) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__111 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C09_ref w__111) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__112 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C10_ref w__112) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__113 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C11_ref w__113) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__114 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C12_ref w__114) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__115 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C13_ref w__115) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__116 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C14_ref w__116) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__117 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C15_ref w__117) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__118 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C16_ref w__118) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__119 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C17_ref w__119) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__120 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C18_ref w__120) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__121 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C19_ref w__121) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__122 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C20_ref w__122) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__123 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C21_ref w__123) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__124 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C22_ref w__124) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__125 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C23_ref w__125) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__126 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C24_ref w__126) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__127 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C25_ref w__127) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__128 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C26_ref w__128) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__129 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C27_ref w__129) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__130 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C28_ref w__130) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__131 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C29_ref w__131) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__132 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C30_ref w__132) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__133 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS C31_ref w__133) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__134 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CTLSU_ref w__134) + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__135 : CapReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CTLSP_ref w__135) + (undefined_CapCauseReg () )) (\ (w__136 : CapCauseReg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS CapCause_ref w__136) + (undefined_int () )) (\ (w__137 : ii) . state_monad$write_regS instCount_ref w__137))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +val _ = Define ` +((initial_regstate:regstate)= + (<| instCount := ((( 0 : int):ii)); + CapCause := + (Mk_CapCauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)); + CTLSP := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + CTLSU := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C31 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C30 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C29 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C28 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C27 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C26 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C25 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C24 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C23 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C22 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C21 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C20 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C19 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C18 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C17 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C16 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C15 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C14 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C13 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C12 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C11 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C10 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C09 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C08 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C07 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C06 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C05 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C04 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C03 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C02 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C01 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + C00 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + inCCallDelay := ((vec_of_bits [B0] : 1 words$word)); + delayedPCC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + nextPCC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + PCC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + UART_RVALID := ((vec_of_bits [B0] : 1 words$word)); + UART_RDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)); + UART_WRITTEN := ((vec_of_bits [B0] : 1 words$word)); + UART_WDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)); + GPR := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + LO := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + HI := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + delayedPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + inBranchDelay := ((vec_of_bits [B0] : 1 words$word)); + branchPending := ((vec_of_bits [B0] : 1 words$word)); + CP0Status := + (Mk_StatusReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0UserLocal := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0HWREna := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0Count := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0BadVAddr := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0LLAddr := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0LLBit := ((vec_of_bits [B0] : 1 words$word)); + CP0ErrorEPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0EPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0Cause := + (Mk_CauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0Compare := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + TLBEntry63 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry62 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry61 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry60 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry59 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry58 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry57 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry56 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry55 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry54 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry53 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry52 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry51 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry50 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry49 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry48 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry47 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry46 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry45 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry44 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry43 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry42 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry41 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry40 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry39 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry38 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry37 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry36 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry35 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry34 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry33 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry32 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry31 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry30 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry29 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry28 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry27 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry26 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry25 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry24 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry23 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry22 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry21 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry20 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry19 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry18 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry17 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry16 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry15 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry14 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry13 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry12 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry11 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry10 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry09 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry08 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry07 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry06 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry05 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry04 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry03 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry02 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry01 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBEntry00 := + (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0] + : 117 words$word)); + TLBXContext := + (Mk_XContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + TLBEntryHi := + (Mk_TLBEntryHiReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : 64 words$word)); + TLBWired := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBPageMask := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)); + TLBContext := + (Mk_ContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + TLBEntryLo1 := + (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : 64 words$word)); + TLBEntryLo0 := + (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : 64 words$word)); + TLBRandom := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBIndex := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBProbe := ((vec_of_bits [B0] : 1 words$word)); + nextPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + PC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml b/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml deleted file mode 100644 index 3bc5ad50..00000000 --- a/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml +++ /dev/null @@ -1,9255 +0,0 @@ -(*Generated by Lem from cheri_sequential.lem.*) -open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory cheri_sequential_typesTheory mips_extras_sequentialTheory; - -val _ = numLib.prefer_num(); - - - -val _ = new_theory "cheri_sequential" - -(*Generated by Sail from cheri_sequential.*) -(*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import State_monad*) -(*open import State*) -(*open import Cheri_sequential_types*) -(*open import Mips_extras_sequential*) - -val _ = Define ` - ((cap_size:int)= ((( 32 : int):sail_values$ii)))`; - - -(*val undefined_option : forall 'a. 'a -> Cheri_sequential_types.M (Maybe.maybe 'a)*) - -val _ = Define ` - ((undefined_option:'a ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('a option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) typ_a= (seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`; - - - - - - - - -(*val neq_bool : bool -> bool -> bool*) - -val _ = Define ` - ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; - - - - - - -(*val builtin_and_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*) - - - -(*val builtin_or_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*) - - - -(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b= - ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; - - -(*val DecStr : Sail_values.ii -> string*) - -(*val HexStr : Sail_values.ii -> string*) - -(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width data= - (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) addr data))`; - - -(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) - -val _ = Define ` - ((MIPS_read:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) addr - : ( 'p8_times_n_ words$word) cheri_sequential_types$M)))`; - - - - -(*val undefined_exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.exception*) - -val _ = Define ` - ((undefined_exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (seqS -(undefined_unit () ) -(undefined_string () )) (\ (w__0 : string) . seqS (seqS (seqS -(undefined_unit () ) -(undefined_unit () )) -(undefined_unit () )) -(internal_pick - [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`; - - -(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -val _ = Define ` - ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; - - -val _ = Define ` - ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; - - -(*val zeros : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*) - -val _ = Define ` - ((zeros:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B0] : 1 words$word) n__tv : 'n words$word)))`; - - -(*val ones : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*) - -val _ = Define ` - ((ones:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B1] : 1 words$word) n__tv : 'n words$word)))`; - - - - - - - - - - -(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; - - -(*val bit_to_bool : Sail_values.bitU -> bool*) - -val _ = Define ` - ((bit_to_bool:sail_values$bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; - - -(*val bits_to_bool : Machine_word.mword Machine_word.ty1 -> bool*) - -val _ = Define ` - ((bits_to_bool:(1)words$word -> bool) x= (bit_to_bool ((access_vec_dec x (( 0 : int):sail_values$ii)))))`; - - -(*val to_bits : forall 'l. Size 'l => Machine_word.itself 'l -> Sail_values.ii -> Machine_word.mword 'l*) - -val _ = Define ` - ((to_bits:'l itself -> int -> 'l words$word) l n= - (let l = (size_itself_int l) in - (get_slice_int instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):sail_values$ii) : 'l words$word)))`; - - -(*val mask : forall 'm 'n . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'm -> Machine_word.mword 'n*) - -val _ = Define ` - ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs= - ((subrange_vec_dec bs ((n__tv - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii) : 'n words$word)))`; - - -(*val extzv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -val _ = Define ` - ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((extz_vec m__tv v : 'm words$word)))`; - - -(*val extsv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -val _ = Define ` - ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((exts_vec m__tv v : 'm words$word)))`; - - -(*val slice_mask : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*) - -val _ = Define ` - ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l= - (let (one1 : 'n cheri_sequential_types$bits) = ((extzv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in - (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`; - - -(*val is_zero_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) - -val _ = Define ` - ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= - (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0] : 1 words$word) : 'n words$word))))`; - - -(*val is_ones_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) - -val _ = Define ` - ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j= - (let (m : 'n cheri_sequential_types$bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i)) : 'n words$word)) in - (((and_vec xs m : 'n words$word)) = m)))`; - - -(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'r*) - -val _ = Define ` - ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'= - (let xs = -((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in - let ys = -((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l' : 'm words$word)) : 'm words$word)) i' - : 'm words$word)) in - (or_vec ((shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)) ((extzv r__tv ys : 'r words$word)) - : 'r words$word)))`; - - -(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Num.integer -> Num.integer -> Machine_word.mword 'r*) - -val _ = Define ` - ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'= - (let xs = -((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in - (shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)))`; - - -(*val subrange_subrange_eq : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*) - -val _ = Define ` - ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'= - (let xs = -((shiftr - ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j - : 'n words$word)) in - let ys = -((shiftr - ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j')) : 'n words$word)) : 'n words$word)) - j' - : 'n words$word)) in - (xs = ys)))`; - - -(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => Num.integer -> Machine_word.mword 'n -> Num.integer -> Num.integer -> Machine_word.mword 'm -> Num.integer -> Num.integer -> Machine_word.mword 's*) - -val _ = Define ` - ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'= - (let xs = -((shiftr - ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j - : 'n words$word)) in - let ys = -((shiftr - ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j')) : 'm words$word)) : 'm words$word)) - j' - : 'm words$word)) in - (or_vec - ((sub_vec_int ((shiftl ((extzv s__tv xs : 's words$word)) i' : 's words$word)) - ((j' - (( 1 : int):sail_values$ii))) - : 's words$word)) ((extzv s__tv ys : 's words$word)) - : 's words$word)))`; - - -(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) - -val _ = Define ` - ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift= - (let xs = -((shiftr - ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j - : 'n words$word)) in - (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; - - -(*val place_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) - -val _ = Define ` - ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift= - (let xs = -((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in - (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; - - -(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) - -val _ = Define ` - ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= - (let xs = -((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in - (extzv m__tv xs : 'm words$word)))`; - - -(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*) - -val _ = Define ` - ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= - (let xs = -((arith_shiftr - ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) - ((((((int_of_num (words$word_len xs))) - i)) - l)) - : 'n words$word)) ((((int_of_num (words$word_len xs))) - l)) - : 'n words$word)) in - (extsv m__tv xs : 'm words$word)))`; - - -(*val unsigned_slice : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*) - -val _ = Define ` - ((unsigned_slice:'n words$word -> int -> int -> int) xs i l= - (let xs = -((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in - lem$w2ui xs))`; - - -(*val unsigned_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*) - -val _ = Define ` - ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j= - (let xs = -((shiftr - ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) i - : 'n words$word)) in - lem$w2ui xs))`; - - -(*val zext_ones : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Machine_word.mword 'n*) - -val _ = Define ` - ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m= - (let (v : 'n cheri_sequential_types$bits) = ((extsv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in - (shiftr v ((((int_of_num (words$word_len v))) - m)) : 'n words$word)))`; - - -(*val undefined_CauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((undefined_CauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 words$word) . - internal_pick [Mk_CauseReg w__0])))`; - - -(*val _get_CauseReg : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32*) - -val _ = Define ` - ((get_CauseReg:cheri_sequential_types$CauseReg ->(32)words$word) (Mk_CauseReg (v))= v)`; - - -(*val _set_CauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_CauseReg v) in - write_regS r_ref r)))`; - - -(*val _get_CapCauseReg : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16*) - -(*val _set_CapCauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -(*val _get_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_CauseReg_BD : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_BD:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_CauseReg_CE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_CE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_CauseReg_IV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_IV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_CauseReg_WP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_WP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_CauseReg_IP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_IP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5*) - -val _ = Define ` - ((get_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)))`; - - -(*val _set_CauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_CauseReg r))))`; - - -(*val _update_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CauseReg*) - -val _ = Define ` - ((update_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _update_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*) - -(*val _get_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*) - -(*val _set_CapCauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -(*val undefined_TLBEntryLoReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((undefined_TLBEntryLoReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryLoReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_TLBEntryLoReg w__0])))`; - - -(*val _get_TLBEntryLoReg : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_TLBEntryLoReg:cheri_sequential_types$TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))= v)`; - - -(*val _set_TLBEntryLoReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_TLBEntryLoReg v) in - write_regS r_ref r)))`; - - -(*val _get_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntryLoReg_CapS : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_CapS:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntryLoReg_CapL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_CapL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24*) - -val _ = Define ` - ((get_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 24 words$word)))`; - - -(*val _set_TLBEntryLoReg_PFN : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_PFN:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3*) - -val _ = Define ` - ((get_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 3 words$word)))`; - - -(*val _set_TLBEntryLoReg_C : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_C:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntryLoReg_D : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_D:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntryLoReg_V : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_V:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntryLoReg_G : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryLoReg_G:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryLoReg r))))`; - - -(*val _update_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*) - -val _ = Define ` - ((update_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val undefined_TLBEntryHiReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryHiReg*) - -val _ = Define ` - ((undefined_TLBEntryHiReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryHiReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_TLBEntryHiReg w__0])))`; - - -(*val _get_TLBEntryHiReg : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_TLBEntryHiReg:cheri_sequential_types$TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))= v)`; - - -(*val _set_TLBEntryHiReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryHiReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_TLBEntryHiReg v) in - write_regS r_ref r)))`; - - -(*val _get_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_TLBEntryHiReg_R : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryHiReg_R:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryHiReg r))))`; - - -(*val _update_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntryHiReg*) - -val _ = Define ` - ((update_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27*) - -val _ = Define ` - ((get_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))= - ((subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))`; - - -(*val _set_TLBEntryHiReg_VPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryHiReg_VPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryHiReg r))))`; - - -(*val _update_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntryHiReg*) - -val _ = Define ` - ((update_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_TLBEntryHiReg_ASID : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntryHiReg_ASID:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_TLBEntryHiReg r))))`; - - -(*val _update_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntryHiReg*) - -val _ = Define ` - ((update_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val undefined_ContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.ContextReg*) - -val _ = Define ` - ((undefined_ContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_ContextReg w__0])))`; - - -(*val _get_ContextReg : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_ContextReg:cheri_sequential_types$ContextReg ->(64)words$word) (Mk_ContextReg (v))= v)`; - - -(*val _set_ContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_ContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_ContextReg v) in - write_regS r_ref r)))`; - - -(*val _get_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41*) - -val _ = Define ` - ((get_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 41 words$word)))`; - - -(*val _set_ContextReg_PTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_ContextReg_PTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(41)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . - let r = ((get_ContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_ContextReg r))))`; - - -(*val _update_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.ContextReg*) - -val _ = Define ` - ((update_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x= - (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19*) - -val _ = Define ` - ((get_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 19 words$word)))`; - - -(*val _set_ContextReg_BadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_ContextReg_BadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(19)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . - let r = ((get_ContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_ContextReg r))))`; - - -(*val _update_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.ContextReg*) - -val _ = Define ` - ((update_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x= - (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val undefined_XContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.XContextReg*) - -val _ = Define ` - ((undefined_XContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$XContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_XContextReg w__0])))`; - - -(*val _get_XContextReg : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_XContextReg:cheri_sequential_types$XContextReg ->(64)words$word) (Mk_XContextReg (v))= v)`; - - -(*val _set_XContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_XContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_XContextReg v) in - write_regS r_ref r)))`; - - -(*val _get_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31*) - -val _ = Define ` - ((get_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word) (Mk_XContextReg (v))= - ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) : 31 words$word)))`; - - -(*val _set_XContextReg_XPTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_XContextReg_XPTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(31)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_XContextReg r))))`; - - -(*val _update_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.XContextReg*) - -val _ = Define ` - ((update_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word) (Mk_XContextReg (v))= ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_XContextReg_XR : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_XContextReg_XR:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_XContextReg r))))`; - - -(*val _update_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.XContextReg*) - -val _ = Define ` - ((update_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27*) - -val _ = Define ` - ((get_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word) (Mk_XContextReg (v))= - ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 27 words$word)))`; - - -(*val _set_XContextReg_XBadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_XContextReg_XBadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_XContextReg r))))`; - - -(*val _update_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.XContextReg*) - -val _ = Define ` - ((update_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((TLBNumEntries:int)= ((( 64 : int):sail_values$ii)))`; - - -val _ = Define ` -((TLBIndexMax:(6)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))`; - - -(*val MAX : Num.integer -> Num.integer*) - -val _ = Define ` - ((MAX0:int -> int) n= (((pow2 n)) - (( 1 : int):sail_values$ii)))`; - - -val _ = Define ` - ((MAX_U64:int)= (MAX0 (( 64 : int):sail_values$ii)))`; - - -val _ = Define ` - ((MAX_VA:int)= (MAX0 (( 40 : int):sail_values$ii)))`; - - -val _ = Define ` - ((MAX_PA:int)= (MAX0 (( 36 : int):sail_values$ii)))`; - - -(*val undefined_TLBEntry : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((undefined_TLBEntry:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntry),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):sail_values$ii) : ( 117 words$word) cheri_sequential_types$M) (\ (w__0 : 117 words$word) . - internal_pick [Mk_TLBEntry w__0])))`; - - -(*val _get_TLBEntry : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117*) - -val _ = Define ` - ((get_TLBEntry:cheri_sequential_types$TLBEntry ->(117)words$word) (Mk_TLBEntry (v))= v)`; - - -(*val _set_TLBEntry : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(117)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_TLBEntry v) in - write_regS r_ref r)))`; - - -(*val _get_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16*) - -val _ = Define ` - ((get_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) : 16 words$word)))`; - - -(*val _set_TLBEntry_pagemask : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_pagemask:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_TLBEntry_r : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_r:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27*) - -val _ = Define ` - ((get_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) : 27 words$word)))`; - - -(*val _set_TLBEntry_vpn2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_vpn2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_TLBEntry_asid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_asid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_g : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_g:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_valid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_valid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_caps1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_caps1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_capl1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_capl1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*) - -val _ = Define ` - ((get_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) : 24 words$word)))`; - - -(*val _set_TLBEntry_pfn1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_pfn1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*) - -val _ = Define ` - ((get_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) : 3 words$word)))`; - - -(*val _set_TLBEntry_c1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_c1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_d1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_d1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_v1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_v1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_caps0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_caps0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_capl0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_capl0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*) - -val _ = Define ` - ((get_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 24 words$word)))`; - - -(*val _set_TLBEntry_pfn0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_pfn0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*) - -val _ = Define ` - ((get_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)))`; - - -(*val _set_TLBEntry_c0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_c0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_d0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_d0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 117 words$word))))`; - - -(*val _get_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_TLBEntry_v0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_TLBEntry_v0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 117 words$word)) in - write_regS r_ref (Mk_TLBEntry r))))`; - - -(*val _update_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*) - -val _ = Define ` - ((update_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 117 words$word))))`; - - -val _ = Define ` -((TLBEntries:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref)list)= - ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; - TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; - TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; - TLBEntry00_ref]))`; - - -(*val undefined_StatusReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((undefined_StatusReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$StatusReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 words$word) . - internal_pick [Mk_StatusReg w__0])))`; - - -(*val _get_StatusReg : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32*) - -val _ = Define ` - ((get_StatusReg:cheri_sequential_types$StatusReg ->(32)words$word) (Mk_StatusReg (v))= v)`; - - -(*val _set_StatusReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_StatusReg v) in - write_regS r_ref r)))`; - - -(*val _get_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4*) - -val _ = Define ` - ((get_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 4 words$word)))`; - - -(*val _set_StatusReg_CU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_CU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(4)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_BEV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_BEV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_StatusReg_IM : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_IM:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_KX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_KX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_SX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_SX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_UX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_UX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_StatusReg_KSU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_KSU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_ERL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_ERL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_EXL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_EXL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val _get_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_StatusReg_IE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_StatusReg_IE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 32 words$word)) in - write_regS r_ref (Mk_StatusReg r))))`; - - -(*val _update_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*) - -val _ = Define ` - ((update_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 32 words$word))))`; - - -(*val execute_branch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_branch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) pc= (seqS -(write_regS delayedPC_ref pc) (write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; - - -(*val NotWordVal : Machine_word.mword Machine_word.ty64 -> bool*) - -val _ = Define ` - ((NotWordVal:(64)words$word -> bool) word= - (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):sail_values$ii))) : 1 words$word)) (( 32 : int):sail_values$ii) - : 32 words$word)) <> ((subrange_vec_dec word (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word))))`; - - -(*val rGPR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((rGPR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx= - (let i = (lem$w2ui idx) in - if (((i = (( 0 : int):sail_values$ii)))) then - returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) - else bindS -(read_regS GPR_ref) (\ (w__0 : ( 64 cheri_sequential_types$bits) list) . - returnS ((access_list_dec w__0 i : 64 words$word)))))`; - - -(*val wGPR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((wGPR:(5)words$word ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx v= - (let i = (lem$w2ui idx) in - if (((i = (( 0 : int):sail_values$ii)))) then returnS () - else bindS -(read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . - write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list)))))`; - - - - - - - - - - - - - - - - -(*val Exception_of_num : Num.integer -> Cheri_sequential_types.Exception*) - -val _ = Define ` - ((Exception_of_num:int -> cheri_sequential_types$Exception) arg_= - (let l__81 = arg_ in - if (((l__81 = (( 0 : int):sail_values$ii)))) then Interrupt - else if (((l__81 = (( 1 : int):sail_values$ii)))) then TLBMod - else if (((l__81 = (( 2 : int):sail_values$ii)))) then TLBL - else if (((l__81 = (( 3 : int):sail_values$ii)))) then TLBS - else if (((l__81 = (( 4 : int):sail_values$ii)))) then AdEL - else if (((l__81 = (( 5 : int):sail_values$ii)))) then AdES - else if (((l__81 = (( 6 : int):sail_values$ii)))) then Sys - else if (((l__81 = (( 7 : int):sail_values$ii)))) then Bp - else if (((l__81 = (( 8 : int):sail_values$ii)))) then ResI - else if (((l__81 = (( 9 : int):sail_values$ii)))) then CpU - else if (((l__81 = (( 10 : int):sail_values$ii)))) then Ov - else if (((l__81 = (( 11 : int):sail_values$ii)))) then Tr - else if (((l__81 = (( 12 : int):sail_values$ii)))) then C2E - else if (((l__81 = (( 13 : int):sail_values$ii)))) then C2Trap - else if (((l__81 = (( 14 : int):sail_values$ii)))) then XTLBRefillL - else if (((l__81 = (( 15 : int):sail_values$ii)))) then XTLBRefillS - else if (((l__81 = (( 16 : int):sail_values$ii)))) then XTLBInvL - else if (((l__81 = (( 17 : int):sail_values$ii)))) then XTLBInvS - else MCheck))`; - - -(*val num_of_Exception : Cheri_sequential_types.Exception -> Num.integer*) - -val _ = Define ` - ((num_of_Exception:cheri_sequential_types$Exception -> int) arg_= - ((case arg_ of - Interrupt => (( 0 : int):sail_values$ii) - | TLBMod => (( 1 : int):sail_values$ii) - | TLBL => (( 2 : int):sail_values$ii) - | TLBS => (( 3 : int):sail_values$ii) - | AdEL => (( 4 : int):sail_values$ii) - | AdES => (( 5 : int):sail_values$ii) - | Sys => (( 6 : int):sail_values$ii) - | Bp => (( 7 : int):sail_values$ii) - | ResI => (( 8 : int):sail_values$ii) - | CpU => (( 9 : int):sail_values$ii) - | Ov => (( 10 : int):sail_values$ii) - | Tr => (( 11 : int):sail_values$ii) - | C2E => (( 12 : int):sail_values$ii) - | C2Trap => (( 13 : int):sail_values$ii) - | XTLBRefillL => (( 14 : int):sail_values$ii) - | XTLBRefillS => (( 15 : int):sail_values$ii) - | XTLBInvL => (( 16 : int):sail_values$ii) - | XTLBInvS => (( 17 : int):sail_values$ii) - | MCheck => (( 18 : int):sail_values$ii) - )))`; - - -(*val undefined_Exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.Exception*) - -val _ = Define ` - ((undefined_Exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = - (internal_pick - [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`; - - -(*val ExceptionCode : Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty5*) - -val _ = Define ` - ((ExceptionCode:cheri_sequential_types$Exception ->(5)words$word) ex= - (let (x : 8 cheri_sequential_types$bits) = -((case ex of - Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) - | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) - | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) - | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) - | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) - | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) - | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) - | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) - | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) - | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word) - | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word) - | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word) - | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) - | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) - | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) - | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) - | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) - | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) - | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) - )) in - (subrange_vec_dec x (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)))`; - - -(*val SignalExceptionMIPS : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) - -val _ = Define ` - ((SignalExceptionMIPS:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex kccBase= (bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS (seqS - (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then bindS - (read_regS inBranchDelay_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) . - if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . seqS -(write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):sail_values$ii) : 64 words$word))) -(set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : 1 words$word))) - else bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . seqS -(write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) - else returnS () ) -(read_regS CP0Status_ref)) (\ (w__4 : cheri_sequential_types$StatusReg) . - let vectorOffset = -(if ((bits_to_bool ((get_StatusReg_EXL w__4 : 1 words$word)))) then - (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then - (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in bindS -(read_regS CP0Status_ref) (\ (w__5 : cheri_sequential_types$StatusReg) . - let (vectorBase : 64 cheri_sequential_types$bits) = -(if ((bits_to_bool ((get_StatusReg_BEV w__5 : 1 words$word)))) then - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) - else - (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)) in seqS (seqS (seqS -(write_regS - nextPC_ref - ((sub_vec - ((add_vec vectorBase ((sign_extend1 (( 64 : int):sail_values$ii) vectorOffset : 64 words$word)) : 64 words$word)) - kccBase - : 64 words$word))) -(set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex : 5 words$word)))) -(set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (throwS (ISAException () )))))))`; - - -(*val SignalException : forall 'o. Cheri_sequential_types.Exception -> Cheri_sequential_types.M 'o*) - -(*val SignalExceptionBadAddr : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) - -(*val capRegToCapStruct : Machine_word.mword Machine_word.ty257 -> Cheri_sequential_types.CapStruct*) - -val _ = Define ` - ((capRegToCapStruct:(257)words$word -> cheri_sequential_types$CapStruct) capReg= - (<| CapStruct_tag := ((bit_to_bool ((access_vec_dec capReg (( 256 : int):sail_values$ii))))); - CapStruct_padding := ((subrange_vec_dec capReg (( 255 : int):sail_values$ii) (( 248 : int):sail_values$ii) : 8 words$word)); - CapStruct_otype := ((subrange_vec_dec capReg (( 247 : int):sail_values$ii) (( 224 : int):sail_values$ii) : 24 words$word)); - CapStruct_uperms := ((subrange_vec_dec capReg (( 223 : int):sail_values$ii) (( 208 : int):sail_values$ii) : 16 words$word)); - CapStruct_perm_reserved11_14 := ((subrange_vec_dec capReg (( 207 : int):sail_values$ii) (( 204 : int):sail_values$ii) : 4 words$word)); - CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec capReg (( 203 : int):sail_values$ii))))); - CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec capReg (( 202 : int):sail_values$ii))))); - CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec capReg (( 201 : int):sail_values$ii))))); - CapStruct_permit_seal := ((bit_to_bool ((access_vec_dec capReg (( 200 : int):sail_values$ii))))); - CapStruct_permit_store_local_cap := ((bit_to_bool ((access_vec_dec capReg (( 199 : int):sail_values$ii))))); - CapStruct_permit_store_cap := ((bit_to_bool ((access_vec_dec capReg (( 198 : int):sail_values$ii))))); - CapStruct_permit_load_cap := ((bit_to_bool ((access_vec_dec capReg (( 197 : int):sail_values$ii))))); - CapStruct_permit_store := ((bit_to_bool ((access_vec_dec capReg (( 196 : int):sail_values$ii))))); - CapStruct_permit_load := ((bit_to_bool ((access_vec_dec capReg (( 195 : int):sail_values$ii))))); - CapStruct_permit_execute := ((bit_to_bool ((access_vec_dec capReg (( 194 : int):sail_values$ii))))); - CapStruct_global := ((bit_to_bool ((access_vec_dec capReg (( 193 : int):sail_values$ii))))); - CapStruct_sealed := ((bit_to_bool ((access_vec_dec capReg (( 192 : int):sail_values$ii))))); - CapStruct_address := ((subrange_vec_dec capReg (( 191 : int):sail_values$ii) (( 128 : int):sail_values$ii) : 64 words$word)); - CapStruct_base := ((subrange_vec_dec capReg (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word)); - CapStruct_length := ((subrange_vec_dec capReg (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) |>))`; - - -(*val getCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31*) - -val _ = Define ` - ((getCapPerms:cheri_sequential_types$CapStruct ->(31)words$word) cap= - ((concat_vec cap.CapStruct_uperms - ((concat_vec cap.CapStruct_perm_reserved11_14 - ((concat_vec ((bool_to_bits cap.CapStruct_access_system_regs : 1 words$word)) - ((concat_vec ((bool_to_bits cap.CapStruct_permit_unseal : 1 words$word)) - ((concat_vec ((bool_to_bits cap.CapStruct_permit_ccall : 1 words$word)) - ((concat_vec ((bool_to_bits cap.CapStruct_permit_seal : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_store_local_cap : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_store_cap : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_load_cap : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_store : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_load : 1 words$word)) - ((concat_vec - ((bool_to_bits cap.CapStruct_permit_execute - : 1 words$word)) - ((bool_to_bits cap.CapStruct_global : 1 words$word)) - : 2 words$word)) - : 3 words$word)) - : 4 words$word)) - : 5 words$word)) - : 6 words$word)) - : 7 words$word)) - : 8 words$word)) - : 9 words$word)) - : 10 words$word)) - : 11 words$word)) - : 15 words$word)) - : 31 words$word)))`; - - -(*val capStructToMemBits256 : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*) - -val _ = Define ` - ((capStructToMemBits256:cheri_sequential_types$CapStruct ->(256)words$word) cap= - ((concat_vec cap.CapStruct_padding - ((concat_vec cap.CapStruct_otype - ((concat_vec ((getCapPerms cap : 31 words$word)) - ((concat_vec ((bool_to_bits cap.CapStruct_sealed : 1 words$word)) - ((concat_vec cap.CapStruct_address - ((concat_vec cap.CapStruct_base cap.CapStruct_length : 128 words$word)) - : 192 words$word)) - : 193 words$word)) - : 224 words$word)) - : 248 words$word)) - : 256 words$word)))`; - - -(*val capStructToCapReg : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty257*) - -val _ = Define ` - ((capStructToCapReg:cheri_sequential_types$CapStruct ->(257)words$word) cap= - ((concat_vec ((bool_to_bits cap.CapStruct_tag : 1 words$word)) - ((capStructToMemBits256 cap : 256 words$word)) - : 257 words$word)))`; - - -(*val getCapBase : Cheri_sequential_types.CapStruct -> Num.integer*) - -val _ = Define ` - ((getCapBase:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_base))`; - - -val _ = Define ` -((null_cap:cheri_sequential_types$CapStruct)= - (<| CapStruct_tag := F; - CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) () : 8 words$word)); - CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); - CapStruct_uperms := ((zeros (( 16 : int):sail_values$ii) () : 16 words$word)); - CapStruct_perm_reserved11_14 := ((zeros (( 4 : int):sail_values$ii) () : 4 words$word)); - CapStruct_access_system_regs := F; - CapStruct_permit_unseal := F; - CapStruct_permit_ccall := F; - CapStruct_permit_seal := F; - CapStruct_permit_store_local_cap := F; - CapStruct_permit_store_cap := F; - CapStruct_permit_load_cap := F; - CapStruct_permit_store := F; - CapStruct_permit_load := F; - CapStruct_permit_execute := F; - CapStruct_global := F; - CapStruct_sealed := F; - CapStruct_address := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); - CapStruct_base := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); - CapStruct_length := -((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1] - : 64 words$word)) |>))`; - - -(*val int_to_cap : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.CapStruct*) - -val _ = Define ` - ((int_to_cap:(64)words$word -> cheri_sequential_types$CapStruct) address= ((null_cap with<| CapStruct_address := address|>)))`; - - -(*val setCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*) - -val _ = Define ` - ((setCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c offset= - (T, (c with<| CapStruct_address := ((add_vec c.CapStruct_base offset : 64 words$word))|>)))`; - - -val _ = Define ` - ((SignalException:cheri_sequential_types$Exception ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex= (bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS (seqS - (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ pc . bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . - let pcc = (capRegToCapStruct w__1) in - let (success, epcc) = (setCapOffset pcc pc) in - if success then write_regS C31_ref ((capStructToCapReg epcc : 257 words$word)) - else - write_regS - C31_ref - ((capStructToCapReg - ((int_to_cap - ((add_vec_int - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase pcc)) - : 64 words$word)) ((lem$w2ui pc)) - : 64 words$word)))) - : 257 words$word)))) - else returnS () ) - (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__2 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS nextPCC_ref w__2) - (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS delayedPCC_ref w__3) - (read_regS C29_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__4 : 257 words$word) . - let base = (getCapBase ((capRegToCapStruct w__4))) in - SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) base : 64 words$word))))))))`; - - -val _ = Define ` - ((SignalExceptionBadAddr:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr= (seqS (write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; - - -(*val SignalExceptionTLB : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*) - -val _ = Define ` - ((SignalExceptionTLB:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr= (seqS (seqS (seqS (seqS (seqS (seqS -(write_regS CP0BadVAddr_ref badAddr) -(set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 19 words$word)))) -(set_XContextReg_XBadVPN2 TLBXContext_ref - ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))) -(set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))) -(set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))) -(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)))) -(SignalException ex)))`; - - -(*val MemAccessType_of_num : Num.integer -> Cheri_sequential_types.MemAccessType*) - -val _ = Define ` - ((MemAccessType_of_num:int -> cheri_sequential_types$MemAccessType) arg_= - (let l__79 = arg_ in - if (((l__79 = (( 0 : int):sail_values$ii)))) then Instruction - else if (((l__79 = (( 1 : int):sail_values$ii)))) then LoadData - else StoreData))`; - - -(*val num_of_MemAccessType : Cheri_sequential_types.MemAccessType -> Num.integer*) - -val _ = Define ` - ((num_of_MemAccessType:cheri_sequential_types$MemAccessType -> int) arg_= - ((case arg_ of Instruction => (( 0 : int):sail_values$ii) | LoadData => (( 1 : int):sail_values$ii) | StoreData => (( 2 : int):sail_values$ii) )))`; - - -(*val undefined_MemAccessType : unit -> Cheri_sequential_types.M Cheri_sequential_types.MemAccessType*) - -val _ = Define ` - ((undefined_MemAccessType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$MemAccessType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [Instruction;LoadData;StoreData]))`; - - -(*val AccessLevel_of_num : Num.integer -> Cheri_sequential_types.AccessLevel*) - -val _ = Define ` - ((AccessLevel_of_num:int -> cheri_sequential_types$AccessLevel) arg_= - (let l__77 = arg_ in - if (((l__77 = (( 0 : int):sail_values$ii)))) then User - else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor - else Kernel))`; - - -(*val num_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Num.integer*) - -val _ = Define ` - ((num_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) arg_= - ((case arg_ of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`; - - -(*val undefined_AccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*) - -val _ = Define ` - ((undefined_AccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [User;Supervisor;Kernel]))`; - - -(*val int_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Sail_values.ii*) - -val _ = Define ` - ((int_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) level= - ((case level of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`; - - -(*val grantsAccess : Cheri_sequential_types.AccessLevel -> Cheri_sequential_types.AccessLevel -> bool*) - -val _ = Define ` - ((grantsAccess:cheri_sequential_types$AccessLevel -> cheri_sequential_types$AccessLevel -> bool) currentLevel requiredLevel= - (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`; - - -(*val getAccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*) - -val _ = Define ` - ((getAccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . bindS -(read_regS CP0Status_ref) (\ (w__1 : cheri_sequential_types$StatusReg) . - if (((((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))) \/ ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) then - returnS Kernel - else bindS -(read_regS CP0Status_ref) (\ (w__2 : cheri_sequential_types$StatusReg) . - let p__132 = ((get_StatusReg_KSU w__2 : 2 words$word)) in - let b__0 = p__132 in - returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor - else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then User - else User))))))`; - - -(*val checkCP0Access : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((checkCP0Access:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(getAccessLevel () ) (\ accessLevel . bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - if ((((((accessLevel <> Kernel))) /\ ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):sail_values$ii)))))))))) - then seqS -(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : 2 words$word)) (SignalException CpU) - else returnS () ))))`; - - -(*val incrementCP0Count : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((incrementCP0Count:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$TLBIndexT) . bindS - (read_regS TLBWired_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__1 : 6 words$word) . bindS - (if (((w__0 = w__1))) then returnS TLBIndexMax - else bindS - (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) (\ (w__2 : 6 words$word) . - returnS ((sub_vec_int w__2 (( 1 : int):sail_values$ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . bindS (seqS -(write_regS TLBRandom_ref w__3) - (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M)) (\ (w__4 : 32 words$word) . bindS (seqS -(write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):sail_values$ii) : 32 words$word))) - (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M)) (\ (w__5 : 32 cheri_sequential_types$bits) . bindS - (read_regS CP0Compare_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__6 : 32 words$word) . bindS (seqS - (if (((w__5 = w__6))) then bindS -(read_regS CP0Cause_ref) (\ (w__7 : cheri_sequential_types$CauseReg) . - set_CauseReg_IP CP0Cause_ref - ((or_vec ((get_CauseReg_IP w__7 : 8 words$word)) - (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) - : 8 words$word))) - else returnS () ) -(read_regS CP0Status_ref)) (\ (w__8 : cheri_sequential_types$StatusReg) . - let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in bindS -(read_regS CP0Cause_ref) (\ (w__9 : cheri_sequential_types$CauseReg) . - let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in bindS -(read_regS CP0Status_ref) (\ (w__10 : cheri_sequential_types$StatusReg) . - let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in bindS -(read_regS CP0Status_ref) (\ (w__11 : cheri_sequential_types$StatusReg) . - let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in bindS -(read_regS CP0Status_ref) (\ (w__12 : cheri_sequential_types$StatusReg) . - let erl = ((get_StatusReg_ERL w__12 : 1 words$word)) in - if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))))))))) then - SignalException Interrupt - else returnS () )))))))))))))`; - - -(*val decode_failure_of_num : Num.integer -> Cheri_sequential_types.decode_failure*) - -val _ = Define ` - ((decode_failure_of_num:int -> cheri_sequential_types$decode_failure) arg_= - (let l__74 = arg_ in - if (((l__74 = (( 0 : int):sail_values$ii)))) then No_matching_pattern - else if (((l__74 = (( 1 : int):sail_values$ii)))) then Unsupported_instruction - else if (((l__74 = (( 2 : int):sail_values$ii)))) then Illegal_instruction - else Internal_error))`; - - -(*val num_of_decode_failure : Cheri_sequential_types.decode_failure -> Num.integer*) - -val _ = Define ` - ((num_of_decode_failure:cheri_sequential_types$decode_failure -> int) arg_= - ((case arg_ of no_matching_pattern => (( 0 : int): sail_values$ii) )))`; - - -(*val undefined_decode_failure : unit -> Cheri_sequential_types.M Cheri_sequential_types.decode_failure*) - -val _ = Define ` - ((undefined_decode_failure:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$decode_failure),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = - (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; - - -(*val Comparison_of_num : Num.integer -> Cheri_sequential_types.Comparison*) - -val _ = Define ` - ((Comparison_of_num:int -> cheri_sequential_types$Comparison) arg_= - (let l__67 = arg_ in - if (((l__67 = (( 0 : int):sail_values$ii)))) then EQ' - else if (((l__67 = (( 1 : int):sail_values$ii)))) then NE - else if (((l__67 = (( 2 : int):sail_values$ii)))) then GE - else if (((l__67 = (( 3 : int):sail_values$ii)))) then GEU - else if (((l__67 = (( 4 : int):sail_values$ii)))) then GT' - else if (((l__67 = (( 5 : int):sail_values$ii)))) then LE - else if (((l__67 = (( 6 : int):sail_values$ii)))) then LT' - else LTU))`; - - -(*val num_of_Comparison : Cheri_sequential_types.Comparison -> Num.integer*) - -val _ = Define ` - ((num_of_Comparison:cheri_sequential_types$Comparison -> int) arg_= - ((case arg_ of - EQ' => (( 0 : int):sail_values$ii) - | NE => (( 1 : int):sail_values$ii) - | GE => (( 2 : int):sail_values$ii) - | GEU => (( 3 : int):sail_values$ii) - | GT' => (( 4 : int):sail_values$ii) - | LE => (( 5 : int):sail_values$ii) - | LT' => (( 6 : int):sail_values$ii) - | LTU => (( 7 : int):sail_values$ii) - )))`; - - -(*val undefined_Comparison : unit -> Cheri_sequential_types.M Cheri_sequential_types.Comparison*) - -val _ = Define ` - ((undefined_Comparison:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Comparison),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; - - -(*val compare : Cheri_sequential_types.Comparison -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> bool*) - -val _ = Define ` - ((compare:cheri_sequential_types$Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB= - ((case cmp of - EQ' => (valA = valB) - | NE => (valA <> valB) - | GE => ((integer_word$w2i valA) >= (integer_word$w2i valB)) - | GEU => ((lem$w2ui valA) >= (lem$w2ui valB)) - | GT' => ((integer_word$w2i valB) < (integer_word$w2i valA)) - | LE => ((integer_word$w2i valB) >= (integer_word$w2i valA)) - | LT' => ((integer_word$w2i valA) < (integer_word$w2i valB)) - | LTU => ((lem$w2ui valA) < (lem$w2ui valB)) - )))`; - - -(*val WordType_of_num : Num.integer -> Cheri_sequential_types.WordType*) - -val _ = Define ` - ((WordType_of_num:int -> cheri_sequential_types$WordType) arg_= - (let l__64 = arg_ in - if (((l__64 = (( 0 : int):sail_values$ii)))) then B - else if (((l__64 = (( 1 : int):sail_values$ii)))) then H - else if (((l__64 = (( 2 : int):sail_values$ii)))) then W0 - else D))`; - - -(*val num_of_WordType : Cheri_sequential_types.WordType -> Num.integer*) - -val _ = Define ` - ((num_of_WordType:cheri_sequential_types$WordType -> int) arg_= - ((case arg_ of B => (( 0 : int):sail_values$ii) | H => (( 1 : int):sail_values$ii) | W0 => (( 2 : int):sail_values$ii) | D => (( 3 : int):sail_values$ii) )))`; - - -(*val undefined_WordType : unit -> Cheri_sequential_types.M Cheri_sequential_types.WordType*) - -val _ = Define ` - ((undefined_WordType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$WordType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [B;H;W0;D]))`; - - -(*val wordWidthBytes : Cheri_sequential_types.WordType -> Num.integer*) - -val _ = Define ` - ((wordWidthBytes:cheri_sequential_types$WordType -> int) w= ((case w of B => (( 1 : int):sail_values$ii) | H => (( 2 : int):sail_values$ii) | W0 => (( 4 : int):sail_values$ii) | D => (( 8 : int):sail_values$ii) )))`; - - -val _ = Define ` - ((alignment_width:int)= ((( 16 : int):sail_values$ii)))`; - - -(*val isAddressAligned : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.WordType -> bool*) - -val _ = Define ` - ((isAddressAligned:(64)words$word -> cheri_sequential_types$WordType -> bool) addr wordType= - (let a = (lem$w2ui addr) in - (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):sail_values$ii))) / - alignment_width)))))`; - - -(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) - -val _ = Define ` - ((MEMr_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1= (bindS - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . - returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; - - -(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*) - -val _ = Define ` - ((MEMr_reserve_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1= (bindS - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . - returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; - - -(*val init_cp0_state : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((init_cp0_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; - - -(*val init_cp2_state : unit -> Cheri_sequential_types.M unit*) - -(*val cp2_next_pc : unit -> Cheri_sequential_types.M unit*) - -(*val dump_cp2_state : unit -> Cheri_sequential_types.M unit*) - -(*val tlbEntryMatch : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty27 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry -> bool*) - -val _ = Define ` - ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> cheri_sequential_types$TLBEntry -> bool) r vpn2 asid entry= - (let entryValid = ((get_TLBEntry_valid entry : 1 words$word)) in - let entryR = ((get_TLBEntry_r entry : 2 words$word)) in - let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in - let entryVPN = ((get_TLBEntry_vpn2 entry : 27 words$word)) in - let entryASID = ((get_TLBEntry_asid entry : 8 words$word)) in - let entryG = ((get_TLBEntry_g entry : 1 words$word)) in - let (vpnMask : 27 cheri_sequential_types$bits) = -((not_vec ((zero_extend1 (( 27 : int):sail_values$ii) entryMask : 27 words$word)) : 27 words$word)) in - (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask : 27 words$word)) = ((and_vec entryVPN vpnMask : 27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`; - - -(*val tlbSearch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Maybe.maybe (Machine_word.mword Machine_word.ty6))*) - -val _ = Define ` - ((tlbSearch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((((6)words$word)option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) VAddr= - (catch_early_returnS - (let r = ((subrange_vec_dec VAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)) in - let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 27 words$word)) in bindS -(liftRS (read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . - let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in seqS - (foreachS (index_list (( 0 : int):sail_values$ii) (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () - (\ idx unit_var . bindS -(liftRS (read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : cheri_sequential_types$TLBEntry) . - if ((tlbEntryMatch r vpn2 asid w__1)) then - (early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):sail_values$ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) - cheri_sequential_types$MR) - else returnS () ))) -(returnS NONE)))))`; - - -(*val TLBTranslate2 : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*) - -val _ = Define ` - ((TLBTranslate2:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS - (tlbSearch vAddr : ( ( 6 words$word)option) cheri_sequential_types$M) (\ idx . - (case idx of - SOME (idx) => - let i = (lem$w2ui idx) in bindS -(read_regS ((access_list_dec TLBEntries i))) (\ entry . - let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in - let b__0 = entryMask in bindS - (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then - returnS (( 12 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) - then - returnS (( 14 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 16 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 18 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 20 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 22 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 24 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 26 : int):sail_values$ii) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) - then - returnS (( 28 : int):sail_values$ii) - else undefined_range (( 12 : int):sail_values$ii) (( 28 : int):sail_values$ii)) (\ (evenOddBit : int) . - let isOdd = (access_vec_dec vAddr evenOddBit) in - let ((caps : 1 cheri_sequential_types$bits), (capl : 1 cheri_sequential_types$bits), (pfn : 24 cheri_sequential_types$bits), (d : 1 cheri_sequential_types$bits), (v : 1 cheri_sequential_types$bits)) = -(if ((bit_to_bool isOdd)) then - ((get_TLBEntry_caps1 entry : 1 words$word), - (get_TLBEntry_capl1 entry : 1 words$word), - (get_TLBEntry_pfn1 entry : 24 words$word), - (get_TLBEntry_d1 entry : 1 words$word), - (get_TLBEntry_v1 entry : 1 words$word)) - else - ((get_TLBEntry_caps0 entry : 1 words$word), - (get_TLBEntry_capl0 entry : 1 words$word), - (get_TLBEntry_pfn0 entry : 24 words$word), - (get_TLBEntry_d0 entry : 1 words$word), - (get_TLBEntry_v0 entry : 1 words$word))) in - if ((~ ((bits_to_bool v)))) then - (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr - : (( 64 words$word # bool)) cheri_sequential_types$M) - else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then - (SignalExceptionTLB TLBMod vAddr : (( 64 words$word # bool)) cheri_sequential_types$M) - else - let (res : 64 cheri_sequential_types$bits) = -((zero_extend1 (( 64 : int):sail_values$ii) - ((subrange_subrange_concat - (((((((( 23 : int):sail_values$ii) - - ((((evenOddBit - (( 12 : int):sail_values$ii))) - (( 1 : int):sail_values$ii))))) - + - ((evenOddBit - (( 1 : int):sail_values$ii))))) - - (((( 0 : int):sail_values$ii) - (( 1 : int):sail_values$ii))))) pfn - (( 23 : int):sail_values$ii) ((evenOddBit - (( 12 : int):sail_values$ii))) vAddr - ((evenOddBit - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii) - : 36 words$word)) - : 64 words$word)) in - returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) - | NONE => - (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr - : (( 64 words$word # bool)) cheri_sequential_types$M) - ))))`; - - -(*val TLBTranslateC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*) - -val _ = Define ` - ((TLBTranslateC:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS -(getAccessLevel () ) (\ currentAccessLevel . - let compat32 = - (((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 31 : int):sail_values$ii) : 31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] - : 31 words$word)) in - let b__0 = ((subrange_vec_dec vAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)) in - let ((requiredLevel : cheri_sequential_types$AccessLevel), (addr : ( 64 cheri_sequential_types$bits)option)) = -(if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then - (case (compat32, (subrange_vec_dec vAddr (( 30 : int):sail_values$ii) (( 29 : int):sail_values$ii) : 2 words$word)) of - (T, b__1) => - if (((b__1 = (vec_of_bits [B1;B1] : 2 words$word)))) then (Kernel, NONE) - else if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then (Supervisor, NONE) - else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then - (Kernel, - SOME ((concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word) - ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) - ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 29 words$word)) - : 32 words$word)) - : 64 words$word))) - else - (Kernel, - SOME ((concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word) - ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) - ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 29 words$word)) - : 32 words$word)) - : 64 words$word))) - | (g__130, g__131) => (Kernel, NONE) - ) - else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then - (Kernel, - SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) - ((subrange_vec_dec vAddr (( 58 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 59 words$word)) - : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then (Supervisor, NONE) - else (User, NONE)) in - if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then - (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr - : (( 64 words$word # bool)) cheri_sequential_types$M) - else bindS - (case addr of - SOME (a) => returnS (a, F) - | NONE => - if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 62 words$word)))) > MAX_VA))))) then - (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr - : (( 64 words$word # bool)) cheri_sequential_types$M) - else (TLBTranslate2 vAddr accessType : (( 64 words$word # bool)) cheri_sequential_types$M) - ) (\ varstup . let ((pa : 64 cheri_sequential_types$bits), (c : bool)) = varstup in - if ((((lem$w2ui pa)) > MAX_PA)) then - (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr - : (( 64 words$word # bool)) cheri_sequential_types$M) - else returnS (pa, c)))))`; - - -(*val TLBTranslate : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((TLBTranslate:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType= (bindS - (TLBTranslateC vAddr accessType : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (addr, c) = varstup in - returnS addr)))`; - - -(*val CPtrCmpOp_of_num : Num.integer -> Cheri_sequential_types.CPtrCmpOp*) - -val _ = Define ` - ((CPtrCmpOp_of_num:int -> cheri_sequential_types$CPtrCmpOp) arg_= - (let l__57 = arg_ in - if (((l__57 = (( 0 : int):sail_values$ii)))) then CEQ - else if (((l__57 = (( 1 : int):sail_values$ii)))) then CNE - else if (((l__57 = (( 2 : int):sail_values$ii)))) then CLT - else if (((l__57 = (( 3 : int):sail_values$ii)))) then CLE - else if (((l__57 = (( 4 : int):sail_values$ii)))) then CLTU - else if (((l__57 = (( 5 : int):sail_values$ii)))) then CLEU - else if (((l__57 = (( 6 : int):sail_values$ii)))) then CEXEQ - else CNEXEQ))`; - - -(*val num_of_CPtrCmpOp : Cheri_sequential_types.CPtrCmpOp -> Num.integer*) - -val _ = Define ` - ((num_of_CPtrCmpOp:cheri_sequential_types$CPtrCmpOp -> int) arg_= - ((case arg_ of - CEQ => (( 0 : int):sail_values$ii) - | CNE => (( 1 : int):sail_values$ii) - | CLT => (( 2 : int):sail_values$ii) - | CLE => (( 3 : int):sail_values$ii) - | CLTU => (( 4 : int):sail_values$ii) - | CLEU => (( 5 : int):sail_values$ii) - | CEXEQ => (( 6 : int):sail_values$ii) - | CNEXEQ => (( 7 : int):sail_values$ii) - )))`; - - -(*val undefined_CPtrCmpOp : unit -> Cheri_sequential_types.M Cheri_sequential_types.CPtrCmpOp*) - -val _ = Define ` - ((undefined_CPtrCmpOp:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CPtrCmpOp),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`; - - -(*val ClearRegSet_of_num : Num.integer -> Cheri_sequential_types.ClearRegSet*) - -val _ = Define ` - ((ClearRegSet_of_num:int -> cheri_sequential_types$ClearRegSet) arg_= - (let l__54 = arg_ in - if (((l__54 = (( 0 : int):sail_values$ii)))) then GPLo - else if (((l__54 = (( 1 : int):sail_values$ii)))) then GPHi - else if (((l__54 = (( 2 : int):sail_values$ii)))) then CLo - else CHi))`; - - -(*val num_of_ClearRegSet : Cheri_sequential_types.ClearRegSet -> Num.integer*) - -val _ = Define ` - ((num_of_ClearRegSet:cheri_sequential_types$ClearRegSet -> int) arg_= - ((case arg_ of GPLo => (( 0 : int):sail_values$ii) | GPHi => (( 1 : int):sail_values$ii) | CLo => (( 2 : int):sail_values$ii) | CHi => (( 3 : int):sail_values$ii) )))`; - - -(*val undefined_ClearRegSet : unit -> Cheri_sequential_types.M Cheri_sequential_types.ClearRegSet*) - -val _ = Define ` - ((undefined_ClearRegSet:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ClearRegSet),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (internal_pick [GPLo;GPHi;CLo;CHi]))`; - - -(*val undefined_CapStruct : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*) - -val _ = Define ` - ((undefined_CapStruct:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(undefined_bool0 () ) (\ (w__0 : bool) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 : 8 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):sail_values$ii) : ( 24 words$word) cheri_sequential_types$M) (\ (w__2 : 24 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 : 16 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):sail_values$ii) : ( 4 words$word) cheri_sequential_types$M) (\ (w__4 : 4 cheri_sequential_types$bits) . bindS -(undefined_bool0 () ) (\ (w__5 : bool) . bindS -(undefined_bool0 () ) (\ (w__6 : bool) . bindS -(undefined_bool0 () ) (\ (w__7 : bool) . bindS -(undefined_bool0 () ) (\ (w__8 : bool) . bindS -(undefined_bool0 () ) (\ (w__9 : bool) . bindS -(undefined_bool0 () ) (\ (w__10 : bool) . bindS -(undefined_bool0 () ) (\ (w__11 : bool) . bindS -(undefined_bool0 () ) (\ (w__12 : bool) . bindS -(undefined_bool0 () ) (\ (w__13 : bool) . bindS -(undefined_bool0 () ) (\ (w__14 : bool) . bindS -(undefined_bool0 () ) (\ (w__15 : bool) . bindS -(undefined_bool0 () ) (\ (w__16 : bool) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__17 : 64 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__18 : 64 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__19 : 64 cheri_sequential_types$bits) . - returnS (<| CapStruct_tag := w__0; - CapStruct_padding := w__1; - CapStruct_otype := w__2; - CapStruct_uperms := w__3; - CapStruct_perm_reserved11_14 := w__4; - CapStruct_access_system_regs := w__5; - CapStruct_permit_unseal := w__6; - CapStruct_permit_ccall := w__7; - CapStruct_permit_seal := w__8; - CapStruct_permit_store_local_cap := w__9; - CapStruct_permit_store_cap := w__10; - CapStruct_permit_load_cap := w__11; - CapStruct_permit_store := w__12; - CapStruct_permit_load := w__13; - CapStruct_permit_execute := w__14; - CapStruct_global := w__15; - CapStruct_sealed := w__16; - CapStruct_address := w__17; - CapStruct_base := w__18; - CapStruct_length := w__19 |>)))))))))))))))))))))))`; - - -val _ = Define ` -((default_cap:cheri_sequential_types$CapStruct)= - (<| CapStruct_tag := T; - CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) () : 8 words$word)); - CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); - CapStruct_uperms := ((ones (( 16 : int):sail_values$ii) () : 16 words$word)); - CapStruct_perm_reserved11_14 := ((ones (( 4 : int):sail_values$ii) () : 4 words$word)); - CapStruct_access_system_regs := T; - CapStruct_permit_unseal := T; - CapStruct_permit_ccall := T; - CapStruct_permit_seal := T; - CapStruct_permit_store_local_cap := T; - CapStruct_permit_store_cap := T; - CapStruct_permit_load_cap := T; - CapStruct_permit_store := T; - CapStruct_permit_load := T; - CapStruct_permit_execute := T; - CapStruct_global := T; - CapStruct_sealed := F; - CapStruct_address := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); - CapStruct_base := ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)); - CapStruct_length := -((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1] - : 64 words$word)) |>))`; - - -val _ = Define ` -((null_cap_bits:(256)words$word)= ((capStructToMemBits256 null_cap : 256 words$word)))`; - - -(*val capStructToMemBits : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*) - -val _ = Define ` - ((capStructToMemBits:cheri_sequential_types$CapStruct ->(256)words$word) cap= - ((xor_vec ((capStructToMemBits256 cap : 256 words$word)) null_cap_bits : 256 words$word)))`; - - -(*val memBitsToCapBits : bool -> Machine_word.mword Machine_word.ty256 -> Machine_word.mword Machine_word.ty257*) - -val _ = Define ` - ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b= - ((concat_vec ((bool_to_bits tag : 1 words$word)) ((xor_vec b null_cap_bits : 256 words$word)) - : 257 words$word)))`; - - -(*val setCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.CapStruct*) - -val _ = Define ` - ((setCapPerms:cheri_sequential_types$CapStruct ->(31)words$word -> cheri_sequential_types$CapStruct) cap perms= - ((cap with<| - CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 16 words$word)); CapStruct_perm_reserved11_14 := - ((subrange_vec_dec perms (( 14 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 4 words$word)); CapStruct_access_system_regs := - ((bit_to_bool ((access_vec_dec perms (( 10 : int):sail_values$ii))))); CapStruct_permit_unseal := - ((bit_to_bool ((access_vec_dec perms (( 9 : int):sail_values$ii))))); CapStruct_permit_ccall := - ((bit_to_bool ((access_vec_dec perms (( 8 : int):sail_values$ii))))); CapStruct_permit_seal := - ((bit_to_bool ((access_vec_dec perms (( 7 : int):sail_values$ii))))); CapStruct_permit_store_local_cap := - ((bit_to_bool ((access_vec_dec perms (( 6 : int):sail_values$ii))))); CapStruct_permit_store_cap := - ((bit_to_bool ((access_vec_dec perms (( 5 : int):sail_values$ii))))); CapStruct_permit_load_cap := - ((bit_to_bool ((access_vec_dec perms (( 4 : int):sail_values$ii))))); CapStruct_permit_store := - ((bit_to_bool ((access_vec_dec perms (( 3 : int):sail_values$ii))))); CapStruct_permit_load := - ((bit_to_bool ((access_vec_dec perms (( 2 : int):sail_values$ii))))); CapStruct_permit_execute := - ((bit_to_bool ((access_vec_dec perms (( 1 : int):sail_values$ii))))); CapStruct_global := - ((bit_to_bool ((access_vec_dec perms (( 0 : int):sail_values$ii)))))|>)))`; - - -(*val sealCap : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty24 -> (bool * Cheri_sequential_types.CapStruct)*) - -val _ = Define ` - ((sealCap:cheri_sequential_types$CapStruct ->(24)words$word -> bool#cheri_sequential_types$CapStruct) cap otype= (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`; - - -(*val getCapTop : Cheri_sequential_types.CapStruct -> Num.integer*) - -val _ = Define ` - ((getCapTop:cheri_sequential_types$CapStruct -> int) c= (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`; - - -(*val getCapOffset : Cheri_sequential_types.CapStruct -> Num.integer*) - -val _ = Define ` - ((getCapOffset:cheri_sequential_types$CapStruct -> int) c= - (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base)))) - ((pow2 (( 64 : int):sail_values$ii)))))`; - - -(*val getCapLength : Cheri_sequential_types.CapStruct -> Num.integer*) - -val _ = Define ` - ((getCapLength:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_length))`; - - -(*val getCapCursor : Cheri_sequential_types.CapStruct -> Num.integer*) - -val _ = Define ` - ((getCapCursor:cheri_sequential_types$CapStruct -> int) c= (lem$w2ui c.CapStruct_address))`; - - -(*val incCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*) - -val _ = Define ` - ((incCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c delta= - (let (newAddr : 64 cheri_sequential_types$bits) = ((add_vec c.CapStruct_address delta : 64 words$word)) in - (T, (c with<| CapStruct_address := newAddr|>))))`; - - -(*val setCapBounds : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty65 -> (bool * Cheri_sequential_types.CapStruct)*) - -val _ = Define ` - ((setCapBounds:cheri_sequential_types$CapStruct ->(64)words$word ->(65)words$word -> bool#cheri_sequential_types$CapStruct) cap base top= - (let (length : 65 cheri_sequential_types$bits) = -((sub_vec top ((concat_vec (vec_of_bits [B0] : 1 words$word) base : 65 words$word)) : 65 words$word)) in - (T, - (cap with<| - CapStruct_base := base; CapStruct_length := - ((subrange_vec_dec length (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)); CapStruct_address := base|>))))`; - - -(*val undefined_ast : unit -> Cheri_sequential_types.M Cheri_sequential_types.ast*) - -val _ = Define ` - ((undefined_ast:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ast),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__0 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__1 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__3 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__4 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__5 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__6 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__7 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__8 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__9 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__10 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__11 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__12 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__13 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__14 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__15 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__16 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__17 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__18 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__19 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__20 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__21 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__22 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__23 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__24 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__25 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__26 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__27 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__28 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__29 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__30 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__31 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__32 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__33 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__34 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__35 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__36 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__37 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__38 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__39 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__40 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__41 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__42 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__43 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__44 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__45 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__46 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__47 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__48 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__49 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__50 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__51 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__52 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__53 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__54 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__55 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__56 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__57 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__58 : 16 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__59 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__60 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__61 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__62 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__63 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__64 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__65 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__66 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__67 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__68 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__69 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__70 : 5 words$word) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii) : ( 5 words$word) cheri_sequential_types$M) (\ (w__71 : 5 words$word) . bindS - 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- -(*val execute : Cheri_sequential_types.ast -> Cheri_sequential_types.M unit*) - -(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Cheri_sequential_types.ast*) - -val _ = Define ` -((DDC:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; - - -val _ = Define ` -((IDC:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; - - -val _ = Define ` -((KR1C:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; - - -val _ = Define ` -((KR2C:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))`; - - -val _ = Define ` -((KCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))`; - - -val _ = Define ` -((KDC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))`; - - -val _ = Define ` -((EPCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; - - -val _ = Define ` -((CapRegs:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapReg))sail_values$register_ref)list)= - ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref; - C10_ref;C09_ref;C08_ref;C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`; - - -val _ = Define ` - ((max_otype:int)= (MAX0 (( 24 : int):sail_values$ii)))`; - - -val _ = Define ` - ((have_cp2:bool)= T)`; - - -(*val readCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*) - -val _ = Define ` - ((readCapReg:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n= - (let i = (lem$w2ui n) in bindS - (read_regS ((access_list_dec CapRegs i : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) - : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . - returnS ((capRegToCapStruct w__0)))))`; - - -(*val writeCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((writeCapReg:(5)words$word -> cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n cap= - (let i = (lem$w2ui n) in - write_regS - ((access_list_dec CapRegs i : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) - ((capStructToCapReg cap : 257 words$word))))`; - - -(*val CapEx_of_num : Num.integer -> Cheri_sequential_types.CapEx*) - -val _ = Define ` - ((CapEx_of_num:int -> cheri_sequential_types$CapEx) arg_= - (let l__32 = arg_ in - if (((l__32 = (( 0 : int):sail_values$ii)))) then CapEx_None - else if (((l__32 = (( 1 : int):sail_values$ii)))) then CapEx_LengthViolation - else if (((l__32 = (( 2 : int):sail_values$ii)))) then CapEx_TagViolation - else if (((l__32 = (( 3 : int):sail_values$ii)))) then CapEx_SealViolation - else if (((l__32 = (( 4 : int):sail_values$ii)))) then CapEx_TypeViolation - else if (((l__32 = (( 5 : int):sail_values$ii)))) then CapEx_CallTrap - else if (((l__32 = (( 6 : int):sail_values$ii)))) then CapEx_ReturnTrap - else if (((l__32 = (( 7 : int):sail_values$ii)))) then CapEx_TSSUnderFlow - else if (((l__32 = (( 8 : int):sail_values$ii)))) then CapEx_UserDefViolation - else if (((l__32 = (( 9 : int):sail_values$ii)))) then CapEx_TLBNoStoreCap - else if (((l__32 = (( 10 : int):sail_values$ii)))) then CapEx_InexactBounds - else if (((l__32 = (( 11 : int):sail_values$ii)))) then CapEx_GlobalViolation - else if (((l__32 = (( 12 : int):sail_values$ii)))) then CapEx_PermitExecuteViolation - else if (((l__32 = (( 13 : int):sail_values$ii)))) then CapEx_PermitLoadViolation - else if (((l__32 = (( 14 : int):sail_values$ii)))) then CapEx_PermitStoreViolation - else if (((l__32 = (( 15 : int):sail_values$ii)))) then CapEx_PermitLoadCapViolation - else if (((l__32 = (( 16 : int):sail_values$ii)))) then CapEx_PermitStoreCapViolation - else if (((l__32 = (( 17 : int):sail_values$ii)))) then CapEx_PermitStoreLocalCapViolation - else if (((l__32 = (( 18 : int):sail_values$ii)))) then CapEx_PermitSealViolation - else if (((l__32 = (( 19 : int):sail_values$ii)))) then CapEx_AccessSystemRegsViolation - else if (((l__32 = (( 20 : int):sail_values$ii)))) then CapEx_PermitCCallViolation - else if (((l__32 = (( 21 : int):sail_values$ii)))) then CapEx_AccessCCallIDCViolation - else CapEx_PermitUnsealViolation))`; - - -(*val num_of_CapEx : Cheri_sequential_types.CapEx -> Num.integer*) - -val _ = Define ` - ((num_of_CapEx:cheri_sequential_types$CapEx -> int) arg_= - ((case arg_ of - CapEx_None => (( 0 : int):sail_values$ii) - | CapEx_LengthViolation => (( 1 : int):sail_values$ii) - | CapEx_TagViolation => (( 2 : int):sail_values$ii) - | CapEx_SealViolation => (( 3 : int):sail_values$ii) - | CapEx_TypeViolation => (( 4 : int):sail_values$ii) - | CapEx_CallTrap => (( 5 : int):sail_values$ii) - | CapEx_ReturnTrap => (( 6 : int):sail_values$ii) - | CapEx_TSSUnderFlow => (( 7 : int):sail_values$ii) - | CapEx_UserDefViolation => (( 8 : int):sail_values$ii) - | CapEx_TLBNoStoreCap => (( 9 : int):sail_values$ii) - | CapEx_InexactBounds => (( 10 : int):sail_values$ii) - | CapEx_GlobalViolation => (( 11 : int):sail_values$ii) - | CapEx_PermitExecuteViolation => (( 12 : int):sail_values$ii) - | CapEx_PermitLoadViolation => (( 13 : int):sail_values$ii) - | CapEx_PermitStoreViolation => (( 14 : int):sail_values$ii) - | CapEx_PermitLoadCapViolation => (( 15 : int):sail_values$ii) - | CapEx_PermitStoreCapViolation => (( 16 : int):sail_values$ii) - | CapEx_PermitStoreLocalCapViolation => (( 17 : int):sail_values$ii) - | CapEx_PermitSealViolation => (( 18 : int):sail_values$ii) - | CapEx_AccessSystemRegsViolation => (( 19 : int):sail_values$ii) - | CapEx_PermitCCallViolation => (( 20 : int):sail_values$ii) - | CapEx_AccessCCallIDCViolation => (( 21 : int):sail_values$ii) - | CapEx_PermitUnsealViolation => (( 22 : int):sail_values$ii) - )))`; - - -(*val undefined_CapEx : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapEx*) - -val _ = Define ` - ((undefined_CapEx:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapEx),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = - (internal_pick - [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`; - - -(*val CapExCode : Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((CapExCode:cheri_sequential_types$CapEx ->(8)words$word) ex= - ((case ex of - CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) - | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) - | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) - | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) - | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) - | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) - | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : 8 words$word) - | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : 8 words$word) - | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) - | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) - | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) - | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0] : 8 words$word) - | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1] : 8 words$word) - | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) - | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1] : 8 words$word) - | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0] : 8 words$word) - | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1] : 8 words$word) - | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0] : 8 words$word) - | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1] : 8 words$word) - | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) - | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1] : 8 words$word) - | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0] : 8 words$word) - | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1] : 8 words$word) - )))`; - - -(*val undefined_CapCauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapCauseReg*) - -val _ = Define ` - ((undefined_CapCauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapCauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__0 : 16 words$word) . - internal_pick [Mk_CapCauseReg w__0])))`; - - -val _ = Define ` - ((get_CapCauseReg:cheri_sequential_types$CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))= v)`; - - -val _ = Define ` - ((set_CapCauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ r . - let r = (Mk_CapCauseReg v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word)))`; - - -val _ = Define ` - ((set_CapCauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . - let r = ((get_CapCauseReg w__0 : 16 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 16 words$word)) in - write_regS r_ref (Mk_CapCauseReg r))))`; - - -val _ = Define ` - ((update_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x= - (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 16 words$word))))`; - - -(*val _get_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_CapCauseReg_RegNum : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((set_CapCauseReg_RegNum:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . - let r = ((get_CapCauseReg w__0 : 16 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 16 words$word)) in - write_regS r_ref (Mk_CapCauseReg r))))`; - - -(*val _update_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*) - -val _ = Define ` - ((update_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x= - (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 16 words$word))))`; - - -(*val execute_branch_pcc : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_branch_pcc:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) newPCC= (seqS (seqS -(write_regS - delayedPC_ref - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapOffset newPCC)) : 64 words$word))) -(write_regS delayedPCC_ref ((capStructToCapReg newPCC : 257 words$word)))) -(write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; - - -(*val ERETHook : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((ERETHook:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS C31_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS nextPCC_ref w__0) - (read_regS C31_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__1 : cheri_sequential_types$CapReg) . write_regS delayedPCC_ref w__1))))`; - - -(*val raise_c2_exception8 : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M 'o*) - -val _ = Define ` - ((raise_c2_exception8:cheri_sequential_types$CapEx ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum= (seqS (seqS -(set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx : 8 words$word))) -(set_CapCauseReg_RegNum CapCause_ref regnum)) -(let mipsEx = -(if ((((((capEx = CapEx_CallTrap))) \/ (((capEx = CapEx_ReturnTrap)))))) then C2Trap - else C2E) in - SignalException mipsEx)))`; - - -(*val raise_c2_exception : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M 'o*) - -val _ = Define ` - ((raise_c2_exception:cheri_sequential_types$CapEx ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum= - (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) regnum : 8 words$word)) in - if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then - raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 - else raise_c2_exception8 capEx reg8))`; - - -(*val raise_c2_exception_noreg : forall 'o. Cheri_sequential_types.CapEx -> Cheri_sequential_types.M 'o*) - -val _ = Define ` - ((raise_c2_exception_noreg:cheri_sequential_types$CapEx ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx= - (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)))`; - - -(*val pcc_access_system_regs : unit -> Cheri_sequential_types.M bool*) - -val _ = Define ` - ((pcc_access_system_regs:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . - let pcc = (capRegToCapStruct w__0) in - returnS pcc.CapStruct_access_system_regs)))`; - - -(*val register_inaccessible : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M bool*) - -val _ = Define ` - ((register_inaccessible:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r= (bindS - (read_regS inCCallDelay_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__0 : 1 words$word) . - if ((((((r = IDC))) /\ ((bits_to_bool w__0))))) then returnS T - else - let b__0 = r in - let (is_sys_reg : bool) = -(if (((b__0 = (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))) then T - else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))) then T - else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then T - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) then T - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))) then T - else F) in - if is_sys_reg then bindS (pcc_access_system_regs () ) (\ (w__1 : bool) . returnS ((~ w__1))) - else returnS F)))`; - - -(*val MEMr_tagged : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*) - -val _ = Define ` - ((MEMr_tagged:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr= (bindS (seqS -(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") -(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . bindS - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) cheri_sequential_types$M) (\ data . - let ((cast_0 : bool), (cast_1 : 256 words$word)) = (tag, (reverse_endianness data : 256 words$word)) in - returnS (cast_0, (words$w2w cast_1 : 256 words$word))))))`; - - -(*val MEMr_tagged_reserve : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*) - -val _ = Define ` - ((MEMr_tagged_reserve:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr= (bindS (seqS -(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") -(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . bindS - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) cheri_sequential_types$M) (\ data . - let ((cast_0 : bool), (cast_1 : 256 words$word)) = (tag, (reverse_endianness data : 256 words$word)) in - returnS (cast_0, (words$w2w cast_1 : 256 words$word))))))`; - - -(*val MEMw_tagged : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data= (seqS (seqS (seqS -(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") -(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) -(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`; - - -(*val MEMw_tagged_conditional : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M bool*) - -val _ = Define ` - ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data= (bindS (seqS (seqS -(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "") -(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) -(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (\ success . seqS - (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else returnS () ) (returnS success))))`; - - -val _ = Define ` - ((cap_addr_mask:(64)words$word)= - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((((pow2 (( 64 : int):sail_values$ii))) - cap_size)) - : 64 words$word)))`; - - -(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data= - (let ledata = ((reverse_endianness data : 'p8_times_n_ words$word)) in - if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))) then seqS -(write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word))) -(write_regS UART_WRITTEN_ref (vec_of_bits [B1] : 1 words$word)) - else seqS (seqS (seqS -(assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec - ((add_vec addr - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - ((size1 - (( 1 : int):sail_values$ii))) - : 64 words$word)) - : 64 words$word)) cap_addr_mask - : 64 words$word))))) "") -(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) -(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F)))`; - - -(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M bool*) - -val _ = Define ` - ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data= (bindS (seqS (seqS -(assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec - ((add_vec addr - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - ((size1 - (( 1 : int):sail_values$ii))) - : 64 words$word)) - : 64 words$word)) cap_addr_mask - : 64 words$word))))) "") -(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) -(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))) (\ success . seqS - (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F - else returnS () ) -(returnS success))))`; - - -(*val addrWrapper : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.WordType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((addrWrapper:(64)words$word -> cheri_sequential_types$MemAccessType -> cheri_sequential_types$WordType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr accessType width= - (let capno = ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)) in bindS -(readCapReg capno) (\ cap . seqS (seqS - (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno - else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno - else returnS () ) - (case accessType of - Instruction => - if ((~ cap.CapStruct_permit_execute)) then - raise_c2_exception CapEx_PermitExecuteViolation capno - else returnS () - | LoadData => - if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno - else returnS () - | StoreData => - if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno - else returnS () - )) -(let cursor = (getCapCursor cap) in - let vAddr = (hardware_mod ((cursor + ((lem$w2ui addr)))) ((pow2 (( 64 : int):sail_values$ii)))) in - let size1 = (wordWidthBytes width) in - let base = (getCapBase cap) in - let top = (getCapTop cap) in - if ((((vAddr + size1)) > top)) then - (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) cheri_sequential_types$M) - else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) cheri_sequential_types$M) - else returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word))))))`; - - -(*val TranslatePC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((TranslatePC:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr= (bindS (seqS -(incrementCP0Count () ) - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M)) (\ (w__0 : 257 words$word) . - let pcc = (capRegToCapStruct w__0) in - let base = (getCapBase pcc) in - let top = (getCapTop pcc) in - let absPC = (base + ((lem$w2ui vAddr))) in - if (((((absPC % (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then - (SignalExceptionBadAddr AdEL - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) absPC : 64 words$word)) - : ( 64 words$word) cheri_sequential_types$M) - else if ((~ pcc.CapStruct_tag)) then - (raise_c2_exception_noreg CapEx_TagViolation : ( 64 words$word) cheri_sequential_types$M) - else if ((((absPC + (( 4 : int):sail_values$ii))) > top)) then - (raise_c2_exception_noreg CapEx_LengthViolation : ( 64 words$word) cheri_sequential_types$M) - else - (TLBTranslate ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) absPC : 64 words$word)) - Instruction - : ( 64 words$word) cheri_sequential_types$M))))`; - - -(*val checkCP2usable : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((checkCP2usable:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 2 : int):sail_values$ii))))))) then seqS -(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : 2 words$word)) (SignalException CpU) - else returnS () )))`; - - -val _ = Define ` - ((init_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = - (let defaultBits = ((capStructToCapReg default_cap : 257 words$word)) in seqS (seqS (seqS -(write_regS PCC_ref defaultBits) -(write_regS nextPCC_ref defaultBits)) -(write_regS delayedPCC_ref defaultBits)) - (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () - (\ i unit_var . - let idx = ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) in - writeCapReg idx default_cap))))`; - - -val _ = Define ` - ((cp2_next_pc:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS nextPCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS PCC_ref w__0) - (read_regS inBranchDelay_ref : ( 1 words$word) cheri_sequential_types$M)) (\ (w__1 : 1 words$word) . - if ((bits_to_bool w__1)) then bindS - (read_regS delayedPCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 : cheri_sequential_types$CapReg) . - write_regS nextPCC_ref w__2) - else write_regS inCCallDelay_ref (vec_of_bits [B0] : 1 words$word)))))`; - - -(*val capToString : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M string*) - -val _ = Define ` - ((capToString:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((string),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cap= (seqS -(skip () ) -(returnS ((STRCAT " t:" - ((STRCAT (if cap.CapStruct_tag then "1" else "0") - ((STRCAT " s:" - ((STRCAT (if cap.CapStruct_sealed then "1" else "0") - ((STRCAT " perms:" - ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict - ((concat_vec (vec_of_bits [B0] : 1 words$word) - ((getCapPerms cap : 31 words$word)) - : 32 words$word)))) - ((STRCAT " type:" - ((STRCAT ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype)) - ((STRCAT " offset:" - ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict - ((to_bits - ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - ((getCapOffset cap)) - : 64 words$word)))) - ((STRCAT " base:" - ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict - ((to_bits - ((make_the_value (( 64 : int):sail_values$ii) - : 64 itself)) - ((getCapBase cap)) - : 64 words$word)))) - ((STRCAT " length:" - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict - ((to_bits - ((make_the_value (( 64 : int):sail_values$ii) - : 64 itself)) - ((int_min ((getCapLength cap)) - ((MAX0 (( 64 : int):sail_values$ii))))) - : 64 words$word)))))))))))))))))))))))))))))))))`; - - -val _ = Define ` - ((dump_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : 257 words$word) . bindS -(capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . - let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in - (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () - (\ i unit_var . bindS -(readCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word))) (\ (w__2 : - cheri_sequential_types$CapStruct) . bindS -(capToString w__2) (\ (w__3 : string) . - returnS (let _ = -(prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int - instance_Show_Show_Num_integer_dict i)) w__3))))) in - () )))))))))`; - - -(*val extendLoad : forall 'sz . Size 'sz => Machine_word.mword 'sz -> bool -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign= - (if sign then (sign_extend1 (( 64 : int):sail_values$ii) memResult : 64 words$word) - else (zero_extend1 (( 64 : int):sail_values$ii) memResult : 64 words$word)))`; - - -(*val TLBWriteEntry : Machine_word.mword Machine_word.ty6 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((TLBWriteEntry:(6)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx= (bindS - (read_regS TLBPageMask_ref : ( 16 words$word) cheri_sequential_types$M) (\ pagemask . - let b__0 = pagemask in seqS - (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) - then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - returnS () - else SignalException MCheck) -(let i = (lem$w2ui idx) in - let entry = (access_list_dec TLBEntries i) in bindS (seqS -(set_TLBEntry_pagemask entry pagemask) -(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS -(set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 : 2 words$word))) -(read_regS TLBEntryHi_ref)) (\ (w__1 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS -(set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 : 27 words$word))) -(read_regS TLBEntryHi_ref)) (\ (w__2 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS -(set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 : 8 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) . bindS -(read_regS TLBEntryLo1_ref) (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS (seqS -(set_TLBEntry_g entry - ((bool_to_bits - (((((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))) /\ ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word))))))) - : 1 words$word))) -(set_TLBEntry_valid entry ((cast_unit_vec0 B1 : 1 words$word)))) -(read_regS TLBEntryLo0_ref)) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__5 : 1 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__6 : 1 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__7 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__7 : 24 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__8 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__8 : 3 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__9 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__9 : 1 words$word))) -(read_regS TLBEntryLo0_ref)) (\ (w__10 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__10 : 1 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__11 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__11 : 1 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__12 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__12 : 1 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__13 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__13 : 24 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__14 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__14 : 3 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__15 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__15 : 1 words$word))) -(read_regS TLBEntryLo1_ref)) (\ (w__16 : cheri_sequential_types$TLBEntryLoReg) . - set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__16 : 1 words$word)))))))))))))))))))))))`; - - -val _ = Define ` - ((decode:(32)words$word ->(cheri_sequential_types$ast)option) v__0= - (if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (DADDIU (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DADDU (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (DADDI (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DADD (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (ADD (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ADDI (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (ADDU (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ADDIU (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DSUBU (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DSUB (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SUB0 (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SUBU (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (AND (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ANDI (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (OR (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ORI (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (NOR (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (XOR (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (XORI (rs,rt,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (LUI (rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSLL (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSLL32 (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DSLLV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRA (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRA32 (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRAV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRL (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRL32 (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (DSRLV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (SLL (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SLLV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (SRA (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SRAV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (SRL (rt,rd,sa)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SRLV (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SLT (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SLTI (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (SLTU (rs,rt,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SLTIU (rs,rt,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (MOVN (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (MOVZ (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (MFHI rd) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (MFLO rd) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] - : 21 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - SOME (MTHI rs) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] - : 21 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - SOME (MTLO rs) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (MUL (rs,rt,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MULT (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MULTU (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DMULT (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DMULTU (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MADD (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MADDU (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MSUB (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (MSUBU (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DIV0 (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DIVU (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DDIV (rs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (DDIVU (rs,rt)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word)))) then - let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 26 words$word)) in - SOME (J offset) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word)))) then - let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 26 words$word)) in - SOME (JAL offset) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - SOME (JR rs) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (JALR (rs,rd)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BEQ (rs,rt,imm,F,F)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BEQ (rs,rt,imm,F,T)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BEQ (rs,rt,imm,T,F)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word)))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BEQ (rs,rt,imm,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LT',F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LT',T,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LT',F,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LT',T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GE,T,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GE,F,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GE,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GT',F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,GT',F,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (BCMPZ (rs,imm,LE,F,T)) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B1;B1;B1;B0;B0;B1;B1;B0;B0] - : 32 words$word)))) then - SOME (SYSCALL_THREAD_START () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then - SOME (SYSCALL () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then - SOME (BREAK () ) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] - : 32 words$word)))) then - SOME (WAIT () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,GE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,GEU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,LT')) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,LTU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,EQ')) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (TRAPREG (rs,rt,NE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,EQ')) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,NE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,GE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,GEU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,LT')) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (TRAPIMM (rs,imm,LTU)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (B,T,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (B,F,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (H,T,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (H,F,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (W0,T,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (W0,F,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (D,F,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (W0,T,T,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Load (D,F,T,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (B,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (H,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (W0,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (D,F,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (W0,T,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (Store (D,T,base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (LWL (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (LWR (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SWL (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SWR (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (LDL (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (LDR (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SDL (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (SDR (base,rt,offset)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (CACHE (base,op,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word)))) then - let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (PREF (base,op,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then - SOME (SYNC () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - SOME (MFC0 (rt,rd,sel,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - SOME (MFC0 (rt,rd,sel,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) - then - SOME (HCF () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) - then - SOME (HCF () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - SOME (MTC0 (rt,rd,sel,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - SOME (MTC0 (rt,rd,sel,T)) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] - : 32 words$word)))) then - SOME (TLBWI () ) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] - : 32 words$word)))) then - SOME (TLBWR () ) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] - : 32 words$word)))) then - SOME (TLBR () ) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] - : 32 words$word)))) then - SOME (TLBP () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : 11 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (RDHWR (rt,rd)) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] - : 32 words$word)))) then - SOME (ERET () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetPerm (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetType (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetBase (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetLen (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetTag (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetSealed (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) - then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetCause rd) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word)))) then - SOME (CReturn () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetOffset (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 21 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetCause rt) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CAndPerm (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CToPtr (rd,cb,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CNE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CLT)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CLE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CLTU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CLEU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CEXEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,ct,CNEXEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CIncOffset (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetOffset (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetBounds (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CClearTag (cd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CFromPtr (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CCheckPerm (cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word))))))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CCheckType (cs,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSeal (cd,cs,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CUnseal (cd,cs,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CJALR (cd,cb,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word))))))) then - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) - then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetCause rd) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) - then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetCause rs) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) - then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetPCC cd) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word))))))) - then - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),cb,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CCheckPerm (cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CCheckType (cs,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CClearTag (cd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CMOVX (cd,cs,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CJALR (cd,cb,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetPerm (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetType (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetBase (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetLen (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetTag (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetSealed (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetOffset (rd,cb)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetPCCSetOffset (cd,rs)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CReadHwr (cd,sel)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CWriteHwr (cb,sel)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 11 words$word))))))) then - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CGetAddr (cb,sel)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSeal (cd,cs,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CUnseal (cd,cs,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CAndPerm (cd,cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetOffset (cd,cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetBounds (cd,cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSetBoundsExact (cd,cs,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CIncOffset (cd,cb,rt)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CBuildCap (cd,cb,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CCopyType (cd,cb,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CCSeal (cd,cs,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CToPtr (rd,cb,ct)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CFromPtr (cd,cb,rs)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word))))))) then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSub (rt,cb,cs)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CMOVX (cd,cs,rs,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CMOVX (cd,cs,rs,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CNE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CLT)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CLE)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CLTU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CLEU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CEXEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CPtrCmp (rd,cb,cs,CNEXEQ)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CTestSubset (rd,cb,ct)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (CBX (cd,imm,T)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (CBX (cd,imm,F)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (CBZ (cd,imm,F)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (CBZ (cd,imm,T)) - else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] - : 32 words$word)))) then - SOME (CReturn () ) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1] : 11 words$word)))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (selector : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in - SOME (CCall (cs,cb,selector)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 16 words$word)))) then - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ClearRegs (GPLo,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1] : 16 words$word)))) then - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ClearRegs (GPHi,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0] : 16 words$word)))) then - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ClearRegs (CLo,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1] : 16 words$word)))) then - let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) in - SOME (ClearRegs (CHi,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in - SOME (CIncOffsetImmediate (cd,cb,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0] : 11 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in - SOME (CSetBoundsImmediate (cd,cb,imm)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,F,B,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,T,B,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,F,H,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,T,H,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,F,W0,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,T,W0,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CLoad (rd,cb,rt,offset,F,D,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),F,B,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),T,B,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),F,H,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),T,H,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),F,W0,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),T,W0,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),F,D,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,B,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,H,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,W0,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 8 words$word)) in - SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,D,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),B,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),H,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),W0,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then - let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] - : 8 words$word),D,T)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word)))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in - SOME (CSC (cs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word))))))) then - let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 5 words$word)) in - SOME (CSC (cs,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 11 words$word),T)) - else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word)))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) in - SOME (CLC (cd,cb,rt,offset,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 11 words$word))))))) then - let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 5 words$word)) in - SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 11 words$word),T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 16 words$word))))))) - then - let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 5 words$word)) in - SOME (C2Dump rt) - else SOME (RI () )))`; - - -(*val execute_XORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; - - -(*val execute_XOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((xor_vec w__0 w__1 : 64 words$word))))))`; - - -(*val execute_WAIT : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_WAIT:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__120= (bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS nextPC_ref w__0)))`; - - -(*val execute_TRAPREG : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TRAPREG:(5)words$word ->(5)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt cmp= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . - let condition = (compare cmp rs_val rt_val) in - if condition then SignalException Tr - else returnS () ))))`; - - -(*val execute_TRAPIMM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TRAPIMM:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . - let (imm_val : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in - let condition = (compare cmp rs_val imm_val) in - if condition then SignalException Tr - else returnS () )))`; - - -(*val execute_TLBWR : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TLBWR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__124= (bindS (seqS -(checkCP0Access () ) - (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; - - -(*val execute_TLBWI : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TLBWI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__123= (bindS (seqS -(checkCP0Access () ) - (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; - - -(*val execute_TLBR : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TLBR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__125= (bindS (seqS -(checkCP0Access () ) - (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : cheri_sequential_types$TLBIndexT) . - let i = (lem$w2ui w__0) in bindS -(read_regS ((access_list_dec TLBEntries i))) (\ entry . seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS -(write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) -(set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry : 2 words$word)))) -(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry : 27 words$word)))) -(set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry : 8 words$word)))) -(set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry : 1 words$word)))) -(set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry : 1 words$word)))) -(set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry : 24 words$word)))) -(set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry : 3 words$word)))) -(set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry : 1 words$word)))) -(set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry : 1 words$word)))) -(set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry : 1 words$word)))) -(set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry : 1 words$word)))) -(set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry : 1 words$word)))) -(set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry : 24 words$word)))) -(set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry : 3 words$word)))) -(set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry : 1 words$word)))) -(set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry : 1 words$word)))) -(set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry : 1 words$word)))))))`; - - -(*val execute_TLBP : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_TLBP:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__126= (bindS (seqS -(checkCP0Access () ) -(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . bindS - (tlbSearch ((get_TLBEntryHiReg w__0 : 64 words$word)) : ( ( 6 words$word)option) cheri_sequential_types$M) (\ result . - (case result of - SOME (idx) => seqS -(write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (write_regS TLBIndex_ref idx) - | NONE => seqS -(write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) - )))))`; - - -(*val execute_Store : Cheri_sequential_types.WordType -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_Store:cheri_sequential_types$WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width conditional base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData width - : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . - if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr - else bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . - if conditional then bindS - (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) . bindS - (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then - (case width of - B => - MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii) - ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - | H => - MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii) - ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - | W0 => - MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii) - ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rt_val - ) - else returnS F) (\ (success : bool) . - wGPR rt ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) - else - (case width of - B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rt_val - )))))))`; - - -(*val execute_SYSCALL_THREAD_START : unit -> unit*) - -val _ = Define ` - ((execute_SYSCALL_THREAD_START:unit -> unit) g__116= () )`; - - -(*val execute_SYSCALL : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SYSCALL:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__118= (SignalException Sys))`; - - -(*val execute_SYNC : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SYNC:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__121= (MEM_sync () ))`; - - -(*val execute_SWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData W0 - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . - let wordAddr = -((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) - (vec_of_bits [B0;B0] : 2 words$word) - : 64 words$word)) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__12 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in - if (((b__12 = (vec_of_bits [B0;B0] : 2 words$word)))) then - MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - else if (((b__12 = (vec_of_bits [B0;B1] : 2 words$word)))) then - MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - else if (((b__12 = (vec_of_bits [B1;B0] : 2 words$word)))) then - MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - else MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))))))))`; - - -(*val execute_SWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData W0 - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__8 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in - if (((b__8 = (vec_of_bits [B0;B0] : 2 words$word)))) then - MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - else if (((b__8 = (vec_of_bits [B0;B1] : 2 words$word)))) then - MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) - else if (((b__8 = (vec_of_bits [B1;B0] : 2 words$word)))) then - MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) - else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word))))))))`; - - -(*val execute_SUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - wGPR rd - ((sign_extend1 (( 64 : int):sail_values$ii) - ((sub_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 32 words$word)) - : 64 words$word))))))`; - - -(*val execute_SUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - let (temp33 : 33 cheri_sequential_types$bits) = -((sub_vec - ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) - : 33 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):sail_values$ii))))))) then - SignalException Ov - else - wGPR rd - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec temp33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))))))`; - - -(*val execute_SRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in - if ((NotWordVal temp)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else - let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; - - -(*val execute_SRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . - if ((NotWordVal temp)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; - - -(*val execute_SRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in - if ((NotWordVal temp)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else - let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; - - -(*val execute_SRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . - if ((NotWordVal temp)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; - - -(*val execute_SLTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . - wGPR rd - ((zero_extend1 (( 64 : int):sail_values$ii) - (if ((((lem$w2ui rs_val) < (lem$w2ui rt_val)))) then (vec_of_bits [B1] : 1 words$word) - else (vec_of_bits [B0] : 1 words$word)) - : 64 words$word))))))`; - - -(*val execute_SLTIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . - let (immext : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in - wGPR rt - ((zero_extend1 (( 64 : int):sail_values$ii) - (if ((((lem$w2ui rs_val) < (lem$w2ui immext)))) then (vec_of_bits [B1] : 1 words$word) - else (vec_of_bits [B0] : 1 words$word)) - : 64 words$word)))))`; - - -(*val execute_SLTI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= - (let imm_val = (integer_word$w2i imm) in bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs_val = (integer_word$w2i w__0) in - wGPR rt - ((zero_extend1 (( 64 : int):sail_values$ii) - (if ((rs_val < imm_val)) then (vec_of_bits [B1] : 1 words$word) - else (vec_of_bits [B0] : 1 words$word)) - : 64 words$word)))))`; - - -(*val execute_SLT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd - ((zero_extend1 (( 64 : int):sail_values$ii) - (if ((((integer_word$w2i w__0) < (integer_word$w2i w__1)))) then (vec_of_bits [B1] : 1 words$word) - else (vec_of_bits [B0] : 1 words$word)) - : 64 words$word))))))`; - - -(*val execute_SLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let rt32 = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word)))))))`; - - -(*val execute_SLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rt32 = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1 : 64 words$word))))))`; - - -(*val execute_SDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData D - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let wordAddr = -((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) - (vec_of_bits [B0;B0;B0] : 3 words$word) - : 64 words$word)) in - let b__40 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - if (((b__40 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - else if (((b__40 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - else if (((b__40 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - else if (((b__40 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - else if (((b__40 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) - else if (((b__40 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) - else if (((b__40 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then - MEMw_wrapper wordAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) - else MEMw_wrapper wordAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))))`; - - -(*val execute_SDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData D - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__32 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - if (((b__32 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then - MEMw_wrapper pAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) - else if (((b__32 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then - MEMw_wrapper pAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) - else if (((b__32 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then - MEMw_wrapper pAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) - else if (((b__32 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then - MEMw_wrapper pAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) - else if (((b__32 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then - MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) - else if (((b__32 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then - MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) - else if (((b__32 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then - MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) - else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word))))))))`; - - -(*val execute_RI : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_RI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__129= (SignalException ResI))`; - - -(*val execute_RDHWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_RDHWR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd= (bindS -(getAccessLevel () ) (\ accessLevel . - let (haveAccessLevel : bool) = (accessLevel = Kernel) in bindS -(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . - let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):sail_values$ii)))) in - let rdi = (lem$w2ui rd) in bindS - (read_regS CP0HWREna_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . - let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in seqS - (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI - else returnS () ) -(let b__146 = rd in bindS - (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then - returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) then - returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then bindS - (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 cheri_sequential_types$bits) . - returnS ((zero_extend1 (( 64 : int):sail_values$ii) w__2 : 64 words$word))) - else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) then - returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) - else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then - (read_regS CP0UserLocal_ref : ( 64 words$word) cheri_sequential_types$M) - else (SignalException ResI : ( 64 words$word) cheri_sequential_types$M)) (\ (temp : 64 cheri_sequential_types$bits) . - wGPR rt temp)))))))`; - - -(*val execute_PREF : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> unit*) - -val _ = Define ` - ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm= () )`; - - -(*val execute_ORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; - - -(*val execute_OR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((or_vec w__0 w__1 : 64 words$word))))))`; - - -(*val execute_NOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((not_vec ((or_vec w__0 w__1 : 64 words$word)) : 64 words$word))))))`; - - -(*val execute_MULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (result : 64 cheri_sequential_types$bits) . seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))`; - - -(*val execute_MULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (result : 64 cheri_sequential_types$bits) . seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))`; - - -(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . - let (result : 64 cheri_sequential_types$bits) = -((sign_extend1 (( 64 : int):sail_values$ii) - ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word)) - : 64 words$word)) in bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (w__1 : 64 words$word) . - wGPR rd w__1)))))`; - - -(*val execute_MTLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MTLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS LO_ref w__0)))`; - - -(*val execute_MTHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MTHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . write_regS HI_ref w__0)))`; - - -(*val execute_MTC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double= (bindS (seqS -(checkCP0Access () ) - (rGPR rt : ( 64 words$word) cheri_sequential_types$M)) (\ reg_val . - (case (rd, sel) of - (b__108, b__109) => - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - write_regS TLBIndex_ref - ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word)) else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - returnS () else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_TLBEntryLoReg TLBEntryLo0_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_TLBEntryLoReg TLBEntryLo1_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_ContextReg_PTEBase TLBContext_ref - ((subrange_vec_dec reg_val (( 63 : int): sail_values$ii) - (( 23 : int): sail_values$ii) : 41 words$word)) else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - write_regS CP0UserLocal_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - write_regS TLBPageMask_ref - ((subrange_vec_dec reg_val (( 28 : int): sail_values$ii) - (( 13 : int): sail_values$ii) : 16 words$word)) else - if ((((((b__108 = - (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - seqS - (write_regS TLBWired_ref - ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word))) - (write_regS TLBRandom_ref TLBIndexMax) else - if ((((((b__108 = - (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - write_regS CP0HWREna_ref - ((concat_vec - ((subrange_vec_dec reg_val - (( 31 : int): sail_values$ii) - (( 29 : int): sail_values$ii) : 3 words$word)) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] : 25 words$word) - ((subrange_vec_dec reg_val - (( 3 : int): sail_values$ii) - (( 0 : int): sail_values$ii) : 4 words$word)) - : 29 words$word)) : 32 words$word)) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - returnS () else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - write_regS CP0Count_ref - ((subrange_vec_dec reg_val - (( 31 : int): sail_values$ii) - (( 0 : int): sail_values$ii) : 32 words$word)) - else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - seqS - (seqS - (set_TLBEntryHiReg_R TLBEntryHi_ref - ((subrange_vec_dec reg_val - (( 63 : int): sail_values$ii) - (( 62 : int): sail_values$ii) : 2 words$word))) - (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref - ((subrange_vec_dec reg_val - (( 39 : int): sail_values$ii) - (( 13 : int): sail_values$ii) : 27 words$word)))) - (set_TLBEntryHiReg_ASID TLBEntryHi_ref - ((subrange_vec_dec reg_val - (( 7 : int): sail_values$ii) - (( 0 : int): sail_values$ii) : 8 words$word))) - else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (seqS - (write_regS CP0Compare_ref - ((subrange_vec_dec reg_val - (( 31 : int): sail_values$ii) - (( 0 : int): sail_values$ii) : 32 words$word))) - (read_regS CP0Cause_ref)) - (\ (w__0 : cheri_sequential_types$CauseReg) . - set_CauseReg_IP CP0Cause_ref - ((and_vec - ((get_CauseReg_IP w__0 : 8 words$word)) - (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) - : 8 words$word))) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - seqS - (seqS - (seqS - (seqS - (seqS - (seqS - (seqS - (seqS - (seqS - (set_StatusReg_CU - CP0Status_ref - ((subrange_vec_dec - reg_val - (( 31 : int): sail_values$ii) - (( 28 : int): sail_values$ii) : 4 words$word))) - (set_StatusReg_BEV - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( - 22 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_IM - CP0Status_ref - ((subrange_vec_dec - reg_val - (( 15 : int): sail_values$ii) - (( 8 : int): sail_values$ii) : 8 words$word)))) - (set_StatusReg_KX - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( 7 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_SX - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( 6 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_UX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 5 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_KSU CP0Status_ref - ((subrange_vec_dec reg_val - (( 4 : int): sail_values$ii) - (( 3 : int): sail_values$ii) : 2 words$word)))) - (set_StatusReg_ERL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 2 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_EXL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 1 : int): sail_values$ii))) : 1 words$word)))) - (set_StatusReg_IE CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 0 : int): sail_values$ii))) : 1 words$word))) - else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (seqS - (set_CauseReg_IV CP0Cause_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 23 : int): sail_values$ii))) : 1 words$word))) - (read_regS CP0Cause_ref)) - (\ (w__1 : cheri_sequential_types$CauseReg) . - let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in - set_CauseReg_IP CP0Cause_ref - ((concat_vec - ((subrange_vec_dec ip - (( 7 : int): sail_values$ii) - (( 2 : int): sail_values$ii) : 6 words$word)) - ((subrange_vec_dec reg_val - (( 9 : int): sail_values$ii) - (( 8 : int): sail_values$ii) : 2 words$word)) - : 8 words$word))) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - write_regS CP0EPC_ref reg_val else - if ((((((b__108 = - (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - returnS () else - if ((((((b__108 = - (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_XContextReg_XPTEBase - TLBXContext_ref - ((subrange_vec_dec reg_val - (( 63 : int): sail_values$ii) - (( 33 : int): sail_values$ii) : 31 words$word)) - else write_regS CP0ErrorEPC_ref reg_val - ))))`; - - -(*val execute_MSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MSUBU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS - (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS - (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . - let result = -((sub_vec - ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word)) mul_result - : 64 words$word)) in seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; - - -(*val execute_MSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MSUB:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS - (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS - (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . - let result = -((sub_vec - ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word)) mul_result - : 64 words$word)) in seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; - - -(*val execute_MOVZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))) then bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else returnS () )))`; - - -(*val execute_MOVN : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))) then bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else returnS () )))`; - - -(*val execute_MFLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MFLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS - (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; - - -(*val execute_MFHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MFHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS - (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; - - -(*val execute_MFC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double= (bindS (seqS -(checkCP0Access () ) (case (rd, sel) of - (b__48, b__49) => - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M) - (\ (w__0 : cheri_sequential_types$TLBIndexT) . - let (idx : 31 cheri_sequential_types$bits) = ((zero_extend1 - (( 31 : int): sail_values$ii) - w__0 : 31 words$word)) in - bindS - (read_regS TLBProbe_ref : ( 1 words$word) cheri_sequential_types$M) - (\ (w__1 : 1 cheri_sequential_types$bits) . - returnS - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word) - ((concat_vec w__1 idx : 32 words$word)) : 64 words$word)))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M) - (\ (w__2 : cheri_sequential_types$TLBIndexT) . - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) w__2 : 64 words$word))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS TLBEntryLo0_ref) - (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) . - returnS ((get_TLBEntryLoReg w__3 : 64 words$word))) else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS TLBEntryLo1_ref) - (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) . - returnS ((get_TLBEntryLoReg w__4 : 64 words$word))) else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS TLBContext_ref) - (\ (w__5 : cheri_sequential_types$ContextReg) . - returnS ((get_ContextReg w__5 : 64 words$word))) else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - (read_regS CP0UserLocal_ref : ( 64 words$word) cheri_sequential_types$M) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) - /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS TLBPageMask_ref : ( 16 words$word) cheri_sequential_types$M) - (\ (w__7 : 16 cheri_sequential_types$bits) . - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) - ((concat_vec w__7 - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - : 28 words$word)) : 64 words$word))) else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS TLBWired_ref : ( 6 words$word) cheri_sequential_types$M) - (\ (w__8 : cheri_sequential_types$TLBIndexT) . - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) w__8 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS CP0HWREna_ref : ( 32 words$word) cheri_sequential_types$M) - (\ (w__9 : 32 cheri_sequential_types$bits) . - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) w__9 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - (read_regS CP0BadVAddr_ref : ( 64 words$word) cheri_sequential_types$M) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M) - (\ (w__11 : 32 cheri_sequential_types$bits) . - returnS - ((zero_extend1 (( 64 : int): sail_values$ii) - w__11 : 64 words$word))) else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS TLBEntryHi_ref) - (\ (w__12 : cheri_sequential_types$TLBEntryHiReg) . - returnS - ((get_TLBEntryHiReg w__12 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS CP0Compare_ref : ( 32 words$word) cheri_sequential_types$M) - (\ (w__13 : 32 cheri_sequential_types$bits) . - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) w__13 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS CP0Status_ref) - (\ (w__14 : cheri_sequential_types$StatusReg) . - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - ((get_StatusReg w__14 : 32 words$word)) : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - bindS (read_regS CP0Cause_ref) - (\ (w__15 : cheri_sequential_types$CauseReg) . - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - ((get_CauseReg w__15 : 32 words$word)) : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - (read_regS CP0EPC_ref : ( 64 words$word) cheri_sequential_types$M) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 15 words$word) - ((concat_vec - (vec_of_bits - [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B1;B0] : 2 words$word) - ((concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B1] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - : 7 words$word)) - : 10 words$word)) - : 13 words$word)) - : 15 words$word)) - : 16 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B1] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - TLBIndexMax - ((concat_vec - (vec_of_bits - [B0;B0;B0] : 3 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0] : 3 words$word) - (( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - ( - bool_to_bits - have_cp2 : 1 words$word)) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - : 1 words$word) - ( - vec_of_bits - [B0] - : 1 words$word) - : 2 words$word)) - : 3 words$word)) - : 4 words$word)) - : 5 words$word)) - : 6 words$word)) - : 7 words$word)) - : 10 words$word)) - : 13 words$word)) - : 16 words$word)) - : 19 words$word)) - : 22 words$word)) - : 25 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B1;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0] : 3 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ((concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - : 8 words$word)) - : 12 words$word)) - : 16 words$word)) - : 20 words$word)) - : 24 words$word)) - : 28 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B1;B1] : 3 words$word))))))) then - returnS - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] : 64 words$word) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B1;B0;B1] : 3 words$word))))))) then - returnS - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] : 64 words$word) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - (read_regS CP0LLAddr_ref : ( 64 words$word) cheri_sequential_types$M) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - (vec_of_bits - [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - ( - vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - returnS - ((zero_extend1 - (( 64 : int): sail_values$ii) - (vec_of_bits - [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - ( - vec_of_bits - [B1;B0;B1;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - ( - vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - bindS - (read_regS - TLBXContext_ref) - (\ (w__18 : cheri_sequential_types$XContextReg) . - returnS - ((get_XContextReg - w__18 : 64 words$word))) - else - (read_regS - CP0ErrorEPC_ref : ( 64 words$word) cheri_sequential_types$M) - )) (\ (result : 64 cheri_sequential_types$bits) . - wGPR rt - (if double then result - else - (sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; - - -(*val execute_MADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MADDU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS - (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS - (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . - let result = -((add_vec mul_result - ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word)) - : 64 words$word)) in seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; - - -(*val execute_MADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_MADD:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) - else - returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) . bindS - (read_regS HI_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS - (read_regS LO_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . - let result = -((add_vec mul_result - ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word)) - : 64 words$word)) in seqS -(write_regS - HI_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) : 64 words$word))) -(write_regS - LO_ref - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))))))`; - - -(*val execute_Load : Cheri_sequential_types.WordType -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_Load:cheri_sequential_types$WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width sign linked base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - width - : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) . - if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr - else bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (if linked then seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (case width of - B => bindS - (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 : 8 words$word) . - returnS ((extendLoad w__1 sign : 64 words$word))) - | H => bindS - (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 : 16 words$word) . - returnS ((extendLoad w__2 sign : 64 words$word))) - | W0 => bindS - (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 : 32 words$word) . - returnS ((extendLoad w__3 sign : 64 words$word))) - | D => bindS - (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__4 : 64 words$word) . - returnS ((extendLoad w__4 sign : 64 words$word))) - ) - else - (case width of - B => bindS - (MEMr_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__6 : 8 words$word) . - returnS ((extendLoad w__6 sign : 64 words$word))) - | H => bindS - (MEMr_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__7 : 16 words$word) . - returnS ((extendLoad w__7 sign : 64 words$word))) - | W0 => bindS - (MEMr_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__8 : 32 words$word) . - returnS ((extendLoad w__8 sign : 64 words$word))) - | D => bindS - (MEMr_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__9 : 64 words$word) . - returnS ((extendLoad w__9 sign : 64 words$word))) - )) (\ (memResult : 64 cheri_sequential_types$bits) . - wGPR rt memResult))))))`; - - -(*val execute_LWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - W0 - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (MEMr_wrapper - ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) - (vec_of_bits [B0;B0] : 2 words$word) - : 64 words$word)) (( 4 : int):sail_values$ii) - : ( 32 words$word) cheri_sequential_types$M) (\ mem_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__4 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in - let (result : 32 cheri_sequential_types$bits) = -(if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) - ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word)) - : 32 words$word) - else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) - ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 16 words$word)) - : 32 words$word) - else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 8 words$word)) - ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 24 words$word)) - : 32 words$word) - else mem_val) in - wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result : 64 words$word)))))))))`; - - -(*val execute_LWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - W0 - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (MEMr_wrapper - ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)) - (vec_of_bits [B0;B0] : 2 words$word) - : 64 words$word)) (( 4 : int):sail_values$ii) - : ( 32 words$word) cheri_sequential_types$M) (\ mem_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__0 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) in - let (result : 32 cheri_sequential_types$bits) = -(if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then mem_val - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - : 32 words$word) - else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - : 32 words$word) - else - (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - : 32 words$word)) in - wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result : 64 words$word)))))))))`; - - -(*val execute_LUI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_LUI:(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt imm= - (wGPR rt - ((sign_extend1 (( 64 : int):sail_values$ii) - ((concat_vec imm - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word) - : 32 words$word)) - : 64 words$word))))`; - - -(*val execute_LDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - D - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (MEMr_wrapper - ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) - (vec_of_bits [B0;B0;B0] : 3 words$word) - : 64 words$word)) (( 8 : int):sail_values$ii) - : ( 64 words$word) cheri_sequential_types$M) (\ mem_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__24 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - wGPR rt - (if (((b__24 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 32 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii) : 24 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 40 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii) : 16 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 48 words$word)) - : 64 words$word) - else if (((b__24 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii) : 8 words$word)) - ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 56 words$word)) - : 64 words$word) - else mem_val))))))))`; - - -(*val execute_LDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset= (bindS - (rGPR base : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - D - : ( 64 words$word) cheri_sequential_types$M) (\ vAddr . bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (MEMr_wrapper - ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 61 words$word)) - (vec_of_bits [B0;B0;B0] : 3 words$word) - : 64 words$word)) (( 8 : int):sail_values$ii) - : ( 64 words$word) cheri_sequential_types$M) (\ mem_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . - let b__16 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 3 words$word)) in - wGPR rt - (if (((b__16 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then mem_val - else if (((b__16 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) - ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - : 64 words$word) - else if (((b__16 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) - ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - : 64 words$word) - else if (((b__16 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) - ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - : 64 words$word) - else if (((b__16 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 64 words$word) - else if (((b__16 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 24 words$word)) - ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 40 words$word)) - : 64 words$word) - else if (((b__16 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then - (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 48 words$word)) - : 64 words$word) - else - (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 56 words$word)) - : 64 words$word)))))))))`; - - -(*val execute_JR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_JR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs= (bindS (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; - - -(*val execute_JALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_JALR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS (seqS -(execute_branch w__0) - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 words$word) . - wGPR rd ((add_vec_int w__1 (( 8 : int):sail_values$ii) : 64 words$word))))))`; - - -(*val execute_JAL : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_JAL:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset= (bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . bindS (seqS -(execute_branch - ((concat_vec - ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii) : 64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 36 words$word)) - ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) - : 64 words$word))) - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 words$word) . - wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) ((add_vec_int w__1 (( 8 : int):sail_values$ii) : 64 words$word))))))`; - - -(*val execute_J : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_J:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset= (bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . - execute_branch - ((concat_vec - ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii) : 64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 36 words$word)) - ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) - : 64 words$word)))))`; - - -(*val execute_ImplementationDefinedStopFetching : unit -> unit*) - -val _ = Define ` - ((execute_ImplementationDefinedStopFetching:unit -> unit) g__117= () )`; - - -(*val execute_HCF : unit -> unit*) - -val _ = Define ` - ((execute_HCF:unit -> unit) g__122= () )`; - - -(*val execute_ERET : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ERET:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__127= (bindS (seqS (seqS (seqS -(checkCP0Access () ) -(ERETHook () )) -(write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word))) -(read_regS CP0Status_ref)) (\ (w__0 : cheri_sequential_types$StatusReg) . - if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then bindS - (read_regS CP0ErrorEPC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) . seqS -(write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) - else bindS - (read_regS CP0EPC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . seqS -(write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word))))))`; - - -(*val execute_DSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((sub_vec w__0 w__1 : 64 words$word))))))`; - - -(*val execute_DSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let (temp65 : 65 cheri_sequential_types$bits) = -((sub_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1 : 65 words$word)) - : 65 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):sail_values$ii))))))) then - SignalException Ov - else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))`; - - -(*val execute_DSRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) in bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; - - -(*val execute_DSRL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . - let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; - - -(*val execute_DSRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; - - -(*val execute_DSRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) in bindS - (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; - - -(*val execute_DSRA32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . - let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in bindS - (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; - - -(*val execute_DSRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ temp . bindS - (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; - - -(*val execute_DSLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : - 64 words$word) . - wGPR rd w__2)))))`; - - -(*val execute_DSLL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) - : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd w__1))))`; - - -(*val execute_DSLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa= (bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; - - -(*val execute_DMULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DMULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let result = ((mult_vec w__0 w__1 : 128 words$word)) in seqS -(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word))) -(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))))`; - - -(*val execute_DMULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DMULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let result = ((mults_vec w__0 w__1 : 128 words$word)) in seqS -(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word))) -(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))))`; - - -(*val execute_DIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))))))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . - returnS (w__0, w__1))) - else - let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in - let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in - let qi = (hardware_quot si ti) in - let ri = (hardware_mod si ti) in - returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) qi : 32 words$word), - (to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in seqS -(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r : 64 words$word))) -(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q : 64 words$word))))))))`; - - -(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rsVal . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . bindS - (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))))))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . - returnS (w__0, w__1))) - else - let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in - let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word))) in - let qi = (hardware_quot si ti) in - let ri = (si - ((ti * qi))) in - returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) qi : 32 words$word), - (to_bits ((make_the_value (( 32 : int):sail_values$ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in seqS -(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r : 64 words$word))) -(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q : 64 words$word))))))))`; - - -(*val execute_DDIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DDIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rsVal = (lem$w2ui w__0) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let rtVal = (lem$w2ui w__1) in bindS - (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . - returnS (w__2, w__3))) - else - let qi = (hardware_quot rsVal rtVal) in - let ri = (hardware_mod rsVal rtVal) in - returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) qi : 64 words$word), - (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in seqS -(write_regS LO_ref q) (write_regS HI_ref r))))))`; - - -(*val execute_DDIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DDIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rsVal = (integer_word$w2i w__0) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let rtVal = (integer_word$w2i w__1) in bindS - (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . - returnS (w__2, w__3))) - else - let qi = (hardware_quot rsVal rtVal) in - let ri = (rsVal - ((qi * rtVal))) in - returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) qi : 64 words$word), - (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in seqS -(write_regS LO_ref q) (write_regS HI_ref r))))))`; - - -(*val execute_DADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((add_vec w__0 w__1 : 64 words$word))))))`; - - -(*val execute_DADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; - - -(*val execute_DADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let (sum65 : 65 cheri_sequential_types$bits) = -((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) imm : 65 words$word)) - : 65 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then - SignalException Ov - else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))))`; - - -(*val execute_DADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let (sum65 : 65 cheri_sequential_types$bits) = -((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1 : 65 words$word)) - : 65 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then - SignalException Ov - else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word))))))`; - - -(*val execute_ClearRegs : Cheri_sequential_types.ClearRegSet -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ClearRegs:cheri_sequential_types$ClearRegSet ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) regset m= (seqS (seqS - (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () - else returnS () ) - (if (((regset = CHi))) then - (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () - (\ i unit_var . - let r = -((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) : 5 words$word)) in bindS -(register_inaccessible r) (\ (w__0 : bool) . - if (((((bit_to_bool ((access_vec_dec m i)))) /\ w__0))) then - raise_c2_exception CapEx_AccessSystemRegsViolation r - else returnS () ))) - else returnS () )) - (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () - (\ i unit_var . - if ((bit_to_bool ((access_vec_dec m i)))) then - (case regset of - GPLo => - wGPR ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) - ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)) - | GPHi => - wGPR - ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) - : 5 words$word)) ((zeros (( 64 : int):sail_values$ii) () : 64 words$word)) - | CLo => - writeCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) i : 5 words$word)) null_cap - | CHi => - writeCapReg - ((to_bits ((make_the_value (( 5 : int):sail_values$ii) : 5 itself)) ((i + (( 16 : int):sail_values$ii))) - : 5 words$word)) null_cap - ) - else returnS () ))))`; - - -(*val execute_CWriteHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb sel= (seqS -(checkCP2usable () ) -(let l__24 = (lem$w2ui sel) in bindS - (if (((l__24 = (( 0 : int):sail_values$ii)))) then returnS (F, F) - else if (((l__24 = (( 1 : int):sail_values$ii)))) then returnS (F, F) - else if (((l__24 = (( 8 : int):sail_values$ii)))) then returnS (F, T) - else if (((l__24 = (( 22 : int):sail_values$ii)))) then returnS (T, F) - else if (((l__24 = (( 23 : int):sail_values$ii)))) then returnS (T, F) - else if (((l__24 = (( 29 : int):sail_values$ii)))) then returnS (T, T) - else if (((l__24 = (( 30 : int):sail_values$ii)))) then returnS (T, T) - else if (((l__24 = (( 31 : int):sail_values$ii)))) then returnS (T, T) - else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS -(register_inaccessible cb) (\ (w__8 : bool) . - if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(pcc_access_system_regs () ) (\ (w__9 : bool) . - if (((needAccessSys /\ ((~ w__9))))) then - raise_c2_exception CapEx_AccessSystemRegsViolation sel - else bindS -(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . - if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then - raise_c2_exception CapEx_AccessSystemRegsViolation sel - else bindS -(readCapReg cb) (\ capVal . - let l__16 = (lem$w2ui sel) in - if (((l__16 = (( 0 : int):sail_values$ii)))) then writeCapReg DDC capVal - else if (((l__16 = (( 1 : int):sail_values$ii)))) then - write_regS CTLSU_ref ((capStructToCapReg capVal : 257 words$word)) - else if (((l__16 = (( 8 : int):sail_values$ii)))) then - write_regS CTLSP_ref ((capStructToCapReg capVal : 257 words$word)) - else if (((l__16 = (( 22 : int):sail_values$ii)))) then writeCapReg KR1C capVal - else if (((l__16 = (( 23 : int):sail_values$ii)))) then writeCapReg KR2C capVal - else if (((l__16 = (( 29 : int):sail_values$ii)))) then writeCapReg KCC capVal - else if (((l__16 = (( 30 : int):sail_values$ii)))) then writeCapReg KDC capVal - else if (((l__16 = (( 31 : int):sail_values$ii)))) then writeCapReg EPCC capVal - else assert_expS F "should be unreachable code"))))))))`; - - -(*val execute_CUnseal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg ct) (\ ct_val . - let ct_cursor = (getCapCursor ct_val) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cs) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible ct) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct - else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs - else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct - else if (((ct_cursor <> ((lem$w2ui cs_val.CapStruct_otype))))) then - raise_c2_exception CapEx_TypeViolation ct - else if ((~ ct_val.CapStruct_permit_unseal)) then - raise_c2_exception CapEx_PermitUnsealViolation ct - else if ((ct_cursor < ((getCapBase ct_val)))) then - raise_c2_exception CapEx_LengthViolation ct - else if ((ct_cursor >= ((getCapTop ct_val)))) then - raise_c2_exception CapEx_LengthViolation ct - else - writeCapReg cd - (cs_val with<| - CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word)); CapStruct_global := - (((cs_val.CapStruct_global /\ ct_val.CapStruct_global)))|>))))))))`; - - -(*val execute_CToPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg ct)) (\ ct_val . bindS -(readCapReg cb) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct - else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then - raise_c2_exception CapEx_SealViolation cb - else - let cbBase = (getCapBase cb_val) in - let cbTop = (getCapTop cb_val) in - let ctBase = (getCapBase ct_val) in - let ctTop = (getCapTop ct_val) in - wGPR rd - (if (((((~ cb_val.CapStruct_tag)) \/ (((((cbBase < ctBase)) \/ ((cbTop > ctTop)))))))) then - (zeros (( 64 : int):sail_values$ii) () : 64 words$word) - else - (to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - ((((getCapCursor cb_val)) - ctBase)) - : 64 words$word))))))))`; - - -(*val execute_CTestSubset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(readCapReg ct) (\ ct_val . - let ct_top = (getCapTop ct_val) in - let ct_base = (getCapBase ct_val) in - let ct_perms = ((getCapPerms ct_val : 31 words$word)) in - let cb_top = (getCapTop cb_val) in - let cb_base = (getCapBase cb_val) in - let cb_perms = ((getCapPerms cb_val : 31 words$word)) in bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else - let (result : 1 cheri_sequential_types$bits) = -(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then - (vec_of_bits [B0] : 1 words$word) - else if ((ct_base < cb_base)) then (vec_of_bits [B0] : 1 words$word) - else if ((ct_top > cb_top)) then (vec_of_bits [B0] : 1 words$word) - else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then - (vec_of_bits [B0] : 1 words$word) - else (vec_of_bits [B1] : 1 words$word)) in - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) result : 64 words$word))))))))`; - - -(*val execute_CSub : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg ct)) (\ ct_val . bindS -(readCapReg cb) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else - wGPR rd - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) - : 64 words$word))))))))`; - - -(*val execute_CStore : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_store)) then - raise_c2_exception CapEx_PermitStoreViolation cb - else - let size1 = (wordWidthBytes width) in - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + size1)) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 - else bindS - (TLBTranslate vAddr64 StoreData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . - if conditional then bindS - (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__2 : 1 cheri_sequential_types$bits) . bindS - (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):sail_values$ii))))) then - (case width of - B => - MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii) - ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - | H => - MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii) - ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - | W0 => - MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii) - ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rs_val - ) - else returnS F) (\ (success : bool) . - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) - else - (case width of - B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) - | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rs_val - ))))))))`; - - -(*val execute_CSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then - raise_c2_exception CapEx_SealViolation cb - else - let (success, newCap) = (setCapOffset cb_val rt_val) in - if success then writeCapReg cd newCap - else - writeCapReg cd - ((int_to_cap - ((add_vec - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) - : 64 words$word)) rt_val - : 64 words$word))))))))))`; - - -(*val execute_CSetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt= (bindS (seqS -(checkCP2usable () ) -(pcc_access_system_regs () )) (\ (w__0 : bool) . - if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation - else bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . seqS -(set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 8 words$word))) -(set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))))))`; - - -(*val execute_CSetBoundsImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . - let immU = (lem$w2ui imm) in - let cursor = (getCapCursor cb_val) in - let base = (getCapBase cb_val) in - let top = (getCapTop cb_val) in - let newTop = (cursor + immU) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb - else (case - setCapBounds cb_val - ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself)) - cursor : 64 words$word)) - ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself)) - newTop : 65 words$word)) of - (_, newCap) => - writeCapReg cd newCap - ))))))`; - - -(*val execute_CSetBoundsExact : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rt_val = (lem$w2ui w__0) in - let cursor = (getCapCursor cb_val) in - let base = (getCapBase cb_val) in - let top = (getCapTop cb_val) in - let newTop = (cursor + rt_val) in bindS -(register_inaccessible cd) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb - else - let (exact, newCap) = -(setCapBounds cb_val - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor : 64 words$word)) - ((to_bits ((make_the_value (( 65 : int):sail_values$ii) : 65 itself)) newTop : 65 words$word))) in - if ((~ exact)) then raise_c2_exception CapEx_InexactBounds cb - else writeCapReg cd newCap))))))`; - - -(*val execute_CSetBounds : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - let rt_val = (lem$w2ui w__0) in - let cursor = (getCapCursor cb_val) in - let base = (getCapBase cb_val) in - let top = (getCapTop cb_val) in - let newTop = (cursor + rt_val) in bindS -(register_inaccessible cd) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb - else (case - setCapBounds cb_val - ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself)) - cursor : 64 words$word)) - ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself)) - newTop : 65 words$word)) of - (_, newCap) => - writeCapReg cd newCap - )))))))`; - - -(*val execute_CSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg ct) (\ ct_val . - let ct_cursor = (getCapCursor ct_val) in - let ct_top = (getCapTop ct_val) in - let ct_base = (getCapBase ct_val) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cs) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible ct) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct - else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs - else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct - else if ((~ ct_val.CapStruct_permit_seal)) then - raise_c2_exception CapEx_PermitSealViolation ct - else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct - else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct - else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct - else - let (success, newCap) = -(sealCap cs_val - ((to_bits ((make_the_value (( 24 : int):sail_values$ii) : 24 itself)) ct_cursor : 24 words$word))) in - if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs - else writeCapReg cd newCap)))))))`; - - -(*val execute_CSC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg cb) (\ cb_val . bindS -(register_inaccessible cs) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_store)) then - raise_c2_exception CapEx_PermitStoreViolation cb - else if ((~ cb_val.CapStruct_permit_store_cap)) then - raise_c2_exception CapEx_PermitStoreCapViolation cb - else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then - raise_c2_exception CapEx_PermitStoreLocalCapViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then - SignalExceptionBadAddr AdES vAddr64 - else bindS - (TLBTranslateC vAddr64 StoreData : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (pAddr, noStoreCap) = varstup in - if (((cs_val.CapStruct_tag /\ noStoreCap))) then - raise_c2_exception CapEx_TLBNoStoreCap cs - else if conditional then bindS - (read_regS CP0LLBit_ref : ( 1 words$word) cheri_sequential_types$M) (\ (w__3 : 1 cheri_sequential_types$bits) . bindS - (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):sail_values$ii))))) then - MEMw_tagged_conditional pAddr cs_val.CapStruct_tag - ((capStructToMemBits cs_val : 256 words$word)) - else returnS F) (\ success . - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) - else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val : 256 words$word))))))))))`; - - -(*val execute_CReturn : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CReturn:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__128= (seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`; - - -(*val execute_CReadHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CReadHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd sel= (seqS -(checkCP2usable () ) -(let l__8 = (lem$w2ui sel) in bindS - (if (((l__8 = (( 0 : int):sail_values$ii)))) then returnS (F, F) - else if (((l__8 = (( 1 : int):sail_values$ii)))) then returnS (F, F) - else if (((l__8 = (( 8 : int):sail_values$ii)))) then returnS (F, T) - else if (((l__8 = (( 22 : int):sail_values$ii)))) then returnS (T, F) - else if (((l__8 = (( 23 : int):sail_values$ii)))) then returnS (T, F) - else if (((l__8 = (( 29 : int):sail_values$ii)))) then returnS (T, T) - else if (((l__8 = (( 30 : int):sail_values$ii)))) then returnS (T, T) - else if (((l__8 = (( 31 : int):sail_values$ii)))) then returnS (T, T) - else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS -(register_inaccessible cd) (\ (w__8 : bool) . - if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(pcc_access_system_regs () ) (\ (w__9 : bool) . - if (((needAccessSys /\ ((~ w__9))))) then - raise_c2_exception CapEx_AccessSystemRegsViolation sel - else bindS -(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . - if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then - raise_c2_exception CapEx_AccessSystemRegsViolation sel - else - let l__0 = (lem$w2ui sel) in bindS - (if (((l__0 = (( 0 : int):sail_values$ii)))) then readCapReg DDC - else if (((l__0 = (( 1 : int):sail_values$ii)))) then bindS - (read_regS CTLSU_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__12 : 257 words$word) . - returnS ((capRegToCapStruct w__12))) - else if (((l__0 = (( 8 : int):sail_values$ii)))) then bindS - (read_regS CTLSP_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__13 : 257 words$word) . - returnS ((capRegToCapStruct w__13))) - else if (((l__0 = (( 22 : int):sail_values$ii)))) then readCapReg KR1C - else if (((l__0 = (( 23 : int):sail_values$ii)))) then readCapReg KR2C - else if (((l__0 = (( 29 : int):sail_values$ii)))) then readCapReg KCC - else if (((l__0 = (( 30 : int):sail_values$ii)))) then readCapReg KDC - else if (((l__0 = (( 31 : int):sail_values$ii)))) then readCapReg EPCC - else seqS (assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal : - cheri_sequential_types$CapStruct) . - writeCapReg cd capVal))))))))`; - - -(*val execute_CPtrCmp : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CPtrCmpOp -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> cheri_sequential_types$CPtrCmpOp ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct op= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else bindS -(readCapReg cb) (\ cb_val . bindS -(readCapReg ct) (\ ct_val . - let equal = F in - let ltu = F in - let lts = F in - let ((equal : bool), (lts : bool), (ltu : bool)) = -(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then - let ((lts : bool), (ltu : bool)) = -(if ((~ cb_val.CapStruct_tag)) then - let (ltu : bool) = T in - let (lts : bool) = T in - (lts, ltu) - else (lts, ltu)) in - (equal, lts, ltu) - else - let cursor1 = (getCapCursor cb_val) in - let cursor2 = (getCapCursor ct_val) in - let (equal : bool) = (cursor1 = cursor2) in - let (ltu : bool) = (cursor1 < cursor2) in - let (lts : bool) = -((integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor1 : 64 words$word))) < (integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) cursor2 : 64 words$word)))) in - (equal, lts, ltu)) in - let (cmp : bool) = -((case op of - CEQ => equal - | CNE => ~ equal - | CLT => lts - | CLE => (lts \/ equal) - | CLTU => ltu - | CLEU => (ltu \/ equal) - | CEXEQ => (cb_val = ct_val) - | CNEXEQ => (cb_val <> ct_val) - )) in - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits cmp : 1 words$word)) : 64 words$word))))))))`; - - -(*val execute_CMOVX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt ismovn= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cd)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - if ((bits_to_bool - ((xor_vec - ((bool_to_bits (((w__2 = ((zeros (( 64 : int):sail_values$ii) () : 64 words$word))))) : 1 words$word)) - ((bool_to_bits ismovn : 1 words$word)) - : 1 words$word)))) then bindS -(readCapReg cb) (\ (w__3 : cheri_sequential_types$CapStruct) . writeCapReg cd w__3) - else returnS () )))))`; - - -(*val execute_CLoad : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> bool -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6= - (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in - (case merge_var of - (rd, cb, rt, offset, signext, B, linked) => bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_load)) then - raise_c2_exception CapEx_PermitLoadViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + (( 1 : int):sail_values$ii))) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 - else bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (if linked then bindS (seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__2 : 8 words$word) . - returnS ((extendLoad w__2 signext : 64 words$word))) - else bindS - (MEMr_wrapper pAddr (( 1 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M) (\ (w__3 : 8 words$word) . - returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . - wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, D, linked) => bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_load)) then - raise_c2_exception CapEx_PermitLoadViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + (( 8 : int):sail_values$ii))) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 - else bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (if linked then bindS (seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__2 : 64 words$word) . - returnS ((extendLoad w__2 signext : 64 words$word))) - else bindS - (MEMr_wrapper pAddr (( 8 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . - returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . - wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, H, linked) => bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_load)) then - raise_c2_exception CapEx_PermitLoadViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + (( 2 : int):sail_values$ii))) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 - else bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (if linked then bindS (seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M)) (\ (w__2 : 16 words$word) . - returnS ((extendLoad w__2 signext : 64 words$word))) - else bindS - (MEMr_wrapper pAddr (( 2 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 : 16 words$word) . - returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . - wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, W0, linked) => bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cb) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_load)) then - raise_c2_exception CapEx_PermitLoadViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + (( 4 : int):sail_values$ii))) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64 - else bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . bindS - (if linked then bindS (seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__2 : 32 words$word) . - returnS ((extendLoad w__2 signext : 64 words$word))) - else bindS - (MEMr_wrapper pAddr (( 4 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 : 32 words$word) . - returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . - wGPR rd memResult))))) - )))`; - - -(*val execute_CLC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt offset linked= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_load)) then - raise_c2_exception CapEx_PermitLoadViolation cb - else - let cursor = (getCapCursor cb_val) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - let vAddr = -(hardware_mod - ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset)))))) - ((pow2 (( 64 : int):sail_values$ii)))) in - let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) vAddr : 64 words$word)) in - if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then - raise_c2_exception CapEx_LengthViolation cb - else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then - SignalExceptionBadAddr AdEL vAddr64 - else bindS - (TLBTranslateC vAddr64 LoadData : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup . let (pAddr, suppressTag) = varstup in - let cd = (lem$w2ui cd) in - if linked then bindS (seqS (seqS -(write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) -(write_regS CP0LLAddr_ref pAddr)) - (MEMr_tagged_reserve pAddr : ((bool # 256 words$word)) cheri_sequential_types$M)) (\ varstup . let (tag, mem) = varstup in - write_regS - ((access_list_dec CapRegs cd : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) - ((memBitsToCapBits - (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) - mem - : 257 words$word))) - else bindS - (MEMr_tagged pAddr : ((bool # 256 words$word)) cheri_sequential_types$M) (\ varstup . let (tag, mem) = varstup in - write_regS - ((access_list_dec CapRegs cd : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref)) - ((memBitsToCapBits - (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) - mem - : 257 words$word))))))))))`; - - -(*val execute_CJALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb link= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . - let cb_ptr = (getCapCursor cb_val) in - let cb_top = (getCapTop cb_val) in - let cb_base = (getCapBase cb_val) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if (((link /\ w__0))) then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((~ cb_val.CapStruct_permit_execute)) then - raise_c2_exception CapEx_PermitExecuteViolation cb - else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((((cb_ptr + (( 4 : int):sail_values$ii))) > cb_top)) then - raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod cb_ptr (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then SignalException AdEL - else seqS - (if link then bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 : 257 words$word) . - let pcc = (capRegToCapStruct w__2) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . - let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__3 (( 8 : int):sail_values$ii) : 64 words$word))) in - if success then writeCapReg cd linkCap - else assert_expS F "")) - else returnS () ) -(execute_branch_pcc cb_val))))))`; - - -(*val execute_CIncOffsetImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . - let (imm64 : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then - raise_c2_exception CapEx_SealViolation cb - else - let (success, newCap) = (incCapOffset cb_val imm64) in - if success then writeCapReg cd newCap - else - writeCapReg cd - ((int_to_cap - ((add_vec - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) - : 64 words$word)) imm64 - : 64 words$word)))))))))`; - - -(*val execute_CIncOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))))))))) then - raise_c2_exception CapEx_SealViolation cb - else - let (success, newCap) = (incCapOffset cb_val rt_val) in - if success then writeCapReg cd newCap - else - writeCapReg cd - ((int_to_cap - ((add_vec - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) - : 64 words$word)) rt_val - : 64 words$word))))))))))`; - - -(*val execute_CGetType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):sail_values$ii) capVal.CapStruct_otype : 64 words$word) - else (replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word))))))`; - - -(*val execute_CGetTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_tag : 1 words$word)) : 64 words$word))))))`; - - -(*val execute_CGetSealed : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetSealed:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_sealed : 1 words$word)) : 64 words$word))))))`; - - -(*val execute_CGetPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms capVal : 31 words$word)) : 64 words$word))))))`; - - -(*val execute_CGetPCCSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd rs= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cd)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . - let pcc = (capRegToCapStruct w__1) in bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . - let (success, newPCC) = (setCapOffset pcc rs_val) in - if success then writeCapReg cd newPCC - else writeCapReg cd ((int_to_cap rs_val)))))))`; - - -(*val execute_CGetPCC : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetPCC:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cd)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS - (read_regS PCC_ref : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 : 257 words$word) . - let pcc = (capRegToCapStruct w__1) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - let (success, pcc2) = (setCapOffset pcc w__2) in seqS -(assert_expS success "") (writeCapReg cd pcc2))))))`; - - -(*val execute_CGetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapOffset capVal)) : 64 words$word))))))`; - - -(*val execute_CGetLen : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetLen:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - let len65 = (getCapLength capVal) in - wGPR rd - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) - (if ((len65 > MAX_U64)) then MAX_U64 - else len65) - : 64 words$word))))))`; - - -(*val execute_CGetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd= (bindS (seqS -(checkCP2usable () ) -(pcc_access_system_regs () )) (\ (w__0 : bool) . - if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation - else bindS -(read_regS CapCause_ref) (\ (w__1 : cheri_sequential_types$CapCauseReg) . - wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((get_CapCauseReg w__1 : 16 words$word)) : 64 words$word))))))`; - - -(*val execute_CGetBase : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetBase:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase capVal)) : 64 words$word))))))`; - - -(*val execute_CGetAddr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CGetAddr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ capVal . - wGPR rd - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapCursor capVal)) : 64 words$word))))))`; - - -(*val execute_CFromPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then writeCapReg cd null_cap - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else - let (success, newCap) = (setCapOffset cb_val rt_val) in - if success then writeCapReg cd newCap - else - writeCapReg cd - ((int_to_cap - ((add_vec - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((getCapBase cb_val)) - : 64 words$word)) rt_val - : 64 words$word))))))))))`; - - -(*val execute_CCopyType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(readCapReg ct) (\ ct_val . - let cb_base = (getCapBase cb_val) in - let cb_top = (getCapTop cb_val) in - let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ct_val.CapStruct_sealed then - if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((ct_otype >= cb_top)) then raise_c2_exception CapEx_LengthViolation cb - else - let (success, cap) = -(setCapOffset cb_val - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ((ct_otype - cb_base)) - : 64 words$word))) in seqS -(assert_expS success "") (writeCapReg cd cap) - else - writeCapReg cd - ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word)))))))))))`; - - -(*val execute_CClearTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CClearTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cd)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS (readCapReg cb) (\ cb_val . writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`; - - -(*val execute_CCheckType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CCheckType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg cb) (\ cb_val . bindS -(register_inaccessible cs) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs - else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb - else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then - raise_c2_exception CapEx_TypeViolation cs - else returnS () ))))))`; - - -(*val execute_CCheckPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . - let (cs_perms : 64 cheri_sequential_types$bits) = -((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms cs_val : 31 words$word)) : 64 words$word)) in bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_perms . bindS -(register_inaccessible cs) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if (((((and_vec cs_perms rt_perms : 64 words$word)) <> rt_perms))) then - raise_c2_exception CapEx_UserDefViolation cs - else returnS () )))))`; - - -(*val execute_CCall : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb b__151= - (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) then bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg cb) (\ cb_val . - let cs_cursor = (getCapCursor cs_val) in bindS -(register_inaccessible cs) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs - else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb - else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then - raise_c2_exception CapEx_TypeViolation cs - else if ((~ cs_val.CapStruct_permit_execute)) then - raise_c2_exception CapEx_PermitExecuteViolation cs - else if cb_val.CapStruct_permit_execute then - raise_c2_exception CapEx_PermitExecuteViolation cb - else if ((cs_cursor < ((getCapBase cs_val)))) then - raise_c2_exception CapEx_LengthViolation cs - else if ((cs_cursor >= ((getCapTop cs_val)))) then - raise_c2_exception CapEx_LengthViolation cs - else raise_c2_exception CapEx_CallTrap cs)))) - else bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg cb) (\ cb_val . - let cs_cursor = (getCapCursor cs_val) in bindS -(register_inaccessible cs) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible cb) (\ (w__3 : bool) . - if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs - else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb - else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then - raise_c2_exception CapEx_TypeViolation cs - else if ((~ cs_val.CapStruct_permit_ccall)) then - raise_c2_exception CapEx_PermitCCallViolation cs - else if ((~ cb_val.CapStruct_permit_ccall)) then - raise_c2_exception CapEx_PermitCCallViolation cb - else if ((~ cs_val.CapStruct_permit_execute)) then - raise_c2_exception CapEx_PermitExecuteViolation cs - else if cb_val.CapStruct_permit_execute then - raise_c2_exception CapEx_PermitExecuteViolation cb - else if ((cs_cursor < ((getCapBase cs_val)))) then - raise_c2_exception CapEx_LengthViolation cs - else if ((cs_cursor >= ((getCapTop cs_val)))) then - raise_c2_exception CapEx_LengthViolation cs - else seqS (seqS -(execute_branch_pcc - (cs_val with<| - CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word))|>)) -(write_regS inCCallDelay_ref (vec_of_bits [B1] : 1 words$word))) -(write_regS - C26_ref - ((capStructToCapReg - (cb_val with<| - CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) () : 24 words$word))|>) - : 257 words$word)))))))))`; - - -(*val execute_CCSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cs)) (\ cs_val . bindS -(readCapReg ct) (\ ct_val . - let ct_cursor = (getCapCursor ct_val) in - let ct_top = (getCapTop ct_val) in - let ct_base = (getCapBase ct_val) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cs) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else bindS -(register_inaccessible ct) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs - else if (((((~ ct_val.CapStruct_tag)) \/ (((((getCapCursor ct_val)) = ((lem$w2ui ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):sail_values$ii) : 64 words$word)))))))))) - then - writeCapReg cd cs_val - else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs - else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct - else if ((~ ct_val.CapStruct_permit_seal)) then - raise_c2_exception CapEx_PermitSealViolation ct - else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct - else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct - else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct - else - let (success, newCap) = -(sealCap cs_val - ((to_bits ((make_the_value (( 24 : int):sail_values$ii) : 24 itself)) ct_cursor : 24 words$word))) in - if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs - else writeCapReg cd newCap)))))))`; - - -(*val execute_CBuildCap : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS -(readCapReg ct) (\ ct_val . - let cb_base = (getCapBase cb_val) in - let ct_base = (getCapBase ct_val) in - let cb_top = (getCapTop cb_val) in - let ct_top = (getCapTop ct_val) in - let cb_perms = ((getCapPerms cb_val : 31 words$word)) in - let ct_perms = ((getCapPerms ct_val : 31 words$word)) in - let ct_offset = (getCapOffset ct_val) in bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(register_inaccessible ct) (\ (w__2 : bool) . - if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb - else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb - else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct - else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then - raise_c2_exception CapEx_UserDefViolation cb - else - let (exact, cd1) = -(setCapBounds cb_val - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ct_base : 64 words$word)) - ((to_bits ((make_the_value (( 65 : int):sail_values$ii) : 65 itself)) ct_top : 65 words$word))) in - let (representable, cd2) = -(setCapOffset cd1 - ((to_bits ((make_the_value (( 64 : int):sail_values$ii) : 64 itself)) ct_offset : 64 words$word))) in - let cd3 = (setCapPerms cd2 ct_perms) in seqS (seqS -(assert_expS exact "") (assert_expS representable "")) (writeCapReg cd cd3))))))))`; - - -(*val execute_CBZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notzero= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . - if ((bits_to_bool - ((xor_vec ((bool_to_bits (((w__1 = null_cap))) : 1 words$word)) - ((bool_to_bits notzero : 1 words$word)) - : 1 words$word)))) then - let (offset : 64 cheri_sequential_types$bits) = -((add_vec_int - ((sign_extend1 (( 64 : int):sail_values$ii) - ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) - : 64 words$word)) (( 4 : int):sail_values$ii) - : 64 words$word)) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - execute_branch ((add_vec w__2 offset : 64 words$word))) - else returnS () ))))`; - - -(*val execute_CBX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notset= (bindS (seqS -(checkCP2usable () ) -(register_inaccessible cb)) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else bindS -(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . - if ((bits_to_bool - ((xor_vec ((bool_to_bits w__1.CapStruct_tag : 1 words$word)) - ((bool_to_bits notset : 1 words$word)) - : 1 words$word)))) then - let (offset : 64 cheri_sequential_types$bits) = -((add_vec_int - ((sign_extend1 (( 64 : int):sail_values$ii) - ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) - : 64 words$word)) (( 4 : int):sail_values$ii) - : 64 words$word)) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - execute_branch ((add_vec w__2 offset : 64 words$word))) - else returnS () ))))`; - - -(*val execute_CAndPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt= (bindS (seqS -(checkCP2usable () ) -(readCapReg cb)) (\ cb_val . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . bindS -(register_inaccessible cd) (\ (w__0 : bool) . - if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else bindS -(register_inaccessible cb) (\ (w__1 : bool) . - if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb - else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb - else - let perms = ((getCapPerms cb_val : 31 words$word)) in - let newCap = -(setCapPerms cb_val - ((and_vec perms ((subrange_vec_dec rt_val (( 30 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 31 words$word)) : 31 words$word))) in - writeCapReg cd newCap))))))`; - - -(*val execute_CACHE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; - - -(*val execute_C2Dump : Machine_word.mword Machine_word.ty5 -> unit*) - -val _ = Define ` - ((execute_C2Dump:(5)words$word -> unit) rt= () )`; - - -(*val execute_BREAK : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_BREAK:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__119= (SignalException Bp))`; - - -(*val execute_BEQ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd imm ne likely= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rd : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - if ((bits_to_bool - ((xor_vec ((bool_to_bits (((w__0 = w__1))) : 1 words$word)) - ((bool_to_bits ne : 1 words$word)) - : 1 words$word)))) then - let (offset : 64 cheri_sequential_types$bits) = -((add_vec_int - ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) - : 64 words$word)) (( 4 : int):sail_values$ii) - : 64 words$word)) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - execute_branch ((add_vec w__2 offset : 64 words$word))) - else if likely then bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 words$word) . - write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):sail_values$ii) : 64 words$word))) - else returnS () ))))`; - - -(*val execute_BCMPZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> bool -> bool -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_BCMPZ:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp link likely= (bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . - let linkVal = ((add_vec_int w__0 (( 8 : int):sail_values$ii) : 64 words$word)) in bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ regVal . - let condition = -(compare cmp regVal ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in seqS - (if condition then - let (offset : 64 cheri_sequential_types$bits) = -((add_vec_int - ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) - : 64 words$word)) (( 4 : int):sail_values$ii) - : 64 words$word)) in bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - execute_branch ((add_vec w__1 offset : 64 words$word))) - else if likely then bindS - (read_regS PC_ref : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 words$word) . - write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):sail_values$ii) : 64 words$word))) - else returnS () ) -(if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) linkVal - else returnS () )))))`; - - -(*val execute_ANDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . - wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)))))`; - - -(*val execute_AND : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 words$word) . - wGPR rd ((and_vec w__0 w__1 : 64 words$word))))))`; - - -(*val execute_ADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - wGPR rd - ((sign_extend1 (( 64 : int):sail_values$ii) - ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - : 32 words$word)) - : 64 words$word))))))`; - - -(*val execute_ADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . - if ((NotWordVal opA)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rt w__0) - else - wGPR rt - ((sign_extend1 (( 64 : int):sail_values$ii) - ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - ((sign_extend1 (( 32 : int):sail_values$ii) imm : 32 words$word)) - : 32 words$word)) - : 64 words$word)))))`; - - -(*val execute_ADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ opA . - if ((NotWordVal opA)) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rt w__0) - else - let (sum33 : 33 cheri_sequential_types$bits) = -((add_vec - ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):sail_values$ii) imm : 33 words$word)) - : 33 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then - SignalException Ov - else - wGPR rt - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; - - -(*val execute_ADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd= (bindS - (rGPR rs : ( 64 words$word) cheri_sequential_types$M) (\ (opA : 64 cheri_sequential_types$bits) . bindS - (rGPR rt : ( 64 words$word) cheri_sequential_types$M) (\ (opB : 64 cheri_sequential_types$bits) . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 words$word) . wGPR rd w__0) - else - let (sum33 : 33 cheri_sequential_types$bits) = -((add_vec - ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 33 words$word)) - : 33 words$word)) in - if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii))))) - ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then - SignalException Ov - else - wGPR rd - ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word))))))`; - - -val _ = Define ` - ((execute:cheri_sequential_types$ast ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) merge_var= - ((case merge_var of - DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm - | DADDU (rs,rt,rd) => execute_DADDU rs rt rd - | DADDI (rs,rt,imm) => execute_DADDI rs rt imm - | DADD (rs,rt,rd) => execute_DADD rs rt rd - | ADD (rs,rt,rd) => execute_ADD rs rt rd - | ADDI (rs,rt,imm) => execute_ADDI rs rt imm - | ADDU (rs,rt,rd) => execute_ADDU rs rt rd - | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm - | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd - | DSUB (rs,rt,rd) => execute_DSUB rs rt rd - | SUB0 (rs,rt,rd) => execute_SUB rs rt rd - | SUBU (rs,rt,rd) => execute_SUBU rs rt rd - | AND (rs,rt,rd) => execute_AND rs rt rd - | ANDI (rs,rt,imm) => execute_ANDI rs rt imm - | OR (rs,rt,rd) => execute_OR rs rt rd - | ORI (rs,rt,imm) => execute_ORI rs rt imm - | NOR (rs,rt,rd) => execute_NOR rs rt rd - | XOR (rs,rt,rd) => execute_XOR rs rt rd - | XORI (rs,rt,imm) => execute_XORI rs rt imm - | LUI (rt,imm) => execute_LUI rt imm - | DSLL (rt,rd,sa) => execute_DSLL rt rd sa - | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa - | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd - | DSRA (rt,rd,sa) => execute_DSRA rt rd sa - | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa - | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd - | DSRL (rt,rd,sa) => execute_DSRL rt rd sa - | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa - | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd - | SLL (rt,rd,sa) => execute_SLL rt rd sa - | SLLV (rs,rt,rd) => execute_SLLV rs rt rd - | SRA (rt,rd,sa) => execute_SRA rt rd sa - | SRAV (rs,rt,rd) => execute_SRAV rs rt rd - | SRL (rt,rd,sa) => execute_SRL rt rd sa - | SRLV (rs,rt,rd) => execute_SRLV rs rt rd - | SLT (rs,rt,rd) => execute_SLT rs rt rd - | SLTI (rs,rt,imm) => execute_SLTI rs rt imm - | SLTU (rs,rt,rd) => execute_SLTU rs rt rd - | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm - | MOVN (rs,rt,rd) => execute_MOVN rs rt rd - | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd - | MFHI (rd) => execute_MFHI rd - | MFLO (rd) => execute_MFLO rd - | MTHI (rs) => execute_MTHI rs - | MTLO (rs) => execute_MTLO rs - | MUL (rs,rt,rd) => execute_MUL rs rt rd - | MULT (rs,rt) => execute_MULT rs rt - | MULTU (rs,rt) => execute_MULTU rs rt - | DMULT (rs,rt) => execute_DMULT rs rt - | DMULTU (rs,rt) => execute_DMULTU rs rt - | MADD (rs,rt) => execute_MADD rs rt - | MADDU (rs,rt) => execute_MADDU rs rt - | MSUB (rs,rt) => execute_MSUB rs rt - | MSUBU (rs,rt) => execute_MSUBU rs rt - | DIV0 (rs,rt) => execute_DIV rs rt - | DIVU (rs,rt) => execute_DIVU rs rt - | DDIV (rs,rt) => execute_DDIV rs rt - | DDIVU (rs,rt) => execute_DDIVU rs rt - | J (offset) => execute_J offset - | JAL (offset) => execute_JAL offset - | JR (rs) => execute_JR rs - | JALR (rs,rd) => execute_JALR rs rd - | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely - | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely - | SYSCALL_THREAD_START (g__116) => returnS ((execute_SYSCALL_THREAD_START g__116)) - | ImplementationDefinedStopFetching (g__117) => - returnS ((execute_ImplementationDefinedStopFetching g__117)) - | SYSCALL (g__118) => execute_SYSCALL g__118 - | BREAK (g__119) => execute_BREAK g__119 - | WAIT (g__120) => execute_WAIT g__120 - | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp - | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp - | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset - | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset - | LWL (base,rt,offset) => execute_LWL base rt offset - | LWR (base,rt,offset) => execute_LWR base rt offset - | SWL (base,rt,offset) => execute_SWL base rt offset - | SWR (base,rt,offset) => execute_SWR base rt offset - | LDL (base,rt,offset) => execute_LDL base rt offset - | LDR (base,rt,offset) => execute_LDR base rt offset - | SDL (base,rt,offset) => execute_SDL base rt offset - | SDR (base,rt,offset) => execute_SDR base rt offset - | CACHE (base,op,imm) => execute_CACHE base op imm - | PREF (base,op,imm) => returnS ((execute_PREF base op imm)) - | SYNC (g__121) => execute_SYNC g__121 - | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double - | HCF (g__122) => returnS ((execute_HCF g__122)) - | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double - | TLBWI (g__123) => execute_TLBWI g__123 - | TLBWR (g__124) => execute_TLBWR g__124 - | TLBR (g__125) => execute_TLBR g__125 - | TLBP (g__126) => execute_TLBP g__126 - | RDHWR (rt,rd) => execute_RDHWR rt rd - | ERET (g__127) => execute_ERET g__127 - | CGetPerm (rd,cb) => execute_CGetPerm rd cb - | CGetType (rd,cb) => execute_CGetType rd cb - | CGetBase (rd,cb) => execute_CGetBase rd cb - | CGetOffset (rd,cb) => execute_CGetOffset rd cb - | CGetLen (rd,cb) => execute_CGetLen rd cb - | CGetTag (rd,cb) => execute_CGetTag rd cb - | CGetSealed (rd,cb) => execute_CGetSealed rd cb - | CGetAddr (rd,cb) => execute_CGetAddr rd cb - | CGetPCC (cd) => execute_CGetPCC cd - | CGetPCCSetOffset (cd,rs) => execute_CGetPCCSetOffset cd rs - | CGetCause (rd) => execute_CGetCause rd - | CSetCause (rt) => execute_CSetCause rt - | CReadHwr (cd,sel) => execute_CReadHwr cd sel - | CWriteHwr (cb,sel) => execute_CWriteHwr cb sel - | CAndPerm (cd,cb,rt) => execute_CAndPerm cd cb rt - | CToPtr (rd,cb,ct) => execute_CToPtr rd cb ct - | CSub (rd,cb,ct) => execute_CSub rd cb ct - | CPtrCmp (rd,cb,ct,op) => execute_CPtrCmp rd cb ct op - | CIncOffset (cd,cb,rt) => execute_CIncOffset cd cb rt - | CIncOffsetImmediate (cd,cb,imm) => execute_CIncOffsetImmediate cd cb imm - | CSetOffset (cd,cb,rt) => execute_CSetOffset cd cb rt - | CSetBounds (cd,cb,rt) => execute_CSetBounds cd cb rt - | CSetBoundsImmediate (cd,cb,imm) => execute_CSetBoundsImmediate cd cb imm - | CSetBoundsExact (cd,cb,rt) => execute_CSetBoundsExact cd cb rt - | CClearTag (cd,cb) => execute_CClearTag cd cb - | CMOVX (cd,cb,rt,ismovn) => execute_CMOVX cd cb rt ismovn - | ClearRegs (regset,m) => execute_ClearRegs regset m - | CFromPtr (cd,cb,rt) => execute_CFromPtr cd cb rt - | CBuildCap (cd,cb,ct) => execute_CBuildCap cd cb ct - | CCopyType (cd,cb,ct) => execute_CCopyType cd cb ct - | CCheckPerm (cs,rt) => execute_CCheckPerm cs rt - | CCheckType (cs,cb) => execute_CCheckType cs cb - | CTestSubset (rd,cb,ct) => execute_CTestSubset rd cb ct - | CSeal (cd,cs,ct) => execute_CSeal cd cs ct - | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct - | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct - | CCall (cs,cb,b__151) => execute_CCall cs cb b__151 - | CReturn (g__128) => execute_CReturn g__128 - | CBX (cb,imm,notset) => execute_CBX cb imm notset - | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero - | CJALR (cd,cb,link) => execute_CJALR cd cb link - | CLoad (rd,cb,rt,offset,signext,arg5,linked) => - execute_CLoad rd cb rt offset signext arg5 linked - | CStore (rs,cb,rt,rd,offset,width,conditional) => - execute_CStore rs cb rt rd offset width conditional - | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional - | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked - | C2Dump (rt) => returnS ((execute_C2Dump rt)) - | RI (g__129) => execute_RI g__129 - )))`; - - -(*val supported_instructions : Cheri_sequential_types.ast -> Maybe.maybe Cheri_sequential_types.ast*) - -val _ = Define ` - ((supported_instructions:cheri_sequential_types$ast ->(cheri_sequential_types$ast)option) instr= (SOME instr))`; - - -(*val initialize_registers : unit -> Cheri_sequential_types.M unit*) - -val _ = Define ` - ((initialize_registers:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS PC_ref w__0) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS nextPC_ref w__1) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__2 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS TLBProbe_ref w__2) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$TLBIndexT) . bindS (seqS -(write_regS TLBIndex_ref w__3) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__4 : cheri_sequential_types$TLBIndexT) . bindS (seqS -(write_regS TLBRandom_ref w__4) -(undefined_TLBEntryLoReg () )) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(write_regS TLBEntryLo0_ref w__5) -(undefined_TLBEntryLoReg () )) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) . bindS (seqS -(write_regS TLBEntryLo1_ref w__6) -(undefined_ContextReg () )) (\ (w__7 : cheri_sequential_types$ContextReg) . bindS (seqS -(write_regS TLBContext_ref w__7) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii) : ( 16 words$word) cheri_sequential_types$M)) (\ (w__8 : 16 cheri_sequential_types$bits) . bindS (seqS -(write_regS TLBPageMask_ref w__8) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii) : ( 6 words$word) cheri_sequential_types$M)) (\ (w__9 : cheri_sequential_types$TLBIndexT) . bindS (seqS -(write_regS TLBWired_ref w__9) -(undefined_TLBEntryHiReg () )) (\ (w__10 : cheri_sequential_types$TLBEntryHiReg) . bindS (seqS -(write_regS TLBEntryHi_ref w__10) -(undefined_XContextReg () )) (\ (w__11 : cheri_sequential_types$XContextReg) . bindS (seqS -(write_regS TLBXContext_ref w__11) -(undefined_TLBEntry () )) (\ (w__12 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry00_ref w__12) -(undefined_TLBEntry () )) (\ (w__13 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry01_ref w__13) -(undefined_TLBEntry () )) (\ (w__14 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry02_ref w__14) -(undefined_TLBEntry () )) (\ (w__15 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry03_ref w__15) -(undefined_TLBEntry () )) (\ (w__16 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry04_ref w__16) -(undefined_TLBEntry () )) (\ (w__17 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry05_ref w__17) -(undefined_TLBEntry () )) (\ (w__18 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry06_ref w__18) -(undefined_TLBEntry () )) (\ (w__19 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry07_ref w__19) -(undefined_TLBEntry () )) (\ (w__20 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry08_ref w__20) -(undefined_TLBEntry () )) (\ (w__21 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry09_ref w__21) -(undefined_TLBEntry () )) (\ (w__22 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry10_ref w__22) -(undefined_TLBEntry () )) (\ (w__23 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry11_ref w__23) -(undefined_TLBEntry () )) (\ (w__24 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry12_ref w__24) -(undefined_TLBEntry () )) (\ (w__25 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry13_ref w__25) -(undefined_TLBEntry () )) (\ (w__26 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry14_ref w__26) -(undefined_TLBEntry () )) (\ (w__27 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry15_ref w__27) -(undefined_TLBEntry () )) (\ (w__28 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry16_ref w__28) -(undefined_TLBEntry () )) (\ (w__29 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry17_ref w__29) -(undefined_TLBEntry () )) (\ (w__30 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry18_ref w__30) -(undefined_TLBEntry () )) (\ (w__31 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry19_ref w__31) -(undefined_TLBEntry () )) (\ (w__32 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry20_ref w__32) -(undefined_TLBEntry () )) (\ (w__33 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry21_ref w__33) -(undefined_TLBEntry () )) (\ (w__34 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry22_ref w__34) -(undefined_TLBEntry () )) (\ (w__35 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry23_ref w__35) -(undefined_TLBEntry () )) (\ (w__36 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry24_ref w__36) -(undefined_TLBEntry () )) (\ (w__37 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry25_ref w__37) -(undefined_TLBEntry () )) (\ (w__38 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry26_ref w__38) -(undefined_TLBEntry () )) (\ (w__39 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry27_ref w__39) -(undefined_TLBEntry () )) (\ (w__40 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry28_ref w__40) -(undefined_TLBEntry () )) (\ (w__41 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry29_ref w__41) -(undefined_TLBEntry () )) (\ (w__42 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry30_ref w__42) -(undefined_TLBEntry () )) (\ (w__43 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry31_ref w__43) -(undefined_TLBEntry () )) (\ (w__44 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry32_ref w__44) -(undefined_TLBEntry () )) (\ (w__45 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry33_ref w__45) -(undefined_TLBEntry () )) (\ (w__46 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry34_ref w__46) -(undefined_TLBEntry () )) (\ (w__47 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry35_ref w__47) -(undefined_TLBEntry () )) (\ (w__48 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry36_ref w__48) -(undefined_TLBEntry () )) (\ (w__49 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry37_ref w__49) -(undefined_TLBEntry () )) (\ (w__50 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry38_ref w__50) -(undefined_TLBEntry () )) (\ (w__51 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry39_ref w__51) -(undefined_TLBEntry () )) (\ (w__52 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry40_ref w__52) -(undefined_TLBEntry () )) (\ (w__53 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry41_ref w__53) -(undefined_TLBEntry () )) (\ (w__54 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry42_ref w__54) -(undefined_TLBEntry () )) (\ (w__55 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry43_ref w__55) -(undefined_TLBEntry () )) (\ (w__56 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry44_ref w__56) -(undefined_TLBEntry () )) (\ (w__57 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry45_ref w__57) -(undefined_TLBEntry () )) (\ (w__58 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry46_ref w__58) -(undefined_TLBEntry () )) (\ (w__59 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry47_ref w__59) -(undefined_TLBEntry () )) (\ (w__60 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry48_ref w__60) -(undefined_TLBEntry () )) (\ (w__61 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry49_ref w__61) -(undefined_TLBEntry () )) (\ (w__62 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry50_ref w__62) -(undefined_TLBEntry () )) (\ (w__63 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry51_ref w__63) -(undefined_TLBEntry () )) (\ (w__64 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry52_ref w__64) -(undefined_TLBEntry () )) (\ (w__65 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry53_ref w__65) -(undefined_TLBEntry () )) (\ (w__66 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry54_ref w__66) -(undefined_TLBEntry () )) (\ (w__67 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry55_ref w__67) -(undefined_TLBEntry () )) (\ (w__68 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry56_ref w__68) -(undefined_TLBEntry () )) (\ (w__69 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry57_ref w__69) -(undefined_TLBEntry () )) (\ (w__70 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry58_ref w__70) -(undefined_TLBEntry () )) (\ (w__71 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry59_ref w__71) -(undefined_TLBEntry () )) (\ (w__72 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry60_ref w__72) -(undefined_TLBEntry () )) (\ (w__73 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry61_ref w__73) -(undefined_TLBEntry () )) (\ (w__74 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry62_ref w__74) -(undefined_TLBEntry () )) (\ (w__75 : cheri_sequential_types$TLBEntry) . bindS (seqS -(write_regS TLBEntry63_ref w__75) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__76 : 32 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0Compare_ref w__76) -(undefined_CauseReg () )) (\ (w__77 : cheri_sequential_types$CauseReg) . bindS (seqS -(write_regS CP0Cause_ref w__77) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__78 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0EPC_ref w__78) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__79 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0ErrorEPC_ref w__79) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__80 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0LLBit_ref w__80) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__81 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0LLAddr_ref w__81) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__82 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0BadVAddr_ref w__82) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__83 : 32 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0Count_ref w__83) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii) : ( 32 words$word) cheri_sequential_types$M)) (\ (w__84 : 32 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0HWREna_ref w__84) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__85 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS CP0UserLocal_ref w__85) -(undefined_StatusReg () )) (\ (w__86 : cheri_sequential_types$StatusReg) . bindS (seqS -(write_regS CP0Status_ref w__86) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__87 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS branchPending_ref w__87) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__88 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS inBranchDelay_ref w__88) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__89 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS delayedPC_ref w__89) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__90 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS HI_ref w__90) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__91 : 64 cheri_sequential_types$bits) . bindS (seqS -(write_regS LO_ref w__91) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) : ( 64 words$word) cheri_sequential_types$M)) (\ (w__92 : 64 words$word) . bindS - (undefined_vector (( 32 : int):sail_values$ii) w__92 : ( ( 64 words$word)list) cheri_sequential_types$M) (\ (w__93 : ( 64 cheri_sequential_types$bits) list) . bindS (seqS -(write_regS GPR_ref w__93) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__94 : 8 cheri_sequential_types$bits) . bindS (seqS -(write_regS UART_WDATA_ref w__94) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__95 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS UART_WRITTEN_ref w__95) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii) : ( 8 words$word) cheri_sequential_types$M)) (\ (w__96 : 8 cheri_sequential_types$bits) . bindS (seqS -(write_regS UART_RDATA_ref w__96) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__97 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS UART_RVALID_ref w__97) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__98 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS PCC_ref w__98) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__99 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS nextPCC_ref w__99) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__100 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS delayedPCC_ref w__100) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii) : ( 1 words$word) cheri_sequential_types$M)) (\ (w__101 : 1 cheri_sequential_types$bits) . bindS (seqS -(write_regS inCCallDelay_ref w__101) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__102 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C00_ref w__102) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__103 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C01_ref w__103) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__104 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C02_ref w__104) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__105 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C03_ref w__105) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__106 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C04_ref w__106) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__107 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C05_ref w__107) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__108 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C06_ref w__108) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__109 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C07_ref w__109) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__110 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C08_ref w__110) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__111 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C09_ref w__111) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__112 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C10_ref w__112) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__113 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C11_ref w__113) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__114 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C12_ref w__114) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__115 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C13_ref w__115) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__116 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C14_ref w__116) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__117 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C15_ref w__117) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__118 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C16_ref w__118) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__119 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C17_ref w__119) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__120 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C18_ref w__120) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__121 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C19_ref w__121) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__122 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C20_ref w__122) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__123 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C21_ref w__123) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__124 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C22_ref w__124) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__125 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C23_ref w__125) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__126 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C24_ref w__126) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__127 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C25_ref w__127) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__128 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C26_ref w__128) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__129 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C27_ref w__129) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__130 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C28_ref w__130) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__131 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C29_ref w__131) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__132 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C30_ref w__132) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__133 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS C31_ref w__133) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__134 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS CTLSU_ref w__134) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii) : ( 257 words$word) cheri_sequential_types$M)) (\ (w__135 : cheri_sequential_types$CapReg) . bindS (seqS -(write_regS CTLSP_ref w__135) -(undefined_CapCauseReg () )) (\ (w__136 : cheri_sequential_types$CapCauseReg) . write_regS CapCause_ref w__136)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; - - - -val _ = export_theory() - diff --git a/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml b/snapshots/hol4/sail/cheri/cheri_typesScript.sml index 459c100e..2bc764e0 100644 --- a/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml +++ b/snapshots/hol4/sail/cheri/cheri_typesScript.sml @@ -1,20 +1,20 @@ -(*Generated by Lem from cheri_sequential_types.lem.*) +(*Generated by Lem from cheri_types.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; val _ = numLib.prefer_num(); -val _ = new_theory "cheri_sequential_types" +val _ = new_theory "cheri_types" -(*Generated by Sail from cheri_sequential.*) +(*Generated by Sail from cheri.*) (*open import Pervasives_extra*) (*open import Sail_instr_kinds*) (*open import Sail_values*) (*open import Sail_operators_mwords*) -(*open import State_monad*) -(*open import State*) +(*open import Prompt_monad*) +(*open import Prompt*) val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); @@ -364,7 +364,7 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` register_value = - Regval_vector of ((sail_values$ii # bool # register_value list)) + Regval_vector of ((ii # bool # register_value list)) | Regval_list of ( register_value list) | Regval_option of ( register_value option) | Regval_CapCauseReg of (CapCauseReg) @@ -375,6 +375,7 @@ val _ = Hol_datatype ` | Regval_TLBEntryHiReg of (TLBEntryHiReg) | Regval_TLBEntryLoReg of (TLBEntryLoReg) | Regval_XContextReg of (XContextReg) + | Regval_int of (ii) | Regval_vector_16_dec_bit of ( 16 words$word) | Regval_vector_1_dec_bit of ( 1 words$word) | Regval_vector_257_dec_bit of ( 257 words$word) @@ -388,7 +389,8 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` regstate = - <| CapCause : CapCauseReg; + <| instCount : ii; + CapCause : CapCauseReg; CTLSP : 257 words$word; CTLSU : 257 words$word; C31 : 257 words$word; @@ -529,11 +531,11 @@ val _ = Hol_datatype ` -(*val CapCauseReg_of_regval : register_value -> Maybe.maybe CapCauseReg*) +(*val CapCauseReg_of_regval : register_value -> maybe CapCauseReg*) val _ = Define ` - ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var= - ((case merge_var of Regval_CapCauseReg (v) => SOME v | g__113 => NONE )))`; + ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var= + ((case merge_var of Regval_CapCauseReg (v) => SOME v | g__114 => NONE )))`; (*val regval_of_CapCauseReg : CapCauseReg -> register_value*) @@ -542,11 +544,11 @@ val _ = Define ` ((regval_of_CapCauseReg:CapCauseReg -> register_value) v= (Regval_CapCauseReg v))`; -(*val CauseReg_of_regval : register_value -> Maybe.maybe CauseReg*) +(*val CauseReg_of_regval : register_value -> maybe CauseReg*) val _ = Define ` - ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var= - ((case merge_var of Regval_CauseReg (v) => SOME v | g__112 => NONE )))`; + ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var= + ((case merge_var of Regval_CauseReg (v) => SOME v | g__113 => NONE )))`; (*val regval_of_CauseReg : CauseReg -> register_value*) @@ -555,11 +557,11 @@ val _ = Define ` ((regval_of_CauseReg:CauseReg -> register_value) v= (Regval_CauseReg v))`; -(*val ContextReg_of_regval : register_value -> Maybe.maybe ContextReg*) +(*val ContextReg_of_regval : register_value -> maybe ContextReg*) val _ = Define ` - ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var= - ((case merge_var of Regval_ContextReg (v) => SOME v | g__111 => NONE )))`; + ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var= + ((case merge_var of Regval_ContextReg (v) => SOME v | g__112 => NONE )))`; (*val regval_of_ContextReg : ContextReg -> register_value*) @@ -568,11 +570,11 @@ val _ = Define ` ((regval_of_ContextReg:ContextReg -> register_value) v= (Regval_ContextReg v))`; -(*val StatusReg_of_regval : register_value -> Maybe.maybe StatusReg*) +(*val StatusReg_of_regval : register_value -> maybe StatusReg*) val _ = Define ` - ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var= - ((case merge_var of Regval_StatusReg (v) => SOME v | g__110 => NONE )))`; + ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var= + ((case merge_var of Regval_StatusReg (v) => SOME v | g__111 => NONE )))`; (*val regval_of_StatusReg : StatusReg -> register_value*) @@ -581,11 +583,11 @@ val _ = Define ` ((regval_of_StatusReg:StatusReg -> register_value) v= (Regval_StatusReg v))`; -(*val TLBEntry_of_regval : register_value -> Maybe.maybe TLBEntry*) +(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*) val _ = Define ` - ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var= - ((case merge_var of Regval_TLBEntry (v) => SOME v | g__109 => NONE )))`; + ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var= + ((case merge_var of Regval_TLBEntry (v) => SOME v | g__110 => NONE )))`; (*val regval_of_TLBEntry : TLBEntry -> register_value*) @@ -594,11 +596,11 @@ val _ = Define ` ((regval_of_TLBEntry:TLBEntry -> register_value) v= (Regval_TLBEntry v))`; -(*val TLBEntryHiReg_of_regval : register_value -> Maybe.maybe TLBEntryHiReg*) +(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*) val _ = Define ` - ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var= - ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__108 => NONE )))`; + ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var= + ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__109 => NONE )))`; (*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) @@ -607,11 +609,11 @@ val _ = Define ` ((regval_of_TLBEntryHiReg:TLBEntryHiReg -> register_value) v= (Regval_TLBEntryHiReg v))`; -(*val TLBEntryLoReg_of_regval : register_value -> Maybe.maybe TLBEntryLoReg*) +(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*) val _ = Define ` - ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var= - ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__107 => NONE )))`; + ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var= + ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__108 => NONE )))`; (*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) @@ -620,11 +622,11 @@ val _ = Define ` ((regval_of_TLBEntryLoReg:TLBEntryLoReg -> register_value) v= (Regval_TLBEntryLoReg v))`; -(*val XContextReg_of_regval : register_value -> Maybe.maybe XContextReg*) +(*val XContextReg_of_regval : register_value -> maybe XContextReg*) val _ = Define ` - ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var= - ((case merge_var of Regval_XContextReg (v) => SOME v | g__106 => NONE )))`; + ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var= + ((case merge_var of Regval_XContextReg (v) => SOME v | g__107 => NONE )))`; (*val regval_of_XContextReg : XContextReg -> register_value*) @@ -633,92 +635,105 @@ val _ = Define ` ((regval_of_XContextReg:XContextReg -> register_value) v= (Regval_XContextReg v))`; -(*val vector_16_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty16)*) +(*val int_of_regval : register_value -> maybe ii*) val _ = Define ` - ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var= - ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`; + ((int_of_regval:register_value ->(int)option) merge_var= + ((case merge_var of Regval_int (v) => SOME v | g__106 => NONE )))`; -(*val regval_of_vector_16_dec_bit : Machine_word.mword Machine_word.ty16 -> register_value*) +(*val regval_of_int : ii -> register_value*) + +val _ = Define ` + ((regval_of_int:int -> register_value) v= (Regval_int v))`; + + +(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*) + +val _ = Define ` + ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var= + ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`; + + +(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) val _ = Define ` ((regval_of_vector_16_dec_bit:(16)words$word -> register_value) v= (Regval_vector_16_dec_bit v))`; -(*val vector_1_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty1)*) +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) val _ = Define ` - ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= - ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`; + ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= + ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`; -(*val regval_of_vector_1_dec_bit : Machine_word.mword Machine_word.ty1 -> register_value*) +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) val _ = Define ` ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v= (Regval_vector_1_dec_bit v))`; -(*val vector_257_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty257)*) +(*val vector_257_dec_bit_of_regval : register_value -> maybe (mword ty257)*) val _ = Define ` - ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var= - ((case merge_var of Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`; + ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var= + ((case merge_var of Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`; -(*val regval_of_vector_257_dec_bit : Machine_word.mword Machine_word.ty257 -> register_value*) +(*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) val _ = Define ` ((regval_of_vector_257_dec_bit:(257)words$word -> register_value) v= (Regval_vector_257_dec_bit v))`; -(*val vector_32_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty32)*) +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) val _ = Define ` - ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= - ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`; + ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= + ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`; -(*val regval_of_vector_32_dec_bit : Machine_word.mword Machine_word.ty32 -> register_value*) +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) val _ = Define ` ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`; -(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) val _ = Define ` - ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= - ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`; + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`; -(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*) +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) val _ = Define ` ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; -(*val vector_6_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty6)*) +(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*) val _ = Define ` - ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var= - ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`; + ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var= + ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`; -(*val regval_of_vector_6_dec_bit : Machine_word.mword Machine_word.ty6 -> register_value*) +(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) val _ = Define ` ((regval_of_vector_6_dec_bit:(6)words$word -> register_value) v= (Regval_vector_6_dec_bit v))`; -(*val vector_8_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty8)*) +(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*) val _ = Define ` - ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var= - ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`; + ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var= + ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`; -(*val regval_of_vector_8_dec_bit : Machine_word.mword Machine_word.ty8 -> register_value*) +(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) val _ = Define ` ((regval_of_vector_8_dec_bit:(8)words$word -> register_value) v= (Regval_vector_8_dec_bit v))`; @@ -726,7 +741,7 @@ val _ = Define ` -(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= (\x . (case x of @@ -735,12 +750,12 @@ val _ = Define ` )))`; -(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*) +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) val _ = Define ` ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; -(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= (\x . (case x of @@ -754,20 +769,32 @@ val _ = Define ` ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; -(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*) +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) val _ = Define ` ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= - (\x . (case x of Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`; + (\x . (case x of + Regval_option v => SOME (OPTION_BIND v of_regval) + | _ => NONE + )))`; -(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*) +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) val _ = Define ` ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; val _ = Define ` - ((CapCause_ref:((regstate),(register_value),(CapCauseReg))sail_values$register_ref)= (<| + ((instCount_ref:((regstate),(register_value),(int))register_ref)= (<| + name := "instCount"; + read_from := (\ s . s.instCount); + write_to := (\ v s . (( s with<| instCount := v |>))); + of_regval := (\ v . int_of_regval v); + regval_of := (\ v . regval_of_int v) |>))`; + + +val _ = Define ` + ((CapCause_ref:((regstate),(register_value),(CapCauseReg))register_ref)= (<| name := "CapCause"; read_from := (\ s . s.CapCause); write_to := (\ v s . (( s with<| CapCause := v |>))); @@ -776,7 +803,7 @@ val _ = Define ` val _ = Define ` - ((CTLSP_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((CTLSP_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "CTLSP"; read_from := (\ s . s.CTLSP); write_to := (\ v s . (( s with<| CTLSP := v |>))); @@ -785,7 +812,7 @@ val _ = Define ` val _ = Define ` - ((CTLSU_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((CTLSU_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "CTLSU"; read_from := (\ s . s.CTLSU); write_to := (\ v s . (( s with<| CTLSU := v |>))); @@ -794,7 +821,7 @@ val _ = Define ` val _ = Define ` - ((C30_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C30_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C30"; read_from := (\ s . s.C30); write_to := (\ v s . (( s with<| C30 := v |>))); @@ -803,7 +830,7 @@ val _ = Define ` val _ = Define ` - ((C28_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C28_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C28"; read_from := (\ s . s.C28); write_to := (\ v s . (( s with<| C28 := v |>))); @@ -812,7 +839,7 @@ val _ = Define ` val _ = Define ` - ((C27_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C27_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C27"; read_from := (\ s . s.C27); write_to := (\ v s . (( s with<| C27 := v |>))); @@ -821,7 +848,7 @@ val _ = Define ` val _ = Define ` - ((C26_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C26_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C26"; read_from := (\ s . s.C26); write_to := (\ v s . (( s with<| C26 := v |>))); @@ -830,7 +857,7 @@ val _ = Define ` val _ = Define ` - ((C25_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C25_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C25"; read_from := (\ s . s.C25); write_to := (\ v s . (( s with<| C25 := v |>))); @@ -839,7 +866,7 @@ val _ = Define ` val _ = Define ` - ((C24_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C24_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C24"; read_from := (\ s . s.C24); write_to := (\ v s . (( s with<| C24 := v |>))); @@ -848,7 +875,7 @@ val _ = Define ` val _ = Define ` - ((C23_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C23_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C23"; read_from := (\ s . s.C23); write_to := (\ v s . (( s with<| C23 := v |>))); @@ -857,7 +884,7 @@ val _ = Define ` val _ = Define ` - ((C22_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C22_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C22"; read_from := (\ s . s.C22); write_to := (\ v s . (( s with<| C22 := v |>))); @@ -866,7 +893,7 @@ val _ = Define ` val _ = Define ` - ((C21_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C21_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C21"; read_from := (\ s . s.C21); write_to := (\ v s . (( s with<| C21 := v |>))); @@ -875,7 +902,7 @@ val _ = Define ` val _ = Define ` - ((C20_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C20_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C20"; read_from := (\ s . s.C20); write_to := (\ v s . (( s with<| C20 := v |>))); @@ -884,7 +911,7 @@ val _ = Define ` val _ = Define ` - ((C19_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C19_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C19"; read_from := (\ s . s.C19); write_to := (\ v s . (( s with<| C19 := v |>))); @@ -893,7 +920,7 @@ val _ = Define ` val _ = Define ` - ((C18_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C18_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C18"; read_from := (\ s . s.C18); write_to := (\ v s . (( s with<| C18 := v |>))); @@ -902,7 +929,7 @@ val _ = Define ` val _ = Define ` - ((C17_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C17_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C17"; read_from := (\ s . s.C17); write_to := (\ v s . (( s with<| C17 := v |>))); @@ -911,7 +938,7 @@ val _ = Define ` val _ = Define ` - ((C16_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C16_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C16"; read_from := (\ s . s.C16); write_to := (\ v s . (( s with<| C16 := v |>))); @@ -920,7 +947,7 @@ val _ = Define ` val _ = Define ` - ((C15_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C15_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C15"; read_from := (\ s . s.C15); write_to := (\ v s . (( s with<| C15 := v |>))); @@ -929,7 +956,7 @@ val _ = Define ` val _ = Define ` - ((C14_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C14_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C14"; read_from := (\ s . s.C14); write_to := (\ v s . (( s with<| C14 := v |>))); @@ -938,7 +965,7 @@ val _ = Define ` val _ = Define ` - ((C13_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C13_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C13"; read_from := (\ s . s.C13); write_to := (\ v s . (( s with<| C13 := v |>))); @@ -947,7 +974,7 @@ val _ = Define ` val _ = Define ` - ((C12_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C12_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C12"; read_from := (\ s . s.C12); write_to := (\ v s . (( s with<| C12 := v |>))); @@ -956,7 +983,7 @@ val _ = Define ` val _ = Define ` - ((C11_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C11_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C11"; read_from := (\ s . s.C11); write_to := (\ v s . (( s with<| C11 := v |>))); @@ -965,7 +992,7 @@ val _ = Define ` val _ = Define ` - ((C10_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C10_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C10"; read_from := (\ s . s.C10); write_to := (\ v s . (( s with<| C10 := v |>))); @@ -974,7 +1001,7 @@ val _ = Define ` val _ = Define ` - ((C09_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C09_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C09"; read_from := (\ s . s.C09); write_to := (\ v s . (( s with<| C09 := v |>))); @@ -983,7 +1010,7 @@ val _ = Define ` val _ = Define ` - ((C08_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C08_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C08"; read_from := (\ s . s.C08); write_to := (\ v s . (( s with<| C08 := v |>))); @@ -992,7 +1019,7 @@ val _ = Define ` val _ = Define ` - ((C07_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C07_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C07"; read_from := (\ s . s.C07); write_to := (\ v s . (( s with<| C07 := v |>))); @@ -1001,7 +1028,7 @@ val _ = Define ` val _ = Define ` - ((C06_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C06_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C06"; read_from := (\ s . s.C06); write_to := (\ v s . (( s with<| C06 := v |>))); @@ -1010,7 +1037,7 @@ val _ = Define ` val _ = Define ` - ((C05_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C05_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C05"; read_from := (\ s . s.C05); write_to := (\ v s . (( s with<| C05 := v |>))); @@ -1019,7 +1046,7 @@ val _ = Define ` val _ = Define ` - ((C04_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C04_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C04"; read_from := (\ s . s.C04); write_to := (\ v s . (( s with<| C04 := v |>))); @@ -1028,7 +1055,7 @@ val _ = Define ` val _ = Define ` - ((C03_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C03_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C03"; read_from := (\ s . s.C03); write_to := (\ v s . (( s with<| C03 := v |>))); @@ -1037,7 +1064,7 @@ val _ = Define ` val _ = Define ` - ((C02_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C02_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C02"; read_from := (\ s . s.C02); write_to := (\ v s . (( s with<| C02 := v |>))); @@ -1046,7 +1073,7 @@ val _ = Define ` val _ = Define ` - ((C01_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C01_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C01"; read_from := (\ s . s.C01); write_to := (\ v s . (( s with<| C01 := v |>))); @@ -1055,7 +1082,7 @@ val _ = Define ` val _ = Define ` - ((C00_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C00_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C00"; read_from := (\ s . s.C00); write_to := (\ v s . (( s with<| C00 := v |>))); @@ -1064,7 +1091,7 @@ val _ = Define ` val _ = Define ` - ((inCCallDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((inCCallDelay_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "inCCallDelay"; read_from := (\ s . s.inCCallDelay); write_to := (\ v s . (( s with<| inCCallDelay := v |>))); @@ -1073,7 +1100,7 @@ val _ = Define ` val _ = Define ` - ((nextPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((nextPCC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "nextPCC"; read_from := (\ s . s.nextPCC); write_to := (\ v s . (( s with<| nextPCC := v |>))); @@ -1082,7 +1109,7 @@ val _ = Define ` val _ = Define ` - ((delayedPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((delayedPCC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "delayedPCC"; read_from := (\ s . s.delayedPCC); write_to := (\ v s . (( s with<| delayedPCC := v |>))); @@ -1091,7 +1118,7 @@ val _ = Define ` val _ = Define ` - ((PCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((PCC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "PCC"; read_from := (\ s . s.PCC); write_to := (\ v s . (( s with<| PCC := v |>))); @@ -1100,7 +1127,7 @@ val _ = Define ` val _ = Define ` - ((C31_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C31_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C31"; read_from := (\ s . s.C31); write_to := (\ v s . (( s with<| C31 := v |>))); @@ -1109,7 +1136,7 @@ val _ = Define ` val _ = Define ` - ((C29_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)= (<| + ((C29_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C29"; read_from := (\ s . s.C29); write_to := (\ v s . (( s with<| C29 := v |>))); @@ -1118,7 +1145,7 @@ val _ = Define ` val _ = Define ` - ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "UART_RVALID"; read_from := (\ s . s.UART_RVALID); write_to := (\ v s . (( s with<| UART_RVALID := v |>))); @@ -1127,7 +1154,7 @@ val _ = Define ` val _ = Define ` - ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)= (<| + ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))register_ref)= (<| name := "UART_RDATA"; read_from := (\ s . s.UART_RDATA); write_to := (\ v s . (( s with<| UART_RDATA := v |>))); @@ -1136,7 +1163,7 @@ val _ = Define ` val _ = Define ` - ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "UART_WRITTEN"; read_from := (\ s . s.UART_WRITTEN); write_to := (\ v s . (( s with<| UART_WRITTEN := v |>))); @@ -1145,7 +1172,7 @@ val _ = Define ` val _ = Define ` - ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)= (<| + ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))register_ref)= (<| name := "UART_WDATA"; read_from := (\ s . s.UART_WDATA); write_to := (\ v s . (( s with<| UART_WDATA := v |>))); @@ -1154,7 +1181,7 @@ val _ = Define ` val _ = Define ` - ((GPR_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)= (<| + ((GPR_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| name := "GPR"; read_from := (\ s . s.GPR); write_to := (\ v s . (( s with<| GPR := v |>))); @@ -1163,7 +1190,7 @@ val _ = Define ` val _ = Define ` - ((LO_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((LO_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "LO"; read_from := (\ s . s.LO); write_to := (\ v s . (( s with<| LO := v |>))); @@ -1172,7 +1199,7 @@ val _ = Define ` val _ = Define ` - ((HI_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((HI_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "HI"; read_from := (\ s . s.HI); write_to := (\ v s . (( s with<| HI := v |>))); @@ -1181,7 +1208,7 @@ val _ = Define ` val _ = Define ` - ((delayedPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((delayedPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "delayedPC"; read_from := (\ s . s.delayedPC); write_to := (\ v s . (( s with<| delayedPC := v |>))); @@ -1190,7 +1217,7 @@ val _ = Define ` val _ = Define ` - ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "inBranchDelay"; read_from := (\ s . s.inBranchDelay); write_to := (\ v s . (( s with<| inBranchDelay := v |>))); @@ -1199,7 +1226,7 @@ val _ = Define ` val _ = Define ` - ((branchPending_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((branchPending_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "branchPending"; read_from := (\ s . s.branchPending); write_to := (\ v s . (( s with<| branchPending := v |>))); @@ -1208,7 +1235,7 @@ val _ = Define ` val _ = Define ` - ((CP0Status_ref:((regstate),(register_value),(StatusReg))sail_values$register_ref)= (<| + ((CP0Status_ref:((regstate),(register_value),(StatusReg))register_ref)= (<| name := "CP0Status"; read_from := (\ s . s.CP0Status); write_to := (\ v s . (( s with<| CP0Status := v |>))); @@ -1217,7 +1244,7 @@ val _ = Define ` val _ = Define ` - ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0UserLocal"; read_from := (\ s . s.CP0UserLocal); write_to := (\ v s . (( s with<| CP0UserLocal := v |>))); @@ -1226,7 +1253,7 @@ val _ = Define ` val _ = Define ` - ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| name := "CP0HWREna"; read_from := (\ s . s.CP0HWREna); write_to := (\ v s . (( s with<| CP0HWREna := v |>))); @@ -1235,7 +1262,7 @@ val _ = Define ` val _ = Define ` - ((CP0Count_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + ((CP0Count_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| name := "CP0Count"; read_from := (\ s . s.CP0Count); write_to := (\ v s . (( s with<| CP0Count := v |>))); @@ -1244,7 +1271,7 @@ val _ = Define ` val _ = Define ` - ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0BadVAddr"; read_from := (\ s . s.CP0BadVAddr); write_to := (\ v s . (( s with<| CP0BadVAddr := v |>))); @@ -1253,7 +1280,7 @@ val _ = Define ` val _ = Define ` - ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0LLAddr"; read_from := (\ s . s.CP0LLAddr); write_to := (\ v s . (( s with<| CP0LLAddr := v |>))); @@ -1262,7 +1289,7 @@ val _ = Define ` val _ = Define ` - ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "CP0LLBit"; read_from := (\ s . s.CP0LLBit); write_to := (\ v s . (( s with<| CP0LLBit := v |>))); @@ -1271,7 +1298,7 @@ val _ = Define ` val _ = Define ` - ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0ErrorEPC"; read_from := (\ s . s.CP0ErrorEPC); write_to := (\ v s . (( s with<| CP0ErrorEPC := v |>))); @@ -1280,7 +1307,7 @@ val _ = Define ` val _ = Define ` - ((CP0EPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((CP0EPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0EPC"; read_from := (\ s . s.CP0EPC); write_to := (\ v s . (( s with<| CP0EPC := v |>))); @@ -1289,7 +1316,7 @@ val _ = Define ` val _ = Define ` - ((CP0Cause_ref:((regstate),(register_value),(CauseReg))sail_values$register_ref)= (<| + ((CP0Cause_ref:((regstate),(register_value),(CauseReg))register_ref)= (<| name := "CP0Cause"; read_from := (\ s . s.CP0Cause); write_to := (\ v s . (( s with<| CP0Cause := v |>))); @@ -1298,7 +1325,7 @@ val _ = Define ` val _ = Define ` - ((CP0Compare_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)= (<| + ((CP0Compare_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| name := "CP0Compare"; read_from := (\ s . s.CP0Compare); write_to := (\ v s . (( s with<| CP0Compare := v |>))); @@ -1307,7 +1334,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry63"; read_from := (\ s . s.TLBEntry63); write_to := (\ v s . (( s with<| TLBEntry63 := v |>))); @@ -1316,7 +1343,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry62"; read_from := (\ s . s.TLBEntry62); write_to := (\ v s . (( s with<| TLBEntry62 := v |>))); @@ -1325,7 +1352,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry61"; read_from := (\ s . s.TLBEntry61); write_to := (\ v s . (( s with<| TLBEntry61 := v |>))); @@ -1334,7 +1361,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry60"; read_from := (\ s . s.TLBEntry60); write_to := (\ v s . (( s with<| TLBEntry60 := v |>))); @@ -1343,7 +1370,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry59"; read_from := (\ s . s.TLBEntry59); write_to := (\ v s . (( s with<| TLBEntry59 := v |>))); @@ -1352,7 +1379,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry58"; read_from := (\ s . s.TLBEntry58); write_to := (\ v s . (( s with<| TLBEntry58 := v |>))); @@ -1361,7 +1388,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry57"; read_from := (\ s . s.TLBEntry57); write_to := (\ v s . (( s with<| TLBEntry57 := v |>))); @@ -1370,7 +1397,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry56"; read_from := (\ s . s.TLBEntry56); write_to := (\ v s . (( s with<| TLBEntry56 := v |>))); @@ -1379,7 +1406,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry55"; read_from := (\ s . s.TLBEntry55); write_to := (\ v s . (( s with<| TLBEntry55 := v |>))); @@ -1388,7 +1415,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry54"; read_from := (\ s . s.TLBEntry54); write_to := (\ v s . (( s with<| TLBEntry54 := v |>))); @@ -1397,7 +1424,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry53"; read_from := (\ s . s.TLBEntry53); write_to := (\ v s . (( s with<| TLBEntry53 := v |>))); @@ -1406,7 +1433,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry52"; read_from := (\ s . s.TLBEntry52); write_to := (\ v s . (( s with<| TLBEntry52 := v |>))); @@ -1415,7 +1442,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry51"; read_from := (\ s . s.TLBEntry51); write_to := (\ v s . (( s with<| TLBEntry51 := v |>))); @@ -1424,7 +1451,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry50"; read_from := (\ s . s.TLBEntry50); write_to := (\ v s . (( s with<| TLBEntry50 := v |>))); @@ -1433,7 +1460,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry49"; read_from := (\ s . s.TLBEntry49); write_to := (\ v s . (( s with<| TLBEntry49 := v |>))); @@ -1442,7 +1469,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry48"; read_from := (\ s . s.TLBEntry48); write_to := (\ v s . (( s with<| TLBEntry48 := v |>))); @@ -1451,7 +1478,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry47"; read_from := (\ s . s.TLBEntry47); write_to := (\ v s . (( s with<| TLBEntry47 := v |>))); @@ -1460,7 +1487,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry46"; read_from := (\ s . s.TLBEntry46); write_to := (\ v s . (( s with<| TLBEntry46 := v |>))); @@ -1469,7 +1496,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry45"; read_from := (\ s . s.TLBEntry45); write_to := (\ v s . (( s with<| TLBEntry45 := v |>))); @@ -1478,7 +1505,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry44"; read_from := (\ s . s.TLBEntry44); write_to := (\ v s . (( s with<| TLBEntry44 := v |>))); @@ -1487,7 +1514,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry43"; read_from := (\ s . s.TLBEntry43); write_to := (\ v s . (( s with<| TLBEntry43 := v |>))); @@ -1496,7 +1523,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry42"; read_from := (\ s . s.TLBEntry42); write_to := (\ v s . (( s with<| TLBEntry42 := v |>))); @@ -1505,7 +1532,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry41"; read_from := (\ s . s.TLBEntry41); write_to := (\ v s . (( s with<| TLBEntry41 := v |>))); @@ -1514,7 +1541,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry40"; read_from := (\ s . s.TLBEntry40); write_to := (\ v s . (( s with<| TLBEntry40 := v |>))); @@ -1523,7 +1550,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry39"; read_from := (\ s . s.TLBEntry39); write_to := (\ v s . (( s with<| TLBEntry39 := v |>))); @@ -1532,7 +1559,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry38"; read_from := (\ s . s.TLBEntry38); write_to := (\ v s . (( s with<| TLBEntry38 := v |>))); @@ -1541,7 +1568,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry37"; read_from := (\ s . s.TLBEntry37); write_to := (\ v s . (( s with<| TLBEntry37 := v |>))); @@ -1550,7 +1577,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry36"; read_from := (\ s . s.TLBEntry36); write_to := (\ v s . (( s with<| TLBEntry36 := v |>))); @@ -1559,7 +1586,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry35"; read_from := (\ s . s.TLBEntry35); write_to := (\ v s . (( s with<| TLBEntry35 := v |>))); @@ -1568,7 +1595,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry34"; read_from := (\ s . s.TLBEntry34); write_to := (\ v s . (( s with<| TLBEntry34 := v |>))); @@ -1577,7 +1604,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry33"; read_from := (\ s . s.TLBEntry33); write_to := (\ v s . (( s with<| TLBEntry33 := v |>))); @@ -1586,7 +1613,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry32"; read_from := (\ s . s.TLBEntry32); write_to := (\ v s . (( s with<| TLBEntry32 := v |>))); @@ -1595,7 +1622,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry31"; read_from := (\ s . s.TLBEntry31); write_to := (\ v s . (( s with<| TLBEntry31 := v |>))); @@ -1604,7 +1631,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry30"; read_from := (\ s . s.TLBEntry30); write_to := (\ v s . (( s with<| TLBEntry30 := v |>))); @@ -1613,7 +1640,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry29"; read_from := (\ s . s.TLBEntry29); write_to := (\ v s . (( s with<| TLBEntry29 := v |>))); @@ -1622,7 +1649,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry28"; read_from := (\ s . s.TLBEntry28); write_to := (\ v s . (( s with<| TLBEntry28 := v |>))); @@ -1631,7 +1658,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry27"; read_from := (\ s . s.TLBEntry27); write_to := (\ v s . (( s with<| TLBEntry27 := v |>))); @@ -1640,7 +1667,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry26"; read_from := (\ s . s.TLBEntry26); write_to := (\ v s . (( s with<| TLBEntry26 := v |>))); @@ -1649,7 +1676,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry25"; read_from := (\ s . s.TLBEntry25); write_to := (\ v s . (( s with<| TLBEntry25 := v |>))); @@ -1658,7 +1685,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry24"; read_from := (\ s . s.TLBEntry24); write_to := (\ v s . (( s with<| TLBEntry24 := v |>))); @@ -1667,7 +1694,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry23"; read_from := (\ s . s.TLBEntry23); write_to := (\ v s . (( s with<| TLBEntry23 := v |>))); @@ -1676,7 +1703,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry22"; read_from := (\ s . s.TLBEntry22); write_to := (\ v s . (( s with<| TLBEntry22 := v |>))); @@ -1685,7 +1712,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry21"; read_from := (\ s . s.TLBEntry21); write_to := (\ v s . (( s with<| TLBEntry21 := v |>))); @@ -1694,7 +1721,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry20"; read_from := (\ s . s.TLBEntry20); write_to := (\ v s . (( s with<| TLBEntry20 := v |>))); @@ -1703,7 +1730,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry19"; read_from := (\ s . s.TLBEntry19); write_to := (\ v s . (( s with<| TLBEntry19 := v |>))); @@ -1712,7 +1739,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry18"; read_from := (\ s . s.TLBEntry18); write_to := (\ v s . (( s with<| TLBEntry18 := v |>))); @@ -1721,7 +1748,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry17"; read_from := (\ s . s.TLBEntry17); write_to := (\ v s . (( s with<| TLBEntry17 := v |>))); @@ -1730,7 +1757,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry16"; read_from := (\ s . s.TLBEntry16); write_to := (\ v s . (( s with<| TLBEntry16 := v |>))); @@ -1739,7 +1766,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry15"; read_from := (\ s . s.TLBEntry15); write_to := (\ v s . (( s with<| TLBEntry15 := v |>))); @@ -1748,7 +1775,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry14"; read_from := (\ s . s.TLBEntry14); write_to := (\ v s . (( s with<| TLBEntry14 := v |>))); @@ -1757,7 +1784,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry13"; read_from := (\ s . s.TLBEntry13); write_to := (\ v s . (( s with<| TLBEntry13 := v |>))); @@ -1766,7 +1793,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry12"; read_from := (\ s . s.TLBEntry12); write_to := (\ v s . (( s with<| TLBEntry12 := v |>))); @@ -1775,7 +1802,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry11"; read_from := (\ s . s.TLBEntry11); write_to := (\ v s . (( s with<| TLBEntry11 := v |>))); @@ -1784,7 +1811,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry10"; read_from := (\ s . s.TLBEntry10); write_to := (\ v s . (( s with<| TLBEntry10 := v |>))); @@ -1793,7 +1820,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry09"; read_from := (\ s . s.TLBEntry09); write_to := (\ v s . (( s with<| TLBEntry09 := v |>))); @@ -1802,7 +1829,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry08"; read_from := (\ s . s.TLBEntry08); write_to := (\ v s . (( s with<| TLBEntry08 := v |>))); @@ -1811,7 +1838,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry07"; read_from := (\ s . s.TLBEntry07); write_to := (\ v s . (( s with<| TLBEntry07 := v |>))); @@ -1820,7 +1847,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry06"; read_from := (\ s . s.TLBEntry06); write_to := (\ v s . (( s with<| TLBEntry06 := v |>))); @@ -1829,7 +1856,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry05"; read_from := (\ s . s.TLBEntry05); write_to := (\ v s . (( s with<| TLBEntry05 := v |>))); @@ -1838,7 +1865,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry04"; read_from := (\ s . s.TLBEntry04); write_to := (\ v s . (( s with<| TLBEntry04 := v |>))); @@ -1847,7 +1874,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry03"; read_from := (\ s . s.TLBEntry03); write_to := (\ v s . (( s with<| TLBEntry03 := v |>))); @@ -1856,7 +1883,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry02"; read_from := (\ s . s.TLBEntry02); write_to := (\ v s . (( s with<| TLBEntry02 := v |>))); @@ -1865,7 +1892,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry01"; read_from := (\ s . s.TLBEntry01); write_to := (\ v s . (( s with<| TLBEntry01 := v |>))); @@ -1874,7 +1901,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)= (<| + ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| name := "TLBEntry00"; read_from := (\ s . s.TLBEntry00); write_to := (\ v s . (( s with<| TLBEntry00 := v |>))); @@ -1883,7 +1910,7 @@ val _ = Define ` val _ = Define ` - ((TLBXContext_ref:((regstate),(register_value),(XContextReg))sail_values$register_ref)= (<| + ((TLBXContext_ref:((regstate),(register_value),(XContextReg))register_ref)= (<| name := "TLBXContext"; read_from := (\ s . s.TLBXContext); write_to := (\ v s . (( s with<| TLBXContext := v |>))); @@ -1892,7 +1919,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))sail_values$register_ref)= (<| + ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))register_ref)= (<| name := "TLBEntryHi"; read_from := (\ s . s.TLBEntryHi); write_to := (\ v s . (( s with<| TLBEntryHi := v |>))); @@ -1901,7 +1928,7 @@ val _ = Define ` val _ = Define ` - ((TLBWired_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + ((TLBWired_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| name := "TLBWired"; read_from := (\ s . s.TLBWired); write_to := (\ v s . (( s with<| TLBWired := v |>))); @@ -1910,7 +1937,7 @@ val _ = Define ` val _ = Define ` - ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))sail_values$register_ref)= (<| + ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))register_ref)= (<| name := "TLBPageMask"; read_from := (\ s . s.TLBPageMask); write_to := (\ v s . (( s with<| TLBPageMask := v |>))); @@ -1919,7 +1946,7 @@ val _ = Define ` val _ = Define ` - ((TLBContext_ref:((regstate),(register_value),(ContextReg))sail_values$register_ref)= (<| + ((TLBContext_ref:((regstate),(register_value),(ContextReg))register_ref)= (<| name := "TLBContext"; read_from := (\ s . s.TLBContext); write_to := (\ v s . (( s with<| TLBContext := v |>))); @@ -1928,7 +1955,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)= (<| + ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)= (<| name := "TLBEntryLo1"; read_from := (\ s . s.TLBEntryLo1); write_to := (\ v s . (( s with<| TLBEntryLo1 := v |>))); @@ -1937,7 +1964,7 @@ val _ = Define ` val _ = Define ` - ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)= (<| + ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)= (<| name := "TLBEntryLo0"; read_from := (\ s . s.TLBEntryLo0); write_to := (\ v s . (( s with<| TLBEntryLo0 := v |>))); @@ -1946,7 +1973,7 @@ val _ = Define ` val _ = Define ` - ((TLBRandom_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + ((TLBRandom_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| name := "TLBRandom"; read_from := (\ s . s.TLBRandom); write_to := (\ v s . (( s with<| TLBRandom := v |>))); @@ -1955,7 +1982,7 @@ val _ = Define ` val _ = Define ` - ((TLBIndex_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)= (<| + ((TLBIndex_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| name := "TLBIndex"; read_from := (\ s . s.TLBIndex); write_to := (\ v s . (( s with<| TLBIndex := v |>))); @@ -1964,7 +1991,7 @@ val _ = Define ` val _ = Define ` - ((TLBProbe_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)= (<| + ((TLBProbe_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| name := "TLBProbe"; read_from := (\ s . s.TLBProbe); write_to := (\ v s . (( s with<| TLBProbe := v |>))); @@ -1973,7 +2000,7 @@ val _ = Define ` val _ = Define ` - ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((nextPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "nextPC"; read_from := (\ s . s.nextPC); write_to := (\ v s . (( s with<| nextPC := v |>))); @@ -1982,7 +2009,7 @@ val _ = Define ` val _ = Define ` - ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "PC"; read_from := (\ s . s.PC); write_to := (\ v s . (( s with<| PC := v |>))); @@ -1990,10 +2017,11 @@ val _ = Define ` regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; -(*val get_regval : string -> regstate -> Maybe.maybe register_value*) +(*val get_regval : string -> regstate -> maybe register_value*) val _ = Define ` - ((get_regval:string -> regstate ->(register_value)option) reg_name s= - (if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "instCount" then SOME (instCount_ref.regval_of (instCount_ref.read_from s)) else + if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else if reg_name = "CTLSP" then SOME (CTLSP_ref.regval_of (CTLSP_ref.read_from s)) else if reg_name = "CTLSU" then SOME (CTLSU_ref.regval_of (CTLSU_ref.read_from s)) else if reg_name = "C30" then SOME (C30_ref.regval_of (C30_ref.read_from s)) else @@ -2132,10 +2160,11 @@ val _ = Define ` NONE))`; -(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*) +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) val _ = Define ` - ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= - (if reg_name = "CapCause" then OPTION_MAP (\ v . CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "instCount" then OPTION_MAP (\ v . instCount_ref.write_to v s) (instCount_ref.of_regval v) else + if reg_name = "CapCause" then OPTION_MAP (\ v . CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else if reg_name = "CTLSP" then OPTION_MAP (\ v . CTLSP_ref.write_to v s) (CTLSP_ref.of_regval v) else if reg_name = "CTLSU" then OPTION_MAP (\ v . CTLSU_ref.write_to v s) (CTLSU_ref.of_regval v) else if reg_name = "C30" then OPTION_MAP (\ v . C30_ref.write_to v s) (C30_ref.of_regval v) else @@ -2279,7 +2308,7 @@ val _ = Define ` -val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``); -val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``); +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``); val _ = export_theory() diff --git a/snapshots/hol4/sail/cheri/mips_extrasScript.sml b/snapshots/hol4/sail/cheri/mips_extrasScript.sml new file mode 100644 index 00000000..399ecc93 --- /dev/null +++ b/snapshots/hol4/sail/cheri/mips_extrasScript.sml @@ -0,0 +1,252 @@ +(*Generated by Lem from /usr/local/google/home/ramanakumar/cheri/sail/mips/mips_extras.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory prompt_monadTheory promptTheory sail_operatorsTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "mips_extras" + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) + +val _ = Define ` + ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`; + +val _ = Define ` + ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`; + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +val _ = Define ` + ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a addr= (state_monad$bindS + (state_monad$read_tagS + dict_Sail_values_Bitvector_a addr) (\ t . + state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`; + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +val _ = Define ` + ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr t= (state_monad$bindS (state_monad$write_tagS + dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) + (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; + + +val _ = Define ` + ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$bindS + (state_monad$read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . state_monad$bindS + (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . + state_monad$returnS (t, v)))))`; + + +val _ = Define ` + ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$bindS + (state_monad$read_memS + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . state_monad$bindS + (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . + state_monad$returnS (t, v)))))`; + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) + +val _ = Define ` + ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS + dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS + dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + +val _ = Define ` + ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS + dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS + dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) + +val _ = Define ` + ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (state_monad$bindS (state_monad$write_mem_valS + dict_Sail_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; + +val _ = Define ` + ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (state_monad$bindS (state_monad$write_mem_valS + dict_Sail_values_Bitvector_b v) (\ b . state_monad$returnS (if b then T else F))))`; + +val _ = Define ` + ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (state_monad$bindS (state_monad$write_mem_valS + dict_Sail_values_Bitvector_b v) (\b . (case (b ) of + ( _ ) => state_monad$bindS + (write_tag_bool dict_Sail_values_Bitvector_a addr t) + (\u . (case (u ) of + ( _ ) => state_monad$returnS () + )) + ))))`; + +val _ = Define ` + ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (state_monad$bindS (state_monad$write_mem_valS + dict_Sail_values_Bitvector_b v) (\ b . state_monad$bindS (write_tag_bool + dict_Sail_values_Bitvector_a addr t) (\u . (case (u ) of ( _ ) => state_monad$returnS (if b then T else F) )))))`; + + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +val _ = Define ` + ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () = (barrier Barrier_MIPS_SYNC))`; + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +val _ = Define ` + ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo= + ( + (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in + let bs = (bools_of_int (hi +( 1 : int)) n) in + subrange_list F bs hi lo))`; + + +(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +val _ = Define ` + ((get_slice_int0:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= ( + dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; + + +val _ = Define ` + ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data= (state_monad$seqS + (MEMea dict_Sail_values_Bitvector_b addr size1) + (MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`; + + +val _ = Define ` + ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr= (MEMr + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`; + + +val _ = Define ` + ((string_of_bits:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs= (string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`; + +val _ = Define ` + ((string_of_int:'a Show_class -> 'a -> string)dict_Show_Show_a= + (dict_Show_Show_a.show_method))`; + + +val _ = Define ` + ((sign_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( + dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`; + +val _ = Define ` + ((zero_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( + dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`; + + +val _ = Define ` + ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + state_monad$maybe_failS "shift_bits_left" r))`; + +val _ = Define ` + ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + state_monad$maybe_failS "shift_bits_right" r))`; + +val _ = Define ` + ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + state_monad$maybe_failS "shift_bits_right_arith" r))`; + + +(* Use constants for undefined values for now *) +val _ = Define ` + ((internal_pick:'a list -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) vs= (state_monad$returnS (HD vs)))`; + +val _ = Define ` + ((undefined_string:unit -> 'a state_monad$sequential_state ->(((string),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS ""))`; + +val _ = Define ` + ((undefined_unit:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS () ))`; + +val _ = Define ` + ((undefined_int:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (( 0 : int):ii)))`; + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +val _ = Define ` + ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u= (state_monad$returnS (repeat [u] len)))`; + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +val _ = Define ` + ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a len= (state_monad$returnS ( + dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`; + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +val _ = Define ` + ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a= + (undefined_bitvector dict_Sail_values_Bitvector_a))`; + +val _ = Define ` + ((undefined_bit:unit -> 'a state_monad$sequential_state ->(((bitU),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS B0))`; + +val _ = Define ` + ((undefined_real:unit -> 'a state_monad$sequential_state ->(((real),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; + +val _ = Define ` + ((undefined_range:'a -> 'd -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i j= (state_monad$returnS i))`; + +val _ = Define ` + ((undefined_atom:'a -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i= (state_monad$returnS i))`; + +val _ = Define ` + ((undefined_nat:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (( 0 : int):ii)))`; + + +val _ = Define ` + ((skip:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS () ))`; + + +(*val elf_entry : unit -> integer*) +val _ = Define ` + ((elf_entry:unit -> int) () = (( 0 : int)))`; + + +val _ = Define ` + ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail_values_Bitvector_a msg bs= (prerr_endline ( STRCAT msg (string_of_bits + dict_Sail_values_Bitvector_a bs))))`; + + +(*val get_time_ns : unit -> integer*) +val _ = Define ` + ((get_time_ns:unit -> int) () = (( 0 : int)))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml b/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml deleted file mode 100644 index 26c1d0a7..00000000 --- a/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml +++ /dev/null @@ -1,235 +0,0 @@ -(*Generated by Lem from /home/bcampbe2/local/rems/github/sail/mips/mips_extras_sequential.lem.*) -open HolKernel Parse boolLib bossLib; -open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory state_monadTheory stateTheory sail_operatorsTheory; - -val _ = numLib.prefer_num(); - - - -val _ = new_theory "mips_extras_sequential" - -(*open import Pervasives*) -(*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import State_monad*) -(*open import State*) - -(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*) -(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*) -(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*) -(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*) - -val _ = Define ` - ((MEMr:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`; - -val _ = Define ` - ((MEMr_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`; - - -(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> State_monad.monadS 'regval bool 'e*) -val _ = Define ` - ((read_tag_bool:'a sail_values$Bitvector_class -> 'a ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr= (bindS -(read_tagS dict_Sail_values_Bitvector_a addr) (\ t . - maybe_failS "read_tag_bool" (bool_of_bitU t))))`; - - -(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> State_monad.monadS 'regval unit 'e*) -val _ = Define ` - ((write_tag_bool:'a sail_values$Bitvector_class -> 'a -> bool ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr t= (bindS (write_tagS - dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) - (\b . (case (b ) of ( _ ) => returnS () ))))`; - - -val _ = Define ` - ((MEMr_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (bindS -(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . bindS -(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . - returnS (t, v)))))`; - - -val _ = Define ` - ((MEMr_tag_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (bindS -(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . bindS -(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . - returnS (t, v)))))`; - - - -(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) -(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) -(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) -(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*) - -val _ = Define ` - ((MEMea:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS - dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; - -val _ = Define ` - ((MEMea_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS - dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; - - -val _ = Define ` - ((MEMea_tag:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS - dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; - -val _ = Define ` - ((MEMea_tag_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1= (write_mem_eaS - dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; - - - -(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval unit 'e*) -(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval bool 'e*) -(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval unit 'e*) -(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval bool 'e*) - -val _ = Define ` - ((MEMval:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (bindS (write_mem_valS - dict_Sail_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => returnS () ))))`; - -val _ = Define ` - ((MEMval_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (bindS (write_mem_valS - dict_Sail_values_Bitvector_b v) (\ b . returnS (if b then T else F))))`; - -val _ = Define ` - ((MEMval_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (bindS (write_mem_valS - dict_Sail_values_Bitvector_b v) (\b . (case (b ) of - ( _ ) => bindS - (write_tag_bool dict_Sail_values_Bitvector_a addr t) - (\u . (case (u ) of ( _ ) => returnS () )) - ))))`; - -val _ = Define ` - ((MEMval_tag_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (bindS (write_mem_valS - dict_Sail_values_Bitvector_b v) (\ b . bindS (write_tag_bool - dict_Sail_values_Bitvector_a addr t) (\u . (case (u ) of ( _ ) => returnS (if b then T else F) )))))`; - - -(*val MEM_sync : forall 'regval 'e. unit -> State_monad.monadS 'regval unit 'e*) - -val _ = Define ` - ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () = (returnS () ))`; - (*barrier Barrier_MIPS_SYNC*) - -(* Some wrappers copied from aarch64_extras *) -(* TODO: Harmonise into a common library *) - -val _ = Define ` - ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo= -( - (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in - let bs = (bools_of_int (hi +( 1 : int)) n) in - subrange_list F bs hi lo))`; - - -(*val get_slice_int : forall 'a. Bitvector 'a => Num.integer -> Num.integer -> Num.integer -> 'a*) -val _ = Define ` - ((get_slice_int:'a sail_values$Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= ( - dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; - - -val _ = Define ` - ((write_ram:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data= (seqS -(MEMea dict_Sail_values_Bitvector_b addr size1) -(MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`; - - -val _ = Define ` - ((read_ram:'a sail_values$Bitvector_class -> 'c sail_values$Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr= (MEMr - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`; - - -val _ = Define ` - ((string_of_bits:'a sail_values$Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs= (string_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`; - -val _ = Define ` - ((string_of_int:'a lem_show$Show_class -> 'a -> string)dict_Show_Show_a= - (dict_Show_Show_a.show_method))`; - - -val _ = Define ` - ((sign_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( - dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`; - -val _ = Define ` - ((zero_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( - dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`; - - -val _ = Define ` - ((shift_bits_left:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= - (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in - maybe_failS "shift_bits_left" r))`; - -val _ = Define ` - ((shift_bits_right:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= - (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in - maybe_failS "shift_bits_right" r))`; - -val _ = Define ` - ((shift_bits_right_arith:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= - (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in - maybe_failS "shift_bits_right_arith" r))`; - - -(* Use constants for undefined values for now *) -val _ = Define ` - ((internal_pick:'a list -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) vs= (returnS (HD vs)))`; - -val _ = Define ` - ((undefined_bool0:unit ->('c,(bool),'a)state_monad$monadS)= undefined_boolS)`; - -val _ = Define ` - ((undefined_string:unit -> 'b state_monad$sequential_state ->(((string),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS ""))`; - -val _ = Define ` - ((undefined_unit:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS () ))`; - -val _ = Define ` - ((undefined_int:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (( 0 : int):sail_values$ii)))`; - -(*val undefined_vector : forall 'rv 'a 'e. Num.integer -> 'a -> State_monad.monadS 'rv (list 'a) 'e*) -val _ = Define ` - ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u= (returnS (repeat [u] len)))`; - -(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*) -val _ = Define ` - ((undefined_bitvector:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a len= (returnS ( - dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`; - -(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*) -val _ = Define ` - ((undefined_bits:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a= - (undefined_bitvector dict_Sail_values_Bitvector_a))`; - -val _ = Define ` - ((undefined_bit:unit -> 'b state_monad$sequential_state ->(((sail_values$bitU),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS B0))`; - -val _ = Define ` - ((undefined_real:unit -> 'b state_monad$sequential_state ->(((real),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; - -val _ = Define ` - ((undefined_range:'a -> 'd -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i j= (returnS i))`; - -val _ = Define ` - ((undefined_atom:'a -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i= (returnS i))`; - -val _ = Define ` - ((undefined_nat:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS (( 0 : int):sail_values$ii)))`; - - -val _ = Define ` - ((skip:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (returnS () ))`; - -val _ = export_theory() - diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile index e8b34295..38611ee1 100644 --- a/snapshots/hol4/sail/lib/hol/Holmakefile +++ b/snapshots/hol4/sail/lib/hol/Holmakefile @@ -1,8 +1,11 @@ -SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \ +LEM_SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \ sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \ state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml -#EXTRA_CLEANS = $(SCRIPTS) +LEM_CLEANS = $(LEM_SCRIPTS) + +SCRIPTS = $(LEM_SCRIPTS) \ + sail_valuesAuxiliaryScript.sml THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS)) @@ -13,9 +16,11 @@ INCLUDES = $(LEMDIR) all: $(THYS) .PHONY: all +# EXTRA_CLEANS = $(LEM_CLEANS) + ifdef POLY HOLHEAP = sail-heap -#EXTRA_CLEANS = $(SCRIPTS) $(HOLHEAP) $(HOLHEAP).o +# EXTRA_CLEANS = $(LEM_CLEANS) $(HOLHEAP) $(HOLHEAP).o EXTRA_CLEANS = $(HOLHEAP) $(HOLHEAP).o BASE_HEAP = $(LEMDIR)/lemheap diff --git a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml b/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml index 627620ff..7c18567b 100644 --- a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml +++ b/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml @@ -16,9 +16,16 @@ val _ = new_theory "prompt_monad" (* Fake interface of the prompt monad by redirecting to the state monad, since the former is not currently supported by HOL4 *) -val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) state_monad$monadS``); -val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) state_monad$monadRS``); +val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e) *) "monad" , ``:('a_rv,'b_a,'c_e) monadS``); +val _ = type_abbrev((* ( 'a_rv, 'b_a, 'c_e, 'd_r) *) "monadR" , ``:('a_rv,'b_a,'c_e,'d_r) monadRS``); + +(* We need to use a target_rep for these because HOL doesn't handle unused + type parameters well. *) + +(*type base_monad 'regval 'regstate 'a 'e = monad 'regstate 'a 'e*) +(*type base_monadR 'regval 'regstate 'a 'r 'e = monadR 'regstate 'a 'r 'e*) val _ = Define ` - ((barrier:'c -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) _= (returnS () ))`; + ((barrier:'c -> 'a sequential_state ->(((unit),'b)result#'a sequential_state)set) _= (returnS () ))`; + val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml b/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml index cfe0ac60..5a119d61 100644 --- a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml @@ -68,31 +68,31 @@ val _ = Hol_datatype ` -(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> Basic_classes.ordering*) +(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*) val _ = Define ` - ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> lem_basic_classes$ordering)dict_Sail_instr_kinds_EnumerationType_a e1 e2= -(genericCompare (<) (=) ( + ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail_instr_kinds_EnumerationType_a e1 e2= + (genericCompare (<) (=) ( dict_Sail_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail_instr_kinds_EnumerationType_a.toNat_method e2)))`; val _ = Define ` -((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a lem_basic_classes$Ord_class)dict_Sail_instr_kinds_EnumerationType_a= (<| +((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail_instr_kinds_EnumerationType_a= (<| compare_method := (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a); isLess_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT); + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LESS); isLessEqual_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> GT); + dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> GREATER); isGreater_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT); + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GREATER); isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> LT)|>))`; + dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`; @@ -117,7 +117,7 @@ val _ = Hol_datatype ` (* the read part of a lock'd instruction (rmw) *) val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_read_kind_dict:(read_kind)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<| show_method := (\x . (case x of @@ -153,7 +153,7 @@ val _ = Hol_datatype ` (* the write part of a lock'd instruction (rmw) *) val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_write_kind_dict:(write_kind)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<| show_method := (\x . (case x of @@ -194,7 +194,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<| show_method := (\x . (case x of @@ -228,7 +228,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_trans_kind_dict:(trans_kind)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<| show_method := (\x . (case x of @@ -253,7 +253,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_instruction_kind_dict:(instruction_kind)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<| show_method := (\x . (case x of diff --git a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml index f1f0c8d4..78109827 100644 --- a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml @@ -14,30 +14,30 @@ val _ = new_theory "sail_operators" (*** Bit vector operations *) -(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list Sail_values.bitU*) +(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*) val _ = Define ` - ((concat_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> 'b ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r= ( + ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r= ( dict_Sail_values_Bitvector_a.bits_of_method l ++ dict_Sail_values_Bitvector_b.bits_of_method r))`; -(*val cons_bv : forall 'a. Bitvector 'a => Sail_values.bitU -> 'a -> list Sail_values.bitU*) +(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*) val _ = Define ` - ((cons_bv:'a sail_values$Bitvector_class -> sail_values$bitU -> 'a ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a b v= (b :: + ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a b v= (b :: dict_Sail_values_Bitvector_a.bits_of_method v))`; -(*val cast_unit_bv : Sail_values.bitU -> list Sail_values.bitU*) +(*val cast_unit_bv : bitU -> list bitU*) val _ = Define ` - ((cast_unit_bv:sail_values$bitU ->(sail_values$bitU)list) b= ([b]))`; + ((cast_unit_bv:bitU ->(bitU)list) b= ([b]))`; -(*val bv_of_bit : Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +(*val bv_of_bit : integer -> bitU -> list bitU*) val _ = Define ` - ((bv_of_bit:int -> sail_values$bitU ->(sail_values$bitU)list) len b= (extz_bits len [b]))`; + ((bv_of_bit:int -> bitU ->(bitU)list) len b= (extz_bits len [b]))`; val _ = Define ` - ((most_significant:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU)dict_Sail_values_Bitvector_a v= ((case + ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail_values_Bitvector_a v= ((case dict_Sail_values_Bitvector_a.bits_of_method v of b :: _ => b | _ => B0 (* Treat empty bitvector as all zeros *) @@ -45,8 +45,8 @@ val _ = Define ` val _ = Define ` - ((get_max_representable_in:bool -> int -> int) sign (n : int) : int= - (if (n =( 64 : int)) then (case sign of T => max_64 | F => max_64u ) + ((get_max_representable_in:bool -> int -> int) sign (n : int) : int= + (if (n =( 64 : int)) then (case sign of T => max_64 | F => max_64u ) else if (n=( 32 : int)) then (case sign of T => max_32 | F => max_32u ) else if (n=( 8 : int)) then max_8 else if (n=( 5 : int)) then max_5 @@ -56,8 +56,8 @@ val _ = Define ` val _ = Define ` - ((get_min_representable_in:'a -> int -> int) _ (n : int) : int= - (if n =( 64 : int) then min_64 + ((get_min_representable_in:'a -> int -> int) _ (n : int) : int= + (if n =( 64 : int) then min_64 else if n =( 32 : int) then min_32 else if n =( 8 : int) then min_8 else if n =( 5 : int) then min_5 @@ -65,25 +65,25 @@ val _ = Define ` (*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => - (Num.integer -> Num.integer -> Num.integer) -> bool -> 'a -> Num.integer -> 'a*) + (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) val _ = Define ` - ((arith_op_bv_int:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail_values_Bitvector_a op sign l r= - (let r' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l r'))`; + ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail_values_Bitvector_a op sign l r= + (let r' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l r'))`; (*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => - (Num.integer -> Num.integer -> Num.integer) -> bool -> Num.integer -> 'a -> 'a*) + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) val _ = Define ` - ((arith_op_int_bv:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail_values_Bitvector_a op sign l r= - (let l' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method r) l) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l' r))`; + ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail_values_Bitvector_a op sign l r= + (let l' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method r) l) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l' r))`; val _ = Define ` - ((arith_op_bv_bool:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a op sign l r= (arith_op_bv_int + ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a op sign l r= (arith_op_bv_int dict_Sail_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`; val _ = Define ` - ((arith_op_bv_bit:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool + ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool dict_Sail_values_Bitvector_a op sign l) (bool_of_bitU r)))`; @@ -161,10 +161,10 @@ val _ = Define ` )))`; -(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> Num.integer -> list Sail_values.bitU*) +(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*) val _ = Define ` - ((shift_op_bv:'a sail_values$Bitvector_class -> shift -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a op v n= - (let v = (dict_Sail_values_Bitvector_a.bits_of_method v) in + ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a op v n= + (let v = (dict_Sail_values_Bitvector_a.bits_of_method v) in if n =( 0 : int) then v else let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in (case op of @@ -184,23 +184,23 @@ val _ = Define ` val _ = Define ` - ((shiftl_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv dict_Sail_values_Bitvector_a LL_shift))`; (*"<<"*) val _ = Define ` - ((shiftr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv dict_Sail_values_Bitvector_a RR_shift))`; (*">>"*) val _ = Define ` - ((arith_shiftr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv dict_Sail_values_Bitvector_a RR_shift_arith))`; val _ = Define ` - ((rotl_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv dict_Sail_values_Bitvector_a LL_rot))`; (*"<<<"*) val _ = Define ` - ((rotr_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv + ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv dict_Sail_values_Bitvector_a LL_rot))`; (*">>>"*) @@ -221,17 +221,17 @@ val _ = Define ` val _ = Define ` - ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r= - (if r =( 0 : int) + ((arith_op_no0:(int -> int -> int) -> int -> int ->(int)option) (op : int -> int -> int) l r= + (if r =( 0 : int) then NONE else SOME (op l r)))`; (*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (Num.integer -> Num.integer -> Num.integer) -> bool -> Num.integer -> 'a -> 'a -> Maybe.maybe 'b*) + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*) val _ = Define ` - ((arith_op_bv_no0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= - (OPTION_BIND (int_of_bv + ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= + (OPTION_BIND (int_of_bv dict_Sail_values_Bitvector_a sign l) (\ l' . OPTION_BIND (int_of_bv dict_Sail_values_Bitvector_a sign r) (\ r' . @@ -240,15 +240,15 @@ val _ = Define ` val _ = Define ` - ((mod_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; val _ = Define ` - ((quot_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; val _ = Define ` - ((quots_bv:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 + ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot T(( 1 : int))))`; @@ -263,16 +263,16 @@ val _ = Define ` val _ = Define ` - ((arith_op_bv_int_no0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= - (arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r)))`; + ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= + (arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r)))`; val _ = Define ` - ((quot_bv_int:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 + ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; val _ = Define ` - ((mod_bv_int:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 + ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; @@ -287,81 +287,41 @@ val _ = Define ` val _ = Define ` - ((replicate_bits_bv:'a sail_values$Bitvector_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a v count1= (repeat ( + ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a v count1= (repeat ( dict_Sail_values_Bitvector_a.bits_of_method v) count1))`; val _ = Define ` - ((duplicate_bit_bv:'a sail_values$BitU_class -> 'a -> int ->(sail_values$bitU)list)dict_Sail_values_BitU_a bit len= (replicate_bits_bv + ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail_values_BitU_a bit len= (replicate_bits_bv (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len))`; (*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) val _ = Define ` - ((eq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ( + ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ( dict_Sail_values_Bitvector_a.bits_of_method l = dict_Sail_values_Bitvector_a.bits_of_method r))`; (*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) val _ = Define ` - ((neq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (eq_bv + ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (eq_bv dict_Sail_values_Bitvector_a l r)))`; -(*val ult_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) val _ = Define ` - ((ult_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (lexicographic_less (\ l r. (compare_bitU l r) = LT) (\ l r. (compare_bitU l r) <> GT) (REVERSE ( - dict_Sail_values_Bitvector_a.bits_of_method l)) (REVERSE (dict_Sail_values_Bitvector_a.bits_of_method r))))`; + ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= + (let hi = ((lo + len) -( 1 : int)) in + let bs = (bools_of_int (hi +( 1 : int)) n) in + dict_Sail_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`; -val _ = Define ` - ((ulteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv - dict_Sail_values_Bitvector_a l r) \/ (ult_bv dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((ugt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (ulteq_bv - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((ugteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv - dict_Sail_values_Bitvector_a l r) \/ (ugt_bv dict_Sail_values_Bitvector_a l r)))`; - - -(*val slt_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) -val _ = Define ` - ((slt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= - ((case (most_significant - dict_Sail_values_Bitvector_a l, most_significant dict_Sail_values_Bitvector_a r) of - (B0, B0) => ult_bv - dict_Sail_values_Bitvector_a l r - | (B0, B1) => F - | (B1, B0) => T - | (B1, B1) => - let l' = (add_one_bit_ignore_overflow ( - dict_Sail_values_Bitvector_a.bits_of_method l)) in - let r' = (add_one_bit_ignore_overflow ( - dict_Sail_values_Bitvector_a.bits_of_method r)) in - ugt_bv (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l' r' - | (BU, BU) => ult_bv - dict_Sail_values_Bitvector_a l r - | (BU, _) => T - | (_, BU) => F - )))`; +(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*) val _ = Define ` - ((slteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv - dict_Sail_values_Bitvector_a l r) \/ (slt_bv dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((sgt_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (slteq_bv - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((sgteq_bv:'a sail_values$Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ((eq_bv - dict_Sail_values_Bitvector_a l r) \/ (sgt_bv dict_Sail_values_Bitvector_a l r)))`; - - -(*val ucmp_mword : forall 'a. Size 'a => (Num.integer -> Num.integer -> bool) -> Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) + ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail_values_Bitvector_a len n lo v= + (let hi = ((lo + len) -( 1 : int)) in + let bs = (bits_of_int (hi +( 1 : int)) n) in + maybe_failwith (signed_of_bits (update_subrange_list F bs hi lo ( + dict_Sail_values_Bitvector_a.bits_of_method v)))))`; -(*val scmp_mword : forall 'a. Size 'a => (Num.integer -> Num.integer -> bool) -> Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml index 5d2978bb..48f4c8cb 100644 --- a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml @@ -17,148 +17,153 @@ val _ = new_theory "sail_operators_bitlists" (* Specialisation of operators to bit lists *) -(*val uint_maybe : list Sail_values.bitU -> Maybe.maybe Num.integer*) +(*val uint_maybe : list bitU -> maybe integer*) val _ = Define ` - ((uint_maybe0:(sail_values$bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`; + ((uint_maybe0:(bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`; val _ = Define ` - ((uint_fail0:'a sail_values$Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "uint" ( + ((uint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "uint" ( dict_Sail_values_Bitvector_a.unsigned_method v)))`; val _ = Define ` - ((uint_oracle0:(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS -(state$bools_of_bits_oracleS v) (\ bs . + ((uint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS + (state$bools_of_bits_oracleS v) (\ bs . state_monad$returnS (int_of_bools F bs))))`; val _ = Define ` - ((uint:(sail_values$bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`; + ((uint:(bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`; -(*val sint_maybe : list Sail_values.bitU -> Maybe.maybe Num.integer*) +(*val sint_maybe : list bitU -> maybe integer*) val _ = Define ` - ((sint_maybe0:(sail_values$bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`; + ((sint_maybe0:(bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`; val _ = Define ` - ((sint_fail0:'a sail_values$Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "sint" ( + ((sint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "sint" ( dict_Sail_values_Bitvector_a.signed_method v)))`; val _ = Define ` - ((sint_oracle0:(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS -(state$bools_of_bits_oracleS v) (\ bs . + ((sint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS + (state$bools_of_bits_oracleS v) (\ bs . state_monad$returnS (int_of_bools T bs))))`; val _ = Define ` - ((sint:(sail_values$bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`; + ((sint:(bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`; -(*val extz_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val extz_vec : integer -> list bitU -> list bitU*) val _ = Define ` - ((extz_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((extz_vec0:int ->(bitU)list ->(bitU)list)= (extz_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val exts_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val exts_vec : integer -> list bitU -> list bitU*) val _ = Define ` - ((exts_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((exts_vec0:int ->(bitU)list ->(bitU)list)= (exts_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val zero_extend : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val zero_extend : list bitU -> integer -> list bitU*) val _ = Define ` - ((zero_extend0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bits len= (extz_bits len bits))`; + ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len= (extz_bits len bits))`; -(*val sign_extend : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val sign_extend : list bitU -> integer -> list bitU*) val _ = Define ` - ((sign_extend0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bits len= (exts_bits len bits))`; + ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len= (exts_bits len bits))`; -(*val vector_truncate : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val zeros : integer -> list bitU*) val _ = Define ` - ((vector_truncate0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) bs len= (extz_bv + ((zeros0:int ->(bitU)list) len= (repeat [B0] len))`; + + +(*val vector_truncate : list bitU -> integer -> list bitU*) +val _ = Define ` + ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len= (extz_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) len bs))`; -(*val vec_of_bits_maybe : list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) -(*val vec_of_bits_fail : forall 'rv 'e. list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'e. list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val vec_of_bits_failwith : list Sail_values.bitU -> list Sail_values.bitU*) -(*val vec_of_bits : list Sail_values.bitU -> list Sail_values.bitU*) +(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) +(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_failwith : list bitU -> list bitU*) +(*val vec_of_bits : list bitU -> list bitU*) -(*val access_vec_inc : list Sail_values.bitU -> Num.integer -> Sail_values.bitU*) +(*val access_vec_inc : list bitU -> integer -> bitU*) val _ = Define ` - ((access_vec_inc0:(sail_values$bitU)list -> int -> sail_values$bitU)= + ((access_vec_inc0:(bitU)list -> int -> bitU)= (access_bv_inc (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val access_vec_dec : list Sail_values.bitU -> Num.integer -> Sail_values.bitU*) +(*val access_vec_dec : list bitU -> integer -> bitU*) val _ = Define ` - ((access_vec_dec0:(sail_values$bitU)list -> int -> sail_values$bitU)= + ((access_vec_dec0:(bitU)list -> int -> bitU)= (access_bv_dec (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val update_vec_inc : list Sail_values.bitU -> Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) val _ = Define ` - ((update_vec_inc0:(sail_values$bitU)list -> int -> sail_values$bitU ->(sail_values$bitU)list)= + ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)= (update_bv_inc (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((update_vec_inc_maybe0:(sail_values$bitU)list -> int -> sail_values$bitU ->((sail_values$bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`; + ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`; val _ = Define ` - ((update_vec_inc_fail0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; + ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; val _ = Define ` - ((update_vec_inc_oracle0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; + ((update_vec_inc_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; -(*val update_vec_dec : list Sail_values.bitU -> Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) val _ = Define ` - ((update_vec_dec0:(sail_values$bitU)list -> int -> sail_values$bitU ->(sail_values$bitU)list)= + ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)= (update_bv_dec (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((update_vec_dec_maybe0:(sail_values$bitU)list -> int -> sail_values$bitU ->((sail_values$bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`; + ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`; val _ = Define ` - ((update_vec_dec_fail0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; + ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; val _ = Define ` - ((update_vec_dec_oracle0:(sail_values$bitU)list -> int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; + ((update_vec_dec_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; -(*val subrange_vec_inc : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU*) +(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) val _ = Define ` - ((subrange_vec_inc0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list)= + ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)= (subrange_bv_inc (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val subrange_vec_dec : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU*) +(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) val _ = Define ` - ((subrange_vec_dec0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list)= + ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)= (subrange_bv_dec (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val update_subrange_vec_inc : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) val _ = Define ` - ((update_subrange_vec_inc0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= (update_subrange_bv_inc (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) @@ -166,9 +171,9 @@ val _ = Define ` instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val update_subrange_vec_dec : list Sail_values.bitU -> Num.integer -> Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) val _ = Define ` - ((update_subrange_vec_dec0:(sail_values$bitU)list -> int -> int ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= (update_subrange_bv_dec (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) @@ -176,9 +181,9 @@ val _ = Define ` instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val concat_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val concat_vec : list bitU -> list bitU -> list bitU*) val _ = Define ` - ((concat_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (concat_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) @@ -186,106 +191,106 @@ val _ = Define ` instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val cons_vec : Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val cons_vec : bitU -> list bitU -> list bitU*) val _ = Define ` - ((cons_vec0:sail_values$bitU ->(sail_values$bitU)list ->(sail_values$bitU)list)= + ((cons_vec0:bitU ->(bitU)list ->(bitU)list)= (cons_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((cons_vec_maybe0:sail_values$bitU ->(sail_values$bitU)list ->((sail_values$bitU)list)option) b v= (SOME (cons_vec0 b v)))`; + ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v= (SOME (cons_vec0 b v)))`; val _ = Define ` - ((cons_vec_fail0:sail_values$bitU ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; + ((cons_vec_fail0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; val _ = Define ` - ((cons_vec_oracle0:sail_values$bitU ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; + ((cons_vec_oracle0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; -(*val cast_unit_vec : Sail_values.bitU -> list Sail_values.bitU*) +(*val cast_unit_vec : bitU -> list bitU*) val _ = Define ` - ((cast_unit_vec0:sail_values$bitU ->(sail_values$bitU)list)= cast_unit_bv)`; + ((cast_unit_vec0:bitU ->(bitU)list)= cast_unit_bv)`; val _ = Define ` - ((cast_unit_vec_maybe0:sail_values$bitU ->((sail_values$bitU)list)option) b= (SOME (cast_unit_vec0 b)))`; + ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b= (SOME (cast_unit_vec0 b)))`; val _ = Define ` - ((cast_unit_vec_fail0:sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; + ((cast_unit_vec_fail0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; val _ = Define ` - ((cast_unit_vec_oracle0:sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; + ((cast_unit_vec_oracle0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; -(*val vec_of_bit : Num.integer -> Sail_values.bitU -> list Sail_values.bitU*) +(*val vec_of_bit : integer -> bitU -> list bitU*) val _ = Define ` - ((vec_of_bit0:int -> sail_values$bitU ->(sail_values$bitU)list)= bv_of_bit)`; + ((vec_of_bit0:int -> bitU ->(bitU)list)= bv_of_bit)`; val _ = Define ` - ((vec_of_bit_maybe0:int -> sail_values$bitU ->((sail_values$bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`; + ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`; val _ = Define ` - ((vec_of_bit_fail0:int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; + ((vec_of_bit_fail0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; val _ = Define ` - ((vec_of_bit_oracle0:int -> sail_values$bitU -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; + ((vec_of_bit_oracle0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; -(*val msb : list Sail_values.bitU -> Sail_values.bitU*) +(*val msb : list bitU -> bitU*) val _ = Define ` - ((msb0:(sail_values$bitU)list -> sail_values$bitU)= + ((msb0:(bitU)list -> bitU)= (most_significant (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val int_of_vec_maybe : bool -> list Sail_values.bitU -> Maybe.maybe Num.integer*) +(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) val _ = Define ` - ((int_of_vec_maybe0:bool ->(sail_values$bitU)list ->(int)option)= + ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)= (int_of_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((int_of_vec_fail0:bool ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`; + ((int_of_vec_fail0:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`; val _ = Define ` - ((int_of_vec_oracle:bool ->(sail_values$bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$bindS (state$bools_of_bits_oracleS v) (\ v . state_monad$returnS (int_of_bools sign v))))`; + ((int_of_vec_oracle:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$bindS (state$bools_of_bits_oracleS v) (\ v . state_monad$returnS (int_of_bools sign v))))`; val _ = Define ` - ((int_of_vec0:bool ->(sail_values$bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`; + ((int_of_vec0:bool ->(bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`; -(*val string_of_vec : list Sail_values.bitU -> string*) +(*val string_of_vec : list bitU -> string*) val _ = Define ` - ((string_of_vec0:(sail_values$bitU)list -> string)= + ((string_of_vec0:(bitU)list -> string)= (string_of_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val and_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val or_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val xor_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val not_vec : list Sail_values.bitU -> list Sail_values.bitU*) +(*val and_vec : list bitU -> list bitU -> list bitU*) +(*val or_vec : list bitU -> list bitU -> list bitU*) +(*val xor_vec : list bitU -> list bitU -> list bitU*) +(*val not_vec : list bitU -> list bitU*) val _ = Define ` - ((and_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list and_bit))`; + ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list and_bit))`; val _ = Define ` - ((or_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list or_bit))`; + ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list or_bit))`; val _ = Define ` - ((xor_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (binop_list xor_bit))`; + ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list xor_bit))`; val _ = Define ` - ((not_vec0:(sail_values$bitU)list ->(sail_values$bitU)list)= (MAP not_bit))`; + ((not_vec0:(bitU)list ->(bitU)list)= (MAP not_bit))`; (*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => - (Num.integer -> Num.integer -> Num.integer) -> bool -> 'a -> 'a -> list Sail_values.bitU*) + (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) val _ = Define ` - ((arith_op_double_bl:'a sail_values$Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(sail_values$bitU)list)dict_Sail_values_Bitvector_a op sign l r= - (let len =(( 2 : int) * + ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a op sign l r= + (let len =(( 2 : int) * dict_Sail_values_Bitvector_a.length_method l) in let l' = (if sign then exts_bv dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in @@ -294,198 +299,198 @@ val _ = Define ` MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`; -(*val add_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val adds_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val sub_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val subs_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val mult_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val mults_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val add_vec : list bitU -> list bitU -> list bitU*) +(*val adds_vec : list bitU -> list bitU -> list bitU*) +(*val sub_vec : list bitU -> list bitU -> list bitU*) +(*val subs_vec : list bitU -> list bitU -> list bitU*) +(*val mult_vec : list bitU -> list bitU -> list bitU*) +(*val mults_vec : list bitU -> list bitU -> list bitU*) val _ = Define ` - ((add_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; val _ = Define ` - ((adds_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; val _ = Define ` - ((sub_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; val _ = Define ` - ((subs_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; val _ = Define ` - ((mult_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (arith_op_double_bl + ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F))`; val _ = Define ` - ((mults_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list)= (arith_op_double_bl + ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T))`; -(*val add_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val adds_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val sub_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val subs_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val mult_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val mults_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val add_vec_int : list bitU -> integer -> list bitU*) +(*val adds_vec_int : list bitU -> integer -> list bitU*) +(*val sub_vec_int : list bitU -> integer -> list bitU*) +(*val subs_vec_int : list bitU -> integer -> list bitU*) +(*val mult_vec_int : list bitU -> integer -> list bitU*) +(*val mults_vec_int : list bitU -> integer -> list bitU*) val _ = Define ` - ((add_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + ((add_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; val _ = Define ` - ((adds_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + ((adds_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; val _ = Define ` - ((sub_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + ((sub_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; val _ = Define ` - ((subs_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_bv_int + ((subs_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; val _ = Define ` - ((mult_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_double_bl + ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; val _ = Define ` - ((mults_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (arith_op_double_bl + ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; -(*val add_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val adds_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val sub_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val subs_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val mult_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val mults_int_vec : Num.integer -> list Sail_values.bitU -> list Sail_values.bitU*) +(*val add_int_vec : integer -> list bitU -> list bitU*) +(*val adds_int_vec : integer -> list bitU -> list bitU*) +(*val sub_int_vec : integer -> list bitU -> list bitU*) +(*val subs_int_vec : integer -> list bitU -> list bitU*) +(*val mult_int_vec : integer -> list bitU -> list bitU*) +(*val mults_int_vec : integer -> list bitU -> list bitU*) val _ = Define ` - ((add_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + ((add_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; val _ = Define ` - ((adds_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + ((adds_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; val _ = Define ` - ((sub_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + ((sub_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; val _ = Define ` - ((subs_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_int_bv + ((subs_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; val _ = Define ` - ((mult_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_double_bl + ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; val _ = Define ` - ((mults_int_vec0:int ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (arith_op_double_bl + ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; -(*val add_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) -(*val adds_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) -(*val sub_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) -(*val subs_vec_bit : list Sail_values.bitU -> Sail_values.bitU -> list Sail_values.bitU*) +(*val add_vec_bit : list bitU -> bitU -> list bitU*) +(*val adds_vec_bit : list bitU -> bitU -> list bitU*) +(*val sub_vec_bit : list bitU -> bitU -> list bitU*) +(*val subs_vec_bit : list bitU -> bitU -> list bitU*) val _ = Define ` - ((add_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool dict_Sail_values_Bitvector_a (+) F l r))`; val _ = Define ` - ((add_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit dict_Sail_values_Bitvector_a (+) F l r))`; val _ = Define ` - ((add_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 + ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 dict_Sail_values_Bitvector_a l r)))`; val _ = Define ` - ((add_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool0 + ((add_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool0 dict_Sail_values_Bitvector_a l r))))`; val _ = Define ` - ((add_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (add_vec_bit_maybe0 + ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (add_vec_bit_maybe0 (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((adds_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool dict_Sail_values_Bitvector_a (+) T l r))`; val _ = Define ` - ((adds_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit dict_Sail_values_Bitvector_a (+) T l r))`; val _ = Define ` - ((adds_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 + ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 dict_Sail_values_Bitvector_a l r)))`; val _ = Define ` - ((adds_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool0 + ((adds_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool0 dict_Sail_values_Bitvector_a l r))))`; val _ = Define ` - ((adds_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (adds_vec_bit_maybe0 + ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (adds_vec_bit_maybe0 (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((sub_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool dict_Sail_values_Bitvector_a (-) F l r))`; val _ = Define ` - ((sub_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit dict_Sail_values_Bitvector_a (-) F l r))`; val _ = Define ` - ((sub_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 + ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 dict_Sail_values_Bitvector_a l r)))`; val _ = Define ` - ((sub_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool0 + ((sub_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool0 dict_Sail_values_Bitvector_a l r))))`; val _ = Define ` - ((sub_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (sub_vec_bit_maybe0 + ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (sub_vec_bit_maybe0 (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((subs_vec_bool0:'a sail_values$Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool + ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool dict_Sail_values_Bitvector_a (-) T l r))`; val _ = Define ` - ((subs_vec_bit_maybe0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit + ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit dict_Sail_values_Bitvector_a (-) T l r))`; val _ = Define ` - ((subs_vec_bit_fail0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 + ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 dict_Sail_values_Bitvector_a l r)))`; val _ = Define ` - ((subs_vec_bit_oracle0:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool0 + ((subs_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool0 dict_Sail_values_Bitvector_a l r))))`; val _ = Define ` - ((subs_vec_bit0:(sail_values$bitU)list -> sail_values$bitU ->(sail_values$bitU)list) l r= (option_CASE (subs_vec_bit_maybe0 + ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (subs_vec_bit_maybe0 (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; @@ -512,279 +517,251 @@ let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed let sub_overflow_vec_bit = sub_overflow_bv_bit let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) -(*val shiftl : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val shiftr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val arith_shiftr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val rotl : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val rotr : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val shiftl : list bitU -> integer -> list bitU*) +(*val shiftr : list bitU -> integer -> list bitU*) +(*val arith_shiftr : list bitU -> integer -> list bitU*) +(*val rotl : list bitU -> integer -> list bitU*) +(*val rotr : list bitU -> integer -> list bitU*) val _ = Define ` - ((shiftl0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((shiftl0:(bitU)list -> int ->(bitU)list)= (shiftl_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((shiftr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((shiftr0:(bitU)list -> int ->(bitU)list)= (shiftr_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((arith_shiftr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((arith_shiftr0:(bitU)list -> int ->(bitU)list)= (arith_shiftr_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((rotl0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((rotl0:(bitU)list -> int ->(bitU)list)= (rotl_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((rotr0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((rotr0:(bitU)list -> int ->(bitU)list)= (rotr_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val mod_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val mod_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) -(*val mod_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val mod_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val mod_vec : list bitU -> list bitU -> list bitU*) +(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) val _ = Define ` - ((mod_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (mod_bv + ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (mod_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((mod_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (mod_bv + ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (mod_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; val _ = Define ` - ((mod_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv + ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; val _ = Define ` - ((mod_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + ((mod_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec0 l r)))`; -(*val quot_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val quot_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) -(*val quot_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val quot_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quot_vec : list bitU -> list bitU -> list bitU*) +(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) val _ = Define ` - ((quot_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (quot_bv + ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quot_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((quot_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (quot_bv + ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quot_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; val _ = Define ` - ((quot_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv + ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; val _ = Define ` - ((quot_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + ((quot_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec0 l r)))`; -(*val quots_vec : list Sail_values.bitU -> list Sail_values.bitU -> list Sail_values.bitU*) -(*val quots_vec_maybe : list Sail_values.bitU -> list Sail_values.bitU -> Maybe.maybe (list Sail_values.bitU)*) -(*val quots_vec_fail : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val quots_vec_oracle : forall 'rv 'e. list Sail_values.bitU -> list Sail_values.bitU -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quots_vec : list bitU -> list bitU -> list bitU*) +(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) val _ = Define ` - ((quots_vec0:(sail_values$bitU)list ->(sail_values$bitU)list ->(sail_values$bitU)list) l r= (option_CASE (quots_bv + ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quots_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((quots_vec_maybe0:(sail_values$bitU)list ->(sail_values$bitU)list ->((sail_values$bitU)list)option) l r= (quots_bv + ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quots_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; val _ = Define ` - ((quots_vec_fail0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv + ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; val _ = Define ` - ((quots_vec_oracle0:(sail_values$bitU)list ->(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + ((quots_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec0 l r)))`; -(*val mod_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val mod_vec_int_maybe : list Sail_values.bitU -> Num.integer -> Maybe.maybe (list Sail_values.bitU)*) -(*val mod_vec_int_fail : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val mod_vec_int : list bitU -> integer -> list bitU*) +(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) val _ = Define ` - ((mod_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (option_CASE (mod_bv_int + ((mod_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (mod_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((mod_vec_int_maybe0:(sail_values$bitU)list -> int ->((sail_values$bitU)list)option) l r= (mod_bv_int + ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (mod_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; val _ = Define ` - ((mod_vec_int_fail0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int + ((mod_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; val _ = Define ` - ((mod_vec_int_oracle0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + ((mod_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int0 l r)))`; -(*val quot_vec_int : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) -(*val quot_vec_int_maybe : list Sail_values.bitU -> Num.integer -> Maybe.maybe (list Sail_values.bitU)*) -(*val quot_vec_int_fail : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'e. list Sail_values.bitU -> Num.integer -> Prompt_monad.monad 'rv (list Sail_values.bitU) 'e*) +(*val quot_vec_int : list bitU -> integer -> list bitU*) +(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) val _ = Define ` - ((quot_vec_int0:(sail_values$bitU)list -> int ->(sail_values$bitU)list) l r= (option_CASE (quot_bv_int + ((quot_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (quot_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; val _ = Define ` - ((quot_vec_int_maybe0:(sail_values$bitU)list -> int ->((sail_values$bitU)list)option) l r= (quot_bv_int + ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (quot_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; val _ = Define ` - ((quot_vec_int_fail0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int + ((quot_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; val _ = Define ` - ((quot_vec_int_oracle0:(sail_values$bitU)list -> int -> 'rv state_monad$sequential_state ->((((sail_values$bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS + ((quot_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int0 l r)))`; -(*val replicate_bits : list Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val replicate_bits : list bitU -> integer -> list bitU*) val _ = Define ` - ((replicate_bits0:(sail_values$bitU)list -> int ->(sail_values$bitU)list)= + ((replicate_bits0:(bitU)list -> int ->(bitU)list)= (replicate_bits_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -(*val duplicate : Sail_values.bitU -> Num.integer -> list Sail_values.bitU*) +(*val duplicate : bitU -> integer -> list bitU*) val _ = Define ` - ((duplicate0:sail_values$bitU -> int ->(sail_values$bitU)list)= + ((duplicate0:bitU -> int ->(bitU)list)= (duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict))`; val _ = Define ` - ((duplicate_maybe0:sail_values$bitU -> int ->((sail_values$bitU)list)option) b n= (SOME (duplicate0 b n)))`; + ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n= (SOME (duplicate0 b n)))`; val _ = Define ` - ((duplicate_fail0:sail_values$bitU -> int -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$returnS (duplicate0 b n)))`; + ((duplicate_fail0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$returnS (duplicate0 b n)))`; val _ = Define ` - ((duplicate_oracle0:sail_values$bitU -> int -> 'a state_monad$sequential_state ->((((sail_values$bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$bindS -(state$bool_of_bitU_oracleS b) (\ b . + ((duplicate_oracle0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$bindS + (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`; -(*val reverse_endianness : list Sail_values.bitU -> list Sail_values.bitU*) +(*val reverse_endianness : list bitU -> list bitU*) val _ = Define ` - ((reverse_endianness0:(sail_values$bitU)list ->(sail_values$bitU)list) v= (reverse_endianness_list v))`; + ((reverse_endianness0:(bitU)list ->(bitU)list) v= (reverse_endianness_list v))`; -(*val eq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val neq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val ult_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val slt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val ugt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val sgt_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val ulteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val slteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val ugteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) -(*val sgteq_vec : list Sail_values.bitU -> list Sail_values.bitU -> bool*) +(*val get_slice_int : integer -> integer -> integer -> list bitU*) val _ = Define ` - ((eq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (eq_bv + ((get_slice_int0:int -> int -> int ->(bitU)list)= + (get_slice_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -val _ = Define ` - ((neq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (neq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; +(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) val _ = Define ` - ((ult_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (ult_bv + ((set_slice_int0:int -> int -> int ->(bitU)list -> int)= + (set_slice_int_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; -val _ = Define ` - ((slt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (slt_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; +(*val slice : list bitU -> integer -> integer -> list bitU*) val _ = Define ` - ((ugt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (ugt_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len= + (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`; -val _ = Define ` - ((sgt_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (sgt_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; +(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*) val _ = Define ` - ((ulteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (ulteq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; + ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v= + (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`; -val _ = Define ` - ((slteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (slteq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; +(*val eq_vec : list bitU -> list bitU -> bool*) +(*val neq_vec : list bitU -> list bitU -> bool*) val _ = Define ` - ((ugteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (ugteq_bv + ((eq_vec:(bitU)list ->(bitU)list -> bool)= + (eq_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; val _ = Define ` - ((sgteq_vec:(sail_values$bitU)list ->(sail_values$bitU)list -> bool)= - (sgteq_bv + ((neq_vec:(bitU)list ->(bitU)list -> bool)= + (neq_bv (instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict)))`; diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml index bd0a68ef..a35707f0 100644 --- a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml @@ -33,188 +33,193 @@ val _ = Define ` ((sint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (integer_word$w2i v)))`; -(*val vec_of_bits_maybe : forall 'a. Size 'a => list Sail_values.bitU -> Maybe.maybe (Machine_word.mword 'a)*) -(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list Sail_values.bitU -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list Sail_values.bitU -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val vec_of_bits_failwith : forall 'a. Size 'a => list Sail_values.bitU -> Machine_word.mword 'a*) -(*val vec_of_bits : forall 'a. Size 'a => list Sail_values.bitU -> Machine_word.mword 'a*) +(*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*) +(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*) +(*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*) val _ = Define ` - ((vec_of_bits_maybe:(sail_values$bitU)list ->('a words$word)option) bits= (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`; + ((vec_of_bits_maybe:(bitU)list ->('a words$word)option) bits= (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`; val _ = Define ` - ((vec_of_bits_fail:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_failS + ((vec_of_bits_fail:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_failS instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` - ((vec_of_bits_oracle:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_oracleS + ((vec_of_bits_oracle:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_oracleS instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` - ((vec_of_bits_failwith:(sail_values$bitU)list -> 'a words$word) bits= (of_bits_failwith + ((vec_of_bits_failwith:(bitU)list -> 'a words$word) bits= (of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` - ((vec_of_bits:(sail_values$bitU)list -> 'a words$word) bits= (of_bits_failwith + ((vec_of_bits:(bitU)list -> 'a words$word) bits= (of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; -(*val access_vec_inc : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Sail_values.bitU*) +(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) val _ = Define ` - ((access_vec_inc:'a words$word -> int -> sail_values$bitU)= + ((access_vec_inc:'a words$word -> int -> bitU)= (access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict))`; -(*val access_vec_dec : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Sail_values.bitU*) +(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) val _ = Define ` - ((access_vec_dec:'a words$word -> int -> sail_values$bitU)= + ((access_vec_dec:'a words$word -> int -> bitU)= (access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict))`; val _ = Define ` - ((update_vec_dec_maybe:'a words$word -> int -> sail_values$bitU ->('a words$word)option) w i b= (update_mword_dec w i b))`; + ((update_vec_dec_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_dec w i b))`; val _ = Define ` - ((update_vec_dec_fail:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS -(state$bool_of_bitU_fail b) (\ b . + ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS + (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (update_mword_bool_dec w i b))))`; val _ = Define ` - ((update_vec_dec_oracle:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS -(state$bool_of_bitU_oracleS b) (\ b . + ((update_vec_dec_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS + (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (update_mword_bool_dec w i b))))`; val _ = Define ` - ((update_vec_dec:'a words$word -> int -> sail_values$bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_dec_maybe w i b)))`; + ((update_vec_dec:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_dec_maybe w i b)))`; val _ = Define ` - ((update_vec_inc_maybe:'a words$word -> int -> sail_values$bitU ->('a words$word)option) w i b= (update_mword_inc w i b))`; + ((update_vec_inc_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_inc w i b))`; val _ = Define ` - ((update_vec_inc_fail:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS -(state$bool_of_bitU_fail b) (\ b . + ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS + (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (update_mword_bool_inc w i b))))`; val _ = Define ` - ((update_vec_inc_oracle:'a words$word -> int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS -(state$bool_of_bitU_oracleS b) (\ b . + ((update_vec_inc_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS + (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (update_mword_bool_inc w i b))))`; val _ = Define ` - ((update_vec_inc:'a words$word -> int -> sail_values$bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_inc_maybe w i b)))`; + ((update_vec_inc:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_inc_maybe w i b)))`; -(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) val _ = Define ` ((subrange_vec_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int i) (nat_of_int j) w))`; -(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) val _ = Define ` ((subrange_vec_inc:'a words$word -> int -> int -> 'b words$word) w i j= (subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j)))`; -(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) val _ = Define ` ((update_subrange_vec_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int i) (nat_of_int j) w' w))`; -(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) val _ = Define ` ((update_subrange_vec_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (update_subrange_vec_dec w ((int_of_num (words$word_len w) -( 1 : int)) - i) ((int_of_num (words$word_len w) -( 1 : int)) - j) w'))`; -(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) val _ = Define ` ((extz_vec:int -> 'a words$word -> 'b words$word) _ w= (words$w2w w))`; -(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) val _ = Define ` ((exts_vec:int -> 'a words$word -> 'b words$word) _ w= (words$sw2sw w))`; -(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((zero_extend:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`; -(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((sign_extend:'a words$word -> int -> 'b words$word) w _= (words$sw2sw w))`; -(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val zeros : forall 'a. Size 'a => integer -> mword 'a*) +val _ = Define ` + ((zeros:int -> 'a words$word) _= (words$n2w(( 0:num))))`; + + +(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((vector_truncate:'a words$word -> int -> 'b words$word) w _= (words$w2w w))`; -(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => Machine_word.mword 'a -> Machine_word.mword 'b -> Machine_word.mword 'c*) +(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*) val _ = Define ` ((concat_vec:'a words$word -> 'b words$word -> 'c words$word)= words$word_concat)`; -(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*) val _ = Define ` ((cons_vec_bool:bool -> 'a words$word -> 'b words$word) b w= (bitstring$v2w (b :: bitstring$w2v w)))`; val _ = Define ` - ((cons_vec_maybe:sail_values$bitU -> 'c words$word ->('b words$word)option) b w= (OPTION_MAP (\ b . cons_vec_bool b w) (bool_of_bitU b)))`; + ((cons_vec_maybe:bitU -> 'c words$word ->('b words$word)option) b w= (OPTION_MAP (\ b . cons_vec_bool b w) (bool_of_bitU b)))`; val _ = Define ` - ((cons_vec_fail:sail_values$bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + ((cons_vec_fail:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; val _ = Define ` - ((cons_vec_oracle:sail_values$bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + ((cons_vec_oracle:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; val _ = Define ` - ((cons_vec:sail_values$bitU -> 'a words$word -> 'b words$word) b w= (maybe_failwith (cons_vec_maybe b w)))`; + ((cons_vec:bitU -> 'a words$word -> 'b words$word) b w= (maybe_failwith (cons_vec_maybe b w)))`; -(*val vec_of_bool : forall 'a. Size 'a => Num.integer -> bool -> Machine_word.mword 'a*) +(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*) val _ = Define ` ((vec_of_bool:int -> bool -> 'a words$word) _ b= (bitstring$v2w [b]))`; val _ = Define ` - ((vec_of_bit_maybe:int -> sail_values$bitU ->('a words$word)option) len b= (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`; + ((vec_of_bit_maybe:int -> bitU ->('a words$word)option) len b= (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`; val _ = Define ` - ((vec_of_bit_fail:int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + ((vec_of_bit_fail:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (vec_of_bool len b))))`; val _ = Define ` - ((vec_of_bit_oracle:int -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + ((vec_of_bit_oracle:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (vec_of_bool len b))))`; val _ = Define ` - ((vec_of_bit:int -> sail_values$bitU -> 'a words$word) len b= (maybe_failwith (vec_of_bit_maybe len b)))`; + ((vec_of_bit:int -> bitU -> 'a words$word) len b= (maybe_failwith (vec_of_bit_maybe len b)))`; -(*val cast_bool_vec : bool -> Machine_word.mword Machine_word.ty1*) +(*val cast_bool_vec : bool -> mword ty1*) val _ = Define ` ((cast_bool_vec:bool ->(1)words$word) b= (vec_of_bool(( 1 : int)) b))`; val _ = Define ` - ((cast_unit_vec_maybe:sail_values$bitU ->('a words$word)option) b= (vec_of_bit_maybe(( 1 : int)) b))`; + ((cast_unit_vec_maybe:bitU ->('a words$word)option) b= (vec_of_bit_maybe(( 1 : int)) b))`; val _ = Define ` - ((cast_unit_vec_fail:sail_values$bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + ((cast_unit_vec_fail:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cast_bool_vec b))))`; val _ = Define ` - ((cast_unit_vec_oracle:sail_values$bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + ((cast_unit_vec_oracle:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cast_bool_vec b))))`; val _ = Define ` - ((cast_unit_vec:sail_values$bitU -> 'a words$word) b= (maybe_failwith (cast_unit_vec_maybe b)))`; + ((cast_unit_vec:bitU -> 'a words$word) b= (maybe_failwith (cast_unit_vec_maybe b)))`; -(*val msb : forall 'a. Size 'a => Machine_word.mword 'a -> Sail_values.bitU*) +(*val msb : forall 'a. Size 'a => mword 'a -> bitU*) val _ = Define ` - ((msb:'a words$word -> sail_values$bitU)= + ((msb:'a words$word -> bitU)= (most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict))`; -(*val int_of_vec : forall 'a. Size 'a => bool -> Machine_word.mword 'a -> Num.integer*) +(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*) val _ = Define ` - ((int_of_vec:bool -> 'a words$word -> int) sign w= - (if sign + ((int_of_vec:bool -> 'a words$word -> int) sign w= + (if sign then integer_word$w2i w else lem$w2ui w))`; @@ -225,16 +230,16 @@ val _ = Define ` ((int_of_vec_fail:bool -> 'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) sign w= (state_monad$returnS (int_of_vec sign w)))`; -(*val string_of_vec : forall 'a. Size 'a => Machine_word.mword 'a -> string*) +(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) val _ = Define ` ((string_of_vec:'a words$word -> string)= (string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; -(*val and_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val or_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val xor_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val not_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*) val _ = Define ` ((and_vec:'a words$word -> 'a words$word -> 'a words$word)= words$word_and)`; @@ -248,12 +253,12 @@ val _ = Define ` ((not_vec:'a words$word -> 'a words$word)= words$word_1comp)`; -(*val add_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val adds_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val sub_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val subs_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'b*) -(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val adds_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val subs_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) +(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) val _ = Define ` ((add_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (integer_word$i2w ((int_of_mword F l) + (int_of_mword F r))))`; @@ -273,12 +278,12 @@ val _ = Define ` ((mults_vec:'a words$word -> 'a words$word -> 'b words$word) l r= (integer_word$i2w ((int_of_mword T (words$sw2sw l : 'b words$word)) * (int_of_mword T (words$sw2sw r : 'b words$word)))))`; -(*val add_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val adds_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val sub_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val subs_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) -(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val adds_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val subs_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((add_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; @@ -304,12 +309,12 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T (words$sw2sw l : 'b words$word) r))`; -(*val add_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val adds_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val sub_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val subs_int_vec : forall 'a. Size 'a => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) -(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => Num.integer -> Machine_word.mword 'a -> Machine_word.mword 'b*) +(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val adds_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val subs_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) val _ = Define ` ((add_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; @@ -335,26 +340,26 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T l (words$sw2sw r : 'b words$word)))`; -(*val add_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) -(*val adds_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) -(*val sub_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) -(*val subs_vec_bool : forall 'a. Size 'a => Machine_word.mword 'a -> bool -> Machine_word.mword 'a*) +(*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val sub_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) val _ = Define ` ((add_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; val _ = Define ` - ((add_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`; + ((add_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((add_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + ((add_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (add_vec_bool l r))))`; val _ = Define ` - ((add_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + ((add_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool l r))))`; val _ = Define ` - ((add_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (add_vec_bit_maybe l r)))`; + ((add_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (add_vec_bit_maybe l r)))`; val _ = Define ` @@ -362,16 +367,16 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; val _ = Define ` - ((adds_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`; + ((adds_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((adds_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + ((adds_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; val _ = Define ` - ((adds_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + ((adds_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; val _ = Define ` - ((adds_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (adds_vec_bit_maybe l r)))`; + ((adds_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (adds_vec_bit_maybe l r)))`; val _ = Define ` @@ -379,16 +384,16 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; val _ = Define ` - ((sub_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`; + ((sub_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((sub_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + ((sub_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; val _ = Define ` - ((sub_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + ((sub_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; val _ = Define ` - ((sub_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (sub_vec_bit_maybe l r)))`; + ((sub_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (sub_vec_bit_maybe l r)))`; val _ = Define ` @@ -396,16 +401,16 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; val _ = Define ` - ((subs_vec_bit_maybe:'a words$word -> sail_values$bitU ->('a words$word)option) l r= (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`; + ((subs_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((subs_vec_bit_fail:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + ((subs_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; val _ = Define ` - ((subs_vec_bit_oracle:'a words$word -> sail_values$bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + ((subs_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; val _ = Define ` - ((subs_vec_bit:'a words$word -> sail_values$bitU -> 'a words$word) l r= (maybe_failwith (subs_vec_bit_maybe l r)))`; + ((subs_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (subs_vec_bit_maybe l r)))`; (* TODO @@ -435,11 +440,11 @@ let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed let sub_overflow_vec_bit = sub_overflow_bv_bit let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) -(*val shiftl : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val shiftr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val arith_shiftr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val rotl : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val rotr : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) +(*val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) val _ = Define ` ((shiftl:'a words$word -> int -> 'a words$word)= shiftl_mword)`; @@ -456,10 +461,10 @@ val _ = Define ` ((rotr:'a words$word -> int -> 'a words$word)= rotr_mword)`; -(*val mod_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val mod_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) -(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((mod_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (mod_mword l r))`; @@ -472,17 +477,17 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((mod_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + ((mod_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of SOME w => state_monad$returnS w | NONE => state$mword_oracleS () )))`; -(*val quot_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val quot_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) -(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quot_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quot_mword l r))`; @@ -495,17 +500,17 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quot_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + ((quot_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of SOME w => state_monad$returnS w | NONE => state$mword_oracleS () )))`; -(*val quots_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Machine_word.mword 'a*) -(*val quots_vec_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Maybe.maybe (Machine_word.mword 'a)*) -(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quots_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quots_mword l r))`; @@ -518,17 +523,17 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quots_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + ((quots_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of SOME w => state_monad$returnS w | NONE => state$mword_oracleS () )))`; -(*val mod_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val mod_vec_int_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Maybe.maybe (Machine_word.mword 'a)*) -(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((mod_vec_int:'a words$word -> int -> 'a words$word) l r= (mod_mword_int l r))`; @@ -541,17 +546,18 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((mod_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + ((mod_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of SOME w => state_monad$returnS w | NONE => state$mword_oracleS () )))`; -(*val quot_vec_int : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'a*) -(*val quot_vec_int_maybe : forall 'a. Size 'a => Machine_word.mword 'a -> Num.integer -> Maybe.maybe (Machine_word.mword 'a)*) -(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => Machine_word.mword 'a -> Num.integer -> Prompt_monad.monad 'rv (Machine_word.mword 'a) 'e*) +(*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quot_vec_int:'a words$word -> int -> 'a words$word) l r= (quot_mword_int l r))`; @@ -564,49 +570,66 @@ val _ = Define ` instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quot_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (quot_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + ((quot_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((case (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of SOME w => state_monad$returnS w | NONE => state$mword_oracleS () )))`; -(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => Machine_word.mword 'a -> Num.integer -> Machine_word.mword 'b*) +(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((replicate_bits:'a words$word -> int -> 'b words$word) v count1= (bitstring$v2w (repeat (bitstring$w2v v) count1)))`; -(*val duplicate_bool : forall 'a. Size 'a => bool -> Num.integer -> Machine_word.mword 'a*) +(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*) val _ = Define ` ((duplicate_bool:bool -> int -> 'a words$word) b n= (bitstring$v2w (repeat [b] n)))`; val _ = Define ` - ((duplicate_maybe:sail_values$bitU -> int ->('a words$word)option) b n= (OPTION_MAP (\ b . duplicate_bool b n) (bool_of_bitU b)))`; + ((duplicate_maybe:bitU -> int ->('a words$word)option) b n= (OPTION_MAP (\ b . duplicate_bool b n) (bool_of_bitU b)))`; val _ = Define ` - ((duplicate_fail:sail_values$bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + ((duplicate_fail:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (duplicate_bool b n))))`; val _ = Define ` - ((duplicate_oracle:sail_values$bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + ((duplicate_oracle:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (duplicate_bool b n))))`; val _ = Define ` - ((duplicate:sail_values$bitU -> int -> 'a words$word) b n= (maybe_failwith (duplicate_maybe b n)))`; + ((duplicate:bitU -> int -> 'a words$word) b n= (maybe_failwith (duplicate_maybe b n)))`; -(*val reverse_endianness : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a*) +(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*) val _ = Define ` ((reverse_endianness:'a words$word -> 'a words$word) v= (bitstring$v2w (reverse_endianness_list (bitstring$w2v v))))`; -(*val eq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val neq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val ult_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val slt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val ugt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val sgt_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val ulteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val slteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val ugteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) -(*val sgteq_vec : forall 'a. Size 'a => Machine_word.mword 'a -> Machine_word.mword 'a -> bool*) +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) +val _ = Define ` + ((get_slice_int:int -> int -> int -> 'a words$word)= + (get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) +val _ = Define ` + ((set_slice_int:int -> int -> int -> 'a words$word -> int)= + (set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + + +(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +val _ = Define ` + ((slice:'a words$word -> int -> int -> 'b words$word) v lo len= + (subrange_vec_dec v ((lo + len) -( 1 : int)) lo))`; + + +(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*) +val _ = Define ` + ((set_slice:int -> int -> 'a words$word -> int -> 'b words$word -> 'a words$word) (out_len:ii) (slice_len:ii) out (n:ii) v= + (update_subrange_vec_dec out ((n + slice_len) -( 1 : int)) n v))`; + + +(*val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) +(*val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml new file mode 100644 index 00000000..af3f56c5 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml @@ -0,0 +1,132 @@ +(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory; +open intLib; + +val _ = numLib.prefer_num(); + + + +open lemLib; +(* val _ = lemLib.run_interactive := true; *) +val _ = new_theory "sail_valuesAuxiliary" + + +(****************************************************) +(* *) +(* Termination Proofs *) +(* *) +(****************************************************) + +(* val gst = Defn.tgoal_no_defn (shr_int_def, shr_int_ind) *) +val (shr_int_rw, shr_int_ind_rw) = + Defn.tprove_no_defn ((shr_int_def, shr_int_ind), + WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC + ) +val shr_int_rw = save_thm ("shr_int_rw", shr_int_rw); +val shr_int_ind_rw = save_thm ("shr_int_ind_rw", shr_int_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (shl_int_def, shl_int_ind) *) +val (shl_int_rw, shl_int_ind_rw) = + Defn.tprove_no_defn ((shl_int_def, shl_int_ind), + WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC + ) +val shl_int_rw = save_thm ("shl_int_rw", shl_int_rw); +val shl_int_ind_rw = save_thm ("shl_int_ind_rw", shl_int_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (repeat_def, repeat_ind) *) +val (repeat_rw, repeat_ind_rw) = + Defn.tprove_no_defn ((repeat_def, repeat_ind), + WF_REL_TAC`measure (Num o SND)` \\ COOPER_TAC + ) +val repeat_rw = save_thm ("repeat_rw", repeat_rw); +val repeat_ind_rw = save_thm ("repeat_ind_rw", repeat_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (bools_of_nat_aux_def, bools_of_nat_aux_ind) *) +val (bools_of_nat_aux_rw, bools_of_nat_aux_ind_rw) = + Defn.tprove_no_defn ((bools_of_nat_aux_def, bools_of_nat_aux_ind), + WF_REL_TAC`measure (Num o FST)` \\ COOPER_TAC + ) +val bools_of_nat_aux_rw = save_thm ("bools_of_nat_aux_rw", bools_of_nat_aux_rw); +val bools_of_nat_aux_ind_rw = save_thm ("bools_of_nat_aux_ind_rw", bools_of_nat_aux_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (pad_list_def, pad_list_ind) *) +val (pad_list_rw, pad_list_ind_rw) = + Defn.tprove_no_defn ((pad_list_def, pad_list_ind), + WF_REL_TAC`measure (Num o SND o SND)` \\ COOPER_TAC + ) +val pad_list_rw = save_thm ("pad_list_rw", pad_list_rw); +val pad_list_ind_rw = save_thm ("pad_list_ind_rw", pad_list_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (reverse_endianness_list_def, reverse_endianness_list_ind) *) +val (reverse_endianness_list_rw, reverse_endianness_list_ind_rw) = + Defn.tprove_no_defn ((reverse_endianness_list_def, reverse_endianness_list_ind), + WF_REL_TAC`measure LENGTH` \\ rw[drop_list_def,nat_of_int_def] + ) +val reverse_endianness_list_rw = save_thm ("reverse_endianness_list_rw", reverse_endianness_list_rw); +val reverse_endianness_list_ind_rw = save_thm ("reverse_endianness_list_ind_rw", reverse_endianness_list_ind_rw); + + +(* val gst = Defn.tgoal_no_defn (index_list_def, index_list_ind) *) +val (index_list_rw, index_list_ind_rw) = + Defn.tprove_no_defn ((index_list_def, index_list_ind), + WF_REL_TAC`measure (λ(x,y,z). Num(1+(if z > 0 then int_max (-1) (y - x) else int_max (-1) (x - y))))` + \\ rw[integerTheory.INT_MAX] + \\ intLib.COOPER_TAC + ) +val index_list_rw = save_thm ("index_list_rw", index_list_rw); +val index_list_ind_rw = save_thm ("index_list_ind_rw", index_list_ind_rw); + + +(* +(* val gst = Defn.tgoal_no_defn (while_def, while_ind) *) +val (while_rw, while_ind_rw) = + Defn.tprove_no_defn ((while_def, while_ind), + cheat (* the termination proof *) + ) +val while_rw = save_thm ("while_rw", while_rw); +val while_ind_rw = save_thm ("while_ind_rw", while_ind_rw); +*) + + +(* +(* val gst = Defn.tgoal_no_defn (until_def, until_ind) *) +val (until_rw, until_ind_rw) = + Defn.tprove_no_defn ((until_def, until_ind), + cheat (* the termination proof *) + ) +val until_rw = save_thm ("until_rw", until_rw); +val until_ind_rw = save_thm ("until_ind_rw", until_ind_rw); +*) + + +(****************************************************) +(* *) +(* Lemmata *) +(* *) +(****************************************************) + +val just_list_spec = store_thm("just_list_spec", +``((! xs. (just_list xs = NONE) <=> MEM NONE xs) /\ + (! xs es. (just_list xs = SOME es) <=> (xs = MAP SOME es)))``, + (* Theorem: just_list_spec*) + conj_tac + \\ ho_match_mp_tac just_list_ind + \\ Cases \\ rw[] + \\ rw[Once just_list_def] + >- ( CASE_TAC \\ fs[] \\ CASE_TAC ) + >- PROVE_TAC[] + \\ Cases_on`es` \\ fs[] + \\ CASE_TAC \\ fs[] + \\ CASE_TAC \\ fs[] +); + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml b/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml index 2d6c019a..f178a336 100644 --- a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml @@ -16,12 +16,12 @@ val _ = new_theory "sail_values" val _ = type_abbrev( "ii" , ``: int``); val _ = type_abbrev( "nn" , ``: num``); -(*val nat_of_int : Num.integer -> nat*) +(*val nat_of_int : integer -> nat*) val _ = Define ` ((nat_of_int:int -> num) i= (if i <( 0 : int) then( 0 : num) else Num (ABS (I i))))`; -(*val pow : Num.integer -> Num.integer -> Num.integer*) +(*val pow : integer -> integer -> integer*) val _ = Define ` ((pow0:int -> int -> int) m n= (m ** (nat_of_int n)))`; @@ -59,12 +59,12 @@ val _ = Define ` ((prerr_endline:string -> unit) _= () )`; -(*val print_int : string -> Num.integer -> unit*) +(*val print_int : string -> integer -> unit*) val _ = Define ` ((print_int:string -> int -> unit) msg i= (prerr_endline ( STRCAT msg (stringFromInteger i))))`; -(*val putchar : Num.integer -> unit*) +(*val putchar : integer -> unit*) val _ = Define ` ((putchar:int -> unit) _= () )`; @@ -75,7 +75,7 @@ val _ = Define ` val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn shr_int_defn; -(*val shl_int : Num.integer -> Num.integer -> Num.integer*) +(*val shl_int : integer -> integer -> integer*) val shl_int_defn = Hol_defn "shl_int" ` ((shl_int:int -> int -> int) i shift= (if shift >( 0 : int) then( 2 : int) * shl_int i (shift -( 1 : int)) else i))`; @@ -87,10 +87,10 @@ val _ = Define ` ((drop_list:int -> 'a list -> 'a list) n xs= (DROP (nat_of_int n) xs))`; -(*val repeat : forall 'a. list 'a -> Num.integer -> list 'a*) +(*val repeat : forall 'a. list 'a -> integer -> list 'a*) val repeat_defn = Hol_defn "repeat" ` - ((repeat:'a list -> int -> 'a list) xs n= - (if n <=( 0 : int) then [] + ((repeat:'a list -> int -> 'a list) xs n= + (if n <=( 0 : int) then [] else xs ++ repeat xs (n -( 1 : int))))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn repeat_defn; @@ -99,7 +99,7 @@ val _ = Define ` ((duplicate_to_list:'a -> int -> 'a list) bit length= (repeat [bit] length))`; - val replace_defn = Hol_defn "replace" ` + val _ = Define ` ((replace:'a list -> int -> 'a -> 'a list) bs (n : int) b'= ((case bs of [] => [] | b :: bs => @@ -107,7 +107,6 @@ val _ = Define ` else b :: replace bs (n -( 1 : int)) b' )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn replace_defn; val _ = Define ` ((upper:'a -> 'a) n= n)`; @@ -116,8 +115,8 @@ val _ = Define ` (* Modulus operation corresponding to quot below -- result has sign of dividend. *) val _ = Define ` - ((hardware_mod:int -> int -> int) (a: int) (b:int) : int= - (let m = ((ABS a) % (ABS b)) in + ((hardware_mod:int -> int -> int) (a: int) (b:int) : int= + (let m = ((ABS a) % (ABS b)) in if a <( 0 : int) then ~ m else m))`; @@ -126,8 +125,8 @@ rounding behaviour on negative operands. Positive operands always round down so derive the one we want (trucation towards zero) from that *) val _ = Define ` - ((hardware_quot:int -> int -> int) (a:int) (b:int) : int= - (let q = ((ABS a) / (ABS b)) in + ((hardware_quot:int -> int -> int) (a:int) (b:int) : int= + (let q = ((ABS a) / (ABS b)) in if ((a<( 0 : int)) <=> (b<( 0 : int))) then q (* same sign -- result positive *) else @@ -167,8 +166,8 @@ val _ = Define ` (* just_list takes a list of maybes and returns Just xs if all elements have a value, and Nothing if one of the elements is Nothing. *) -(*val just_list : forall 'a. list (Maybe.maybe 'a) -> Maybe.maybe (list 'a)*) - val just_list_defn = Hol_defn "just_list" ` +(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*) + val _ = Define ` ((just_list:('a option)list ->('a list)option) l= ((case l of [] => SOME [] | (x :: xs) => @@ -178,9 +177,8 @@ val _ = Define ` ) )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn just_list_defn; -(*val maybe_failwith : forall 'a. Maybe.maybe 'a -> 'a*) +(*val maybe_failwith : forall 'a. maybe 'a -> 'a*) val _ = Define ` ((maybe_failwith:'a option -> 'a)= (\x . (case x of SOME a => a | NONE => failwith "maybe_failwith" )))`; @@ -202,36 +200,36 @@ val _ = Define ` val _ = Define ` -((instance_Show_Show_Sail_values_bitU_dict:(bitU)lem_show$Show_class)= (<| +((instance_Show_Show_Sail_values_bitU_dict:(bitU)Show_class)= (<| show_method := showBitU|>))`; -(*val compare_bitU : bitU -> bitU -> Basic_classes.ordering*) +(*val compare_bitU : bitU -> bitU -> ordering*) val _ = Define ` - ((compare_bitU:bitU -> bitU -> lem_basic_classes$ordering) l r= ((case (l, r) of - (BU, BU) => EQ - | (B0, B0) => EQ - | (B1, B1) => EQ - | (BU, _) => LT - | (_, BU) => GT - | (B0, _) => LT - | (_, _) => GT + ((compare_bitU:bitU -> bitU -> ordering) l r= ((case (l, r) of + (BU, BU) => EQUAL + | (B0, B0) => EQUAL + | (B1, B1) => EQUAL + | (BU, _) => LESS + | (_, BU) => GREATER + | (B0, _) => LESS + | (_, _) => GREATER )))`; val _ = Define ` -((instance_Basic_classes_Ord_Sail_values_bitU_dict:(bitU)lem_basic_classes$Ord_class)= (<| +((instance_Basic_classes_Ord_Sail_values_bitU_dict:(bitU)Ord_class)= (<| compare_method := compare_bitU; - isLess_method := (\ l r. (compare_bitU l r) = LT); + isLess_method := (\ l r. (compare_bitU l r) = LESS); - isLessEqual_method := (\ l r. (compare_bitU l r) <> GT); + isLessEqual_method := (\ l r. (compare_bitU l r) <> GREATER); - isGreater_method := (\ l r. (compare_bitU l r) = GT); + isGreater_method := (\ l r. (compare_bitU l r) = GREATER); - isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LT)|>))`; + isGreaterEqual_method := (\ l r. (compare_bitU l r) <> LESS)|>))`; val _ = Hol_datatype ` @@ -272,16 +270,16 @@ val _ = Define ` (\x . (case x of B1 => B0 | B0 => B1 | BU => BU )))`; -(*val is_one : Num.integer -> bitU*) +(*val is_one : integer -> bitU*) val _ = Define ` - ((is_one:int -> bitU) i= - (if i =( 1 : int) then B1 else B0))`; + ((is_one:int -> bitU) i= + (if i =( 1 : int) then B1 else B0))`; (*val and_bit : bitU -> bitU -> bitU*) val _ = Define ` - ((and_bit:bitU -> bitU -> bitU) x y= - ((case (x, y) of + ((and_bit:bitU -> bitU -> bitU) x y= + ((case (x, y) of (B0, _) => B0 | (_, B0) => B0 | (B1, B1) => B1 @@ -291,8 +289,8 @@ val _ = Define ` (*val or_bit : bitU -> bitU -> bitU*) val _ = Define ` - ((or_bit:bitU -> bitU -> bitU) x y= - ((case (x, y) of + ((or_bit:bitU -> bitU -> bitU) x y= + ((case (x, y) of (B1, _) => B1 | (_, B1) => B1 | (B0, B0) => B0 @@ -302,8 +300,8 @@ val _ = Define ` (*val xor_bit : bitU -> bitU -> bitU*) val _ = Define ` - ((xor_bit:bitU -> bitU -> bitU) x y= -((case (x, y) of + ((xor_bit:bitU -> bitU -> bitU) x y= + ((case (x, y) of (B0, B0) => B0 | (B0, B1) => B1 | (B1, B0) => B1 @@ -321,10 +319,10 @@ val _ = Define ` (*** Bool lists ***) -(*val bools_of_nat_aux : Num.integer -> Num.natural -> list bool -> list bool*) +(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*) val bools_of_nat_aux_defn = Hol_defn "bools_of_nat_aux" ` - ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc= - (if len <=( 0 : int) then acc + ((bools_of_nat_aux:int -> num ->(bool)list ->(bool)list) len x acc= + (if len <=( 0 : int) then acc else bools_of_nat_aux (len -( 1 : int)) (x DIV( 2:num)) ((if (x MOD( 2:num)) =( 1:num) then T else F) :: acc)))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn bools_of_nat_aux_defn; @@ -332,49 +330,48 @@ val _ = Define ` ((bools_of_nat:int -> num ->(bool)list) len n= (bools_of_nat_aux len n []))`; (*List.reverse (bools_of_nat_aux n)*) -(*val nat_of_bools_aux : Num.natural -> list bool -> Num.natural*) - val nat_of_bools_aux_defn = Hol_defn "nat_of_bools_aux" ` +(*val nat_of_bools_aux : natural -> list bool -> natural*) + val _ = Define ` ((nat_of_bools_aux:num ->(bool)list -> num) acc bs= ((case bs of [] => acc | T :: bs => nat_of_bools_aux ((( 2:num) * acc) +( 1:num)) bs | F :: bs => nat_of_bools_aux (( 2:num) * acc) bs )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn nat_of_bools_aux_defn; val _ = Define ` ((nat_of_bools:(bool)list -> num) bs= (nat_of_bools_aux(( 0:num)) bs))`; -(*val unsigned_of_bools : list bool -> Num.integer*) +(*val unsigned_of_bools : list bool -> integer*) val _ = Define ` ((unsigned_of_bools:(bool)list -> int) bs= (int_of_num (nat_of_bools bs)))`; -(*val signed_of_bools : list bool -> Num.integer*) +(*val signed_of_bools : list bool -> integer*) val _ = Define ` - ((signed_of_bools:(bool)list -> int) bs= - ((case bs of + ((signed_of_bools:(bool)list -> int) bs= + ((case bs of T :: _ =>( 0 : int) - (( 1 : int) + (unsigned_of_bools (MAP (\ x. ~ x) bs))) | F :: _ => unsigned_of_bools bs | [] =>( 0 : int) (* Treat empty list as all zeros *) )))`; -(*val int_of_bools : bool -> list bool -> Num.integer*) +(*val int_of_bools : bool -> list bool -> integer*) val _ = Define ` ((int_of_bools:bool ->(bool)list -> int) sign bs= (if sign then signed_of_bools bs else unsigned_of_bools bs))`; -(*val pad_list : forall 'a. 'a -> list 'a -> Num.integer -> list 'a*) +(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*) val pad_list_defn = Hol_defn "pad_list" ` - ((pad_list:'a -> 'a list -> int -> 'a list) x xs n= - (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`; + ((pad_list:'a -> 'a list -> int -> 'a list) x xs n= + (if n <=( 0 : int) then xs else pad_list x (x :: xs) (n -( 1 : int))))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn pad_list_defn; val _ = Define ` - ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs= - (let longer = (len - (int_of_num (LENGTH xs))) in + ((ext_list:'a -> int -> 'a list -> 'a list) pad len xs= + (let longer = (len - (int_of_num (LENGTH xs))) in if longer <( 0 : int) then DROP (nat_of_int (ABS (longer))) xs else pad_list pad xs longer))`; @@ -383,25 +380,24 @@ val _ = Define ` ((extz_bools:int ->(bool)list ->(bool)list) len bs= (ext_list F len bs))`; val _ = Define ` - ((exts_bools:int ->(bool)list ->(bool)list) len bs= - ((case bs of + ((exts_bools:int ->(bool)list ->(bool)list) len bs= + ((case bs of T :: _ => ext_list T len bs | _ => ext_list F len bs )))`; - val add_one_bool_ignore_overflow_aux_defn = Hol_defn "add_one_bool_ignore_overflow_aux" ` + val _ = Define ` ((add_one_bool_ignore_overflow_aux:(bool)list ->(bool)list) bits= ((case bits of [] => [] | F :: bits => T :: bits | T :: bits => F :: add_one_bool_ignore_overflow_aux bits )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn add_one_bool_ignore_overflow_aux_defn; val _ = Define ` - ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits= - (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`; + ((add_one_bool_ignore_overflow:(bool)list ->(bool)list) bits= + (REVERSE (add_one_bool_ignore_overflow_aux (REVERSE bits))))`; (*let bool_list_of_int n = @@ -410,8 +406,8 @@ val _ = Define ` else add_one_bool_ignore_overflow (List.map not bs_abs) let bools_of_int len n = exts_bools len (bool_list_of_int n)*) val _ = Define ` - ((bools_of_int:int -> int ->(bool)list) len n= - (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in + ((bools_of_int:int -> int ->(bool)list) len n= + (let bs_abs = (bools_of_nat len (Num (ABS (ABS n)))) in if n >= (( 0 : int) : int) then bs_abs else add_one_bool_ignore_overflow (MAP (\ x. ~ x) bs_abs)))`; @@ -429,8 +425,8 @@ val _ = Define ` val _ = Define ` - ((nat_of_bits:(bitU)list ->(num)option) bits= - ((case (just_list (MAP bool_of_bitU bits)) of + ((nat_of_bits:(bitU)list ->(num)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of SOME bs => SOME (nat_of_bools bs) | NONE => NONE )))`; @@ -442,27 +438,27 @@ val _ = Define ` (*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*) val _ = Define ` - ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys= - (FOLDR (\ (x, y) acc . op x y :: acc) [] (list_combine xs ys)))`; + ((binop_list:('a -> 'a -> 'a) -> 'a list -> 'a list -> 'a list) op xs ys= + (FOLDR (\ (x, y) acc . op x y :: acc) [] (list_combine xs ys)))`; val _ = Define ` - ((unsigned_of_bits:(bitU)list ->(int)option) bits= - ((case (just_list (MAP bool_of_bitU bits)) of + ((unsigned_of_bits:(bitU)list ->(int)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of SOME bs => SOME (unsigned_of_bools bs) | NONE => NONE )))`; val _ = Define ` - ((signed_of_bits:(bitU)list ->(int)option) bits= - ((case (just_list (MAP bool_of_bitU bits)) of + ((signed_of_bits:(bitU)list ->(int)option) bits= + ((case (just_list (MAP bool_of_bitU bits)) of SOME bs => SOME (signed_of_bools bs) | NONE => NONE )))`; -(*val int_of_bits : bool -> list bitU -> Maybe.maybe Num.integer*) +(*val int_of_bits : bool -> list bitU -> maybe integer*) val _ = Define ` ((int_of_bits:bool ->(bitU)list ->(int)option) sign bs= (if sign then signed_of_bits bs else unsigned_of_bits bs))`; @@ -471,15 +467,15 @@ val _ = Define ` ((extz_bits:int ->(bitU)list ->(bitU)list) len bits= (ext_list B0 len bits))`; val _ = Define ` - ((exts_bits:int ->(bitU)list ->(bitU)list) len bits= - ((case bits of + ((exts_bits:int ->(bitU)list ->(bitU)list) len bits= + ((case bits of BU :: _ => ext_list BU len bits | B1 :: _ => ext_list B1 len bits | _ => ext_list B0 len bits )))`; - val add_one_bit_ignore_overflow_aux_defn = Hol_defn "add_one_bit_ignore_overflow_aux" ` + val _ = Define ` ((add_one_bit_ignore_overflow_aux:(bitU)list ->(bitU)list) bits= ((case bits of [] => [] | B0 :: bits => B1 :: bits @@ -488,11 +484,10 @@ val _ = Define ` (case (b ) of ( _ ) => BU )) bits )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn add_one_bit_ignore_overflow_aux_defn; val _ = Define ` - ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits= - (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`; + ((add_one_bit_ignore_overflow:(bitU)list ->(bitU)list) bits= + (REVERSE (add_one_bit_ignore_overflow_aux (REVERSE bits))))`; (*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n) @@ -502,10 +497,10 @@ val _ = Define ` (*val arith_op_bits : - (Num.integer -> Num.integer -> Num.integer) -> bool -> list bitU -> list bitU -> list bitU*) + (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*) val _ = Define ` - ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r= - ((case (int_of_bits sign l, int_of_bits sign r) of + ((arith_op_bits:(int -> int -> int) -> bool ->(bitU)list ->(bitU)list ->(bitU)list) op sign l r= + ((case (int_of_bits sign l, int_of_bits sign r) of (SOME li, SOME ri) => bits_of_int (int_of_num (LENGTH l)) (op li ri) | (_, _) => repeat [BU] (int_of_num (LENGTH l)) )))`; @@ -534,7 +529,7 @@ val _ = Define ` )))`; - val hexstring_of_bits_defn = Hol_defn "hexstring_of_bits" ` + val _ = Define ` ((hexstring_of_bits:(bitU)list ->((char)list)option) bs= ((case bs of b1 :: b2 :: b3 :: b4 :: bs => let n = (char_of_nibble (b1, b2, b3, b4)) in @@ -543,94 +538,94 @@ val _ = Define ` (SOME n, SOME s) => SOME (n :: s) | _ => NONE ) + | [] => SOME [] | _ => NONE )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn hexstring_of_bits_defn; val _ = Define ` - ((show_bitlist:(bitU)list -> string) bs= - ((case hexstring_of_bits bs of + ((show_bitlist:(bitU)list -> string) bs= + ((case hexstring_of_bits bs of SOME s => IMPLODE (#"0" :: (#"x" :: s)) | NONE => IMPLODE (#"0" :: (#"b" :: MAP bitU_char bs)) )))`; -(*val subrange_list_inc : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a*) +(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*) val _ = Define ` - ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j= - (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in + ((subrange_list_inc:'a list -> int -> int -> 'a list) xs i j= + (let (toJ,suffix0) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in let (prefix0,fromItoJ) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in fromItoJ))`; -(*val subrange_list_dec : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a*) +(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*) val _ = Define ` - ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j= - (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + ((subrange_list_dec:'a list -> int -> int -> 'a list) xs i j= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in subrange_list_inc xs (top - i) (top - j)))`; -(*val subrange_list : forall 'a. bool -> list 'a -> Num.integer -> Num.integer -> list 'a*) +(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*) val _ = Define ` ((subrange_list:bool -> 'a list -> int -> int -> 'a list) is_inc xs i j= (if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j))`; -(*val update_subrange_list_inc : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) val _ = Define ` - ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= - (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in - let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in -(prefix ++ xs') ++ suffix))`; + ((update_subrange_list_inc:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= + (let (toJ,suffix) = (TAKE (nat_of_int (j +( 1 : int))) xs, DROP (nat_of_int (j +( 1 : int))) xs) in + let (prefix,fromItoJ0) = (TAKE (nat_of_int i) toJ, DROP (nat_of_int i) toJ) in + (prefix ++ xs') ++ suffix))`; -(*val update_subrange_list_dec : forall 'a. list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) val _ = Define ` - ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= - (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + ((update_subrange_list_dec:'a list -> int -> int -> 'a list -> 'a list) xs i j xs'= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in update_subrange_list_inc xs (top - i) (top - j) xs'))`; -(*val update_subrange_list : forall 'a. bool -> list 'a -> Num.integer -> Num.integer -> list 'a -> list 'a*) +(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*) val _ = Define ` - ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'= - (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`; + ((update_subrange_list:bool -> 'a list -> int -> int -> 'a list -> 'a list) is_inc xs i j xs'= + (if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs'))`; -(*val access_list_inc : forall 'a. list 'a -> Num.integer -> 'a*) +(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*) val _ = Define ` ((access_list_inc:'a list -> int -> 'a) xs n= (EL (nat_of_int n) xs))`; -(*val access_list_dec : forall 'a. list 'a -> Num.integer -> 'a*) +(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*) val _ = Define ` - ((access_list_dec:'a list -> int -> 'a) xs n= - (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + ((access_list_dec:'a list -> int -> 'a) xs n= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in access_list_inc xs (top - n)))`; -(*val access_list : forall 'a. bool -> list 'a -> Num.integer -> 'a*) +(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*) val _ = Define ` - ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n= - (if is_inc then access_list_inc xs n else access_list_dec xs n))`; + ((access_list:bool -> 'a list -> int -> 'a) is_inc xs n= + (if is_inc then access_list_inc xs n else access_list_dec xs n))`; -(*val update_list_inc : forall 'a. list 'a -> Num.integer -> 'a -> list 'a*) +(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*) val _ = Define ` ((update_list_inc:'a list -> int -> 'a -> 'a list) xs n x= (LUPDATE x (nat_of_int n) xs))`; -(*val update_list_dec : forall 'a. list 'a -> Num.integer -> 'a -> list 'a*) +(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*) val _ = Define ` - ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x= - (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in + ((update_list_dec:'a list -> int -> 'a -> 'a list) xs n x= + (let top = ((int_of_num (LENGTH xs)) -( 1 : int)) in update_list_inc xs (top - n) x))`; -(*val update_list : forall 'a. bool -> list 'a -> Num.integer -> 'a -> list 'a*) +(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*) val _ = Define ` - ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x= - (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`; + ((update_list:bool -> 'a list -> int -> 'a -> 'a list) is_inc xs n x= + (if is_inc then update_list_inc xs n x else update_list_dec xs n x))`; val _ = Define ` @@ -640,62 +635,62 @@ val _ = Define ` (*** Machine words *) -(*val length_mword : forall 'a. Machine_word.mword 'a -> Num.integer*) +(*val length_mword : forall 'a. mword 'a -> integer*) -(*val slice_mword_dec : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) val _ = Define ` ((slice_mword_dec:'a words$word -> int -> int -> 'b words$word) w i j= (words$word_extract (nat_of_int j) (nat_of_int i) w))`; -(*val slice_mword_inc : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) val _ = Define ` - ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j= - (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + ((slice_mword_inc:'a words$word -> int -> int -> 'b words$word) w i j= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in slice_mword_dec w (top - i) (top - j)))`; -(*val slice_mword : forall 'a 'b. bool -> Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b*) +(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*) val _ = Define ` ((slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word) is_inc w i j= (if is_inc then slice_mword_inc w i j else slice_mword_dec w i j))`; -(*val update_slice_mword_dec : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) val _ = Define ` ((update_slice_mword_dec:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= (words$bit_field_insert (nat_of_int j) (nat_of_int i) w' w))`; -(*val update_slice_mword_inc : forall 'a 'b. Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) val _ = Define ` - ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= - (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + ((update_slice_mword_inc:'a words$word -> int -> int -> 'b words$word -> 'a words$word) w i j w'= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in update_slice_mword_dec w (top - i) (top - j) w'))`; -(*val update_slice_mword : forall 'a 'b. bool -> Machine_word.mword 'a -> Num.integer -> Num.integer -> Machine_word.mword 'b -> Machine_word.mword 'a*) +(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*) val _ = Define ` - ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'= - (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`; + ((update_slice_mword:bool -> 'a words$word -> int -> int -> 'b words$word -> 'a words$word) is_inc w i j w'= + (if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w'))`; -(*val access_mword_dec : forall 'a. Machine_word.mword 'a -> Num.integer -> bitU*) +(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*) val _ = Define ` ((access_mword_dec:'a words$word -> int -> bitU) w n= (bitU_of_bool (words$word_bit (nat_of_int n) w)))`; -(*val access_mword_inc : forall 'a. Machine_word.mword 'a -> Num.integer -> bitU*) +(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*) val _ = Define ` - ((access_mword_inc:'a words$word -> int -> bitU) w n= - (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + ((access_mword_inc:'a words$word -> int -> bitU) w n= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in access_mword_dec w (top - n)))`; -(*val access_mword : forall 'a. bool -> Machine_word.mword 'a -> Num.integer -> bitU*) +(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*) val _ = Define ` - ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n= - (if is_inc then access_mword_inc w n else access_mword_dec w n))`; + ((access_mword:bool -> 'a words$word -> int -> bitU) is_inc w n= + (if is_inc then access_mword_inc w n else access_mword_dec w n))`; -(*val update_mword_bool_dec : forall 'a. Machine_word.mword 'a -> Num.integer -> bool -> Machine_word.mword 'a*) +(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*) val _ = Define ` ((update_mword_bool_dec:'a words$word -> int -> bool -> 'a words$word) w n b= ($:+ (nat_of_int n) b w))`; @@ -703,20 +698,20 @@ val _ = Define ` ((update_mword_dec:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_dec w n) (bool_of_bitU b)))`; -(*val update_mword_bool_inc : forall 'a. Machine_word.mword 'a -> Num.integer -> bool -> Machine_word.mword 'a*) +(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*) val _ = Define ` - ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b= - (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in + ((update_mword_bool_inc:'a words$word -> int -> bool -> 'a words$word) w n b= + (let top = ((int_of_num (words$word_len w)) -( 1 : int)) in update_mword_bool_dec w (top - n) b))`; val _ = Define ` ((update_mword_inc:'a words$word -> int -> bitU ->('a words$word)option) w n b= (OPTION_MAP (update_mword_bool_inc w n) (bool_of_bitU b)))`; -(*val int_of_mword : forall 'a. bool -> Machine_word.mword 'a -> Num.integer*) +(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*) val _ = Define ` - ((int_of_mword:bool -> 'a words$word -> int) sign w= - (if sign then integer_word$w2i w else lem$w2ui w))`; + ((int_of_mword:bool -> 'a words$word -> int) sign w= + (if sign then integer_word$w2i w else lem$w2ui w))`; (* Translating between a type level number (itself 'n) and an integer *) @@ -728,7 +723,7 @@ val _ = Define ` (* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), the actual integer is ignored. *) -(*val make_the_value : forall 'n. Num.integer -> Machine_word.itself 'n*) +(*val make_the_value : forall 'n. integer -> itself 'n*) val _ = Define ` ((make_the_value:int -> 'n itself) _= the_value)`; @@ -850,13 +845,13 @@ val _ = Define ` dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`; -(*val extz_bv : forall 'a. Bitvector 'a => Num.integer -> 'a -> list bitU*) +(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) val _ = Define ` ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (extz_bits n ( dict_Sail_values_Bitvector_a.bits_of_method v)))`; -(*val exts_bv : forall 'a. Bitvector 'a => Num.integer -> 'a -> list bitU*) +(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) val _ = Define ` ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (exts_bits n ( dict_Sail_values_Bitvector_a.bits_of_method v)))`; @@ -872,8 +867,8 @@ val _ = Define ` val _ = type_abbrev( "memory_byte" , ``: bitU list``); -(*val byte_chunks : forall 'a. list 'a -> Maybe.maybe (list (list 'a))*) - val byte_chunks_defn = Hol_defn "byte_chunks" ` +(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*) + val _ = Define ` ((byte_chunks:'a list ->(('a list)list)option) bs= ((case bs of [] => SOME [] | a::b::c::d::e::f::g::h::rest => @@ -881,9 +876,8 @@ val _ = type_abbrev( "memory_byte" , ``: bitU list``); | _ => NONE )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn byte_chunks_defn; -(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> Maybe.maybe (list memory_byte)*) +(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*) val _ = Define ` ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail_values_Bitvector_a bs= (byte_chunks ( dict_Sail_values_Bitvector_a.bits_of_method bs)))`; @@ -946,8 +940,8 @@ let address_of_bitv v = address_of_byte_list bytes*) val reverse_endianness_list_defn = Hol_defn "reverse_endianness_list" ` - ((reverse_endianness_list:'a list -> 'a list) bits= - (if LENGTH bits <=( 8 : num) then bits else + ((reverse_endianness_list:'a list -> 'a list) bits= + (if LENGTH bits <=( 8 : num) then bits else reverse_endianness_list (drop_list(( 8 : int)) bits) ++ take_list(( 8 : int)) bits))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn reverse_endianness_list_defn; @@ -1116,19 +1110,18 @@ let internal_mem_value bytes = (*val foreach : forall 'a 'vars. (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*) - val foreach_defn = Hol_defn "foreach" ` - ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body= - ((case l of + val _ = Define ` + ((foreach:'a list -> 'vars ->('a -> 'vars -> 'vars) -> 'vars) l vars body= + ((case l of [] => vars | (x :: xs) => foreach xs (body x vars) body )))`; -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreach_defn; -(*val index_list : Num.integer -> Num.integer -> Num.integer -> list Num.integer*) +(*val index_list : integer -> integer -> integer -> list integer*) val index_list_defn = Hol_defn "index_list" ` - ((index_list:int -> int -> int ->(int)list) from to step= - (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then + ((index_list:int -> int -> int ->(int)list) from to step= + (if ((step >( 0 : int)) /\ (from <= to)) \/ ((step <( 0 : int)) /\ (to <= from)) then from :: index_list (from + step) to step else []))`; @@ -1136,15 +1129,15 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn (*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) val while_defn = Hol_defn "while" ` - ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= - (if cond vars then while (body vars) cond body else vars))`; + ((while:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= + (if cond vars then while (body vars) cond body else vars))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn while_defn; (*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) val until_defn = Hol_defn "until" ` - ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= - (let vars = (body vars) in + ((until:'vars ->('vars -> bool) ->('vars -> 'vars) -> 'vars) vars cond body= + (let vars = (body vars) in if cond vars then vars else until (body vars) cond body))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn until_defn; @@ -1178,8 +1171,8 @@ val _ = Define ` val _ = Define ` - ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5)= - (dict_Sail_values_ToNatural_d.toNatural_method n1, dict_Sail_values_ToNatural_c.toNatural_method n2, dict_Sail_values_ToNatural_b.toNatural_method n3, dict_Sail_values_ToNatural_a.toNatural_method n4, dict_Sail_values_ToNatural_e.toNatural_method n5))`; + ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5)= + (dict_Sail_values_ToNatural_d.toNatural_method n1, dict_Sail_values_ToNatural_c.toNatural_method n2, dict_Sail_values_ToNatural_b.toNatural_method n3, dict_Sail_values_ToNatural_a.toNatural_method n4, dict_Sail_values_ToNatural_e.toNatural_method n5))`; (* Let the following types be generated by Sail per spec, using either bitlists diff --git a/snapshots/hol4/sail/lib/hol/stateScript.sml b/snapshots/hol4/sail/lib/hol/stateScript.sml index 0eb048a0..ec3e6c26 100644 --- a/snapshots/hol4/sail/lib/hol/stateScript.sml +++ b/snapshots/hol4/sail/lib/hol/stateScript.sml @@ -13,41 +13,51 @@ val _ = new_theory "state" (*open import State_monad*) (*open import {isabelle} `State_monad_lemmas`*) -(*val iterS_aux : forall 'rv 'a 'e. Num.integer -> (Num.integer -> 'a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) +(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) val iterS_aux_defn = Hol_defn "iterS_aux" ` - ((iterS_aux:int ->(int -> 'a -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) i f xs= ((case xs of + ((iterS_aux:int ->(int -> 'a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) i f xs= ((case xs of x :: xs => seqS (f i x) (iterS_aux (i +( 1 : int)) f xs) | [] => returnS () )))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn iterS_aux_defn; -(*val iteriS : forall 'rv 'a 'e. (Num.integer -> 'a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) +(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) val _ = Define ` - ((iteriS:(int -> 'a ->('rv,(unit),'e)state_monad$monadS) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) f xs= (iterS_aux(( 0 : int)) f xs))`; + ((iteriS:(int -> 'a ->('rv,(unit),'e)monadS) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs= (iterS_aux(( 0 : int)) f xs))`; -(*val iterS : forall 'rv 'a 'e. ('a -> State_monad.monadS 'rv unit 'e) -> list 'a -> State_monad.monadS 'rv unit 'e*) +(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) val _ = Define ` - ((iterS:('a -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'a list -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) f xs= (iteriS (\i x . + ((iterS:('a -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) -> 'a list -> 'rv sequential_state ->(((unit),'e)result#'rv sequential_state)set) f xs= (iteriS (\i x . (case (i ,x ) of ( _ , x ) => f x )) xs))`; (*val foreachS : forall 'a 'rv 'vars 'e. - list 'a -> 'vars -> ('a -> 'vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) + list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) val foreachS_defn = Hol_defn "foreachS" ` - ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) xs vars body= ((case xs of + ((foreachS:'a list -> 'vars ->('a -> 'vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) xs vars body= ((case xs of [] => returnS vars - | x :: xs => bindS -(body x vars) (\ vars . + | x :: xs => bindS + (body x vars) (\ vars . foreachS xs vars body) )))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn foreachS_defn; -(*val bool_of_bitU_fail : forall 'rv 'e. Sail_values.bitU -> State_monad.monadS 'rv bool 'e*) +(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*) val _ = Define ` - ((bool_of_bitU_fail:sail_values$bitU -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set)= + ((and_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r= (bindS l (\ l . if l then r else returnS F)))`; + + +(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*) +val _ = Define ` + ((or_boolS:('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) l r= (bindS l (\ l . if l then returnS T else r)))`; + + +(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) +val _ = Define ` + ((bool_of_bitU_fail:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= (\x . (case x of B0 => returnS F | B1 => returnS T @@ -55,9 +65,9 @@ val _ = Define ` )))`; -(*val bool_of_bitU_oracleS : forall 'rv 'e. Sail_values.bitU -> State_monad.monadS 'rv bool 'e*) +(*val bool_of_bitU_oracleS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) val _ = Define ` - ((bool_of_bitU_oracleS:sail_values$bitU -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set)= + ((bool_of_bitU_oracleS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= (\x . (case x of B0 => returnS F | B1 => returnS T @@ -65,52 +75,52 @@ val _ = Define ` )))`; -(*val bools_of_bits_oracleS : forall 'rv 'e. list Sail_values.bitU -> State_monad.monadS 'rv (list bool) 'e*) +(*val bools_of_bits_oracleS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*) val _ = Define ` - ((bools_of_bits_oracleS:(sail_values$bitU)list -> 'rv state_monad$sequential_state ->((((bool)list),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= - (foreachS bits [] - (\ b bools . bindS -(bool_of_bitU_oracleS b) (\ b . + ((bools_of_bits_oracleS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits= + (foreachS bits [] + (\ b bools . bindS + (bool_of_bitU_oracleS b) (\ b . returnS (bools ++ [b])))))`; -(*val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list Sail_values.bitU -> State_monad.monadS 'rv 'a 'e*) +(*val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) val _ = Define ` - ((of_bits_oracleS:'a sail_values$Bitvector_class ->(sail_values$bitU)list ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a bits= (bindS -(bools_of_bits_oracleS bits) (\ bs . + ((of_bits_oracleS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits= (bindS + (bools_of_bits_oracleS bits) (\ bs . returnS (dict_Sail_values_Bitvector_a.of_bools_method bs))))`; -(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list Sail_values.bitU -> State_monad.monadS 'rv 'a 'e*) +(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) val _ = Define ` - ((of_bits_failS:'a sail_values$Bitvector_class ->(sail_values$bitU)list ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a bits= (maybe_failS "of_bits" ( + ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits= (maybe_failS "of_bits" ( dict_Sail_values_Bitvector_a.of_bits_method bits)))`; -(*val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> State_monad.monadS 'rv (Machine_word.mword 'a) 'e*) +(*val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*) val _ = Define ` - ((mword_oracleS:unit -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) () = (bindS -(bools_of_bits_oracleS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . + ((mword_oracleS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () = (bindS + (bools_of_bits_oracleS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . returnS (bitstring$v2w bs))))`; -(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> State_monad.monadS 'rv bool 'e) -> - ('vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) +(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) val whileS_defn = Hol_defn "whileS" ` - ((whileS:'vars ->('vars -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set) ->('vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) vars cond body s= - (( bindS(cond vars) (\ cond_val s' . + ((whileS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s= + (( bindS(cond vars) (\ cond_val s' . if cond_val then ( bindS(body vars) (\ vars s'' . whileS vars cond body s'')) s' else returnS vars s')) s))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn whileS_defn; -(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> State_monad.monadS 'rv bool 'e) -> - ('vars -> State_monad.monadS 'rv 'vars 'e) -> State_monad.monadS 'rv 'vars 'e*) +(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) val untilS_defn = Hol_defn "untilS" ` - ((untilS:'vars ->('vars -> 'rv state_monad$sequential_state ->(((bool),'e)state_monad$result#'rv state_monad$sequential_state)set) ->('vars -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) -> 'rv state_monad$sequential_state ->(('vars,'e)state_monad$result#'rv state_monad$sequential_state)set) vars cond body s= - (( bindS(body vars) (\ vars s' . + ((untilS:'vars ->('vars -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set) ->('vars -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) -> 'rv sequential_state ->(('vars,'e)result#'rv sequential_state)set) vars cond body s= + (( bindS(body vars) (\ vars s' . ( bindS(cond vars) (\ cond_val s'' . if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`; diff --git a/snapshots/hol4/sail/lib/hol/state_monadScript.sml b/snapshots/hol4/sail/lib/hol/state_monadScript.sml index cf4764c0..ba687761 100644 --- a/snapshots/hol4/sail/lib/hol/state_monadScript.sml +++ b/snapshots/hol4/sail/lib/hol/state_monadScript.sml @@ -14,8 +14,8 @@ val _ = new_theory "state_monad" (* 'a is result type *) -val _ = type_abbrev( "memstate" , ``: (int, sail_values$memory_byte) fmap``); -val _ = type_abbrev( "tagstate" , ``: (int, sail_values$bitU) fmap``); +val _ = type_abbrev( "memstate" , ``: (int, memory_byte) fmap``); +val _ = type_abbrev( "tagstate" , ``: (int, bitU) fmap``); (* type regstate = map string (vector bitU) *) val _ = Hol_datatype ` @@ -23,7 +23,7 @@ val _ = Hol_datatype ` <| regstate : 'regs; memstate : memstate; tagstate : tagstate; - write_ea : (sail_instr_kinds$write_kind # int # int)option; + write_ea : (write_kind # int # int)option; last_exclusive_operation_was_load : bool; (* Random bool generator for use as an undefined bit oracle *) next_bool : num -> (bool # num); @@ -32,8 +32,8 @@ val _ = Hol_datatype ` (*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) val _ = Define ` - ((init_state:'regs ->(num -> bool#num) -> num -> 'regs sequential_state) regs o1 s= - (<| regstate := regs; + ((init_state:'regs ->(num -> bool#num) -> num -> 'regs sequential_state) regs o1 s= + (<| regstate := regs; memstate := FEMPTY; tagstate := FEMPTY; write_ea := NONE; @@ -65,8 +65,8 @@ val _ = Define ` (*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*) val _ = Define ` - ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)= - (BIGUNION (IMAGE (\x . + ((bindS:('regs sequential_state ->(('a,'e)result#'regs sequential_state)set) ->('a -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) -> 'regs sequential_state ->(('b,'e)result#'regs sequential_state)set) m f (s : 'regs sequential_state)= + (BIGUNION (IMAGE (\x . (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s))))`; @@ -98,10 +98,10 @@ val _ = Define ` (*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) val _ = Define ` - ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS -(readS (\ s . s.next_bool (s.seed))) (\ (b, seed) . seqS -(updateS (\ s . ( s with<| seed := seed |>))) -(returnS b))))`; + ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS + (readS (\ s . s.next_bool (s.seed))) (\ (b, seed) . seqS + (updateS (\ s . ( s with<| seed := seed |>))) + (returnS b))))`; (*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) @@ -116,8 +116,8 @@ val _ = Define ` (*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*) val _ = Define ` - ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s= - (BIGUNION (IMAGE (\x . + ((try_catchS:('regs sequential_state ->(('a,'e1)result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e2)result#'regs sequential_state)set) m h s= + (BIGUNION (IMAGE (\x . (case x of (Value a, s') => returnS a s' | (Ex (Throw e), s') => h e s' @@ -142,8 +142,8 @@ val _ = Define ` (*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) val _ = Define ` - ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m= - (try_catchS m + ((catch_early_returnS:('regs sequential_state ->(('a,(('a,'e)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) m= + (try_catchS m (\x . (case x of INL a => returnS a | INR e => throwS e ))))`; @@ -156,30 +156,30 @@ val _ = Define ` (* Catch exceptions in the presence of early returns *) (*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2*) val _ = Define ` - ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h= - (try_catchS m + ((try_catchRS:('regs sequential_state ->(('a,(('r,'e1)sum))result#'regs sequential_state)set) ->('e1 -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) -> 'regs sequential_state ->(('a,(('r,'e2)sum))result#'regs sequential_state)set) m h= + (try_catchS m (\x . (case x of INL r => throwS (INL r) | INR e => h e ))))`; -(*val maybe_failS : forall 'regs 'a 'e. string -> Maybe.maybe 'a -> monadS 'regs 'a 'e*) +(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*) val _ = Define ` ((maybe_failS:string -> 'a option -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) msg= (\x . (case x of SOME a => returnS a | NONE => failS msg )))`; -(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs Sail_values.bitU 'e*) +(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*) val _ = Define ` - ((read_tagS:'a sail_values$Bitvector_class -> 'a ->('regs,(sail_values$bitU),'e)monadS)dict_Sail_values_Bitvector_a addr= (bindS -(maybe_failS "unsigned" ( + ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail_values_Bitvector_a addr= (bindS + (maybe_failS "unsigned" ( dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . readS (\ s . option_CASE (FLOOKUP s.tagstate addr) B0 I))))`; (* Read bytes from memory and return in little endian order *) -(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => Sail_instr_kinds.read_kind -> 'a -> nat -> monadS 'regs (list Sail_values.memory_byte) 'e*) +(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*) val _ = Define ` - ((read_mem_bytesS:'a sail_values$Bitvector_class -> sail_instr_kinds$read_kind -> 'a -> num ->('regs,((sail_values$memory_byte)list),'e)monadS)dict_Sail_values_Bitvector_a read_kind addr sz= (bindS -(maybe_failS "unsigned" ( + ((read_mem_bytesS:'a Bitvector_class -> read_kind -> 'a -> num ->('regs,((memory_byte)list),'e)monadS)dict_Sail_values_Bitvector_a read_kind addr sz= (bindS + (maybe_failS "unsigned" ( dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . let sz = (int_of_num sz) in let addrs = (index_list addr ((addr+sz)-( 1 : int))(( 1 : int))) in @@ -196,36 +196,36 @@ val _ = Define ` )))))`; -(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => Sail_instr_kinds.read_kind -> 'a -> Num.integer -> monadS 'regs 'b 'e*) +(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*) val _ = Define ` - ((read_memS:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> sail_instr_kinds$read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz= (bindS -(read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . + ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz= (bindS + (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . maybe_failS "bits_of_mem_bytes" ( dict_Sail_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`; (*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) val _ = Define ` - ((excl_resultS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS -(readS (\ s . s.last_exclusive_operation_was_load)) (\ excl_load . seqS -(updateS (\ s . ( s with<| last_exclusive_operation_was_load := F |>))) -(chooseS (if excl_load then {F; T} else {F})))))`; + ((excl_resultS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS + (readS (\ s . s.last_exclusive_operation_was_load)) (\ excl_load . seqS + (updateS (\ s . ( s with<| last_exclusive_operation_was_load := F |>))) + (chooseS (if excl_load then {F; T} else {F})))))`; -(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => Sail_instr_kinds.write_kind -> 'a -> nat -> monadS 'regs unit 'e*) +(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*) val _ = Define ` - ((write_mem_eaS:'a sail_values$Bitvector_class -> sail_instr_kinds$write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail_values_Bitvector_a write_kind addr sz= (bindS -(maybe_failS "unsigned" ( + ((write_mem_eaS:'a Bitvector_class -> write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail_values_Bitvector_a write_kind addr sz= (bindS + (maybe_failS "unsigned" ( dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . let sz = (int_of_num sz) in updateS (\ s . ( s with<| write_ea := (SOME (write_kind, addr, sz)) |>)))))`; (* Write little-endian list of bytes to previously announced address *) -(*val write_mem_bytesS : forall 'regs 'e. list Sail_values.memory_byte -> monadS 'regs bool 'e*) +(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*) val _ = Define ` - ((write_mem_bytesS:((sail_values$bitU)list)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) v= (bindS -(readS (\ s . s.write_ea)) (\x . + ((write_mem_bytesS:((bitU)list)list -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) v= (bindS + (readS (\ s . s.write_ea)) (\x . (case x of NONE => failS "write ea has not been announced yet" | SOME (_, addr, sz) => @@ -245,25 +245,25 @@ val _ = Define ` (*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) val _ = Define ` - ((write_mem_valS:'a sail_values$Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a v= ((case mem_bytes_of_bits + ((write_mem_valS:'a Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a v= ((case mem_bytes_of_bits dict_Sail_values_Bitvector_a v of SOME v => write_mem_bytesS v | NONE => failS "write_mem_val" )))`; -(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> Sail_values.bitU -> monadS 'regs bool 'e*) +(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*) val _ = Define ` - ((write_tagS:'a sail_values$Bitvector_class -> 'a -> sail_values$bitU ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a addr t= (bindS -(maybe_failS "unsigned" ( - dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . seqS -(updateS (\ s . ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>))) -(returnS T))))`; + ((write_tagS:'a Bitvector_class -> 'a -> bitU ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a addr t= (bindS + (maybe_failS "unsigned" ( + dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . seqS + (updateS (\ s . ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>))) + (returnS T))))`; -(*val read_regS : forall 'regs 'rv 'a 'e. Sail_values.register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*) +(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*) val _ = Define ` - ((read_regS:('regs,'rv,'a)sail_values$register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg= (readS (\ s . reg.read_from s.regstate)))`; + ((read_regS:('regs,'rv,'a)register_ref -> 'regs sequential_state ->(('a,'e)result#'regs sequential_state)set) reg= (readS (\ s . reg.read_from s.regstate)))`; (* TODO @@ -281,10 +281,10 @@ let read_reg_bitfield reg regfield = read_reg_bit reg i *) (*val read_regvalS : forall 'regs 'rv 'e. - Sail_values.register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*) + register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*) val _ = Define ` - ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg= (bindS -(readS (\ s . read reg s.regstate)) (\x . + ((read_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'regs sequential_state ->(('rv,'e)result#'regs sequential_state)set) (read, _) reg= (bindS + (readS (\ s . read reg s.regstate)) (\x . (case x of SOME v => returnS v | NONE => failS ( STRCAT "read_regvalS " reg) @@ -292,20 +292,20 @@ val _ = Define ` (*val write_regvalS : forall 'regs 'rv 'e. - Sail_values.register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*) + register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*) val _ = Define ` - ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v= (bindS -(readS (\ s . write reg v s.regstate)) (\x . + ((write_regvalS:(string -> 'regs -> 'rv option)#(string -> 'rv -> 'regs -> 'regs option) -> string -> 'rv -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) (_, write) reg v= (bindS + (readS (\ s . write reg v s.regstate)) (\x . (case x of SOME rs' => updateS (\ s . ( s with<| regstate := rs' |>)) | NONE => failS ( STRCAT "write_regvalS " reg) ))))`; -(*val write_regS : forall 'regs 'rv 'a 'e. Sail_values.register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*) +(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*) val _ = Define ` - ((write_regS:('regs,'rv,'a)sail_values$register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v= - (updateS (\ s . ( s with<| regstate := (reg.write_to v s.regstate) |>))))`; + ((write_regS:('regs,'rv,'a)register_ref -> 'a -> 'regs sequential_state ->(((unit),'e)result#'regs sequential_state)set) reg v= + (updateS (\ s . ( s with<| regstate := (reg.write_to v s.regstate) |>))))`; (* TODO @@ -344,5 +344,24 @@ let update_reg_field_bit regfield i reg_val bit = let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in regfield.set_field reg_val new_field_value let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*) + +(* TODO Add Show typeclass for value and exception type *) +(*val show_result : forall 'a 'e. result 'a 'e -> string*) +val _ = Define ` + ((show_result:('a,'e)result -> string)= + (\x . (case x of + Value _ => "Value ()" + | Ex (Failure msg) => STRCAT "Failure " msg + | Ex (Throw _) => "Throw" + )))`; + + +(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*) +val _ = Define ` + ((prerr_results:(('a,'e)result#'s)set -> unit) rs= + (let _ = (IMAGE (\p . + (case (p ) of ( (r, _) ) => let _ = (prerr_endline (show_result r)) in () )) rs) in + () ))`; + val _ = export_theory() diff --git a/snapshots/hol4/sail/riscv/Holmakefile b/snapshots/hol4/sail/riscv/Holmakefile index 626e6f2f..8269bc36 100644 --- a/snapshots/hol4/sail/riscv/Holmakefile +++ b/snapshots/hol4/sail/riscv/Holmakefile @@ -2,7 +2,7 @@ LEMDIR=../../lem/hol-lib INCLUDES = $(LEMDIR) ../lib/hol -all: riscv_sequentialTheory.uo +all: riscvTheory.uo .PHONY: all ifdef POLY diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml index 463da979..160f550f 100644 --- a/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml +++ b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml @@ -1,6 +1,6 @@ -(*Generated by Lem from riscv_sequential.lem.*) +(*Generated by Lem from riscv.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory riscv_sequentialTheory; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory riscvTheory; val _ = numLib.prefer_num(); @@ -8,7 +8,7 @@ val _ = numLib.prefer_num(); open lemLib; (* val _ = lemLib.run_interactive := true; *) -val _ = new_theory "riscv_sequentialAuxiliary" +val _ = new_theory "riscvAuxiliary" (****************************************************) diff --git a/snapshots/hol4/sail/riscv/riscvScript.sml b/snapshots/hol4/sail/riscv/riscvScript.sml new file mode 100644 index 00000000..e8514af3 --- /dev/null +++ b/snapshots/hol4/sail/riscv/riscvScript.sml @@ -0,0 +1,7912 @@ +(*Generated by Lem from riscv.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "riscv" + +(*Generated by Sail from riscv.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import Riscv_types*) +(*open import Riscv_extras*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) + +val _ = Define ` + ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1= ((get_slice_int0 n m o1 : 'n words$word)))`; + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +val _ = Define ` + ((cast_unit_vec0:bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) + +val _ = Define ` + ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (state_monad$seqS + (write_ram (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr data) + (state_monad$returnS T)))`; + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) + +val _ = Define ` + ((RISCV_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= (state_monad$bindS + (read_ram (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__0 : 'int8_times_n words$word) . + state_monad$returnS (SOME w__0))))`; + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val ex_nat : ii -> integer*) + +val _ = Define ` + ((ex_nat:int -> int) n= n)`; + + +(*val ex_int : ii -> integer*) + +val _ = Define ` + ((ex_int:int -> int) n= n)`; + + +(*val coerce_int_nat : ii -> M ii*) + +val _ = Define ` + ((coerce_int_nat:int ->(regstate)state_monad$sequential_state ->(((int),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) x= (state_monad$seqS (state_monad$assert_expS T "") (state_monad$returnS x)))`; + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((EXTS:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend v m__tv : 'm words$word)))`; + + +val _ = Define ` + ((EXTZ:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend v m__tv : 'm words$word)))`; + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +val _ = Define ` + ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) >= ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) < ((lem$w2ui y))))`; + + +val _ = Define ` + ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) >= ((lem$w2ui y))))`; + + +val _ = Define ` + ((zopz0zIzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) <= ((lem$w2ui y))))`; + + +(*val bool_to_bits : bool -> mword ty1*) + +val _ = Define ` + ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val bit_to_bool : bitU -> bool*) + +val _ = Define ` + ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; + + +(*val vector64 : ii -> mword ty64*) + +val _ = Define ` + ((vector64:int ->(64)words$word) n= ((get_slice_int0 (( 64 : int):ii) n (( 0 : int):ii) : 64 words$word)))`; + + +(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) + +val _ = Define ` + ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int0 l n (( 0 : int):ii) : 'l words$word)))`; + + +(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) + +val _ = Define ` + ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 bits) (shift : 6 bits)= + (let (v128 : 128 bits) = ((EXTS (( 128 : int):ii) v : 128 words$word)) in + (subrange_vec_dec ((shift_bits_right v128 shift : 128 words$word)) (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) + +val _ = Define ` + ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 bits) (shift : 5 bits)= + (let (v64 : 64 bits) = ((EXTS (( 64 : int):ii) v : 64 words$word)) in + (subrange_vec_dec ((shift_bits_right v64 shift : 64 words$word)) (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; + + +val _ = Define ` + ((xlen:int)= ((( 64 : int):ii)))`; + + +val _ = Define ` + ((xlen_max_unsigned:int)= (((pow2 xlen)) - (( 1 : int):ii)))`; + + +val _ = Define ` + ((xlen_max_signed:int)= (((pow2 ((xlen - (( 1 : int):ii))))) - (( 1 : int):ii)))`; + + +val _ = Define ` + ((xlen_min_signed:int)= ((( 0 : int):ii) - ((pow2 ((xlen - (( 1 : int):ii)))))))`; + + +(*val regbits_to_regno : mword ty5 -> integer*) + +val _ = Define ` + ((regbits_to_regno:(5)words$word -> int) b= + (let r = (lem$w2ui b) in + r))`; + + +(*val creg2reg_bits : mword ty3 -> mword ty5*) + +val _ = Define ` + ((creg2reg_bits:(3)words$word ->(5)words$word) creg= ((concat_vec (vec_of_bits [B0;B1] : 2 words$word) creg : 5 words$word)))`; + + +val _ = Define ` +((zreg:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((ra:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))`; + + +val _ = Define ` +((sp:(5)words$word)= ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))`; + + +(*val rX : integer -> M (mword ty64)*) + +val _ = Define ` + ((rX:int ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) l__81= + (if (((l__81 = (( 0 : int):ii)))) then + state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else state_monad$bindS + (state_monad$read_regS Xs_ref) (\ (w__0 : xlenbits list) . + state_monad$returnS ((access_list_dec w__0 l__81 : 64 words$word)))))`; + + +(*val wX : integer -> mword ty64 -> M unit*) + +val _ = Define ` + ((wX:int ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r v= + (if (((r <> (( 0 : int):ii)))) then state_monad$bindS + (state_monad$read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) . state_monad$seqS + (state_monad$write_regS Xs_ref ((update_list_dec w__0 r v : ( 64 words$word) list))) + (state_monad$returnS ((prerr_endline + ((STRCAT "x" + ((STRCAT ((stringFromInteger r)) + ((STRCAT " <- " ((string_of_vec v)))))))))))) + else state_monad$returnS () ))`; + + +(*val reg_name_abi : mword ty5 -> string*) + +val _ = Define ` + ((reg_name_abi:(5)words$word -> string) r= + (let b__0 = r in + if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then + "zero" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then + "ra" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then + "sp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then + "gp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + "tp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then + "t0" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then + "t1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then + "t2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + "fp" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then + "s1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then + "a0" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then + "a1" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + "a2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then + "a3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then + "a4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then + "a5" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + "a6" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then + "a7" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then + "s2" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then + "s3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + "s4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then + "s5" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then + "s6" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then + "s7" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + "s8" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then + "s9" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then + "s10" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then + "s11" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then + "t3" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then + "t4" + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then + "t5" + else "t6"))`; + + +(*val Architecture_of_num : integer -> Architecture*) + +val _ = Define ` + ((Architecture_of_num:int -> Architecture) arg_= + (let l__79 = arg_ in + if (((l__79 = (( 0 : int):ii)))) then RV32 + else if (((l__79 = (( 1 : int):ii)))) then RV64 + else RV128))`; + + +(*val num_of_Architecture : Architecture -> integer*) + +val _ = Define ` + ((num_of_Architecture:Architecture -> int) arg_= + ((case arg_ of RV32 => (( 0 : int):ii) | RV64 => (( 1 : int):ii) | RV128 => (( 2 : int):ii) )))`; + + +(*val architecture : mword ty2 -> maybe Architecture*) + +val _ = Define ` + ((architecture:(2)words$word ->(Architecture)option) a= + (let b__0 = a in + if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then SOME RV32 + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then SOME RV64 + else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then SOME RV128 + else NONE))`; + + +(*val arch_to_bits : Architecture -> mword ty2*) + +val _ = Define ` + ((arch_to_bits:Architecture ->(2)words$word) a= + ((case a of + RV32 => (vec_of_bits [B0;B1] : 2 words$word) + | RV64 => (vec_of_bits [B1;B0] : 2 words$word) + | RV128 => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val Privilege_of_num : integer -> Privilege*) + +val _ = Define ` + ((Privilege_of_num:int -> Privilege) arg_= + (let l__77 = arg_ in + if (((l__77 = (( 0 : int):ii)))) then User + else if (((l__77 = (( 1 : int):ii)))) then Supervisor + else Machine))`; + + +(*val num_of_Privilege : Privilege -> integer*) + +val _ = Define ` + ((num_of_Privilege:Privilege -> int) arg_= + ((case arg_ of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Machine => (( 2 : int):ii) )))`; + + +(*val privLevel_to_bits : Privilege -> mword ty2*) + +val _ = Define ` + ((privLevel_to_bits:Privilege ->(2)words$word) p= + ((case p of + User => (vec_of_bits [B0;B0] : 2 words$word) + | Supervisor => (vec_of_bits [B0;B1] : 2 words$word) + | Machine => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val privLevel_of_bits : mword ty2 -> Privilege*) + +val _ = Define ` + ((privLevel_of_bits:(2)words$word -> Privilege) p= + (let b__0 = p in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then User + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor + else Machine))`; + + +(*val privLevel_to_str : Privilege -> string*) + +val _ = Define ` + ((privLevel_to_str:Privilege -> string) p= ((case p of User => "U" | Supervisor => "S" | Machine => "M" )))`; + + +(*val AccessType_of_num : integer -> AccessType*) + +val _ = Define ` + ((AccessType_of_num:int -> AccessType) arg_= + (let l__74 = arg_ in + if (((l__74 = (( 0 : int):ii)))) then Read + else if (((l__74 = (( 1 : int):ii)))) then Write + else if (((l__74 = (( 2 : int):ii)))) then ReadWrite + else Execute))`; + + +(*val num_of_AccessType : AccessType -> integer*) + +val _ = Define ` + ((num_of_AccessType:AccessType -> int) arg_= + ((case arg_ of Read => (( 0 : int):ii) | Write => (( 1 : int):ii) | ReadWrite => (( 2 : int):ii) | Execute => (( 3 : int):ii) )))`; + + +(*val ReadType_of_num : integer -> ReadType*) + +val _ = Define ` + ((ReadType_of_num:int -> ReadType) arg_= + (let l__73 = arg_ in + if (((l__73 = (( 0 : int):ii)))) then Instruction + else Data))`; + + +(*val num_of_ReadType : ReadType -> integer*) + +val _ = Define ` + ((num_of_ReadType:ReadType -> int) arg_= ((case arg_ of Instruction => (( 0 : int):ii) | Data => (( 1 : int):ii) )))`; + + +(*val ExceptionType_of_num : integer -> ExceptionType*) + +val _ = Define ` + ((ExceptionType_of_num:int -> ExceptionType) arg_= + (let l__58 = arg_ in + if (((l__58 = (( 0 : int):ii)))) then E_Fetch_Addr_Align + else if (((l__58 = (( 1 : int):ii)))) then E_Fetch_Access_Fault + else if (((l__58 = (( 2 : int):ii)))) then E_Illegal_Instr + else if (((l__58 = (( 3 : int):ii)))) then E_Breakpoint + else if (((l__58 = (( 4 : int):ii)))) then E_Load_Addr_Align + else if (((l__58 = (( 5 : int):ii)))) then E_Load_Access_Fault + else if (((l__58 = (( 6 : int):ii)))) then E_SAMO_Addr_Align + else if (((l__58 = (( 7 : int):ii)))) then E_SAMO_Access_Fault + else if (((l__58 = (( 8 : int):ii)))) then E_U_EnvCall + else if (((l__58 = (( 9 : int):ii)))) then E_S_EnvCall + else if (((l__58 = (( 10 : int):ii)))) then E_Reserved_10 + else if (((l__58 = (( 11 : int):ii)))) then E_M_EnvCall + else if (((l__58 = (( 12 : int):ii)))) then E_Fetch_Page_Fault + else if (((l__58 = (( 13 : int):ii)))) then E_Load_Page_Fault + else if (((l__58 = (( 14 : int):ii)))) then E_Reserved_14 + else E_SAMO_Page_Fault))`; + + +(*val num_of_ExceptionType : ExceptionType -> integer*) + +val _ = Define ` + ((num_of_ExceptionType:ExceptionType -> int) arg_= + ((case arg_ of + E_Fetch_Addr_Align => (( 0 : int):ii) + | E_Fetch_Access_Fault => (( 1 : int):ii) + | E_Illegal_Instr => (( 2 : int):ii) + | E_Breakpoint => (( 3 : int):ii) + | E_Load_Addr_Align => (( 4 : int):ii) + | E_Load_Access_Fault => (( 5 : int):ii) + | E_SAMO_Addr_Align => (( 6 : int):ii) + | E_SAMO_Access_Fault => (( 7 : int):ii) + | E_U_EnvCall => (( 8 : int):ii) + | E_S_EnvCall => (( 9 : int):ii) + | E_Reserved_10 => (( 10 : int):ii) + | E_M_EnvCall => (( 11 : int):ii) + | E_Fetch_Page_Fault => (( 12 : int):ii) + | E_Load_Page_Fault => (( 13 : int):ii) + | E_Reserved_14 => (( 14 : int):ii) + | E_SAMO_Page_Fault => (( 15 : int):ii) + )))`; + + +(*val exceptionType_to_bits : ExceptionType -> mword ty4*) + +val _ = Define ` + ((exceptionType_to_bits:ExceptionType ->(4)words$word) e= + ((case e of + E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : 4 words$word) + | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : 4 words$word) + | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : 4 words$word) + | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : 4 words$word) + | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : 4 words$word) + | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : 4 words$word) + )))`; + + +(*val exceptionType_to_str : ExceptionType -> string*) + +val _ = Define ` + ((exceptionType_to_str:ExceptionType -> string) e= + ((case e of + E_Fetch_Addr_Align => "fisaligned-fetch" + | E_Fetch_Access_Fault => "fetch-access-fault" + | E_Illegal_Instr => "illegal-instruction" + | E_Breakpoint => "breakpoint" + | E_Load_Addr_Align => "misaligned-load" + | E_Load_Access_Fault => "load-access-fault" + | E_SAMO_Addr_Align => "misaliged-store/amo" + | E_SAMO_Access_Fault => "store/amo-access-fault" + | E_U_EnvCall => "u-call" + | E_S_EnvCall => "s-call" + | E_Reserved_10 => "reserved-0" + | E_M_EnvCall => "m-call" + | E_Fetch_Page_Fault => "fetch-page-fault" + | E_Load_Page_Fault => "load-page-fault" + | E_Reserved_14 => "reserved-1" + | E_SAMO_Page_Fault => "store/amo-page-fault" + )))`; + + +(*val InterruptType_of_num : integer -> InterruptType*) + +val _ = Define ` + ((InterruptType_of_num:int -> InterruptType) arg_= + (let l__50 = arg_ in + if (((l__50 = (( 0 : int):ii)))) then I_U_Software + else if (((l__50 = (( 1 : int):ii)))) then I_S_Software + else if (((l__50 = (( 2 : int):ii)))) then I_M_Software + else if (((l__50 = (( 3 : int):ii)))) then I_U_Timer + else if (((l__50 = (( 4 : int):ii)))) then I_S_Timer + else if (((l__50 = (( 5 : int):ii)))) then I_M_Timer + else if (((l__50 = (( 6 : int):ii)))) then I_U_External + else if (((l__50 = (( 7 : int):ii)))) then I_S_External + else I_M_External))`; + + +(*val num_of_InterruptType : InterruptType -> integer*) + +val _ = Define ` + ((num_of_InterruptType:InterruptType -> int) arg_= + ((case arg_ of + I_U_Software => (( 0 : int):ii) + | I_S_Software => (( 1 : int):ii) + | I_M_Software => (( 2 : int):ii) + | I_U_Timer => (( 3 : int):ii) + | I_S_Timer => (( 4 : int):ii) + | I_M_Timer => (( 5 : int):ii) + | I_U_External => (( 6 : int):ii) + | I_S_External => (( 7 : int):ii) + | I_M_External => (( 8 : int):ii) + )))`; + + +(*val interruptType_to_bits : InterruptType -> mword ty4*) + +val _ = Define ` + ((interruptType_to_bits:InterruptType ->(4)words$word) i= + ((case i of + I_U_Software => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + | I_U_External => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + | I_S_External => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + | I_M_External => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + )))`; + + +(*val TrapVectorMode_of_num : integer -> TrapVectorMode*) + +val _ = Define ` + ((TrapVectorMode_of_num:int -> TrapVectorMode) arg_= + (let l__48 = arg_ in + if (((l__48 = (( 0 : int):ii)))) then TV_Direct + else if (((l__48 = (( 1 : int):ii)))) then TV_Vector + else TV_Reserved))`; + + +(*val num_of_TrapVectorMode : TrapVectorMode -> integer*) + +val _ = Define ` + ((num_of_TrapVectorMode:TrapVectorMode -> int) arg_= + ((case arg_ of TV_Direct => (( 0 : int):ii) | TV_Vector => (( 1 : int):ii) | TV_Reserved => (( 2 : int):ii) )))`; + + +(*val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode*) + +val _ = Define ` + ((trapVectorMode_of_bits:(2)words$word -> TrapVectorMode) m= + (let b__0 = m in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then TV_Direct + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then TV_Vector + else TV_Reserved))`; + + +(*val not_implemented : forall 'a. string -> M 'a*) + +val _ = Define ` + ((not_implemented:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) message= (state_monad$throwS (Error_not_implemented message)))`; + + +(*val internal_error : forall 'a. string -> M 'a*) + +val _ = Define ` + ((internal_error:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) s= (state_monad$seqS (state_monad$assert_expS F s) (state_monad$throwS (Error_internal_error () ))))`; + + +(*val ExtStatus_of_num : integer -> ExtStatus*) + +val _ = Define ` + ((ExtStatus_of_num:int -> ExtStatus) arg_= + (let l__45 = arg_ in + if (((l__45 = (( 0 : int):ii)))) then Off + else if (((l__45 = (( 1 : int):ii)))) then Initial + else if (((l__45 = (( 2 : int):ii)))) then Clean + else Dirty))`; + + +(*val num_of_ExtStatus : ExtStatus -> integer*) + +val _ = Define ` + ((num_of_ExtStatus:ExtStatus -> int) arg_= + ((case arg_ of Off => (( 0 : int):ii) | Initial => (( 1 : int):ii) | Clean => (( 2 : int):ii) | Dirty => (( 3 : int):ii) )))`; + + +(*val extStatus_to_bits : ExtStatus -> mword ty2*) + +val _ = Define ` + ((extStatus_to_bits:ExtStatus ->(2)words$word) e= + ((case e of + Off => (vec_of_bits [B0;B0] : 2 words$word) + | Initial => (vec_of_bits [B0;B1] : 2 words$word) + | Clean => (vec_of_bits [B1;B0] : 2 words$word) + | Dirty => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val extStatus_of_bits : mword ty2 -> ExtStatus*) + +val _ = Define ` + ((extStatus_of_bits:(2)words$word -> ExtStatus) e= + (let b__0 = e in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Off + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Initial + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then Clean + else Dirty))`; + + +(*val SATPMode_of_num : integer -> SATPMode*) + +val _ = Define ` + ((SATPMode_of_num:int -> SATPMode) arg_= + (let l__43 = arg_ in + if (((l__43 = (( 0 : int):ii)))) then Sbare + else if (((l__43 = (( 1 : int):ii)))) then Sv32 + else Sv39))`; + + +(*val num_of_SATPMode : SATPMode -> integer*) + +val _ = Define ` + ((num_of_SATPMode:SATPMode -> int) arg_= ((case arg_ of Sbare => (( 0 : int):ii) | Sv32 => (( 1 : int):ii) | Sv39 => (( 2 : int):ii) )))`; + + +(*val satpMode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*) + +val _ = Define ` + ((satpMode_of_bits:Architecture ->(4)words$word ->(SATPMode)option) (a : Architecture) (m : satp_mode)= + ((case (a, m) of (g__113, b__0) => SOME Sbare )))`; + + +(*val uop_of_num : integer -> uop*) + +val _ = Define ` + ((uop_of_num:int -> uop) arg_= + (let l__42 = arg_ in + if (((l__42 = (( 0 : int):ii)))) then RISCV_LUI + else RISCV_AUIPC))`; + + +(*val num_of_uop : uop -> integer*) + +val _ = Define ` + ((num_of_uop:uop -> int) arg_= ((case arg_ of RISCV_LUI => (( 0 : int):ii) | RISCV_AUIPC => (( 1 : int):ii) )))`; + + +(*val bop_of_num : integer -> bop*) + +val _ = Define ` + ((bop_of_num:int -> bop) arg_= + (let l__37 = arg_ in + if (((l__37 = (( 0 : int):ii)))) then RISCV_BEQ + else if (((l__37 = (( 1 : int):ii)))) then RISCV_BNE + else if (((l__37 = (( 2 : int):ii)))) then RISCV_BLT + else if (((l__37 = (( 3 : int):ii)))) then RISCV_BGE + else if (((l__37 = (( 4 : int):ii)))) then RISCV_BLTU + else RISCV_BGEU))`; + + +(*val num_of_bop : bop -> integer*) + +val _ = Define ` + ((num_of_bop:bop -> int) arg_= + ((case arg_ of + RISCV_BEQ => (( 0 : int):ii) + | RISCV_BNE => (( 1 : int):ii) + | RISCV_BLT => (( 2 : int):ii) + | RISCV_BGE => (( 3 : int):ii) + | RISCV_BLTU => (( 4 : int):ii) + | RISCV_BGEU => (( 5 : int):ii) + )))`; + + +(*val iop_of_num : integer -> iop*) + +val _ = Define ` + ((iop_of_num:int -> iop) arg_= + (let l__32 = arg_ in + if (((l__32 = (( 0 : int):ii)))) then RISCV_ADDI + else if (((l__32 = (( 1 : int):ii)))) then RISCV_SLTI + else if (((l__32 = (( 2 : int):ii)))) then RISCV_SLTIU + else if (((l__32 = (( 3 : int):ii)))) then RISCV_XORI + else if (((l__32 = (( 4 : int):ii)))) then RISCV_ORI + else RISCV_ANDI))`; + + +(*val num_of_iop : iop -> integer*) + +val _ = Define ` + ((num_of_iop:iop -> int) arg_= + ((case arg_ of + RISCV_ADDI => (( 0 : int):ii) + | RISCV_SLTI => (( 1 : int):ii) + | RISCV_SLTIU => (( 2 : int):ii) + | RISCV_XORI => (( 3 : int):ii) + | RISCV_ORI => (( 4 : int):ii) + | RISCV_ANDI => (( 5 : int):ii) + )))`; + + +(*val sop_of_num : integer -> sop*) + +val _ = Define ` + ((sop_of_num:int -> sop) arg_= + (let l__30 = arg_ in + if (((l__30 = (( 0 : int):ii)))) then RISCV_SLLI + else if (((l__30 = (( 1 : int):ii)))) then RISCV_SRLI + else RISCV_SRAI))`; + + +(*val num_of_sop : sop -> integer*) + +val _ = Define ` + ((num_of_sop:sop -> int) arg_= + ((case arg_ of RISCV_SLLI => (( 0 : int):ii) | RISCV_SRLI => (( 1 : int):ii) | RISCV_SRAI => (( 2 : int):ii) )))`; + + +(*val rop_of_num : integer -> rop*) + +val _ = Define ` + ((rop_of_num:int -> rop) arg_= + (let l__21 = arg_ in + if (((l__21 = (( 0 : int):ii)))) then RISCV_ADD + else if (((l__21 = (( 1 : int):ii)))) then RISCV_SUB + else if (((l__21 = (( 2 : int):ii)))) then RISCV_SLL + else if (((l__21 = (( 3 : int):ii)))) then RISCV_SLT + else if (((l__21 = (( 4 : int):ii)))) then RISCV_SLTU + else if (((l__21 = (( 5 : int):ii)))) then RISCV_XOR + else if (((l__21 = (( 6 : int):ii)))) then RISCV_SRL + else if (((l__21 = (( 7 : int):ii)))) then RISCV_SRA + else if (((l__21 = (( 8 : int):ii)))) then RISCV_OR + else RISCV_AND))`; + + +(*val num_of_rop : rop -> integer*) + +val _ = Define ` + ((num_of_rop:rop -> int) arg_= + ((case arg_ of + RISCV_ADD => (( 0 : int):ii) + | RISCV_SUB => (( 1 : int):ii) + | RISCV_SLL => (( 2 : int):ii) + | RISCV_SLT => (( 3 : int):ii) + | RISCV_SLTU => (( 4 : int):ii) + | RISCV_XOR => (( 5 : int):ii) + | RISCV_SRL => (( 6 : int):ii) + | RISCV_SRA => (( 7 : int):ii) + | RISCV_OR => (( 8 : int):ii) + | RISCV_AND => (( 9 : int):ii) + )))`; + + +(*val ropw_of_num : integer -> ropw*) + +val _ = Define ` + ((ropw_of_num:int -> ropw) arg_= + (let l__17 = arg_ in + if (((l__17 = (( 0 : int):ii)))) then RISCV_ADDW + else if (((l__17 = (( 1 : int):ii)))) then RISCV_SUBW + else if (((l__17 = (( 2 : int):ii)))) then RISCV_SLLW + else if (((l__17 = (( 3 : int):ii)))) then RISCV_SRLW + else RISCV_SRAW))`; + + +(*val num_of_ropw : ropw -> integer*) + +val _ = Define ` + ((num_of_ropw:ropw -> int) arg_= + ((case arg_ of + RISCV_ADDW => (( 0 : int):ii) + | RISCV_SUBW => (( 1 : int):ii) + | RISCV_SLLW => (( 2 : int):ii) + | RISCV_SRLW => (( 3 : int):ii) + | RISCV_SRAW => (( 4 : int):ii) + )))`; + + +(*val amoop_of_num : integer -> amoop*) + +val _ = Define ` + ((amoop_of_num:int -> amoop) arg_= + (let l__9 = arg_ in + if (((l__9 = (( 0 : int):ii)))) then AMOSWAP + else if (((l__9 = (( 1 : int):ii)))) then AMOADD + else if (((l__9 = (( 2 : int):ii)))) then AMOXOR + else if (((l__9 = (( 3 : int):ii)))) then AMOAND + else if (((l__9 = (( 4 : int):ii)))) then AMOOR + else if (((l__9 = (( 5 : int):ii)))) then AMOMIN + else if (((l__9 = (( 6 : int):ii)))) then AMOMAX + else if (((l__9 = (( 7 : int):ii)))) then AMOMINU + else AMOMAXU))`; + + +(*val num_of_amoop : amoop -> integer*) + +val _ = Define ` + ((num_of_amoop:amoop -> int) arg_= + ((case arg_ of + AMOSWAP => (( 0 : int):ii) + | AMOADD => (( 1 : int):ii) + | AMOXOR => (( 2 : int):ii) + | AMOAND => (( 3 : int):ii) + | AMOOR => (( 4 : int):ii) + | AMOMIN => (( 5 : int):ii) + | AMOMAX => (( 6 : int):ii) + | AMOMINU => (( 7 : int):ii) + | AMOMAXU => (( 8 : int):ii) + )))`; + + +(*val csrop_of_num : integer -> csrop*) + +val _ = Define ` + ((csrop_of_num:int -> csrop) arg_= + (let l__7 = arg_ in + if (((l__7 = (( 0 : int):ii)))) then CSRRW + else if (((l__7 = (( 1 : int):ii)))) then CSRRS + else CSRRC))`; + + +(*val num_of_csrop : csrop -> integer*) + +val _ = Define ` + ((num_of_csrop:csrop -> int) arg_= ((case arg_ of CSRRW => (( 0 : int):ii) | CSRRS => (( 1 : int):ii) | CSRRC => (( 2 : int):ii) )))`; + + +(*val word_width_of_num : integer -> word_width*) + +val _ = Define ` + ((word_width_of_num:int -> word_width) arg_= + (let l__4 = arg_ in + if (((l__4 = (( 0 : int):ii)))) then BYTE + else if (((l__4 = (( 1 : int):ii)))) then HALF + else if (((l__4 = (( 2 : int):ii)))) then WORD + else DOUBLE))`; + + +(*val num_of_word_width : word_width -> integer*) + +val _ = Define ` + ((num_of_word_width:word_width -> int) arg_= + ((case arg_ of BYTE => (( 0 : int):ii) | HALF => (( 1 : int):ii) | WORD => (( 2 : int):ii) | DOUBLE => (( 3 : int):ii) )))`; + + +(*val is_aligned_addr : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):ii)))`; + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((checked_mem_read:ReadType ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int)= (state_monad$bindS + (RISCV_read addr width : ( ( 'int8_times_n words$word)option) M) (\ (w__0 : + ( 'int8_times_n words$word)option) . + state_monad$returnS ((case (t, w__0) of + (Instruction, NONE) => MemException E_Fetch_Access_Fault + | (Data, NONE) => MemException E_Load_Access_Fault + | (_, SOME (v)) => MemValue v + )))))`; + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((MEMr:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl res= + (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then + state_monad$returnS (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (F, F, F) => (MEMr addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (T, F, F) => (MEMr_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, F, T) => + (MEMr_reserved addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (T, F, T) => + (MEMr_reserved_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, T, F) => state_monad$throwS (Error_not_implemented "load.rl") + | (T, T, F) => + (MEMr_strong_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, T, T) => state_monad$throwS (Error_not_implemented "lr.rl") + | (T, T, T) => + (MEMr_reserved_strong_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + )))`; + + +(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + state_monad$returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => state_monad$seqS (MEMea addr width) (state_monad$returnS (MemValue () )) + | (F, T, F) => state_monad$seqS (MEMea_release addr width) (state_monad$returnS (MemValue () )) + | (F, F, T) => state_monad$seqS (MEMea_conditional addr width) (state_monad$returnS (MemValue () )) + | (F, T, T) => state_monad$seqS (MEMea_conditional_release addr width) (state_monad$returnS (MemValue () )) + | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq") + | (T, T, F) => state_monad$seqS (MEMea_strong_release addr width) (state_monad$returnS (MemValue () )) + | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq") + | (T, T, T) => state_monad$seqS (MEMea_conditional_strong_release addr width) (state_monad$returnS (MemValue () )) + )))`; + + +(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)= (state_monad$bindS + (RISCV_write addr width data) (\ (w__0 : bool) . + state_monad$returnS (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault))))`; + + +(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width value aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + state_monad$returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => MEMval addr width value + | (F, T, F) => MEMval_release addr width value + | (F, F, T) => MEMval_conditional addr width value + | (F, T, T) => MEMval_conditional_release addr width value + | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq") + | (T, T, F) => MEMval_strong_release addr width value + | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq") + | (T, T, T) => MEMval_conditional_strong_release addr width value + )))`; + + +(*val _get_Misa : Misa -> mword ty64*) + +val _ = Define ` + ((get_Misa:Misa ->(64)words$word) (Mk_Misa (v))= v)`; + + +(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Misa:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Misa v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_SV39_PTE : SV39_PTE -> mword ty64*) + +(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) + +(*val _get_Misa_MXL : Misa -> mword ty2*) + +val _ = Define ` + ((get_Misa_MXL:Misa ->(2)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; + + +(*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*) + +val _ = Define ` + ((update_Misa_MXL:Misa ->(2)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_Z : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_Z:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 25 : int):ii) (( 25 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Z : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_Z:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_Y : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_Y:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 24 : int):ii) (( 24 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Y : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_Y:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_X : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_X:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_X : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_X:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_X : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_W : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_W:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_W : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_W:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_W : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_V : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_V:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_V : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_V:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_V : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_U : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_U:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_U : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_U:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_U : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_T : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_T:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_T : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_T:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_S : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_S:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_S : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_S:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_R : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_R:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_R : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_R:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_R : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_Q : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_Q:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 16 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_Q : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_Q:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_P : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_P:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_P : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_P:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_O : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_O:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 14 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_O : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_O:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_N : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_N:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_N : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_N:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_M : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_M:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_M : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_M:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_L : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_L:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_L : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_L:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_K : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_K:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_K : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_K:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_J : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_J:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_J : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_J:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_I : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_I:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_I : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_I:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_H : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_H:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_H : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_H:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_G : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_G:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_G : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_G:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_G : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_F : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_F:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_F : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_F:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_E : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_E:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_E : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_E:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_D : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_D:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_D : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_D:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_D : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_C : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_C:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_C : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_C:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_B : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_B:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_B : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_B:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +(*val _get_Misa_A : Misa -> mword ty1*) + +val _ = Define ` + ((get_Misa_A:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Misa) . + let r = ((get_Misa w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Misa r))))`; + + +(*val _update_Misa_A : Misa -> mword ty1 -> Misa*) + +val _ = Define ` + ((update_Misa_A:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= + (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_A : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val legalize_misa : Misa -> mword ty64 -> Misa*) + +val _ = Define ` + ((legalize_misa:Misa ->(64)words$word -> Misa) (m : Misa) (v : xlenbits)= m)`; + + +(*val _get_Mstatus : Mstatus -> mword ty64*) + +val _ = Define ` + ((get_Mstatus:Mstatus ->(64)words$word) (Mk_Mstatus (v))= v)`; + + +(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Mstatus:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Mstatus v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_Mstatus_SD : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_SD:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SD : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SXL : Mstatus -> mword ty2*) + +val _ = Define ` + ((get_Mstatus_SXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii) : 2 words$word)))`; + + +(*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 34 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_UXL : Mstatus -> mword ty2*) + +val _ = Define ` + ((get_Mstatus_UXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; + + +(*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mstatus_UXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_UXL : Sstatus -> mword ty2*) + +(*val _set_Sstatus_UXL : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_TSR : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_TSR:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_TW : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_TW:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_TVM : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_TVM:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_MXR : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_MXR:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_MXR : Sstatus -> mword ty1*) + +(*val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SUM : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_SUM:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SUM : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPRV : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_MPRV:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_XS : Mstatus -> mword ty2*) + +val _ = Define ` + ((get_Mstatus_XS:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; + + +(*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_XS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_FS : Mstatus -> mword ty2*) + +val _ = Define ` + ((get_Mstatus_FS:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; + + +(*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_FS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_MPP : Mstatus -> mword ty2*) + +val _ = Define ` + ((get_Mstatus_MPP:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)))`; + + +(*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 11 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SPP : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_SPP:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPP : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_MPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SPIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_SPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UPIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_UPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_MIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mstatus_SIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_SIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UIE : Mstatus -> mword ty1*) + +val _ = Define ` + ((get_Mstatus_UIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . + let r = ((get_Mstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mstatus r))))`; + + +(*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= + (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val legalize_mstatus : Mstatus -> mword ty64 -> Mstatus*) + +val _ = Define ` + ((legalize_mstatus:Mstatus ->(64)words$word -> Mstatus) (o1 : Mstatus) (v : xlenbits)= + (let (m : Mstatus) = (Mk_Mstatus v) in + let m = (update_Mstatus_XS m ((extStatus_to_bits Off : 2 words$word))) in + let m = + (update_Mstatus_SD m + ((bool_to_bits + ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m : 2 words$word)))) + : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word))))) \/ (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m : 2 words$word)))) + : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) + : 1 words$word))) in + let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1 : 2 words$word))) in + let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1 : 2 words$word))) in + let m = (update_Mstatus_UPIE m ((bool_to_bits F : 1 words$word))) in + update_Mstatus_UIE m ((bool_to_bits F : 1 words$word))))`; + + +(*val cur_Architecture : unit -> M Architecture*) + +val _ = Define ` + ((cur_Architecture:unit ->(regstate)state_monad$sequential_state ->(((Architecture),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS + (case w__0 of + Machine => state_monad$bindS + (state_monad$read_regS misa_ref) (\ (w__1 : Misa) . state_monad$returnS ((get_Misa_MXL w__1 : 2 words$word))) + | Supervisor => state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . state_monad$returnS ((get_Mstatus_SXL w__2 : 2 words$word))) + | User => state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . state_monad$returnS ((get_Mstatus_UXL w__3 : 2 words$word))) + ) (\ (a : arch_xlen) . + (case ((architecture a)) of + SOME (a) => state_monad$returnS a + | NONE => internal_error "Invalid current architecture" + )))))`; + + +(*val in32BitMode : unit -> M bool*) + +val _ = Define ` + ((in32BitMode:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) . state_monad$returnS (((w__0 = RV32))))))`; + + +(*val haveAtomics : unit -> M bool*) + +val _ = Define ` + ((haveAtomics:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + state_monad$returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveRVC : unit -> M bool*) + +val _ = Define ` + ((haveRVC:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveMulDiv : unit -> M bool*) + +val _ = Define ` + ((haveMulDiv:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + state_monad$returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + + +(*val haveFP : unit -> M bool*) + +val _ = Define ` + ((haveFP:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (state$or_boolS + ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + state_monad$returnS (((((get_Misa_F w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__1 : Misa) . + state_monad$returnS (((((get_Misa_D w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))))`; + + +(*val _get_Minterrupts : Minterrupts -> mword ty64*) + +val _ = Define ` + ((get_Minterrupts:Minterrupts ->(64)words$word) (Mk_Minterrupts (v))= v)`; + + +(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Minterrupts:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Minterrupts v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_STI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_STI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_STI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +(*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_USI : Minterrupts -> mword ty1*) + +val _ = Define ` + ((get_Minterrupts_USI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . + let r = ((get_Minterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + + +(*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*) + +val _ = Define ` + ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= + (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_USI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val legalize_mip : Minterrupts -> mword ty64 -> Minterrupts*) + +val _ = Define ` + ((legalize_mip:Minterrupts ->(64)words$word -> Minterrupts) (o1 : Minterrupts) (v : xlenbits)= + (let v = (Mk_Minterrupts v) in + let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v : 1 words$word))) in + let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; + + +(*val legalize_mie : Minterrupts -> mword ty64 -> Minterrupts*) + +val _ = Define ` + ((legalize_mie:Minterrupts ->(64)words$word -> Minterrupts) (o1 : Minterrupts) (v : xlenbits)= + (let v = (Mk_Minterrupts v) in + let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v : 1 words$word))) in + let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v : 1 words$word))) in + let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v : 1 words$word))) in + let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v : 1 words$word))) in + let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; + + +(*val legalize_mideleg : Minterrupts -> mword ty64 -> Minterrupts*) + +val _ = Define ` + ((legalize_mideleg:Minterrupts ->(64)words$word -> Minterrupts) (o1 : Minterrupts) (v : xlenbits)= + (let m = (Mk_Minterrupts v) in + let m = (update_Minterrupts_MEI m ((bool_to_bits F : 1 words$word))) in + let m = (update_Minterrupts_MTI m ((bool_to_bits F : 1 words$word))) in + update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`; + + +(*val _get_Medeleg : Medeleg -> mword ty64*) + +val _ = Define ` + ((get_Medeleg:Medeleg ->(64)words$word) (Mk_Medeleg (v))= v)`; + + +(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Medeleg:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Medeleg v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + + +(*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= + ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*) + +val _ = Define ` + ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . + let r = ((get_Medeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Medeleg r))))`; + + +(*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= + (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val legalize_medeleg : Medeleg -> mword ty64 -> Medeleg*) + +val _ = Define ` + ((legalize_medeleg:Medeleg ->(64)words$word -> Medeleg) (o1 : Medeleg) (v : xlenbits)= + (let m = (Mk_Medeleg v) in + update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`; + + +(*val _get_Mtvec : Mtvec -> mword ty64*) + +val _ = Define ` + ((get_Mtvec:Mtvec ->(64)words$word) (Mk_Mtvec (v))= v)`; + + +(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Mtvec:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Mtvec v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_Mtvec_Base : Mtvec -> mword ty62*) + +val _ = Define ` + ((get_Mtvec_Base:Mtvec ->(62)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)))`; + + +(*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*) + +val _ = Define ` + ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . + let r = ((get_Mtvec w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 2 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mtvec r))))`; + + +(*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*) + +val _ = Define ` + ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) (Mk_Mtvec (v)) x= + (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mtvec_Mode : Mtvec -> mword ty2*) + +val _ = Define ` + ((get_Mtvec_Mode:Mtvec ->(2)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)))`; + + +(*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . + let r = ((get_Mtvec w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mtvec r))))`; + + +(*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*) + +val _ = Define ` + ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) (Mk_Mtvec (v)) x= + (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*) + +(*val _get_Satp64_Mode : Satp64 -> mword ty4*) + +(*val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit*) + +(*val legalize_tvec : Mtvec -> mword ty64 -> Mtvec*) + +val _ = Define ` + ((legalize_tvec:Mtvec ->(64)words$word -> Mtvec) (o1 : Mtvec) (v : xlenbits)= + (let v = (Mk_Mtvec v) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v : 2 words$word)))) of + TV_Direct => v + | TV_Vector => v + | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 : 2 words$word)) + )))`; + + +(*val _get_Mcause : Mcause -> mword ty64*) + +val _ = Define ` + ((get_Mcause:Mcause ->(64)words$word) (Mk_Mcause (v))= v)`; + + +(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Mcause:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Mcause v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*) + +val _ = Define ` + ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . + let r = ((get_Mcause w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mcause r))))`; + + +(*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*) + +val _ = Define ` + ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) (Mk_Mcause (v)) x= + (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + + +(*val _get_Mcause_Cause : Mcause -> mword ty63*) + +val _ = Define ` + ((get_Mcause_Cause:Mcause ->(63)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)))`; + + +(*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*) + +val _ = Define ` + ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . + let r = ((get_Mcause w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Mcause r))))`; + + +(*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*) + +val _ = Define ` + ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) (Mk_Mcause (v)) x= + (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*) + +val _ = Define ` + ((tvec_addr:Mtvec -> Mcause ->((64)words$word)option) (m : Mtvec) (c : Mcause)= + (let (base : xlenbits) = + ((concat_vec ((get_Mtvec_Base m : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m : 2 words$word)))) of + TV_Direct => SOME base + | TV_Vector => + if (((((get_Mcause_IsInterrupt c : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME ((add_vec base + ((shift_bits_left + ((EXTZ (( 64 : int):ii) ((get_Mcause_Cause c : 63 words$word)) : 64 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 64 words$word)) + : 64 words$word)) + else SOME base + | TV_Reserved => NONE + )))`; + + +(*val legalize_xepc : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((legalize_xepc:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) v= (state_monad$bindS + (haveRVC () ) (\ (w__0 : bool) . + state_monad$returnS ((and_vec v + ((EXTS (( 64 : int):ii) + (if w__0 then (vec_of_bits [B1;B1;B0] : 3 words$word) + else (vec_of_bits [B1;B0;B0] : 3 words$word)) + : 64 words$word)) + : 64 words$word)))))`; + + +(*val _get_Sstatus : Sstatus -> mword ty64*) + +val _ = Define ` + ((get_Sstatus:Sstatus ->(64)words$word) (Mk_Sstatus (v))= v)`; + + +(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Sstatus:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Sstatus v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sstatus_SD:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UXL:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UXL:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_MXR:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SUM:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_XS:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_FS:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SPP:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_SIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sstatus_UIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . + let r = ((get_Sstatus w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sstatus r))))`; + + +val _ = Define ` + ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= + (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val lower_mstatus : Mstatus -> Sstatus*) + +val _ = Define ` + ((lower_mstatus:Mstatus -> Sstatus) m= + (let s = (Mk_Sstatus ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = (update_Sstatus_SD s ((get_Mstatus_SD m : 1 words$word))) in + let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m : 2 words$word))) in + let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m : 1 words$word))) in + let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m : 1 words$word))) in + let s = (update_Sstatus_XS s ((get_Mstatus_XS m : 2 words$word))) in + let s = (update_Sstatus_FS s ((get_Mstatus_FS m : 2 words$word))) in + let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m : 1 words$word))) in + let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m : 1 words$word))) in + let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m : 1 words$word))) in + let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m : 1 words$word))) in + update_Sstatus_UIE s ((get_Mstatus_UIE m : 1 words$word))))`; + + +(*val lift_sstatus : Mstatus -> Sstatus -> Mstatus*) + +val _ = Define ` + ((lift_sstatus:Mstatus -> Sstatus -> Mstatus) (m : Mstatus) (s : Sstatus)= + (let m = (update_Mstatus_SD m ((get_Sstatus_SD s : 1 words$word))) in + let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s : 2 words$word))) in + let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in + let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in + let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in + let m = (update_Mstatus_FS m ((get_Sstatus_FS s : 2 words$word))) in + let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s : 1 words$word))) in + let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s : 1 words$word))) in + let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s : 1 words$word))) in + let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s : 1 words$word))) in + update_Mstatus_UIE m ((get_Sstatus_UIE s : 1 words$word))))`; + + +(*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*) + +val _ = Define ` + ((legalize_sstatus:Mstatus ->(64)words$word -> Mstatus) (m : Mstatus) (v : xlenbits)= (lift_sstatus m (Mk_Sstatus v)))`; + + +(*val _get_Sedeleg : Sedeleg -> mword ty64*) + +val _ = Define ` + ((get_Sedeleg:Sedeleg ->(64)words$word) (Mk_Sedeleg (v))= v)`; + + +(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Sedeleg:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Sedeleg v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= + ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . + let r = ((get_Sedeleg w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + + +val _ = Define ` + ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= + (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*) + +val _ = Define ` + ((legalize_sedeleg:Sedeleg ->(64)words$word -> Sedeleg) (s : Sedeleg) (v : xlenbits)= + (Mk_Sedeleg ((EXTZ (( 64 : int):ii) ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word)) : 64 words$word))))`; + + +(*val _get_Sinterrupts : Sinterrupts -> mword ty64*) + +val _ = Define ` + ((get_Sinterrupts:Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))= v)`; + + +(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Sinterrupts:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Sinterrupts v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + + +val _ = Define ` + ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . + let r = ((get_Sinterrupts w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + + +val _ = Define ` + ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= + (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*) + +val _ = Define ` + ((lower_mip:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)= + (let (s : Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) + : 1 words$word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts*) + +val _ = Define ` + ((lower_mie:Minterrupts -> Minterrupts -> Sinterrupts) (m : Minterrupts) (d : Minterrupts)= + (let (s : Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in + let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) + : 1 words$word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +val _ = Define ` + ((lift_sip:Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)= + (let (m : Minterrupts) = o1 in + let m = + (update_Minterrupts_SSI m + ((and_vec ((get_Sinterrupts_SSI s : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) + : 1 words$word))) in + let m = + (update_Minterrupts_UEI m + ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) + : 1 words$word))) in + update_Minterrupts_USI m + ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) + : 1 words$word))))`; + + +(*val legalize_sip : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +val _ = Define ` + ((legalize_sip:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)= + (lift_sip m d (Mk_Sinterrupts v)))`; + + +(*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +val _ = Define ` + ((lift_sie:Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts) (o1 : Minterrupts) (d : Minterrupts) (s : Sinterrupts)= + (let (m : Minterrupts) = o1 in + let m = + (if (((((get_Minterrupts_SEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_SEI m ((get_Sinterrupts_SEI s : 1 words$word)) + else m) in + let m = + (if (((((get_Minterrupts_STI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_STI m ((get_Sinterrupts_STI s : 1 words$word)) + else m) in + let m = + (if (((((get_Minterrupts_SSI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_SSI m ((get_Sinterrupts_SSI s : 1 words$word)) + else m) in + let m = + (if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word)) + else m) in + let m = + (if (((((get_Minterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_UTI m ((get_Sinterrupts_UTI s : 1 words$word)) + else m) in + if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word)) + else m))`; + + +(*val legalize_sie : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +val _ = Define ` + ((legalize_sie:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)= + (lift_sie m d (Mk_Sinterrupts v)))`; + + +(*val _get_Satp64 : Satp64 -> mword ty64*) + +val _ = Define ` + ((get_Satp64:Satp64 ->(64)words$word) (Mk_Satp64 (v))= v)`; + + +(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Satp64:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_Satp64 v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_Satp64_Mode:Satp64 ->(4)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii) : 4 words$word)))`; + + +val _ = Define ` + ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 60 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Satp64 r))))`; + + +val _ = Define ` + ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii) x : 64 words$word))))`; + + +(*val _get_Satp64_Asid : Satp64 -> mword ty16*) + +val _ = Define ` + ((get_Satp64_Asid:Satp64 ->(16)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii) : 16 words$word)))`; + + +(*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*) + +val _ = Define ` + ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 44 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Satp64 r))))`; + + +(*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*) + +val _ = Define ` + ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii) x : 64 words$word))))`; + + +(*val _get_Satp64_PPN : Satp64 -> mword ty44*) + +val _ = Define ` + ((get_Satp64_PPN:Satp64 ->(44)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)))`; + + +(*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*) + +val _ = Define ` + ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . + let r = ((get_Satp64 w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 43 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_Satp64 r))))`; + + +(*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*) + +val _ = Define ` + ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) (Mk_Satp64 (v)) x= + (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*) + +val _ = Define ` + ((legalize_satp:Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : Architecture) (o1 : xlenbits) (v : xlenbits)= + (let s = (Mk_Satp64 v) in + (case ((satpMode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of + NONE => o1 + | SOME (Sv32) => o1 + | SOME (_) => (get_Satp64 s : 64 words$word) + )))`; + + +(*val csr_name : mword ty12 -> string*) + +val _ = Define ` + ((csr_name:(12)words$word -> string) csr= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "ustatus" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "uie" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "utvec" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "fflags" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "frm" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "fcsr" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycle" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "time" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instret" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycleh" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "timeh" + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instreth" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sstatus" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "sedeleg" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "sideleg" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sie" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "stvec" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "scounteren" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sscratch" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "sepc" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "scause" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "stval" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sip" + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "satp" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + "mvendorid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + "marchid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + "mimpid" + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + "mhartid" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mstatus" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "misa" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "medeleg" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mideleg" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mie" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "mtvec" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "mcounteren" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mscratch" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "mepc" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "mcause" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mtval" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mip" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycle" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstret" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycleh" + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstreth" + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + "tselect" + else "UNKNOWN"))`; + + +(*val csrAccess : mword ty12 -> mword ty2*) + +val _ = Define ` + ((csrAccess:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)))`; + + +(*val csrPriv : mword ty12 -> mword ty2*) + +val _ = Define ` + ((csrPriv:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`; + + +(*val is_CSR_defined : mword ty12 -> Privilege -> bool*) + +val _ = Define ` + ((is_CSR_defined:(12)words$word -> Privilege -> bool) (csr : 12 bits) (p : Privilege)= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else F))`; + + +(*val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool*) + +val _ = Define ` + ((check_CSR_access:(2)words$word ->(2)words$word -> Privilege -> bool -> bool) csrrw csrpr p isWrite= + (((~ ((((((((bool_to_bits isWrite : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((csrrw = (vec_of_bits [B1;B1] : 2 words$word))))))))) /\ ((zopz0zKzJ_u ((privLevel_to_bits p : 2 words$word)) csrpr))))`; + + +(*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*) + +val _ = Define ` + ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (state_monad$bindS + (state$and_boolS + (state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word))))) + (state$and_boolS + (state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + state_monad$returnS (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ (w__2 : + bool) . + state_monad$returnS ((~ w__2)))))`; + + +(*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*) + +val _ = Define ` + ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)= + (state$and_boolS (state_monad$returnS ((is_CSR_defined csr p))) + (state$and_boolS + (state_monad$returnS ((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p + isWrite))) ((check_TVM_SATP csr p)))))`; + + +(*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*) + +val _ = Define ` + ((exception_delegatee:ExceptionType -> Privilege ->(regstate)state_monad$sequential_state ->(((Privilege),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)= + (let idx = (num_of_ExceptionType e) in state_monad$bindS + (state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) . + let super = (access_vec_dec ((get_Medeleg w__0 : 64 words$word)) idx) in state_monad$bindS + (state_monad$read_regS sedeleg_ref) (\ (w__1 : Sedeleg) . + let user = (access_vec_dec ((get_Sedeleg w__1 : 64 words$word)) idx) in state_monad$bindS + (state$and_boolS + ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__2 : Misa) . + state_monad$returnS (((((get_Misa_S w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + (state_monad$returnS ((bit_to_bool super)))) (\ (w__3 : bool) . + let deleg = (if w__3 then Supervisor else Machine) in + state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg : 2 words$word)) + ((privLevel_to_bits p : 2 words$word)))) then + p + else deleg))))))`; + + +(*val findPendingInterrupt : mword ty64 -> maybe InterruptType*) + +val _ = Define ` + ((findPendingInterrupt:(64)words$word ->(InterruptType)option) ip= + (let ip = (Mk_Minterrupts ip) in + if (((((get_Minterrupts_MEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + SOME I_M_External + else if (((((get_Minterrupts_MSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_M_Software + else if (((((get_Minterrupts_MTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_M_Timer + else if (((((get_Minterrupts_SEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_External + else if (((((get_Minterrupts_SSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_Software + else if (((((get_Minterrupts_STI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_S_Timer + else if (((((get_Minterrupts_UEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_External + else if (((((get_Minterrupts_USI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_Software + else if (((((get_Minterrupts_UTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + SOME I_U_Timer + else NONE))`; + + +(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) + +val _ = Define ` + ((curInterrupt:Minterrupts -> Minterrupts -> Minterrupts ->(regstate)state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts)= + (let (en_mip : xlenbits) = + ((and_vec ((get_Minterrupts pend : 64 words$word)) ((get_Minterrupts enbl : 64 words$word)) + : 64 words$word)) in + if (((en_mip = ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) then + state_monad$returnS NONE + else + let eff_mip = + ((and_vec en_mip ((not_vec ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) + : 64 words$word)) in + let eff_sip = ((and_vec en_mip ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) in state_monad$bindS + (state$and_boolS + ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + state_monad$returnS (((((get_Mstatus_MIE w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + (state_monad$returnS (((eff_mip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))))) (\ (w__1 : + bool) . + if w__1 then + state_monad$returnS ((case ((findPendingInterrupt eff_mip)) of + SOME (i) => + let r = (i, Machine) in + SOME r + | NONE => NONE + )) + else state_monad$bindS + (state$and_boolS + ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + state_monad$returnS (((((get_Mstatus_SIE w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + (state$and_boolS + (state_monad$returnS (((eff_sip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))) + (state$or_boolS + ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__3 : Privilege) . + state_monad$returnS (((((privLevel_to_bits w__3 : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))) + ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__4 : Privilege) . + state_monad$returnS (((((privLevel_to_bits w__4 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))))))) (\ (w__7 : bool) . + state_monad$returnS (if w__7 then + (case ((findPendingInterrupt eff_sip)) of + SOME (i) => + let r = (i, Supervisor) in + SOME r + | NONE => NONE + ) + else NONE)))))`; + + +(*val tval : maybe (mword ty64) -> mword ty64*) + +val _ = Define ` + ((tval:((64)words$word)option ->(64)words$word) excinfo= + ((case excinfo of + SOME (e) => e + | NONE => (EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word) + )))`; + + +(*val handle_trap : Privilege -> bool -> mword ty4 -> mword ty64 -> maybe (mword ty64) -> M (mword ty64)*) + +val _ = Define ` + ((handle_trap:Privilege -> bool ->(4)words$word ->(64)words$word ->(xlenbits)option ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info : + xlenbits option)= + (let (_ : unit) = + (prerr_endline + ((STRCAT "handling " + ((STRCAT (if intr then "int#" else "exc#") + ((STRCAT ((string_of_vec c)) + ((STRCAT " at priv " + ((STRCAT ((privLevel_to_str del_priv)) + ((STRCAT " with tval " + ((string_of_vec ((tval info : 64 words$word))))))))))))))))) in + (case del_priv of + Machine => state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word))) + (set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word)))) + (state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word))) + (set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word)))) + (state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word))) + (state_monad$write_regS mtval_ref ((tval info : 64 words$word)))) + (state_monad$write_regS mepc_ref pc)) + (state_monad$write_regS cur_privilege_ref del_priv)) + (state_monad$read_regS mtvec_ref)) (\ (w__2 : Mtvec) . state_monad$bindS + (state_monad$read_regS mcause_ref) (\ (w__3 : Mcause) . + (case ((tvec_addr w__2 w__3 : ( 64 words$word)option)) of + SOME (epc) => state_monad$returnS epc + | NONE => (internal_error "Invalid mtvec mode" : ( 64 words$word) M) + ))))) + | Supervisor => state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))) + (set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word)))) + (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word))) + (set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word)))) + (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . state_monad$bindS + (case w__7 of + User => state_monad$returnS ((bool_to_bits F : 1 words$word)) + | Supervisor => state_monad$returnS ((bool_to_bits T : 1 words$word)) + | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) M) + ) (\ (w__9 : 1 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (set_Mstatus_SPP mstatus_ref w__9) + (state_monad$write_regS stval_ref ((tval info : 64 words$word)))) + (state_monad$write_regS sepc_ref pc)) + (state_monad$write_regS cur_privilege_ref del_priv)) + (state_monad$read_regS stvec_ref)) (\ (w__10 : Mtvec) . state_monad$bindS + (state_monad$read_regS scause_ref) (\ (w__11 : Mcause) . + (case ((tvec_addr w__10 w__11 : ( 64 words$word)option)) of + SOME (epc) => state_monad$returnS epc + | NONE => (internal_error "Invalid stvec mode" : ( 64 words$word) M) + )))))) + | User => (internal_error "the N extension is currently unsupported" : ( 64 words$word) M) + )))`; + + +(*val handle_exception : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((handle_exception:Privilege -> ctl_result ->(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)= + ((case (cur_priv, ctl) of + (_, CTL_TRAP (e)) => state_monad$bindS + (exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . + let (_ : unit) = + (prerr_endline + ((STRCAT "trapping from " + ((STRCAT ((privLevel_to_str cur_priv)) + ((STRCAT " to " + ((STRCAT ((privLevel_to_str del_priv)) + ((STRCAT " to handle " + ((exceptionType_to_str e.sync_exception_trap))))))))))))) in + (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap : 4 words$word)) pc + e.sync_exception_excinfo + : ( 64 words$word) M)) + | (_, CTL_MRET (_)) => state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ prev_priv . state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word))) + (set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) + (state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) + (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User : 2 words$word)))) + (state_monad$read_regS cur_privilege_ref)) (\ (w__3 : Privilege) . + let (_ : unit) = + (prerr_endline + ((STRCAT "ret-ing from " + ((STRCAT ((privLevel_to_str prev_priv)) + ((STRCAT " to " ((privLevel_to_str w__3))))))))) in + (state_monad$read_regS mepc_ref : ( 64 words$word) M))))) + | (_, CTL_SRET (_)) => state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ prev_priv . state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 : 1 words$word))) + (set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) + (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS + cur_privilege_ref + (if (((((get_Mstatus_SPP w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + Supervisor + else User)) + (set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word)))) + (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . + let (_ : unit) = + (prerr_endline + ((STRCAT "ret-ing from " + ((STRCAT ((privLevel_to_str prev_priv)) + ((STRCAT " to " ((privLevel_to_str w__7))))))))) in + (state_monad$read_regS sepc_ref : ( 64 words$word) M))))) + )))`; + + +(*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*) + +val _ = Define ` + ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)= + (let (t : sync_exception) = (<| sync_exception_trap := e; sync_exception_excinfo := (SOME addr) |>) in state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . + state_monad$write_regS nextPC_ref w__2)))))`; + + +(*val handle_decode_exception : mword ty64 -> M unit*) + +val _ = Define ` + ((handle_decode_exception:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) instbits= + (let (t : sync_exception) = + (<| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := (SOME instbits) |>) in state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . + state_monad$write_regS nextPC_ref w__2)))))`; + + +(*val handle_interrupt : InterruptType -> Privilege -> M unit*) + +val _ = Define ` + ((handle_interrupt:InterruptType -> Privilege ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + (handle_trap del_priv T ((interruptType_to_bits i : 4 words$word)) w__0 NONE + : ( 64 words$word) M) (\ (w__1 : xlenbits) . + state_monad$write_regS nextPC_ref w__1))))`; + + +(*val handle_illegal : unit -> M unit*) + +val _ = Define ` + ((handle_illegal:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + (let (t : sync_exception) = + (<| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := NONE |>) in state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . + state_monad$write_regS nextPC_ref w__2)))))`; + + +(*val init_sys : unit -> M unit*) + +val _ = Define ` + ((init_sys:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (state_monad$write_regS cur_privilege_ref Machine) + (set_Misa_MXL misa_ref ((arch_to_bits RV64 : 2 words$word)))) + (set_Misa_C misa_ref ((bool_to_bits T : 1 words$word)))) + (set_Misa_U misa_ref ((bool_to_bits T : 1 words$word)))) + (set_Misa_S misa_ref ((bool_to_bits T : 1 words$word)))) + (state_monad$read_regS misa_ref)) (\ (w__0 : Misa) . state_monad$bindS (state_monad$seqS + (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 : 2 words$word))) + (state_monad$read_regS misa_ref)) (\ (w__1 : Misa) . state_monad$seqS (state_monad$seqS + (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 : 2 words$word))) + (set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word)))) + (state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))`; + + +(*val tick_clock : unit -> M unit*) + +val _ = Define ` + ((tick_clock:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii) : 64 words$word)))))`; + + +val _ = Define ` + ((PAGESIZE_BITS:int)= ((( 12 : int):ii)))`; + + +(*val _get_PTE_Bits : PTE_Bits -> mword ty8*) + +val _ = Define ` + ((get_PTE_Bits:PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))= v)`; + + +(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_PTE_Bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_PTE_Bits v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 8 words$word))))`; + + +val _ = Define ` + ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . + let r = ((get_PTE_Bits w__0 : 8 words$word)) in + let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 8 words$word)) in + state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + + +val _ = Define ` + ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= + (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 8 words$word))))`; + + +(*val isPTEPtr : mword ty8 -> bool*) + +val _ = Define ` + ((isPTEPtr:(8)words$word -> bool) p= + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; + + +(*val isInvalidPTE : mword ty8 -> bool*) + +val _ = Define ` + ((isInvalidPTE:(8)words$word -> bool) p= + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_V a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; + + +(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*) + +val _ = Define ` + ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : + PTE_Bits)= + ((case (ac, priv) of + (Read, User) => + state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + | (Write, User) => + state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (ReadWrite, User) => + state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + | (Execute, User) => + state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (Read, Supervisor) => + state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + | (Write, Supervisor) => + state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (ReadWrite, Supervisor) => + state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + | (Execute, Supervisor) => + state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + | (_, Machine) => internal_error "m-mode mem perm check" + )))`; + + +(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*) + +val _ = Define ` + ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)= + (let update_d = + (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in + let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in + if (((update_d \/ update_a))) then + let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in + let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T : 1 words$word)) else np) in + SOME np + else NONE))`; + + +(*val PTW_Error_of_num : integer -> PTW_Error*) + +val _ = Define ` + ((PTW_Error_of_num:int -> PTW_Error) arg_= + (let l__0 = arg_ in + if (((l__0 = (( 0 : int):ii)))) then PTW_Access + else if (((l__0 = (( 1 : int):ii)))) then PTW_Invalid_PTE + else if (((l__0 = (( 2 : int):ii)))) then PTW_No_Permission + else if (((l__0 = (( 3 : int):ii)))) then PTW_Misaligned + else PTW_PTE_Update))`; + + +(*val num_of_PTW_Error : PTW_Error -> integer*) + +val _ = Define ` + ((num_of_PTW_Error:PTW_Error -> int) arg_= + ((case arg_ of + PTW_Access => (( 0 : int):ii) + | PTW_Invalid_PTE => (( 1 : int):ii) + | PTW_No_Permission => (( 2 : int):ii) + | PTW_Misaligned => (( 3 : int):ii) + | PTW_PTE_Update => (( 4 : int):ii) + )))`; + + +(*val translationException : AccessType -> PTW_Error -> ExceptionType*) + +val _ = Define ` + ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)= + ((case (a, f) of + (Read, PTW_Access) => E_Load_Access_Fault + | (Read, _) => E_Load_Page_Fault + | (Write, PTW_Access) => E_SAMO_Access_Fault + | (Write, _) => E_SAMO_Page_Fault + | (Fetch, PTW_Access) => E_Fetch_Access_Fault + | (Fetch, _) => E_Fetch_Page_Fault + )))`; + + +val _ = Define ` + ((SV39_LEVEL_BITS:int)= ((( 9 : int):ii)))`; + + +val _ = Define ` + ((SV39_LEVELS:int)= ((( 3 : int):ii)))`; + + +val _ = Define ` + ((PTE39_LOG_SIZE:int)= ((( 3 : int):ii)))`; + + +val _ = Define ` + ((PTE39_SIZE:int)= ((( 8 : int):ii)))`; + + +(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*) + +val _ = Define ` + ((get_SV39_Vaddr:SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))= v)`; + + +(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) + +val _ = Define ` + ((set_SV39_Vaddr:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_SV39_Vaddr v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*) + +val _ = Define ` + ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`; + + +(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . + let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in + let r = ((update_subrange_vec_dec r (( 38 : int):ii) (( 12 : int):ii) v : 39 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`; + + +(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*) + +val _ = Define ` + ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= + (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii) x : 39 words$word))))`; + + +(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*) + +val _ = Define ` + ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; + + +(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*) + +val _ = Define ` + ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . + let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v : 39 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`; + + +(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*) + +val _ = Define ` + ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= + (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x : 39 words$word))))`; + + +(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*) + +(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*) + +(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*) + +(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*) + +val _ = Define ` + ((get_SV39_Paddr:SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))= v)`; + + +(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) + +val _ = Define ` + ((set_SV39_Paddr:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_SV39_Paddr v) in + state_monad$write_regS r_ref r)))`; + + +(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*) + +val _ = Define ` + ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`; + + +(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*) + +val _ = Define ` + ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . + let r = ((get_SV39_Paddr w__0 : 56 words$word)) in + let r = ((update_subrange_vec_dec r (( 55 : int):ii) (( 12 : int):ii) v : 56 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`; + + +(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*) + +val _ = Define ` + ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x= + (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii) x : 56 words$word))))`; + + +(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*) + +(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*) + +(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*) + +val _ = Define ` + ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; + + +val _ = Define ` + ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . + let r = ((get_SV39_Paddr w__0 : 56 words$word)) in + let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v : 56 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`; + + +val _ = Define ` + ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x= + (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x : 56 words$word))))`; + + +val _ = Define ` + ((get_SV39_PTE:SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))= v)`; + + +val _ = Define ` + ((set_SV39_PTE:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ r . + let r = (Mk_SV39_PTE v) in + state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`; + + +val _ = Define ` + ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 53 : int):ii) (( 10 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + + +val _ = Define ` + ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + + +(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*) + +val _ = Define ` + ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`; + + +(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 8 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + + +(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*) + +val _ = Define ` + ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + + +(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*) + +val _ = Define ` + ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS + (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . + let r = ((get_SV39_PTE w__0 : 64 words$word)) in + let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 64 words$word)) in + state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + + +(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*) + +val _ = Define ` + ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= + (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + + +(*val curAsid64 : unit -> M (mword ty16)*) + +val _ = Define ` + ((curAsid64:unit ->(regstate)state_monad$sequential_state ->((((16)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let satp64 = (Mk_Satp64 w__0) in + state_monad$returnS ((get_Satp64_Asid satp64 : 16 words$word)))))`; + + +(*val curPTB39 : unit -> M (mword ty56)*) + +val _ = Define ` + ((curPTB39:unit ->(regstate)state_monad$sequential_state ->((((56)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let satp64 = (Mk_Satp64 w__0) in + state_monad$returnS ((EXTZ (( 56 : int):ii) + ((shiftl ((get_Satp64_PPN satp64 : 44 words$word)) PAGESIZE_BITS : 44 words$word)) + : 56 words$word)))))`; + + +(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*) + + val walk39_defn = Hol_defn "walk39" ` + ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((PTW_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global= + (let va = (Mk_SV39_Vaddr vaddr) in + let (pt_ofs : paddr39) = + ((shiftl + ((EXTZ (( 56 : int):ii) + ((subrange_vec_dec + ((shiftr ((get_SV39_Vaddr_VPNi va : 27 words$word)) + ((level * SV39_LEVEL_BITS)) + : 27 words$word)) ((SV39_LEVEL_BITS - (( 1 : int):ii))) (( 0 : int):ii) + : 9 words$word)) + : 56 words$word)) PTE39_LOG_SIZE + : 56 words$word)) in + let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in state_monad$bindS + (checked_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr : 64 words$word)) (( 8 : int):ii) + : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) . + (case w__0 of + MemException (_) => state_monad$returnS (PTW_Failure PTW_Access) + | MemValue (v) => + let pte = (Mk_SV39_PTE v) in + let pbits = ((get_SV39_PTE_BITS pte : 8 words$word)) in + let pattr = (Mk_PTE_Bits pbits) in + let is_global = + (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in + if ((isInvalidPTE pbits)) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE) + else if ((isPTEPtr pbits)) then + if (((level = (( 0 : int):ii)))) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE) + else + walk39 vaddr ac priv mxr do_sum + ((EXTZ (( 56 : int):ii) + ((shiftl ((get_SV39_PTE_PPNi pte : 44 words$word)) PAGESIZE_BITS : 44 words$word)) + : 56 words$word)) ((level - (( 1 : int):ii))) is_global + else state_monad$bindS + (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) . + state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission + else if ((level > (( 0 : int):ii))) then + let mask = + ((sub_vec_int + ((shiftl + ((xor_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((xor_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((EXTZ (( 44 : int):ii) (vec_of_bits [B1] : 1 words$word) : 44 words$word)) + : 44 words$word)) + : 44 words$word)) ((level * SV39_LEVEL_BITS)) + : 44 words$word)) (( 1 : int):ii) + : 44 words$word)) in + if (((((and_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) mask : 44 words$word)) <> ((EXTZ (( 44 : int):ii) (vec_of_bits [B0] : 1 words$word) : 44 words$word))))) then + PTW_Failure PTW_Misaligned + else + let ppn = + ((or_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((and_vec + ((EXTZ (( 44 : int):ii) ((get_SV39_Vaddr_VPNi va : 27 words$word)) : 44 words$word)) + mask + : 44 words$word)) + : 44 words$word)) in + PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va : 12 words$word)) + : 56 words$word),pte,pte_addr,level,is_global) + else + PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) + ((get_SV39_Vaddr_PgOfs va : 12 words$word)) + : 56 words$word),pte,pte_addr,level,is_global))) + ))))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn; + +(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*) + +val _ = Define ` + ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> SV39_PTE -> int ->(56)words$word ->(regstate)state_monad$sequential_state ->(((TLB39_Entry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr= + (let (shift : ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in + let (vAddrMask : vaddr39) = + ((sub_vec_int + ((shiftl + ((xor_vec vAddr + ((xor_vec vAddr ((EXTZ (( 39 : int):ii) (vec_of_bits [B1] : 1 words$word) : 39 words$word)) + : 39 words$word)) + : 39 words$word)) shift + : 39 words$word)) (( 1 : int):ii) + : 39 words$word)) in + let (vMatchMask : vaddr39) = ((not_vec vAddrMask : 39 words$word)) in state_monad$bindS + (state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + state_monad$returnS (<| TLB39_Entry_asid := asid; + TLB39_Entry_global := global; + TLB39_Entry_pte := pte; + TLB39_Entry_pteAddr := pteAddr; + TLB39_Entry_vAddrMask := vAddrMask; + TLB39_Entry_vMatchMask := vMatchMask; + TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask : 39 words$word)); + TLB39_Entry_pAddr := + ((shiftl ((shiftr pAddr shift : 56 words$word)) shift : 56 words$word)); + TLB39_Entry_age := w__0 |>))))`; + + +val _ = Define ` + ((TLBEntries:int)= ((( 32 : int):ii)))`; + + +(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*) + +val _ = Define ` + ((lookupTLB39:(16)words$word ->(39)words$word ->(regstate)state_monad$sequential_state ->((((int#TLB39_Entry)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vaddr= (state_monad$bindS + (state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . + state_monad$returnS ((case w__0 of + NONE => NONE + | SOME (e) => + if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr : 39 words$word)))))))) + then + SOME ((( 0 : int):ii), e) + else NONE + )))))`; + + +(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*) + +val _ = Define ` + ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (state_monad$bindS + (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . + state_monad$write_regS tlb39_ref (SOME ent))))`; + + +(*val writeTLB39 : ii -> TLB39_Entry -> M unit*) + +val _ = Define ` + ((writeTLB39:int -> TLB39_Entry ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)= (state_monad$write_regS tlb39_ref (SOME ent)))`; + + +(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*) + +val _ = Define ` + ((flushTLB:((16)words$word)option ->((39)words$word)option ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid addr= (state_monad$bindS + (state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . + let (ent : TLB39_Entry option) = + ((case (w__0, asid, addr) of + (NONE, _, _) => NONE + | (SOME (e), NONE, NONE) => NONE + | (SOME (e), NONE, SOME (a)) => + if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a : 39 words$word))))) then + NONE + else SOME e + | (SOME (e), SOME (i), NONE) => + if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE + else SOME e + | (SOME (e), SOME (i), SOME (a)) => + if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask : 39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then + NONE + else SOME e + )) in + state_monad$write_regS tlb39_ref ent)))`; + + +val _ = Define ` + ((enable_dirty_update:bool)= F)`; + + +(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*) + +val _ = Define ` + ((translate39:(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)state_monad$sequential_state ->(((TR39_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac priv mxr do_sum level= (state_monad$bindS + (curAsid64 () : ( 16 words$word) M) (\ asid . state_monad$bindS + (lookupTLB39 asid vAddr) (\ (w__0 : ((ii # TLB39_Entry))option) . + (case w__0 of + SOME (idx,ent) => + let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte : 8 words$word))) in state_monad$bindS + (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) . + if ((~ w__1)) then state_monad$returnS (TR39_Failure PTW_No_Permission) + else + (case ((update_PTE_Bits pteBits ac)) of + NONE => + state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + ((EXTZ (( 56 : int):ii) + ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) + : 56 words$word)) + : 56 words$word))) + | SOME (pbits) => + if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update) + else + let (n_ent : TLB39_Entry) = ent in + let n_ent = + ((n_ent with<| + TLB39_Entry_pte := + ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits : 8 words$word))))|>)) in state_monad$bindS (state_monad$seqS + (writeTLB39 idx n_ent) + (checked_mem_write ((EXTZ (( 64 : int):ii) ent.TLB39_Entry_pteAddr : 64 words$word)) (( 8 : int):ii) + ((get_SV39_PTE ent.TLB39_Entry_pte : 64 words$word)))) (\ (w__2 : unit + MemoryOpResult) . state_monad$seqS + (case w__2 of + MemValue (_) => state_monad$returnS () + | MemException (e) => internal_error "invalid physical address in TLB" + ) + (state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + ((EXTZ (( 56 : int):ii) + ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) + : 56 words$word)) + : 56 words$word))))) + )) + | NONE => state_monad$bindS + (curPTB39 () : ( 56 words$word) M) (\ (w__6 : 56 words$word) . state_monad$bindS + (walk39 vAddr ac priv mxr do_sum w__6 level F) (\ (w__7 : PTW_Result) . + (case w__7 of + PTW_Failure (f) => state_monad$returnS (TR39_Failure f) + | PTW_Success (pAddr,pte,pteAddr,level,global) => + (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word))) ac)) of + NONE => state_monad$seqS + (addToTLB39 asid vAddr pAddr pte pteAddr level global) (state_monad$returnS (TR39_Address pAddr)) + | SOME (pbits) => + if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update) + else + let (w_pte : SV39_PTE) = + (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits : 8 words$word))) in state_monad$bindS + (checked_mem_write ((EXTZ (( 64 : int):ii) pteAddr : 64 words$word)) (( 8 : int):ii) + ((get_SV39_PTE w_pte : 64 words$word))) (\ (w__8 : unit MemoryOpResult) . + (case w__8 of + MemValue (_) => state_monad$seqS + (addToTLB39 asid vAddr pAddr w_pte pteAddr level global) + (state_monad$returnS (TR39_Address pAddr)) + | MemException (e) => state_monad$returnS (TR39_Failure PTW_Access) + )) + ) + ))) + )))))`; + + +(*val translationMode : Privilege -> M SATPMode*) + +val _ = Define ` + ((translationMode:Privilege ->(regstate)state_monad$sequential_state ->(((SATPMode),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) priv= + (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) + then + state_monad$returnS Sbare + else state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + let arch = (architecture ((get_Mstatus_SXL w__0 : 2 words$word))) in + (case arch of + SOME (RV64) => state_monad$bindS + (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (mbits : satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) : 4 words$word)) in + (case ((satpMode_of_bits RV64 mbits)) of + SOME (m) => state_monad$returnS m + | NONE => internal_error "invalid RV64 translation mode in satp" + )) + | _ => internal_error "unsupported address translation arch" + ))))`; + + +(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*) + +val _ = Define ` + ((translateAddr:(64)words$word -> AccessType -> ReadType ->(regstate)state_monad$sequential_state ->(((TR_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac rt= (state_monad$bindS + (case rt of + Instruction => state_monad$read_regS cur_privilege_ref + | Data => state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + if (((((get_Mstatus_MPRV w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + state_monad$returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) + else state_monad$read_regS cur_privilege_ref) + ) (\ (effPriv : Privilege) . state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . + let (mxr : bool) = + (((get_Mstatus_MXR w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) . + let (do_sum : bool) = + (((get_Mstatus_SUM w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in state_monad$bindS + (translationMode effPriv) (\ (mode : SATPMode) . + (case mode of + Sbare => state_monad$returnS (TR_Address vAddr) + | SV39 => state_monad$bindS + (translate39 + ((subrange_vec_dec vAddr (( 38 : int): ii) + (( 0 : int): ii) : 39 words$word)) ac effPriv + mxr do_sum ((SV39_LEVELS - (( 1 : int): ii)))) + (\ (w__7 : TR39_Result) . + state_monad$returnS + ((case w__7 of + TR39_Address (pa) => TR_Address + ((EXTZ (( 64 : int): ii) pa : 64 words$word)) + | TR39_Failure (f) => TR_Failure + ((translationException ac f)) + ))) + )))))))`; + + +(*val decode : mword ty32 -> maybe ast*) + +(*val decodeCompressed : mword ty16 -> maybe ast*) + +(*val execute : ast -> M unit*) + +(*val print_insn : ast -> string*) + +(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*) + +val _ = Define ` + ((extend_value:bool ->('int8_times_n words$word)MemoryOpResult ->((64)words$word)MemoryOpResult) is_unsigned value= + ((case value of + MemValue (v) => + MemValue (if is_unsigned then (EXTZ (( 64 : int):ii) v : 64 words$word) + else (EXTS (( 64 : int):ii) v : 64 words$word)) + | MemException (e) => MemException e + )))`; + + +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*) + +val _ = Define ` + ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd addr value is_unsigned= + ((case ((extend_value is_unsigned value : ( 64 words$word) MemoryOpResult)) of + MemValue (result) => wX ((regbits_to_regno rd)) result + | MemException (e) => handle_mem_exception addr e + )))`; + + +(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*) + +(*val readCSR : mword ty12 -> M (mword ty64)*) + +val _ = Define ` + ((readCSR:(12)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr= + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + (state_monad$read_regS mvendorid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + (state_monad$read_regS marchid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + (state_monad$read_regS mimpid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + (state_monad$read_regS mhartid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . state_monad$returnS ((get_Mstatus w__4 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS misa_ref) (\ (w__5 : Misa) . state_monad$returnS ((get_Misa w__5 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . state_monad$returnS ((get_Medeleg w__6 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . + state_monad$returnS ((get_Minterrupts w__7 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) . state_monad$returnS ((get_Minterrupts w__8 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mtvec_ref) (\ (w__9 : Mtvec) . state_monad$returnS ((get_Mtvec w__9 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (state_monad$read_regS mscratch_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (state_monad$read_regS mepc_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mcause_ref) (\ (w__12 : Mcause) . state_monad$returnS ((get_Mcause w__12 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (state_monad$read_regS mtval_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mip_ref) (\ (w__14 : Minterrupts) . + state_monad$returnS ((get_Minterrupts w__14 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) . state_monad$returnS ((get_Mstatus w__15 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS sedeleg_ref) (\ (w__16 : Sedeleg) . state_monad$returnS ((get_Sedeleg w__16 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) . + state_monad$returnS ((get_Sinterrupts w__17 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mie_ref) (\ (w__18 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__19 : Minterrupts) . + state_monad$returnS ((get_Sinterrupts ((lower_mie w__18 w__19)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS stvec_ref) (\ (w__20 : Mtvec) . state_monad$returnS ((get_Mtvec w__20 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (state_monad$read_regS sscratch_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (state_monad$read_regS sepc_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS scause_ref) (\ (w__23 : Mcause) . state_monad$returnS ((get_Mcause w__23 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (state_monad$read_regS stval_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mip_ref) (\ (w__25 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__26 : Minterrupts) . + state_monad$returnS ((get_Sinterrupts ((lower_mip w__25 w__26)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (state_monad$read_regS satp_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (state_monad$read_regS mcycle_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (state_monad$read_regS mtime_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (state_monad$read_regS minstret_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS tselect_ref : ( 64 words$word) M) (\ (w__31 : 64 words$word) . + state_monad$returnS ((not_vec w__31 : 64 words$word))) + else + let (_ : unit) = (print_bits "unhandled read to CSR " csr) in + state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))`; + + +(*val writeCSR : mword ty12 -> mword ty64 -> M unit*) + +val _ = Define ` + ((writeCSR:(12)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= + (let b__0 = csr in state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mstatus_ref ((legalize_mstatus w__0 value))) + (state_monad$read_regS mstatus_ref)) (\ (w__1 : Mstatus) . + state_monad$returnS (SOME ((get_Mstatus w__1 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS medeleg_ref) (\ (w__2 : Medeleg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS medeleg_ref ((legalize_medeleg w__2 value))) + (state_monad$read_regS medeleg_ref)) (\ (w__3 : Medeleg) . + state_monad$returnS (SOME ((get_Medeleg w__3 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__4 : Minterrupts) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mideleg_ref ((legalize_mideleg w__4 value))) + (state_monad$read_regS mideleg_ref)) (\ (w__5 : Minterrupts) . + state_monad$returnS (SOME ((get_Minterrupts w__5 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mie_ref ((legalize_mie w__6 value))) + (state_monad$read_regS mie_ref)) (\ (w__7 : Minterrupts) . + state_monad$returnS (SOME ((get_Minterrupts w__7 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mtvec_ref) (\ (w__8 : Mtvec) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mtvec_ref ((legalize_tvec w__8 value))) + (state_monad$read_regS mtvec_ref)) (\ (w__9 : Mtvec) . state_monad$returnS (SOME ((get_Mtvec w__9 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (state_monad$write_regS mscratch_ref value) + (state_monad$read_regS mscratch_ref : ( 64 words$word) M)) (\ (w__10 : 64 words$word) . state_monad$returnS (SOME w__10)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS + (legalize_xepc value : ( 64 words$word) M) (\ (w__11 : xlenbits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mepc_ref w__11) + (state_monad$read_regS mepc_ref : ( 64 words$word) M)) (\ (w__12 : 64 words$word) . state_monad$returnS (SOME w__12))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (set_Mcause mcause_ref value) + (state_monad$read_regS mcause_ref)) (\ (w__13 : Mcause) . + state_monad$returnS (SOME ((get_Mcause w__13 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (state_monad$write_regS mtval_ref value) + (state_monad$read_regS mtval_ref : ( 64 words$word) M)) (\ (w__14 : 64 words$word) . state_monad$returnS (SOME w__14)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mip_ref) (\ (w__15 : Minterrupts) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mip_ref ((legalize_mip w__15 value))) + (state_monad$read_regS mip_ref)) (\ (w__16 : Minterrupts) . + state_monad$returnS (SOME ((get_Minterrupts w__16 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__17 : Mstatus) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mstatus_ref ((legalize_sstatus w__17 value))) + (state_monad$read_regS mstatus_ref)) (\ (w__18 : Mstatus) . + state_monad$returnS (SOME ((get_Mstatus w__18 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS sedeleg_ref) (\ (w__19 : Sedeleg) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__19 value))) + (state_monad$read_regS sedeleg_ref)) (\ (w__20 : Sedeleg) . + state_monad$returnS (SOME ((get_Sedeleg w__20 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (set_Sinterrupts sideleg_ref value) + (state_monad$read_regS sideleg_ref)) (\ (w__21 : Sinterrupts) . + state_monad$returnS (SOME ((get_Sinterrupts w__21 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mie_ref) (\ (w__22 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__23 : Minterrupts) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mie_ref ((legalize_sie w__22 w__23 value))) + (state_monad$read_regS mie_ref)) (\ (w__24 : Minterrupts) . + state_monad$returnS (SOME ((get_Minterrupts w__24 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS stvec_ref) (\ (w__25 : Mtvec) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS stvec_ref ((legalize_tvec w__25 value))) + (state_monad$read_regS stvec_ref)) (\ (w__26 : Mtvec) . state_monad$returnS (SOME ((get_Mtvec w__26 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (state_monad$write_regS sscratch_ref value) + (state_monad$read_regS sscratch_ref : ( 64 words$word) M)) (\ (w__27 : 64 words$word) . state_monad$returnS (SOME w__27)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS + (legalize_xepc value : ( 64 words$word) M) (\ (w__28 : xlenbits) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS sepc_ref w__28) + (state_monad$read_regS sepc_ref : ( 64 words$word) M)) (\ (w__29 : 64 words$word) . state_monad$returnS (SOME w__29))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (set_Mcause scause_ref value) + (state_monad$read_regS scause_ref)) (\ (w__30 : Mcause) . + state_monad$returnS (SOME ((get_Mcause w__30 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (state_monad$write_regS stval_ref value) + (state_monad$read_regS stval_ref : ( 64 words$word) M)) (\ (w__31 : 64 words$word) . state_monad$returnS (SOME w__31)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS + (state_monad$read_regS mip_ref) (\ (w__32 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__33 : Minterrupts) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS mip_ref ((legalize_sip w__32 w__33 value))) + (state_monad$read_regS mip_ref)) (\ (w__34 : Minterrupts) . + state_monad$returnS (SOME ((get_Minterrupts w__34 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS + (cur_Architecture () ) (\ (w__35 : Architecture) . state_monad$bindS + (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__36 : 64 words$word) . state_monad$bindS (state_monad$seqS + (state_monad$write_regS satp_ref ((legalize_satp w__35 w__36 value : 64 words$word))) + (state_monad$read_regS satp_ref : ( 64 words$word) M)) (\ (w__37 : 64 words$word) . state_monad$returnS (SOME w__37)))) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS + (state_monad$write_regS tselect_ref value) + (state_monad$read_regS tselect_ref : ( 64 words$word) M)) (\ (w__38 : 64 words$word) . state_monad$returnS (SOME w__38)) + else state_monad$returnS NONE) (\ (res : xlenbits option) . + state_monad$returnS ((case res of + SOME (v) => + prerr_endline + ((STRCAT "CSR " + ((STRCAT ((csr_name csr)) + ((STRCAT " <- " + ((STRCAT ((string_of_vec v)) + ((STRCAT " (input: " ((STRCAT ((string_of_vec value)) ")")))))))))))) + | NONE => print_bits "unhandled write to CSR " csr + )))))`; + + +val _ = Define ` + ((decode:(32)words$word ->(ast)option) v__0= + (if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (UTYPE (imm,rd,RISCV_LUI)) + else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (UTYPE (imm,rd,RISCV_AUIPC)) + else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then + let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + ((concat_vec + ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm (( 18 : int):ii) (( 13 : int):ii) : 6 words$word)) + ((concat_vec + ((subrange_vec_dec imm (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 20 words$word)) + : 21 words$word),rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RISCV_JALR (imm,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BEQ)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BNE)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BLT)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BGE)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BLTU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,RISCV_BGEU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ADDI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_SLTI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_XORI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ORI)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ITYPE (imm,rs1,rd,RISCV_ANDI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_ADD)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SUB)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLL)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLT)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_XOR)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SRL)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_SRA)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_OR)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPE (rs2,rs1,rd,RISCV_AND)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOAD (imm,rs1,rd,T,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,BYTE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,HALF,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,WORD,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,DOUBLE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))) then + let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (ADDIW (imm,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,F,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (MUL (rs2,rs1,rd,T,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (DIV0 (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (DIV0 (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (REM (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (REM (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (MULW (rs2,rs1,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (DIVW (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (DIVW (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (REMW (rs2,rs1,rd,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (REMW (rs2,rs1,rd,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : 20 words$word))))))) then + let (pred : 4 bits) = ((subrange_vec_dec v__0 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in + let (succ : 4 bits) = ((subrange_vec_dec v__0 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in + SOME (FENCE (pred,succ)) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B1] + : 32 words$word)))) then + SOME (FENCEI () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (ECALL () ) + else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (MRET () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (SRET () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (EBREAK () ) + else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B1;B1;B1;B0;B0;B1;B1] + : 32 words$word)))) then + SOME (WFI () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word))))))) + then + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + SOME (SFENCE_VMA (rs1,rs2)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then + let aq = (access_vec_dec v__0 (( 26 : int):ii)) in + let rl = (access_vec_dec v__0 (( 25 : int):ii)) in + let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRW)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRS)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,F,CSRRC)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRW)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRS)) + else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then + let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SOME (CSR (csr,rs1,rd,T,CSRRC)) + else NONE))`; + + +val _ = Define ` + ((decodeCompressed:(16)words$word ->(ast)option) v__418= + (if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi1 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (nzi0 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + if ((((((nzi1 = (vec_of_bits [B0] : 1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) then + SOME (NOP () ) + else NONE + else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + SOME (ILLEGAL () ) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (nz54 : 2 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in + let (nz96 : 4 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in + let (nz2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (nz3 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let nzimm = + ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word)) + : 8 words$word)) in + if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then NONE + else SOME (C_ADDI4SPN (rd,nzimm)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in + SOME (C_LW (uimm,rs1,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in + SOME (C_LD (uimm,rs1,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in + SOME (C_SW (uimm,rs1,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (rs2 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in + SOME (C_SD (uimm,rs1,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (nzi40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let nzi = ((concat_vec nzi5 nzi40 : 6 words$word)) in + if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_ADDI (nzi,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + SOME (C_ADDIW ((concat_vec imm5 imm40 : 6 words$word),rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LI ((concat_vec imm5 imm40 : 6 words$word),rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi9 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (nzi4 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (nzi6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (nzi87 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + let nzimm = + ((concat_vec nzi9 + ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word)) + : 5 words$word)) + : 6 words$word)) in + if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_ADDI16SP nzimm) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm17 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm1612 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then + NONE + else SOME (C_LUI ((concat_vec imm17 imm1612 : 6 words$word),rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_SRLI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE + else SOME (C_SRAI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + SOME (C_ANDI ((concat_vec i5 i40 : 6 words$word),rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_SUB (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_XOR (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_OR (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_AND (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_SUBW (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + SOME (C_ADDW (rsd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i11 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i4 : 1 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in + let (i98 : 2 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in + let (i10 : 1 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in + let (i6 : 1 bits) = ((subrange_vec_dec v__418 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let (i7 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (i31 : 3 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + SOME (C_J ((concat_vec i11 + ((concat_vec i10 + ((concat_vec i98 + ((concat_vec i7 + ((concat_vec i6 + ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 9 words$word)) + : 10 words$word)) + : 11 words$word))) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + SOME (C_BEQZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) + : 7 words$word)) + : 8 words$word),rs)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + SOME (C_BNEZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) + : 7 words$word)) + : 8 words$word),rs)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in + if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_SLLI (shamt,rsd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (ui42 : 3 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 4 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let (uimm : 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LWSP (uimm,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (ui43 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (uimm : 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_LDSP (uimm,rd)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui52 : 4 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let (uimm : 6 bits) = ((concat_vec ui76 ui52 : 6 words$word)) in + SOME (C_SWSP (uimm,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + let (uimm : 6 bits) = ((concat_vec ui86 ui53 : 6 words$word)) in + SOME (C_SDSP (uimm,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_JR rs1) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE + else SOME (C_JALR rs1) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_MV (rd,rs2)) + else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then + NONE + else SOME (C_ADD (rsd,rs2)) + else NONE))`; + + +(*val execute_WFI : unit -> M unit*) + + val _ = Define ` + ((execute_WFI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__110= (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + (case w__0 of + Machine => state_monad$returnS () + | Supervisor => state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + handle_illegal () + else state_monad$returnS () ) + | User => handle_illegal () + ))))`; + + +(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*) + + val _ = Define ` + ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd op= + (let (off : xlenbits) = + ((EXTS (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 32 words$word)) + : 64 words$word)) in state_monad$bindS + (case op of + RISCV_LUI => state_monad$returnS off + | RISCV_AUIPC => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + state_monad$returnS ((add_vec w__0 off : 64 words$word))) + ) (\ (ret : xlenbits) . + wX ((regbits_to_regno rd)) ret)))`; + + +(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (state_monad$bindS + (speculate_conditional_success () ) (\ (w__0 : bool) . + let (status : 1 bits) = + (if w__0 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):ii) status : 64 words$word))) + (if (((status = (vec_of_bits [B1] : 1 words$word)))) then state_monad$returnS () + else state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS + (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => state_monad$bindS + (case width of + WORD => mem_write_ea addr (( 4 : int):ii) aq rl T + | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (eares : unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . state_monad$bindS + (case width of + WORD => + mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + aq rl T + | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (res : unit MemoryOpResult) . + (case res of + MemValue (_) => state_monad$returnS () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))))`; + + +(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*) + + val _ = Define ` + ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in state_monad$bindS + (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => state_monad$bindS + (case width of + BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F + | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F + | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F + | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F + ) (\ (eares : unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . state_monad$bindS + (case width of + BYTE => + mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) aq + rl F + | HALF => + mem_write_value addr (( 2 : int):ii) ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) aq + rl F + | WORD => + mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq + rl F + | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl F + ) (\ (res : unit MemoryOpResult) . + (case res of + MemValue (_) => state_monad$returnS () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))`; + + +(*val execute_SRET : unit -> M unit*) + + val _ = Define ` + ((execute_SRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__108= (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + (case w__0 of + User => handle_illegal () + | Supervisor => state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + if (((((get_Mstatus_TSR w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + handle_illegal () + else state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . state_monad$bindS + (handle_exception w__2 (CTL_SRET () ) w__3 : ( 64 words$word) M) (\ (w__4 : xlenbits) . + state_monad$write_regS nextPC_ref w__4)))) + | Machine => state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . state_monad$bindS + (handle_exception w__5 (CTL_SRET () ) w__6 : ( 64 words$word) M) (\ (w__7 : xlenbits) . + state_monad$write_regS nextPC_ref w__7))) + ))))`; + + +(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*) + + val _ = Define ` + ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in + let (result : 32 bits) = + ((case op of + RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word) + | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word)))))`; + + +(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*) + + val _ = Define ` + ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . + let (result : xlenbits) = + ((case op of + RISCV_SLLI => (shift_bits_left rs1_val shamt : 64 words$word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt : 64 words$word) + | RISCV_SRAI => (shift_right_arith64 rs1_val shamt : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result)))`; + + +(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs1 rs2= (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) + then + handle_illegal () + else state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . state_monad$bindS + (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + let p__104 = + (architecture ((get_Mstatus_SXL w__1 : 2 words$word)), (get_Mstatus_TVM w__2 : 1 words$word)) in + (case p__104 of + (SOME (RV64), v_0) => + if (((v_0 = ((bool_to_bits T : 1 words$word))))) then handle_illegal () + else state_monad$bindS + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then state_monad$returnS NONE + else state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + state_monad$returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))))) (\ (addr : + vaddr39 option) . state_monad$bindS + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then state_monad$returnS NONE + else state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + state_monad$returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))))) (\ (asid : + asid64 option) . + flushTLB asid addr)) + | (g__102, g__103) => internal_error "unimplemented sfence architecture" + ))))))`; + + +(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*) + + val _ = Define ` + ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in + let (result : 32 bits) = + ((case op of + RISCV_ADDW => (add_vec rs1_val rs2_val : 32 words$word) + | RISCV_SUBW => (sub_vec rs1_val rs2_val : 32 words$word) + | RISCV_SLLW => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word) + | RISCV_SRLW => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word) + | RISCV_SRAW => + (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))))))`; + + +(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*) + + val _ = Define ` + ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . + let (result : xlenbits) = + ((case op of + RISCV_ADD => (add_vec rs1_val rs2_val : 64 words$word) + | RISCV_SUB => (sub_vec rs1_val rs2_val : 64 words$word) + | RISCV_SLL => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + : 64 words$word) + | RISCV_SLT => + (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) : 1 words$word)) : 64 words$word) + | RISCV_SLTU => + (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) : 1 words$word)) : 64 words$word) + | RISCV_XOR => (xor_vec rs1_val rs2_val : 64 words$word) + | RISCV_SRL => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + : 64 words$word) + | RISCV_SRA => + (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) + : 64 words$word) + | RISCV_OR => (or_vec rs1_val rs2_val : 64 words$word) + | RISCV_AND => (and_vec rs1_val rs2_val : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd= (state_monad$bindS + (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS (state_monad$seqS + (wX ((regbits_to_regno rd)) w__0) + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + let (newPC : xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in + state_monad$write_regS + nextPC_ref + ((concat_vec ((subrange_vec_dec newPC (( 63 : int):ii) (( 1 : int):ii) : 63 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 64 words$word))))))`; + + +(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (pc : xlenbits) . state_monad$bindS + (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$seqS + (wX ((regbits_to_regno rd)) w__0) + (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in + state_monad$write_regS nextPC_ref ((add_vec pc offset : 64 words$word)))))))`; + + +(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + + val _ = Define ` + ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in + let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r : 32 words$word)) : 64 words$word))))))`; + + +(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + + val _ = Define ` + ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . + let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((to_bits xlen r : 64 words$word))))))`; + + +(*val execute_NOP : unit -> unit*) + + val _ = Define ` + ((execute_NOP:unit -> unit) g__111= () )`; + + +(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in + let (rs1_int : ii) = (integer_word$w2i rs1_val) in + let (rs2_int : ii) = (integer_word$w2i rs2_val) in + let result32 = + ((subrange_vec_dec ((to_bits (( 64 : int):ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):ii) + (( 0 : int):ii) + : 32 words$word)) in + let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32 : 64 words$word)) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*) + + val _ = Define ` + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . + let (rs1_int : ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let result128 = ((to_bits (( 128 : int):ii) ((rs1_int * rs2_int)) : 128 words$word)) in + let result = + (if high then (subrange_vec_dec result128 (( 127 : int):ii) (( 64 : int):ii) : 64 words$word) + else (subrange_vec_dec result128 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) in + wX ((regbits_to_regno rd)) result))))`; + + +(*val execute_MRET : unit -> M unit*) + + val _ = Define ` + ((execute_MRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__107= (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) + then state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$bindS + (handle_exception w__1 (CTL_MRET () ) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . + state_monad$write_regS nextPC_ref w__3))) + else handle_illegal () )))`; + + +(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs1 width rd= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS + (translateAddr vaddr Read Data) (\ (w__0 : TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => state_monad$bindS + (mem_read addr (( 4 : int):ii) aq rl T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__1 : ( 32 words$word) + MemoryOpResult) . + process_load rd addr w__1 F) + | DOUBLE => state_monad$bindS + (mem_read addr (( 8 : int):ii) aq rl T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__2 : ( 64 words$word) + MemoryOpResult) . + process_load rd addr w__2 F) + | _ => internal_error "LOADRES expected WORD or DOUBLE" + ) + )))))`; + + +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*) + + val _ = Define ` + ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in state_monad$bindS + (translateAddr vaddr Read Data) (\ (w__1 : TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => state_monad$bindS + (mem_read addr (( 1 : int):ii) aq rl F : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word) + MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => state_monad$bindS + (mem_read addr (( 2 : int):ii) aq rl F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__3 : ( 16 words$word) + MemoryOpResult) . + process_load rd vaddr w__3 is_unsigned) + | WORD => state_monad$bindS + (mem_read addr (( 4 : int):ii) aq rl F : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word) + MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | DOUBLE => state_monad$bindS + (mem_read addr (( 8 : int):ii) aq rl F : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word) + MemoryOpResult) . + process_load rd vaddr w__5 is_unsigned) + ) + )))))`; + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + + val _ = Define ` + ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . + let (immext : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in + let (result : xlenbits) = + ((case op of + RISCV_ADDI => (add_vec rs1_val immext : 64 words$word) + | RISCV_SLTI => + (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) : 1 words$word)) : 64 words$word) + | RISCV_SLTIU => + (EXTZ (( 64 : int):ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) : 1 words$word)) : 64 words$word) + | RISCV_XORI => (xor_vec rs1_val immext : 64 words$word) + | RISCV_ORI => (or_vec rs1_val immext : 64 words$word) + | RISCV_ANDI => (and_vec rs1_val immext : 64 words$word) + )) in + wX ((regbits_to_regno rd)) result)))`; + + +(*val execute_ILLEGAL : unit -> M unit*) + + val _ = Define ` + ((execute_ILLEGAL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__112= (handle_illegal () ))`; + + +(*val execute_FENCEI : unit -> M unit*) + + val _ = Define ` + ((execute_FENCEI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__105= (MEM_fence_i () ))`; + + +(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*) + + val _ = Define ` + ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pred succ= + ((case (pred, succ) of + (b__0, b__1) => + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then + MEM_fence_rw_rw () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then + MEM_fence_r_rw () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then + MEM_fence_r_r () else + if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ + (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then + MEM_fence_rw_w () else MEM_fence_w_w () + )))`; + + +(*val execute_ECALL : unit -> M unit*) + + val _ = Define ` + ((execute_ECALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__106= (state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + let (t : sync_exception) = + (<| sync_exception_trap := + ((case w__0 of + User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + )); + sync_exception_excinfo := NONE |>) in state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$bindS + (handle_exception w__1 (CTL_TRAP t) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . + state_monad$write_regS nextPC_ref w__3))))))`; + + +(*val execute_EBREAK : unit -> M unit*) + + val _ = Define ` + ((execute_EBREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__109= (state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + handle_mem_exception w__0 E_Breakpoint)))`; + + +(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + + val _ = Define ` + ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in + let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in + let (q' : ii) = + (if (((s /\ ((q > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then + (( 0 : int):ii) - ((ex_int ((pow0 (( 2 : int):ii) (( 31 : int):ii))))) + else q) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q' : 32 words$word)) : 64 words$word))))))`; + + +(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + + val _ = Define ` + ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . + let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in + let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in + let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in + let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in + wX ((regbits_to_regno rd)) ((to_bits xlen q' : 64 words$word))))))`; + + +(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rsd= + (let (imm : 32 bits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in state_monad$bindS + (rX ((regbits_to_regno rsd)) : ( 64 words$word) M) (\ rs_val . + let (res : 32 bits) = + ((add_vec ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) imm : 32 words$word)) in + wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):ii) res : 64 words$word)))))`; + + +(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*) + + val _ = Define ` + ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op= (state_monad$bindS + (if is_imm then state_monad$returnS ((EXTZ (( 64 : int):ii) rs1 : 64 words$word)) + else (rX ((regbits_to_regno rs1)) : ( 64 words$word) M)) (\ (rs1_val : xlenbits) . + let (isWrite : bool) = + ((case op of + CSRRW => T + | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii)) + )) in state_monad$bindS + (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS + (check_CSR csr w__1 isWrite) (\ (w__2 : bool) . + if ((~ w__2)) then handle_illegal () + else state_monad$bindS + (readCSR csr : ( 64 words$word) M) (\ csr_val . state_monad$seqS + (if isWrite then + let (new_val : xlenbits) = + ((case op of + CSRRW => rs1_val + | CSRRS => (or_vec csr_val rs1_val : 64 words$word) + | CSRRC => (and_vec csr_val ((not_vec rs1_val : 64 words$word)) : 64 words$word) + )) in + writeCSR csr new_val + else state_monad$returnS () ) + (wX ((regbits_to_regno rd)) csr_val)))))))`; + + +(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*) + + val _ = Define ` + ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 op= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . + let (taken : bool) = + ((case op of + RISCV_BEQ => (rs1_val = rs2_val) + | RISCV_BNE => (rs1_val <> rs2_val) + | RISCV_BLT => zopz0zI_s rs1_val rs2_val + | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val + | RISCV_BLTU => zopz0zI_u rs1_val rs2_val + | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val + )) in + if taken then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + state_monad$write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word))) + else state_monad$returnS () ))))`; + + +(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS + (translateAddr vaddr ReadWrite Data) (\ (w__0 : TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => state_monad$bindS + (case width of + WORD => mem_write_ea addr (( 4 : int):ii) (((aq /\ rl))) rl T + | DOUBLE => mem_write_ea addr (( 8 : int):ii) (((aq /\ rl))) rl T + | _ => internal_error "AMO expected WORD or DOUBLE" + ) (\ (eares : unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => state_monad$bindS + (case width of + WORD => state_monad$bindS + (mem_read addr (( 4 : int):ii) aq (((aq /\ rl))) T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word) + MemoryOpResult) . + state_monad$returnS ((extend_value F w__4 : ( 64 words$word) MemoryOpResult))) + | DOUBLE => state_monad$bindS + (mem_read addr (( 8 : int):ii) aq (((aq /\ rl))) T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word) + MemoryOpResult) . + state_monad$returnS ((extend_value F w__5 : ( 64 words$word) MemoryOpResult))) + | _ => (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)MemoryOpResult) M) + ) (\ (rval : xlenbits MemoryOpResult) . + (case rval of + MemException (e) => handle_mem_exception addr e + | MemValue (loaded) => state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (rs2_val : xlenbits) . + let (result : xlenbits) = + ((case op of + AMOSWAP => rs2_val + | AMOADD => (add_vec rs2_val loaded : 64 words$word) + | AMOXOR => (xor_vec rs2_val loaded : 64 words$word) + | AMOAND => (and_vec rs2_val loaded : 64 words$word) + | AMOOR => (or_vec rs2_val loaded : 64 words$word) + | AMOMIN => (vector64 ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) + | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) + | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) + | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) + )) in state_monad$bindS + (case width of + WORD => + mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + (((aq /\ rl))) rl T + | DOUBLE => mem_write_value addr (( 8 : int):ii) result (((aq /\ rl))) rl T + | _ => internal_error "AMO expected WORD or DOUBLE" + ) (\ (wval : unit MemoryOpResult) . + (case wval of + MemValue (_) => wX ((regbits_to_regno rd)) loaded + | MemException (e) => handle_mem_exception addr e + ))) + )) + )) + )))))`; + + +(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + + val _ = Define ` + ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd= (state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm : 64 words$word)) w__0 : 64 words$word)) in + wX ((regbits_to_regno rd)) + ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + + + val execute_defn = Hol_defn "execute" ` + ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var= + ((case merge_var of + C_ADDI4SPN (rdc,nzimm) => + let (imm : 12 bits) = + ((concat_vec (vec_of_bits [B0;B0] : 2 words$word) + ((concat_vec nzimm (vec_of_bits [B0;B0] : 2 words$word) : 10 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + execute (ITYPE (imm,sp,rd,RISCV_ADDI)) + | C_LW (uimm,rsc,rdc) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + let rs = ((creg2reg_bits rsc : 5 words$word)) in + execute (LOAD (imm,rs,rd,F,WORD,F,F)) + | C_LD (uimm,rsc,rdc) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) + : 12 words$word)) in + let rd = ((creg2reg_bits rdc : 5 words$word)) in + let rs = ((creg2reg_bits rsc : 5 words$word)) in + execute (LOAD (imm,rs,rd,F,DOUBLE,F,F)) + | C_SW (uimm,rsc1,rsc2) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) + : 12 words$word)) in + let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in + let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in + execute (STORE (imm,rs2,rs1,WORD,F,F)) + | C_SD (uimm,rsc1,rsc2) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) + : 12 words$word)) in + let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in + let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in + execute (STORE (imm,rs2,rs1,DOUBLE,F,F)) + | C_ADDI (nzi,rsd) => + let (imm : 12 bits) = ((EXTS (( 12 : int):ii) nzi : 12 words$word)) in + execute (ITYPE (imm,rsd,rsd,RISCV_ADDI)) + | C_JAL (imm) => + execute + (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) + : 21 words$word),ra)) + | C_LI (imm,rd) => + let (imm : 12 bits) = ((EXTS (( 12 : int):ii) imm : 12 words$word)) in + execute (ITYPE (imm,zreg,rd,RISCV_ADDI)) + | C_ADDI16SP (imm) => + let (imm : 12 bits) = + ((EXTS (( 12 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 10 words$word)) + : 12 words$word)) in + execute (ITYPE (imm,sp,sp,RISCV_ADDI)) + | C_LUI (imm,rd) => + let (res : 20 bits) = ((EXTS (( 20 : int):ii) imm : 20 words$word)) in + execute (UTYPE (res,rd,RISCV_LUI)) + | C_SRLI (shamt,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI)) + | C_SRAI (shamt,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI)) + | C_ANDI (imm,rsd) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + execute (ITYPE ((EXTS (( 12 : int):ii) imm : 12 words$word),rsd,rsd,RISCV_ANDI)) + | C_SUB (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_SUB)) + | C_XOR (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_XOR)) + | C_OR (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_OR)) + | C_AND (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_AND)) + | C_SUBW (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW)) + | C_ADDW (rsd,rs2) => + let rsd = ((creg2reg_bits rsd : 5 words$word)) in + let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW)) + | C_J (imm) => + execute + (RISCV_JAL ((EXTS (( 21 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) + : 21 words$word),zreg)) + | C_BEQZ (imm,rs) => + execute + (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) + : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BEQ)) + | C_BNEZ (imm,rs) => + execute + (BTYPE ((EXTS (( 13 : int):ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) + : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BNE)) + | C_SLLI (shamt,rsd) => execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI)) + | C_LWSP (uimm,rd) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) + : 12 words$word)) in + execute (LOAD (imm,sp,rd,F,WORD,F,F)) + | C_LDSP (uimm,rd) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) + : 12 words$word)) in + execute (LOAD (imm,sp,rd,F,DOUBLE,F,F)) + | C_SWSP (uimm,rs2) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) + : 12 words$word)) in + execute (STORE (imm,rs2,sp,WORD,F,F)) + | C_SDSP (uimm,rs2) => + let (imm : 12 bits) = + ((EXTZ (( 12 : int):ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) + : 12 words$word)) in + execute (STORE (imm,rs2,sp,DOUBLE,F,F)) + | C_JR (rs1) => + execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,zreg)) + | C_JALR (rs1) => + execute (RISCV_JALR ((EXTZ (( 12 : int):ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,ra)) + | C_MV (rd,rs2) => execute (RTYPE (rs2,zreg,rd,RISCV_ADD)) + | C_ADD (rsd,rs2) => execute (RTYPE (rs2,rsd,rsd,RISCV_ADD)) + | UTYPE (imm,rd,op) => execute_UTYPE imm rd op + | RISCV_JAL (imm,rd) => execute_RISCV_JAL imm rd + | RISCV_JALR (imm,rs1,rd) => execute_RISCV_JALR imm rs1 rd + | BTYPE (imm,rs2,rs1,op) => execute_BTYPE imm rs2 rs1 op + | ITYPE (imm,rs1,rd,op) => execute_ITYPE imm rs1 rd op + | SHIFTIOP (shamt,rs1,rd,op) => execute_SHIFTIOP shamt rs1 rd op + | RTYPE (rs2,rs1,rd,op) => execute_RTYPE rs2 rs1 rd op + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => execute_LOAD imm rs1 rd is_unsigned width aq rl + | STORE (imm,rs2,rs1,width,aq,rl) => execute_STORE imm rs2 rs1 width aq rl + | ADDIW (imm,rs1,rd) => execute_ADDIW imm rs1 rd + | SHIFTW (shamt,rs1,rd,op) => execute_SHIFTW shamt rs1 rd op + | RTYPEW (rs2,rs1,rd,op) => execute_RTYPEW rs2 rs1 rd op + | MUL (rs2,rs1,rd,high,signed1,signed2) => execute_MUL rs2 rs1 rd high signed1 signed2 + | DIV0 (rs2,rs1,rd,s) => execute_DIV rs2 rs1 rd s + | REM (rs2,rs1,rd,s) => execute_REM rs2 rs1 rd s + | MULW (rs2,rs1,rd) => execute_MULW rs2 rs1 rd + | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s + | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s + | FENCE (pred,succ) => execute_FENCE pred succ + | FENCEI (g__105) => execute_FENCEI g__105 + | ECALL (g__106) => execute_ECALL g__106 + | MRET (g__107) => execute_MRET g__107 + | SRET (g__108) => execute_SRET g__108 + | EBREAK (g__109) => execute_EBREAK g__109 + | WFI (g__110) => execute_WFI g__110 + | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2 + | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd + | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd + | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd + | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op + | NOP (g__111) => state_monad$returnS ((execute_NOP g__111)) + | ILLEGAL (g__112) => execute_ILLEGAL g__112 + | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn; + +val _ = Define ` + ((print_insn:ast -> string) merge_var= + ((case merge_var of + UTYPE (imm,rd,op) => + (case op of + RISCV_LUI => + STRCAT "lui " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | RISCV_AUIPC => + STRCAT "auipc " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + ) + | RISCV_JAL (imm,rd) => + STRCAT "jal " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | RISCV_JALR (imm,rs1,rd) => + STRCAT "jalr " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | BTYPE (imm,rs2,rs1,op) => + let (insn : string) = + ((case op of + RISCV_BEQ => "beq " + | RISCV_BNE => "bne " + | RISCV_BLT => "blt " + | RISCV_BGE => "bge " + | RISCV_BLTU => "bltu " + | RISCV_BGEU => "bgeu " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rs1)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | ITYPE (imm,rs1,rd,op) => + let (insn : string) = + ((case op of + RISCV_ADDI => "addi " + | RISCV_SLTI => "slti " + | RISCV_SLTIU => "sltiu " + | RISCV_XORI => "xori " + | RISCV_ORI => "ori " + | RISCV_ANDI => "andi " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | SHIFTIOP (shamt,rs1,rd,op) => + let (insn : string) = + ((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + | RTYPE (rs2,rs1,rd,op) => + let (insn : string) = + ((case op of + RISCV_ADD => "add " + | RISCV_SUB => "sub " + | RISCV_SLL => "sll " + | RISCV_SLT => "slt " + | RISCV_SLTU => "sltu " + | RISCV_XOR => "xor " + | RISCV_SRL => "srl " + | RISCV_SRA => "sra " + | RISCV_OR => "or " + | RISCV_AND => "and " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => + let (insn : string) = + ((case (width, is_unsigned) of + (BYTE, F) => "lb " + | (BYTE, T) => "lbu " + | (HALF, F) => "lh " + | (HALF, T) => "lhu " + | (WORD, F) => "lw " + | (WORD, T) => "lwu " + | (DOUBLE, F) => "ld " + | (DOUBLE, T) => "ldu " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | STORE (imm,rs2,rs1,width,aq,rl) => + let (insn : string) = + ((case width of + BYTE => "sb " + | HALF => "sh " + | WORD => "sw " + | DOUBLE => "sd " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rs2)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | ADDIW (imm,rs1,rd) => + STRCAT "addiw " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + | SHIFTW (shamt,rs1,rd,op) => + let (insn : string) = + ((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + | RTYPEW (rs2,rs1,rd,op) => + let (insn : string) = + ((case op of + RISCV_ADDW => "addw " + | RISCV_SUBW => "subw " + | RISCV_SLLW => "sllw " + | RISCV_SRLW => "srlw " + | RISCV_SRAW => "sraw " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + let (insn : string) = + ((case (high, signed1, signed2) of + (F, T, T) => "mul " + | (T, T, T) => "mulh " + | (T, T, F) => "mulhsu " + | (T, F, F) => "mulhu" + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | DIV0 (rs2,rs1,rd,s) => + let (insn : string) = (if s then "div " else "divu ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | REM (rs2,rs1,rd,s) => + let (insn : string) = (if s then "rem " else "remu ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | MULW (rs2,rs1,rd) => + STRCAT "mulw " + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | DIVW (rs2,rs1,rd,s) => + let (insn : string) = (if s then "divw " else "divuw ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | REMW (rs2,rs1,rd,s) => + let (insn : string) = (if s then "remw " else "remuw ") in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | FENCE (pred,succ) => "fence" + | FENCEI (g__93) => "fence.i" + | ECALL (g__94) => "ecall" + | MRET (g__95) => "mret" + | SRET (g__96) => "sret" + | EBREAK (g__97) => "ebreak" + | WFI (g__98) => "wfi" + | SFENCE_VMA (rs1,rs2) => + STRCAT "sfence.vma " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))) + | LOADRES (aq,rl,rs1,width,rd) => + let (insn : string) = + ((case width of WORD => "lr.w " | DOUBLE => "lr.d " | _ => "lr.bad " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1)))))) + | STORECON (aq,rl,rs2,rs1,width,rd) => + let (insn : string) = + ((case width of WORD => "sc.w " | DOUBLE => "sc.d " | _ => "sc.bad " )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + let (insn : string) = + ((case (op, width) of + (AMOSWAP, WORD) => "amoswap.w " + | (AMOADD, WORD) => "amoadd.w " + | (AMOXOR, WORD) => "amoxor.w " + | (AMOAND, WORD) => "amoand.w " + | (AMOOR, WORD) => "amoor.w " + | (AMOMIN, WORD) => "amomin.w " + | (AMOMAX, WORD) => "amomax.w " + | (AMOMINU, WORD) => "amominu.w " + | (AMOMAXU, WORD) => "amomaxu.w " + | (AMOSWAP, DOUBLE) => "amoswap.d " + | (AMOADD, DOUBLE) => "amoadd.d " + | (AMOXOR, DOUBLE) => "amoxor.d " + | (AMOAND, DOUBLE) => "amoand.d " + | (AMOOR, DOUBLE) => "amoor.d " + | (AMOMIN, DOUBLE) => "amomin.d " + | (AMOMAX, DOUBLE) => "amomax.d " + | (AMOMINU, DOUBLE) => "amominu.d " + | (AMOMAXU, DOUBLE) => "amomaxu.d " + | (_, _) => "amo.bad " + )) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " + ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + | CSR (csr,rs1,rd,is_imm,op) => + let (insn : string) = + ((case (op, is_imm) of + (CSRRW, T) => "csrrwi " + | (CSRRW, F) => "csrrw " + | (CSRRS, T) => "csrrsi " + | (CSRRS, F) => "csrrs " + | (CSRRC, T) => "csrrci " + | (CSRRC, F) => "csrrc " + )) in + let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in + STRCAT insn + ((STRCAT ((reg_name_abi rd)) + ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr)))))))))) + | NOP (g__99) => "nop" + | ILLEGAL (g__100) => "illegal" + | C_ADDI4SPN (rdc,nzimm) => + STRCAT "c.addi4spn " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec nzimm)))))) + | C_LW (uimm,rsc,rdc) => + STRCAT "c.lw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_LD (uimm,rsc,rdc) => + STRCAT "c.ld " + ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_SW (uimm,rsc1,rsc2) => + STRCAT "c.sw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_SD (uimm,rsc1,rsc2) => + STRCAT "c.sd " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) + ((STRCAT ", " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) + ((STRCAT ", " ((string_of_vec uimm)))))))))) + | C_ADDI (nzi,rsd) => + STRCAT "c.addi " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi)))))) + | C_JAL (imm) => STRCAT "c.jal " ((string_of_vec imm)) + | C_ADDIW (imm,rsd) => + STRCAT "c.addiw " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_LI (imm,rd) => + STRCAT "c.li " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_ADDI16SP (imm) => STRCAT "c.addi16sp " ((string_of_vec imm)) + | C_LUI (imm,rd) => + STRCAT "c.lui " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + | C_SRLI (shamt,rsd) => + STRCAT "c.srli " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec shamt)))))) + | C_SRAI (shamt,rsd) => + STRCAT "c.srai " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec shamt)))))) + | C_ANDI (imm,rsd) => + STRCAT "c.andi " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_SUB (rsd,rs2) => + STRCAT "c.sub " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_XOR (rsd,rs2) => + STRCAT "c.xor " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_OR (rsd,rs2) => + STRCAT "c.or " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_AND (rsd,rs2) => + STRCAT "c.and " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_SUBW (rsd,rs2) => + STRCAT "c.subw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_ADDW (rsd,rs2) => + STRCAT "c.addw " + ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) + ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) + | C_J (imm) => STRCAT "c.j " ((string_of_vec imm)) + | C_BEQZ (imm,rs) => + STRCAT "c.beqz " + ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_BNEZ (imm,rs) => + STRCAT "c.bnez " + ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) + ((STRCAT ", " ((string_of_vec imm)))))) + | C_SLLI (shamt,rsd) => + STRCAT "c.slli " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt)))))) + | C_LWSP (uimm,rd) => + STRCAT "c.lwsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_LDSP (uimm,rd) => + STRCAT "c.ldsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_SWSP (uimm,rd) => + STRCAT "c.swsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_SDSP (uimm,rd) => + STRCAT "c.sdsp " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + | C_JR (rs1) => STRCAT "c.jr " ((reg_name_abi rs1)) + | C_JALR (rs1) => STRCAT "c.jalr " ((reg_name_abi rs1)) + | C_MV (rd,rs2) => + STRCAT "c.mv " + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs2)))))) + | C_ADD (rsd,rs2) => + STRCAT "c.add " + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2)))))) + )))`; + + +(*val isRVC : mword ty16 -> bool*) + +val _ = Define ` + ((isRVC:(16)words$word -> bool) h= + (~ (((((subrange_vec_dec h (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))`; + + +(*val fetch : unit -> M FetchResult*) + +val _ = Define ` + ((fetch:unit ->(regstate)state_monad$sequential_state ->(((FetchResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state$or_boolS + ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) + (state$and_boolS + ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : xlenbits) . + state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) + ( state_monad$bindS(haveRVC () ) (\ (w__2 : bool) . state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . + if w__4 then state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . + state_monad$returnS (F_Error (E_Fetch_Addr_Align,w__5))) + else state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . state_monad$bindS + (translateAddr w__6 Execute Instruction) (\ (w__7 : TR_Result) . + (case w__7 of + TR_Failure (e) => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) . state_monad$returnS (F_Error (e,w__8))) + | TR_Address (ppclo) => state_monad$bindS + (checked_mem_read Instruction ppclo (( 2 : int):ii) : ( ( 16 words$word)MemoryOpResult) M) (\ (w__9 : ( 16 words$word) + MemoryOpResult) . + (case w__9 of + MemException (e) => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . + state_monad$returnS (F_Error (E_Fetch_Access_Fault,w__10))) + | MemValue (ilo) => + if ((isRVC ilo)) then state_monad$returnS (F_RVC ilo) + else state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) . + let (PChi : xlenbits) = ((add_vec_int w__11 (( 2 : int):ii) : 64 words$word)) in state_monad$bindS + (translateAddr PChi Execute Instruction) (\ (w__12 : TR_Result) . + (case w__12 of + TR_Failure (e) => state_monad$returnS (F_Error (e,PChi)) + | TR_Address (ppchi) => state_monad$bindS + (checked_mem_read Instruction ppchi (( 2 : int):ii) : ( ( 16 words$word)MemoryOpResult) M) (\ (w__13 : ( 16 words$word) + MemoryOpResult) . + state_monad$returnS ((case w__13 of + MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) + | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word)) + ))) + ))) + )) + ))))))`; + + +(*val step : unit -> M bool*) + +val _ = Define ` + ((step:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + (state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mie_ref) (\ (w__1 : Minterrupts) . state_monad$bindS + (state_monad$read_regS mideleg_ref) (\ (w__2 : Minterrupts) . state_monad$bindS + (curInterrupt w__0 w__1 w__2) (\ (w__3 : ((InterruptType # Privilege))option) . + (case w__3 of + SOME (intr,priv) => + let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr : 4 words$word))) in state_monad$seqS + (handle_interrupt intr priv) (state_monad$returnS F) + | NONE => state_monad$bindS + (fetch () ) (\ (w__4 : FetchResult) . + (case w__4 of + F_Error (e,addr) => state_monad$seqS (handle_mem_exception addr e) (state_monad$returnS F) + | F_RVC (h) => + (case ((decodeCompressed h)) of + NONE => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : xlenbits) . + let (_ : unit) = + (prerr_endline + ((STRCAT "PC: " + ((STRCAT ((string_of_vec w__5)) + ((STRCAT " instr: " + ((STRCAT ((string_of_vec h)) " : <no-decode>"))))))))) in state_monad$seqS + (handle_decode_exception ((EXTZ (( 64 : int):ii) h : 64 words$word))) (state_monad$returnS F)) + | SOME (ast) => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : xlenbits) . + let (_ : unit) = + (prerr_endline + ((STRCAT "PC: " + ((STRCAT ((string_of_vec w__6)) + ((STRCAT " instr: " + ((STRCAT ((string_of_vec h)) + ((STRCAT " : " ((print_insn ast))))))))))))) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__7 : 64 words$word) . state_monad$seqS (state_monad$seqS + (state_monad$write_regS nextPC_ref ((add_vec_int w__7 (( 2 : int):ii) : 64 words$word))) + (execute ast)) (state_monad$returnS T))) + ) + | F_Base (w) => + (case ((decode w)) of + NONE => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : xlenbits) . + let (_ : unit) = + (prerr_endline + ((STRCAT "PC: " + ((STRCAT ((string_of_vec w__9)) + ((STRCAT " instr: " + ((STRCAT ((string_of_vec w)) " : <no-decode>"))))))))) in state_monad$seqS + (handle_decode_exception ((EXTZ (( 64 : int):ii) w : 64 words$word))) (state_monad$returnS F)) + | SOME (ast) => state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : xlenbits) . + let (_ : unit) = + (prerr_endline + ((STRCAT "PC: " + ((STRCAT ((string_of_vec w__10)) + ((STRCAT " instr: " + ((STRCAT ((string_of_vec w)) + ((STRCAT " : " ((print_insn ast))))))))))))) in state_monad$bindS + (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) . state_monad$seqS (state_monad$seqS + (state_monad$write_regS nextPC_ref ((add_vec_int w__11 (( 4 : int):ii) : 64 words$word))) + (execute ast)) (state_monad$returnS T))) + ) + )) + )))))))`; + + +val _ = Define ` +((initial_regstate:regstate)= + (<| tlb39 := NONE; + tselect := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + stval := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + scause := + (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + sepc := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + sscratch := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + stvec := + (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + satp := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + sideleg := + (Mk_Sinterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + sedeleg := + (Mk_Sedeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + pmpcfg0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + pmpaddr0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mhartid := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + marchid := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mimpid := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mvendorid := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + minstret := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mtime := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mcycle := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mscratch := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mtval := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mepc := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mcause := + (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mtvec := + (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + medeleg := + (Mk_Medeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mideleg := + (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + mie := + (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + mip := + (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : 64 words$word)); + mstatus := + (Mk_Mstatus (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + misa := + (Mk_Misa (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + cur_inst := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + cur_privilege := User; + Xs := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + nextPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + PC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml index 541bc1d3..41ae5deb 100644 --- a/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml +++ b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml @@ -1,102 +1,101 @@ -(*Generated by Lem from riscv_extras_sequential.lem.*) +(*Generated by Lem from riscv_extras.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; +open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; val _ = numLib.prefer_num(); -val _ = new_theory "riscv_extras_sequential" +val _ = new_theory "riscv_extras" (*open import Pervasives*) (*open import Pervasives_extra*) (*open import Sail_instr_kinds*) (*open import Sail_values*) (*open import Sail_operators_mwords*) -(*open import State_monad*) -(*open import State*) +(*open import Prompt_monad*) +(*open import Prompt*) val _ = type_abbrev((* 'a *) "bitvector" , ``: 'a words$word``); -(*val barrierS : forall 'rv 'e. Sail_instr_kinds.barrier_kind -> State_monad.monadS 'rv unit 'e*) val _ = Define ` - ((barrierS:sail_instr_kinds$barrier_kind -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) _= (returnS () ))`; - - -val _ = Define ` - ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_rw_rw))`; + ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_rw))`; val _ = Define ` - ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_r_rw))`; + ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_rw))`; val _ = Define ` - ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_r_r))`; + ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_r))`; val _ = Define ` - ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_rw_w))`; + ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_w))`; val _ = Define ` - ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_w_w))`; + ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_w))`; val _ = Define ` - ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrierS Barrier_RISCV_i))`; + ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_i))`; -(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) -(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) -(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) -(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) -(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) -(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*) +(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) val _ = Define ` - ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (write_mem_eaS + ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= -(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`; + ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= + (state_monad$write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`; (*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> State_monad.monadS 'rv unit 'e*) + integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*) val _ = Define ` - ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value= (bindS (seqS -(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1)) -(write_mem_valS instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b . (case (b ) of ( _ ) => returnS () ))))`; + ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value= (state_monad$bindS (state_monad$seqS + (state_monad$write_mem_eaS + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1)) + (state_monad$write_mem_valS + instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; (*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => - Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> State_monad.monadS 'rv (bitvector 'b) 'e*) + integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) val _ = Define ` - ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address= - (read_memS instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; + ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address= + (state_monad$read_memS + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; val _ = Define ` - ((speculate_conditional_success:unit -> 'b state_monad$sequential_state ->(((bool),'a)state_monad$result#'b state_monad$sequential_state)set) () = (excl_resultS () ))`; + ((speculate_conditional_success:unit -> 'a state_monad$sequential_state ->(((bool),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$excl_resultS () ))`; -(*val get_slice_int : forall 'a. Size 'a => Num.integer -> Num.integer -> Num.integer -> bitvector 'a*) +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*) val _ = Define ` - ((get_slice_int:int -> int -> int -> 'a words$word) len n lo= -( + ((get_slice_int0:int -> int -> int -> 'a words$word) len n lo= + ( (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in let bits = (bits_of_int (hi +( 1 : int)) n) in of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list F bits hi lo)))`; @@ -120,8 +119,5 @@ val _ = Define ` val _ = Define ` ((print_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`; - -val _ = Define ` - ((reg_deref0:('d,'c,'b)sail_values$register_ref ->('d,'b,'a)state_monad$monadS)= read_regS)`; val _ = export_theory() diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml deleted file mode 100644 index 22d8e899..00000000 --- a/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml +++ /dev/null @@ -1,7554 +0,0 @@ -(*Generated by Lem from riscv_sequential.lem.*) -open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory; - -val _ = numLib.prefer_num(); - - - -val _ = new_theory "riscv_sequential" - -(*Generated by Sail from riscv_sequential.*) -(*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import State_monad*) -(*open import State*) -(*open import Riscv_sequential_types*) -(*open import Riscv_extras_sequential*) - - - - - - - - - -(*val builtin_and_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*) - - - -(*val builtin_or_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*) - - - -(*val __raw_SetSlice_int : forall 'w. Num.integer -> Sail_values.ii -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Sail_values.ii*) - -(*val __GetSlice_int : forall 'n. Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*) - -val _ = Define ` - ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1= ((get_slice_int n m o1 : 'n words$word)))`; - - -(*val __raw_SetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Riscv_sequential_types.bits 'n*) - -(*val __raw_GetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w*) - -(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b= - ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; - - -(*val DecStr : Sail_values.ii -> string*) - -(*val HexStr : Sail_values.ii -> string*) - -(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (seqS -(write_ram (( 64 : int):sail_values$ii) width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) addr data) -(returnS T)))`; - - -(*val __TraceMemoryWrite : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*) - -(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Maybe.maybe (Machine_word.mword 'int8_times_n))*) - -val _ = Define ` - ((RISCV_read:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= (bindS - (read_ram (( 64 : int):sail_values$ii) width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) addr - : ( 'int8_times_n words$word) riscv_sequential_types$M) (\ (w__0 : 'int8_times_n words$word) . - returnS (SOME w__0))))`; - - -(*val __TraceMemoryRead : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*) - -(*val ex_nat : Sail_values.ii -> Num.integer*) - -val _ = Define ` - ((ex_nat:int -> int) n= n)`; - - -(*val ex_int : Sail_values.ii -> Num.integer*) - -val _ = Define ` - ((ex_int:int -> int) n= n)`; - - -(*val coerce_int_nat : Sail_values.ii -> Riscv_sequential_types.M Sail_values.ii*) - -val _ = Define ` - ((coerce_int_nat:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((int),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) x= (seqS (assert_expS T "") (returnS x)))`; - - -(*val EXTS : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*) - -val _ = Define ` - ((EXTS:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend v m__tv : 'm words$word)))`; - - -val _ = Define ` - ((EXTZ:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend v m__tv : 'm words$word)))`; - - - - - - - - - - - - -(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; - - -(*val bit_to_bool : Sail_values.bitU -> bool*) - -val _ = Define ` - ((bit_to_bool:sail_values$bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; - - -(*val vector64 : Sail_values.ii -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((vector64:int ->(64)words$word) n= ((get_slice_int (( 64 : int):sail_values$ii) n (( 0 : int):sail_values$ii) : 64 words$word)))`; - - -(*val to_bits : forall 'l. Size 'l => Num.integer -> Sail_values.ii -> Machine_word.mword 'l*) - -val _ = Define ` - ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int l n (( 0 : int):sail_values$ii) : 'l words$word)))`; - - -(*val shift_right_arith64 : Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 riscv_sequential_types$bits) (shift : 6 riscv_sequential_types$bits)= - (let (v128 : 128 riscv_sequential_types$bits) = ((EXTS (( 128 : int):sail_values$ii) v : 128 words$word)) in - (subrange_vec_dec ((shift_bits_right v128 shift : 128 words$word)) (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)))`; - - -(*val shift_right_arith32 : Machine_word.mword Machine_word.ty32 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty32*) - -val _ = Define ` - ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 riscv_sequential_types$bits) (shift : 5 riscv_sequential_types$bits)= - (let (v64 : 64 riscv_sequential_types$bits) = ((EXTS (( 64 : int):sail_values$ii) v : 64 words$word)) in - (subrange_vec_dec ((shift_bits_right v64 shift : 64 words$word)) (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)))`; - - -val _ = Define ` - ((xlen:int)= ((( 64 : int):sail_values$ii)))`; - - -val _ = Define ` - ((xlen_max_unsigned:int)= (((pow2 xlen)) - (( 1 : int):sail_values$ii)))`; - - -val _ = Define ` - ((xlen_max_signed:int)= (((pow2 ((xlen - (( 1 : int):sail_values$ii))))) - (( 1 : int):sail_values$ii)))`; - - -val _ = Define ` - ((xlen_min_signed:int)= ((( 0 : int):sail_values$ii) - ((pow2 ((xlen - (( 1 : int):sail_values$ii)))))))`; - - -(*val regbits_to_regno : Machine_word.mword Machine_word.ty5 -> Num.integer*) - -val _ = Define ` - ((regbits_to_regno:(5)words$word -> int) b= - (let r = (lem$w2ui b) in - r))`; - - -(*val creg2reg_bits : Machine_word.mword Machine_word.ty3 -> Machine_word.mword Machine_word.ty5*) - -val _ = Define ` - ((creg2reg_bits:(3)words$word ->(5)words$word) creg= ((concat_vec (vec_of_bits [B0;B1] : 2 words$word) creg : 5 words$word)))`; - - -val _ = Define ` -((zreg:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; - - -val _ = Define ` -((ra:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))`; - - -val _ = Define ` -((sp:(5)words$word)= ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))`; - - -(*val rX : Num.integer -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((rX:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) l__81= - (if (((l__81 = (( 0 : int):sail_values$ii)))) then - returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word) - else bindS -(read_regS Xs_ref) (\ (w__0 : riscv_sequential_types$xlenbits list) . - returnS ((access_list_dec w__0 l__81 : 64 words$word)))))`; - - -(*val wX : Num.integer -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((wX:int ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r v= - (if (((r <> (( 0 : int):sail_values$ii)))) then bindS -(read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) . seqS -(write_regS Xs_ref ((update_list_dec w__0 r v : ( 64 words$word) list))) -(returnS ((prerr_endline - ((STRCAT "x" - ((STRCAT ((stringFromInteger r)) - ((STRCAT " <- " ((string_of_vec v)))))))))))) - else returnS () ))`; - - -(*val reg_name_abi : Machine_word.mword Machine_word.ty5 -> string*) - -val _ = Define ` - ((reg_name_abi:(5)words$word -> string) r= - (let b__0 = r in - if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then - "zero" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then - "ra" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then - "sp" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then - "gp" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then - "tp" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then - "t0" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then - "t1" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then - "t2" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then - "fp" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then - "s1" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then - "a0" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then - "a1" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then - "a2" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then - "a3" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then - "a4" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then - "a5" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then - "a6" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then - "a7" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then - "s2" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then - "s3" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then - "s4" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then - "s5" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then - "s6" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then - "s7" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then - "s8" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then - "s9" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then - "s10" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then - "s11" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then - "t3" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then - "t4" - else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then - "t5" - else "t6"))`; - - -(*val Architecture_of_num : Num.integer -> Riscv_sequential_types.Architecture*) - -val _ = Define ` - ((Architecture_of_num:int -> riscv_sequential_types$Architecture) arg_= - (let l__79 = arg_ in - if (((l__79 = (( 0 : int):sail_values$ii)))) then RV32 - else if (((l__79 = (( 1 : int):sail_values$ii)))) then RV64 - else RV128))`; - - -(*val num_of_Architecture : Riscv_sequential_types.Architecture -> Num.integer*) - -val _ = Define ` - ((num_of_Architecture:riscv_sequential_types$Architecture -> int) arg_= - ((case arg_ of RV32 => (( 0 : int):sail_values$ii) | RV64 => (( 1 : int):sail_values$ii) | RV128 => (( 2 : int):sail_values$ii) )))`; - - -(*val architecture : Machine_word.mword Machine_word.ty2 -> Maybe.maybe Riscv_sequential_types.Architecture*) - -val _ = Define ` - ((architecture:(2)words$word ->(riscv_sequential_types$Architecture)option) a= - (let b__0 = a in - if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then SOME RV32 - else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then SOME RV64 - else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then SOME RV128 - else NONE))`; - - -(*val arch_to_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((arch_to_bits:riscv_sequential_types$Architecture ->(2)words$word) a= - ((case a of - RV32 => (vec_of_bits [B0;B1] : 2 words$word) - | RV64 => (vec_of_bits [B1;B0] : 2 words$word) - | RV128 => (vec_of_bits [B1;B1] : 2 words$word) - )))`; - - -(*val Privilege_of_num : Num.integer -> Riscv_sequential_types.Privilege*) - -val _ = Define ` - ((Privilege_of_num:int -> riscv_sequential_types$Privilege) arg_= - (let l__77 = arg_ in - if (((l__77 = (( 0 : int):sail_values$ii)))) then User - else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor - else Machine))`; - - -(*val num_of_Privilege : Riscv_sequential_types.Privilege -> Num.integer*) - -val _ = Define ` - ((num_of_Privilege:riscv_sequential_types$Privilege -> int) arg_= - ((case arg_ of User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Machine => (( 2 : int):sail_values$ii) )))`; - - -(*val privLevel_to_bits : Riscv_sequential_types.Privilege -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((privLevel_to_bits:riscv_sequential_types$Privilege ->(2)words$word) p= - ((case p of - User => (vec_of_bits [B0;B0] : 2 words$word) - | Supervisor => (vec_of_bits [B0;B1] : 2 words$word) - | Machine => (vec_of_bits [B1;B1] : 2 words$word) - )))`; - - -(*val privLevel_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege*) - -val _ = Define ` - ((privLevel_of_bits:(2)words$word -> riscv_sequential_types$Privilege) p= - (let b__0 = p in - if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then User - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor - else Machine))`; - - -(*val privLevel_to_str : Riscv_sequential_types.Privilege -> string*) - -val _ = Define ` - ((privLevel_to_str:riscv_sequential_types$Privilege -> string) p= ((case p of User => "U" | Supervisor => "S" | Machine => "M" )))`; - - -(*val AccessType_of_num : Num.integer -> Riscv_sequential_types.AccessType*) - -val _ = Define ` - ((AccessType_of_num:int -> riscv_sequential_types$AccessType) arg_= - (let l__74 = arg_ in - if (((l__74 = (( 0 : int):sail_values$ii)))) then Read - else if (((l__74 = (( 1 : int):sail_values$ii)))) then Write - else if (((l__74 = (( 2 : int):sail_values$ii)))) then ReadWrite - else Execute))`; - - -(*val num_of_AccessType : Riscv_sequential_types.AccessType -> Num.integer*) - -val _ = Define ` - ((num_of_AccessType:riscv_sequential_types$AccessType -> int) arg_= - ((case arg_ of Read => (( 0 : int):sail_values$ii) | Write => (( 1 : int):sail_values$ii) | ReadWrite => (( 2 : int):sail_values$ii) | Execute => (( 3 : int):sail_values$ii) )))`; - - -(*val ReadType_of_num : Num.integer -> Riscv_sequential_types.ReadType*) - -val _ = Define ` - ((ReadType_of_num:int -> riscv_sequential_types$ReadType) arg_= - (let l__73 = arg_ in - if (((l__73 = (( 0 : int):sail_values$ii)))) then Instruction - else Data))`; - - -(*val num_of_ReadType : Riscv_sequential_types.ReadType -> Num.integer*) - -val _ = Define ` - ((num_of_ReadType:riscv_sequential_types$ReadType -> int) arg_= ((case arg_ of Instruction => (( 0 : int):sail_values$ii) | Data => (( 1 : int):sail_values$ii) )))`; - - -(*val ExceptionType_of_num : Num.integer -> Riscv_sequential_types.ExceptionType*) - -val _ = Define ` - ((ExceptionType_of_num:int -> riscv_sequential_types$ExceptionType) arg_= - (let l__58 = arg_ in - if (((l__58 = (( 0 : int):sail_values$ii)))) then E_Fetch_Addr_Align - else if (((l__58 = (( 1 : int):sail_values$ii)))) then E_Fetch_Access_Fault - else if (((l__58 = (( 2 : int):sail_values$ii)))) then E_Illegal_Instr - else if (((l__58 = (( 3 : int):sail_values$ii)))) then E_Breakpoint - else if (((l__58 = (( 4 : int):sail_values$ii)))) then E_Load_Addr_Align - else if (((l__58 = (( 5 : int):sail_values$ii)))) then E_Load_Access_Fault - else if (((l__58 = (( 6 : int):sail_values$ii)))) then E_SAMO_Addr_Align - else if (((l__58 = (( 7 : int):sail_values$ii)))) then E_SAMO_Access_Fault - else if (((l__58 = (( 8 : int):sail_values$ii)))) then E_U_EnvCall - else if (((l__58 = (( 9 : int):sail_values$ii)))) then E_S_EnvCall - else if (((l__58 = (( 10 : int):sail_values$ii)))) then E_Reserved_10 - else if (((l__58 = (( 11 : int):sail_values$ii)))) then E_M_EnvCall - else if (((l__58 = (( 12 : int):sail_values$ii)))) then E_Fetch_Page_Fault - else if (((l__58 = (( 13 : int):sail_values$ii)))) then E_Load_Page_Fault - else if (((l__58 = (( 14 : int):sail_values$ii)))) then E_Reserved_14 - else E_SAMO_Page_Fault))`; - - -(*val num_of_ExceptionType : Riscv_sequential_types.ExceptionType -> Num.integer*) - -val _ = Define ` - ((num_of_ExceptionType:riscv_sequential_types$ExceptionType -> int) arg_= - ((case arg_ of - E_Fetch_Addr_Align => (( 0 : int):sail_values$ii) - | E_Fetch_Access_Fault => (( 1 : int):sail_values$ii) - | E_Illegal_Instr => (( 2 : int):sail_values$ii) - | E_Breakpoint => (( 3 : int):sail_values$ii) - | E_Load_Addr_Align => (( 4 : int):sail_values$ii) - | E_Load_Access_Fault => (( 5 : int):sail_values$ii) - | E_SAMO_Addr_Align => (( 6 : int):sail_values$ii) - | E_SAMO_Access_Fault => (( 7 : int):sail_values$ii) - | E_U_EnvCall => (( 8 : int):sail_values$ii) - | E_S_EnvCall => (( 9 : int):sail_values$ii) - | E_Reserved_10 => (( 10 : int):sail_values$ii) - | E_M_EnvCall => (( 11 : int):sail_values$ii) - | E_Fetch_Page_Fault => (( 12 : int):sail_values$ii) - | E_Load_Page_Fault => (( 13 : int):sail_values$ii) - | E_Reserved_14 => (( 14 : int):sail_values$ii) - | E_SAMO_Page_Fault => (( 15 : int):sail_values$ii) - )))`; - - -(*val exceptionType_to_bits : Riscv_sequential_types.ExceptionType -> Machine_word.mword Machine_word.ty4*) - -val _ = Define ` - ((exceptionType_to_bits:riscv_sequential_types$ExceptionType ->(4)words$word) e= - ((case e of - E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) - | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) - | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : 4 words$word) - | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) - | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) - | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) - | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : 4 words$word) - | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) - | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) - | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) - | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : 4 words$word) - | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) - | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : 4 words$word) - | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : 4 words$word) - | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : 4 words$word) - | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : 4 words$word) - )))`; - - -(*val exceptionType_to_str : Riscv_sequential_types.ExceptionType -> string*) - -val _ = Define ` - ((exceptionType_to_str:riscv_sequential_types$ExceptionType -> string) e= - ((case e of - E_Fetch_Addr_Align => "fisaligned-fetch" - | E_Fetch_Access_Fault => "fetch-access-fault" - | E_Illegal_Instr => "illegal-instruction" - | E_Breakpoint => "breakpoint" - | E_Load_Addr_Align => "misaligned-load" - | E_Load_Access_Fault => "load-access-fault" - | E_SAMO_Addr_Align => "misaliged-store/amo" - | E_SAMO_Access_Fault => "store/amo-access-fault" - | E_U_EnvCall => "u-call" - | E_S_EnvCall => "s-call" - | E_Reserved_10 => "reserved-0" - | E_M_EnvCall => "m-call" - | E_Fetch_Page_Fault => "fetch-page-fault" - | E_Load_Page_Fault => "load-page-fault" - | E_Reserved_14 => "reserved-1" - | E_SAMO_Page_Fault => "store/amo-page-fault" - )))`; - - -(*val InterruptType_of_num : Num.integer -> Riscv_sequential_types.InterruptType*) - -val _ = Define ` - ((InterruptType_of_num:int -> riscv_sequential_types$InterruptType) arg_= - (let l__50 = arg_ in - if (((l__50 = (( 0 : int):sail_values$ii)))) then I_U_Software - else if (((l__50 = (( 1 : int):sail_values$ii)))) then I_S_Software - else if (((l__50 = (( 2 : int):sail_values$ii)))) then I_M_Software - else if (((l__50 = (( 3 : int):sail_values$ii)))) then I_U_Timer - else if (((l__50 = (( 4 : int):sail_values$ii)))) then I_S_Timer - else if (((l__50 = (( 5 : int):sail_values$ii)))) then I_M_Timer - else if (((l__50 = (( 6 : int):sail_values$ii)))) then I_U_External - else if (((l__50 = (( 7 : int):sail_values$ii)))) then I_S_External - else I_M_External))`; - - -(*val num_of_InterruptType : Riscv_sequential_types.InterruptType -> Num.integer*) - -val _ = Define ` - ((num_of_InterruptType:riscv_sequential_types$InterruptType -> int) arg_= - ((case arg_ of - I_U_Software => (( 0 : int):sail_values$ii) - | I_S_Software => (( 1 : int):sail_values$ii) - | I_M_Software => (( 2 : int):sail_values$ii) - | I_U_Timer => (( 3 : int):sail_values$ii) - | I_S_Timer => (( 4 : int):sail_values$ii) - | I_M_Timer => (( 5 : int):sail_values$ii) - | I_U_External => (( 6 : int):sail_values$ii) - | I_S_External => (( 7 : int):sail_values$ii) - | I_M_External => (( 8 : int):sail_values$ii) - )))`; - - -(*val interruptType_to_bits : Riscv_sequential_types.InterruptType -> Machine_word.mword Machine_word.ty4*) - -val _ = Define ` - ((interruptType_to_bits:riscv_sequential_types$InterruptType ->(4)words$word) i= - ((case i of - I_U_Software => (vec_of_bits [B0;B0;B0;B0] : 4 words$word) - | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : 4 words$word) - | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : 4 words$word) - | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : 4 words$word) - | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : 4 words$word) - | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : 4 words$word) - | I_U_External => (vec_of_bits [B1;B0;B0;B0] : 4 words$word) - | I_S_External => (vec_of_bits [B1;B0;B0;B1] : 4 words$word) - | I_M_External => (vec_of_bits [B1;B0;B1;B1] : 4 words$word) - )))`; - - -(*val TrapVectorMode_of_num : Num.integer -> Riscv_sequential_types.TrapVectorMode*) - -val _ = Define ` - ((TrapVectorMode_of_num:int -> riscv_sequential_types$TrapVectorMode) arg_= - (let l__48 = arg_ in - if (((l__48 = (( 0 : int):sail_values$ii)))) then TV_Direct - else if (((l__48 = (( 1 : int):sail_values$ii)))) then TV_Vector - else TV_Reserved))`; - - -(*val num_of_TrapVectorMode : Riscv_sequential_types.TrapVectorMode -> Num.integer*) - -val _ = Define ` - ((num_of_TrapVectorMode:riscv_sequential_types$TrapVectorMode -> int) arg_= - ((case arg_ of TV_Direct => (( 0 : int):sail_values$ii) | TV_Vector => (( 1 : int):sail_values$ii) | TV_Reserved => (( 2 : int):sail_values$ii) )))`; - - -(*val trapVectorMode_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.TrapVectorMode*) - -val _ = Define ` - ((trapVectorMode_of_bits:(2)words$word -> riscv_sequential_types$TrapVectorMode) m= - (let b__0 = m in - if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then TV_Direct - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then TV_Vector - else TV_Reserved))`; - - -(*val not_implemented : forall 'a. string -> Riscv_sequential_types.M 'a*) - -val _ = Define ` - ((not_implemented:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) message= (throwS (Error_not_implemented message)))`; - - -(*val internal_error : forall 'a. string -> Riscv_sequential_types.M 'a*) - -val _ = Define ` - ((internal_error:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) s= (seqS (assert_expS F s) (throwS (Error_internal_error () ))))`; - - -(*val ExtStatus_of_num : Num.integer -> Riscv_sequential_types.ExtStatus*) - -val _ = Define ` - ((ExtStatus_of_num:int -> riscv_sequential_types$ExtStatus) arg_= - (let l__45 = arg_ in - if (((l__45 = (( 0 : int):sail_values$ii)))) then Off - else if (((l__45 = (( 1 : int):sail_values$ii)))) then Initial - else if (((l__45 = (( 2 : int):sail_values$ii)))) then Clean - else Dirty))`; - - -(*val num_of_ExtStatus : Riscv_sequential_types.ExtStatus -> Num.integer*) - -val _ = Define ` - ((num_of_ExtStatus:riscv_sequential_types$ExtStatus -> int) arg_= - ((case arg_ of Off => (( 0 : int):sail_values$ii) | Initial => (( 1 : int):sail_values$ii) | Clean => (( 2 : int):sail_values$ii) | Dirty => (( 3 : int):sail_values$ii) )))`; - - -(*val extStatus_to_bits : Riscv_sequential_types.ExtStatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((extStatus_to_bits:riscv_sequential_types$ExtStatus ->(2)words$word) e= - ((case e of - Off => (vec_of_bits [B0;B0] : 2 words$word) - | Initial => (vec_of_bits [B0;B1] : 2 words$word) - | Clean => (vec_of_bits [B1;B0] : 2 words$word) - | Dirty => (vec_of_bits [B1;B1] : 2 words$word) - )))`; - - -(*val extStatus_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.ExtStatus*) - -val _ = Define ` - ((extStatus_of_bits:(2)words$word -> riscv_sequential_types$ExtStatus) e= - (let b__0 = e in - if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Off - else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Initial - else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then Clean - else Dirty))`; - - -(*val SATPMode_of_num : Num.integer -> Riscv_sequential_types.SATPMode*) - -val _ = Define ` - ((SATPMode_of_num:int -> riscv_sequential_types$SATPMode) arg_= - (let l__43 = arg_ in - if (((l__43 = (( 0 : int):sail_values$ii)))) then Sbare - else if (((l__43 = (( 1 : int):sail_values$ii)))) then Sv32 - else Sv39))`; - - -(*val num_of_SATPMode : Riscv_sequential_types.SATPMode -> Num.integer*) - -val _ = Define ` - ((num_of_SATPMode:riscv_sequential_types$SATPMode -> int) arg_= ((case arg_ of Sbare => (( 0 : int):sail_values$ii) | Sv32 => (( 1 : int):sail_values$ii) | Sv39 => (( 2 : int):sail_values$ii) )))`; - - -(*val satpMode_of_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty4 -> Maybe.maybe Riscv_sequential_types.SATPMode*) - -val _ = Define ` - ((satpMode_of_bits:riscv_sequential_types$Architecture ->(4)words$word ->(riscv_sequential_types$SATPMode)option) (a : riscv_sequential_types$Architecture) (m : riscv_sequential_types$satp_mode)= - ((case (a, m) of (g__113, b__0) => SOME Sbare )))`; - - -(*val uop_of_num : Num.integer -> Riscv_sequential_types.uop*) - -val _ = Define ` - ((uop_of_num:int -> riscv_sequential_types$uop) arg_= - (let l__42 = arg_ in - if (((l__42 = (( 0 : int):sail_values$ii)))) then RISCV_LUI - else RISCV_AUIPC))`; - - -(*val num_of_uop : Riscv_sequential_types.uop -> Num.integer*) - -val _ = Define ` - ((num_of_uop:riscv_sequential_types$uop -> int) arg_= ((case arg_ of RISCV_LUI => (( 0 : int):sail_values$ii) | RISCV_AUIPC => (( 1 : int):sail_values$ii) )))`; - - -(*val bop_of_num : Num.integer -> Riscv_sequential_types.bop*) - -val _ = Define ` - ((bop_of_num:int -> riscv_sequential_types$bop) arg_= - (let l__37 = arg_ in - if (((l__37 = (( 0 : int):sail_values$ii)))) then RISCV_BEQ - else if (((l__37 = (( 1 : int):sail_values$ii)))) then RISCV_BNE - else if (((l__37 = (( 2 : int):sail_values$ii)))) then RISCV_BLT - else if (((l__37 = (( 3 : int):sail_values$ii)))) then RISCV_BGE - else if (((l__37 = (( 4 : int):sail_values$ii)))) then RISCV_BLTU - else RISCV_BGEU))`; - - -(*val num_of_bop : Riscv_sequential_types.bop -> Num.integer*) - -val _ = Define ` - ((num_of_bop:riscv_sequential_types$bop -> int) arg_= - ((case arg_ of - RISCV_BEQ => (( 0 : int):sail_values$ii) - | RISCV_BNE => (( 1 : int):sail_values$ii) - | RISCV_BLT => (( 2 : int):sail_values$ii) - | RISCV_BGE => (( 3 : int):sail_values$ii) - | RISCV_BLTU => (( 4 : int):sail_values$ii) - | RISCV_BGEU => (( 5 : int):sail_values$ii) - )))`; - - -(*val iop_of_num : Num.integer -> Riscv_sequential_types.iop*) - -val _ = Define ` - ((iop_of_num:int -> riscv_sequential_types$iop) arg_= - (let l__32 = arg_ in - if (((l__32 = (( 0 : int):sail_values$ii)))) then RISCV_ADDI - else if (((l__32 = (( 1 : int):sail_values$ii)))) then RISCV_SLTI - else if (((l__32 = (( 2 : int):sail_values$ii)))) then RISCV_SLTIU - else if (((l__32 = (( 3 : int):sail_values$ii)))) then RISCV_XORI - else if (((l__32 = (( 4 : int):sail_values$ii)))) then RISCV_ORI - else RISCV_ANDI))`; - - -(*val num_of_iop : Riscv_sequential_types.iop -> Num.integer*) - -val _ = Define ` - ((num_of_iop:riscv_sequential_types$iop -> int) arg_= - ((case arg_ of - RISCV_ADDI => (( 0 : int):sail_values$ii) - | RISCV_SLTI => (( 1 : int):sail_values$ii) - | RISCV_SLTIU => (( 2 : int):sail_values$ii) - | RISCV_XORI => (( 3 : int):sail_values$ii) - | RISCV_ORI => (( 4 : int):sail_values$ii) - | RISCV_ANDI => (( 5 : int):sail_values$ii) - )))`; - - -(*val sop_of_num : Num.integer -> Riscv_sequential_types.sop*) - -val _ = Define ` - ((sop_of_num:int -> riscv_sequential_types$sop) arg_= - (let l__30 = arg_ in - if (((l__30 = (( 0 : int):sail_values$ii)))) then RISCV_SLLI - else if (((l__30 = (( 1 : int):sail_values$ii)))) then RISCV_SRLI - else RISCV_SRAI))`; - - -(*val num_of_sop : Riscv_sequential_types.sop -> Num.integer*) - -val _ = Define ` - ((num_of_sop:riscv_sequential_types$sop -> int) arg_= - ((case arg_ of RISCV_SLLI => (( 0 : int):sail_values$ii) | RISCV_SRLI => (( 1 : int):sail_values$ii) | RISCV_SRAI => (( 2 : int):sail_values$ii) )))`; - - -(*val rop_of_num : Num.integer -> Riscv_sequential_types.rop*) - -val _ = Define ` - ((rop_of_num:int -> riscv_sequential_types$rop) arg_= - (let l__21 = arg_ in - if (((l__21 = (( 0 : int):sail_values$ii)))) then RISCV_ADD - else if (((l__21 = (( 1 : int):sail_values$ii)))) then RISCV_SUB - else if (((l__21 = (( 2 : int):sail_values$ii)))) then RISCV_SLL - else if (((l__21 = (( 3 : int):sail_values$ii)))) then RISCV_SLT - else if (((l__21 = (( 4 : int):sail_values$ii)))) then RISCV_SLTU - else if (((l__21 = (( 5 : int):sail_values$ii)))) then RISCV_XOR - else if (((l__21 = (( 6 : int):sail_values$ii)))) then RISCV_SRL - else if (((l__21 = (( 7 : int):sail_values$ii)))) then RISCV_SRA - else if (((l__21 = (( 8 : int):sail_values$ii)))) then RISCV_OR - else RISCV_AND))`; - - -(*val num_of_rop : Riscv_sequential_types.rop -> Num.integer*) - -val _ = Define ` - ((num_of_rop:riscv_sequential_types$rop -> int) arg_= - ((case arg_ of - RISCV_ADD => (( 0 : int):sail_values$ii) - | RISCV_SUB => (( 1 : int):sail_values$ii) - | RISCV_SLL => (( 2 : int):sail_values$ii) - | RISCV_SLT => (( 3 : int):sail_values$ii) - | RISCV_SLTU => (( 4 : int):sail_values$ii) - | RISCV_XOR => (( 5 : int):sail_values$ii) - | RISCV_SRL => (( 6 : int):sail_values$ii) - | RISCV_SRA => (( 7 : int):sail_values$ii) - | RISCV_OR => (( 8 : int):sail_values$ii) - | RISCV_AND => (( 9 : int):sail_values$ii) - )))`; - - -(*val ropw_of_num : Num.integer -> Riscv_sequential_types.ropw*) - -val _ = Define ` - ((ropw_of_num:int -> riscv_sequential_types$ropw) arg_= - (let l__17 = arg_ in - if (((l__17 = (( 0 : int):sail_values$ii)))) then RISCV_ADDW - else if (((l__17 = (( 1 : int):sail_values$ii)))) then RISCV_SUBW - else if (((l__17 = (( 2 : int):sail_values$ii)))) then RISCV_SLLW - else if (((l__17 = (( 3 : int):sail_values$ii)))) then RISCV_SRLW - else RISCV_SRAW))`; - - -(*val num_of_ropw : Riscv_sequential_types.ropw -> Num.integer*) - -val _ = Define ` - ((num_of_ropw:riscv_sequential_types$ropw -> int) arg_= - ((case arg_ of - RISCV_ADDW => (( 0 : int):sail_values$ii) - | RISCV_SUBW => (( 1 : int):sail_values$ii) - | RISCV_SLLW => (( 2 : int):sail_values$ii) - | RISCV_SRLW => (( 3 : int):sail_values$ii) - | RISCV_SRAW => (( 4 : int):sail_values$ii) - )))`; - - -(*val amoop_of_num : Num.integer -> Riscv_sequential_types.amoop*) - -val _ = Define ` - ((amoop_of_num:int -> riscv_sequential_types$amoop) arg_= - (let l__9 = arg_ in - if (((l__9 = (( 0 : int):sail_values$ii)))) then AMOSWAP - else if (((l__9 = (( 1 : int):sail_values$ii)))) then AMOADD - else if (((l__9 = (( 2 : int):sail_values$ii)))) then AMOXOR - else if (((l__9 = (( 3 : int):sail_values$ii)))) then AMOAND - else if (((l__9 = (( 4 : int):sail_values$ii)))) then AMOOR - else if (((l__9 = (( 5 : int):sail_values$ii)))) then AMOMIN - else if (((l__9 = (( 6 : int):sail_values$ii)))) then AMOMAX - else if (((l__9 = (( 7 : int):sail_values$ii)))) then AMOMINU - else AMOMAXU))`; - - -(*val num_of_amoop : Riscv_sequential_types.amoop -> Num.integer*) - -val _ = Define ` - ((num_of_amoop:riscv_sequential_types$amoop -> int) arg_= - ((case arg_ of - AMOSWAP => (( 0 : int):sail_values$ii) - | AMOADD => (( 1 : int):sail_values$ii) - | AMOXOR => (( 2 : int):sail_values$ii) - | AMOAND => (( 3 : int):sail_values$ii) - | AMOOR => (( 4 : int):sail_values$ii) - | AMOMIN => (( 5 : int):sail_values$ii) - | AMOMAX => (( 6 : int):sail_values$ii) - | AMOMINU => (( 7 : int):sail_values$ii) - | AMOMAXU => (( 8 : int):sail_values$ii) - )))`; - - -(*val csrop_of_num : Num.integer -> Riscv_sequential_types.csrop*) - -val _ = Define ` - ((csrop_of_num:int -> riscv_sequential_types$csrop) arg_= - (let l__7 = arg_ in - if (((l__7 = (( 0 : int):sail_values$ii)))) then CSRRW - else if (((l__7 = (( 1 : int):sail_values$ii)))) then CSRRS - else CSRRC))`; - - -(*val num_of_csrop : Riscv_sequential_types.csrop -> Num.integer*) - -val _ = Define ` - ((num_of_csrop:riscv_sequential_types$csrop -> int) arg_= ((case arg_ of CSRRW => (( 0 : int):sail_values$ii) | CSRRS => (( 1 : int):sail_values$ii) | CSRRC => (( 2 : int):sail_values$ii) )))`; - - -(*val word_width_of_num : Num.integer -> Riscv_sequential_types.word_width*) - -val _ = Define ` - ((word_width_of_num:int -> riscv_sequential_types$word_width) arg_= - (let l__4 = arg_ in - if (((l__4 = (( 0 : int):sail_values$ii)))) then BYTE - else if (((l__4 = (( 1 : int):sail_values$ii)))) then HALF - else if (((l__4 = (( 2 : int):sail_values$ii)))) then WORD - else DOUBLE))`; - - -(*val num_of_word_width : Riscv_sequential_types.word_width -> Num.integer*) - -val _ = Define ` - ((num_of_word_width:riscv_sequential_types$word_width -> int) arg_= - ((case arg_ of BYTE => (( 0 : int):sail_values$ii) | HALF => (( 1 : int):sail_values$ii) | WORD => (( 2 : int):sail_values$ii) | DOUBLE => (( 3 : int):sail_values$ii) )))`; - - -(*val is_aligned_addr : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool*) - -val _ = Define ` - ((is_aligned_addr:(64)words$word -> int -> bool) (addr : riscv_sequential_types$xlenbits) (width : int)= - (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):sail_values$ii)))`; - - -(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => Riscv_sequential_types.ReadType -> Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -val _ = Define ` - ((checked_mem_read:riscv_sequential_types$ReadType ->(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (t : riscv_sequential_types$ReadType) (addr : riscv_sequential_types$xlenbits) (width : int)= (bindS - (RISCV_read addr width : ( ( 'int8_times_n words$word)option) riscv_sequential_types$M) (\ (w__0 : - ( 'int8_times_n words$word)option) . - returnS ((case (t, w__0) of - (Instruction, NONE) => MemException E_Fetch_Access_Fault - | (Data, NONE) => MemException E_Load_Access_Fault - | (_, SOME (v)) => MemValue v - )))))`; - - -(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -val _ = Define ` - ((MEMr:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -val _ = Define ` - ((MEMr_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -val _ = Define ` - ((MEMr_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -val _ = Define ` - ((MEMr_reserved:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -val _ = Define ` - ((MEMr_reserved_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -val _ = Define ` - ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`; - - -(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*) - -val _ = Define ` - ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl res= - (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then - returnS (MemException E_Load_Addr_Align) - else - (case (aq, rl, res) of - (F, F, F) => (MEMr addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - | (T, F, F) => (MEMr_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - | (F, F, T) => - (MEMr_reserved addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - | (T, F, T) => - (MEMr_reserved_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - | (F, T, F) => throwS (Error_not_implemented "load.rl") - | (T, T, F) => - (MEMr_strong_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - | (F, T, T) => throwS (Error_not_implemented "lr.rl") - | (T, T, T) => - (MEMr_reserved_strong_acquire addr width : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - )))`; - - -(*val mem_write_ea : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -val _ = Define ` - ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl con= - (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then - returnS (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (F, F, F) => seqS (MEMea addr width) (returnS (MemValue () )) - | (F, T, F) => seqS (MEMea_release addr width) (returnS (MemValue () )) - | (F, F, T) => seqS (MEMea_conditional addr width) (returnS (MemValue () )) - | (F, T, T) => seqS (MEMea_conditional_release addr width) (returnS (MemValue () )) - | (T, F, F) => throwS (Error_not_implemented "store.aq") - | (T, T, F) => seqS (MEMea_strong_release addr width) (returnS (MemValue () )) - | (T, F, T) => throwS (Error_not_implemented "sc.aq") - | (T, T, T) => seqS (MEMea_conditional_strong_release addr width) (returnS (MemValue () )) - )))`; - - -(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -val _ = Define ` - ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (width : int) (data : 'int8_times_n riscv_sequential_types$bits)= (bindS -(RISCV_write addr width data) (\ (w__0 : bool) . - returnS (if w__0 then MemValue () - else MemException E_SAMO_Access_Fault))))`; - - -(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -val _ = Define ` - ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -val _ = Define ` - ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -val _ = Define ` - ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -val _ = Define ` - ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -val _ = Define ` - ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -val _ = Define ` - ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; - - -(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*) - -val _ = Define ` - ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width value aq rl con= - (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then - returnS (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (F, F, F) => MEMval addr width value - | (F, T, F) => MEMval_release addr width value - | (F, F, T) => MEMval_conditional addr width value - | (F, T, T) => MEMval_conditional_release addr width value - | (T, F, F) => throwS (Error_not_implemented "store.aq") - | (T, T, F) => MEMval_strong_release addr width value - | (T, F, T) => throwS (Error_not_implemented "sc.aq") - | (T, T, T) => MEMval_conditional_strong_release addr width value - )))`; - - -(*val _get_Misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Misa:riscv_sequential_types$Misa ->(64)words$word) (Mk_Misa (v))= v)`; - - -(*val _set_Misa : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Misa v) in - write_regS r_ref r)))`; - - -(*val _get_SV39_PTE : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64*) - -(*val _set_SV39_PTE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Misa_MXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_MXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_Z:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_Z : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_Z:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_Z:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_Y:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_Y : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_Y:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_Y:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_X:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_X:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_W:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_W:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_V:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_V:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_U:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_U:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_T:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_T : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_T:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_T:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_S:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_S : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_S:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_S:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_R:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_R:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_Q:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_Q : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_Q:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_Q:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_P:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_P : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_P:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_P:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_O:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_O : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_O:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_O:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_N:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_N : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_N:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_N:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_M:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_M : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_M:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_M:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_L:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_L : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_L:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_L:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_K:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_K : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_K:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_K:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_J:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_J : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_J:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_J:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_I:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_I : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_I:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_I:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_H:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_H : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_H:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_H:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_G:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_G:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_F:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_F : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_F:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_F:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_E:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_E : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_E:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_E:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_D:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_D:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_C:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_C : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_C:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_C:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_B:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_B : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_B:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_B:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Misa_A:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Misa_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Misa_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Misa r))))`; - - -(*val _update_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((update_Misa_A:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*) - -(*val _get_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*) - -(*val _set_PTE_Bits_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val legalize_misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Misa*) - -val _ = Define ` - ((legalize_misa:riscv_sequential_types$Misa ->(64)words$word -> riscv_sequential_types$Misa) (m : riscv_sequential_types$Misa) (v : riscv_sequential_types$xlenbits)= m)`; - - -(*val _get_Mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Mstatus:riscv_sequential_types$Mstatus ->(64)words$word) (Mk_Mstatus (v))= v)`; - - -(*val _set_Mstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Mstatus v) in - write_regS r_ref r)))`; - - -(*val _get_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mstatus_SXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) - -(*val _set_Sstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_TSR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_TSR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_TW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_TW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_TVM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_TVM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_MPRV : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_MPRV:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) - -(*val _set_Sstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*) - -(*val _set_Sstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mstatus_MPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_MPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_MPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_MPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_MIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_MIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mstatus r))))`; - - -(*val _update_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((update_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*) - -(*val _get_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val legalize_mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((legalize_mstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (o1 : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)= - (let (m : riscv_sequential_types$Mstatus) = (Mk_Mstatus v) in - let m = (update_Mstatus_XS m ((extStatus_to_bits Off : 2 words$word))) in - let m = -(update_Mstatus_SD m - ((bool_to_bits - ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m : 2 words$word)))) - : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word))))) \/ (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m : 2 words$word)))) - : 2 words$word)) = ((extStatus_to_bits Dirty : 2 words$word)))))))) - : 1 words$word))) in - let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1 : 2 words$word))) in - let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1 : 2 words$word))) in - let m = (update_Mstatus_UPIE m ((bool_to_bits F : 1 words$word))) in - update_Mstatus_UIE m ((bool_to_bits F : 1 words$word))))`; - - -(*val cur_Architecture : unit -> Riscv_sequential_types.M Riscv_sequential_types.Architecture*) - -val _ = Define ` - ((cur_Architecture:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Architecture),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS - (case w__0 of - Machine => bindS -(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) . returnS ((get_Misa_MXL w__1 : 2 words$word))) - | Supervisor => bindS -(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . - returnS ((get_Mstatus_SXL w__2 : 2 words$word))) - | User => bindS -(read_regS mstatus_ref) (\ (w__3 : riscv_sequential_types$Mstatus) . - returnS ((get_Mstatus_UXL w__3 : 2 words$word))) - ) (\ (a : riscv_sequential_types$arch_xlen) . - (case ((architecture a)) of - SOME (a) => returnS a - | NONE => internal_error "Invalid current architecture" - )))))`; - - -(*val in32BitMode : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((in32BitMode:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (cur_Architecture () ) (\ (w__0 : riscv_sequential_types$Architecture) . returnS (((w__0 = RV32))))))`; - - -(*val haveAtomics : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((haveAtomics:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . - returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; - - -(*val haveRVC : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((haveRVC:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . - returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; - - -(*val haveMulDiv : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((haveMulDiv:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . - returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; - - -(*val haveFP : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((haveFP:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . bindS -(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) . - returnS ((((((((get_Misa_F w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ (((((get_Misa_D w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))))))`; - - -(*val _get_Minterrupts : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Minterrupts:riscv_sequential_types$Minterrupts ->(64)words$word) (Mk_Minterrupts (v))= v)`; - - -(*val _set_Minterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Minterrupts v) in - write_regS r_ref r)))`; - - -(*val _get_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_MEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_MEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_MTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_MTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_MSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_MSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Minterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Minterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Minterrupts r))))`; - - -(*val _update_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((update_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*) - -(*val _get_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sinterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val legalize_mip : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((legalize_mip:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= - (let v = (Mk_Minterrupts v) in - let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v : 1 words$word))) in - let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in - update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; - - -(*val legalize_mie : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((legalize_mie:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= - (let v = (Mk_Minterrupts v) in - let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v : 1 words$word))) in - let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v : 1 words$word))) in - let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v : 1 words$word))) in - let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v : 1 words$word))) in - let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v : 1 words$word))) in - update_Minterrupts_SSI m ((get_Minterrupts_SSI v : 1 words$word))))`; - - -(*val legalize_mideleg : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((legalize_mideleg:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= - (let m = (Mk_Minterrupts v) in - let m = (update_Minterrupts_MEI m ((bool_to_bits F : 1 words$word))) in - let m = (update_Minterrupts_MTI m ((bool_to_bits F : 1 words$word))) in - update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`; - - -(*val _get_Medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Medeleg:riscv_sequential_types$Medeleg ->(64)words$word) (Mk_Medeleg (v))= v)`; - - -(*val _set_Medeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Medeleg v) in - write_regS r_ref r)))`; - - -(*val _get_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_SAMO_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_SAMO_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Load_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Load_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Fetch_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Fetch_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_MEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_MEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_SEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_SEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val _get_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Medeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Medeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Medeleg r))))`; - - -(*val _update_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((update_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*) - -(*val _get_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*) - -(*val _set_Sedeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -(*val legalize_medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Medeleg*) - -val _ = Define ` - ((legalize_medeleg:riscv_sequential_types$Medeleg ->(64)words$word -> riscv_sequential_types$Medeleg) (o1 : riscv_sequential_types$Medeleg) (v : riscv_sequential_types$xlenbits)= - (let m = (Mk_Medeleg v) in - update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`; - - -(*val _get_Mtvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Mtvec:riscv_sequential_types$Mtvec ->(64)words$word) (Mk_Mtvec (v))= v)`; - - -(*val _set_Mtvec : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mtvec:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Mtvec v) in - write_regS r_ref r)))`; - - -(*val _get_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62*) - -val _ = Define ` - ((get_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 62 words$word)))`; - - -(*val _set_Mtvec_Base : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mtvec_Base:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(62)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . - let r = ((get_Mtvec w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mtvec r))))`; - - -(*val _update_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.Mtvec*) - -val _ = Define ` - ((update_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x= - (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_Mtvec_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mtvec_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . - let r = ((get_Mtvec w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mtvec r))))`; - - -(*val _update_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mtvec*) - -val _ = Define ` - ((update_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x= - (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _update_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.Satp64*) - -(*val _get_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4*) - -(*val _set_Satp64_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*) - -(*val legalize_tvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mtvec*) - -val _ = Define ` - ((legalize_tvec:riscv_sequential_types$Mtvec ->(64)words$word -> riscv_sequential_types$Mtvec) (o1 : riscv_sequential_types$Mtvec) (v : riscv_sequential_types$xlenbits)= - (let v = (Mk_Mtvec v) in - (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v : 2 words$word)))) of - TV_Direct => v - | TV_Vector => v - | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 : 2 words$word)) - )))`; - - -(*val _get_Mcause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Mcause:riscv_sequential_types$Mcause ->(64)words$word) (Mk_Mcause (v))= v)`; - - -(*val _set_Mcause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mcause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Mcause v) in - write_regS r_ref r)))`; - - -(*val _get_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1*) - -val _ = Define ` - ((get_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; - - -(*val _set_Mcause_IsInterrupt : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mcause_IsInterrupt:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . - let r = ((get_Mcause w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mcause r))))`; - - -(*val _update_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mcause*) - -val _ = Define ` - ((update_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x= - (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63*) - -val _ = Define ` - ((get_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 63 words$word)))`; - - -(*val _set_Mcause_Cause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Mcause_Cause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(63)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . - let r = ((get_Mcause w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Mcause r))))`; - - -(*val _update_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.Mcause*) - -val _ = Define ` - ((update_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x= - (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val tvec_addr : Riscv_sequential_types.Mtvec -> Riscv_sequential_types.Mcause -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((tvec_addr:riscv_sequential_types$Mtvec -> riscv_sequential_types$Mcause ->((64)words$word)option) (m : riscv_sequential_types$Mtvec) (c : riscv_sequential_types$Mcause)= - (let (base : riscv_sequential_types$xlenbits) = -((concat_vec ((get_Mtvec_Base m : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) - : 64 words$word)) in - (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m : 2 words$word)))) of - TV_Direct => SOME base - | TV_Vector => - if (((((get_Mcause_IsInterrupt c : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME ((add_vec base - ((shift_bits_left - ((EXTZ (( 64 : int):sail_values$ii) ((get_Mcause_Cause c : 63 words$word)) : 64 words$word)) - (vec_of_bits [B1;B0] : 2 words$word) - : 64 words$word)) - : 64 words$word)) - else SOME base - | TV_Reserved => NONE - )))`; - - -(*val legalize_xepc : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((legalize_xepc:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) v= (bindS -(haveRVC () ) (\ (w__0 : bool) . - returnS ((and_vec v - ((EXTS (( 64 : int):sail_values$ii) - (if w__0 then (vec_of_bits [B1;B1;B0] : 3 words$word) - else (vec_of_bits [B1;B0;B0] : 3 words$word)) - : 64 words$word)) - : 64 words$word)))))`; - - -(*val _get_Sstatus : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Sstatus:riscv_sequential_types$Sstatus ->(64)words$word) (Mk_Sstatus (v))= v)`; - - -(*val _set_Sstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Sstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Sstatus v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) : 2 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 2 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 2 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sstatus r))))`; - - -val _ = Define ` - ((update_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val lower_mstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus*) - -val _ = Define ` - ((lower_mstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus) m= - (let s = (Mk_Sstatus ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in - let s = (update_Sstatus_SD s ((get_Mstatus_SD m : 1 words$word))) in - let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m : 2 words$word))) in - let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m : 1 words$word))) in - let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m : 1 words$word))) in - let s = (update_Sstatus_XS s ((get_Mstatus_XS m : 2 words$word))) in - let s = (update_Sstatus_FS s ((get_Mstatus_FS m : 2 words$word))) in - let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m : 1 words$word))) in - let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m : 1 words$word))) in - let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m : 1 words$word))) in - let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m : 1 words$word))) in - update_Sstatus_UIE s ((get_Mstatus_UIE m : 1 words$word))))`; - - -(*val lift_sstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((lift_sstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (s : riscv_sequential_types$Sstatus)= - (let m = (update_Mstatus_SD m ((get_Sstatus_SD s : 1 words$word))) in - let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s : 2 words$word))) in - let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in - let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in - let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in - let m = (update_Mstatus_FS m ((get_Sstatus_FS s : 2 words$word))) in - let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s : 1 words$word))) in - let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s : 1 words$word))) in - let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s : 1 words$word))) in - let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s : 1 words$word))) in - update_Mstatus_UIE m ((get_Sstatus_UIE s : 1 words$word))))`; - - -(*val legalize_sstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*) - -val _ = Define ` - ((legalize_sstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)= (lift_sstatus m (Mk_Sstatus v)))`; - - -(*val _get_Sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word) (Mk_Sedeleg (v))= v)`; - - -(*val _set_Sedeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Sedeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Sedeleg v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sedeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sedeleg r))))`; - - -val _ = Define ` - ((update_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val legalize_sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Sedeleg*) - -val _ = Define ` - ((legalize_sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word -> riscv_sequential_types$Sedeleg) (s : riscv_sequential_types$Sedeleg) (v : riscv_sequential_types$xlenbits)= - (Mk_Sedeleg ((EXTZ (( 64 : int):sail_values$ii) ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 9 words$word)) : 64 words$word))))`; - - -(*val _get_Sinterrupts : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Sinterrupts:riscv_sequential_types$Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))= v)`; - - -(*val _set_Sinterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Sinterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Sinterrupts v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 64 words$word))))`; - - -val _ = Define ` - ((get_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_Sinterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Sinterrupts r))))`; - - -val _ = Define ` - ((update_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val lower_mip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*) - -val _ = Define ` - ((lower_mip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)= - (let (s : riscv_sequential_types$Sinterrupts) = -(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in - let s = -(update_Sinterrupts_SEI s - ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_STI s - ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_SSI s - ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_UEI s - ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_UTI s - ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) - : 1 words$word))) in - update_Sinterrupts_USI s - ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) - : 1 words$word))))`; - - -(*val lower_mie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*) - -val _ = Define ` - ((lower_mie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)= - (let (s : riscv_sequential_types$Sinterrupts) = -(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in - let s = -(update_Sinterrupts_SEI s - ((and_vec ((get_Minterrupts_SEI m : 1 words$word)) ((get_Minterrupts_SEI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_STI s - ((and_vec ((get_Minterrupts_STI m : 1 words$word)) ((get_Minterrupts_STI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_SSI s - ((and_vec ((get_Minterrupts_SSI m : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_UEI s - ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) - : 1 words$word))) in - let s = -(update_Sinterrupts_UTI s - ((and_vec ((get_Minterrupts_UTI m : 1 words$word)) ((get_Minterrupts_UTI d : 1 words$word)) - : 1 words$word))) in - update_Sinterrupts_USI s - ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) - : 1 words$word))))`; - - -(*val lift_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((lift_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)= - (let (m : riscv_sequential_types$Minterrupts) = o1 in - let m = -(update_Minterrupts_SSI m - ((and_vec ((get_Sinterrupts_SSI s : 1 words$word)) ((get_Minterrupts_SSI d : 1 words$word)) - : 1 words$word))) in - let m = -(update_Minterrupts_UEI m - ((and_vec ((get_Minterrupts_UEI m : 1 words$word)) ((get_Minterrupts_UEI d : 1 words$word)) - : 1 words$word))) in - update_Minterrupts_USI m - ((and_vec ((get_Minterrupts_USI m : 1 words$word)) ((get_Minterrupts_USI d : 1 words$word)) - : 1 words$word))))`; - - -(*val legalize_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((legalize_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= - (lift_sip m d (Mk_Sinterrupts v)))`; - - -(*val lift_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((lift_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)= - (let (m : riscv_sequential_types$Minterrupts) = o1 in - let m = -(if (((((get_Minterrupts_SEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_SEI m ((get_Sinterrupts_SEI s : 1 words$word)) - else m) in - let m = -(if (((((get_Minterrupts_STI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_STI m ((get_Sinterrupts_STI s : 1 words$word)) - else m) in - let m = -(if (((((get_Minterrupts_SSI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_SSI m ((get_Sinterrupts_SSI s : 1 words$word)) - else m) in - let m = -(if (((((get_Minterrupts_UEI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_UEI m ((get_Sinterrupts_UEI s : 1 words$word)) - else m) in - let m = -(if (((((get_Minterrupts_UTI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_UTI m ((get_Sinterrupts_UTI s : 1 words$word)) - else m) in - if (((((get_Minterrupts_USI d : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - update_Minterrupts_USI m ((get_Sinterrupts_USI s : 1 words$word)) - else m))`; - - -(*val legalize_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*) - -val _ = Define ` - ((legalize_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)= - (lift_sie m d (Mk_Sinterrupts v)))`; - - -(*val _get_Satp64 : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((get_Satp64:riscv_sequential_types$Satp64 ->(64)words$word) (Mk_Satp64 (v))= v)`; - - -(*val _set_Satp64 : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Satp64:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_Satp64 v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) : 4 words$word)))`; - - -val _ = Define ` - ((set_Satp64_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Satp64 r))))`; - - -val _ = Define ` - ((update_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16*) - -val _ = Define ` - ((get_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) : 16 words$word)))`; - - -(*val _set_Satp64_Asid : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Satp64_Asid:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(16)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Satp64 r))))`; - - -(*val _update_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.Satp64*) - -val _ = Define ` - ((update_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44*) - -val _ = Define ` - ((get_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 44 words$word)))`; - - -(*val _set_Satp64_PPN : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_Satp64_PPN:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_Satp64 r))))`; - - -(*val _update_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.Satp64*) - -val _ = Define ` - ((update_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val legalize_satp : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((legalize_satp:riscv_sequential_types$Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : riscv_sequential_types$Architecture) (o1 : riscv_sequential_types$xlenbits) (v : riscv_sequential_types$xlenbits)= - (let s = (Mk_Satp64 v) in - (case ((satpMode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of - NONE => o1 - | SOME (Sv32) => o1 - | SOME (_) => (get_Satp64 s : 64 words$word) - )))`; - - -(*val csr_name : Machine_word.mword Machine_word.ty12 -> string*) - -val _ = Define ` - ((csr_name:(12)words$word -> string) csr= - (let b__0 = csr in - if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "ustatus" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - "uie" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then - "utvec" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "fflags" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "frm" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - "fcsr" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "cycle" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "time" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "instret" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "cycleh" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "timeh" - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "instreth" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "sstatus" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "sedeleg" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - "sideleg" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - "sie" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then - "stvec" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then - "scounteren" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "sscratch" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "sepc" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "scause" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - "stval" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - "sip" - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "satp" - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then - "mvendorid" - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then - "marchid" - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then - "mimpid" - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then - "mhartid" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "mstatus" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "misa" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "medeleg" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - "mideleg" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - "mie" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then - "mtvec" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then - "mcounteren" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "mscratch" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - "mepc" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "mcause" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - "mtval" - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - "mip" - else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "mcycle" - else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "minstret" - else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - "mcycleh" - else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - "minstreth" - else "UNKNOWN"))`; - - -(*val csrAccess : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((csrAccess:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)))`; - - -(*val csrPriv : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((csrPriv:(12)words$word ->(2)words$word) csr= ((subrange_vec_dec csr (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 2 words$word)))`; - - -(*val is_CSR_defined : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool*) - -val _ = Define ` - ((is_CSR_defined:(12)words$word -> riscv_sequential_types$Privilege -> bool) (csr : 12 riscv_sequential_types$bits) (p : riscv_sequential_types$Privilege)= - (let b__0 = csr in - if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - else F))`; - - -(*val check_CSR_access : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege -> bool -> bool*) - -val _ = Define ` - ((check_CSR_access:(2)words$word ->(2)words$word -> riscv_sequential_types$Privilege -> bool -> bool) csrrw csrpr p isWrite= - (((~ ((((((((bool_to_bits isWrite : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((csrrw = (vec_of_bits [B1;B1] : 2 words$word))))))))) /\ ((((lem$w2ui ((privLevel_to_bits p : 2 words$word))) >= (lem$w2ui csrpr))))))`; - - -(*val check_TVM_SATP : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((check_TVM_SATP:(12)words$word -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege)= (bindS -(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - returnS ((~ ((((((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) /\ ((((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))) /\ (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))))))))))`; - - -(*val check_CSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((check_CSR:(12)words$word -> riscv_sequential_types$Privilege -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege) (isWrite : bool)= (bindS -(check_TVM_SATP csr p) (\ (w__0 : bool) . - returnS (((((is_CSR_defined csr p)) /\ (((((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p - isWrite)) /\ w__0)))))))))`; - - -(*val exception_delegatee : Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.Privilege*) - -val _ = Define ` - ((exception_delegatee:riscv_sequential_types$ExceptionType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Privilege),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (e : riscv_sequential_types$ExceptionType) (p : riscv_sequential_types$Privilege)= - (let idx = (num_of_ExceptionType e) in bindS -(read_regS medeleg_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . - let super = (access_vec_dec ((get_Medeleg w__0 : 64 words$word)) idx) in bindS -(read_regS sedeleg_ref) (\ (w__1 : riscv_sequential_types$Sedeleg) . - let user = (access_vec_dec ((get_Sedeleg w__1 : 64 words$word)) idx) in bindS -(read_regS misa_ref) (\ (w__2 : riscv_sequential_types$Misa) . - let deleg = -(if ((((((((get_Misa_S w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((bit_to_bool super))))) then - Supervisor - else Machine) in - returnS (if ((((lem$w2ui ((privLevel_to_bits deleg : 2 words$word))) < (lem$w2ui ((privLevel_to_bits p : 2 words$word)))))) then - p - else deleg))))))`; - - -(*val findPendingInterrupt : Machine_word.mword Machine_word.ty64 -> Maybe.maybe Riscv_sequential_types.InterruptType*) - -val _ = Define ` - ((findPendingInterrupt:(64)words$word ->(riscv_sequential_types$InterruptType)option) ip= - (let ip = (Mk_Minterrupts ip) in - if (((((get_Minterrupts_MEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - SOME I_M_External - else if (((((get_Minterrupts_MSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_M_Software - else if (((((get_Minterrupts_MTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_M_Timer - else if (((((get_Minterrupts_SEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_S_External - else if (((((get_Minterrupts_SSI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_S_Software - else if (((((get_Minterrupts_STI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_S_Timer - else if (((((get_Minterrupts_UEI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_U_External - else if (((((get_Minterrupts_USI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_U_Software - else if (((((get_Minterrupts_UTI ip : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - SOME I_U_Timer - else NONE))`; - - -(*val curInterrupt : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.M (Maybe.maybe ((Riscv_sequential_types.InterruptType * Riscv_sequential_types.Privilege)))*) - -val _ = Define ` - ((curInterrupt:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((riscv_sequential_types$InterruptType#riscv_sequential_types$Privilege)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (pend : riscv_sequential_types$Minterrupts) (enbl : riscv_sequential_types$Minterrupts) (delg : riscv_sequential_types$Minterrupts)= - (let (en_mip : riscv_sequential_types$xlenbits) = -((and_vec ((get_Minterrupts pend : 64 words$word)) ((get_Minterrupts enbl : 64 words$word)) - : 64 words$word)) in - if (((en_mip = ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) then - returnS NONE - else - let eff_mip = -((and_vec en_mip ((not_vec ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) - : 64 words$word)) in - let eff_sip = ((and_vec en_mip ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) in bindS -(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - if ((((((((get_Mstatus_MIE w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((eff_mip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))) then - returnS ((case ((findPendingInterrupt eff_mip)) of - SOME (i) => - let r = (i, Machine) in - SOME r - | NONE => NONE - )) - else bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS -(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) . bindS -(read_regS cur_privilege_ref) (\ (w__3 : riscv_sequential_types$Privilege) . - returnS (if ((((((((get_Mstatus_SIE w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((eff_sip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) /\ ((((((((privLevel_to_bits w__2 : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))) \/ (((((privLevel_to_bits w__3 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))))))))))) then - (case ((findPendingInterrupt eff_sip)) of - SOME (i) => - let r = (i, Supervisor) in - SOME r - | NONE => NONE - ) - else NONE)))))))`; - - -(*val tval : Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Machine_word.mword Machine_word.ty64*) - -val _ = Define ` - ((tval:((64)words$word)option ->(64)words$word) excinfo= - ((case excinfo of - SOME (e) => e - | NONE => (EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word) - )))`; - - -(*val handle_trap : Riscv_sequential_types.Privilege -> bool -> Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty64 -> Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((handle_trap:riscv_sequential_types$Privilege -> bool ->(4)words$word ->(64)words$word ->(riscv_sequential_types$xlenbits)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (del_priv : riscv_sequential_types$Privilege) (intr : bool) (c : riscv_sequential_types$exc_code) (pc : riscv_sequential_types$xlenbits) (info : - riscv_sequential_types$xlenbits option)= - (let (_ : unit) = -(prerr_endline - ((STRCAT "handling " - ((STRCAT (if intr then "int#" else "exc#") - ((STRCAT ((string_of_vec c)) - ((STRCAT " at priv " ((privLevel_to_str del_priv))))))))))) in - (case del_priv of - Machine => bindS (seqS (seqS -(set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word))) -(set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):sail_values$ii) c : 63 words$word)))) -(read_regS mstatus_ref)) (\ (w__0 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word))) -(set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word)))) -(read_regS cur_privilege_ref)) (\ (w__1 : riscv_sequential_types$Privilege) . bindS (seqS (seqS (seqS (seqS -(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word))) -(write_regS mtval_ref ((tval info : 64 words$word)))) -(write_regS mepc_ref pc)) -(write_regS cur_privilege_ref del_priv)) -(read_regS mtvec_ref)) (\ (w__2 : riscv_sequential_types$Mtvec) . bindS -(read_regS mcause_ref) (\ (w__3 : riscv_sequential_types$Mcause) . - (case ((tvec_addr w__2 w__3 : ( 64 words$word)option)) of - SOME (epc) => returnS epc - | NONE => (internal_error "Invalid mtvec mode" : ( 64 words$word) riscv_sequential_types$M) - ))))) - | Supervisor => bindS (seqS (seqS -(set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))) -(set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):sail_values$ii) c : 63 words$word)))) -(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word))) -(set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word)))) -(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) . bindS - (case w__7 of - User => returnS ((bool_to_bits F : 1 words$word)) - | Supervisor => returnS ((bool_to_bits T : 1 words$word)) - | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) riscv_sequential_types$M) - ) (\ (w__9 : 1 words$word) . bindS (seqS (seqS (seqS (seqS -(set_Mstatus_SPP mstatus_ref w__9) -(write_regS stval_ref ((tval info : 64 words$word)))) -(write_regS sepc_ref pc)) -(write_regS cur_privilege_ref del_priv)) -(read_regS stvec_ref)) (\ (w__10 : riscv_sequential_types$Mtvec) . bindS -(read_regS scause_ref) (\ (w__11 : riscv_sequential_types$Mcause) . - (case ((tvec_addr w__10 w__11 : ( 64 words$word)option)) of - SOME (epc) => returnS epc - | NONE => (internal_error "Invalid stvec mode" : ( 64 words$word) riscv_sequential_types$M) - )))))) - | User => (internal_error "the N extension is currently unsupported" : ( 64 words$word) riscv_sequential_types$M) - )))`; - - -(*val handle_exception : Riscv_sequential_types.Privilege -> Riscv_sequential_types.ctl_result -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((handle_exception:riscv_sequential_types$Privilege -> riscv_sequential_types$ctl_result ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (cur_priv : riscv_sequential_types$Privilege) (ctl : riscv_sequential_types$ctl_result) (pc : riscv_sequential_types$xlenbits)= - ((case (cur_priv, ctl) of - (_, CTL_TRAP (e)) => bindS -(exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . - let (_ : unit) = -(prerr_endline - ((STRCAT "trapping from " - ((STRCAT ((privLevel_to_str cur_priv)) - ((STRCAT " to " - ((STRCAT ((privLevel_to_str del_priv)) - ((STRCAT " to handle " - ((exceptionType_to_str e.sync_exception_trap))))))))))))) in - (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap : 4 words$word)) pc - e.sync_exception_excinfo - : ( 64 words$word) riscv_sequential_types$M)) - | (_, CTL_MRET (_)) => bindS -(read_regS cur_privilege_ref) (\ prev_priv . bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word))) -(set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) -(read_regS mstatus_ref)) (\ (w__2 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) -(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User : 2 words$word)))) -(read_regS cur_privilege_ref)) (\ (w__3 : riscv_sequential_types$Privilege) . - let (_ : unit) = -(prerr_endline - ((STRCAT "ret-ing from " - ((STRCAT ((privLevel_to_str prev_priv)) - ((STRCAT " to " ((privLevel_to_str w__3))))))))) in - (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M))))) - | (_, CTL_SRET (_)) => bindS -(read_regS cur_privilege_ref) (\ prev_priv . bindS -(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 : 1 words$word))) -(set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) -(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) . bindS (seqS (seqS -(write_regS - cur_privilege_ref - (if (((((get_Mstatus_SPP w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) - then - Supervisor - else User)) -(set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word)))) -(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) . - let (_ : unit) = -(prerr_endline - ((STRCAT "ret-ing from " - ((STRCAT ((privLevel_to_str prev_priv)) - ((STRCAT " to " ((privLevel_to_str w__7))))))))) in - (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M))))) - )))`; - - -(*val handle_mem_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((handle_mem_exception:(64)words$word -> riscv_sequential_types$ExceptionType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (e : riscv_sequential_types$ExceptionType)= - (let (t : riscv_sequential_types$sync_exception) = (<| sync_exception_trap := e; sync_exception_excinfo := (SOME addr) |>) in bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS - (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__2)))))`; - - -(*val handle_decode_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((handle_decode_exception:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) instbits= - (let (t : riscv_sequential_types$sync_exception) = -(<| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := (SOME instbits) |>) in bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS - (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__2)))))`; - - -(*val handle_interrupt : Riscv_sequential_types.InterruptType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((handle_interrupt:riscv_sequential_types$InterruptType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (i : riscv_sequential_types$InterruptType) (del_priv : riscv_sequential_types$Privilege)= (bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . bindS - (handle_trap del_priv T ((interruptType_to_bits i : 4 words$word)) w__0 NONE - : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__1))))`; - - -(*val handle_illegal : unit -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((handle_illegal:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = - (let (t : riscv_sequential_types$sync_exception) = -(<| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := NONE |>) in bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . bindS - (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__2)))))`; - - -(*val init_sys : unit -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((init_sys:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS (seqS (seqS (seqS (seqS (seqS -(write_regS cur_privilege_ref Machine) -(set_Misa_MXL misa_ref ((arch_to_bits RV64 : 2 words$word)))) -(set_Misa_C misa_ref ((bool_to_bits T : 1 words$word)))) -(set_Misa_U misa_ref ((bool_to_bits T : 1 words$word)))) -(set_Misa_S misa_ref ((bool_to_bits T : 1 words$word)))) -(read_regS misa_ref)) (\ (w__0 : riscv_sequential_types$Misa) . bindS (seqS -(set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 : 2 words$word))) -(read_regS misa_ref)) (\ (w__1 : riscv_sequential_types$Misa) . seqS (seqS -(set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 : 2 words$word))) -(set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word)))) -(write_regS mhartid_ref ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))`; - - -(*val tick_clock : unit -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((tick_clock:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):sail_values$ii) : 64 words$word)))))`; - - -val _ = Define ` - ((PAGESIZE_BITS:int)= ((( 12 : int):sail_values$ii)))`; - - -(*val _get_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_PTE_Bits:riscv_sequential_types$PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))= v)`; - - -(*val _set_PTE_Bits : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_PTE_Bits:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_PTE_Bits v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x : 8 words$word))))`; - - -val _ = Define ` - ((get_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 1 words$word)))`; - - -val _ = Define ` - ((set_PTE_Bits_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 8 words$word)) in - write_regS r_ref (Mk_PTE_Bits r))))`; - - -val _ = Define ` - ((update_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 8 words$word))))`; - - -(*val isPTEPtr : Machine_word.mword Machine_word.ty8 -> bool*) - -val _ = Define ` - ((isPTEPtr:(8)words$word -> bool) p= - (let a = (Mk_PTE_Bits p) in - ((((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; - - -(*val isInvalidPTE : Machine_word.mword Machine_word.ty8 -> bool*) - -val _ = Define ` - ((isInvalidPTE:(8)words$word -> bool) p= - (let a = (Mk_PTE_Bits p) in - ((((((get_PTE_Bits_V a : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ ((((((((get_PTE_Bits_W a : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_R a : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))))))))`; - - -(*val checkPTEPermission : Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((checkPTEPermission:riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> riscv_sequential_types$PTE_Bits ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (ac : riscv_sequential_types$AccessType) (priv : riscv_sequential_types$Privilege) (mxr : bool) (sum : bool) (p : riscv_sequential_types$PTE_Bits)= - ((case (ac, priv) of - (Read, User) => - returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) - | (Write, User) => - returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) - | (ReadWrite, User) => - returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) - | (Execute, User) => - returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) - | (Read, Supervisor) => - returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) - | (Write, Supervisor) => - returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) - | (ReadWrite, Supervisor) => - returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) - | (Execute, Supervisor) => - returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) - | (_, Machine) => internal_error "m-mode mem perm check" - )))`; - - -(*val update_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.AccessType -> Maybe.maybe Riscv_sequential_types.PTE_Bits*) - -val _ = Define ` - ((update_PTE_Bits:riscv_sequential_types$PTE_Bits -> riscv_sequential_types$AccessType ->(riscv_sequential_types$PTE_Bits)option) (p : riscv_sequential_types$PTE_Bits) (a : riscv_sequential_types$AccessType)= - (let update_d = - (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in - let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in - if (((update_d \/ update_a))) then - let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in - let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T : 1 words$word)) else np) in - SOME np - else NONE))`; - - -(*val PTW_Error_of_num : Num.integer -> Riscv_sequential_types.PTW_Error*) - -val _ = Define ` - ((PTW_Error_of_num:int -> riscv_sequential_types$PTW_Error) arg_= - (let l__0 = arg_ in - if (((l__0 = (( 0 : int):sail_values$ii)))) then PTW_Access - else if (((l__0 = (( 1 : int):sail_values$ii)))) then PTW_Invalid_PTE - else if (((l__0 = (( 2 : int):sail_values$ii)))) then PTW_No_Permission - else if (((l__0 = (( 3 : int):sail_values$ii)))) then PTW_Misaligned - else PTW_PTE_Update))`; - - -(*val num_of_PTW_Error : Riscv_sequential_types.PTW_Error -> Num.integer*) - -val _ = Define ` - ((num_of_PTW_Error:riscv_sequential_types$PTW_Error -> int) arg_= - ((case arg_ of - PTW_Access => (( 0 : int):sail_values$ii) - | PTW_Invalid_PTE => (( 1 : int):sail_values$ii) - | PTW_No_Permission => (( 2 : int):sail_values$ii) - | PTW_Misaligned => (( 3 : int):sail_values$ii) - | PTW_PTE_Update => (( 4 : int):sail_values$ii) - )))`; - - -(*val translationException : Riscv_sequential_types.AccessType -> Riscv_sequential_types.PTW_Error -> Riscv_sequential_types.ExceptionType*) - -val _ = Define ` - ((translationException:riscv_sequential_types$AccessType -> riscv_sequential_types$PTW_Error -> riscv_sequential_types$ExceptionType) (a : riscv_sequential_types$AccessType) (f : riscv_sequential_types$PTW_Error)= - ((case (a, f) of - (Read, PTW_Access) => E_Load_Access_Fault - | (Read, _) => E_Load_Page_Fault - | (Write, PTW_Access) => E_SAMO_Access_Fault - | (Write, _) => E_SAMO_Page_Fault - | (Fetch, PTW_Access) => E_Fetch_Access_Fault - | (Fetch, _) => E_Fetch_Page_Fault - )))`; - - -val _ = Define ` - ((SV39_LEVEL_BITS:int)= ((( 9 : int):sail_values$ii)))`; - - -val _ = Define ` - ((SV39_LEVELS:int)= ((( 3 : int):sail_values$ii)))`; - - -val _ = Define ` - ((PTE39_LOG_SIZE:int)= ((( 3 : int):sail_values$ii)))`; - - -val _ = Define ` - ((PTE39_SIZE:int)= ((( 8 : int):sail_values$ii)))`; - - -(*val _get_SV39_Vaddr : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39*) - -val _ = Define ` - ((get_SV39_Vaddr:riscv_sequential_types$SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))= v)`; - - -(*val _set_SV39_Vaddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_Vaddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_SV39_Vaddr v) in - write_regS r_ref r)))`; - - -(*val _get_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27*) - -val _ = Define ` - ((get_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 27 words$word)))`; - - -(*val _set_SV39_Vaddr_VPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_Vaddr_VPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(27)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . - let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in - let r = ((update_subrange_vec_dec r (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 39 words$word)) in - write_regS r_ref (Mk_SV39_Vaddr r))))`; - - -(*val _update_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.SV39_Vaddr*) - -val _ = Define ` - ((update_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= - (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 39 words$word))))`; - - -(*val _get_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12*) - -val _ = Define ` - ((get_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 12 words$word)))`; - - -(*val _set_SV39_Vaddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_Vaddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . - let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 39 words$word)) in - write_regS r_ref (Mk_SV39_Vaddr r))))`; - - -(*val _update_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Vaddr*) - -val _ = Define ` - ((update_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= - (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 39 words$word))))`; - - -(*val _update_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Paddr*) - -(*val _get_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12*) - -(*val _set_SV39_Paddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*) - -(*val _get_SV39_Paddr : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56*) - -val _ = Define ` - ((get_SV39_Paddr:riscv_sequential_types$SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))= v)`; - - -(*val _set_SV39_Paddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_Paddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_SV39_Paddr v) in - write_regS r_ref r)))`; - - -(*val _get_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44*) - -val _ = Define ` - ((get_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 44 words$word)))`; - - -(*val _set_SV39_Paddr_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_Paddr_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . - let r = ((get_SV39_Paddr w__0 : 56 words$word)) in - let r = ((update_subrange_vec_dec r (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) v : 56 words$word)) in - write_regS r_ref (Mk_SV39_Paddr r))))`; - - -(*val _update_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_Paddr*) - -val _ = Define ` - ((update_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x= - (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) x : 56 words$word))))`; - - -(*val _update_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_PTE*) - -(*val _get_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44*) - -(*val _set_SV39_PTE_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((get_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 12 words$word)))`; - - -val _ = Define ` - ((set_SV39_Paddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . - let r = ((get_SV39_Paddr w__0 : 56 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 56 words$word)) in - write_regS r_ref (Mk_SV39_Paddr r))))`; - - -val _ = Define ` - ((update_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x= - (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 56 words$word))))`; - - -val _ = Define ` - ((get_SV39_PTE:riscv_sequential_types$SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))= v)`; - - -val _ = Define ` - ((set_SV39_PTE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ r . - let r = (Mk_SV39_PTE v) in - write_regS r_ref r)))`; - - -val _ = Define ` - ((get_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 44 words$word)))`; - - -val _ = Define ` - ((set_SV39_PTE_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_SV39_PTE r))))`; - - -val _ = Define ` - ((update_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2*) - -val _ = Define ` - ((get_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 2 words$word)))`; - - -(*val _set_SV39_PTE_RSW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_PTE_RSW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_SV39_PTE r))))`; - - -(*val _update_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.SV39_PTE*) - -val _ = Define ` - ((update_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val _get_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8*) - -val _ = Define ` - ((get_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)))`; - - -(*val _set_SV39_PTE_BITS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((set_SV39_PTE_BITS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v= (bindS -(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v : 64 words$word)) in - write_regS r_ref (Mk_SV39_PTE r))))`; - - -(*val _update_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.SV39_PTE*) - -val _ = Define ` - ((update_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x : 64 words$word))))`; - - -(*val curAsid64 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty16)*) - -val _ = Define ` - ((curAsid64:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((16)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let satp64 = (Mk_Satp64 w__0) in - returnS ((get_Satp64_Asid satp64 : 16 words$word)))))`; - - -(*val curPTB39 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty56)*) - -val _ = Define ` - ((curPTB39:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((56)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let satp64 = (Mk_Satp64 w__0) in - returnS ((EXTZ (( 56 : int):sail_values$ii) - ((shiftl ((get_Satp64_PPN satp64 : 44 words$word)) PAGESIZE_BITS : 44 words$word)) - : 56 words$word)))))`; - - -(*val walk39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M Riscv_sequential_types.PTW_Result*) - - val walk39_defn = Hol_defn "walk39" ` - ((walk39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$PTW_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vaddr ac priv mxr sum ptb level global= - (let va = (Mk_SV39_Vaddr vaddr) in - let (pt_ofs : riscv_sequential_types$paddr39) = -((shiftl - ((EXTZ (( 56 : int):sail_values$ii) - ((subrange_vec_dec - ((shiftr ((get_SV39_Vaddr_VPNi va : 27 words$word)) - ((level * SV39_LEVEL_BITS)) - : 27 words$word)) SV39_LEVEL_BITS (( 0 : int):sail_values$ii) - : 10 words$word)) - : 56 words$word)) PTE39_LOG_SIZE - : 56 words$word)) in - let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in bindS - (checked_mem_read Data ((EXTZ (( 64 : int):sail_values$ii) pte_addr : 64 words$word)) (( 8 : int):sail_values$ii) - : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__0 : ( 64 words$word) riscv_sequential_types$MemoryOpResult) . - (case w__0 of - MemException (_) => returnS (PTW_Failure PTW_Access) - | MemValue (v) => - let pte = (Mk_SV39_PTE v) in - let pbits = ((get_SV39_PTE_BITS pte : 8 words$word)) in - let pattr = (Mk_PTE_Bits pbits) in - let is_global = - (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in - if ((isInvalidPTE pbits)) then returnS (PTW_Failure PTW_Invalid_PTE) - else if ((isPTEPtr pbits)) then - if (((level = (( 0 : int):sail_values$ii)))) then returnS (PTW_Failure PTW_Invalid_PTE) - else - walk39 vaddr ac priv mxr sum - ((EXTZ (( 56 : int):sail_values$ii) ((get_SV39_PTE_PPNi pte : 44 words$word)) : 56 words$word)) - ((level - (( 1 : int):sail_values$ii))) is_global - else bindS -(checkPTEPermission ac priv mxr sum pattr) (\ (w__3 : bool) . - returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission - else if ((level > (( 0 : int):sail_values$ii))) then - let masked = -((and_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) - ((EXTZ (( 44 : int):sail_values$ii) - ((sub_vec_int - ((shiftl (vec_of_bits [B1] : 1 words$word) - ((level * SV39_LEVEL_BITS)) - : 1 words$word)) (( 1 : int):sail_values$ii) - : 1 words$word)) - : 44 words$word)) - : 44 words$word)) in - if (((masked <> ((EXTZ (( 44 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 44 words$word))))) - then - PTW_Failure PTW_Misaligned - else - let ppn = -((or_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) - ((and_vec - ((EXTZ (( 44 : int):sail_values$ii) ((get_SV39_Vaddr_VPNi va : 27 words$word)) : 44 words$word)) - ((EXTZ (( 44 : int):sail_values$ii) - ((sub_vec_int - ((shiftl (vec_of_bits [B1] : 1 words$word) - ((level * SV39_LEVEL_BITS)) - : 1 words$word)) (( 1 : int):sail_values$ii) - : 1 words$word)) - : 44 words$word)) - : 44 words$word)) - : 44 words$word)) in - PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va : 12 words$word)) - : 56 words$word),pte,pte_addr,level,is_global) - else - PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte : 44 words$word)) - ((get_SV39_Vaddr_PgOfs va : 12 words$word)) - : 56 words$word),pte,pte_addr,level,is_global))) - ))))`; - -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn; - -(*val make_TLB39_Entry : Machine_word.mword Machine_word.ty16 -> bool -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Sail_values.ii -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M Riscv_sequential_types.TLB39_Entry*) - -val _ = Define ` - ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE -> int ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TLB39_Entry),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr= - (let (shift : sail_values$ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in - let (vAddrMask : riscv_sequential_types$vaddr39) = -((sub_vec_int - ((shiftl ((EXTZ (( 39 : int):sail_values$ii) (vec_of_bits [B1] : 1 words$word) : 39 words$word)) shift : 39 words$word)) - (( 1 : int):sail_values$ii) - : 39 words$word)) in - let (vMatchMask : riscv_sequential_types$vaddr39) = ((not_vec vAddrMask : 39 words$word)) in bindS - (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) . - returnS (<| TLB39_Entry_asid := asid; - TLB39_Entry_global := global; - TLB39_Entry_pte := pte; - TLB39_Entry_pteAddr := pteAddr; - TLB39_Entry_vAddrMask := vAddrMask; - TLB39_Entry_vMatchMask := vMatchMask; - TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask : 39 words$word)); - TLB39_Entry_pAddr := - ((shiftl ((shiftr pAddr shift : 56 words$word)) shift : 56 words$word)); - TLB39_Entry_age := w__0 |>))))`; - - -val _ = Define ` - ((TLBEntries:int)= ((( 32 : int):sail_values$ii)))`; - - -(*val lookupTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M (Maybe.maybe ((Sail_values.ii * Riscv_sequential_types.TLB39_Entry)))*) - -val _ = Define ` - ((lookupTLB39:(16)words$word ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((int#riscv_sequential_types$TLB39_Entry)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vaddr= (bindS -(read_regS tlb39_ref) (\ (w__0 : riscv_sequential_types$TLB39_Entry option) . - returnS ((case w__0 of - NONE => NONE - | SOME (e) => - if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr : 39 words$word)))))))) then - SOME ((( 0 : int):sail_values$ii), e) - else NONE - )))))`; - - -(*val addToTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (bindS -(make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . - write_regS tlb39_ref (SOME ent))))`; - - -(*val writeTLB39 : Sail_values.ii -> Riscv_sequential_types.TLB39_Entry -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((writeTLB39:int -> riscv_sequential_types$TLB39_Entry ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (idx : sail_values$ii) (ent : riscv_sequential_types$TLB39_Entry)= (write_regS tlb39_ref (SOME ent)))`; - - -(*val flushTLB : Maybe.maybe (Machine_word.mword Machine_word.ty16) -> Maybe.maybe (Machine_word.mword Machine_word.ty39) -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((flushTLB:((16)words$word)option ->((39)words$word)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid addr= (bindS -(read_regS tlb39_ref) (\ (w__0 : riscv_sequential_types$TLB39_Entry option) . - let (ent : riscv_sequential_types$TLB39_Entry option) = -((case (w__0, asid, addr) of - (NONE, _, _) => NONE - | (SOME (e), NONE, NONE) => NONE - | (SOME (e), NONE, SOME (a)) => - if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a : 39 words$word))))) then - NONE - else SOME e - | (SOME (e), SOME (i), NONE) => - if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE - else SOME e - | (SOME (e), SOME (i), SOME (a)) => - if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask : 39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then - NONE - else SOME e - )) in - write_regS tlb39_ref ent)))`; - - -val _ = Define ` - ((enable_dirty_update:bool)= T)`; - - -(*val translate39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Sail_values.ii -> Riscv_sequential_types.M Riscv_sequential_types.TR39_Result*) - -val _ = Define ` - ((translate39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR39_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac priv mxr sum level= (bindS - (curAsid64 () : ( 16 words$word) riscv_sequential_types$M) (\ asid . bindS -(lookupTLB39 asid vAddr) (\ (w__0 : ((sail_values$ii # riscv_sequential_types$TLB39_Entry))option) . - (case w__0 of - SOME (idx,ent) => - let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte : 8 words$word))) in bindS -(checkPTEPermission ac priv mxr sum pteBits) (\ (w__1 : bool) . - if ((~ w__1)) then returnS (TR39_Failure PTW_No_Permission) - else - (case ((update_PTE_Bits pteBits ac)) of - NONE => - returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr - ((EXTZ (( 56 : int):sail_values$ii) - ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) - : 56 words$word)) - : 56 words$word))) - | SOME (pbits) => - if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update) - else - let (n_ent : riscv_sequential_types$TLB39_Entry) = ent in - let n_ent = -((n_ent with<| - TLB39_Entry_pte := - ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits : 8 words$word))))|>)) in bindS (seqS -(writeTLB39 idx n_ent) -(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) ent.TLB39_Entry_pteAddr : 64 words$word)) (( 8 : int):sail_values$ii) - ((get_SV39_PTE ent.TLB39_Entry_pte : 64 words$word)))) (\ (w__2 : unit - riscv_sequential_types$MemoryOpResult) . seqS - (case w__2 of - MemValue (_) => returnS () - | MemException (e) => internal_error "invalid physical address in TLB" - ) -(returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr - ((EXTZ (( 56 : int):sail_values$ii) - ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) - : 56 words$word)) - : 56 words$word))))) - )) - | NONE => bindS - (curPTB39 () : ( 56 words$word) riscv_sequential_types$M) (\ (w__6 : 56 words$word) . bindS -(walk39 vAddr ac priv mxr sum w__6 level F) (\ (w__7 : riscv_sequential_types$PTW_Result) . - (case w__7 of - PTW_Failure (f) => returnS (TR39_Failure f) - | PTW_Success (pAddr,pte,pteAddr,level,global) => - (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word))) ac)) of - NONE => seqS -(addToTLB39 asid vAddr pAddr pte pteAddr level global) (returnS (TR39_Address pAddr)) - | SOME (pbits) => - if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update) - else - let (w_pte : riscv_sequential_types$SV39_PTE) = -(update_SV39_PTE_BITS pte ((get_PTE_Bits pbits : 8 words$word))) in bindS -(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) pteAddr : 64 words$word)) (( 8 : int):sail_values$ii) - ((get_SV39_PTE w_pte : 64 words$word))) (\ (w__8 : unit riscv_sequential_types$MemoryOpResult) . - (case w__8 of - MemValue (_) => seqS -(addToTLB39 asid vAddr pAddr w_pte pteAddr level global) -(returnS (TR39_Address pAddr)) - | MemException (e) => returnS (TR39_Failure PTW_Access) - )) - ) - ))) - )))))`; - - -(*val translationMode : Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.SATPMode*) - -val _ = Define ` - ((translationMode:riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$SATPMode),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) priv= - (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) - then - returnS Sbare - else bindS -(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . - let arch = (architecture ((get_Mstatus_SXL w__0 : 2 words$word))) in - (case arch of - SOME (RV64) => bindS - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . - let (mbits : riscv_sequential_types$satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) : 4 words$word)) in - (case ((satpMode_of_bits RV64 mbits)) of - SOME (m) => returnS m - | NONE => internal_error "invalid RV64 translation mode in satp" - )) - | _ => internal_error "unsupported address translation arch" - ))))`; - - -(*val translateAddr : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.ReadType -> Riscv_sequential_types.M Riscv_sequential_types.TR_Result*) - -val _ = Define ` - ((translateAddr:(64)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$ReadType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac rt= (bindS - (case rt of - Instruction => read_regS cur_privilege_ref - | Data => bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . - if (((((get_Mstatus_MPRV w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then bindS -(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . - returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) - else read_regS cur_privilege_ref) - ) (\ (effPriv : riscv_sequential_types$Privilege) . bindS -(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) . - let (mxr : bool) = - (((get_Mstatus_MXR w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in bindS -(read_regS mstatus_ref) (\ (w__6 : riscv_sequential_types$Mstatus) . - let (sum : bool) = - (((get_Mstatus_SUM w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in bindS -(translationMode effPriv) (\ (mode : riscv_sequential_types$SATPMode) . - (case mode of - Sbare => returnS (TR_Address vAddr) - | SV39 => bindS - (translate39 - ((subrange_vec_dec vAddr (( 38 : int): sail_values$ii) - (( 0 : int): sail_values$ii) : 39 words$word)) - ac effPriv mxr sum - ((SV39_LEVELS - (( 1 : int): sail_values$ii)))) - (\ (w__7 : riscv_sequential_types$TR39_Result) . - returnS - ((case w__7 of - TR39_Address (pa) => TR_Address - ((EXTZ - (( 64 : int): sail_values$ii) - pa : 64 words$word)) - | TR39_Failure (f) => TR_Failure - ((translationException ac f)) - ))) - )))))))`; - - -(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Riscv_sequential_types.ast*) - -(*val decodeCompressed : Machine_word.mword Machine_word.ty16 -> Maybe.maybe Riscv_sequential_types.ast*) - -(*val execute : Riscv_sequential_types.ast -> Riscv_sequential_types.M unit*) - -(*val print_insn : Riscv_sequential_types.ast -> string*) - -(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((extend_value:bool ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult ->((64)words$word)riscv_sequential_types$MemoryOpResult) is_unsigned value= - ((case value of - MemValue (v) => - MemValue (if is_unsigned then (EXTZ (( 64 : int):sail_values$ii) v : 64 words$word) - else (EXTS (( 64 : int):sail_values$ii) v : 64 words$word)) - | MemException (e) => MemException e - )))`; - - -(*val process_load : forall 'int8_times_n . Size 'int8_times_n => Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> bool -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rd addr value is_unsigned= - ((case ((extend_value is_unsigned value : ( 64 words$word) riscv_sequential_types$MemoryOpResult)) of - MemValue (result) => wX ((regbits_to_regno rd)) result - | MemException (e) => handle_mem_exception addr e - )))`; - - -(*val process_loadres : forall 'int8_times_n . Riscv_sequential_types.regbits -> Riscv_sequential_types.xlenbits -> Riscv_sequential_types.MemoryOpResult (Riscv_sequential_types.bits 'int8_times_n) -> bool -> unit*) - -(*val readCSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*) - -val _ = Define ` - ((readCSR:(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr= - (let b__0 = csr in - if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then - (read_regS mvendorid_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then - (read_regS marchid_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then - (read_regS mimpid_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then - (read_regS mhartid_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS -(read_regS mstatus_ref) (\ (w__4 : riscv_sequential_types$Mstatus) . returnS ((get_Mstatus w__4 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS medeleg_ref) (\ (w__5 : riscv_sequential_types$Medeleg) . returnS ((get_Medeleg w__5 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS -(read_regS mideleg_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) . - returnS ((get_Minterrupts w__6 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mie_ref) (\ (w__7 : riscv_sequential_types$Minterrupts) . - returnS ((get_Minterrupts w__7 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS -(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) . returnS ((get_Mtvec w__8 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (read_regS mscratch_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS mcause_ref) (\ (w__11 : riscv_sequential_types$Mcause) . returnS ((get_Mcause w__11 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (read_regS mtval_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mip_ref) (\ (w__13 : riscv_sequential_types$Minterrupts) . - returnS ((get_Minterrupts w__13 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS -(read_regS mstatus_ref) (\ (w__14 : riscv_sequential_types$Mstatus) . - returnS ((get_Mstatus w__14 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS sedeleg_ref) (\ (w__15 : riscv_sequential_types$Sedeleg) . - returnS ((get_Sedeleg w__15 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS -(read_regS sideleg_ref) (\ (w__16 : riscv_sequential_types$Sinterrupts) . - returnS ((get_Sinterrupts w__16 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mie_ref) (\ (w__17 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mideleg_ref) (\ (w__18 : riscv_sequential_types$Minterrupts) . - returnS ((get_Sinterrupts ((lower_mie w__17 w__18)) : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS -(read_regS stvec_ref) (\ (w__19 : riscv_sequential_types$Mtvec) . returnS ((get_Mtvec w__19 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (read_regS sscratch_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS scause_ref) (\ (w__22 : riscv_sequential_types$Mcause) . returnS ((get_Mcause w__22 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (read_regS stval_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mip_ref) (\ (w__24 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mideleg_ref) (\ (w__25 : riscv_sequential_types$Minterrupts) . - returnS ((get_Sinterrupts ((lower_mip w__24 w__25)) : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (read_regS mcycle_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (read_regS mtime_ref : ( 64 words$word) riscv_sequential_types$M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - (read_regS minstret_ref : ( 64 words$word) riscv_sequential_types$M) - else - let (_ : unit) = (print_bits "unhandled read to CSR " csr) in - returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)))`; - - -(*val writeCSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((writeCSR:(12)words$word ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (value : riscv_sequential_types$xlenbits)= - (let b__0 = csr in bindS - (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS -(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . bindS (seqS -(write_regS mstatus_ref ((legalize_mstatus w__0 value))) -(read_regS mstatus_ref)) (\ (w__1 : riscv_sequential_types$Mstatus) . - returnS (SOME ((get_Mstatus w__1 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS medeleg_ref) (\ (w__2 : riscv_sequential_types$Medeleg) . bindS (seqS -(write_regS medeleg_ref ((legalize_medeleg w__2 value))) -(read_regS medeleg_ref)) (\ (w__3 : riscv_sequential_types$Medeleg) . - returnS (SOME ((get_Medeleg w__3 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS -(read_regS mideleg_ref) (\ (w__4 : riscv_sequential_types$Minterrupts) . bindS (seqS -(write_regS mideleg_ref ((legalize_mideleg w__4 value))) -(read_regS mideleg_ref)) (\ (w__5 : riscv_sequential_types$Minterrupts) . - returnS (SOME ((get_Minterrupts w__5 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mie_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) . bindS (seqS -(write_regS mie_ref ((legalize_mie w__6 value))) -(read_regS mie_ref)) (\ (w__7 : riscv_sequential_types$Minterrupts) . - returnS (SOME ((get_Minterrupts w__7 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS -(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) . bindS (seqS -(write_regS mtvec_ref ((legalize_tvec w__8 value))) -(read_regS mtvec_ref)) (\ (w__9 : riscv_sequential_types$Mtvec) . - returnS (SOME ((get_Mtvec w__9 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS (seqS -(write_regS mscratch_ref value) - (read_regS mscratch_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__10 : 64 words$word) . - returnS (SOME w__10)) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then bindS - (legalize_xepc value : ( 64 words$word) riscv_sequential_types$M) (\ (w__11 : riscv_sequential_types$xlenbits) . bindS (seqS -(write_regS mepc_ref w__11) - (read_regS mepc_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__12 : 64 words$word) . returnS (SOME w__12))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS (seqS -(set_Mcause mcause_ref value) -(read_regS mcause_ref)) (\ (w__13 : riscv_sequential_types$Mcause) . - returnS (SOME ((get_Mcause w__13 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS -(write_regS mtval_ref value) - (read_regS mtval_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__14 : 64 words$word) . returnS (SOME w__14)) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mip_ref) (\ (w__15 : riscv_sequential_types$Minterrupts) . bindS (seqS -(write_regS mip_ref ((legalize_mip w__15 value))) -(read_regS mip_ref)) (\ (w__16 : riscv_sequential_types$Minterrupts) . - returnS (SOME ((get_Minterrupts w__16 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS -(read_regS mstatus_ref) (\ (w__17 : riscv_sequential_types$Mstatus) . bindS (seqS -(write_regS mstatus_ref ((legalize_sstatus w__17 value))) -(read_regS mstatus_ref)) (\ (w__18 : riscv_sequential_types$Mstatus) . - returnS (SOME ((get_Mstatus w__18 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS -(read_regS sedeleg_ref) (\ (w__19 : riscv_sequential_types$Sedeleg) . bindS (seqS -(write_regS sedeleg_ref ((legalize_sedeleg w__19 value))) -(read_regS sedeleg_ref)) (\ (w__20 : riscv_sequential_types$Sedeleg) . - returnS (SOME ((get_Sedeleg w__20 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS -(set_Sinterrupts sideleg_ref value) -(read_regS sideleg_ref)) (\ (w__21 : riscv_sequential_types$Sinterrupts) . - returnS (SOME ((get_Sinterrupts w__21 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mie_ref) (\ (w__22 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mideleg_ref) (\ (w__23 : riscv_sequential_types$Minterrupts) . bindS (seqS -(write_regS mie_ref ((legalize_sie w__22 w__23 value))) -(read_regS mie_ref)) (\ (w__24 : riscv_sequential_types$Minterrupts) . - returnS (SOME ((get_Minterrupts w__24 : 64 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then bindS -(read_regS stvec_ref) (\ (w__25 : riscv_sequential_types$Mtvec) . bindS (seqS -(write_regS stvec_ref ((legalize_tvec w__25 value))) -(read_regS stvec_ref)) (\ (w__26 : riscv_sequential_types$Mtvec) . - returnS (SOME ((get_Mtvec w__26 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS (seqS -(write_regS sscratch_ref value) - (read_regS sscratch_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__27 : 64 words$word) . - returnS (SOME w__27)) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then bindS - (legalize_xepc value : ( 64 words$word) riscv_sequential_types$M) (\ (w__28 : riscv_sequential_types$xlenbits) . bindS (seqS -(write_regS sepc_ref w__28) - (read_regS sepc_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__29 : 64 words$word) . returnS (SOME w__29))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then bindS (seqS -(set_Mcause scause_ref value) -(read_regS scause_ref)) (\ (w__30 : riscv_sequential_types$Mcause) . - returnS (SOME ((get_Mcause w__30 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then bindS (seqS -(write_regS stval_ref value) - (read_regS stval_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__31 : 64 words$word) . returnS (SOME w__31)) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then bindS -(read_regS mip_ref) (\ (w__32 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mideleg_ref) (\ (w__33 : riscv_sequential_types$Minterrupts) . bindS (seqS -(write_regS mip_ref ((legalize_sip w__32 w__33 value))) -(read_regS mip_ref)) (\ (w__34 : riscv_sequential_types$Minterrupts) . - returnS (SOME ((get_Minterrupts w__34 : 64 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then bindS -(cur_Architecture () ) (\ (w__35 : riscv_sequential_types$Architecture) . bindS - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__36 : 64 words$word) . bindS (seqS -(write_regS satp_ref ((legalize_satp w__35 w__36 value : 64 words$word))) - (read_regS satp_ref : ( 64 words$word) riscv_sequential_types$M)) (\ (w__37 : 64 words$word) . returnS (SOME w__37)))) - else returnS NONE) (\ (res : riscv_sequential_types$xlenbits option) . - returnS ((case res of - SOME (v) => - prerr_endline - ((STRCAT "CSR " - ((STRCAT ((csr_name csr)) - ((STRCAT " <- " - ((STRCAT ((string_of_vec v)) - ((STRCAT " (input: " - ((STRCAT ((string_of_vec value)) ")")))))))))))) - | NONE => print_bits "unhandled write to CSR " csr - )))))`; - - -(*val signalIllegalInstruction : unit -> Riscv_sequential_types.M unit*) - -val _ = Define ` - ((signalIllegalInstruction:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (not_implemented "illegal instruction"))`; - - -val _ = Define ` - ((decode:(32)words$word ->(riscv_sequential_types$ast)option) v__0= - (if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (UTYPE (imm,rd,RISCV_LUI)) - else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (UTYPE (imm,rd,RISCV_AUIPC)) - else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 20 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) - ((concat_vec - ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm (( 18 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 6 words$word)) - ((concat_vec - ((subrange_vec_dec imm (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 20 words$word)) - : 21 words$word),rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RISCV_JALR (imm,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BEQ)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BNE)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BLT)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BGE)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BLTU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BGEU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ADDI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_SLTI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_XORI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ORI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ANDI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 6 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_ADD)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SUB)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLL)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLT)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_XOR)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SRL)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SRA)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_OR)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_AND)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,DOUBLE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (ADDIW (imm,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,F,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,T,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (DIV0 (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (DIV0 (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (REM (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (REM (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (MULW (rs2,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (DIVW (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (DIVW (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (REMW (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (REMW (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : 20 words$word))))))) then - let (pred : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 27 : int):sail_values$ii) (( 24 : int):sail_values$ii) : 4 words$word)) in - let (succ : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 23 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 4 words$word)) in - SOME (FENCE (pred,succ)) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; - B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : 32 words$word)))) then - SOME (FENCEI () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (ECALL () ) - else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (MRET () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (SRET () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (EBREAK () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (WFI () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word))))))) - then - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - SOME (SFENCE_VMA (rs1,rs2)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 5 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRW)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRS)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRC)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRW)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRS)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii) : 12 words$word)) in - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii) : 5 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRC)) - else NONE))`; - - -val _ = Define ` - ((decodeCompressed:(16)words$word ->(riscv_sequential_types$ast)option) v__418= - (if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzi1 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (nzi0 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - if ((((((nzi1 = (vec_of_bits [B0] : 1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) then - SOME (NOP () ) - else NONE - else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then - SOME (ILLEGAL () ) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (nz54 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 2 words$word)) in - let (nz96 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 4 words$word)) in - let (nz2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in - let (nz3 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let nzimm = -((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word)) - : 8 words$word)) in - if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then NONE - else SOME (C_ADDI4SPN (rd,nzimm)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in - let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in - let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in - SOME (C_LW (uimm,rs1,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in - let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in - let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in - SOME (C_LD (uimm,rs1,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in - let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in - let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in - SOME (C_SW (uimm,rs1,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in - let (rs1 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in - let (rs2 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in - SOME (C_SD (uimm,rs1,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (nzi40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let nzi = ((concat_vec nzi5 nzi40 : 6 words$word)) in - if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then - NONE - else SOME (C_ADDI (nzi,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - SOME (C_ADDIW ((concat_vec imm5 imm40 : 6 words$word),rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE - else SOME (C_LI ((concat_vec imm5 imm40 : 6 words$word),rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzi9 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (nzi4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in - let (nzi6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 1 words$word)) in - let (nzi87 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in - let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in - let nzimm = -((concat_vec nzi9 - ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word)) - : 5 words$word)) - : 6 words$word)) in - if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE - else SOME (C_ADDI16SP nzimm) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm17 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (imm1612 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then - NONE - else SOME (C_LUI ((concat_vec imm17 imm1612 : 6 words$word),rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in - if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE - else SOME (C_SRLI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in - if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE - else SOME (C_SRAI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (i40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - SOME (C_ANDI ((concat_vec i5 i40 : 6 words$word),rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_SUB (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_XOR (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_OR (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_AND (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_SUBW (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - SOME (C_ADDW (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i11 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (i4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) : 1 words$word)) in - let (i98 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 2 words$word)) in - let (i10 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) : 1 words$word)) in - let (i6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 1 words$word)) in - let (i7 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) : 1 words$word)) in - let (i31 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 3 words$word)) in - let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in - SOME (C_J ((concat_vec i11 - ((concat_vec i10 - ((concat_vec i98 - ((concat_vec i7 - ((concat_vec i6 - ((concat_vec i5 ((concat_vec i4 i31 : 4 words$word)) : 5 words$word)) - : 6 words$word)) - : 7 words$word)) - : 9 words$word)) - : 10 words$word)) - : 11 words$word))) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) in - let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in - let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in - let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in - SOME (C_BEQZ ((concat_vec i8 - ((concat_vec i76 - ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) - : 7 words$word)) - : 8 words$word),rs)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 2 words$word)) in - let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in - let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) : 2 words$word)) in - let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 1 words$word)) in - SOME (C_BNEZ ((concat_vec i8 - ((concat_vec i76 - ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) - : 7 words$word)) - : 8 words$word),rs)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in - if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then - NONE - else SOME (C_SLLI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (ui42 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 4 : int):sail_values$ii) : 3 words$word)) in - let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 3 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 2 words$word)) in - let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word)) in - if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE - else SOME (C_LWSP (uimm,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 1 words$word)) in - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (ui43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii) : 2 words$word)) in - let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 3 words$word)) in - let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word)) in - if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE - else SOME (C_LDSP (uimm,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui52 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii) : 4 words$word)) in - let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 2 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ui52 : 6 words$word)) in - SOME (C_SWSP (uimm,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii) : 3 words$word)) in - let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 3 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ui53 : 6 words$word)) in - SOME (C_SDSP (uimm,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE - else SOME (C_JR rs1) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then - let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE - else SOME (C_JALR rs1) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then - NONE - else SOME (C_MV (rd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii) : 5 words$word)) in - let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) : 5 words$word)) in - if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then - NONE - else SOME (C_ADD (rsd,rs2)) - else NONE))`; - - -(*val execute_WFI : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_WFI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__110= (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . - (case w__0 of - Machine => returnS () - | Supervisor => bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . - if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - handle_illegal () - else returnS () ) - | User => handle_illegal () - ))))`; - - -(*val execute_UTYPE : Machine_word.mword Machine_word.ty20 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.uop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_UTYPE:(20)words$word ->(5)words$word -> riscv_sequential_types$uop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd op= - (let (off : riscv_sequential_types$xlenbits) = -((EXTS (( 64 : int):sail_values$ii) - ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - : 32 words$word)) - : 64 words$word)) in bindS - (case op of - RISCV_LUI => returnS off - | RISCV_AUIPC => bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - returnS ((add_vec w__0 off : 64 words$word))) - ) (\ (ret : riscv_sequential_types$xlenbits) . - wX ((regbits_to_regno rd)) ret)))`; - - -(*val execute_STORECON : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (bindS -(speculate_conditional_success () ) (\ (w__0 : bool) . - let (status : 1 riscv_sequential_types$bits) = -(if w__0 then (vec_of_bits [B0] : 1 words$word) - else (vec_of_bits [B1] : 1 words$word)) in seqS -(wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):sail_values$ii) status : 64 words$word))) -(if (((status = (vec_of_bits [B1] : 1 words$word)))) then returnS () - else bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS -(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => bindS - (case width of - WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl T - | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl T - | _ => internal_error "STORECON expected word or double" - ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . - (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . bindS - (case width of - WORD => - mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - aq rl T - | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl T - | _ => internal_error "STORECON expected word or double" - ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . - (case res of - MemValue (_) => returnS () - | MemException (e) => handle_mem_exception addr e - ))) - )) - )))))))`; - - -(*val execute_STORE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in bindS -(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => bindS - (case width of - BYTE => mem_write_ea addr (( 1 : int):sail_values$ii) aq rl F - | HALF => mem_write_ea addr (( 2 : int):sail_values$ii) aq rl F - | WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl F - | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl F - ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . - (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . bindS - (case width of - BYTE => - mem_write_value addr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 8 words$word)) aq - rl F - | HALF => - mem_write_value addr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word)) aq - rl F - | WORD => - mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) aq - rl F - | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl F - ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . - (case res of - MemValue (_) => returnS () - | MemException (e) => handle_mem_exception addr e - ))) - )) - )))))`; - - -(*val execute_SRET : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_SRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__108= (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . - (case w__0 of - User => handle_illegal () - | Supervisor => bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . - if (((((get_Mstatus_TSR w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - handle_illegal () - else bindS -(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . bindS - (handle_exception w__2 (CTL_SRET () ) w__3 : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__4)))) - | Machine => bindS -(read_regS cur_privilege_ref) (\ (w__5 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . bindS - (handle_exception w__5 (CTL_SRET () ) w__6 : ( 64 words$word) riscv_sequential_types$M) (\ (w__7 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__7))) - ))))`; - - -(*val execute_SHIFTW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in - let (result : 32 riscv_sequential_types$bits) = -((case op of - RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word) - | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word) - | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word) - )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result : 64 words$word)))))`; - - -(*val execute_SHIFTIOP : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . - let (result : riscv_sequential_types$xlenbits) = -((case op of - RISCV_SLLI => (shift_bits_left rs1_val shamt : 64 words$word) - | RISCV_SRLI => (shift_bits_right rs1_val shamt : 64 words$word) - | RISCV_SRAI => (shift_right_arith64 rs1_val shamt : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result)))`; - - -(*val execute_SFENCE_VMA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs1 rs2= (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . - if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) - then - handle_illegal () - else bindS -(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . bindS -(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . - let p__104 = - (architecture ((get_Mstatus_SXL w__1 : 2 words$word)), (get_Mstatus_TVM w__2 : 1 words$word)) in - (case p__104 of - (SOME (RV64), v_0) => - if (((v_0 = ((bool_to_bits T : 1 words$word))))) then handle_illegal () - else bindS - (if (((((regbits_to_regno rs1)) = (( 0 : int):sail_values$ii)))) then returnS NONE - else bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . - returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 39 words$word))))) (\ (addr : - riscv_sequential_types$vaddr39 option) . bindS - (if (((((regbits_to_regno rs2)) = (( 0 : int):sail_values$ii)))) then returnS NONE - else bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : 64 words$word) . - returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 16 words$word))))) (\ (asid : - riscv_sequential_types$asid64 option) . - flushTLB asid addr)) - | (g__102, g__103) => internal_error "unimplemented sfence architecture" - ))))))`; - - -(*val execute_RTYPEW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.ropw -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$ropw ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . - let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in - let (result : 32 riscv_sequential_types$bits) = -((case op of - RISCV_ADDW => (add_vec rs1_val rs2_val : 32 words$word) - | RISCV_SUBW => (sub_vec rs1_val rs2_val : 32 words$word) - | RISCV_SLLW => - (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) - : 32 words$word) - | RISCV_SRLW => - (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) - : 32 words$word) - | RISCV_SRAW => - (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 5 words$word)) - : 32 words$word) - )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result : 64 words$word))))))`; - - -(*val execute_RTYPE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.rop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$rop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . - let (result : riscv_sequential_types$xlenbits) = -((case op of - RISCV_ADD => (add_vec rs1_val rs2_val : 64 words$word) - | RISCV_SUB => (sub_vec rs1_val rs2_val : 64 words$word) - | RISCV_SLL => - (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - : 64 words$word) - | RISCV_SLT => - (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val)))) : 1 words$word)) : 64 words$word) - | RISCV_SLTU => - (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui rs2_val)))) : 1 words$word)) : 64 words$word) - | RISCV_XOR => (xor_vec rs1_val rs2_val : 64 words$word) - | RISCV_SRL => - (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - : 64 words$word) - | RISCV_SRA => - (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 6 words$word)) - : 64 words$word) - | RISCV_OR => (or_vec rs1_val rs2_val : 64 words$word) - | RISCV_AND => (and_vec rs1_val rs2_val : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result))))`; - - -(*val execute_RISCV_JALR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd= (bindS - (read_regS nextPC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . bindS (seqS -(wX ((regbits_to_regno rd)) w__0) - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M)) (\ (w__1 : 64 words$word) . - let (newPC : riscv_sequential_types$xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in - write_regS - nextPC_ref - ((concat_vec ((subrange_vec_dec newPC (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii) : 63 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 64 words$word))))))`; - - -(*val execute_RISCV_JAL : Machine_word.mword Machine_word.ty21 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd= (bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (pc : riscv_sequential_types$xlenbits) . bindS - (read_regS nextPC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . seqS -(wX ((regbits_to_regno rd)) w__0) -(let (offset : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) in - write_regS nextPC_ref ((add_vec pc offset : 64 words$word)))))))`; - - -(*val execute_REMW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . - let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in - let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in - let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) r : 32 words$word)) : 64 words$word))))))`; - - -(*val execute_REM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . - let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in - let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((to_bits xlen r : 64 words$word))))))`; - - -(*val execute_NOP : unit -> unit*) - - val _ = Define ` - ((execute_NOP:unit -> unit) g__111= () )`; - - -(*val execute_MULW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . - let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in - let (rs1_int : sail_values$ii) = (integer_word$w2i rs1_val) in - let (rs2_int : sail_values$ii) = (integer_word$w2i rs2_val) in - let result32 = -((subrange_vec_dec ((to_bits (( 64 : int):sail_values$ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):sail_values$ii) - (( 0 : int):sail_values$ii) - : 32 words$word)) in - let (result : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) result32 : 64 words$word)) in - wX ((regbits_to_regno rd)) result))))`; - - -(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> bool -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . - let (rs1_int : sail_values$ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in - let (rs2_int : sail_values$ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let result128 = ((to_bits (( 128 : int):sail_values$ii) ((rs1_int * rs2_int)) : 128 words$word)) in - let result = -(if high then (subrange_vec_dec result128 (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii) : 64 words$word) - else (subrange_vec_dec result128 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 64 words$word)) in - wX ((regbits_to_regno rd)) result))))`; - - -(*val execute_MRET : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_MRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__107= (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . - if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) - then bindS -(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : 64 words$word) . bindS - (handle_exception w__1 (CTL_MRET () ) w__2 : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__3))) - else handle_illegal () )))`; - - -(*val execute_LOADRES : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_LOADRES:bool -> bool ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs1 width rd= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS -(translateAddr vaddr Read Data) (\ (w__0 : riscv_sequential_types$TR_Result) . - (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - WORD => bindS - (mem_read addr (( 4 : int):sail_values$ii) aq rl T : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__1 : ( 32 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd addr w__1 F) - | DOUBLE => bindS - (mem_read addr (( 8 : int):sail_values$ii) aq rl T : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 64 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd addr w__2 F) - | _ => internal_error "LOADRES expected WORD or DOUBLE" - ) - )))))`; - - -(*val execute_LOAD : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word)) in bindS -(translateAddr vaddr Read Data) (\ (w__1 : riscv_sequential_types$TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - BYTE => bindS - (mem_read addr (( 1 : int):sail_values$ii) aq rl F : ( ( 8 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 8 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd vaddr w__2 is_unsigned) - | HALF => bindS - (mem_read addr (( 2 : int):sail_values$ii) aq rl F : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__3 : ( 16 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd vaddr w__3 is_unsigned) - | WORD => bindS - (mem_read addr (( 4 : int):sail_values$ii) aq rl F : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd vaddr w__4 is_unsigned) - | DOUBLE => bindS - (mem_read addr (( 8 : int):sail_values$ii) aq rl F : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word) - riscv_sequential_types$MemoryOpResult) . - process_load rd vaddr w__5 is_unsigned) - ) - )))))`; - - -(*val execute_ITYPE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.iop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$iop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . - let (immext : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) in - let (result : riscv_sequential_types$xlenbits) = -((case op of - RISCV_ADDI => (add_vec rs1_val immext : 64 words$word) - | RISCV_SLTI => - (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i immext)))) : 1 words$word)) : 64 words$word) - | RISCV_SLTIU => - (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui immext)))) : 1 words$word)) : 64 words$word) - | RISCV_XORI => (xor_vec rs1_val immext : 64 words$word) - | RISCV_ORI => (or_vec rs1_val immext : 64 words$word) - | RISCV_ANDI => (and_vec rs1_val immext : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result)))`; - - -(*val execute_ILLEGAL : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_ILLEGAL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__112= (handle_illegal () ))`; - - -(*val execute_FENCEI : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_FENCEI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__105= (MEM_fence_i () ))`; - - -(*val execute_FENCE : Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_FENCE:(4)words$word ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) pred succ= - ((case (pred, succ) of - (b__0, b__1) => - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then - MEM_fence_rw_rw () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then - MEM_fence_r_rw () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then - MEM_fence_r_r () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then - MEM_fence_rw_w () else MEM_fence_w_w () - )))`; - - -(*val execute_ECALL : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_ECALL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__106= (bindS -(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . - let (t : riscv_sequential_types$sync_exception) = -(<| sync_exception_trap := - ((case w__0 of - User => E_U_EnvCall - | Supervisor => E_S_EnvCall - | Machine => E_M_EnvCall - )); - sync_exception_excinfo := NONE |>) in bindS -(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : 64 words$word) . bindS - (handle_exception w__1 (CTL_TRAP t) w__2 : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . - write_regS nextPC_ref w__3))))))`; - - -(*val execute_EBREAK : unit -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_EBREAK:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__109= (throwS (Error_EBREAK () )))`; - - -(*val execute_DIVW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : 64 words$word) . - let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) in - let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in - let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in - let (q' : sail_values$ii) = -(if (((s /\ ((q > ((((pow2 (( 31 : int):sail_values$ii))) - (( 1 : int):sail_values$ii)))))))) then - (( 0 : int):sail_values$ii) - ((ex_int ((pow0 (( 2 : int):sail_values$ii) (( 31 : int):sail_values$ii))))) - else q) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) q' : 32 words$word)) : 64 words$word))))))`; - - -(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . - let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in - let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in - let (q' : sail_values$ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in - wX ((regbits_to_regno rd)) ((to_bits xlen q' : 64 words$word))))))`; - - -(*val execute_C_ADDIW : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rsd= - (let (imm : 32 riscv_sequential_types$bits) = ((EXTS (( 32 : int):sail_values$ii) imm : 32 words$word)) in bindS - (rX ((regbits_to_regno rsd)) : ( 64 words$word) riscv_sequential_types$M) (\ rs_val . - let (res : 32 riscv_sequential_types$bits) = -((add_vec ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) imm : 32 words$word)) in - wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):sail_values$ii) res : 64 words$word)))))`; - - -(*val execute_CSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.csrop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$csrop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op= (bindS - (if is_imm then returnS ((EXTZ (( 64 : int):sail_values$ii) rs1 : 64 words$word)) - else (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M)) (\ (rs1_val : riscv_sequential_types$xlenbits) . - let (isWrite : bool) = -((case op of - CSRRW => T - | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):sail_values$ii)) else (((lem$w2ui rs1)) <> (( 0 : int):sail_values$ii)) - )) in bindS -(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) . bindS -(check_CSR csr w__1 isWrite) (\ (w__2 : bool) . - if ((~ w__2)) then handle_illegal () - else bindS - (readCSR csr : ( 64 words$word) riscv_sequential_types$M) (\ csr_val . seqS - (if isWrite then - let (new_val : riscv_sequential_types$xlenbits) = -((case op of - CSRRW => rs1_val - | CSRRS => (or_vec csr_val rs1_val : 64 words$word) - | CSRRC => (and_vec csr_val ((not_vec rs1_val : 64 words$word)) : 64 words$word) - )) in - writeCSR csr new_val - else returnS () ) -(wX ((regbits_to_regno rd)) csr_val)))))))`; - - -(*val execute_BTYPE : Machine_word.mword Machine_word.ty13 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.bop -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$bop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 op= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . - let (taken : bool) = -((case op of - RISCV_BEQ => (rs1_val = rs2_val) - | RISCV_BNE => (rs1_val <> rs2_val) - | RISCV_BLT => ((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val)) - | RISCV_BGE => ((integer_word$w2i rs1_val) >= (integer_word$w2i rs2_val)) - | RISCV_BLTU => ((lem$w2ui rs1_val) < (lem$w2ui rs2_val)) - | RISCV_BGEU => ((lem$w2ui rs1_val) >= (lem$w2ui rs2_val)) - )) in - if taken then bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) : 64 words$word))) - else returnS () ))))`; - - -(*val execute_AMO : Riscv_sequential_types.amoop -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_AMO:riscv_sequential_types$amoop -> bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) . bindS -(translateAddr vaddr ReadWrite Data) (\ (w__0 : riscv_sequential_types$TR_Result) . - (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => bindS - (case width of - WORD => mem_write_ea addr (( 4 : int):sail_values$ii) (((aq /\ rl))) rl T - | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) (((aq /\ rl))) rl T - | _ => internal_error "AMO expected WORD or DOUBLE" - ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . - (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => bindS - (case width of - WORD => bindS - (mem_read addr (( 4 : int):sail_values$ii) aq (((aq /\ rl))) T : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word) - riscv_sequential_types$MemoryOpResult) . - returnS ((extend_value F w__4 : ( 64 words$word) riscv_sequential_types$MemoryOpResult))) - | DOUBLE => bindS - (mem_read addr (( 8 : int):sail_values$ii) aq (((aq /\ rl))) T : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word) - riscv_sequential_types$MemoryOpResult) . - returnS ((extend_value F w__5 : ( 64 words$word) riscv_sequential_types$MemoryOpResult))) - | _ => (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) - ) (\ (rval : riscv_sequential_types$xlenbits riscv_sequential_types$MemoryOpResult) . - (case rval of - MemException (e) => handle_mem_exception addr e - | MemValue (loaded) => bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) riscv_sequential_types$M) (\ (rs2_val : riscv_sequential_types$xlenbits) . - let (result : riscv_sequential_types$xlenbits) = -((case op of - AMOSWAP => rs2_val - | AMOADD => (add_vec rs2_val loaded : 64 words$word) - | AMOXOR => (xor_vec rs2_val loaded : 64 words$word) - | AMOAND => (and_vec rs2_val loaded : 64 words$word) - | AMOOR => (or_vec rs2_val loaded : 64 words$word) - | AMOMIN => (vector64 ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) - | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) - | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) - | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) - )) in bindS - (case width of - WORD => - mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) - (((aq /\ rl))) rl T - | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) result (((aq /\ rl))) rl T - | _ => internal_error "AMO expected WORD or DOUBLE" - ) (\ (wval : unit riscv_sequential_types$MemoryOpResult) . - (case wval of - MemValue (_) => wX ((regbits_to_regno rd)) loaded - | MemException (e) => handle_mem_exception addr e - ))) - )) - )) - )))))`; - - -(*val execute_ADDIW : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*) - - val _ = Define ` - ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd= (bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : 64 words$word) . - let (result : riscv_sequential_types$xlenbits) = ((add_vec ((EXTS (( 64 : int):sail_values$ii) imm : 64 words$word)) w__0 : 64 words$word)) in - wX ((regbits_to_regno rd)) - ((EXTS (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 32 words$word)) : 64 words$word)))))`; - - - val execute_defn = Hol_defn "execute" ` - ((execute:riscv_sequential_types$ast ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) merge_var= - ((case merge_var of - C_ADDI4SPN (rdc,nzimm) => - let (imm : 12 riscv_sequential_types$bits) = -((concat_vec (vec_of_bits [B0;B0] : 2 words$word) - ((concat_vec nzimm (vec_of_bits [B0;B0] : 2 words$word) : 10 words$word)) - : 12 words$word)) in - let rd = ((creg2reg_bits rdc : 5 words$word)) in - execute (ITYPE (imm,sp,rd,RISCV_ADDI)) - | C_LW (uimm,rsc,rdc) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) - : 12 words$word)) in - let rd = ((creg2reg_bits rdc : 5 words$word)) in - let rs = ((creg2reg_bits rsc : 5 words$word)) in - execute (LOAD (imm,rs,rd,F,WORD,F,F)) - | C_LD (uimm,rsc,rdc) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) - : 12 words$word)) in - let rd = ((creg2reg_bits rdc : 5 words$word)) in - let rs = ((creg2reg_bits rsc : 5 words$word)) in - execute (LOAD (imm,rs,rd,F,DOUBLE,F,F)) - | C_SW (uimm,rsc1,rsc2) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 7 words$word)) - : 12 words$word)) in - let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in - let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in - execute (STORE (imm,rs2,rs1,WORD,F,F)) - | C_SD (uimm,rsc1,rsc2) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 8 words$word)) - : 12 words$word)) in - let rs1 = ((creg2reg_bits rsc1 : 5 words$word)) in - let rs2 = ((creg2reg_bits rsc2 : 5 words$word)) in - execute (STORE (imm,rs2,rs1,DOUBLE,F,F)) - | C_ADDI (nzi,rsd) => - let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) nzi : 12 words$word)) in - execute (ITYPE (imm,rsd,rsd,RISCV_ADDI)) - | C_JAL (imm) => - execute - (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) - : 21 words$word),ra)) - | C_LI (imm,rd) => - let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) imm : 12 words$word)) in - execute (ITYPE (imm,zreg,rd,RISCV_ADDI)) - | C_ADDI16SP (imm) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTS (( 12 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 10 words$word)) - : 12 words$word)) in - execute (ITYPE (imm,sp,sp,RISCV_ADDI)) - | C_LUI (imm,rd) => - let (res : 20 riscv_sequential_types$bits) = ((EXTS (( 20 : int):sail_values$ii) imm : 20 words$word)) in - execute (UTYPE (res,rd,RISCV_LUI)) - | C_SRLI (shamt,rsd) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI)) - | C_SRAI (shamt,rsd) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI)) - | C_ANDI (imm,rsd) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - execute (ITYPE ((EXTS (( 12 : int):sail_values$ii) imm : 12 words$word),rsd,rsd,RISCV_ANDI)) - | C_SUB (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPE (rs2,rsd,rsd,RISCV_SUB)) - | C_XOR (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPE (rs2,rsd,rsd,RISCV_XOR)) - | C_OR (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPE (rs2,rsd,rsd,RISCV_OR)) - | C_AND (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPE (rs2,rsd,rsd,RISCV_AND)) - | C_SUBW (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW)) - | C_ADDW (rsd,rs2) => - let rsd = ((creg2reg_bits rsd : 5 words$word)) in - let rs2 = ((creg2reg_bits rs2 : 5 words$word)) in - execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW)) - | C_J (imm) => - execute - (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 12 words$word)) - : 21 words$word),zreg)) - | C_BEQZ (imm,rs) => - execute - (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) - : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BEQ)) - | C_BNEZ (imm,rs) => - execute - (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0] : 1 words$word) : 9 words$word)) - : 13 words$word),zreg,(creg2reg_bits rs : 5 words$word),RISCV_BNE)) - | C_SLLI (shamt,rsd) => execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI)) - | C_LWSP (uimm,rd) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) - : 12 words$word)) in - execute (LOAD (imm,sp,rd,F,WORD,F,F)) - | C_LDSP (uimm,rd) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) - : 12 words$word)) in - execute (LOAD (imm,sp,rd,F,DOUBLE,F,F)) - | C_SWSP (uimm,rs2) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0] : 2 words$word) : 8 words$word)) - : 12 words$word)) in - execute (STORE (imm,rs2,sp,WORD,F,F)) - | C_SDSP (uimm,rs2) => - let (imm : 12 riscv_sequential_types$bits) = -((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0] : 3 words$word) : 9 words$word)) - : 12 words$word)) in - execute (STORE (imm,rs2,sp,DOUBLE,F,F)) - | C_JR (rs1) => - execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,zreg)) - | C_JALR (rs1) => - execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0] : 1 words$word) : 12 words$word),rs1,ra)) - | C_MV (rd,rs2) => execute (RTYPE (rs2,zreg,rd,RISCV_ADD)) - | C_ADD (rsd,rs2) => execute (RTYPE (rs2,rsd,rsd,RISCV_ADD)) - | UTYPE (imm,rd,op) => execute_UTYPE imm rd op - | RISCV_JAL (imm,rd) => execute_RISCV_JAL imm rd - | RISCV_JALR (imm,rs1,rd) => execute_RISCV_JALR imm rs1 rd - | BTYPE (imm,rs2,rs1,op) => execute_BTYPE imm rs2 rs1 op - | ITYPE (imm,rs1,rd,op) => execute_ITYPE imm rs1 rd op - | SHIFTIOP (shamt,rs1,rd,op) => execute_SHIFTIOP shamt rs1 rd op - | RTYPE (rs2,rs1,rd,op) => execute_RTYPE rs2 rs1 rd op - | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => execute_LOAD imm rs1 rd is_unsigned width aq rl - | STORE (imm,rs2,rs1,width,aq,rl) => execute_STORE imm rs2 rs1 width aq rl - | ADDIW (imm,rs1,rd) => execute_ADDIW imm rs1 rd - | SHIFTW (shamt,rs1,rd,op) => execute_SHIFTW shamt rs1 rd op - | RTYPEW (rs2,rs1,rd,op) => execute_RTYPEW rs2 rs1 rd op - | MUL (rs2,rs1,rd,high,signed1,signed2) => execute_MUL rs2 rs1 rd high signed1 signed2 - | DIV0 (rs2,rs1,rd,s) => execute_DIV rs2 rs1 rd s - | REM (rs2,rs1,rd,s) => execute_REM rs2 rs1 rd s - | MULW (rs2,rs1,rd) => execute_MULW rs2 rs1 rd - | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s - | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s - | FENCE (pred,succ) => execute_FENCE pred succ - | FENCEI (g__105) => execute_FENCEI g__105 - | ECALL (g__106) => execute_ECALL g__106 - | MRET (g__107) => execute_MRET g__107 - | SRET (g__108) => execute_SRET g__108 - | EBREAK (g__109) => execute_EBREAK g__109 - | WFI (g__110) => execute_WFI g__110 - | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2 - | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd - | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd - | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd - | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op - | NOP (g__111) => returnS ((execute_NOP g__111)) - | ILLEGAL (g__112) => execute_ILLEGAL g__112 - | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd - )))`; - -val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn; - -val _ = Define ` - ((print_insn:riscv_sequential_types$ast -> string) merge_var= - ((case merge_var of - UTYPE (imm,rd,op) => - (case op of - RISCV_LUI => - STRCAT "lui " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | RISCV_AUIPC => - STRCAT "auipc " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - ) - | RISCV_JAL (imm,rd) => - STRCAT "jal " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | RISCV_JALR (imm,rs1,rd) => - STRCAT "jalr " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | BTYPE (imm,rs2,rs1,op) => - let (insn : string) = -((case op of - RISCV_BEQ => "beq " - | RISCV_BNE => "bne " - | RISCV_BLT => "blt " - | RISCV_BGE => "bge " - | RISCV_BLTU => "bltu " - | RISCV_BGEU => "bgeu " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rs1)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | ITYPE (imm,rs1,rd,op) => - let (insn : string) = -((case op of - RISCV_ADDI => "addi " - | RISCV_SLTI => "slti " - | RISCV_SLTIU => "sltiu " - | RISCV_XORI => "xori " - | RISCV_ORI => "ori " - | RISCV_ANDI => "andi " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | SHIFTIOP (shamt,rs1,rd,op) => - let (insn : string) = -((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) - | RTYPE (rs2,rs1,rd,op) => - let (insn : string) = -((case op of - RISCV_ADD => "add " - | RISCV_SUB => "sub " - | RISCV_SLL => "sll " - | RISCV_SLT => "slt " - | RISCV_SLTU => "sltu " - | RISCV_XOR => "xor " - | RISCV_SRL => "srl " - | RISCV_SRA => "sra " - | RISCV_OR => "or " - | RISCV_AND => "and " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => - let (insn : string) = -((case (width, is_unsigned) of - (BYTE, F) => "lb " - | (BYTE, T) => "lbu " - | (HALF, F) => "lh " - | (HALF, T) => "lhu " - | (WORD, F) => "lw " - | (WORD, T) => "lwu " - | (_, _) => "ld.bad " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | STORE (imm,rs2,rs1,width,aq,rl) => - let (insn : string) = -((case width of - BYTE => "sb " - | HALF => "sh " - | WORD => "sw " - | DOUBLE => "sd " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rs2)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | ADDIW (imm,rs1,rd) => - STRCAT "addiw " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | SHIFTW (shamt,rs1,rd,op) => - let (insn : string) = -((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) - | RTYPEW (rs2,rs1,rd,op) => - let (insn : string) = -((case op of - RISCV_ADDW => "addw " - | RISCV_SUBW => "subw " - | RISCV_SLLW => "sllw " - | RISCV_SRLW => "srlw " - | RISCV_SRAW => "sraw " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | MUL (rs2,rs1,rd,high,signed1,signed2) => - let (insn : string) = -((case (high, signed1, signed2) of - (F, T, T) => "mul " - | (T, T, T) => "mulh " - | (T, T, F) => "mulhsu " - | (T, F, F) => "mulhu" - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | DIV0 (rs2,rs1,rd,s) => - let (insn : string) = (if s then "div " else "divu ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | REM (rs2,rs1,rd,s) => - let (insn : string) = (if s then "rem " else "remu ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | MULW (rs2,rs1,rd) => - STRCAT "mulw " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | DIVW (rs2,rs1,rd,s) => - let (insn : string) = (if s then "divw " else "divuw ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | REMW (rs2,rs1,rd,s) => - let (insn : string) = (if s then "remw " else "remuw ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | FENCE (pred,succ) => "fence" - | FENCEI (g__93) => "fence.i" - | ECALL (g__94) => "ecall" - | MRET (g__95) => "mret" - | SRET (g__96) => "sret" - | EBREAK (g__97) => "ebreak" - | WFI (g__98) => "wfi" - | SFENCE_VMA (rs1,rs2) => - STRCAT "sfence.vma " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))) - | LOADRES (aq,rl,rs1,width,rd) => - let (insn : string) = -((case width of WORD => "lr.w " | DOUBLE => "lr.d " | _ => "lr.bad " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1)))))) - | STORECON (aq,rl,rs2,rs1,width,rd) => - let (insn : string) = -((case width of WORD => "sc.w " | DOUBLE => "sc.d " | _ => "sc.bad " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | AMO (op,aq,rl,rs2,rs1,width,rd) => - let (insn : string) = -((case (op, width) of - (AMOSWAP, WORD) => "amoswap.w " - | (AMOADD, WORD) => "amoadd.w " - | (AMOXOR, WORD) => "amoxor.w " - | (AMOAND, WORD) => "amoand.w " - | (AMOOR, WORD) => "amoor.w " - | (AMOMIN, WORD) => "amomin.w " - | (AMOMAX, WORD) => "amomax.w " - | (AMOMINU, WORD) => "amominu.w " - | (AMOMAXU, WORD) => "amomaxu.w " - | (AMOSWAP, DOUBLE) => "amoswap.d " - | (AMOADD, DOUBLE) => "amoadd.d " - | (AMOXOR, DOUBLE) => "amoxor.d " - | (AMOAND, DOUBLE) => "amoand.d " - | (AMOOR, DOUBLE) => "amoor.d " - | (AMOMIN, DOUBLE) => "amomin.d " - | (AMOMAX, DOUBLE) => "amomax.d " - | (AMOMINU, DOUBLE) => "amominu.d " - | (AMOMAXU, DOUBLE) => "amomaxu.d " - | (_, _) => "amo.bad " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | CSR (csr,rs1,rd,is_imm,op) => - let (insn : string) = -((case (op, is_imm) of - (CSRRW, T) => "csrrwi " - | (CSRRW, F) => "csrrw " - | (CSRRS, T) => "csrrsi " - | (CSRRS, F) => "csrrs " - | (CSRRC, T) => "csrrci " - | (CSRRC, F) => "csrrc " - )) in - let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr)))))))))) - | NOP (g__99) => "nop" - | ILLEGAL (g__100) => "illegal" - | C_ADDI4SPN (rdc,nzimm) => - STRCAT "c.addi4spn " - ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec nzimm)))))) - | C_LW (uimm,rsc,rdc) => - STRCAT "c.lw " - ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) - ((STRCAT ", " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) - | C_LD (uimm,rsc,rdc) => - STRCAT "c.ld " - ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) - ((STRCAT ", " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) - | C_SW (uimm,rsc1,rsc2) => - STRCAT "c.sw " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) - ((STRCAT ", " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) - | C_SD (uimm,rsc1,rsc2) => - STRCAT "c.sd " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) - ((STRCAT ", " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) - | C_ADDI (nzi,rsd) => - STRCAT "c.addi " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi)))))) - | C_JAL (imm) => STRCAT "c.jal " ((string_of_vec imm)) - | C_ADDIW (imm,rsd) => - STRCAT "c.addiw " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm)))))) - | C_LI (imm,rd) => - STRCAT "c.li " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | C_ADDI16SP (imm) => STRCAT "c.addi16sp " ((string_of_vec imm)) - | C_LUI (imm,rd) => - STRCAT "c.lui " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | C_SRLI (shamt,rsd) => - STRCAT "c.srli " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec shamt)))))) - | C_SRAI (shamt,rsd) => - STRCAT "c.srai " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec shamt)))))) - | C_ANDI (imm,rsd) => - STRCAT "c.andi " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) - | C_SUB (rsd,rs2) => - STRCAT "c.sub " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_XOR (rsd,rs2) => - STRCAT "c.xor " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_OR (rsd,rs2) => - STRCAT "c.or " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_AND (rsd,rs2) => - STRCAT "c.and " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_SUBW (rsd,rs2) => - STRCAT "c.subw " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_ADDW (rsd,rs2) => - STRCAT "c.addw " - ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_J (imm) => STRCAT "c.j " ((string_of_vec imm)) - | C_BEQZ (imm,rs) => - STRCAT "c.beqz " - ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) - | C_BNEZ (imm,rs) => - STRCAT "c.bnez " - ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) - | C_SLLI (shamt,rsd) => - STRCAT "c.slli " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt)))))) - | C_LWSP (uimm,rd) => - STRCAT "c.lwsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) - | C_LDSP (uimm,rd) => - STRCAT "c.ldsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) - | C_SWSP (uimm,rd) => - STRCAT "c.swsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) - | C_SDSP (uimm,rd) => - STRCAT "c.sdsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) - | C_JR (rs1) => STRCAT "c.jr " ((reg_name_abi rs1)) - | C_JALR (rs1) => STRCAT "c.jalr " ((reg_name_abi rs1)) - | C_MV (rd,rs2) => - STRCAT "c.mv " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs2)))))) - | C_ADD (rsd,rs2) => - STRCAT "c.add " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2)))))) - )))`; - - -(*val isRVC : Machine_word.mword Machine_word.ty16 -> bool*) - -val _ = Define ` - ((isRVC:(16)words$word -> bool) h= - (~ (((((subrange_vec_dec h (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))`; - - -(*val fetch : unit -> Riscv_sequential_types.M Riscv_sequential_types.FetchResult*) - -val _ = Define ` - ((fetch:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$FetchResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) . bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) . bindS -(haveRVC () ) (\ (w__2 : bool) . - if ((((((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):sail_values$ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))) \/ ((((((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):sail_values$ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))) /\ ((~ w__2)))))))) then bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : 64 words$word) . - returnS (F_Error (E_Fetch_Addr_Align,w__3))) - else bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : 64 words$word) . bindS -(translateAddr w__4 Execute Instruction) (\ (w__5 : riscv_sequential_types$TR_Result) . - (case w__5 of - TR_Failure (e) => bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . - returnS (F_Error (e,w__6))) - | TR_Address (ppclo) => bindS - (checked_mem_read Instruction ppclo (( 2 : int):sail_values$ii) : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__7 : ( 16 words$word) - riscv_sequential_types$MemoryOpResult) . - (case w__7 of - MemException (e) => bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 : 64 words$word) . - returnS (F_Error (E_Fetch_Access_Fault,w__8))) - | MemValue (ilo) => - if ((isRVC ilo)) then returnS (F_RVC ilo) - else bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__9 : 64 words$word) . - let (PChi : riscv_sequential_types$xlenbits) = ((add_vec_int w__9 (( 2 : int):sail_values$ii) : 64 words$word)) in bindS -(translateAddr PChi Execute Instruction) (\ (w__10 : riscv_sequential_types$TR_Result) . - (case w__10 of - TR_Failure (e) => returnS (F_Error (e,PChi)) - | TR_Address (ppchi) => bindS - (checked_mem_read Instruction ppchi (( 2 : int):sail_values$ii) : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__11 : ( 16 words$word) - riscv_sequential_types$MemoryOpResult) . - returnS ((case w__11 of - MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) - | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word)) - ))) - ))) - )) - ))))))))`; - - -(*val step : unit -> Riscv_sequential_types.M bool*) - -val _ = Define ` - ((step:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () = (bindS -(read_regS mip_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mie_ref) (\ (w__1 : riscv_sequential_types$Minterrupts) . bindS -(read_regS mideleg_ref) (\ (w__2 : riscv_sequential_types$Minterrupts) . bindS -(curInterrupt w__0 w__1 w__2) (\ (w__3 : ((riscv_sequential_types$InterruptType # riscv_sequential_types$Privilege))option) . - (case w__3 of - SOME (intr,priv) => - let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr : 4 words$word))) in seqS -(handle_interrupt intr priv) (returnS F) - | NONE => bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . - let (_ : unit) = (print_bits "PC: " w__4) in bindS -(fetch () ) (\ (w__5 : riscv_sequential_types$FetchResult) . - (case w__5 of - F_Error (e,addr) => seqS (handle_mem_exception addr e) (returnS F) - | F_RVC (h) => - (case ((decodeCompressed h)) of - NONE => - let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec h)) " : <no-decode>"))) in seqS -(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) h : 64 words$word))) (returnS F) - | SOME (ast) => - let (_ : unit) = -(prerr_endline - ((STRCAT ((string_of_vec h)) ((STRCAT " : " ((print_insn ast))))))) in bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 : 64 words$word) . seqS (seqS -(write_regS nextPC_ref ((add_vec_int w__6 (( 2 : int):sail_values$ii) : 64 words$word))) -(execute ast)) (returnS T)) - ) - | F_Base (w) => - (case ((decode w)) of - NONE => - let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec w)) " : <no-decode>"))) in seqS -(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) w : 64 words$word))) (returnS F) - | SOME (ast) => - let (_ : unit) = -(prerr_endline - ((STRCAT ((string_of_vec w)) ((STRCAT " : " ((print_insn ast))))))) in bindS - (read_regS PC_ref : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 : 64 words$word) . seqS (seqS -(write_regS nextPC_ref ((add_vec_int w__8 (( 4 : int):sail_values$ii) : 64 words$word))) -(execute ast)) (returnS T)) - ) - ))) - )))))))`; - - - -val _ = export_theory() - diff --git a/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml b/snapshots/hol4/sail/riscv/riscv_typesScript.sml index e9b73fd8..4637d1df 100644 --- a/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml +++ b/snapshots/hol4/sail/riscv/riscv_typesScript.sml @@ -1,20 +1,20 @@ -(*Generated by Lem from riscv_sequential_types.lem.*) +(*Generated by Lem from riscv_types.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory; +open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; val _ = numLib.prefer_num(); -val _ = new_theory "riscv_sequential_types" +val _ = new_theory "riscv_types" -(*Generated by Sail from riscv_sequential.*) +(*Generated by Sail from riscv.*) (*open import Pervasives_extra*) (*open import Sail_instr_kinds*) (*open import Sail_values*) (*open import Sail_operators_mwords*) -(*open import State_monad*) -(*open import State*) +(*open import Prompt_monad*) +(*open import Prompt*) val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); @@ -117,11 +117,7 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` - exception = - Error_not_implemented of (string) - | Error_misaligned_access of (unit) - | Error_EBREAK of (unit) - | Error_internal_error of (unit)`; + exception = Error_not_implemented of (string) | Error_internal_error of (unit)`; @@ -328,7 +324,7 @@ val _ = type_abbrev( "asid64" , ``: 16 bits``); val _ = Hol_datatype ` PTW_Result = - PTW_Success of ((paddr39 # SV39_PTE # paddr39 # sail_values$ii # bool)) | PTW_Failure of (PTW_Error)`; + PTW_Success of ((paddr39 # SV39_PTE # paddr39 # ii # bool)) | PTW_Failure of (PTW_Error)`; @@ -437,7 +433,7 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` register_value = - Regval_vector of ((sail_values$ii # bool # register_value list)) + Regval_vector of ((ii # bool # register_value list)) | Regval_list of ( register_value list) | Regval_option of ( register_value option) | Regval_Mcause of (Mcause) @@ -458,6 +454,7 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` regstate = <| tlb39 : TLB39_Entry option; + tselect : 64 words$word; stval : 64 words$word; scause : Mcause; sepc : 64 words$word; @@ -496,11 +493,11 @@ val _ = Hol_datatype ` -(*val Mcause_of_regval : register_value -> Maybe.maybe Mcause*) +(*val Mcause_of_regval : register_value -> maybe Mcause*) val _ = Define ` - ((Mcause_of_regval:register_value ->(Mcause)option) merge_var= - ((case merge_var of Regval_Mcause (v) => SOME v | g__92 => NONE )))`; + ((Mcause_of_regval:register_value ->(Mcause)option) merge_var= + ((case merge_var of Regval_Mcause (v) => SOME v | g__92 => NONE )))`; (*val regval_of_Mcause : Mcause -> register_value*) @@ -509,11 +506,11 @@ val _ = Define ` ((regval_of_Mcause:Mcause -> register_value) v= (Regval_Mcause v))`; -(*val Medeleg_of_regval : register_value -> Maybe.maybe Medeleg*) +(*val Medeleg_of_regval : register_value -> maybe Medeleg*) val _ = Define ` - ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var= - ((case merge_var of Regval_Medeleg (v) => SOME v | g__91 => NONE )))`; + ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var= + ((case merge_var of Regval_Medeleg (v) => SOME v | g__91 => NONE )))`; (*val regval_of_Medeleg : Medeleg -> register_value*) @@ -522,11 +519,11 @@ val _ = Define ` ((regval_of_Medeleg:Medeleg -> register_value) v= (Regval_Medeleg v))`; -(*val Minterrupts_of_regval : register_value -> Maybe.maybe Minterrupts*) +(*val Minterrupts_of_regval : register_value -> maybe Minterrupts*) val _ = Define ` - ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var= - ((case merge_var of Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`; + ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var= + ((case merge_var of Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`; (*val regval_of_Minterrupts : Minterrupts -> register_value*) @@ -535,11 +532,11 @@ val _ = Define ` ((regval_of_Minterrupts:Minterrupts -> register_value) v= (Regval_Minterrupts v))`; -(*val Misa_of_regval : register_value -> Maybe.maybe Misa*) +(*val Misa_of_regval : register_value -> maybe Misa*) val _ = Define ` - ((Misa_of_regval:register_value ->(Misa)option) merge_var= - ((case merge_var of Regval_Misa (v) => SOME v | g__89 => NONE )))`; + ((Misa_of_regval:register_value ->(Misa)option) merge_var= + ((case merge_var of Regval_Misa (v) => SOME v | g__89 => NONE )))`; (*val regval_of_Misa : Misa -> register_value*) @@ -548,11 +545,11 @@ val _ = Define ` ((regval_of_Misa:Misa -> register_value) v= (Regval_Misa v))`; -(*val Mstatus_of_regval : register_value -> Maybe.maybe Mstatus*) +(*val Mstatus_of_regval : register_value -> maybe Mstatus*) val _ = Define ` - ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var= - ((case merge_var of Regval_Mstatus (v) => SOME v | g__88 => NONE )))`; + ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var= + ((case merge_var of Regval_Mstatus (v) => SOME v | g__88 => NONE )))`; (*val regval_of_Mstatus : Mstatus -> register_value*) @@ -561,11 +558,11 @@ val _ = Define ` ((regval_of_Mstatus:Mstatus -> register_value) v= (Regval_Mstatus v))`; -(*val Mtvec_of_regval : register_value -> Maybe.maybe Mtvec*) +(*val Mtvec_of_regval : register_value -> maybe Mtvec*) val _ = Define ` - ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= - ((case merge_var of Regval_Mtvec (v) => SOME v | g__87 => NONE )))`; + ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= + ((case merge_var of Regval_Mtvec (v) => SOME v | g__87 => NONE )))`; (*val regval_of_Mtvec : Mtvec -> register_value*) @@ -574,11 +571,11 @@ val _ = Define ` ((regval_of_Mtvec:Mtvec -> register_value) v= (Regval_Mtvec v))`; -(*val Privilege_of_regval : register_value -> Maybe.maybe Privilege*) +(*val Privilege_of_regval : register_value -> maybe Privilege*) val _ = Define ` - ((Privilege_of_regval:register_value ->(Privilege)option) merge_var= - ((case merge_var of Regval_Privilege (v) => SOME v | g__86 => NONE )))`; + ((Privilege_of_regval:register_value ->(Privilege)option) merge_var= + ((case merge_var of Regval_Privilege (v) => SOME v | g__86 => NONE )))`; (*val regval_of_Privilege : Privilege -> register_value*) @@ -587,11 +584,11 @@ val _ = Define ` ((regval_of_Privilege:Privilege -> register_value) v= (Regval_Privilege v))`; -(*val Sedeleg_of_regval : register_value -> Maybe.maybe Sedeleg*) +(*val Sedeleg_of_regval : register_value -> maybe Sedeleg*) val _ = Define ` - ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var= - ((case merge_var of Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`; + ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var= + ((case merge_var of Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`; (*val regval_of_Sedeleg : Sedeleg -> register_value*) @@ -600,11 +597,11 @@ val _ = Define ` ((regval_of_Sedeleg:Sedeleg -> register_value) v= (Regval_Sedeleg v))`; -(*val Sinterrupts_of_regval : register_value -> Maybe.maybe Sinterrupts*) +(*val Sinterrupts_of_regval : register_value -> maybe Sinterrupts*) val _ = Define ` - ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var= - ((case merge_var of Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`; + ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var= + ((case merge_var of Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`; (*val regval_of_Sinterrupts : Sinterrupts -> register_value*) @@ -613,11 +610,11 @@ val _ = Define ` ((regval_of_Sinterrupts:Sinterrupts -> register_value) v= (Regval_Sinterrupts v))`; -(*val TLB39_Entry_of_regval : register_value -> Maybe.maybe TLB39_Entry*) +(*val TLB39_Entry_of_regval : register_value -> maybe TLB39_Entry*) val _ = Define ` - ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var= - ((case merge_var of Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`; + ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var= + ((case merge_var of Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`; (*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) @@ -626,14 +623,14 @@ val _ = Define ` ((regval_of_TLB39_Entry:TLB39_Entry -> register_value) v= (Regval_TLB39_Entry v))`; -(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*) +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) val _ = Define ` - ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= - ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`; + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`; -(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*) +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) val _ = Define ` ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; @@ -641,7 +638,7 @@ val _ = Define ` -(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= (\x . (case x of @@ -650,12 +647,12 @@ val _ = Define ` )))`; -(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*) +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) val _ = Define ` ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; -(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*) +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= (\x . (case x of @@ -669,20 +666,23 @@ val _ = Define ` ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; -(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*) +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) val _ = Define ` ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= - (\x . (case x of Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`; + (\x . (case x of + Regval_option v => SOME (OPTION_BIND v of_regval) + | _ => NONE + )))`; -(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*) +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) val _ = Define ` ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; val _ = Define ` - ((tlb39_ref:((regstate),(register_value),((TLB39_Entry)option))sail_values$register_ref)= (<| + ((tlb39_ref:((regstate),(register_value),((TLB39_Entry)option))register_ref)= (<| name := "tlb39"; read_from := (\ s . s.tlb39); write_to := (\ v s . (( s with<| tlb39 := v |>))); @@ -691,7 +691,16 @@ val _ = Define ` val _ = Define ` - ((stval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((tselect_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "tselect"; + read_from := (\ s . s.tselect); + write_to := (\ v s . (( s with<| tselect := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((stval_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "stval"; read_from := (\ s . s.stval); write_to := (\ v s . (( s with<| stval := v |>))); @@ -700,7 +709,7 @@ val _ = Define ` val _ = Define ` - ((scause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)= (<| + ((scause_ref:((regstate),(register_value),(Mcause))register_ref)= (<| name := "scause"; read_from := (\ s . s.scause); write_to := (\ v s . (( s with<| scause := v |>))); @@ -709,7 +718,7 @@ val _ = Define ` val _ = Define ` - ((sepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((sepc_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "sepc"; read_from := (\ s . s.sepc); write_to := (\ v s . (( s with<| sepc := v |>))); @@ -718,7 +727,7 @@ val _ = Define ` val _ = Define ` - ((sscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((sscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "sscratch"; read_from := (\ s . s.sscratch); write_to := (\ v s . (( s with<| sscratch := v |>))); @@ -727,7 +736,7 @@ val _ = Define ` val _ = Define ` - ((stvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)= (<| + ((stvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<| name := "stvec"; read_from := (\ s . s.stvec); write_to := (\ v s . (( s with<| stvec := v |>))); @@ -736,7 +745,7 @@ val _ = Define ` val _ = Define ` - ((satp_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((satp_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "satp"; read_from := (\ s . s.satp); write_to := (\ v s . (( s with<| satp := v |>))); @@ -745,7 +754,7 @@ val _ = Define ` val _ = Define ` - ((sideleg_ref:((regstate),(register_value),(Sinterrupts))sail_values$register_ref)= (<| + ((sideleg_ref:((regstate),(register_value),(Sinterrupts))register_ref)= (<| name := "sideleg"; read_from := (\ s . s.sideleg); write_to := (\ v s . (( s with<| sideleg := v |>))); @@ -754,7 +763,7 @@ val _ = Define ` val _ = Define ` - ((sedeleg_ref:((regstate),(register_value),(Sedeleg))sail_values$register_ref)= (<| + ((sedeleg_ref:((regstate),(register_value),(Sedeleg))register_ref)= (<| name := "sedeleg"; read_from := (\ s . s.sedeleg); write_to := (\ v s . (( s with<| sedeleg := v |>))); @@ -763,7 +772,7 @@ val _ = Define ` val _ = Define ` - ((pmpcfg0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((pmpcfg0_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "pmpcfg0"; read_from := (\ s . s.pmpcfg0); write_to := (\ v s . (( s with<| pmpcfg0 := v |>))); @@ -772,7 +781,7 @@ val _ = Define ` val _ = Define ` - ((pmpaddr0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((pmpaddr0_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "pmpaddr0"; read_from := (\ s . s.pmpaddr0); write_to := (\ v s . (( s with<| pmpaddr0 := v |>))); @@ -781,7 +790,7 @@ val _ = Define ` val _ = Define ` - ((mhartid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mhartid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mhartid"; read_from := (\ s . s.mhartid); write_to := (\ v s . (( s with<| mhartid := v |>))); @@ -790,7 +799,7 @@ val _ = Define ` val _ = Define ` - ((marchid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((marchid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "marchid"; read_from := (\ s . s.marchid); write_to := (\ v s . (( s with<| marchid := v |>))); @@ -799,7 +808,7 @@ val _ = Define ` val _ = Define ` - ((mimpid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mimpid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mimpid"; read_from := (\ s . s.mimpid); write_to := (\ v s . (( s with<| mimpid := v |>))); @@ -808,7 +817,7 @@ val _ = Define ` val _ = Define ` - ((mvendorid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mvendorid_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mvendorid"; read_from := (\ s . s.mvendorid); write_to := (\ v s . (( s with<| mvendorid := v |>))); @@ -817,7 +826,7 @@ val _ = Define ` val _ = Define ` - ((minstret_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((minstret_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "minstret"; read_from := (\ s . s.minstret); write_to := (\ v s . (( s with<| minstret := v |>))); @@ -826,7 +835,7 @@ val _ = Define ` val _ = Define ` - ((mtime_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mtime_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mtime"; read_from := (\ s . s.mtime); write_to := (\ v s . (( s with<| mtime := v |>))); @@ -835,7 +844,7 @@ val _ = Define ` val _ = Define ` - ((mcycle_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mcycle_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mcycle"; read_from := (\ s . s.mcycle); write_to := (\ v s . (( s with<| mcycle := v |>))); @@ -844,7 +853,7 @@ val _ = Define ` val _ = Define ` - ((mscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mscratch"; read_from := (\ s . s.mscratch); write_to := (\ v s . (( s with<| mscratch := v |>))); @@ -853,7 +862,7 @@ val _ = Define ` val _ = Define ` - ((mtval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mtval_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mtval"; read_from := (\ s . s.mtval); write_to := (\ v s . (( s with<| mtval := v |>))); @@ -862,7 +871,7 @@ val _ = Define ` val _ = Define ` - ((mepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((mepc_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mepc"; read_from := (\ s . s.mepc); write_to := (\ v s . (( s with<| mepc := v |>))); @@ -871,7 +880,7 @@ val _ = Define ` val _ = Define ` - ((mcause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)= (<| + ((mcause_ref:((regstate),(register_value),(Mcause))register_ref)= (<| name := "mcause"; read_from := (\ s . s.mcause); write_to := (\ v s . (( s with<| mcause := v |>))); @@ -880,7 +889,7 @@ val _ = Define ` val _ = Define ` - ((mtvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)= (<| + ((mtvec_ref:((regstate),(register_value),(Mtvec))register_ref)= (<| name := "mtvec"; read_from := (\ s . s.mtvec); write_to := (\ v s . (( s with<| mtvec := v |>))); @@ -889,7 +898,7 @@ val _ = Define ` val _ = Define ` - ((medeleg_ref:((regstate),(register_value),(Medeleg))sail_values$register_ref)= (<| + ((medeleg_ref:((regstate),(register_value),(Medeleg))register_ref)= (<| name := "medeleg"; read_from := (\ s . s.medeleg); write_to := (\ v s . (( s with<| medeleg := v |>))); @@ -898,7 +907,7 @@ val _ = Define ` val _ = Define ` - ((mideleg_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + ((mideleg_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<| name := "mideleg"; read_from := (\ s . s.mideleg); write_to := (\ v s . (( s with<| mideleg := v |>))); @@ -907,7 +916,7 @@ val _ = Define ` val _ = Define ` - ((mie_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + ((mie_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<| name := "mie"; read_from := (\ s . s.mie); write_to := (\ v s . (( s with<| mie := v |>))); @@ -916,7 +925,7 @@ val _ = Define ` val _ = Define ` - ((mip_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)= (<| + ((mip_ref:((regstate),(register_value),(Minterrupts))register_ref)= (<| name := "mip"; read_from := (\ s . s.mip); write_to := (\ v s . (( s with<| mip := v |>))); @@ -925,7 +934,7 @@ val _ = Define ` val _ = Define ` - ((mstatus_ref:((regstate),(register_value),(Mstatus))sail_values$register_ref)= (<| + ((mstatus_ref:((regstate),(register_value),(Mstatus))register_ref)= (<| name := "mstatus"; read_from := (\ s . s.mstatus); write_to := (\ v s . (( s with<| mstatus := v |>))); @@ -934,7 +943,7 @@ val _ = Define ` val _ = Define ` - ((misa_ref:((regstate),(register_value),(Misa))sail_values$register_ref)= (<| + ((misa_ref:((regstate),(register_value),(Misa))register_ref)= (<| name := "misa"; read_from := (\ s . s.misa); write_to := (\ v s . (( s with<| misa := v |>))); @@ -943,7 +952,7 @@ val _ = Define ` val _ = Define ` - ((cur_inst_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((cur_inst_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "cur_inst"; read_from := (\ s . s.cur_inst); write_to := (\ v s . (( s with<| cur_inst := v |>))); @@ -952,7 +961,7 @@ val _ = Define ` val _ = Define ` - ((cur_privilege_ref:((regstate),(register_value),(Privilege))sail_values$register_ref)= (<| + ((cur_privilege_ref:((regstate),(register_value),(Privilege))register_ref)= (<| name := "cur_privilege"; read_from := (\ s . s.cur_privilege); write_to := (\ v s . (( s with<| cur_privilege := v |>))); @@ -961,7 +970,7 @@ val _ = Define ` val _ = Define ` - ((Xs_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)= (<| + ((Xs_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| name := "Xs"; read_from := (\ s . s.Xs); write_to := (\ v s . (( s with<| Xs := v |>))); @@ -970,7 +979,7 @@ val _ = Define ` val _ = Define ` - ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((nextPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "nextPC"; read_from := (\ s . s.nextPC); write_to := (\ v s . (( s with<| nextPC := v |>))); @@ -979,7 +988,7 @@ val _ = Define ` val _ = Define ` - ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)= (<| + ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "PC"; read_from := (\ s . s.PC); write_to := (\ v s . (( s with<| PC := v |>))); @@ -987,10 +996,11 @@ val _ = Define ` regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; -(*val get_regval : string -> regstate -> Maybe.maybe register_value*) +(*val get_regval : string -> regstate -> maybe register_value*) val _ = Define ` - ((get_regval:string -> regstate ->(register_value)option) reg_name s= - (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else + if reg_name = "tselect" then SOME (tselect_ref.regval_of (tselect_ref.read_from s)) else if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else if reg_name = "sepc" then SOME (sepc_ref.regval_of (sepc_ref.read_from s)) else @@ -1027,10 +1037,11 @@ val _ = Define ` NONE))`; -(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*) +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) val _ = Define ` - ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= - (if reg_name = "tlb39" then OPTION_MAP (\ v . tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "tlb39" then OPTION_MAP (\ v . tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else + if reg_name = "tselect" then OPTION_MAP (\ v . tselect_ref.write_to v s) (tselect_ref.of_regval v) else if reg_name = "stval" then OPTION_MAP (\ v . stval_ref.write_to v s) (stval_ref.of_regval v) else if reg_name = "scause" then OPTION_MAP (\ v . scause_ref.write_to v s) (scause_ref.of_regval v) else if reg_name = "sepc" then OPTION_MAP (\ v . sepc_ref.write_to v s) (sepc_ref.of_regval v) else @@ -1072,7 +1083,7 @@ val _ = Define ` -val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``); -val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``); +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``); val _ = export_theory() |