diff options
Diffstat (limited to 'snapshots')
34 files changed, 73101 insertions, 8607 deletions
diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md index 5ce3b5cb..5ce37726 100644 --- a/snapshots/hol4/README.md +++ b/snapshots/hol4/README.md @@ -1,12 +1,5 @@ # Snapshot of HOL4 output for Sail CHERI and RISC-V models These theories are a snapshot of the generated files for the Sail -CHERI and RISC-V models, translated to HOL4 via Lem. - -Generated using the following repository versions: -HOL4: (master) bb9eaf3448d2c44c84c5d06849d0dc73db23670c, 17 May 2018 -Lem: (master) 55cb119f5b9e9feae8ed02c1b63ef38360eff3a1, 17 May 2018 -Sail: (sail2) b08f0e8538081d8efbbbd6431e739a0b83307678, 17 May 2018 - -The theories are accepted by HOL4, but we have not done any -further testing of them yet. +MIPS, CHERI, RISC-V, and Aarch64 models, translated to HOL4 via Lem. +They only require HOL4; the necessary Lem library files are included. diff --git a/snapshots/hol4/build b/snapshots/hol4/build index 2b8be130..e85bdb13 100755 --- a/snapshots/hol4/build +++ b/snapshots/hol4/build @@ -1,5 +1,5 @@ #!/bin/bash -for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do +for d in lem/hol-lib sail/lib/hol sail/mips sail/cheri sail/riscv sail/aarch64; do (cd $d; Holmake) done diff --git a/snapshots/hol4/clean b/snapshots/hol4/clean index f4301d3f..822fede5 100755 --- a/snapshots/hol4/clean +++ b/snapshots/hol4/clean @@ -1,5 +1,5 @@ #!/bin/bash -for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do +for d in lem/hol-lib sail/lib/hol sail/mips sail/cheri sail/riscv sail/aarch64; do (cd $d; Holmake cleanAll) done diff --git a/snapshots/hol4/lem/hol-lib/lem_numScript.sml b/snapshots/hol4/lem/hol-lib/lem_numScript.sml index 6064416b..de65941f 100644 --- a/snapshots/hol4/lem/hol-lib/lem_numScript.sml +++ b/snapshots/hol4/lem/hol-lib/lem_numScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from num.lem.*) open HolKernel Parse boolLib bossLib; -open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory; +open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory transcTheory; val _ = numLib.prefer_num(); @@ -12,8 +12,8 @@ val _ = new_theory "lem_num" (*open import Bool Basic_classes*) (*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*) -(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*) -(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) +(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`*) +(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) (*class inline ( Numeral 'a ) val fromNumeral : numeral -> 'a diff --git a/snapshots/hol4/sail/aarch64/Holmakefile b/snapshots/hol4/sail/aarch64/Holmakefile new file mode 100644 index 00000000..feafe6c4 --- /dev/null +++ b/snapshots/hol4/sail/aarch64/Holmakefile @@ -0,0 +1,11 @@ +LEMDIR=../../lem/hol-lib + +INCLUDES = $(LEMDIR) ../lib/hol + +all: aarch64_monoTheory.uo +.PHONY: all + +ifdef POLY +HOLHEAP = ../lib/hol/sail-heap + +endif diff --git a/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml b/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml new file mode 100644 index 00000000..51d55245 --- /dev/null +++ b/snapshots/hol4/sail/aarch64/aarch64_extrasScript.sml @@ -0,0 +1,135 @@ +(*Generated by Lem from ../aarch64_extras.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "aarch64_extras" + +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) + +(*type ty512*) +(*type ty1024*) +(*type ty2048*) + +val _ = Define ` + ((hexchar_to_bool_list:char ->((bool)list)option) c= + (if c = #"0" then SOME ([F;F;F;F]) + else if c = #"1" then SOME ([F;F;F;T ]) + else if c = #"2" then SOME ([F;F;T; F]) + else if c = #"3" then SOME ([F;F;T; T ]) + else if c = #"4" then SOME ([F;T; F;F]) + else if c = #"5" then SOME ([F;T; F;T ]) + else if c = #"6" then SOME ([F;T; T; F]) + else if c = #"7" then SOME ([F;T; T; T ]) + else if c = #"8" then SOME ([T; F;F;F]) + else if c = #"9" then SOME ([T; F;F;T ]) + else if c = #"A" then SOME ([T; F;T; F]) + else if c = #"a" then SOME ([T; F;T; F]) + else if c = #"B" then SOME ([T; F;T; T ]) + else if c = #"b" then SOME ([T; F;T; T ]) + else if c = #"C" then SOME ([T; T; F;F]) + else if c = #"c" then SOME ([T; T; F;F]) + else if c = #"D" then SOME ([T; T; F;T ]) + else if c = #"d" then SOME ([T; T; F;T ]) + else if c = #"E" then SOME ([T; T; T; F]) + else if c = #"e" then SOME ([T; T; T; F]) + else if c = #"F" then SOME ([T; T; T; T ]) + else if c = #"f" then SOME ([T; T; T; T ]) + else NONE))`; + + +val _ = Define ` + ((hexstring_to_bools:string ->((bool)list)option) s= + ((case (EXPLODE s) of + z :: x :: hs => + let str = (if ((z = #"0") /\ (x = #"x")) then hs else z :: (x :: hs)) in + OPTION_MAP FLAT (just_list (MAP hexchar_to_bool_list str)) + | _ => NONE + )))`; + + +(*val hex_slice : forall 'rv 'n 'e. Size 'n => string -> integer -> integer -> monad 'rv (mword 'n) 'e*) +val _ = Define ` + ((hex_slice:string -> int -> int -> 'rv sail2_state_monad$sequential_state ->((('n words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) v len lo= (sail2_state_monad$bindS + (sail2_state_monad$maybe_failS "hex_slice" (hexstring_to_bools v)) (\ bs . + let hi = ((len + lo) -( 1 : int)) in + let bs = (ext_list F (len + lo) bs) in + sail2_state_monad$returnS (bitstring$v2w (subrange_list F bs hi lo)))))`; + + +(*val BigEndianReverse : forall 'rv 'n 'e. Size 'n => mword 'n -> monad 'rv (mword 'n) 'e*) +val _ = Define ` + ((BigEndianReverse:'n words$word -> 'rv sail2_state_monad$sequential_state ->((('n words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) w= (sail2_state_monad$returnS (reverse_endianness w)))`; + + +(* Use constants for some undefined values for now *) +val _ = Define ` + ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS ""))`; + +val _ = Define ` + ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`; + +val _ = Define ` + ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +val _ = Define ` + ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u= (sail2_state_monad$returnS (repeat [u] len)))`; + +(*val undefined_bitvector : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*) +val _ = Define ` + ((undefined_bitvector:int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len= (sail2_state_monad$returnS (bitstring$v2w (repeat [F] len))))`; + +(*val undefined_bits : forall 'rv 'a 'e. Size 'a => integer -> monad 'rv (mword 'a) 'e*) +val _ = Define ` + ((undefined_bits:int ->('rv,('a words$word),'e)monad)= undefined_bitvector)`; + +val _ = Define ` + ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS B0))`; + +val _ = Define ` + ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; + +val _ = Define ` + ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j= (sail2_state_monad$returnS i))`; + +val _ = Define ` + ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i= (sail2_state_monad$returnS i))`; + +val _ = Define ` + ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; + + +(*val write_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c => + integer -> integer -> mword 'a -> mword 'b -> mword 'c -> monad 'rv unit 'e*) +val _ = Define ` + ((write_ram:int -> int -> 'a words$word -> 'b words$word -> 'c words$word -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address value= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1)) + (sail2_state_monad$write_mem_valS + instance_Sail2_values_Bitvector_Machine_word_mword_dict value)) (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; + + +(*val read_ram : forall 'rv 'a 'b 'c 'e. Size 'b, Size 'c => + integer -> integer -> mword 'a -> mword 'b -> monad 'rv (mword 'c) 'e*) +val _ = Define ` + ((read_ram:int -> int -> 'a words$word -> 'b words$word -> 'rv sail2_state_monad$sequential_state ->((('c words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address= + ( + (*let _ = prerr_endline ("Reading " ^ (stringFromInteger size) ^ " bytes from address " ^ (stringFromInteger (unsigned address))) in*)sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; + + +(*val elf_entry : unit -> integer*) +val _ = Define ` + ((elf_entry:unit -> int) () = (( 0 : int)))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml new file mode 100644 index 00000000..b454337e --- /dev/null +++ b/snapshots/hol4/sail/aarch64/aarch64_monoScript.sml @@ -0,0 +1,36178 @@ +(*Generated by Lem from aarch64_mono.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory aarch64_mono_typesTheory aarch64_extrasTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "aarch64_mono" + +(*Generated by Sail from aarch64_mono.*) +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) +(*open import Aarch64_mono_types*) +(*open import Aarch64_extras*) + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +val _ = Define ` + ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; + + +(*val vcons : forall 'a. 'a -> list 'a -> list 'a*) + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => itself 'n -> ii -> ii -> mword 'n*) + +val _ = Define ` + ((GetSlice_int:'n itself -> int -> int -> 'n words$word) n m o1= + (let n = (size_itself_int n) in + (get_slice_int n m o1 : 'n words$word)))`; + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +val _ = Define ` + ((cast_unit_vec0:bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val BoolStr : bool -> string*) + +val _ = Define ` + ((BoolStr:bool -> string) b= (if b then "true" else "false"))`; + + +(*val ex_nat : ii -> integer*) + +val _ = Define ` + ((ex_nat:int -> int) n= n)`; + + +(*val ex_int : ii -> integer*) + +val _ = Define ` + ((ex_int:int -> int) n= n)`; + + +(*val ex_range : integer -> integer*) + +(*val coerce_int_nat : ii -> M ii*) + +val _ = Define ` + ((coerce_int_nat:int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= (sail2_state_monad$seqS (sail2_state_monad$assert_expS T "Cannot coerce int to nat") (sail2_state_monad$returnS x)))`; + + +(*val break : unit -> unit*) + +val _ = Define ` + ((break:unit -> unit) () = () )`; + + +(*val undefined_exception : unit -> M exception*) + +val _ = Define ` + ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_string () ) (\ (u_0 : string) . sail2_state_monad$bindS + (undefined_unit () ) (\ (u_1 : unit) . + sail2_state$internal_pickS + [Error_Undefined u_1;Error_See u_0;Error_Implementation_Defined u_0;Error_ReservedEncoding u_1;Error_ExceptionTaken u_1]))))`; + + +(*val __GetVerbosity : unit -> M (bits ty64)*) + +(*val get_cycle_count : unit -> M ii*) + +(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*) + +val _ = Define ` + ((InitRAM:int -> int -> 'm words$word ->(8)words$word -> unit) g__302 g__303 g__304 g__305= () )`; + + +(*val __ReadRAM : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((ReadRAM:'m itself -> int -> 'm words$word -> 'm words$word ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr_length bytes hex_ram addr= + (let addr_length = (size_itself_int addr_length) in + (read_ram addr_length bytes hex_ram addr : ( 'p8_times_n_ words$word) M)))`; + + +(*val __TraceMemoryWrite : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*) + +(*val __WriteRAM : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> mword 'p8_times_n_ -> M unit*) + +val _ = Define ` + ((WriteRAM:'m itself -> int -> 'm words$word -> 'm words$word -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr_length bytes hex_ram addr data= + (let addr_length = (size_itself_int addr_length) in + write_ram addr_length bytes hex_ram addr data))`; + + +val _ = Define ` + ((TraceMemoryWrite:int -> 'm words$word -> 'p8_times_n_ words$word -> unit) bytes addr data= () )`; + + +(*val __TraceMemoryRead : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*) + +val _ = Define ` + ((TraceMemoryRead:int -> 'm words$word -> 'p8_times_n_ words$word -> unit) bytes addr data= () )`; + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((extz_vec m__tv v : 'm words$word)))`; + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((exts_vec m__tv v : 'm words$word)))`; + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +val _ = Define ` + ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l= + (let (one1 : 'n bits) = ((extzv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`; + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= + (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0] : 1 words$word) : 'n words$word))))`; + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j= + (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i)) : 'n words$word)) in + (((and_vec xs m : 'n words$word)) = m)))`; + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +val _ = Define ` + ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + let ys = + ((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l' : 'm words$word)) : 'm words$word)) i' + : 'm words$word)) in + (or_vec ((shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)) ((extzv r__tv ys : 'r words$word)) + : 'r words$word)))`; + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +val _ = Define ` + ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)))`; + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j')) : 'n words$word)) : 'n words$word)) + j' + : 'n words$word)) in + (xs = ys)))`; + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +val _ = Define ` + ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j')) : 'm words$word)) : 'm words$word)) + j' + : 'm words$word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs : 's words$word)) i' : 's words$word)) + ((j' - (( 1 : int):ii))) + : 's words$word)) ((extzv s__tv ys : 's words$word)) + : 's words$word)))`; + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (extzv m__tv xs : 'm words$word)))`; + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) + ((((((int_of_num (words$word_len xs))) - i)) - l)) + : 'n words$word)) ((((int_of_num (words$word_len xs))) - l)) + : 'n words$word)) in + (extsv m__tv xs : 'm words$word)))`; + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_slice:'n words$word -> int -> int -> int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + lem$w2ui xs))`; + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) i + : 'n words$word)) in + lem$w2ui xs))`; + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +val _ = Define ` + ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m= + (let (v : 'n bits) = ((extsv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftr v ((((int_of_num (words$word_len v))) - m)) : 'n words$word)))`; + + +(*val boolean_of_num : integer -> boolean*) + +val _ = Define ` + ((boolean_of_num:int -> boolean) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FALSE + else TRUE))`; + + +(*val num_of_boolean : boolean -> integer*) + +val _ = Define ` + ((num_of_boolean:boolean -> int) arg_= ((case arg_ of FALSE => (( 0 : int):ii) | TRUE => (( 1 : int):ii) )))`; + + +(*val undefined_boolean : unit -> M boolean*) + +val _ = Define ` + ((undefined_boolean:unit ->(regstate)sail2_state_monad$sequential_state ->(((boolean),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [FALSE;TRUE]))`; + + +(*val signal_of_num : integer -> signal*) + +val _ = Define ` + ((signal_of_num:int -> signal) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then LOW + else HIGH))`; + + +(*val num_of_signal : signal -> integer*) + +val _ = Define ` + ((num_of_signal:signal -> int) arg_= ((case arg_ of LOW => (( 0 : int):ii) | HIGH => (( 1 : int):ii) )))`; + + +(*val undefined_signal : unit -> M signal*) + +val _ = Define ` + ((undefined_signal:unit ->(regstate)sail2_state_monad$sequential_state ->(((signal),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [LOW;HIGH]))`; + + +(*val __RetCode_of_num : integer -> __RetCode*) + +val _ = Define ` + ((RetCode_of_num:int -> RetCode) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RC_OK + else if (((p0_ = (( 1 : int):ii)))) then RC_UNDEFINED + else if (((p0_ = (( 2 : int):ii)))) then RC_UNPREDICTABLE + else if (((p0_ = (( 3 : int):ii)))) then RC_SEE + else if (((p0_ = (( 4 : int):ii)))) then RC_IMPLEMENTATION_DEFINED + else if (((p0_ = (( 5 : int):ii)))) then RC_SUBARCHITECTURE_DEFINED + else if (((p0_ = (( 6 : int):ii)))) then RC_EXCEPTION_TAKEN + else if (((p0_ = (( 7 : int):ii)))) then RC_ASSERT_FAILED + else RC_UNMATCHED_CASE))`; + + +(*val num_of___RetCode : __RetCode -> integer*) + +val _ = Define ` + ((num_of___RetCode:RetCode -> int) arg_= + ((case arg_ of + RC_OK => (( 0 : int):ii) + | RC_UNDEFINED => (( 1 : int):ii) + | RC_UNPREDICTABLE => (( 2 : int):ii) + | RC_SEE => (( 3 : int):ii) + | RC_IMPLEMENTATION_DEFINED => (( 4 : int):ii) + | RC_SUBARCHITECTURE_DEFINED => (( 5 : int):ii) + | RC_EXCEPTION_TAKEN => (( 6 : int):ii) + | RC_ASSERT_FAILED => (( 7 : int):ii) + | RC_UNMATCHED_CASE => (( 8 : int):ii) + )))`; + + +(*val undefined___RetCode : unit -> M __RetCode*) + +val _ = Define ` + ((undefined___RetCode:unit ->(regstate)sail2_state_monad$sequential_state ->(((RetCode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [RC_OK;RC_UNDEFINED;RC_UNPREDICTABLE;RC_SEE;RC_IMPLEMENTATION_DEFINED;RC_SUBARCHITECTURE_DEFINED;RC_EXCEPTION_TAKEN;RC_ASSERT_FAILED;RC_UNMATCHED_CASE]))`; + + +(*val FPConvOp_of_num : integer -> FPConvOp*) + +val _ = Define ` + ((FPConvOp_of_num:int -> FPConvOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPConvOp_CVT_FtoI + else if (((p0_ = (( 1 : int):ii)))) then FPConvOp_CVT_ItoF + else if (((p0_ = (( 2 : int):ii)))) then FPConvOp_MOV_FtoI + else if (((p0_ = (( 3 : int):ii)))) then FPConvOp_MOV_ItoF + else FPConvOp_CVT_FtoI_JS))`; + + +(*val num_of_FPConvOp : FPConvOp -> integer*) + +val _ = Define ` + ((num_of_FPConvOp:FPConvOp -> int) arg_= + ((case arg_ of + FPConvOp_CVT_FtoI => (( 0 : int):ii) + | FPConvOp_CVT_ItoF => (( 1 : int):ii) + | FPConvOp_MOV_FtoI => (( 2 : int):ii) + | FPConvOp_MOV_ItoF => (( 3 : int):ii) + | FPConvOp_CVT_FtoI_JS => (( 4 : int):ii) + )))`; + + +(*val undefined_FPConvOp : unit -> M FPConvOp*) + +val _ = Define ` + ((undefined_FPConvOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPConvOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [FPConvOp_CVT_FtoI;FPConvOp_CVT_ItoF;FPConvOp_MOV_FtoI;FPConvOp_MOV_ItoF;FPConvOp_CVT_FtoI_JS]))`; + + +(*val Exception_of_num : integer -> Exception*) + +val _ = Define ` + ((Exception_of_num:int -> Exception) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Exception_Uncategorized + else if (((p0_ = (( 1 : int):ii)))) then Exception_WFxTrap + else if (((p0_ = (( 2 : int):ii)))) then Exception_CP15RTTrap + else if (((p0_ = (( 3 : int):ii)))) then Exception_CP15RRTTrap + else if (((p0_ = (( 4 : int):ii)))) then Exception_CP14RTTrap + else if (((p0_ = (( 5 : int):ii)))) then Exception_CP14DTTrap + else if (((p0_ = (( 6 : int):ii)))) then Exception_AdvSIMDFPAccessTrap + else if (((p0_ = (( 7 : int):ii)))) then Exception_FPIDTrap + else if (((p0_ = (( 8 : int):ii)))) then Exception_PACTrap + else if (((p0_ = (( 9 : int):ii)))) then Exception_CP14RRTTrap + else if (((p0_ = (( 10 : int):ii)))) then Exception_IllegalState + else if (((p0_ = (( 11 : int):ii)))) then Exception_SupervisorCall + else if (((p0_ = (( 12 : int):ii)))) then Exception_HypervisorCall + else if (((p0_ = (( 13 : int):ii)))) then Exception_MonitorCall + else if (((p0_ = (( 14 : int):ii)))) then Exception_SystemRegisterTrap + else if (((p0_ = (( 15 : int):ii)))) then Exception_ERetTrap + else if (((p0_ = (( 16 : int):ii)))) then Exception_InstructionAbort + else if (((p0_ = (( 17 : int):ii)))) then Exception_PCAlignment + else if (((p0_ = (( 18 : int):ii)))) then Exception_DataAbort + else if (((p0_ = (( 19 : int):ii)))) then Exception_SPAlignment + else if (((p0_ = (( 20 : int):ii)))) then Exception_FPTrappedException + else if (((p0_ = (( 21 : int):ii)))) then Exception_SError + else if (((p0_ = (( 22 : int):ii)))) then Exception_Breakpoint + else if (((p0_ = (( 23 : int):ii)))) then Exception_SoftwareStep + else if (((p0_ = (( 24 : int):ii)))) then Exception_Watchpoint + else if (((p0_ = (( 25 : int):ii)))) then Exception_SoftwareBreakpoint + else if (((p0_ = (( 26 : int):ii)))) then Exception_VectorCatch + else if (((p0_ = (( 27 : int):ii)))) then Exception_IRQ + else Exception_FIQ))`; + + +(*val num_of_Exception : Exception -> integer*) + +val _ = Define ` + ((num_of_Exception:Exception -> int) arg_= + ((case arg_ of + Exception_Uncategorized => (( 0 : int):ii) + | Exception_WFxTrap => (( 1 : int):ii) + | Exception_CP15RTTrap => (( 2 : int):ii) + | Exception_CP15RRTTrap => (( 3 : int):ii) + | Exception_CP14RTTrap => (( 4 : int):ii) + | Exception_CP14DTTrap => (( 5 : int):ii) + | Exception_AdvSIMDFPAccessTrap => (( 6 : int):ii) + | Exception_FPIDTrap => (( 7 : int):ii) + | Exception_PACTrap => (( 8 : int):ii) + | Exception_CP14RRTTrap => (( 9 : int):ii) + | Exception_IllegalState => (( 10 : int):ii) + | Exception_SupervisorCall => (( 11 : int):ii) + | Exception_HypervisorCall => (( 12 : int):ii) + | Exception_MonitorCall => (( 13 : int):ii) + | Exception_SystemRegisterTrap => (( 14 : int):ii) + | Exception_ERetTrap => (( 15 : int):ii) + | Exception_InstructionAbort => (( 16 : int):ii) + | Exception_PCAlignment => (( 17 : int):ii) + | Exception_DataAbort => (( 18 : int):ii) + | Exception_SPAlignment => (( 19 : int):ii) + | Exception_FPTrappedException => (( 20 : int):ii) + | Exception_SError => (( 21 : int):ii) + | Exception_Breakpoint => (( 22 : int):ii) + | Exception_SoftwareStep => (( 23 : int):ii) + | Exception_Watchpoint => (( 24 : int):ii) + | Exception_SoftwareBreakpoint => (( 25 : int):ii) + | Exception_VectorCatch => (( 26 : int):ii) + | Exception_IRQ => (( 27 : int):ii) + | Exception_FIQ => (( 28 : int):ii) + )))`; + + +(*val undefined_Exception : unit -> M Exception*) + +val _ = Define ` + ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [Exception_Uncategorized;Exception_WFxTrap;Exception_CP15RTTrap;Exception_CP15RRTTrap;Exception_CP14RTTrap;Exception_CP14DTTrap;Exception_AdvSIMDFPAccessTrap;Exception_FPIDTrap;Exception_PACTrap;Exception_CP14RRTTrap;Exception_IllegalState;Exception_SupervisorCall;Exception_HypervisorCall;Exception_MonitorCall;Exception_SystemRegisterTrap;Exception_ERetTrap;Exception_InstructionAbort;Exception_PCAlignment;Exception_DataAbort;Exception_SPAlignment;Exception_FPTrappedException;Exception_SError;Exception_Breakpoint;Exception_SoftwareStep;Exception_Watchpoint;Exception_SoftwareBreakpoint;Exception_VectorCatch;Exception_IRQ;Exception_FIQ]))`; + + +(*val ArchVersion_of_num : integer -> ArchVersion*) + +val _ = Define ` + ((ArchVersion_of_num:int -> ArchVersion) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then ARMv8p0 + else if (((p0_ = (( 1 : int):ii)))) then ARMv8p1 + else if (((p0_ = (( 2 : int):ii)))) then ARMv8p2 + else ARMv8p3))`; + + +(*val num_of_ArchVersion : ArchVersion -> integer*) + +val _ = Define ` + ((num_of_ArchVersion:ArchVersion -> int) arg_= + ((case arg_ of + ARMv8p0 => (( 0 : int):ii) + | ARMv8p1 => (( 1 : int):ii) + | ARMv8p2 => (( 2 : int):ii) + | ARMv8p3 => (( 3 : int):ii) + )))`; + + +(*val undefined_ArchVersion : unit -> M ArchVersion*) + +val _ = Define ` + ((undefined_ArchVersion:unit ->(regstate)sail2_state_monad$sequential_state ->(((ArchVersion),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [ARMv8p0;ARMv8p1;ARMv8p2;ARMv8p3]))`; + + +(*val Unpredictable_of_num : integer -> Unpredictable*) + +val _ = Define ` + ((Unpredictable_of_num:int -> Unpredictable) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Unpredictable_WBOVERLAPLD + else if (((p0_ = (( 1 : int):ii)))) then Unpredictable_WBOVERLAPST + else if (((p0_ = (( 2 : int):ii)))) then Unpredictable_LDPOVERLAP + else if (((p0_ = (( 3 : int):ii)))) then Unpredictable_BASEOVERLAP + else if (((p0_ = (( 4 : int):ii)))) then Unpredictable_DATAOVERLAP + else if (((p0_ = (( 5 : int):ii)))) then Unpredictable_DEVPAGE2 + else if (((p0_ = (( 6 : int):ii)))) then Unpredictable_INSTRDEVICE + else if (((p0_ = (( 7 : int):ii)))) then Unpredictable_RESCPACR + else if (((p0_ = (( 8 : int):ii)))) then Unpredictable_RESMAIR + else if (((p0_ = (( 9 : int):ii)))) then Unpredictable_RESTEXCB + else if (((p0_ = (( 10 : int):ii)))) then Unpredictable_RESPRRR + else if (((p0_ = (( 11 : int):ii)))) then Unpredictable_RESDACR + else if (((p0_ = (( 12 : int):ii)))) then Unpredictable_RESVTCRS + else if (((p0_ = (( 13 : int):ii)))) then Unpredictable_RESTnSZ + else if (((p0_ = (( 14 : int):ii)))) then Unpredictable_OORTnSZ + else if (((p0_ = (( 15 : int):ii)))) then Unpredictable_LARGEIPA + else if (((p0_ = (( 16 : int):ii)))) then Unpredictable_ESRCONDPASS + else if (((p0_ = (( 17 : int):ii)))) then Unpredictable_ILZEROIT + else if (((p0_ = (( 18 : int):ii)))) then Unpredictable_ILZEROT + else if (((p0_ = (( 19 : int):ii)))) then Unpredictable_BPVECTORCATCHPRI + else if (((p0_ = (( 20 : int):ii)))) then Unpredictable_VCMATCHHALF + else if (((p0_ = (( 21 : int):ii)))) then Unpredictable_VCMATCHDAPA + else if (((p0_ = (( 22 : int):ii)))) then Unpredictable_WPMASKANDBAS + else if (((p0_ = (( 23 : int):ii)))) then Unpredictable_WPBASCONTIGUOUS + else if (((p0_ = (( 24 : int):ii)))) then Unpredictable_RESWPMASK + else if (((p0_ = (( 25 : int):ii)))) then Unpredictable_WPMASKEDBITS + else if (((p0_ = (( 26 : int):ii)))) then Unpredictable_RESBPWPCTRL + else if (((p0_ = (( 27 : int):ii)))) then Unpredictable_BPNOTIMPL + else if (((p0_ = (( 28 : int):ii)))) then Unpredictable_RESBPTYPE + else if (((p0_ = (( 29 : int):ii)))) then Unpredictable_BPNOTCTXCMP + else if (((p0_ = (( 30 : int):ii)))) then Unpredictable_BPMATCHHALF + else if (((p0_ = (( 31 : int):ii)))) then Unpredictable_BPMISMATCHHALF + else if (((p0_ = (( 32 : int):ii)))) then Unpredictable_RESTARTALIGNPC + else if (((p0_ = (( 33 : int):ii)))) then Unpredictable_RESTARTZEROUPPERPC + else if (((p0_ = (( 34 : int):ii)))) then Unpredictable_ZEROUPPER + else if (((p0_ = (( 35 : int):ii)))) then Unpredictable_ERETZEROUPPERPC + else if (((p0_ = (( 36 : int):ii)))) then Unpredictable_A32FORCEALIGNPC + else if (((p0_ = (( 37 : int):ii)))) then Unpredictable_SMD + else if (((p0_ = (( 38 : int):ii)))) then Unpredictable_AFUPDATE + else if (((p0_ = (( 39 : int):ii)))) then Unpredictable_IESBinDebug + else if (((p0_ = (( 40 : int):ii)))) then Unpredictable_ZEROPMSEVFR + else if (((p0_ = (( 41 : int):ii)))) then Unpredictable_NOOPTYPES + else if (((p0_ = (( 42 : int):ii)))) then Unpredictable_ZEROMINLATENCY + else if (((p0_ = (( 43 : int):ii)))) then Unpredictable_CLEARERRITEZERO + else Unpredictable_TBD))`; + + +(*val num_of_Unpredictable : Unpredictable -> integer*) + +val _ = Define ` + ((num_of_Unpredictable:Unpredictable -> int) arg_= + ((case arg_ of + Unpredictable_WBOVERLAPLD => (( 0 : int):ii) + | Unpredictable_WBOVERLAPST => (( 1 : int):ii) + | Unpredictable_LDPOVERLAP => (( 2 : int):ii) + | Unpredictable_BASEOVERLAP => (( 3 : int):ii) + | Unpredictable_DATAOVERLAP => (( 4 : int):ii) + | Unpredictable_DEVPAGE2 => (( 5 : int):ii) + | Unpredictable_INSTRDEVICE => (( 6 : int):ii) + | Unpredictable_RESCPACR => (( 7 : int):ii) + | Unpredictable_RESMAIR => (( 8 : int):ii) + | Unpredictable_RESTEXCB => (( 9 : int):ii) + | Unpredictable_RESPRRR => (( 10 : int):ii) + | Unpredictable_RESDACR => (( 11 : int):ii) + | Unpredictable_RESVTCRS => (( 12 : int):ii) + | Unpredictable_RESTnSZ => (( 13 : int):ii) + | Unpredictable_OORTnSZ => (( 14 : int):ii) + | Unpredictable_LARGEIPA => (( 15 : int):ii) + | Unpredictable_ESRCONDPASS => (( 16 : int):ii) + | Unpredictable_ILZEROIT => (( 17 : int):ii) + | Unpredictable_ILZEROT => (( 18 : int):ii) + | Unpredictable_BPVECTORCATCHPRI => (( 19 : int):ii) + | Unpredictable_VCMATCHHALF => (( 20 : int):ii) + | Unpredictable_VCMATCHDAPA => (( 21 : int):ii) + | Unpredictable_WPMASKANDBAS => (( 22 : int):ii) + | Unpredictable_WPBASCONTIGUOUS => (( 23 : int):ii) + | Unpredictable_RESWPMASK => (( 24 : int):ii) + | Unpredictable_WPMASKEDBITS => (( 25 : int):ii) + | Unpredictable_RESBPWPCTRL => (( 26 : int):ii) + | Unpredictable_BPNOTIMPL => (( 27 : int):ii) + | Unpredictable_RESBPTYPE => (( 28 : int):ii) + | Unpredictable_BPNOTCTXCMP => (( 29 : int):ii) + | Unpredictable_BPMATCHHALF => (( 30 : int):ii) + | Unpredictable_BPMISMATCHHALF => (( 31 : int):ii) + | Unpredictable_RESTARTALIGNPC => (( 32 : int):ii) + | Unpredictable_RESTARTZEROUPPERPC => (( 33 : int):ii) + | Unpredictable_ZEROUPPER => (( 34 : int):ii) + | Unpredictable_ERETZEROUPPERPC => (( 35 : int):ii) + | Unpredictable_A32FORCEALIGNPC => (( 36 : int):ii) + | Unpredictable_SMD => (( 37 : int):ii) + | Unpredictable_AFUPDATE => (( 38 : int):ii) + | Unpredictable_IESBinDebug => (( 39 : int):ii) + | Unpredictable_ZEROPMSEVFR => (( 40 : int):ii) + | Unpredictable_NOOPTYPES => (( 41 : int):ii) + | Unpredictable_ZEROMINLATENCY => (( 42 : int):ii) + | Unpredictable_CLEARERRITEZERO => (( 43 : int):ii) + | Unpredictable_TBD => (( 44 : int):ii) + )))`; + + +(*val undefined_Unpredictable : unit -> M Unpredictable*) + +val _ = Define ` + ((undefined_Unpredictable:unit ->(regstate)sail2_state_monad$sequential_state ->(((Unpredictable),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [Unpredictable_WBOVERLAPLD;Unpredictable_WBOVERLAPST;Unpredictable_LDPOVERLAP;Unpredictable_BASEOVERLAP;Unpredictable_DATAOVERLAP;Unpredictable_DEVPAGE2;Unpredictable_INSTRDEVICE;Unpredictable_RESCPACR;Unpredictable_RESMAIR;Unpredictable_RESTEXCB;Unpredictable_RESPRRR;Unpredictable_RESDACR;Unpredictable_RESVTCRS;Unpredictable_RESTnSZ;Unpredictable_OORTnSZ;Unpredictable_LARGEIPA;Unpredictable_ESRCONDPASS;Unpredictable_ILZEROIT;Unpredictable_ILZEROT;Unpredictable_BPVECTORCATCHPRI;Unpredictable_VCMATCHHALF;Unpredictable_VCMATCHDAPA;Unpredictable_WPMASKANDBAS;Unpredictable_WPBASCONTIGUOUS;Unpredictable_RESWPMASK;Unpredictable_WPMASKEDBITS;Unpredictable_RESBPWPCTRL;Unpredictable_BPNOTIMPL;Unpredictable_RESBPTYPE;Unpredictable_BPNOTCTXCMP;Unpredictable_BPMATCHHALF;Unpredictable_BPMISMATCHHALF;Unpredictable_RESTARTALIGNPC;Unpredictable_RESTARTZEROUPPERPC;Unpredictable_ZEROUPPER;Unpredictable_ERETZEROUPPERPC;Unpredictable_A32FORCEALIGNPC;Unpredictable_SMD;Unpredictable_AFUPDATE;Unpredictable_IESBinDebug;Unpredictable_ZEROPMSEVFR;Unpredictable_NOOPTYPES;Unpredictable_ZEROMINLATENCY;Unpredictable_CLEARERRITEZERO;Unpredictable_TBD]))`; + + +(*val Constraint_of_num : integer -> Constraint*) + +val _ = Define ` + ((Constraint_of_num:int -> Constraint) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Constraint_NONE + else if (((p0_ = (( 1 : int):ii)))) then Constraint_UNKNOWN + else if (((p0_ = (( 2 : int):ii)))) then Constraint_UNDEF + else if (((p0_ = (( 3 : int):ii)))) then Constraint_UNDEFEL0 + else if (((p0_ = (( 4 : int):ii)))) then Constraint_NOP + else if (((p0_ = (( 5 : int):ii)))) then Constraint_TRUE + else if (((p0_ = (( 6 : int):ii)))) then Constraint_FALSE + else if (((p0_ = (( 7 : int):ii)))) then Constraint_DISABLED + else if (((p0_ = (( 8 : int):ii)))) then Constraint_UNCOND + else if (((p0_ = (( 9 : int):ii)))) then Constraint_COND + else if (((p0_ = (( 10 : int):ii)))) then Constraint_ADDITIONAL_DECODE + else if (((p0_ = (( 11 : int):ii)))) then Constraint_WBSUPPRESS + else if (((p0_ = (( 12 : int):ii)))) then Constraint_FAULT + else if (((p0_ = (( 13 : int):ii)))) then Constraint_FORCE + else Constraint_FORCENOSLCHECK))`; + + +(*val num_of_Constraint : Constraint -> integer*) + +val _ = Define ` + ((num_of_Constraint:Constraint -> int) arg_= + ((case arg_ of + Constraint_NONE => (( 0 : int):ii) + | Constraint_UNKNOWN => (( 1 : int):ii) + | Constraint_UNDEF => (( 2 : int):ii) + | Constraint_UNDEFEL0 => (( 3 : int):ii) + | Constraint_NOP => (( 4 : int):ii) + | Constraint_TRUE => (( 5 : int):ii) + | Constraint_FALSE => (( 6 : int):ii) + | Constraint_DISABLED => (( 7 : int):ii) + | Constraint_UNCOND => (( 8 : int):ii) + | Constraint_COND => (( 9 : int):ii) + | Constraint_ADDITIONAL_DECODE => (( 10 : int):ii) + | Constraint_WBSUPPRESS => (( 11 : int):ii) + | Constraint_FAULT => (( 12 : int):ii) + | Constraint_FORCE => (( 13 : int):ii) + | Constraint_FORCENOSLCHECK => (( 14 : int):ii) + )))`; + + +(*val undefined_Constraint : unit -> M Constraint*) + +val _ = Define ` + ((undefined_Constraint:unit ->(regstate)sail2_state_monad$sequential_state ->(((Constraint),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [Constraint_NONE;Constraint_UNKNOWN;Constraint_UNDEF;Constraint_UNDEFEL0;Constraint_NOP;Constraint_TRUE;Constraint_FALSE;Constraint_DISABLED;Constraint_UNCOND;Constraint_COND;Constraint_ADDITIONAL_DECODE;Constraint_WBSUPPRESS;Constraint_FAULT;Constraint_FORCE;Constraint_FORCENOSLCHECK]))`; + + +(*val InstrSet_of_num : integer -> InstrSet*) + +val _ = Define ` + ((InstrSet_of_num:int -> InstrSet) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then InstrSet_A64 + else if (((p0_ = (( 1 : int):ii)))) then InstrSet_A32 + else InstrSet_T32))`; + + +(*val num_of_InstrSet : InstrSet -> integer*) + +val _ = Define ` + ((num_of_InstrSet:InstrSet -> int) arg_= + ((case arg_ of InstrSet_A64 => (( 0 : int):ii) | InstrSet_A32 => (( 1 : int):ii) | InstrSet_T32 => (( 2 : int):ii) )))`; + + +(*val undefined_InstrSet : unit -> M InstrSet*) + +val _ = Define ` + ((undefined_InstrSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [InstrSet_A64;InstrSet_A32;InstrSet_T32]))`; + + +(*val undefined_ProcState : unit -> M ProcState*) + +val _ = Define ` + ((undefined_ProcState:unit ->(regstate)sail2_state_monad$sequential_state ->(((ProcState),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__0 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__2 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__3 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__4 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__5 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__6 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__7 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__8 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__9 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__10 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__11 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__12 : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__13 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__14 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__15 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__16 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (w__17 : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__18 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__19 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__20 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 5 : int):ii) : ( 5 words$word) M) (\ (w__21 : 5 bits) . + sail2_state_monad$returnS (<| ProcState_N := w__0; + ProcState_Z := w__1; + ProcState_C := w__2; + ProcState_V := w__3; + ProcState_D := w__4; + ProcState_A := w__5; + ProcState_I := w__6; + ProcState_F := w__7; + ProcState_PAN := w__8; + ProcState_UAO := w__9; + ProcState_SS := w__10; + ProcState_IL := w__11; + ProcState_EL := w__12; + ProcState_nRW := w__13; + ProcState_SP := w__14; + ProcState_Q := w__15; + ProcState_GE := w__16; + ProcState_IT := w__17; + ProcState_J := w__18; + ProcState_T := w__19; + ProcState_E := w__20; + ProcState_M := w__21 |>)))))))))))))))))))))))))`; + + +(*val BranchType_of_num : integer -> BranchType*) + +val _ = Define ` + ((BranchType_of_num:int -> BranchType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then BranchType_CALL + else if (((p0_ = (( 1 : int):ii)))) then BranchType_ERET + else if (((p0_ = (( 2 : int):ii)))) then BranchType_DBGEXIT + else if (((p0_ = (( 3 : int):ii)))) then BranchType_RET + else if (((p0_ = (( 4 : int):ii)))) then BranchType_JMP + else if (((p0_ = (( 5 : int):ii)))) then BranchType_EXCEPTION + else BranchType_UNKNOWN))`; + + +(*val num_of_BranchType : BranchType -> integer*) + +val _ = Define ` + ((num_of_BranchType:BranchType -> int) arg_= + ((case arg_ of + BranchType_CALL => (( 0 : int):ii) + | BranchType_ERET => (( 1 : int):ii) + | BranchType_DBGEXIT => (( 2 : int):ii) + | BranchType_RET => (( 3 : int):ii) + | BranchType_JMP => (( 4 : int):ii) + | BranchType_EXCEPTION => (( 5 : int):ii) + | BranchType_UNKNOWN => (( 6 : int):ii) + )))`; + + +(*val undefined_BranchType : unit -> M BranchType*) + +val _ = Define ` + ((undefined_BranchType:unit ->(regstate)sail2_state_monad$sequential_state ->(((BranchType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [BranchType_CALL;BranchType_ERET;BranchType_DBGEXIT;BranchType_RET;BranchType_JMP;BranchType_EXCEPTION;BranchType_UNKNOWN]))`; + + +(*val undefined_ExceptionRecord : unit -> M ExceptionRecord*) + +val _ = Define ` + ((undefined_ExceptionRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_Exception () ) (\ (w__0 : Exception) . sail2_state_monad$bindS + (undefined_bitvector (( 25 : int):ii) : ( 25 words$word) M) (\ (w__1 : 25 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (w__4 : 52 bits) . + sail2_state_monad$returnS (<| ExceptionRecord_typ := w__0; + ExceptionRecord_syndrome := w__1; + ExceptionRecord_vaddress := w__2; + ExceptionRecord_ipavalid := w__3; + ExceptionRecord_ipaddress := w__4 |>))))))))`; + + +(*val Fault_of_num : integer -> Fault*) + +val _ = Define ` + ((Fault_of_num:int -> Fault) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Fault_None + else if (((p0_ = (( 1 : int):ii)))) then Fault_AccessFlag + else if (((p0_ = (( 2 : int):ii)))) then Fault_Alignment + else if (((p0_ = (( 3 : int):ii)))) then Fault_Background + else if (((p0_ = (( 4 : int):ii)))) then Fault_Domain + else if (((p0_ = (( 5 : int):ii)))) then Fault_Permission + else if (((p0_ = (( 6 : int):ii)))) then Fault_Translation + else if (((p0_ = (( 7 : int):ii)))) then Fault_AddressSize + else if (((p0_ = (( 8 : int):ii)))) then Fault_SyncExternal + else if (((p0_ = (( 9 : int):ii)))) then Fault_SyncExternalOnWalk + else if (((p0_ = (( 10 : int):ii)))) then Fault_SyncParity + else if (((p0_ = (( 11 : int):ii)))) then Fault_SyncParityOnWalk + else if (((p0_ = (( 12 : int):ii)))) then Fault_AsyncParity + else if (((p0_ = (( 13 : int):ii)))) then Fault_AsyncExternal + else if (((p0_ = (( 14 : int):ii)))) then Fault_Debug + else if (((p0_ = (( 15 : int):ii)))) then Fault_TLBConflict + else if (((p0_ = (( 16 : int):ii)))) then Fault_Lockdown + else if (((p0_ = (( 17 : int):ii)))) then Fault_Exclusive + else Fault_ICacheMaint))`; + + +(*val num_of_Fault : Fault -> integer*) + +val _ = Define ` + ((num_of_Fault:Fault -> int) arg_= + ((case arg_ of + Fault_None => (( 0 : int):ii) + | Fault_AccessFlag => (( 1 : int):ii) + | Fault_Alignment => (( 2 : int):ii) + | Fault_Background => (( 3 : int):ii) + | Fault_Domain => (( 4 : int):ii) + | Fault_Permission => (( 5 : int):ii) + | Fault_Translation => (( 6 : int):ii) + | Fault_AddressSize => (( 7 : int):ii) + | Fault_SyncExternal => (( 8 : int):ii) + | Fault_SyncExternalOnWalk => (( 9 : int):ii) + | Fault_SyncParity => (( 10 : int):ii) + | Fault_SyncParityOnWalk => (( 11 : int):ii) + | Fault_AsyncParity => (( 12 : int):ii) + | Fault_AsyncExternal => (( 13 : int):ii) + | Fault_Debug => (( 14 : int):ii) + | Fault_TLBConflict => (( 15 : int):ii) + | Fault_Lockdown => (( 16 : int):ii) + | Fault_Exclusive => (( 17 : int):ii) + | Fault_ICacheMaint => (( 18 : int):ii) + )))`; + + +(*val undefined_Fault : unit -> M Fault*) + +val _ = Define ` + ((undefined_Fault:unit ->(regstate)sail2_state_monad$sequential_state ->(((Fault),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [Fault_None;Fault_AccessFlag;Fault_Alignment;Fault_Background;Fault_Domain;Fault_Permission;Fault_Translation;Fault_AddressSize;Fault_SyncExternal;Fault_SyncExternalOnWalk;Fault_SyncParity;Fault_SyncParityOnWalk;Fault_AsyncParity;Fault_AsyncExternal;Fault_Debug;Fault_TLBConflict;Fault_Lockdown;Fault_Exclusive;Fault_ICacheMaint]))`; + + +(*val AccType_of_num : integer -> AccType*) + +val _ = Define ` + ((AccType_of_num:int -> AccType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then AccType_NORMAL + else if (((p0_ = (( 1 : int):ii)))) then AccType_VEC + else if (((p0_ = (( 2 : int):ii)))) then AccType_STREAM + else if (((p0_ = (( 3 : int):ii)))) then AccType_VECSTREAM + else if (((p0_ = (( 4 : int):ii)))) then AccType_ATOMIC + else if (((p0_ = (( 5 : int):ii)))) then AccType_ATOMICRW + else if (((p0_ = (( 6 : int):ii)))) then AccType_ORDERED + else if (((p0_ = (( 7 : int):ii)))) then AccType_ORDEREDRW + else if (((p0_ = (( 8 : int):ii)))) then AccType_LIMITEDORDERED + else if (((p0_ = (( 9 : int):ii)))) then AccType_UNPRIV + else if (((p0_ = (( 10 : int):ii)))) then AccType_IFETCH + else if (((p0_ = (( 11 : int):ii)))) then AccType_PTW + else if (((p0_ = (( 12 : int):ii)))) then AccType_DC + else if (((p0_ = (( 13 : int):ii)))) then AccType_IC + else if (((p0_ = (( 14 : int):ii)))) then AccType_DCZVA + else AccType_AT))`; + + +(*val num_of_AccType : AccType -> integer*) + +val _ = Define ` + ((num_of_AccType:AccType -> int) arg_= + ((case arg_ of + AccType_NORMAL => (( 0 : int):ii) + | AccType_VEC => (( 1 : int):ii) + | AccType_STREAM => (( 2 : int):ii) + | AccType_VECSTREAM => (( 3 : int):ii) + | AccType_ATOMIC => (( 4 : int):ii) + | AccType_ATOMICRW => (( 5 : int):ii) + | AccType_ORDERED => (( 6 : int):ii) + | AccType_ORDEREDRW => (( 7 : int):ii) + | AccType_LIMITEDORDERED => (( 8 : int):ii) + | AccType_UNPRIV => (( 9 : int):ii) + | AccType_IFETCH => (( 10 : int):ii) + | AccType_PTW => (( 11 : int):ii) + | AccType_DC => (( 12 : int):ii) + | AccType_IC => (( 13 : int):ii) + | AccType_DCZVA => (( 14 : int):ii) + | AccType_AT => (( 15 : int):ii) + )))`; + + +(*val undefined_AccType : unit -> M AccType*) + +val _ = Define ` + ((undefined_AccType:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [AccType_NORMAL;AccType_VEC;AccType_STREAM;AccType_VECSTREAM;AccType_ATOMIC;AccType_ATOMICRW;AccType_ORDERED;AccType_ORDEREDRW;AccType_LIMITEDORDERED;AccType_UNPRIV;AccType_IFETCH;AccType_PTW;AccType_DC;AccType_IC;AccType_DCZVA;AccType_AT]))`; + + +(*val undefined_FaultRecord : unit -> M FaultRecord*) + +val _ = Define ` + ((undefined_FaultRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_Fault () ) (\ (w__0 : Fault) . sail2_state_monad$bindS + (undefined_AccType () ) (\ (w__1 : AccType) . sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (w__2 : 52 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__4 : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__5 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__6 : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__7 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__8 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__9 : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__10 : 4 bits) . + sail2_state_monad$returnS (<| FaultRecord_typ := w__0; + FaultRecord_acctype := w__1; + FaultRecord_ipaddress := w__2; + FaultRecord_s2fs1walk := w__3; + FaultRecord_write := w__4; + FaultRecord_level := w__5; + FaultRecord_extflag := w__6; + FaultRecord_secondstage := w__7; + FaultRecord_domain := w__8; + FaultRecord_errortype := w__9; + FaultRecord_debugmoe := w__10 |>))))))))))))))`; + + +(*val MBReqDomain_of_num : integer -> MBReqDomain*) + +val _ = Define ` + ((MBReqDomain_of_num:int -> MBReqDomain) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MBReqDomain_Nonshareable + else if (((p0_ = (( 1 : int):ii)))) then MBReqDomain_InnerShareable + else if (((p0_ = (( 2 : int):ii)))) then MBReqDomain_OuterShareable + else MBReqDomain_FullSystem))`; + + +(*val num_of_MBReqDomain : MBReqDomain -> integer*) + +val _ = Define ` + ((num_of_MBReqDomain:MBReqDomain -> int) arg_= + ((case arg_ of + MBReqDomain_Nonshareable => (( 0 : int):ii) + | MBReqDomain_InnerShareable => (( 1 : int):ii) + | MBReqDomain_OuterShareable => (( 2 : int):ii) + | MBReqDomain_FullSystem => (( 3 : int):ii) + )))`; + + +(*val undefined_MBReqDomain : unit -> M MBReqDomain*) + +val _ = Define ` + ((undefined_MBReqDomain:unit ->(regstate)sail2_state_monad$sequential_state ->(((MBReqDomain),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [MBReqDomain_Nonshareable;MBReqDomain_InnerShareable;MBReqDomain_OuterShareable;MBReqDomain_FullSystem]))`; + + +(*val MBReqTypes_of_num : integer -> MBReqTypes*) + +val _ = Define ` + ((MBReqTypes_of_num:int -> MBReqTypes) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MBReqTypes_Reads + else if (((p0_ = (( 1 : int):ii)))) then MBReqTypes_Writes + else MBReqTypes_All))`; + + +(*val num_of_MBReqTypes : MBReqTypes -> integer*) + +val _ = Define ` + ((num_of_MBReqTypes:MBReqTypes -> int) arg_= + ((case arg_ of + MBReqTypes_Reads => (( 0 : int):ii) + | MBReqTypes_Writes => (( 1 : int):ii) + | MBReqTypes_All => (( 2 : int):ii) + )))`; + + +(*val undefined_MBReqTypes : unit -> M MBReqTypes*) + +val _ = Define ` + ((undefined_MBReqTypes:unit ->(regstate)sail2_state_monad$sequential_state ->(((MBReqTypes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [MBReqTypes_Reads;MBReqTypes_Writes;MBReqTypes_All]))`; + + +(*val MemType_of_num : integer -> MemType*) + +val _ = Define ` + ((MemType_of_num:int -> MemType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MemType_Normal + else MemType_Device))`; + + +(*val num_of_MemType : MemType -> integer*) + +val _ = Define ` + ((num_of_MemType:MemType -> int) arg_= ((case arg_ of MemType_Normal => (( 0 : int):ii) | MemType_Device => (( 1 : int):ii) )))`; + + +(*val undefined_MemType : unit -> M MemType*) + +val _ = Define ` + ((undefined_MemType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [MemType_Normal;MemType_Device]))`; + + +(*val DeviceType_of_num : integer -> DeviceType*) + +val _ = Define ` + ((DeviceType_of_num:int -> DeviceType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then DeviceType_GRE + else if (((p0_ = (( 1 : int):ii)))) then DeviceType_nGRE + else if (((p0_ = (( 2 : int):ii)))) then DeviceType_nGnRE + else DeviceType_nGnRnE))`; + + +(*val num_of_DeviceType : DeviceType -> integer*) + +val _ = Define ` + ((num_of_DeviceType:DeviceType -> int) arg_= + ((case arg_ of + DeviceType_GRE => (( 0 : int):ii) + | DeviceType_nGRE => (( 1 : int):ii) + | DeviceType_nGnRE => (( 2 : int):ii) + | DeviceType_nGnRnE => (( 3 : int):ii) + )))`; + + +(*val undefined_DeviceType : unit -> M DeviceType*) + +val _ = Define ` + ((undefined_DeviceType:unit ->(regstate)sail2_state_monad$sequential_state ->(((DeviceType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [DeviceType_GRE;DeviceType_nGRE;DeviceType_nGnRE;DeviceType_nGnRnE]))`; + + +(*val undefined_MemAttrHints : unit -> M MemAttrHints*) + +val _ = Define ` + ((undefined_MemAttrHints:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__0 : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__1 : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__2 : bool) . + sail2_state_monad$returnS (<| MemAttrHints_attrs := w__0; + MemAttrHints_hints := w__1; + MemAttrHints_transient := w__2 |>))))))`; + + +(*val undefined_MemoryAttributes : unit -> M MemoryAttributes*) + +val _ = Define ` + ((undefined_MemoryAttributes:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_MemType () ) (\ (w__0 : MemType) . sail2_state_monad$bindS + (undefined_DeviceType () ) (\ (w__1 : DeviceType) . sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (w__2 : MemAttrHints) . sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (w__3 : MemAttrHints) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__4 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__5 : bool) . + sail2_state_monad$returnS (<| MemoryAttributes_typ := w__0; + MemoryAttributes_device := w__1; + MemoryAttributes_inner := w__2; + MemoryAttributes_outer := w__3; + MemoryAttributes_shareable := w__4; + MemoryAttributes_outershareable := w__5 |>)))))))))`; + + +(*val undefined_FullAddress : unit -> M FullAddress*) + +val _ = Define ` + ((undefined_FullAddress:unit ->(regstate)sail2_state_monad$sequential_state ->(((FullAddress),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (w__0 : 52 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__1 : 1 bits) . + sail2_state_monad$returnS (<| FullAddress_physicaladdress := w__0; + FullAddress_NS := w__1 |>)))))`; + + +(*val undefined_AddressDescriptor : unit -> M AddressDescriptor*) + +val _ = Define ` + ((undefined_AddressDescriptor:unit ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_FaultRecord () ) (\ (w__0 : FaultRecord) . sail2_state_monad$bindS + (undefined_MemoryAttributes () ) (\ (w__1 : MemoryAttributes) . sail2_state_monad$bindS + (undefined_FullAddress () ) (\ (w__2 : FullAddress) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (<| AddressDescriptor_fault := w__0; + AddressDescriptor_memattrs := w__1; + AddressDescriptor_paddress := w__2; + AddressDescriptor_vaddress := w__3 |>)))))))`; + + +(*val undefined_DescriptorUpdate : unit -> M DescriptorUpdate*) + +val _ = Define ` + ((undefined_DescriptorUpdate:unit ->(regstate)sail2_state_monad$sequential_state ->(((DescriptorUpdate),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (w__2 : AddressDescriptor) . + sail2_state_monad$returnS (<| DescriptorUpdate_AF := w__0; + DescriptorUpdate_AP := w__1; + DescriptorUpdate_descaddr := w__2 |>))))))`; + + +(*val MemAtomicOp_of_num : integer -> MemAtomicOp*) + +val _ = Define ` + ((MemAtomicOp_of_num:int -> MemAtomicOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MemAtomicOp_ADD + else if (((p0_ = (( 1 : int):ii)))) then MemAtomicOp_BIC + else if (((p0_ = (( 2 : int):ii)))) then MemAtomicOp_EOR + else if (((p0_ = (( 3 : int):ii)))) then MemAtomicOp_ORR + else if (((p0_ = (( 4 : int):ii)))) then MemAtomicOp_SMAX + else if (((p0_ = (( 5 : int):ii)))) then MemAtomicOp_SMIN + else if (((p0_ = (( 6 : int):ii)))) then MemAtomicOp_UMAX + else if (((p0_ = (( 7 : int):ii)))) then MemAtomicOp_UMIN + else MemAtomicOp_SWP))`; + + +(*val num_of_MemAtomicOp : MemAtomicOp -> integer*) + +val _ = Define ` + ((num_of_MemAtomicOp:MemAtomicOp -> int) arg_= + ((case arg_ of + MemAtomicOp_ADD => (( 0 : int):ii) + | MemAtomicOp_BIC => (( 1 : int):ii) + | MemAtomicOp_EOR => (( 2 : int):ii) + | MemAtomicOp_ORR => (( 3 : int):ii) + | MemAtomicOp_SMAX => (( 4 : int):ii) + | MemAtomicOp_SMIN => (( 5 : int):ii) + | MemAtomicOp_UMAX => (( 6 : int):ii) + | MemAtomicOp_UMIN => (( 7 : int):ii) + | MemAtomicOp_SWP => (( 8 : int):ii) + )))`; + + +(*val undefined_MemAtomicOp : unit -> M MemAtomicOp*) + +val _ = Define ` + ((undefined_MemAtomicOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAtomicOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [MemAtomicOp_ADD;MemAtomicOp_BIC;MemAtomicOp_EOR;MemAtomicOp_ORR;MemAtomicOp_SMAX;MemAtomicOp_SMIN;MemAtomicOp_UMAX;MemAtomicOp_UMIN;MemAtomicOp_SWP]))`; + + +(*val FPType_of_num : integer -> FPType*) + +val _ = Define ` + ((FPType_of_num:int -> FPType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPType_Nonzero + else if (((p0_ = (( 1 : int):ii)))) then FPType_Zero + else if (((p0_ = (( 2 : int):ii)))) then FPType_Infinity + else if (((p0_ = (( 3 : int):ii)))) then FPType_QNaN + else FPType_SNaN))`; + + +(*val num_of_FPType : FPType -> integer*) + +val _ = Define ` + ((num_of_FPType:FPType -> int) arg_= + ((case arg_ of + FPType_Nonzero => (( 0 : int):ii) + | FPType_Zero => (( 1 : int):ii) + | FPType_Infinity => (( 2 : int):ii) + | FPType_QNaN => (( 3 : int):ii) + | FPType_SNaN => (( 4 : int):ii) + )))`; + + +(*val undefined_FPType : unit -> M FPType*) + +val _ = Define ` + ((undefined_FPType:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [FPType_Nonzero;FPType_Zero;FPType_Infinity;FPType_QNaN;FPType_SNaN]))`; + + +(*val FPExc_of_num : integer -> FPExc*) + +val _ = Define ` + ((FPExc_of_num:int -> FPExc) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPExc_InvalidOp + else if (((p0_ = (( 1 : int):ii)))) then FPExc_DivideByZero + else if (((p0_ = (( 2 : int):ii)))) then FPExc_Overflow + else if (((p0_ = (( 3 : int):ii)))) then FPExc_Underflow + else if (((p0_ = (( 4 : int):ii)))) then FPExc_Inexact + else FPExc_InputDenorm))`; + + +(*val num_of_FPExc : FPExc -> integer*) + +val _ = Define ` + ((num_of_FPExc:FPExc -> int) arg_= + ((case arg_ of + FPExc_InvalidOp => (( 0 : int):ii) + | FPExc_DivideByZero => (( 1 : int):ii) + | FPExc_Overflow => (( 2 : int):ii) + | FPExc_Underflow => (( 3 : int):ii) + | FPExc_Inexact => (( 4 : int):ii) + | FPExc_InputDenorm => (( 5 : int):ii) + )))`; + + +(*val undefined_FPExc : unit -> M FPExc*) + +val _ = Define ` + ((undefined_FPExc:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPExc),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [FPExc_InvalidOp;FPExc_DivideByZero;FPExc_Overflow;FPExc_Underflow;FPExc_Inexact;FPExc_InputDenorm]))`; + + +(*val FPRounding_of_num : integer -> FPRounding*) + +val _ = Define ` + ((FPRounding_of_num:int -> FPRounding) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPRounding_TIEEVEN + else if (((p0_ = (( 1 : int):ii)))) then FPRounding_POSINF + else if (((p0_ = (( 2 : int):ii)))) then FPRounding_NEGINF + else if (((p0_ = (( 3 : int):ii)))) then FPRounding_ZERO + else if (((p0_ = (( 4 : int):ii)))) then FPRounding_TIEAWAY + else FPRounding_ODD))`; + + +(*val num_of_FPRounding : FPRounding -> integer*) + +val _ = Define ` + ((num_of_FPRounding:FPRounding -> int) arg_= + ((case arg_ of + FPRounding_TIEEVEN => (( 0 : int):ii) + | FPRounding_POSINF => (( 1 : int):ii) + | FPRounding_NEGINF => (( 2 : int):ii) + | FPRounding_ZERO => (( 3 : int):ii) + | FPRounding_TIEAWAY => (( 4 : int):ii) + | FPRounding_ODD => (( 5 : int):ii) + )))`; + + +(*val undefined_FPRounding : unit -> M FPRounding*) + +val _ = Define ` + ((undefined_FPRounding:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPRounding),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [FPRounding_TIEEVEN;FPRounding_POSINF;FPRounding_NEGINF;FPRounding_ZERO;FPRounding_TIEAWAY;FPRounding_ODD]))`; + + +(*val SysRegAccess_of_num : integer -> SysRegAccess*) + +val _ = Define ` + ((SysRegAccess_of_num:int -> SysRegAccess) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then SysRegAccess_OK + else if (((p0_ = (( 1 : int):ii)))) then SysRegAccess_UNDEFINED + else if (((p0_ = (( 2 : int):ii)))) then SysRegAccess_TrapToEL1 + else if (((p0_ = (( 3 : int):ii)))) then SysRegAccess_TrapToEL2 + else SysRegAccess_TrapToEL3))`; + + +(*val num_of_SysRegAccess : SysRegAccess -> integer*) + +val _ = Define ` + ((num_of_SysRegAccess:SysRegAccess -> int) arg_= + ((case arg_ of + SysRegAccess_OK => (( 0 : int):ii) + | SysRegAccess_UNDEFINED => (( 1 : int):ii) + | SysRegAccess_TrapToEL1 => (( 2 : int):ii) + | SysRegAccess_TrapToEL2 => (( 3 : int):ii) + | SysRegAccess_TrapToEL3 => (( 4 : int):ii) + )))`; + + +(*val undefined_SysRegAccess : unit -> M SysRegAccess*) + +val _ = Define ` + ((undefined_SysRegAccess:unit ->(regstate)sail2_state_monad$sequential_state ->(((SysRegAccess),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [SysRegAccess_OK;SysRegAccess_UNDEFINED;SysRegAccess_TrapToEL1;SysRegAccess_TrapToEL2;SysRegAccess_TrapToEL3]))`; + + +(*val SRType_of_num : integer -> SRType*) + +val _ = Define ` + ((SRType_of_num:int -> SRType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then SRType_LSL + else if (((p0_ = (( 1 : int):ii)))) then SRType_LSR + else if (((p0_ = (( 2 : int):ii)))) then SRType_ASR + else if (((p0_ = (( 3 : int):ii)))) then SRType_ROR + else SRType_RRX))`; + + +(*val num_of_SRType : SRType -> integer*) + +val _ = Define ` + ((num_of_SRType:SRType -> int) arg_= + ((case arg_ of + SRType_LSL => (( 0 : int):ii) + | SRType_LSR => (( 1 : int):ii) + | SRType_ASR => (( 2 : int):ii) + | SRType_ROR => (( 3 : int):ii) + | SRType_RRX => (( 4 : int):ii) + )))`; + + +(*val undefined_SRType : unit -> M SRType*) + +val _ = Define ` + ((undefined_SRType:unit ->(regstate)sail2_state_monad$sequential_state ->(((SRType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [SRType_LSL;SRType_LSR;SRType_ASR;SRType_ROR;SRType_RRX]))`; + + +(*val ShiftType_of_num : integer -> ShiftType*) + +val _ = Define ` + ((ShiftType_of_num:int -> ShiftType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then ShiftType_LSL + else if (((p0_ = (( 1 : int):ii)))) then ShiftType_LSR + else if (((p0_ = (( 2 : int):ii)))) then ShiftType_ASR + else ShiftType_ROR))`; + + +(*val num_of_ShiftType : ShiftType -> integer*) + +val _ = Define ` + ((num_of_ShiftType:ShiftType -> int) arg_= + ((case arg_ of + ShiftType_LSL => (( 0 : int):ii) + | ShiftType_LSR => (( 1 : int):ii) + | ShiftType_ASR => (( 2 : int):ii) + | ShiftType_ROR => (( 3 : int):ii) + )))`; + + +(*val undefined_ShiftType : unit -> M ShiftType*) + +val _ = Define ` + ((undefined_ShiftType:unit ->(regstate)sail2_state_monad$sequential_state ->(((ShiftType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [ShiftType_LSL;ShiftType_LSR;ShiftType_ASR;ShiftType_ROR]))`; + + +(*val PrefetchHint_of_num : integer -> PrefetchHint*) + +val _ = Define ` + ((PrefetchHint_of_num:int -> PrefetchHint) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Prefetch_READ + else if (((p0_ = (( 1 : int):ii)))) then Prefetch_WRITE + else Prefetch_EXEC))`; + + +(*val num_of_PrefetchHint : PrefetchHint -> integer*) + +val _ = Define ` + ((num_of_PrefetchHint:PrefetchHint -> int) arg_= + ((case arg_ of + Prefetch_READ => (( 0 : int):ii) + | Prefetch_WRITE => (( 1 : int):ii) + | Prefetch_EXEC => (( 2 : int):ii) + )))`; + + +(*val undefined_PrefetchHint : unit -> M PrefetchHint*) + +val _ = Define ` + ((undefined_PrefetchHint:unit ->(regstate)sail2_state_monad$sequential_state ->(((PrefetchHint),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [Prefetch_READ;Prefetch_WRITE;Prefetch_EXEC]))`; + + +(*val InterruptID_of_num : integer -> InterruptID*) + +val _ = Define ` + ((InterruptID_of_num:int -> InterruptID) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then InterruptID_PMUIRQ + else if (((p0_ = (( 1 : int):ii)))) then InterruptID_COMMIRQ + else if (((p0_ = (( 2 : int):ii)))) then InterruptID_CTIIRQ + else if (((p0_ = (( 3 : int):ii)))) then InterruptID_COMMRX + else InterruptID_COMMTX))`; + + +(*val num_of_InterruptID : InterruptID -> integer*) + +val _ = Define ` + ((num_of_InterruptID:InterruptID -> int) arg_= + ((case arg_ of + InterruptID_PMUIRQ => (( 0 : int):ii) + | InterruptID_COMMIRQ => (( 1 : int):ii) + | InterruptID_CTIIRQ => (( 2 : int):ii) + | InterruptID_COMMRX => (( 3 : int):ii) + | InterruptID_COMMTX => (( 4 : int):ii) + )))`; + + +(*val undefined_InterruptID : unit -> M InterruptID*) + +val _ = Define ` + ((undefined_InterruptID:unit ->(regstate)sail2_state_monad$sequential_state ->(((InterruptID),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [InterruptID_PMUIRQ;InterruptID_COMMIRQ;InterruptID_CTIIRQ;InterruptID_COMMRX;InterruptID_COMMTX]))`; + + +(*val CrossTriggerOut_of_num : integer -> CrossTriggerOut*) + +val _ = Define ` + ((CrossTriggerOut_of_num:int -> CrossTriggerOut) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CrossTriggerOut_DebugRequest + else if (((p0_ = (( 1 : int):ii)))) then CrossTriggerOut_RestartRequest + else if (((p0_ = (( 2 : int):ii)))) then CrossTriggerOut_IRQ + else if (((p0_ = (( 3 : int):ii)))) then CrossTriggerOut_RSVD3 + else if (((p0_ = (( 4 : int):ii)))) then CrossTriggerOut_TraceExtIn0 + else if (((p0_ = (( 5 : int):ii)))) then CrossTriggerOut_TraceExtIn1 + else if (((p0_ = (( 6 : int):ii)))) then CrossTriggerOut_TraceExtIn2 + else CrossTriggerOut_TraceExtIn3))`; + + +(*val num_of_CrossTriggerOut : CrossTriggerOut -> integer*) + +val _ = Define ` + ((num_of_CrossTriggerOut:CrossTriggerOut -> int) arg_= + ((case arg_ of + CrossTriggerOut_DebugRequest => (( 0 : int):ii) + | CrossTriggerOut_RestartRequest => (( 1 : int):ii) + | CrossTriggerOut_IRQ => (( 2 : int):ii) + | CrossTriggerOut_RSVD3 => (( 3 : int):ii) + | CrossTriggerOut_TraceExtIn0 => (( 4 : int):ii) + | CrossTriggerOut_TraceExtIn1 => (( 5 : int):ii) + | CrossTriggerOut_TraceExtIn2 => (( 6 : int):ii) + | CrossTriggerOut_TraceExtIn3 => (( 7 : int):ii) + )))`; + + +(*val undefined_CrossTriggerOut : unit -> M CrossTriggerOut*) + +val _ = Define ` + ((undefined_CrossTriggerOut:unit ->(regstate)sail2_state_monad$sequential_state ->(((CrossTriggerOut),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [CrossTriggerOut_DebugRequest;CrossTriggerOut_RestartRequest;CrossTriggerOut_IRQ;CrossTriggerOut_RSVD3;CrossTriggerOut_TraceExtIn0;CrossTriggerOut_TraceExtIn1;CrossTriggerOut_TraceExtIn2;CrossTriggerOut_TraceExtIn3]))`; + + +(*val CrossTriggerIn_of_num : integer -> CrossTriggerIn*) + +val _ = Define ` + ((CrossTriggerIn_of_num:int -> CrossTriggerIn) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CrossTriggerIn_CrossHalt + else if (((p0_ = (( 1 : int):ii)))) then CrossTriggerIn_PMUOverflow + else if (((p0_ = (( 2 : int):ii)))) then CrossTriggerIn_RSVD2 + else if (((p0_ = (( 3 : int):ii)))) then CrossTriggerIn_RSVD3 + else if (((p0_ = (( 4 : int):ii)))) then CrossTriggerIn_TraceExtOut0 + else if (((p0_ = (( 5 : int):ii)))) then CrossTriggerIn_TraceExtOut1 + else if (((p0_ = (( 6 : int):ii)))) then CrossTriggerIn_TraceExtOut2 + else CrossTriggerIn_TraceExtOut3))`; + + +(*val num_of_CrossTriggerIn : CrossTriggerIn -> integer*) + +val _ = Define ` + ((num_of_CrossTriggerIn:CrossTriggerIn -> int) arg_= + ((case arg_ of + CrossTriggerIn_CrossHalt => (( 0 : int):ii) + | CrossTriggerIn_PMUOverflow => (( 1 : int):ii) + | CrossTriggerIn_RSVD2 => (( 2 : int):ii) + | CrossTriggerIn_RSVD3 => (( 3 : int):ii) + | CrossTriggerIn_TraceExtOut0 => (( 4 : int):ii) + | CrossTriggerIn_TraceExtOut1 => (( 5 : int):ii) + | CrossTriggerIn_TraceExtOut2 => (( 6 : int):ii) + | CrossTriggerIn_TraceExtOut3 => (( 7 : int):ii) + )))`; + + +(*val undefined_CrossTriggerIn : unit -> M CrossTriggerIn*) + +val _ = Define ` + ((undefined_CrossTriggerIn:unit ->(regstate)sail2_state_monad$sequential_state ->(((CrossTriggerIn),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [CrossTriggerIn_CrossHalt;CrossTriggerIn_PMUOverflow;CrossTriggerIn_RSVD2;CrossTriggerIn_RSVD3;CrossTriggerIn_TraceExtOut0;CrossTriggerIn_TraceExtOut1;CrossTriggerIn_TraceExtOut2;CrossTriggerIn_TraceExtOut3]))`; + + +(*val MemBarrierOp_of_num : integer -> MemBarrierOp*) + +val _ = Define ` + ((MemBarrierOp_of_num:int -> MemBarrierOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MemBarrierOp_DSB + else if (((p0_ = (( 1 : int):ii)))) then MemBarrierOp_DMB + else MemBarrierOp_ISB))`; + + +(*val num_of_MemBarrierOp : MemBarrierOp -> integer*) + +val _ = Define ` + ((num_of_MemBarrierOp:MemBarrierOp -> int) arg_= + ((case arg_ of + MemBarrierOp_DSB => (( 0 : int):ii) + | MemBarrierOp_DMB => (( 1 : int):ii) + | MemBarrierOp_ISB => (( 2 : int):ii) + )))`; + + +(*val undefined_MemBarrierOp : unit -> M MemBarrierOp*) + +val _ = Define ` + ((undefined_MemBarrierOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemBarrierOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [MemBarrierOp_DSB;MemBarrierOp_DMB;MemBarrierOp_ISB]))`; + + +(*val undefined_AccessDescriptor : unit -> M AccessDescriptor*) + +val _ = Define ` + ((undefined_AccessDescriptor:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_AccType () ) (\ (w__0 : AccType) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__4 : ii) . + sail2_state_monad$returnS (<| AccessDescriptor_acctype := w__0; + AccessDescriptor_page_table_walk := w__1; + AccessDescriptor_secondstage := w__2; + AccessDescriptor_s2fs1walk := w__3; + AccessDescriptor_level := w__4 |>))))))))`; + + +(*val undefined_Permissions : unit -> M Permissions*) + +val _ = Define ` + ((undefined_Permissions:unit ->(regstate)sail2_state_monad$sequential_state ->(((Permissions),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M) (\ (w__0 : 3 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__2 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__3 : 1 bits) . + sail2_state_monad$returnS (<| Permissions_ap := w__0; + Permissions_xn := w__1; + Permissions_xxn := w__2; + Permissions_pxn := w__3 |>)))))))`; + + +(*val undefined_TLBRecord : unit -> M TLBRecord*) + +val _ = Define ` + ((undefined_TLBRecord:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_Permissions () ) (\ (w__0 : Permissions) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__2 : 4 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__4 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__5 : ii) . sail2_state_monad$bindS + (undefined_DescriptorUpdate () ) (\ (w__6 : DescriptorUpdate) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__7 : 1 bits) . sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (w__8 : AddressDescriptor) . + sail2_state_monad$returnS (<| TLBRecord_perms := w__0; + TLBRecord_nG := w__1; + TLBRecord_domain := w__2; + TLBRecord_contiguous := w__3; + TLBRecord_level := w__4; + TLBRecord_blocksize := w__5; + TLBRecord_descupdate := w__6; + TLBRecord_CnP := w__7; + TLBRecord_addrdesc := w__8 |>))))))))))))`; + + +(*val ImmediateOp_of_num : integer -> ImmediateOp*) + +val _ = Define ` + ((ImmediateOp_of_num:int -> ImmediateOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then ImmediateOp_MOVI + else if (((p0_ = (( 1 : int):ii)))) then ImmediateOp_MVNI + else if (((p0_ = (( 2 : int):ii)))) then ImmediateOp_ORR + else ImmediateOp_BIC))`; + + +(*val num_of_ImmediateOp : ImmediateOp -> integer*) + +val _ = Define ` + ((num_of_ImmediateOp:ImmediateOp -> int) arg_= + ((case arg_ of + ImmediateOp_MOVI => (( 0 : int):ii) + | ImmediateOp_MVNI => (( 1 : int):ii) + | ImmediateOp_ORR => (( 2 : int):ii) + | ImmediateOp_BIC => (( 3 : int):ii) + )))`; + + +(*val undefined_ImmediateOp : unit -> M ImmediateOp*) + +val _ = Define ` + ((undefined_ImmediateOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((ImmediateOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [ImmediateOp_MOVI;ImmediateOp_MVNI;ImmediateOp_ORR;ImmediateOp_BIC]))`; + + +(*val MoveWideOp_of_num : integer -> MoveWideOp*) + +val _ = Define ` + ((MoveWideOp_of_num:int -> MoveWideOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MoveWideOp_N + else if (((p0_ = (( 1 : int):ii)))) then MoveWideOp_Z + else MoveWideOp_K))`; + + +(*val num_of_MoveWideOp : MoveWideOp -> integer*) + +val _ = Define ` + ((num_of_MoveWideOp:MoveWideOp -> int) arg_= + ((case arg_ of MoveWideOp_N => (( 0 : int):ii) | MoveWideOp_Z => (( 1 : int):ii) | MoveWideOp_K => (( 2 : int):ii) )))`; + + +(*val undefined_MoveWideOp : unit -> M MoveWideOp*) + +val _ = Define ` + ((undefined_MoveWideOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MoveWideOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [MoveWideOp_N;MoveWideOp_Z;MoveWideOp_K]))`; + + +(*val SystemAccessType_of_num : integer -> SystemAccessType*) + +val _ = Define ` + ((SystemAccessType_of_num:int -> SystemAccessType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then SystemAccessType_RT + else if (((p0_ = (( 1 : int):ii)))) then SystemAccessType_RRT + else SystemAccessType_DT))`; + + +(*val num_of_SystemAccessType : SystemAccessType -> integer*) + +val _ = Define ` + ((num_of_SystemAccessType:SystemAccessType -> int) arg_= + ((case arg_ of + SystemAccessType_RT => (( 0 : int):ii) + | SystemAccessType_RRT => (( 1 : int):ii) + | SystemAccessType_DT => (( 2 : int):ii) + )))`; + + +(*val undefined_SystemAccessType : unit -> M SystemAccessType*) + +val _ = Define ` + ((undefined_SystemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [SystemAccessType_RT;SystemAccessType_RRT;SystemAccessType_DT]))`; + + +(*val VBitOp_of_num : integer -> VBitOp*) + +val _ = Define ` + ((VBitOp_of_num:int -> VBitOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then VBitOp_VBIF + else if (((p0_ = (( 1 : int):ii)))) then VBitOp_VBIT + else if (((p0_ = (( 2 : int):ii)))) then VBitOp_VBSL + else VBitOp_VEOR))`; + + +(*val num_of_VBitOp : VBitOp -> integer*) + +val _ = Define ` + ((num_of_VBitOp:VBitOp -> int) arg_= + ((case arg_ of + VBitOp_VBIF => (( 0 : int):ii) + | VBitOp_VBIT => (( 1 : int):ii) + | VBitOp_VBSL => (( 2 : int):ii) + | VBitOp_VEOR => (( 3 : int):ii) + )))`; + + +(*val undefined_VBitOp : unit -> M VBitOp*) + +val _ = Define ` + ((undefined_VBitOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((VBitOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [VBitOp_VBIF;VBitOp_VBIT;VBitOp_VBSL;VBitOp_VEOR]))`; + + +(*val TimeStamp_of_num : integer -> TimeStamp*) + +val _ = Define ` + ((TimeStamp_of_num:int -> TimeStamp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then TimeStamp_None + else if (((p0_ = (( 1 : int):ii)))) then TimeStamp_Virtual + else TimeStamp_Physical))`; + + +(*val num_of_TimeStamp : TimeStamp -> integer*) + +val _ = Define ` + ((num_of_TimeStamp:TimeStamp -> int) arg_= + ((case arg_ of + TimeStamp_None => (( 0 : int):ii) + | TimeStamp_Virtual => (( 1 : int):ii) + | TimeStamp_Physical => (( 2 : int):ii) + )))`; + + +(*val undefined_TimeStamp : unit -> M TimeStamp*) + +val _ = Define ` + ((undefined_TimeStamp:unit ->(regstate)sail2_state_monad$sequential_state ->(((TimeStamp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [TimeStamp_None;TimeStamp_Virtual;TimeStamp_Physical]))`; + + +(*val PrivilegeLevel_of_num : integer -> PrivilegeLevel*) + +val _ = Define ` + ((PrivilegeLevel_of_num:int -> PrivilegeLevel) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then PL3 + else if (((p0_ = (( 1 : int):ii)))) then PL2 + else if (((p0_ = (( 2 : int):ii)))) then PL1 + else PL0))`; + + +(*val num_of_PrivilegeLevel : PrivilegeLevel -> integer*) + +val _ = Define ` + ((num_of_PrivilegeLevel:PrivilegeLevel -> int) arg_= + ((case arg_ of PL3 => (( 0 : int):ii) | PL2 => (( 1 : int):ii) | PL1 => (( 2 : int):ii) | PL0 => (( 3 : int):ii) )))`; + + +(*val undefined_PrivilegeLevel : unit -> M PrivilegeLevel*) + +val _ = Define ` + ((undefined_PrivilegeLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((PrivilegeLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [PL3;PL2;PL1;PL0]))`; + + +(*val undefined_AArch32_SErrorSyndrome : unit -> M AArch32_SErrorSyndrome*) + +val _ = Define ` + ((undefined_AArch32_SErrorSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->(((AArch32_SErrorSyndrome),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__0 : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__1 : 1 bits) . + sail2_state_monad$returnS (<| AArch32_SErrorSyndrome_AET := w__0; + AArch32_SErrorSyndrome_ExT := w__1 |>)))))`; + + +(*val SystemOp_of_num : integer -> SystemOp*) + +val _ = Define ` + ((SystemOp_of_num:int -> SystemOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Sys_AT + else if (((p0_ = (( 1 : int):ii)))) then Sys_DC + else if (((p0_ = (( 2 : int):ii)))) then Sys_IC + else if (((p0_ = (( 3 : int):ii)))) then Sys_TLBI + else Sys_SYS))`; + + +(*val num_of_SystemOp : SystemOp -> integer*) + +val _ = Define ` + ((num_of_SystemOp:SystemOp -> int) arg_= + ((case arg_ of + Sys_AT => (( 0 : int):ii) + | Sys_DC => (( 1 : int):ii) + | Sys_IC => (( 2 : int):ii) + | Sys_TLBI => (( 3 : int):ii) + | Sys_SYS => (( 4 : int):ii) + )))`; + + +(*val undefined_SystemOp : unit -> M SystemOp*) + +val _ = Define ` + ((undefined_SystemOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [Sys_AT;Sys_DC;Sys_IC;Sys_TLBI;Sys_SYS]))`; + + +(*val undefined_PCSample : unit -> M PCSample*) + +val _ = Define ` + ((undefined_PCSample:unit ->(regstate)sail2_state_monad$sequential_state ->(((PCSample),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__2 : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__3 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__4 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__5 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__6 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (w__7 : 16 bits) . + sail2_state_monad$returnS (<| PCSample_valid_name := w__0; + PCSample_pc := w__1; + PCSample_el := w__2; + PCSample_rw := w__3; + PCSample_ns := w__4; + PCSample_contextidr := w__5; + PCSample_contextidr_el2 := w__6; + PCSample_vmid := w__7 |>)))))))))))`; + + +(*val ReduceOp_of_num : integer -> ReduceOp*) + +val _ = Define ` + ((ReduceOp_of_num:int -> ReduceOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then ReduceOp_FMINNUM + else if (((p0_ = (( 1 : int):ii)))) then ReduceOp_FMAXNUM + else if (((p0_ = (( 2 : int):ii)))) then ReduceOp_FMIN + else if (((p0_ = (( 3 : int):ii)))) then ReduceOp_FMAX + else if (((p0_ = (( 4 : int):ii)))) then ReduceOp_FADD + else ReduceOp_ADD))`; + + +(*val num_of_ReduceOp : ReduceOp -> integer*) + +val _ = Define ` + ((num_of_ReduceOp:ReduceOp -> int) arg_= + ((case arg_ of + ReduceOp_FMINNUM => (( 0 : int):ii) + | ReduceOp_FMAXNUM => (( 1 : int):ii) + | ReduceOp_FMIN => (( 2 : int):ii) + | ReduceOp_FMAX => (( 3 : int):ii) + | ReduceOp_FADD => (( 4 : int):ii) + | ReduceOp_ADD => (( 5 : int):ii) + )))`; + + +(*val undefined_ReduceOp : unit -> M ReduceOp*) + +val _ = Define ` + ((undefined_ReduceOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((ReduceOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [ReduceOp_FMINNUM;ReduceOp_FMAXNUM;ReduceOp_FMIN;ReduceOp_FMAX;ReduceOp_FADD;ReduceOp_ADD]))`; + + +(*val LogicalOp_of_num : integer -> LogicalOp*) + +val _ = Define ` + ((LogicalOp_of_num:int -> LogicalOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then LogicalOp_AND + else if (((p0_ = (( 1 : int):ii)))) then LogicalOp_EOR + else LogicalOp_ORR))`; + + +(*val num_of_LogicalOp : LogicalOp -> integer*) + +val _ = Define ` + ((num_of_LogicalOp:LogicalOp -> int) arg_= + ((case arg_ of LogicalOp_AND => (( 0 : int):ii) | LogicalOp_EOR => (( 1 : int):ii) | LogicalOp_ORR => (( 2 : int):ii) )))`; + + +(*val undefined_LogicalOp : unit -> M LogicalOp*) + +val _ = Define ` + ((undefined_LogicalOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((LogicalOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [LogicalOp_AND;LogicalOp_EOR;LogicalOp_ORR]))`; + + +(*val ExtendType_of_num : integer -> ExtendType*) + +val _ = Define ` + ((ExtendType_of_num:int -> ExtendType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then ExtendType_SXTB + else if (((p0_ = (( 1 : int):ii)))) then ExtendType_SXTH + else if (((p0_ = (( 2 : int):ii)))) then ExtendType_SXTW + else if (((p0_ = (( 3 : int):ii)))) then ExtendType_SXTX + else if (((p0_ = (( 4 : int):ii)))) then ExtendType_UXTB + else if (((p0_ = (( 5 : int):ii)))) then ExtendType_UXTH + else if (((p0_ = (( 6 : int):ii)))) then ExtendType_UXTW + else ExtendType_UXTX))`; + + +(*val num_of_ExtendType : ExtendType -> integer*) + +val _ = Define ` + ((num_of_ExtendType:ExtendType -> int) arg_= + ((case arg_ of + ExtendType_SXTB => (( 0 : int):ii) + | ExtendType_SXTH => (( 1 : int):ii) + | ExtendType_SXTW => (( 2 : int):ii) + | ExtendType_SXTX => (( 3 : int):ii) + | ExtendType_UXTB => (( 4 : int):ii) + | ExtendType_UXTH => (( 5 : int):ii) + | ExtendType_UXTW => (( 6 : int):ii) + | ExtendType_UXTX => (( 7 : int):ii) + )))`; + + +(*val undefined_ExtendType : unit -> M ExtendType*) + +val _ = Define ` + ((undefined_ExtendType:unit ->(regstate)sail2_state_monad$sequential_state ->(((ExtendType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [ExtendType_SXTB;ExtendType_SXTH;ExtendType_SXTW;ExtendType_SXTX;ExtendType_UXTB;ExtendType_UXTH;ExtendType_UXTW;ExtendType_UXTX]))`; + + +(*val SystemHintOp_of_num : integer -> SystemHintOp*) + +val _ = Define ` + ((SystemHintOp_of_num:int -> SystemHintOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then SystemHintOp_NOP + else if (((p0_ = (( 1 : int):ii)))) then SystemHintOp_YIELD + else if (((p0_ = (( 2 : int):ii)))) then SystemHintOp_WFE + else if (((p0_ = (( 3 : int):ii)))) then SystemHintOp_WFI + else if (((p0_ = (( 4 : int):ii)))) then SystemHintOp_SEV + else if (((p0_ = (( 5 : int):ii)))) then SystemHintOp_SEVL + else if (((p0_ = (( 6 : int):ii)))) then SystemHintOp_ESB + else SystemHintOp_PSB))`; + + +(*val num_of_SystemHintOp : SystemHintOp -> integer*) + +val _ = Define ` + ((num_of_SystemHintOp:SystemHintOp -> int) arg_= + ((case arg_ of + SystemHintOp_NOP => (( 0 : int):ii) + | SystemHintOp_YIELD => (( 1 : int):ii) + | SystemHintOp_WFE => (( 2 : int):ii) + | SystemHintOp_WFI => (( 3 : int):ii) + | SystemHintOp_SEV => (( 4 : int):ii) + | SystemHintOp_SEVL => (( 5 : int):ii) + | SystemHintOp_ESB => (( 6 : int):ii) + | SystemHintOp_PSB => (( 7 : int):ii) + )))`; + + +(*val undefined_SystemHintOp : unit -> M SystemHintOp*) + +val _ = Define ` + ((undefined_SystemHintOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((SystemHintOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [SystemHintOp_NOP;SystemHintOp_YIELD;SystemHintOp_WFE;SystemHintOp_WFI;SystemHintOp_SEV;SystemHintOp_SEVL;SystemHintOp_ESB;SystemHintOp_PSB]))`; + + +(*val MemOp_of_num : integer -> MemOp*) + +val _ = Define ` + ((MemOp_of_num:int -> MemOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then MemOp_LOAD + else if (((p0_ = (( 1 : int):ii)))) then MemOp_STORE + else MemOp_PREFETCH))`; + + +(*val num_of_MemOp : MemOp -> integer*) + +val _ = Define ` + ((num_of_MemOp:MemOp -> int) arg_= + ((case arg_ of MemOp_LOAD => (( 0 : int):ii) | MemOp_STORE => (( 1 : int):ii) | MemOp_PREFETCH => (( 2 : int):ii) )))`; + + +(*val undefined_MemOp : unit -> M MemOp*) + +val _ = Define ` + ((undefined_MemOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [MemOp_LOAD;MemOp_STORE;MemOp_PREFETCH]))`; + + +(*val OpType_of_num : integer -> OpType*) + +val _ = Define ` + ((OpType_of_num:int -> OpType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then OpType_Load + else if (((p0_ = (( 1 : int):ii)))) then OpType_Store + else if (((p0_ = (( 2 : int):ii)))) then OpType_LoadAtomic + else if (((p0_ = (( 3 : int):ii)))) then OpType_Branch + else OpType_Other))`; + + +(*val num_of_OpType : OpType -> integer*) + +val _ = Define ` + ((num_of_OpType:OpType -> int) arg_= + ((case arg_ of + OpType_Load => (( 0 : int):ii) + | OpType_Store => (( 1 : int):ii) + | OpType_LoadAtomic => (( 2 : int):ii) + | OpType_Branch => (( 3 : int):ii) + | OpType_Other => (( 4 : int):ii) + )))`; + + +(*val undefined_OpType : unit -> M OpType*) + +val _ = Define ` + ((undefined_OpType:unit ->(regstate)sail2_state_monad$sequential_state ->(((OpType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [OpType_Load;OpType_Store;OpType_LoadAtomic;OpType_Branch;OpType_Other]))`; + + +(*val FPUnaryOp_of_num : integer -> FPUnaryOp*) + +val _ = Define ` + ((FPUnaryOp_of_num:int -> FPUnaryOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPUnaryOp_ABS + else if (((p0_ = (( 1 : int):ii)))) then FPUnaryOp_MOV + else if (((p0_ = (( 2 : int):ii)))) then FPUnaryOp_NEG + else FPUnaryOp_SQRT))`; + + +(*val num_of_FPUnaryOp : FPUnaryOp -> integer*) + +val _ = Define ` + ((num_of_FPUnaryOp:FPUnaryOp -> int) arg_= + ((case arg_ of + FPUnaryOp_ABS => (( 0 : int):ii) + | FPUnaryOp_MOV => (( 1 : int):ii) + | FPUnaryOp_NEG => (( 2 : int):ii) + | FPUnaryOp_SQRT => (( 3 : int):ii) + )))`; + + +(*val undefined_FPUnaryOp : unit -> M FPUnaryOp*) + +val _ = Define ` + ((undefined_FPUnaryOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPUnaryOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [FPUnaryOp_ABS;FPUnaryOp_MOV;FPUnaryOp_NEG;FPUnaryOp_SQRT]))`; + + +(*val CompareOp_of_num : integer -> CompareOp*) + +val _ = Define ` + ((CompareOp_of_num:int -> CompareOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CompareOp_GT + else if (((p0_ = (( 1 : int):ii)))) then CompareOp_GE + else if (((p0_ = (( 2 : int):ii)))) then CompareOp_EQ + else if (((p0_ = (( 3 : int):ii)))) then CompareOp_LE + else CompareOp_LT))`; + + +(*val num_of_CompareOp : CompareOp -> integer*) + +val _ = Define ` + ((num_of_CompareOp:CompareOp -> int) arg_= + ((case arg_ of + CompareOp_GT => (( 0 : int):ii) + | CompareOp_GE => (( 1 : int):ii) + | CompareOp_EQ => (( 2 : int):ii) + | CompareOp_LE => (( 3 : int):ii) + | CompareOp_LT => (( 4 : int):ii) + )))`; + + +(*val undefined_CompareOp : unit -> M CompareOp*) + +val _ = Define ` + ((undefined_CompareOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CompareOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [CompareOp_GT;CompareOp_GE;CompareOp_EQ;CompareOp_LE;CompareOp_LT]))`; + + +(*val PSTATEField_of_num : integer -> PSTATEField*) + +val _ = Define ` + ((PSTATEField_of_num:int -> PSTATEField) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then PSTATEField_DAIFSet + else if (((p0_ = (( 1 : int):ii)))) then PSTATEField_DAIFClr + else if (((p0_ = (( 2 : int):ii)))) then PSTATEField_PAN + else if (((p0_ = (( 3 : int):ii)))) then PSTATEField_UAO + else PSTATEField_SP))`; + + +(*val num_of_PSTATEField : PSTATEField -> integer*) + +val _ = Define ` + ((num_of_PSTATEField:PSTATEField -> int) arg_= + ((case arg_ of + PSTATEField_DAIFSet => (( 0 : int):ii) + | PSTATEField_DAIFClr => (( 1 : int):ii) + | PSTATEField_PAN => (( 2 : int):ii) + | PSTATEField_UAO => (( 3 : int):ii) + | PSTATEField_SP => (( 4 : int):ii) + )))`; + + +(*val undefined_PSTATEField : unit -> M PSTATEField*) + +val _ = Define ` + ((undefined_PSTATEField:unit ->(regstate)sail2_state_monad$sequential_state ->(((PSTATEField),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [PSTATEField_DAIFSet;PSTATEField_DAIFClr;PSTATEField_PAN;PSTATEField_UAO;PSTATEField_SP]))`; + + +(*val FPMaxMinOp_of_num : integer -> FPMaxMinOp*) + +val _ = Define ` + ((FPMaxMinOp_of_num:int -> FPMaxMinOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then FPMaxMinOp_MAX + else if (((p0_ = (( 1 : int):ii)))) then FPMaxMinOp_MIN + else if (((p0_ = (( 2 : int):ii)))) then FPMaxMinOp_MAXNUM + else FPMaxMinOp_MINNUM))`; + + +(*val num_of_FPMaxMinOp : FPMaxMinOp -> integer*) + +val _ = Define ` + ((num_of_FPMaxMinOp:FPMaxMinOp -> int) arg_= + ((case arg_ of + FPMaxMinOp_MAX => (( 0 : int):ii) + | FPMaxMinOp_MIN => (( 1 : int):ii) + | FPMaxMinOp_MAXNUM => (( 2 : int):ii) + | FPMaxMinOp_MINNUM => (( 3 : int):ii) + )))`; + + +(*val undefined_FPMaxMinOp : unit -> M FPMaxMinOp*) + +val _ = Define ` + ((undefined_FPMaxMinOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((FPMaxMinOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [FPMaxMinOp_MAX;FPMaxMinOp_MIN;FPMaxMinOp_MAXNUM;FPMaxMinOp_MINNUM]))`; + + +(*val CountOp_of_num : integer -> CountOp*) + +val _ = Define ` + ((CountOp_of_num:int -> CountOp) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CountOp_CLZ + else if (((p0_ = (( 1 : int):ii)))) then CountOp_CLS + else CountOp_CNT))`; + + +(*val num_of_CountOp : CountOp -> integer*) + +val _ = Define ` + ((num_of_CountOp:CountOp -> int) arg_= + ((case arg_ of CountOp_CLZ => (( 0 : int):ii) | CountOp_CLS => (( 1 : int):ii) | CountOp_CNT => (( 2 : int):ii) )))`; + + +(*val undefined_CountOp : unit -> M CountOp*) + +val _ = Define ` + ((undefined_CountOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CountOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [CountOp_CLZ;CountOp_CLS;CountOp_CNT]))`; + + +(*val VFPNegMul_of_num : integer -> VFPNegMul*) + +val _ = Define ` + ((VFPNegMul_of_num:int -> VFPNegMul) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then VFPNegMul_VNMLA + else if (((p0_ = (( 1 : int):ii)))) then VFPNegMul_VNMLS + else VFPNegMul_VNMUL))`; + + +(*val num_of_VFPNegMul : VFPNegMul -> integer*) + +val _ = Define ` + ((num_of_VFPNegMul:VFPNegMul -> int) arg_= + ((case arg_ of + VFPNegMul_VNMLA => (( 0 : int):ii) + | VFPNegMul_VNMLS => (( 1 : int):ii) + | VFPNegMul_VNMUL => (( 2 : int):ii) + )))`; + + +(*val undefined_VFPNegMul : unit -> M VFPNegMul*) + +val _ = Define ` + ((undefined_VFPNegMul:unit ->(regstate)sail2_state_monad$sequential_state ->(((VFPNegMul),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [VFPNegMul_VNMLA;VFPNegMul_VNMLS;VFPNegMul_VNMUL]))`; + + +(*val VBitOps_of_num : integer -> VBitOps*) + +val _ = Define ` + ((VBitOps_of_num:int -> VBitOps) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then VBitOps_VBIF + else if (((p0_ = (( 1 : int):ii)))) then VBitOps_VBIT + else VBitOps_VBSL))`; + + +(*val num_of_VBitOps : VBitOps -> integer*) + +val _ = Define ` + ((num_of_VBitOps:VBitOps -> int) arg_= + ((case arg_ of VBitOps_VBIF => (( 0 : int):ii) | VBitOps_VBIT => (( 1 : int):ii) | VBitOps_VBSL => (( 2 : int):ii) )))`; + + +(*val undefined_VBitOps : unit -> M VBitOps*) + +val _ = Define ` + ((undefined_VBitOps:unit ->(regstate)sail2_state_monad$sequential_state ->(((VBitOps),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [VBitOps_VBIF;VBitOps_VBIT;VBitOps_VBSL]))`; + + +(*val VCGEtype_of_num : integer -> VCGEtype*) + +val _ = Define ` + ((VCGEtype_of_num:int -> VCGEtype) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then VCGEtype_signed + else if (((p0_ = (( 1 : int):ii)))) then VCGEtype_unsigned + else VCGEtype_fp))`; + + +(*val num_of_VCGEtype : VCGEtype -> integer*) + +val _ = Define ` + ((num_of_VCGEtype:VCGEtype -> int) arg_= + ((case arg_ of + VCGEtype_signed => (( 0 : int):ii) + | VCGEtype_unsigned => (( 1 : int):ii) + | VCGEtype_fp => (( 2 : int):ii) + )))`; + + +(*val undefined_VCGEtype : unit -> M VCGEtype*) + +val _ = Define ` + ((undefined_VCGEtype:unit ->(regstate)sail2_state_monad$sequential_state ->(((VCGEtype),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [VCGEtype_signed;VCGEtype_unsigned;VCGEtype_fp]))`; + + +(*val VCGTtype_of_num : integer -> VCGTtype*) + +val _ = Define ` + ((VCGTtype_of_num:int -> VCGTtype) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then VCGTtype_signed + else if (((p0_ = (( 1 : int):ii)))) then VCGTtype_unsigned + else VCGTtype_fp))`; + + +(*val num_of_VCGTtype : VCGTtype -> integer*) + +val _ = Define ` + ((num_of_VCGTtype:VCGTtype -> int) arg_= + ((case arg_ of + VCGTtype_signed => (( 0 : int):ii) + | VCGTtype_unsigned => (( 1 : int):ii) + | VCGTtype_fp => (( 2 : int):ii) + )))`; + + +(*val undefined_VCGTtype : unit -> M VCGTtype*) + +val _ = Define ` + ((undefined_VCGTtype:unit ->(regstate)sail2_state_monad$sequential_state ->(((VCGTtype),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [VCGTtype_signed;VCGTtype_unsigned;VCGTtype_fp]))`; + + +(*val __InstrEnc_of_num : integer -> __InstrEnc*) + +val _ = Define ` + ((InstrEnc_of_num:int -> InstrEnc) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then A64 + else if (((p0_ = (( 1 : int):ii)))) then A32 + else if (((p0_ = (( 2 : int):ii)))) then T16 + else T32))`; + + +(*val num_of___InstrEnc : __InstrEnc -> integer*) + +val _ = Define ` + ((num_of___InstrEnc:InstrEnc -> int) arg_= + ((case arg_ of A64 => (( 0 : int):ii) | A32 => (( 1 : int):ii) | T16 => (( 2 : int):ii) | T32 => (( 3 : int):ii) )))`; + + +(*val undefined___InstrEnc : unit -> M __InstrEnc*) + +val _ = Define ` + ((undefined___InstrEnc:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrEnc),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [A64;A32;T16;T32]))`; + + +(*val AArch64_CheckAndUpdateDescriptor_SecondStage : DescriptorUpdate -> FaultRecord -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +(*val AArch64_TranslationTableWalk_SecondStage : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> ii -> M TLBRecord*) + +(*val AArch64_SecondStageTranslate : AddressDescriptor -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> bool -> M AddressDescriptor*) + +(*val AArch64_CheckAndUpdateDescriptor : DescriptorUpdate -> FaultRecord -> bool -> mword ty64 -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +(*val __UNKNOWN_real : unit -> real*) + +val _ = Define ` + ((UNKNOWN_real:unit -> real) () = (realFromFrac(( 0 : int))(( 10 : int))))`; + + +(*val __UNKNOWN_integer : unit -> ii*) + +val _ = Define ` + ((UNKNOWN_integer:unit -> int) () = ((( 0 : int):ii)))`; + + +(*val aget_PC : unit -> M (mword ty64)*) + +val _ = Define ` + ((aget_PC:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)))`; + + +(*val UndefinedFault : unit -> M unit*) + +val _ = Define ` + ((UndefinedFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$assert_expS F "Undefined fault"))`; + + +(*val ThisInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +val _ = Define ` + ((ThisInstrAddr:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + sail2_state_monad$returnS ((slice w__0 (( 0 : int):ii) N__tv : 'N words$word)))))`; + + +(*val ThisInstr : unit -> M (mword ty32)*) + +val _ = Define ` + ((ThisInstr0:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS ThisInstr_ref : ( 32 words$word) M)))`; + + +(*val __UNKNOWN_SystemHintOp : unit -> SystemHintOp*) + +val _ = Define ` + ((UNKNOWN_SystemHintOp:unit -> SystemHintOp) () = SystemHintOp_NOP)`; + + +(*val SynchronizeContext : unit -> unit*) + +val _ = Define ` + ((SynchronizeContext:unit -> unit) () = () )`; + + +(*val SErrorPending : unit -> M bool*) + +val _ = Define ` + ((SErrorPending:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$read_regS PendingPhysicalSError_ref))`; + + +(*val ResetExternalDebugRegisters : bool -> unit*) + +val _ = Define ` + ((ResetExternalDebugRegisters:bool -> unit) cold_reset= () )`; + + +(*val ProfilingSynchronizationBarrier : unit -> unit*) + +val _ = Define ` + ((ProfilingSynchronizationBarrier:unit -> unit) () = () )`; + + +(*val ProcessorID : unit -> ii*) + +val _ = Define ` + ((ProcessorID:unit -> int) () = ((( 0 : int):ii)))`; + + +(*val __UNKNOWN_PrefetchHint : unit -> PrefetchHint*) + +val _ = Define ` + ((UNKNOWN_PrefetchHint:unit -> PrefetchHint) () = Prefetch_READ)`; + + +(*val __UNKNOWN_PSTATEField : unit -> PSTATEField*) + +val _ = Define ` + ((UNKNOWN_PSTATEField:unit -> PSTATEField) () = PSTATEField_DAIFSet)`; + + +(*val PACCellShuffle : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((PACCellShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (outdata : 64 bits) . + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 44 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) ((slice indata (( 60 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS outdata)))`; + + +(*val PACCellInvShuffle : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((PACCellInvShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (outdata : 64 bits) . + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 44 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) ((slice indata (( 60 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS outdata)))`; + + +(*val __UNKNOWN_MoveWideOp : unit -> MoveWideOp*) + +val _ = Define ` + ((UNKNOWN_MoveWideOp:unit -> MoveWideOp) () = MoveWideOp_N)`; + + +(*val __UNKNOWN_MemType : unit -> MemType*) + +val _ = Define ` + ((UNKNOWN_MemType:unit -> MemType) () = MemType_Normal)`; + + +(*val __UNKNOWN_MemOp : unit -> MemOp*) + +val _ = Define ` + ((UNKNOWN_MemOp:unit -> MemOp) () = MemOp_LOAD)`; + + +val _ = Define ` +((MemHint_RWA:(2)words$word)= ((vec_of_bits [B1;B1] : 2 words$word)))`; + + +val _ = Define ` +((MemHint_RA:(2)words$word)= ((vec_of_bits [B1;B0] : 2 words$word)))`; + + +val _ = Define ` +((MemHint_No:(2)words$word)= ((vec_of_bits [B0;B0] : 2 words$word)))`; + + +(*val __UNKNOWN_MemBarrierOp : unit -> MemBarrierOp*) + +val _ = Define ` + ((UNKNOWN_MemBarrierOp:unit -> MemBarrierOp) () = MemBarrierOp_DSB)`; + + +val _ = Define ` +((MemAttr_WT:(2)words$word)= ((vec_of_bits [B1;B0] : 2 words$word)))`; + + +val _ = Define ` +((MemAttr_WB:(2)words$word)= ((vec_of_bits [B1;B1] : 2 words$word)))`; + + +val _ = Define ` +((MemAttr_NC:(2)words$word)= ((vec_of_bits [B0;B0] : 2 words$word)))`; + + +(*val __UNKNOWN_MemAtomicOp : unit -> MemAtomicOp*) + +val _ = Define ` + ((UNKNOWN_MemAtomicOp:unit -> MemAtomicOp) () = MemAtomicOp_ADD)`; + + +(*val __UNKNOWN_MBReqTypes : unit -> MBReqTypes*) + +val _ = Define ` + ((UNKNOWN_MBReqTypes:unit -> MBReqTypes) () = MBReqTypes_Reads)`; + + +(*val __UNKNOWN_MBReqDomain : unit -> MBReqDomain*) + +val _ = Define ` + ((UNKNOWN_MBReqDomain:unit -> MBReqDomain) () = MBReqDomain_Nonshareable)`; + + +val _ = Define ` +((M32_User:(5)words$word)= ((vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))`; + + +val _ = Define ` +((M32_Undef:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((M32_System:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((M32_Svc:(5)words$word)= ((vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))`; + + +val _ = Define ` +((M32_Monitor:(5)words$word)= ((vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((M32_IRQ:(5)words$word)= ((vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((M32_Hyp:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; + + +val _ = Define ` +((M32_FIQ:(5)words$word)= ((vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))`; + + +val _ = Define ` +((M32_Abort:(5)words$word)= ((vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))`; + + +(*val __UNKNOWN_LogicalOp : unit -> LogicalOp*) + +val _ = Define ` + ((UNKNOWN_LogicalOp:unit -> LogicalOp) () = LogicalOp_AND)`; + + +(*val IsExclusiveLocal : FullAddress -> ii -> ii -> M bool*) + +val _ = Define ` + ((IsExclusiveLocal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1= (sail2_state_monad$read_regS ExclusiveLocal_ref))`; + + +(*val InterruptPending : unit -> M bool*) + +val _ = Define ` + ((InterruptPending:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$read_regS PendingInterrupt_ref))`; + + +(*val asl_Int : forall 'N . Size 'N => mword 'N -> bool -> ii*) + +val _ = Define ` + ((asl_Int:'N words$word -> bool -> int) x unsigned= (if unsigned then lem$w2ui x else integer_word$w2i x))`; + + +(*val InstructionSynchronizationBarrier : unit -> unit*) + +val _ = Define ` + ((InstructionSynchronizationBarrier:unit -> unit) () = () )`; + + +(*val __UNKNOWN_InstrSet : unit -> InstrSet*) + +val _ = Define ` + ((UNKNOWN_InstrSet:unit -> InstrSet) () = InstrSet_A64)`; + + +(*val Hint_Yield : unit -> unit*) + +val _ = Define ` + ((Hint_Yield:unit -> unit) () = () )`; + + +(*val Hint_Prefetch : mword ty64 -> PrefetchHint -> ii -> bool -> unit*) + +val _ = Define ` + ((Hint_Prefetch:(64)words$word -> PrefetchHint -> int -> bool -> unit) address hint target stream= () )`; + + +(*val Hint_Branch : BranchType -> unit*) + +val _ = Define ` + ((Hint_Branch:BranchType -> unit) hint= () )`; + + +(*val HaveFP16Ext : unit -> bool*) + +val _ = Define ` + ((HaveFP16Ext:unit -> bool) () = T)`; + + +(*val HaveAnyAArch32 : unit -> bool*) + +val _ = Define ` + ((HaveAnyAArch32:unit -> bool) () = F)`; + + +(*val __UNKNOWN_Fault : unit -> Fault*) + +val _ = Define ` + ((UNKNOWN_Fault:unit -> Fault) () = Fault_None)`; + + +(*val __UNKNOWN_FPUnaryOp : unit -> FPUnaryOp*) + +val _ = Define ` + ((UNKNOWN_FPUnaryOp:unit -> FPUnaryOp) () = FPUnaryOp_ABS)`; + + +(*val __UNKNOWN_FPType : unit -> FPType*) + +val _ = Define ` + ((UNKNOWN_FPType:unit -> FPType) () = FPType_Nonzero)`; + + +(*val __UNKNOWN_FPRounding : unit -> FPRounding*) + +val _ = Define ` + ((UNKNOWN_FPRounding:unit -> FPRounding) () = FPRounding_TIEEVEN)`; + + +(*val __UNKNOWN_FPMaxMinOp : unit -> FPMaxMinOp*) + +val _ = Define ` + ((UNKNOWN_FPMaxMinOp:unit -> FPMaxMinOp) () = FPMaxMinOp_MAX)`; + + +(*val FPDecodeRounding : mword ty2 -> FPRounding*) + +val _ = Define ` + ((FPDecodeRounding:(2)words$word -> FPRounding) rmode= + (let b__0 = rmode in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then FPRounding_TIEEVEN + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then FPRounding_POSINF + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then FPRounding_NEGINF + else FPRounding_ZERO))`; + + +(*val FPRoundingMode : mword ty32 -> FPRounding*) + +val _ = Define ` + ((FPRoundingMode:(32)words$word -> FPRounding) fpcr= (FPDecodeRounding ((slice fpcr (( 22 : int):ii) (( 2 : int):ii) : 2 words$word))))`; + + +(*val __UNKNOWN_FPConvOp : unit -> FPConvOp*) + +val _ = Define ` + ((UNKNOWN_FPConvOp:unit -> FPConvOp) () = FPConvOp_CVT_FtoI)`; + + +(*val __UNKNOWN_boolean : unit -> bool*) + +val _ = Define ` + ((UNKNOWN_boolean:unit -> bool) () = F)`; + + +(*val __ResetInterruptState : unit -> M unit*) + +val _ = Define ` + ((ResetInterruptState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS + (sail2_state_monad$write_regS PendingPhysicalSError_ref F) (sail2_state_monad$write_regS PendingInterrupt_ref F)))`; + + +(*val __ResetExecuteState : unit -> M unit*) + +val _ = Define ` + ((ResetExecuteState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS Sleeping_ref F))`; + + +(*val Unreachable : unit -> M unit*) + +val _ = Define ` + ((Unreachable:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val RBankSelect : mword ty5 -> ii -> ii -> ii -> ii -> ii -> ii -> ii -> M ii*) + +val _ = Define ` + ((RBankSelect:(5)words$word -> int -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode usr fiq irq svc abt und hyp= (sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let pat_0 = mode in + if (((pat_0 = M32_User))) then sail2_state_monad$returnS usr + else if (((pat_0 = M32_FIQ))) then sail2_state_monad$returnS fiq + else if (((pat_0 = M32_IRQ))) then sail2_state_monad$returnS irq + else if (((pat_0 = M32_Svc))) then sail2_state_monad$returnS svc + else if (((pat_0 = M32_Abort))) then sail2_state_monad$returnS abt + else if (((pat_0 = M32_Hyp))) then sail2_state_monad$returnS hyp + else if (((pat_0 = M32_Undef))) then sail2_state_monad$returnS und + else if (((pat_0 = M32_System))) then sail2_state_monad$returnS usr + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result))))`; + + +(*val TakeUnmaskedSErrorInterrupts : unit -> M unit*) + +val _ = Define ` + ((TakeUnmaskedSErrorInterrupts:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val TakeUnmaskedPhysicalSErrorInterrupts : bool -> M unit*) + +val _ = Define ` + ((TakeUnmaskedPhysicalSErrorInterrupts:bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) iesb_req= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val StopInstructionPrefetchAndEnableITR : unit -> M unit*) + +val _ = Define ` + ((StopInstructionPrefetchAndEnableITR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val SendEvent : unit -> M unit*) + +val _ = Define ` + ((SendEvent:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val MarkExclusiveLocal : FullAddress -> ii -> ii -> M unit*) + +val _ = Define ` + ((MarkExclusiveLocal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1= (sail2_state_monad$write_regS ExclusiveLocal_ref F))`; + + +(*val MarkExclusiveGlobal : FullAddress -> ii -> ii -> M unit*) + +val _ = Define ` + ((MarkExclusiveGlobal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val IsExclusiveGlobal : FullAddress -> ii -> ii -> M bool*) + +val _ = Define ` + ((IsExclusiveGlobal:FullAddress -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) paddress processorid size1= (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`; + + +(*val ExclusiveMonitorsStatus : unit -> M (mword ty1)*) + +val _ = Define ` + ((ExclusiveMonitorsStatus:unit ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word))))`; + + +(*val __UNKNOWN_Exception : unit -> Exception*) + +val _ = Define ` + ((UNKNOWN_Exception:unit -> Exception) () = Exception_Uncategorized)`; + + +(*val SendEventLocal : unit -> M unit*) + +val _ = Define ` + ((SendEventLocal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS EventRegister_ref (vec_of_bits [B1] : 1 words$word)))`; + + +(*val ErrorSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*) + +val _ = Define ` + ((ErrorSynchronizationBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types= () )`; + + +(*val EnterLowPowerState : unit -> M unit*) + +val _ = Define ` + ((EnterLowPowerState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS Sleeping_ref T))`; + + +(*val WaitForInterrupt : unit -> M unit*) + +val _ = Define ` + ((WaitForInterrupt:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (EnterLowPowerState () ))`; + + +(*val EndOfInstruction : unit -> M unit*) + +val _ = Define ` + ((EndOfInstruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$throwS (Error_ExceptionTaken () )))`; + + +(*val TweakCellRot : mword ty4 -> M (mword ty4)*) + +val _ = Define ` + ((TweakCellRot:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name= (sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (outcell : 4 bits) . + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 3 : int):ii) + ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)] : 1 words$word) + : 1 words$word)) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 2 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 3 : int):ii)] : 1 words$word) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 1 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 2 : int):ii)] : 1 words$word) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 0 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)] : 1 words$word) + : 4 words$word)) in + sail2_state_monad$returnS outcell)))`; + + +(*val TweakShuffle : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((TweakShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (outdata : 64 bits) . + let (outdata : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) ((slice indata (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__0 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) w__0 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 44 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__1 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) w__1 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 32 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__2 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) w__2 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) ((slice indata (( 48 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) ((slice indata (( 56 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 60 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__3 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) w__3 : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__4 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) w__4 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 40 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__5 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) w__5 : 64 words$word)) in sail2_state_monad$bindS + (TweakCellRot ((slice indata (( 36 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__6 : + 4 words$word) . + let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) w__6 : 64 words$word)) in + sail2_state_monad$returnS outdata))))))))))`; + + +(*val TweakCellInvRot : mword ty4 -> M (mword ty4)*) + +val _ = Define ` + ((TweakCellInvRot:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name= (sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (outcell : 4 bits) . + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 3 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 2 : int):ii)] : 1 words$word) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 2 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 1 : int):ii)] : 1 words$word) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 1 : int):ii) + (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)] : 1 words$word) + : 4 words$word)) in + let (outcell : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) outcell (( 0 : int):ii) + ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec incell_name (( 3 : int):ii)] : 1 words$word) + : 1 words$word)) + : 4 words$word)) in + sail2_state_monad$returnS outcell)))`; + + +(*val TweakInvShuffle : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((TweakInvShuffle:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) indata= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (outdata : 64 bits) . sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 48 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__0 : + 4 words$word) . + let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 0 : int):ii) w__0 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 4 : int):ii) ((slice indata (( 52 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 8 : int):ii) ((slice indata (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 12 : int):ii) ((slice indata (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 16 : int):ii) ((slice indata (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 20 : int):ii) ((slice indata (( 4 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__1 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 24 : int):ii) w__1 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 28 : int):ii) ((slice indata (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__2 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 32 : int):ii) w__2 : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 60 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__3 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 36 : int):ii) w__3 : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 56 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__4 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 40 : int):ii) w__4 : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__5 : + 4 words$word) . + let outdata = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 44 : int):ii) w__5 : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 48 : int):ii) ((slice indata (( 32 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 52 : int):ii) ((slice indata (( 36 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let outdata = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 56 : int):ii) ((slice indata (( 40 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (TweakCellInvRot ((slice indata (( 44 : int):ii) (( 4 : int):ii) : 4 words$word)) : ( 4 words$word) M) (\ (w__6 : + 4 words$word) . + let (outdata : 64 bits) = ((set_slice (( 64 : int):ii) (( 4 : int):ii) outdata (( 60 : int):ii) w__6 : 64 words$word)) in + sail2_state_monad$returnS outdata))))))))))`; + + +val _ = Define ` +((EL3:(2)words$word)= ((vec_of_bits [B1;B1] : 2 words$word)))`; + + +val _ = Define ` +((EL2:(2)words$word)= ((vec_of_bits [B1;B0] : 2 words$word)))`; + + +val _ = Define ` +((EL1:(2)words$word)= ((vec_of_bits [B0;B1] : 2 words$word)))`; + + +val _ = Define ` +((EL0:(2)words$word)= ((vec_of_bits [B0;B0] : 2 words$word)))`; + + +(*val __UNKNOWN_DeviceType : unit -> DeviceType*) + +val _ = Define ` + ((UNKNOWN_DeviceType:unit -> DeviceType) () = DeviceType_GRE)`; + + +(*val DecodeShift : mword ty2 -> ShiftType*) + +val _ = Define ` + ((DecodeShift:(2)words$word -> ShiftType) op= + (let b__0 = op in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then ShiftType_LSL + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then ShiftType_LSR + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then ShiftType_ASR + else ShiftType_ROR))`; + + +(*val DecodeRegExtend : mword ty3 -> ExtendType*) + +val _ = Define ` + ((DecodeRegExtend:(3)words$word -> ExtendType) op= + (let b__0 = op in + if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then ExtendType_UXTB + else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then ExtendType_UXTH + else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then ExtendType_UXTW + else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then ExtendType_UXTX + else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then ExtendType_SXTB + else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then ExtendType_SXTH + else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then ExtendType_SXTW + else ExtendType_SXTX))`; + + +val _ = Define ` +((DebugHalt_Watchpoint:(6)words$word)= ((vec_of_bits [B1;B0;B1;B0;B1;B1] : 6 words$word)))`; + + +val _ = Define ` +((DebugHalt_HaltInstruction:(6)words$word)= ((vec_of_bits [B1;B0;B1;B1;B1;B1] : 6 words$word)))`; + + +val _ = Define ` +((DebugHalt_Breakpoint:(6)words$word)= ((vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word)))`; + + +val _ = Define ` +((DebugException_VectorCatch:(4)words$word)= ((vec_of_bits [B0;B1;B0;B1] : 4 words$word)))`; + + +(*val DataSynchronizationBarrier : MBReqDomain -> MBReqTypes -> unit*) + +val _ = Define ` + ((DataSynchronizationBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types= () )`; + + +(*val DataMemoryBarrier : MBReqDomain -> MBReqTypes -> unit*) + +val _ = Define ` + ((DataMemoryBarrier:MBReqDomain -> MBReqTypes -> unit) domain1 types= () )`; + + +(*val aarch64_system_barriers : MBReqDomain -> MemBarrierOp -> MBReqTypes -> unit*) + +val _ = Define ` + ((aarch64_system_barriers:MBReqDomain -> MemBarrierOp -> MBReqTypes -> unit) domain1 op types= + ((case op of + MemBarrierOp_DSB => DataSynchronizationBarrier domain1 types + | MemBarrierOp_DMB => DataMemoryBarrier domain1 types + | MemBarrierOp_ISB => InstructionSynchronizationBarrier () + )))`; + + +(*val __UNKNOWN_Constraint : unit -> Constraint*) + +val _ = Define ` + ((UNKNOWN_Constraint:unit -> Constraint) () = Constraint_NONE)`; + + +(*val ConstrainUnpredictable : Unpredictable -> Constraint*) + +val _ = Define ` + ((ConstrainUnpredictable:Unpredictable -> Constraint) which= + ((case which of + Unpredictable_WBOVERLAPLD => Constraint_WBSUPPRESS + | Unpredictable_WBOVERLAPST => Constraint_NONE + | Unpredictable_LDPOVERLAP => Constraint_UNDEF + | Unpredictable_BASEOVERLAP => Constraint_NONE + | Unpredictable_DATAOVERLAP => Constraint_NONE + | Unpredictable_DEVPAGE2 => Constraint_FAULT + | Unpredictable_INSTRDEVICE => Constraint_NONE + | Unpredictable_RESCPACR => Constraint_UNKNOWN + | Unpredictable_RESMAIR => Constraint_UNKNOWN + | Unpredictable_RESTEXCB => Constraint_UNKNOWN + | Unpredictable_RESDACR => Constraint_UNKNOWN + | Unpredictable_RESPRRR => Constraint_UNKNOWN + | Unpredictable_RESVTCRS => Constraint_UNKNOWN + | Unpredictable_RESTnSZ => Constraint_FORCE + | Unpredictable_OORTnSZ => Constraint_FORCE + | Unpredictable_LARGEIPA => Constraint_FORCE + | Unpredictable_ESRCONDPASS => Constraint_FALSE + | Unpredictable_ILZEROIT => Constraint_FALSE + | Unpredictable_ILZEROT => Constraint_FALSE + | Unpredictable_BPVECTORCATCHPRI => Constraint_TRUE + | Unpredictable_VCMATCHHALF => Constraint_FALSE + | Unpredictable_VCMATCHDAPA => Constraint_FALSE + | Unpredictable_WPMASKANDBAS => Constraint_FALSE + | Unpredictable_WPBASCONTIGUOUS => Constraint_FALSE + | Unpredictable_RESWPMASK => Constraint_DISABLED + | Unpredictable_WPMASKEDBITS => Constraint_FALSE + | Unpredictable_RESBPWPCTRL => Constraint_DISABLED + | Unpredictable_BPNOTIMPL => Constraint_DISABLED + | Unpredictable_RESBPTYPE => Constraint_DISABLED + | Unpredictable_BPNOTCTXCMP => Constraint_DISABLED + | Unpredictable_BPMATCHHALF => Constraint_FALSE + | Unpredictable_BPMISMATCHHALF => Constraint_FALSE + | Unpredictable_RESTARTALIGNPC => Constraint_FALSE + | Unpredictable_RESTARTZEROUPPERPC => Constraint_TRUE + | Unpredictable_ZEROUPPER => Constraint_TRUE + | Unpredictable_ERETZEROUPPERPC => Constraint_TRUE + | Unpredictable_A32FORCEALIGNPC => Constraint_FALSE + | Unpredictable_SMD => Constraint_UNDEF + | Unpredictable_AFUPDATE => Constraint_TRUE + | Unpredictable_IESBinDebug => Constraint_TRUE + | Unpredictable_CLEARERRITEZERO => Constraint_FALSE + )))`; + + +(*val ClearPendingPhysicalSError : unit -> M unit*) + +val _ = Define ` + ((ClearPendingPhysicalSError:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS PendingPhysicalSError_ref F))`; + + +(*val ClearExclusiveLocal : ii -> M unit*) + +val _ = Define ` + ((ClearExclusiveLocal:int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) processorid= (sail2_state_monad$write_regS ExclusiveLocal_ref F))`; + + +(*val aarch64_system_monitors : unit -> M unit*) + +val _ = Define ` + ((aarch64_system_monitors:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (ClearExclusiveLocal ((ProcessorID () ))))`; + + +(*val system_monitors_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_monitors_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) (aarch64_system_monitors () )))`; + + +(*val ClearExclusiveByAddress : FullAddress -> ii -> ii -> unit*) + +val _ = Define ` + ((ClearExclusiveByAddress:FullAddress -> int -> int -> unit) paddress processorid size1= () )`; + + +(*val ClearEventRegister : unit -> M unit*) + +val _ = Define ` + ((ClearEventRegister:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$write_regS EventRegister_ref (vec_of_bits [B0] : 1 words$word)))`; + + +(*val CTI_SignalEvent : CrossTriggerIn -> M unit*) + +val _ = Define ` + ((CTI_SignalEvent:CrossTriggerIn ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) id= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val __UNKNOWN_BranchType : unit -> BranchType*) + +val _ = Define ` + ((UNKNOWN_BranchType:unit -> BranchType) () = BranchType_CALL)`; + + +(*val __UNKNOWN_AccType : unit -> AccType*) + +val _ = Define ` + ((UNKNOWN_AccType:unit -> AccType) () = AccType_NORMAL)`; + + +(*val CreateAccessDescriptorPTW : AccType -> bool -> bool -> ii -> M AccessDescriptor*) + +val _ = Define ` + ((CreateAccessDescriptorPTW:AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype secondstage s2fs1walk level= (sail2_state_monad$bindS + (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) . + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_acctype := acctype|>)) in + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_page_table_walk := T|>)) in + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_secondstage := s2fs1walk|>)) in + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_secondstage := secondstage|>)) in + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_level := level|>)) in + sail2_state_monad$returnS accdesc)))`; + + +(*val CreateAccessDescriptor : AccType -> M AccessDescriptor*) + +val _ = Define ` + ((CreateAccessDescriptor:AccType ->(regstate)sail2_state_monad$sequential_state ->(((AccessDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype= (sail2_state_monad$bindS + (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) . + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_acctype := acctype|>)) in + let (accdesc : AccessDescriptor) = ((accdesc with<| AccessDescriptor_page_table_walk := F|>)) in + sail2_state_monad$returnS accdesc)))`; + + +(*val aarch64_system_register_cpsr : PSTATEField -> mword ty4 -> M unit*) + +val _ = Define ` + ((aarch64_system_register_cpsr:PSTATEField ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) field' operand= + ((case field' of + PSTATEField_SP => sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__0 with<| ProcState_SP := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)] : 1 words$word))|>)) + | PSTATEField_DAIFSet => sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__1 with<| + ProcState_D := + ((or_vec w__2.ProcState_D (vec_of_bits [access_vec_dec operand (( 3 : int):ii)] : 1 words$word) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__3 with<| + ProcState_A := + ((or_vec w__4.ProcState_A (vec_of_bits [access_vec_dec operand (( 2 : int):ii)] : 1 words$word) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__5 with<| + ProcState_I := + ((or_vec w__6.ProcState_I (vec_of_bits [access_vec_dec operand (( 1 : int):ii)] : 1 words$word) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__7 with<| + ProcState_F := + ((or_vec w__8.ProcState_F (vec_of_bits [access_vec_dec operand (( 0 : int):ii)] : 1 words$word) + : 1 words$word))|>))))))))) + | PSTATEField_DAIFClr => sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__9 with<| + ProcState_D := + ((and_vec w__10.ProcState_D + ((not_vec (vec_of_bits [access_vec_dec operand (( 3 : int):ii)] : 1 words$word) : 1 words$word)) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__11 with<| + ProcState_A := + ((and_vec w__12.ProcState_A + ((not_vec (vec_of_bits [access_vec_dec operand (( 2 : int):ii)] : 1 words$word) : 1 words$word)) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__13 with<| + ProcState_I := + ((and_vec w__14.ProcState_I + ((not_vec (vec_of_bits [access_vec_dec operand (( 1 : int):ii)] : 1 words$word) : 1 words$word)) + : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__15 with<| + ProcState_F := + ((and_vec w__16.ProcState_F + ((not_vec (vec_of_bits [access_vec_dec operand (( 0 : int):ii)] : 1 words$word) : 1 words$word)) + : 1 words$word))|>))))))))) + | PSTATEField_PAN => sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__17 with<| ProcState_PAN := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)] : 1 words$word))|>)) + | PSTATEField_UAO => sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__18 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__18 with<| ProcState_UAO := ((vec_of_bits [access_vec_dec operand (( 0 : int):ii)] : 1 words$word))|>)) + )))`; + + +(*val AArch64_SysRegWrite : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*) + +val _ = Define ` + ((AArch64_SysRegWrite:int -> int -> int -> int -> int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 val_name= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val AArch64_SysRegRead : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*) + +val _ = Define ` + ((AArch64_SysRegRead:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4= + (let g__301 = (arg0, arg1, arg2, arg3, arg4) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "Tried to read system register") + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)))`; + + +(*val AArch64_SysInstr : ii -> ii -> ii -> ii -> ii -> mword ty64 -> M unit*) + +val _ = Define ` + ((AArch64_SysInstr:int -> int -> int -> int -> int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 val_name= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val AArch64_ResetControlRegisters : bool -> unit*) + +val _ = Define ` + ((AArch64_ResetControlRegisters:bool -> unit) cold_reset= () )`; + + +(*val AArch64_ReportDeferredSError : mword ty25 -> M (mword ty64)*) + +val _ = Define ` + ((AArch64_ReportDeferredSError:(25)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) syndrome= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (target : 64 bits) . + let (target : 64 bits) = + ((set_slice (( 64 : int):ii) (( 1 : int):ii) target (( 31 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) in + let (target : 64 bits) = + ((set_slice (( 64 : int):ii) (( 1 : int):ii) target (( 24 : int):ii) + (vec_of_bits [access_vec_dec syndrome (( 24 : int):ii)] : 1 words$word) + : 64 words$word)) in + let (target : 64 bits) = + ((set_slice (( 64 : int):ii) (( 24 : int):ii) target (( 0 : int):ii) ((slice syndrome (( 0 : int):ii) (( 24 : int):ii) : 24 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS target)))`; + + +(*val AArch64_MarkExclusiveVA : mword ty64 -> ii -> ii -> M unit*) + +val _ = Define ` + ((AArch64_MarkExclusiveVA:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address processorid size1= (sail2_state_monad$assert_expS F "FALSE"))`; + + +(*val AArch64_IsExclusiveVA : mword ty64 -> ii -> ii -> M bool*) + +val _ = Define ` + ((AArch64_IsExclusiveVA:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address processorid size1= (sail2_state_monad$seqS (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`; + + +(*val AArch64_CreateFaultRecord : Fault -> mword ty52 -> ii -> AccType -> bool -> mword ty1 -> mword ty2 -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CreateFaultRecord:Fault ->(52)words$word -> int -> AccType -> bool ->(1)words$word ->(2)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ ipaddress level acctype write extflag errortype secondstage s2fs1walk= (sail2_state_monad$bindS + (undefined_FaultRecord () ) (\ (fault : FaultRecord) . + let fault = ((fault with<| FaultRecord_typ := typ|>)) in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__0 : 4 bits) . + let fault = ((fault with<| FaultRecord_domain := w__0|>)) in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__1 : 4 bits) . + let (fault : FaultRecord) = ((fault with<| FaultRecord_debugmoe := w__1|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_errortype := errortype|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_ipaddress := ipaddress|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_level := level|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_acctype := acctype|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_write := write|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_extflag := extflag|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_secondstage := secondstage|>)) in + let (fault : FaultRecord) = ((fault with<| FaultRecord_s2fs1walk := s2fs1walk|>)) in + sail2_state_monad$returnS fault)))))`; + + +(*val AArch64_TranslationFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_TranslationFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . + AArch64_CreateFaultRecord Fault_Translation ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))`; + + +(*val AArch64_PermissionFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_PermissionFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . + AArch64_CreateFaultRecord Fault_Permission ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))`; + + +(*val AArch64_NoFault : unit -> M FaultRecord*) + +val _ = Define ` + ((AArch64_NoFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (level : ii) . + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . + let (secondstage : bool) = F in + let (s2fs1walk : bool) = F in + AArch64_CreateFaultRecord Fault_None ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))))))`; + + +(*val AArch64_DebugFault : AccType -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_DebugFault:AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype iswrite= (sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (level : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . + let (secondstage : bool) = F in + let (s2fs1walk : bool) = F in + AArch64_CreateFaultRecord Fault_Debug ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))))`; + + +(*val AArch64_CheckUnallocatedSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M bool*) + +val _ = Define ` + ((AArch64_CheckUnallocatedSystemAccess:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS F)))`; + + +(*val AArch64_CheckSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*) + +val _ = Define ` + ((AArch64_CheckSystemRegisterTraps:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (F, (vec_of_bits [B0;B0] : 2 words$word)))))`; + + +(*val AArch64_CheckAdvSIMDFPSystemRegisterTraps : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty1 -> M (bool * mword ty2)*) + +val _ = Define ` + ((AArch64_CheckAdvSIMDFPSystemRegisterTraps:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 read= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") (sail2_state_monad$returnS (F, (vec_of_bits [B0;B0] : 2 words$word)))))`; + + +(*val AArch64_AlignmentFault : AccType -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_AlignmentFault:AccType -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype iswrite secondstage= (sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (level : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) . + AArch64_CreateFaultRecord Fault_Alignment ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk)))))))`; + + +(*val AArch64_AddressSizeFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_AddressSizeFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . + AArch64_CreateFaultRecord Fault_AddressSize ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))`; + + +(*val AArch64_AccessFlagFault : mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_AccessFlagFault:(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress level acctype iswrite secondstage s2fs1walk= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (extflag : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (errortype : 2 bits) . + AArch64_CreateFaultRecord Fault_AccessFlag ipaddress level acctype iswrite extflag errortype + secondstage s2fs1walk))))`; + + +(*val AArch32_CurrentCond : unit -> M (mword ty4)*) + +val _ = Define ` + ((AArch32_CurrentCond:unit ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = ((sail2_state_monad$read_regS currentCond_ref : ( 4 words$word) M)))`; + + +(*val aget_SP : forall 'width . Size 'width => integer -> unit -> M (mword 'width)*) + +val _ = Define ` + ((aget_SP:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) () = (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . + if (((w__0.ProcState_SP = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SP_EL0_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + sail2_state_monad$returnS ((slice w__1 (( 0 : int):ii) width__tv : 'width words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__300 = (w__2.ProcState_EL) in + let pat_0 = p__300 in + if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SP_EL0_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((slice w__3 (( 0 : int):ii) width__tv : 'width words$word))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SP_EL1_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((slice w__4 (( 0 : int):ii) width__tv : 'width words$word))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SP_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((slice w__5 (( 0 : int):ii) width__tv : 'width words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SP_EL3_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((slice w__6 (( 0 : int):ii) width__tv : 'width words$word)))))))`; + + +(*val __IMPDEF_integer : string -> ii*) + +val _ = Define ` + ((IMPDEF_integer:string -> int) x= + (if (((x = "Maximum Physical Address Size"))) then (( 52 : int):ii) + else if (((x = "Maximum Virtual Address Size"))) then (( 56 : int):ii) + else (( 0 : int):ii)))`; + + +(*val VAMax : unit -> ii*) + +val _ = Define ` + ((VAMax:unit -> int) () = (IMPDEF_integer "Maximum Virtual Address Size"))`; + + +(*val PAMax : unit -> ii*) + +val _ = Define ` + ((PAMax:unit -> int) () = (IMPDEF_integer "Maximum Physical Address Size"))`; + + +(*val __IMPDEF_boolean : string -> bool*) + +val _ = Define ` + ((IMPDEF_boolean:string -> bool) x= + (if (((x = "Condition valid for trapped T32"))) then T + else if (((x = "Has Dot Product extension"))) then T + else if (((x = "Has RAS extension"))) then T + else if (((x = "Has SHA512 and SHA3 Crypto instructions"))) then T + else if (((x = "Has SM3 and SM4 Crypto instructions"))) then T + else if (((x = "Has basic Crypto instructions"))) then T + else if (((x = "Have CRC extension"))) then T + else if (((x = "Report I-cache maintenance fault in IFSR"))) then T + else if (((x = "Reserved Control Space EL0 Trapped"))) then T + else if (((x = "Translation fault on misprogrammed contiguous bit"))) then T + else if (((x = "UNDEF unallocated CP15 access at NS EL0"))) then T + else if (((x = "UNDEF unallocated CP15 access at NS EL0"))) then T + else F))`; + + +(*val WaitForEvent : unit -> M unit*) + +val _ = Define ` + ((WaitForEvent:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS EventRegister_ref : ( 1 words$word) M) (\ (w__0 : 1 bits) . + if (((w__0 = (vec_of_bits [B0] : 1 words$word)))) then EnterLowPowerState () + else sail2_state_monad$returnS () )))`; + + +(*val ThisInstrLength : unit -> M ii*) + +val _ = Define ` + ((ThisInstrLength:unit ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS ThisInstrEnc_ref) (\ (w__0 : InstrEnc) . + sail2_state_monad$returnS (if (((w__0 = T16))) then (( 16 : int):ii) + else (( 32 : int):ii)))))`; + + +(*val RoundTowardsZero : real -> ii*) + +val _ = Define ` + ((RoundTowardsZero:real -> int) x= + (if (((x = (realFromFrac(( 0 : int))(( 10 : int)))))) then (( 0 : int):ii) + else if ((x >= (realFromFrac(( 0 : int))(( 10 : int))))) then flr x + else clg x))`; + + +(*val Restarting : unit -> M bool*) + +val _ = Define ` + ((Restarting:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS (((((slice w__0 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))))))`; + + +(*val PtrHasUpperAndLowerAddRanges : unit -> M bool*) + +val _ = Define ` + ((PtrHasUpperAndLowerAddRanges:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL1))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL = EL0)))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL = EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))))`; + + +(*val MemAttrDefaults : MemoryAttributes -> M MemoryAttributes*) + +val _ = Define ` + ((MemAttrDefaults:MemoryAttributes ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) memattrs__arg= + (let memattrs = memattrs__arg in + if (((memattrs.MemoryAttributes_typ = MemType_Device))) then sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (w__0 : MemAttrHints) . + let memattrs = ((memattrs with<| MemoryAttributes_inner := w__0|>)) in sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (w__1 : MemAttrHints) . + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_shareable := T|>)) in + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_outershareable := T|>)) in + sail2_state_monad$returnS memattrs)) + else sail2_state_monad$bindS + (undefined_DeviceType () ) (\ (w__2 : DeviceType) . + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_device := w__2|>)) in + let (memattrs : MemoryAttributes) = + (if ((((((memattrs.MemoryAttributes_inner.MemAttrHints_attrs = MemAttr_NC))) /\ (((memattrs.MemoryAttributes_outer.MemAttrHints_attrs = MemAttr_NC)))))) then + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_shareable := T|>)) in + (memattrs with<| MemoryAttributes_outershareable := T|>) + else memattrs) in + sail2_state_monad$returnS memattrs)))`; + + +(*val IsEventRegisterSet : unit -> M bool*) + +val _ = Define ` + ((IsEventRegisterSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS EventRegister_ref : ( 1 words$word) M) (\ (w__0 : 1 bits) . + sail2_state_monad$returnS (((w__0 = (vec_of_bits [B1] : 1 words$word)))))))`; + + +(*val HaveEL : mword ty2 -> bool*) + +val _ = Define ` + ((HaveEL:(2)words$word -> bool) el= (if ((((((el = EL1))) \/ (((el = EL0)))))) then T else T))`; + + +(*val HighestEL : unit -> mword ty2*) + +val _ = Define ` + ((HighestEL:unit ->(2)words$word) () = (if ((HaveEL EL3)) then EL3 else if ((HaveEL EL2)) then EL2 else EL1))`; + + +(*val Have16bitVMID : unit -> bool*) + +val _ = Define ` + ((Have16bitVMID:unit -> bool) () = (HaveEL EL2))`; + + +(*val HasArchVersion : ArchVersion -> bool*) + +val _ = Define ` + ((HasArchVersion:ArchVersion -> bool) version= + ((((version = ARMv8p0))) \/ ((((((version = ARMv8p1))) \/ ((((((version = ARMv8p2))) \/ (((version = ARMv8p3)))))))))))`; + + +(*val HaveVirtHostExt : unit -> bool*) + +val _ = Define ` + ((HaveVirtHostExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val HaveUAOExt : unit -> bool*) + +val _ = Define ` + ((HaveUAOExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HaveTrapLoadStoreMultipleDeviceExt : unit -> bool*) + +val _ = Define ` + ((HaveTrapLoadStoreMultipleDeviceExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HaveStatisticalProfiling : unit -> bool*) + +val _ = Define ` + ((HaveStatisticalProfiling:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HaveRASExt : unit -> bool*) + +val _ = Define ` + ((HaveRASExt:unit -> bool) () = (((HasArchVersion ARMv8p2)) \/ ((IMPDEF_boolean "Has RAS extension"))))`; + + +(*val HavePrivATExt : unit -> bool*) + +val _ = Define ` + ((HavePrivATExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HavePANExt : unit -> bool*) + +val _ = Define ` + ((HavePANExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val HavePACExt : unit -> bool*) + +val _ = Define ` + ((HavePACExt:unit -> bool) () = (HasArchVersion ARMv8p3))`; + + +(*val HaveNVExt : unit -> bool*) + +val _ = Define ` + ((HaveNVExt:unit -> bool) () = (HasArchVersion ARMv8p3))`; + + +(*val HaveFJCVTZSExt : unit -> bool*) + +val _ = Define ` + ((HaveFJCVTZSExt:unit -> bool) () = (HasArchVersion ARMv8p3))`; + + +(*val HaveExtendedExecuteNeverExt : unit -> bool*) + +val _ = Define ` + ((HaveExtendedExecuteNeverExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HaveDirtyBitModifierExt : unit -> bool*) + +val _ = Define ` + ((HaveDirtyBitModifierExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val HaveCommonNotPrivateTransExt : unit -> bool*) + +val _ = Define ` + ((HaveCommonNotPrivateTransExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val HaveCRCExt : unit -> bool*) + +val _ = Define ` + ((HaveCRCExt:unit -> bool) () = (((HasArchVersion ARMv8p1)) \/ ((IMPDEF_boolean "Have CRC extension"))))`; + + +(*val HaveAtomicExt : unit -> bool*) + +val _ = Define ` + ((HaveAtomicExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val HaveAccessFlagUpdateExt : unit -> bool*) + +val _ = Define ` + ((HaveAccessFlagUpdateExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val Have52BitVAExt : unit -> bool*) + +val _ = Define ` + ((Have52BitVAExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val Have52BitPAExt : unit -> bool*) + +val _ = Define ` + ((Have52BitPAExt:unit -> bool) () = (HasArchVersion ARMv8p2))`; + + +(*val AArch64_HaveHPDExt : unit -> bool*) + +val _ = Define ` + ((AArch64_HaveHPDExt:unit -> bool) () = (HasArchVersion ARMv8p1))`; + + +(*val ExternalInvasiveDebugEnabled : unit -> M bool*) + +val _ = Define ` + ((ExternalInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGEN_ref) (\ (w__0 : signal) . sail2_state_monad$returnS (((w__0 = HIGH))))))`; + + +(*val ConstrainUnpredictableInteger : ii -> ii -> Unpredictable -> M (Constraint * ii)*) + +val _ = Define ` + ((ConstrainUnpredictableInteger:int -> int -> Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((Constraint#int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) low high which= + (let (c : Constraint) = (ConstrainUnpredictable which) in + if (((c = Constraint_UNKNOWN))) then sail2_state_monad$returnS (c, low) + else sail2_state_monad$bindS (undefined_int () ) (\ (w__0 : ii) . sail2_state_monad$returnS (c, w__0))))`; + + +(*val ConstrainUnpredictableBool : Unpredictable -> M bool*) + +val _ = Define ` + ((ConstrainUnpredictableBool:Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) which= + (let (c : Constraint) = (ConstrainUnpredictable which) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_TRUE))) \/ (((c = Constraint_FALSE)))))) "((c == Constraint_TRUE) || (c == Constraint_FALSE))") + (sail2_state_monad$returnS (((c = Constraint_TRUE))))))`; + + +(*val CombineS1S2Device : DeviceType -> DeviceType -> M DeviceType*) + +val _ = Define ` + ((CombineS1S2Device:DeviceType -> DeviceType ->(regstate)sail2_state_monad$sequential_state ->(((DeviceType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1device s2device= (sail2_state_monad$bindS + (undefined_DeviceType () ) (\ (result : DeviceType) . + let (result : DeviceType) = + (if ((((((s2device = DeviceType_nGnRnE))) \/ (((s1device = DeviceType_nGnRnE)))))) then + DeviceType_nGnRnE + else if ((((((s2device = DeviceType_nGnRE))) \/ (((s1device = DeviceType_nGnRE)))))) then + DeviceType_nGnRE + else if ((((((s2device = DeviceType_nGRE))) \/ (((s1device = DeviceType_nGRE)))))) then + DeviceType_nGRE + else DeviceType_GRE) in + sail2_state_monad$returnS result)))`; + + +(*val CombineS1S2AttrHints : MemAttrHints -> MemAttrHints -> M MemAttrHints*) + +val _ = Define ` + ((CombineS1S2AttrHints:MemAttrHints -> MemAttrHints ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1desc s2desc= (sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (result : MemAttrHints) . sail2_state_monad$bindS + (if ((((((s2desc.MemAttrHints_attrs = (vec_of_bits [B0;B1] : 2 words$word)))) \/ (((s1desc.MemAttrHints_attrs = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__0 : 2 bits) . + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := w__0|>)) in + sail2_state_monad$returnS result) + else + let (result : MemAttrHints) = + (if ((((((s2desc.MemAttrHints_attrs = MemAttr_NC))) \/ (((s1desc.MemAttrHints_attrs = MemAttr_NC)))))) then + (result with<| MemAttrHints_attrs := MemAttr_NC|>) + else if ((((((s2desc.MemAttrHints_attrs = MemAttr_WT))) \/ (((s1desc.MemAttrHints_attrs = MemAttr_WT)))))) then + (result with<| MemAttrHints_attrs := MemAttr_WT|>) + else (result with<| MemAttrHints_attrs := MemAttr_WB|>)) in + sail2_state_monad$returnS result) (\ (result : MemAttrHints) . + let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := (s1desc.MemAttrHints_hints)|>)) in + let (result : MemAttrHints) = + ((result with<| MemAttrHints_transient := (s1desc.MemAttrHints_transient)|>)) in + sail2_state_monad$returnS result))))`; + + +(*val AArch64_InstructionDevice : AddressDescriptor -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M AddressDescriptor*) + +val _ = Define ` + ((AArch64_InstructionDevice:AddressDescriptor ->(64)words$word ->(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addrdesc__arg vaddress ipaddress level acctype iswrite secondstage s2fs1walk= + (let addrdesc = addrdesc__arg in + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_INSTRDEVICE) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_NONE))) \/ (((c = Constraint_FAULT)))))) "((c == Constraint_NONE) || (c == Constraint_FAULT))") + (if (((c = Constraint_FAULT))) then sail2_state_monad$bindS + (AArch64_PermissionFault ipaddress level acctype iswrite secondstage s2fs1walk) (\ (w__0 : + FaultRecord) . + let (addrdesc : AddressDescriptor) = ((addrdesc with<| AddressDescriptor_fault := w__0|>)) in + sail2_state_monad$returnS addrdesc) + else + let (tmp_120 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in + let tmp_120 = ((tmp_120 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_120|>)) in + let (tmp_130 : MemAttrHints) = (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let tmp_130 = ((tmp_130 with<| MemAttrHints_attrs := MemAttr_NC|>)) in + let (tmp_140 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in + let tmp_140 = ((tmp_140 with<| MemoryAttributes_inner := tmp_130|>)) in + let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_140|>)) in + let (tmp_150 : MemAttrHints) = (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let tmp_150 = ((tmp_150 with<| MemAttrHints_hints := MemHint_No|>)) in + let (tmp_160 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in + let tmp_160 = ((tmp_160 with<| MemoryAttributes_inner := tmp_150|>)) in + let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_160|>)) in + let (tmp_170 : MemoryAttributes) = (addrdesc.AddressDescriptor_memattrs) in + let tmp_170 = + ((tmp_170 with<| + MemoryAttributes_outer := (addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner)|>)) in + let addrdesc = ((addrdesc with<| AddressDescriptor_memattrs := tmp_170|>)) in sail2_state_monad$bindS + (MemAttrDefaults addrdesc.AddressDescriptor_memattrs) (\ (w__1 : MemoryAttributes) . + let (addrdesc : AddressDescriptor) = ((addrdesc with<| AddressDescriptor_memattrs := w__1|>)) in + sail2_state_monad$returnS addrdesc))))`; + + +(*val aget_Vpart : forall 'width . Size 'width => integer -> ii -> ii -> M (mword 'width)*) + +val _ = Define ` + ((aget_Vpart:int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n part= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((part = (( 0 : int):ii)))) \/ (((part = (( 1 : int):ii))))))) "((part == 0) || (part == 1))")) + (if (((part = (( 0 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))") + (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 bits) list) . + sail2_state_monad$returnS ((slice ((access_list_dec w__0 n : 128 words$word)) (( 0 : int):ii) width__tv : 'width words$word))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((width__tv = (( 64 : int):ii)))) "(width == 64)") + (sail2_state_monad$read_regS V_ref)) (\ (w__1 : ( 128 bits) list) . + sail2_state_monad$returnS ((words$w2w + ((slice ((access_list_dec w__1 n : 128 words$word)) (( 64 : int):ii) (( 64 : int):ii) : 'width words$word)) + : 'width words$word))))))`; + + +(*val aget_V : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*) + +val _ = Define ` + ((aget_V:int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ ((((((width__tv = (( 64 : int):ii)))) \/ (((width__tv = (( 128 : int):ii)))))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))")) + (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 bits) list) . + sail2_state_monad$returnS ((slice ((access_list_dec w__0 n : 128 words$word)) (( 0 : int):ii) width__tv : 'width words$word)))))`; + + +(*val LookUpRIndex : ii -> mword ty5 -> M ii*) + +val _ = Define ` + ((LookUpRIndex:int ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n mode= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 14 : int):ii)))))) "((n >= 0) && (n <= 14))") + (undefined_int () )) (\ (result : ii) . + let p0_ = n in + if (((p0_ = (( 8 : int):ii)))) then RBankSelect mode (( 8 : int):ii) (( 24 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii) (( 8 : int):ii) + else if (((p0_ = (( 9 : int):ii)))) then RBankSelect mode (( 9 : int):ii) (( 25 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii) (( 9 : int):ii) + else if (((p0_ = (( 10 : int):ii)))) then + RBankSelect mode (( 10 : int):ii) (( 26 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii) (( 10 : int):ii) + else if (((p0_ = (( 11 : int):ii)))) then + RBankSelect mode (( 11 : int):ii) (( 27 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii) (( 11 : int):ii) + else if (((p0_ = (( 12 : int):ii)))) then + RBankSelect mode (( 12 : int):ii) (( 28 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii) (( 12 : int):ii) + else if (((p0_ = (( 13 : int):ii)))) then + RBankSelect mode (( 13 : int):ii) (( 29 : int):ii) (( 17 : int):ii) (( 19 : int):ii) (( 21 : int):ii) (( 23 : int):ii) (( 15 : int):ii) + else if (((p0_ = (( 14 : int):ii)))) then + RBankSelect mode (( 14 : int):ii) (( 30 : int):ii) (( 16 : int):ii) (( 18 : int):ii) (( 20 : int):ii) (( 22 : int):ii) (( 14 : int):ii) + else sail2_state_monad$returnS n)))`; + + +(*val HighestSetBit : forall 'N . Size 'N => mword 'N -> M ii*) + +val _ = Define ` + ((HighestSetBit:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= + (sail2_state_monad$catch_early_returnS + ( sail2_state_monad$seqS(sail2_state$foreachS (index_list ((((int_of_num (words$word_len x))) - (( 1 : int):ii))) (( 0 : int):ii) (~ (( 1 : int):ii))) () + (\ i unit_var . + if ((((vec_of_bits [access_vec_dec x i] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (sail2_state_monad$early_returnS i : (unit, ii) MR) + else sail2_state_monad$returnS () )) + (sail2_state_monad$returnS ((~ (( 1 : int):ii)))))))`; + + +(*val CountLeadingZeroBits : forall 'N . Size 'N => mword 'N -> M ii*) + +val _ = Define ` + ((CountLeadingZeroBits:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= (sail2_state_monad$bindS + (HighestSetBit x) (\ (w__0 : ii) . + sail2_state_monad$returnS ((((((int_of_num (words$word_len x))) - (( 1 : int):ii))) - ((ex_int w__0)))))))`; + + +(*val CountLeadingSignBits : forall 'N . Size 'N => mword 'N -> M ii*) + +val _ = Define ` + ((CountLeadingSignBits:'N words$word ->(regstate)sail2_state_monad$sequential_state ->(((ii),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= + (CountLeadingZeroBits + ((xor_vec ((shiftr x (( 1 : int):ii) : 'N words$word)) + ((and_vec x ((slice_mask ((int_of_num (words$word_len x))) (( 0 : int):ii) ((int_of_num (words$word_len x))) : 'N words$word)) : 'N words$word)) + : 'N words$word))))`; + + +(*val BitReverse : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +val _ = Define ` + ((BitReverse:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data= (sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data))) : ( 'N words$word) M) (\ (result : 'N bits) . + let (result : 'N bits) = + (foreach (index_list (( 0 : int):ii) ((((int_of_num (words$word_len data))) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice ((int_of_num (words$word_len data))) (( 1 : int):ii) result + ((((((int_of_num (words$word_len data))) - i)) - (( 1 : int):ii))) + (vec_of_bits [access_vec_dec data i] : 1 words$word) + : 'N words$word))) in + sail2_state_monad$returnS result)))`; + + +(*val NextInstrAddr : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +val _ = Define ` + ((NextInstrAddr:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (ThisInstrLength () ) (\ (w__1 : ii) . + sail2_state_monad$returnS ((slice ((add_vec_int w__0 ((((ex_int w__1)) / (( 8 : int):ii))) : 64 words$word)) (( 0 : int):ii) + N__tv + : 'N words$word))))))`; + + +(*val AArch32_ExceptionClass : Exception -> M (ii * mword ty1)*) + +val _ = Define ` + ((AArch32_ExceptionClass:Exception ->(regstate)sail2_state_monad$sequential_state ->(((int#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ= (sail2_state_monad$bindS + (ThisInstrLength () ) (\ (w__0 : ii) . + let (il : 1 bits) = + (if (((((ex_int w__0)) = (( 32 : int):ii)))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_int () ) (\ (ec : ii) . sail2_state_monad$bindS + (case typ of + Exception_Uncategorized => + let (ec : ii) = ((( 0 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_WFxTrap => + let (ec : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP15RTTrap => + let (ec : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP15RRTTrap => + let (ec : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP14RTTrap => + let (ec : ii) = ((( 5 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP14DTTrap => + let (ec : ii) = ((( 6 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_AdvSIMDFPAccessTrap => + let (ec : ii) = ((( 7 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_FPIDTrap => + let (ec : ii) = ((( 8 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP14RRTTrap => + let (ec : ii) = ((( 12 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_IllegalState => + let (ec : ii) = ((( 14 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_SupervisorCall => + let (ec : ii) = ((( 17 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_HypervisorCall => + let (ec : ii) = ((( 18 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_MonitorCall => + let (ec : ii) = ((( 19 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_InstructionAbort => + let (ec : ii) = ((( 32 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_PCAlignment => + let (ec : ii) = ((( 34 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_DataAbort => + let (ec : ii) = ((( 36 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_FPTrappedException => + let (ec : ii) = ((( 40 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS (ec, il)) + ) (\ varstup . let ((ec : ii), (il : 1 bits)) = varstup in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((((ex_int ec)) = (( 32 : int):ii)))) \/ (((((ex_int ec)) = (( 36 : int):ii)))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL = EL2)))))) (\ (w__2 : + bool) . + let (ec : ii) = (if w__2 then ((ex_int ec)) + (( 1 : int):ii) else ec) in + sail2_state_monad$returnS (ec, il)))))))`; + + +(*val RotCell : mword ty4 -> ii -> M (mword ty4)*) + +val _ = Define ` + ((RotCell:(4)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) incell_name amount= (sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (tmp : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (outcell : 4 bits) . + let (tmp : 8 bits) = + ((set_slice (( 8 : int):ii) (( 8 : int):ii) tmp (( 0 : int):ii) + ((concat_vec ((slice incell_name (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice incell_name (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 8 words$word)) + : 8 words$word)) in + let (outcell : 4 bits) = ((slice tmp (((( 4 : int):ii) - amount)) (( 4 : int):ii) : 4 words$word)) in + sail2_state_monad$returnS outcell))))`; + + +(*val FPNeg : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +val _ = Define ` + ((FPNeg:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op= + (let p0_ = (int_of_num (words$word_len op)) in + if (((p0_ = (( 16 : int):ii)))) then + let (op : 16 words$word) = ((words$w2w op : 16 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op (((( 16 : int):ii) - (( 1 : int):ii)))] + : 1 words$word) + : 1 words$word)) + ((slice op (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii))) : 15 words$word)) + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then + let (op : 32 words$word) = ((words$w2w op : 32 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op (((( 32 : int):ii) - (( 1 : int):ii)))] + : 1 words$word) + : 1 words$word)) + ((slice op (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii))) : 31 words$word)) + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then + let (op : 64 words$word) = ((words$w2w op : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec + ((not_vec + (vec_of_bits [access_vec_dec op (((( 64 : int):ii) - (( 1 : int):ii)))] + : 1 words$word) + : 1 words$word)) + ((slice op (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii))) : 63 words$word)) + : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val FPAbs : forall 'N . Size 'N => mword 'N -> M (mword 'N)*) + +val _ = Define ` + ((FPAbs:'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op= + (let p0_ = (int_of_num (words$word_len op)) in + if (((p0_ = (( 16 : int):ii)))) then + let (op : 16 words$word) = ((words$w2w op : 16 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((slice op (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii))) : 15 words$word)) + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then + let (op : 32 words$word) = ((words$w2w op : 32 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((slice op (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii))) : 31 words$word)) + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then + let (op : 64 words$word) = ((words$w2w op : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$returnS ((words$w2w + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((slice op (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii))) : 63 words$word)) + : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val EncodeLDFSC : Fault -> ii -> M (mword ty6)*) + +val _ = Define ` + ((EncodeLDFSC:Fault -> int ->(regstate)sail2_state_monad$sequential_state ->((((6)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ level= (sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (result : 6 bits) . + (case typ of + Fault_AddressSize => + let result = + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + (sail2_state_monad$returnS result) + | Fault_AccessFlag => + let result = + ((concat_vec (vec_of_bits [B0;B0;B1;B0] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii)))))))))) "((level == 1) || ((level == 2) || (level == 3)))") + (sail2_state_monad$returnS result) + | Fault_Permission => + let result = + ((concat_vec (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii)))))))))) "((level == 1) || ((level == 2) || (level == 3)))") + (sail2_state_monad$returnS result) + | Fault_Translation => + let result = + ((concat_vec (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + (sail2_state_monad$returnS result) + | Fault_SyncExternal => + let (result : 6 bits) = ((vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_SyncExternalOnWalk => + let result = + ((concat_vec (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + (sail2_state_monad$returnS result) + | Fault_SyncParity => + let (result : 6 bits) = ((vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_SyncParityOnWalk => + let result = + ((concat_vec (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + ((GetSlice_int ((make_the_value (( 2 : int):ii) : 2 itself)) level (( 0 : int):ii) : 2 words$word)) + : 6 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((level = (( 0 : int):ii)))) \/ ((((((level = (( 1 : int):ii)))) \/ ((((((level = (( 2 : int):ii)))) \/ (((level = (( 3 : int):ii))))))))))))) "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + (sail2_state_monad$returnS result) + | Fault_AsyncParity => + let (result : 6 bits) = ((vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_AsyncExternal => + let (result : 6 bits) = ((vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_Alignment => + let (result : 6 bits) = ((vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_Debug => + let (result : 6 bits) = ((vec_of_bits [B1;B0;B0;B0;B1;B0] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_TLBConflict => + let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_Lockdown => + let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word)) in + sail2_state_monad$returnS result + | Fault_Exclusive => + let (result : 6 bits) = ((vec_of_bits [B1;B1;B0;B1;B0;B1] : 6 words$word)) in + sail2_state_monad$returnS result + | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result) + ))))`; + + + + +(*val AArch32_ReportHypEntry : ExceptionRecord -> M unit*) + +val _ = Define ` + ((AArch32_ReportHypEntry:ExceptionRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception= + (let (typ : Exception) = (exception.ExceptionRecord_typ) in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (il : 1 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (ec : ii) . sail2_state_monad$bindS + (AArch32_ExceptionClass typ : ((ii # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let ec = tup__0 in + let il = tup__1 in + let (iss : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (il : 1 bits) = + (if (((((((((((ex_int ec)) = (( 36 : int):ii)))) \/ (((((ex_int ec)) = (( 37 : int):ii))))))) /\ ((((vec_of_bits [access_vec_dec iss (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + (vec_of_bits [B1] : 1 words$word) + else il) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + HSR_ref + ((concat_vec + ((concat_vec + ((GetSlice_int ((make_the_value (( 6 : int):ii) : 6 itself)) ec (( 0 : int):ii) : 6 words$word)) il + : 7 words$word)) iss + : 32 words$word))) + (if ((((((typ = Exception_InstructionAbort))) \/ (((typ = Exception_PCAlignment)))))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HIFAR_ref ((slice exception.ExceptionRecord_vaddress (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__0 : 32 bits) . + sail2_state_monad$write_regS HDFAR_ref w__0) + else if (((typ = Exception_DataAbort))) then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS HIFAR_ref w__1) + (sail2_state_monad$write_regS HDFAR_ref ((slice exception.ExceptionRecord_vaddress (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)))) + else sail2_state_monad$returnS () )) + (if exception.ExceptionRecord_ipavalid then sail2_state_monad$bindS + (sail2_state_monad$read_regS HPFAR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + sail2_state_monad$write_regS + HPFAR_ref + ((set_slice (( 32 : int):ii) (( 28 : int):ii) w__2 (( 4 : int):ii) + ((slice exception.ExceptionRecord_ipaddress (( 12 : int):ii) (( 28 : int):ii) : 28 words$word)) + : 32 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HPFAR_ref : ( 32 words$word) M) (\ (w__3 : 32 words$word) . sail2_state_monad$bindS + (undefined_bitvector (( 28 : int):ii) : ( 28 words$word) M) (\ (w__4 : 28 words$word) . + sail2_state_monad$write_regS HPFAR_ref ((set_slice (( 32 : int):ii) (( 28 : int):ii) w__3 (( 4 : int):ii) w__4 : 32 words$word))))))))))`; + + +(*val aset_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> mword 'size -> M (mword 'N)*) + +(*val aset_Elem__1 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> mword 'size -> M (mword 'N)*) + +val _ = Define ` + ((aset_Elem__0:'N words$word -> int -> 'size itself -> 'size words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name__arg e size1 value_name= + (let size1 = (size_itself_int size1) in + let vector_name = vector_name__arg in sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((e >= (( 0 : int):ii))) /\ ((((((e + (( 1 : int):ii))) * size1)) <= ((int_of_num (words$word_len vector_name)))))))) "((e >= 0) && (((e + 1) * size) <= N))") + (let (vector_name : 'N words$word) = + ((set_slice ((int_of_num (words$word_len vector_name))) size1 vector_name ((e * size1)) value_name + : 'N words$word)) in + sail2_state_monad$returnS vector_name)))`; + + +val _ = Define ` + ((aset_Elem__1:'N words$word -> int -> 'size words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name__arg e value_name= + (let vector_name = vector_name__arg in + (aset_Elem__0 vector_name e ((make_the_value ((int_of_num (words$word_len value_name))) : 'size itself)) value_name + : ( 'N words$word) M)))`; + + +(*val aget_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> M (mword 'size)*) + +(*val aget_Elem__1 : forall 'N 'size . Size 'N, Size 'size => integer -> mword 'N -> ii -> M (mword 'size)*) + +val _ = Define ` + ((aget_Elem__0:'N words$word -> int -> 'size itself ->(regstate)sail2_state_monad$sequential_state ->((('size words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vector_name e size1= + (let size1 = (size_itself_int size1) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((e >= (( 0 : int):ii))) /\ ((((((e + (( 1 : int):ii))) * size1)) <= ((int_of_num (words$word_len vector_name)))))))) "((e >= 0) && (((e + 1) * size) <= N))") + (sail2_state_monad$returnS ((slice vector_name ((e * size1)) size1 : 'size words$word)))))`; + + +val _ = Define ` + ((aget_Elem__1:int -> 'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('size words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (size__tv : int) vector_name e= + ((aget_Elem__0 vector_name e ((make_the_value size__tv : 'size itself)) : ( 'size words$word) M)))`; + + +(*val UnsignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) + +val _ = Define ` + ((UnsignedSatQ:int -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N= + (let N = (size_itself_int N) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (saturated : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let ((result : ii), (saturated : bool)) = + (if ((i > ((((pow2 N)) - (( 1 : int):ii))))) then + let (result : ii) = (((pow2 N)) - (( 1 : int):ii)) in + let (saturated : bool) = T in + (result, saturated) + else + let ((result : ii), (saturated : bool)) = + (if ((i < (( 0 : int):ii))) then + let (result : ii) = ((( 0 : int):ii)) in + let (saturated : bool) = T in + (result, saturated) + else + let (result : ii) = i in + let (saturated : bool) = F in + (result, saturated)) in + (result, saturated)) in + sail2_state_monad$returnS ((GetSlice_int ((make_the_value N : 'N itself)) result (( 0 : int):ii) : 'N words$word), saturated)))))`; + + +(*val SignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) + +val _ = Define ` + ((SignedSatQ:int -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N= + (let N = (size_itself_int N) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (saturated : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let ((result : ii), (saturated : bool)) = + (if ((i > ((((pow2 ((N - (( 1 : int):ii))))) - (( 1 : int):ii))))) then + let (result : ii) = (((pow2 ((N - (( 1 : int):ii))))) - (( 1 : int):ii)) in + let (saturated : bool) = T in + (result, saturated) + else + let ((result : ii), (saturated : bool)) = + (if ((i < ((~ ((pow2 ((N - (( 1 : int):ii))))))))) then + let (result : ii) = (~ ((pow2 ((N - (( 1 : int):ii)))))) in + let (saturated : bool) = T in + (result, saturated) + else + let (result : ii) = i in + let (saturated : bool) = F in + (result, saturated)) in + (result, saturated)) in + sail2_state_monad$returnS ((GetSlice_int ((make_the_value N : 'N itself)) result (( 0 : int):ii) : 'N words$word), saturated)))))`; + + +(*val SatQ : forall 'N . Size 'N => ii -> itself 'N -> bool -> M (mword 'N * bool)*) + +val _ = Define ` + ((SatQ:int -> 'N itself -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) i N unsigned= + (let N = (size_itself_int N) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (sat : bool) . sail2_state_monad$bindS + (undefined_bitvector N : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (if unsigned then (UnsignedSatQ i ((make_the_value N : 'N itself)) : (( 'N words$word # bool)) M) + else (SignedSatQ i ((make_the_value N : 'N itself)) : (( 'N words$word # bool)) M)) (\ varstup . let (tup__0, tup__1) = varstup in + let (result : 'N bits) = tup__0 in + let (sat : bool) = tup__1 in + sail2_state_monad$returnS (result, sat))))))`; + + +(*val Replicate : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +val _ = Define ` + ((Replicate:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((N__tv % ((int_of_num (words$word_len x))))) = (( 0 : int):ii)))) "((N MOD M) == 0)") + (let O1 = (N__tv / ((int_of_num (words$word_len x)))) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") (sail2_state_monad$returnS ((replicate_bits x ((N__tv / ((int_of_num (words$word_len x))))) : 'N words$word))))))`; + + +(*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) + +(*val Zeros__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*) + +val _ = Define ` + ((Zeros__0:'N itself -> 'N words$word) N= + (let N = (size_itself_int N) in + (replicate_bits (vec_of_bits [B0] : 1 words$word) N : 'N words$word)))`; + + +val _ = Define ` + ((Zeros__1:int -> unit -> 'N words$word) (N__tv : int) () = ((Zeros__0 ((make_the_value N__tv : 'N itself)) : 'N words$word)))`; + + +(*val __ResetMemoryState : unit -> M unit*) + +val _ = Define ` + ((ResetMemoryState:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS Memory_ref : ( 52 words$word) M) (\ (w__0 : 52 words$word) . + let (_ : unit) = + (InitRAM (( 52 : int):ii) (( 1 : int):ii) w__0 ((Zeros__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word))) in + sail2_state_monad$write_regS ExclusiveLocal_ref F)))`; + + +(*val ZeroExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*) + +(*val ZeroExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +val _ = Define ` + ((ZeroExtend__0:'M words$word -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N= + (let N = (size_itself_int N) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((N >= ((int_of_num (words$word_len x))))) "") (sail2_state_monad$returnS ((extzv N x : 'N words$word)))))`; + + +val _ = Define ` + ((ZeroExtend__1:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x= + ((ZeroExtend__0 x ((make_the_value N__tv : 'N itself)) : ( 'N words$word) M)))`; + + +(*val aset_Vpart : forall 'width . Size 'width => ii -> ii -> mword 'width -> M unit*) + +val _ = Define ` + ((aset_Vpart:int -> int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n part value_name= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((part = (( 0 : int):ii)))) \/ (((part = (( 1 : int):ii))))))) "((part == 0) || (part == 1))")) + (if (((part = (( 0 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 8 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))") + (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 words$word) list) . sail2_state_monad$bindS + (ZeroExtend__1 (( 128 : int):ii) value_name : ( 128 words$word) M) (\ (w__1 : 128 bits) . + sail2_state_monad$write_regS V_ref ((update_list_dec w__0 n w__1 : ( 128 words$word) list)))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii)))) "(width == 64)") + (sail2_state_monad$read_regS V_ref)) (\ (w__2 : ( 128 bits) list) . + let (tmp_2870 : 128 bits) = ((access_list_dec w__2 n : 128 words$word)) in + let tmp_2870 = + ((update_subrange_vec_dec tmp_2870 (( 127 : int):ii) (( 64 : int):ii) + ((subrange_vec_dec value_name (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS V_ref) (\ (w__3 : ( 128 words$word) list) . + sail2_state_monad$write_regS V_ref ((update_list_dec w__3 n tmp_2870 : ( 128 words$word) list)))))))`; + + +(*val aset_V : forall 'width . Size 'width => ii -> mword 'width -> M unit*) + +val _ = Define ` + ((aset_V:int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 8 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ ((((((((int_of_num (words$word_len value_name))) = (( 64 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 128 : int):ii)))))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))")) + (sail2_state_monad$read_regS V_ref)) (\ (w__0 : ( 128 words$word) list) . sail2_state_monad$bindS + (ZeroExtend__1 (( 128 : int):ii) value_name : ( 128 words$word) M) (\ (w__1 : 128 bits) . + sail2_state_monad$write_regS V_ref ((update_list_dec w__0 n w__1 : ( 128 words$word) list))))))`; + + +(*val AArch64_ResetSIMDFPRegisters : unit -> M unit*) + +val _ = Define ` + ((AArch64_ResetSIMDFPRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . aset_V i w__0))))`; + + +(*val aset_SP : forall 'width . Size 'width => mword 'width -> M unit*) + +val _ = Define ` + ((aset_SP:'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))) "((width == 32) || (width == 64))") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . + if (((w__0.ProcState_SP = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) value_name : ( 64 words$word) M) (\ (w__1 : 64 bits) . + sail2_state_monad$write_regS SP_EL0_ref w__1) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__299 = (w__2.ProcState_EL) in + let pat_0 = p__299 in + if (((pat_0 = EL0))) then sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) value_name : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$write_regS SP_EL0_ref w__3) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) value_name : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$write_regS SP_EL1_ref w__4) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) value_name : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$write_regS SP_EL2_ref w__5) + else sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) value_name : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$write_regS SP_EL3_ref w__6)))))`; + + +(*val LSR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +val _ = Define ` + ((LSR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)") + (let (result : 'N bits) = ((shiftr x shift : 'N words$word)) in + let (carry_out : 1 bits) = + (if ((shift > ((int_of_num (words$word_len result))))) then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [access_vec_dec x ((shift - (( 1 : int):ii)))] : 1 words$word)) in + sail2_state_monad$returnS (result, carry_out))))`; + + +(*val LSR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +val _ = Define ` + ((LSR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)") + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M)) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len x))) : ( 'N words$word) M) (\ (result : 'N bits) . + if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x + else sail2_state_monad$bindS + (LSR_C x shift : (( 'N words$word # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let (result : 'N bits) = tup__0 in + let (anon10 : 1 bits) = tup__1 in + sail2_state_monad$returnS result)))))`; + + +(*val Poly32Mod2 : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword ty32)*) + +val _ = Define ` + ((Poly32Mod2:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data__arg poly= + (let data = data__arg in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((int_of_num (words$word_len data))) > (( 32 : int):ii))) "(N > 32)") + (let (poly' : 'N bits) = ((extzv ((int_of_num (words$word_len data))) poly : 'N words$word)) in + let (data : 'N words$word) = + (foreach (index_list ((((int_of_num (words$word_len data))) - (( 1 : int):ii))) (( 32 : int):ii) (~ (( 1 : int):ii))) data + (\ i data . + if ((((vec_of_bits [access_vec_dec data i] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (or_vec data ((sub_vec_int ((shiftl poly' i : 'N words$word)) (( 32 : int):ii) : 'N words$word)) + : 'N words$word) + else data)) in + sail2_state_monad$returnS ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)))))`; + + +(*val LSL_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +val _ = Define ` + ((LSL_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)") + (let (result : 'N bits) = ((shiftl x shift : 'N words$word)) in + let (carry_out : 1 bits) = + (if ((shift > ((int_of_num (words$word_len result))))) then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [access_vec_dec x ((((int_of_num (words$word_len result))) - shift))] : 1 words$word)) in + sail2_state_monad$returnS (result, carry_out))))`; + + +(*val LSL : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +val _ = Define ` + ((LSL:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)") + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M)) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len x))) : ( 'N words$word) M) (\ (result : 'N bits) . + if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x + else sail2_state_monad$bindS + (LSL_C x shift : (( 'N words$word # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let (result : 'N bits) = tup__0 in + let (anon10 : 1 bits) = tup__1 in + sail2_state_monad$returnS result)))))`; + + +(*val AArch32_ITAdvance : unit -> M unit*) + +val _ = Define ` + ((AArch32_ITAdvance:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + if (((((slice w__0.ProcState_IT (( 0 : int):ii) (( 3 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__1 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let (tmp_2760 : 8 bits) = (w__2.ProcState_IT) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$bindS + (LSL ((slice w__3.ProcState_IT (( 0 : int):ii) (( 5 : int):ii) : 5 words$word)) (( 1 : int):ii) : ( 5 words$word) M) (\ (w__4 : + 5 words$word) . + let tmp_2760 = ((set_slice (( 8 : int):ii) (( 5 : int):ii) tmp_2760 (( 0 : int):ii) w__4 : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_IT := tmp_2760|>))))))))`; + + +(*val LSInstructionSyndrome : unit -> M (mword ty11)*) + +val _ = Define ` + ((LSInstructionSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->((((11)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") + (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 11 : int):ii) : 11 itself)) : 11 words$word)))))`; + + +(*val IsZero : forall 'N . Size 'N => mword 'N -> bool*) + +val _ = Define ` + ((IsZero:'N words$word -> bool) x= (x = ((Zeros__0 ((make_the_value ((int_of_num (words$word_len x))) : 'N itself)) : 'N words$word))))`; + + +(*val IsZeroBit : forall 'N . Size 'N => mword 'N -> mword ty1*) + +val _ = Define ` + ((IsZeroBit:'N words$word ->(1)words$word) x= + (if ((IsZero x)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val AddWithCarry : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty1 -> (mword 'N * mword ty4)*) + +val _ = Define ` + ((AddWithCarry:'N words$word -> 'N words$word ->(1)words$word -> 'N words$word#(4)words$word) x y carry_in= + (let (unsigned_sum : ii) = (((((lem$w2ui x)) + ((lem$w2ui y)))) + ((lem$w2ui carry_in))) in + let (signed_sum : ii) = (((((integer_word$w2i x)) + ((integer_word$w2i y)))) + ((lem$w2ui carry_in))) in + let (result : 'N bits) = + ((GetSlice_int ((make_the_value ((int_of_num (words$word_len x))) : 'N itself)) unsigned_sum (( 0 : int):ii) : 'N words$word)) in + let (n : 1 bits) = + ((vec_of_bits [access_vec_dec result ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))] : 1 words$word)) in + let (z : 1 bits) = + (if ((IsZero result)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in + let (c : 1 bits) = + (if (((((lem$w2ui result)) = ((ex_int unsigned_sum))))) then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + let (v : 1 bits) = + (if (((((integer_word$w2i result)) = ((ex_int signed_sum))))) then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + (result, + (concat_vec ((concat_vec ((concat_vec n z : 2 words$word)) c : 3 words$word)) v : 4 words$word))))`; + + +(*val GetPSRFromPSTATE : unit -> M (mword ty32)*) + +val _ = Define ` + ((GetPSRFromPSTATE:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (let (spsr : 32 bits) = ((Zeros__1 (( 32 : int):ii) () : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 31 : int):ii) (( 31 : int):ii) w__0.ProcState_N : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 30 : int):ii) (( 30 : int):ii) w__1.ProcState_Z : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 29 : int):ii) (( 29 : int):ii) w__2.ProcState_C : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 28 : int):ii) (( 28 : int):ii) w__3.ProcState_V : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 21 : int):ii) (( 21 : int):ii) w__4.ProcState_SS : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 20 : int):ii) (( 20 : int):ii) w__5.ProcState_IL : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + if (((w__6.ProcState_nRW = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 27 : int):ii) (( 27 : int):ii) w__7.ProcState_Q : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + let spsr = + ((update_subrange_vec_dec spsr (( 26 : int):ii) (( 25 : int):ii) + ((subrange_vec_dec w__8.ProcState_IT (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 19 : int):ii) (( 16 : int):ii) w__9.ProcState_GE : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + let spsr = + ((update_subrange_vec_dec spsr (( 15 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec w__10.ProcState_IT (( 7 : int):ii) (( 2 : int):ii) : 6 words$word)) + : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 9 : int):ii) (( 9 : int):ii) w__11.ProcState_E : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 8 : int):ii) (( 8 : int):ii) w__12.ProcState_A : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 7 : int):ii) (( 7 : int):ii) w__13.ProcState_I : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 6 : int):ii) (( 6 : int):ii) w__14.ProcState_F : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 5 : int):ii) (( 5 : int):ii) w__15.ProcState_T : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((vec_of_bits [access_vec_dec w__16.ProcState_M (( 4 : int):ii)] : 1 words$word) = w__17.ProcState_nRW))) "(((PSTATE).M)<4> == (PSTATE).nRW)") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . + let (spsr : 32 bits) = + ((update_subrange_vec_dec spsr (( 4 : int):ii) (( 0 : int):ii) w__18.ProcState_M : 32 words$word)) in + sail2_state_monad$returnS spsr)))))))))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 9 : int):ii) (( 9 : int):ii) w__19.ProcState_D : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 8 : int):ii) (( 8 : int):ii) w__20.ProcState_A : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 7 : int):ii) (( 7 : int):ii) w__21.ProcState_I : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 6 : int):ii) (( 6 : int):ii) w__22.ProcState_F : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__23 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 4 : int):ii) (( 4 : int):ii) w__23.ProcState_nRW : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) . + let spsr = ((update_subrange_vec_dec spsr (( 3 : int):ii) (( 2 : int):ii) w__24.ProcState_EL : 32 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__25 : ProcState) . + let (spsr : 32 bits) = + ((update_subrange_vec_dec spsr (( 0 : int):ii) (( 0 : int):ii) w__25.ProcState_SP : 32 words$word)) in + sail2_state_monad$returnS spsr))))))))))))))))`; + + +(*val FPZero : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +val _ = Define ` + ((FPZero:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign= + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in + let (exp : 5 bits) = ((Zeros__0 ((make_the_value (( 5 : int):ii) : 5 itself)) : 5 words$word)) in + let (frac : 10 bits) = ((Zeros__0 ((make_the_value F1 : 10 itself)) : 10 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 6 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in + let (exp : 8 bits) = ((Zeros__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) in + let (frac : 23 bits) = ((Zeros__0 ((make_the_value F1 : 23 itself)) : 23 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 9 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in + let (exp : 11 bits) = ((Zeros__0 ((make_the_value (( 11 : int):ii) : 11 itself)) : 11 words$word)) in + let (frac : 52 bits) = ((Zeros__0 ((make_the_value F1 : 52 itself)) : 52 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 12 words$word)) frac : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val ExceptionSyndrome : Exception -> M ExceptionRecord*) + +val _ = Define ` + ((ExceptionSyndrome:Exception ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ= (sail2_state_monad$bindS + (undefined_ExceptionRecord () ) (\ (r : ExceptionRecord) . + let (r : ExceptionRecord) = ((r with<| ExceptionRecord_typ := typ|>)) in + let (r : ExceptionRecord) = + ((r with<| ExceptionRecord_syndrome := ((Zeros__1 (( 25 : int):ii) () : 25 words$word))|>)) in + let (r : ExceptionRecord) = + ((r with<| ExceptionRecord_vaddress := ((Zeros__1 (( 64 : int):ii) () : 64 words$word))|>)) in + let (r : ExceptionRecord) = ((r with<| ExceptionRecord_ipavalid := F|>)) in + let (r : ExceptionRecord) = + ((r with<| ExceptionRecord_ipaddress := ((Zeros__1 (( 52 : int):ii) () : 52 words$word))|>)) in + sail2_state_monad$returnS r)))`; + + +(*val ConstrainUnpredictableBits : forall 'width . Size 'width => integer -> Unpredictable -> M (Constraint * mword 'width)*) + +val _ = Define ` + ((ConstrainUnpredictableBits:int -> Unpredictable ->(regstate)sail2_state_monad$sequential_state ->(((Constraint#'width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) which= + (let (c : Constraint) = (ConstrainUnpredictable which) in + if (((c = Constraint_UNKNOWN))) then + sail2_state_monad$returnS (c, (Zeros__0 ((make_the_value width__tv : 'width itself)) : 'width words$word)) + else sail2_state_monad$bindS + (undefined_bitvector width__tv : ( 'width words$word) M) (\ (w__0 : 'width words$word) . + sail2_state_monad$returnS (c, w__0))))`; + + +(*val AArch64_SysInstrWithResult : ii -> ii -> ii -> ii -> ii -> M (mword ty64)*) + +val _ = Define ` + ((AArch64_SysInstrWithResult:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") + (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 64 : int):ii) : 64 itself)) : 64 words$word)))))`; + + +(*val AArch64_PhysicalSErrorSyndrome : bool -> M (mword ty25)*) + +val _ = Define ` + ((AArch64_PhysicalSErrorSyndrome:bool ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) implicit_esb= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") + (sail2_state_monad$returnS ((Zeros__0 ((make_the_value (( 25 : int):ii) : 25 itself)) : 25 words$word)))))`; + + +(*val AArch32_PhysicalSErrorSyndrome : unit -> M AArch32_SErrorSyndrome*) + +val _ = Define ` + ((AArch32_PhysicalSErrorSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->(((AArch32_SErrorSyndrome),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS F "FALSE") + (undefined_AArch32_SErrorSyndrome () )) (\ (r : AArch32_SErrorSyndrome) . + let (r : AArch32_SErrorSyndrome) = + ((r with<| + AArch32_SErrorSyndrome_AET := + ((Zeros__0 ((make_the_value (( 2 : int):ii) : 2 itself)) : 2 words$word))|>)) in + let (r : AArch32_SErrorSyndrome) = + ((r with<| + AArch32_SErrorSyndrome_ExT := + ((Zeros__0 ((make_the_value (( 1 : int):ii) : 1 itself)) : 1 words$word))|>)) in + sail2_state_monad$returnS r)))`; + + +(*val VFPExpandImm : forall 'N . Size 'N => integer -> mword ty8 -> M (mword 'N)*) + +val _ = Define ` + ((VFPExpandImm:int ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) imm8= + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)] : 1 words$word)) in + let (exp : 5 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) : 1 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) + (((( 5 : int):ii) - (( 3 : int):ii))) + : 2 words$word)) + : 3 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) + : 5 words$word)) in + let (frac : 10 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii))) : 6 itself)) : 6 words$word)) + : 10 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 6 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)] : 1 words$word)) in + let (exp : 8 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) : 1 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) + (((( 8 : int):ii) - (( 3 : int):ii))) + : 5 words$word)) + : 6 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) + : 8 words$word)) in + let (frac : 23 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii))) : 19 itself)) : 19 words$word)) + : 23 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 9 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 : int):ii)] : 1 words$word)) in + let (exp : 11 bits) = + ((concat_vec + ((concat_vec + ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) : 1 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec imm8 (( 6 : int):ii)] : 1 words$word) + (((( 11 : int):ii) - (( 3 : int):ii))) + : 8 words$word)) + : 9 words$word)) ((subrange_vec_dec imm8 (( 5 : int):ii) (( 4 : int):ii) : 2 words$word)) + : 11 words$word)) in + let (frac : 52 bits) = + ((concat_vec ((subrange_vec_dec imm8 (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + ((Zeros__0 ((make_the_value ((F1 - (( 4 : int):ii))) : 48 itself)) : 48 words$word)) + : 52 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 12 words$word)) frac : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val SignExtend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> M (mword 'N)*) + +(*val SignExtend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> M (mword 'N)*) + +val _ = Define ` + ((SignExtend__0:'M words$word -> 'N itself ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N= + (let N = (size_itself_int N) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((N >= ((int_of_num (words$word_len x))))) "") (sail2_state_monad$returnS ((extsv N x : 'N words$word)))))`; + + +val _ = Define ` + ((SignExtend__1:int -> 'M words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x= + ((SignExtend__0 x ((make_the_value N__tv : 'N itself)) : ( 'N words$word) M)))`; + + +(*val Extend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> bool -> M (mword 'N)*) + +(*val Extend__1 : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> bool -> M (mword 'N)*) + +val _ = Define ` + ((Extend__0:'M words$word -> 'N itself -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x N unsigned= + (let N = (size_itself_int N) in + if unsigned then (ZeroExtend__0 x ((make_the_value N : 'N itself)) : ( 'N words$word) M) + else (SignExtend__0 x ((make_the_value N : 'N itself)) : ( 'N words$word) M)))`; + + +val _ = Define ` + ((Extend__1:int -> 'M words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) x unsigned= + ((Extend__0 x ((make_the_value N__tv : 'N itself)) unsigned : ( 'N words$word) M)))`; + + +(*val ASR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +val _ = Define ` + ((ASR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift > (( 0 : int):ii))) "(shift > 0)") + (let (result : 'N bits) = ((arith_shiftr x shift : 'N words$word)) in + let (carry_out : 1 bits) = + (if ((shift > ((int_of_num (words$word_len result))))) then + (vec_of_bits [access_vec_dec x ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))] : 1 words$word) + else (vec_of_bits [access_vec_dec x ((shift - (( 1 : int):ii)))] : 1 words$word)) in + sail2_state_monad$returnS (result, carry_out))))`; + + +(*val ASR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +val _ = Define ` + ((ASR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)") + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M)) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len x))) : ( 'N words$word) M) (\ (result : 'N bits) . + if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x + else sail2_state_monad$bindS + (ASR_C x shift : (( 'N words$word # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let (result : 'N bits) = tup__0 in + let (anon10 : 1 bits) = tup__1 in + sail2_state_monad$returnS result)))))`; + + +(*val Ones__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) + +(*val Ones__1 : forall 'N . Size 'N => integer -> unit -> mword 'N*) + +val _ = Define ` + ((Ones__0:'N itself -> 'N words$word) N= + (let N = (size_itself_int N) in + (replicate_bits (vec_of_bits [B1] : 1 words$word) N : 'N words$word)))`; + + +val _ = Define ` + ((Ones__1:int -> unit -> 'N words$word) (N__tv : int) () = ((Ones__0 ((make_the_value N__tv : 'N itself)) : 'N words$word)))`; + + +(*val IsOnes : forall 'N . Size 'N => mword 'N -> bool*) + +val _ = Define ` + ((IsOnes:'N words$word -> bool) x= (x = ((Ones__0 ((make_the_value ((int_of_num (words$word_len x))) : 'N itself)) : 'N words$word))))`; + + +(*val FPMaxNormal : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +val _ = Define ` + ((FPMaxNormal:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign= + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in + let (exp : 5 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 5 : int):ii) - (( 1 : int):ii))) : 4 itself)) : 4 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 5 words$word)) in + let (frac : 10 bits) = ((Ones__0 ((make_the_value F1 : 10 itself)) : 10 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 6 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in + let (exp : 8 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 8 : int):ii) - (( 1 : int):ii))) : 7 itself)) : 7 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 8 words$word)) in + let (frac : 23 bits) = ((Ones__0 ((make_the_value F1 : 23 itself)) : 23 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 9 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in + let (exp : 11 bits) = + ((concat_vec + ((Ones__0 ((make_the_value (((( 11 : int):ii) - (( 1 : int):ii))) : 10 itself)) : 10 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 11 words$word)) in + let (frac : 52 bits) = ((Ones__0 ((make_the_value F1 : 52 itself)) : 52 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 12 words$word)) frac : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val FPInfinity : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) + +val _ = Define ` + ((FPInfinity:int ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) sign= + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in + let (exp : 5 bits) = ((Ones__0 ((make_the_value (( 5 : int):ii) : 5 itself)) : 5 words$word)) in + let (frac : 10 bits) = ((Zeros__0 ((make_the_value F1 : 10 itself)) : 10 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 6 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in + let (exp : 8 bits) = ((Ones__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) in + let (frac : 23 bits) = ((Zeros__0 ((make_the_value F1 : 23 itself)) : 23 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 9 words$word)) frac : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in + let (exp : 11 bits) = ((Ones__0 ((make_the_value (( 11 : int):ii) : 11 itself)) : 11 words$word)) in + let (frac : 52 bits) = ((Zeros__0 ((make_the_value F1 : 52 itself)) : 52 words$word)) in + sail2_state_monad$returnS ((words$w2w ((concat_vec ((concat_vec sign exp : 12 words$word)) frac : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val FPDefaultNaN : forall 'N . Size 'N => integer -> unit -> M (mword 'N)*) + +val _ = Define ` + ((FPDefaultNaN:int -> unit ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) () = + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 16 : int):ii) - (( 5 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (exp : 5 bits) = ((Ones__0 ((make_the_value (( 5 : int):ii) : 5 itself)) : 5 words$word)) in + let (frac : 10 bits) = + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii))) : 9 itself)) : 9 words$word)) + : 10 words$word)) in + sail2_state_monad$returnS ((words$w2w + ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) exp : 6 words$word)) frac + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 32 : int):ii) - (( 8 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (exp : 8 bits) = ((Ones__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) in + let (frac : 23 bits) = + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii))) : 22 itself)) : 22 words$word)) + : 23 words$word)) in + sail2_state_monad$returnS ((words$w2w + ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) exp : 9 words$word)) frac + : 'N words$word)) + : 'N words$word))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "((N == 16) || ((N == 32) || (N == 64)))") + (let (F1 : int) = ((((( 64 : int):ii) - (( 11 : int):ii))) - (( 1 : int):ii)) in + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (exp : 11 bits) = ((Ones__0 ((make_the_value (( 11 : int):ii) : 11 itself)) : 11 words$word)) in + let (frac : 52 bits) = + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((Zeros__0 ((make_the_value ((F1 - (( 1 : int):ii))) : 51 itself)) : 51 words$word)) + : 52 words$word)) in + sail2_state_monad$returnS ((words$w2w + ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) exp : 12 words$word)) frac + : 'N words$word)) + : 'N words$word))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "((N == 16) || ((N == 32) || (N == 64)))") (sail2_state_monad$exitS () )))`; + + +(*val FPConvertNaN : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> M (mword 'M)*) + +val _ = Define ` + ((FPConvertNaN:int -> 'N words$word ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$assert_expS ((((((M__tv = (( 16 : int):ii)))) \/ ((((((M__tv = (( 32 : int):ii)))) \/ (((M__tv = (( 64 : int):ii)))))))))) "((M == 16) || ((M == 32) || (M == 64)))")) + (undefined_bitvector M__tv : ( 'M words$word) M)) (\ (result : 'M bits) . sail2_state_monad$bindS + (undefined_bitvector (( 51 : int):ii) : ( 51 words$word) M) (\ (frac : 51 bits) . + let (sign : 1 bits) = + ((vec_of_bits [access_vec_dec op ((((int_of_num (words$word_len op))) - (( 1 : int):ii)))] : 1 words$word)) in + let p0_ = (int_of_num (words$word_len op)) in + let (frac : 51 bits) = + (if (((p0_ = (( 64 : int):ii)))) then + let (op : 64 words$word) = ((words$w2w op : 64 words$word)) in + (slice op (( 0 : int):ii) (( 51 : int):ii) : 51 words$word) + else if (((p0_ = (( 32 : int):ii)))) then + let (op : 32 words$word) = ((words$w2w op : 32 words$word)) in + (concat_vec ((slice op (( 0 : int):ii) (( 22 : int):ii) : 22 words$word)) + ((Zeros__0 ((make_the_value (( 29 : int):ii) : 29 itself)) : 29 words$word)) + : 51 words$word) + else + let (op : 16 words$word) = ((words$w2w op : 16 words$word)) in + (concat_vec ((slice op (( 0 : int):ii) (( 9 : int):ii) : 9 words$word)) + ((Zeros__0 ((make_the_value (( 42 : int):ii) : 42 itself)) : 42 words$word)) + : 51 words$word)) in + let p0_ = (int_of_num (words$word_len result)) in + let (result : 'M bits) = + (if (((p0_ = (( 64 : int):ii)))) then + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 : int):ii) - (( 52 : int):ii))) )) : 12 words$word)) + : 13 words$word)) frac + : 'M words$word) + else if (((p0_ = (( 32 : int):ii)))) then + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 : int):ii) - (( 23 : int):ii))) )) : 9 words$word)) + : 10 words$word)) ((slice frac (( 29 : int):ii) (( 22 : int):ii) : 22 words$word)) + : 'M words$word) + else + (concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value ((p0_ - (( 10 : int):ii))) )) : 6 words$word)) + : 7 words$word)) ((slice frac (( 42 : int):ii) (( 9 : int):ii) : 9 words$word)) + : 'M words$word)) in + sail2_state_monad$returnS result))))`; + + +(*val ExcVectorBase : unit -> M (mword ty32)*) + +val _ = Define ` + ((ExcVectorBase:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__0 (( 13 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + sail2_state_monad$returnS ((concat_vec ((Ones__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + ((Zeros__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + : 32 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS VBAR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((concat_vec ((slice w__1 (( 5 : int):ii) (( 27 : int):ii) : 27 words$word)) + ((Zeros__0 ((make_the_value (( 5 : int):ii) : 5 itself)) : 5 words$word)) + : 32 words$word))))))`; + + +(*val PACSub : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((PACSub:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Tinput= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (Toutput : 64 bits) . + let (Toutput : 64 bits) = + (foreach (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) Toutput + (\ i Toutput . + let b__0 = ((slice Tinput (((( 4 : int):ii) * i)) (( 4 : int):ii) : 4 words$word)) in + if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + : 64 words$word) + else + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B1;B0] : 4 words$word) + : 64 words$word))) in + sail2_state_monad$returnS Toutput)))`; + + +(*val PACMult : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((PACMult:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Sinput= (sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (t0 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (t1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (t2 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (t3 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (Soutput : 64 bits) . sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 3 : int):ii) (( 1 : int):ii)) (Soutput, t0, t1, t2, t3) + (\ i varstup . let (Soutput, t0, t1, t2, t3) = varstup in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__0 : 4 words$word) . sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 2 : int):ii) + : ( 4 words$word) M) (\ (w__1 : 4 words$word) . + let t0 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t0 (( 0 : int):ii) ((xor_vec w__0 w__1 : 4 words$word)) : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii) : 4 words$word)) (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__2 : 4 words$word) . + let t0 = + ((set_slice (( 4 : int):ii) (( 4 : int):ii) t0 (( 0 : int):ii) + ((xor_vec ((slice t0 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) w__2 : 4 words$word)) + : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__3 : 4 words$word) . sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__4 : 4 words$word) . + let t1 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t1 (( 0 : int):ii) ((xor_vec w__3 w__4 : 4 words$word)) : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii) : 4 words$word)) (( 2 : int):ii) + : ( 4 words$word) M) (\ (w__5 : 4 words$word) . + let t1 = + ((set_slice (( 4 : int):ii) (( 4 : int):ii) t1 (( 0 : int):ii) + ((xor_vec ((slice t1 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) w__5 : 4 words$word)) + : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 2 : int):ii) + : ( 4 words$word) M) (\ (w__6 : 4 words$word) . sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__7 : 4 words$word) . + let t2 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t2 (( 0 : int):ii) ((xor_vec w__6 w__7 : 4 words$word)) : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * i)) (( 4 : int):ii) : 4 words$word)) (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__8 : 4 words$word) . + let t2 = + ((set_slice (( 4 : int):ii) (( 4 : int):ii) t2 (( 0 : int):ii) + ((xor_vec ((slice t2 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) w__8 : 4 words$word)) + : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__9 : 4 words$word) . sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 2 : int):ii) + : ( 4 words$word) M) (\ (w__10 : 4 words$word) . + let t3 = ((set_slice (( 4 : int):ii) (( 4 : int):ii) t3 (( 0 : int):ii) ((xor_vec w__9 w__10 : 4 words$word)) : 4 words$word)) in sail2_state_monad$bindS + (RotCell ((slice Sinput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) (( 4 : int):ii) : 4 words$word)) + (( 1 : int):ii) + : ( 4 words$word) M) (\ (w__11 : 4 words$word) . + let (t3 : 4 bits) = + ((set_slice (( 4 : int):ii) (( 4 : int):ii) t3 (( 0 : int):ii) + ((xor_vec ((slice t3 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) w__11 : 4 words$word)) + : 4 words$word)) in + let (Soutput : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * i)) + ((slice t3 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (Soutput : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 4 : int):ii))))) + ((slice t2 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (Soutput : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 8 : int):ii))))) + ((slice t1 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + let (Soutput : 64 bits) = + ((set_slice (( 64 : int):ii) (( 4 : int):ii) Soutput (((( 4 : int):ii) * ((i + (( 12 : int):ii))))) + ((slice t0 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS (Soutput, t0, t1, t2, t3))))))))))))))) (\ varstup . let ((Soutput : 64 bits), (t0 : 4 + bits), (t1 : 4 bits), (t2 : 4 bits), (t3 : 4 bits)) = varstup in + sail2_state_monad$returnS Soutput))))))))`; + + +(*val PACInvSub : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((PACInvSub:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Tinput= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (Toutput : 64 bits) . + let (Toutput : 64 bits) = + (foreach (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) Toutput + (\ i Toutput . + let b__0 = ((slice Tinput (((( 4 : int):ii) * i)) (( 4 : int):ii) : 4 words$word)) in + if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B0;B0;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B1;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B1;B1] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B0;B1;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B1] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B1;B1;B0;B0] : 4 words$word) + : 64 words$word) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B0] : 4 words$word)))) then + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B1;B1;B1] : 4 words$word) + : 64 words$word) + else + (set_slice (( 64 : int):ii) (( 4 : int):ii) Toutput (((( 4 : int):ii) * i)) + (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + : 64 words$word))) in + sail2_state_monad$returnS Toutput)))`; + + +(*val ComputePAC : mword ty64 -> mword ty64 -> mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((ComputePAC:(64)words$word ->(64)words$word ->(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) data modifier key0 key1= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (workingval : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (runningmod : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (roundkey : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (modk0 : 64 bits) . sail2_state_monad$bindS + (hex_slice "0xC0AC29B7C97C50DD" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (Alpha : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS RC_ref) (\ (w__0 : ( 64 words$word) list) . sail2_state_monad$bindS + (hex_slice "0x0" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref ((update_list_dec w__0 (( 0 : int):ii) w__1 : ( 64 words$word) list))) + (sail2_state_monad$read_regS RC_ref)) (\ (w__2 : ( 64 words$word) list) . sail2_state_monad$bindS + (hex_slice "0x13198A2E03707344" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref ((update_list_dec w__2 (( 1 : int):ii) w__3 : ( 64 words$word) list))) + (sail2_state_monad$read_regS RC_ref)) (\ (w__4 : ( 64 words$word) list) . sail2_state_monad$bindS + (hex_slice "0xA493822299F31D0" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (w__5 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref ((update_list_dec w__4 (( 2 : int):ii) w__5 : ( 64 words$word) list))) + (sail2_state_monad$read_regS RC_ref)) (\ (w__6 : ( 64 words$word) list) . sail2_state_monad$bindS + (hex_slice "0x82EFA98EC4E6C89" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (w__7 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref ((update_list_dec w__6 (( 3 : int):ii) w__7 : ( 64 words$word) list))) + (sail2_state_monad$read_regS RC_ref)) (\ (w__8 : ( 64 words$word) list) . sail2_state_monad$bindS + (hex_slice "0x452821E638D01377" (( 64 : int):ii) (( 0 : int):ii) : ( 64 words$word) M) (\ (w__9 : 64 words$word) . sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref ((update_list_dec w__8 (( 4 : int):ii) w__9 : ( 64 words$word) list))) + (let modk0 = + ((concat_vec + ((concat_vec (vec_of_bits [access_vec_dec key0 (( 0 : int):ii)] : 1 words$word) + ((slice key0 (( 2 : int):ii) (( 62 : int):ii) : 62 words$word)) + : 63 words$word)) + ((xor_vec (vec_of_bits [access_vec_dec key0 (( 63 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec key0 (( 1 : int):ii)] : 1 words$word) + : 1 words$word)) + : 64 words$word)) in + let runningmod = modifier in + let workingval = ((xor_vec data key0 : 64 words$word)) in sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 4 : int):ii) (( 1 : int):ii)) (roundkey, runningmod, workingval) + (\ i varstup . let (roundkey, runningmod, workingval) = varstup in + let roundkey = ((xor_vec key1 runningmod : 64 words$word)) in + let workingval = ((xor_vec workingval roundkey : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS RC_ref) (\ (w__10 : ( 64 bits) list) . + let workingval = ((xor_vec workingval ((access_list_dec w__10 i : 64 words$word)) : 64 words$word)) in sail2_state_monad$bindS + (if ((i > (( 0 : int):ii))) then sail2_state_monad$bindS + (PACCellShuffle workingval : ( 64 words$word) M) (\ (w__11 : 64 bits) . + let workingval = w__11 in + (PACMult workingval : ( 64 words$word) M)) + else sail2_state_monad$returnS workingval) (\ (workingval : 64 bits) . sail2_state_monad$bindS + (PACSub workingval : ( 64 words$word) M) (\ (w__13 : 64 bits) . + let workingval = w__13 in sail2_state_monad$bindS + (TweakShuffle ((slice runningmod (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) : ( 64 words$word) M) (\ (w__14 : 64 + bits) . + let (runningmod : 64 bits) = w__14 in + sail2_state_monad$returnS (roundkey, runningmod, workingval))))))) (\ varstup . let ((roundkey : 64 bits), (runningmod : 64 + bits), (workingval : 64 bits)) = varstup in + let roundkey = ((xor_vec modk0 runningmod : 64 words$word)) in + let workingval = ((xor_vec workingval roundkey : 64 words$word)) in sail2_state_monad$bindS + (PACCellShuffle workingval : ( 64 words$word) M) (\ (w__15 : 64 bits) . + let workingval = w__15 in sail2_state_monad$bindS + (PACMult workingval : ( 64 words$word) M) (\ (w__16 : 64 bits) . + let workingval = w__16 in sail2_state_monad$bindS + (PACSub workingval : ( 64 words$word) M) (\ (w__17 : 64 bits) . + let workingval = w__17 in sail2_state_monad$bindS + (PACCellShuffle workingval : ( 64 words$word) M) (\ (w__18 : 64 bits) . + let workingval = w__18 in sail2_state_monad$bindS + (PACMult workingval : ( 64 words$word) M) (\ (w__19 : 64 bits) . + let workingval = w__19 in + let workingval = ((xor_vec key1 workingval : 64 words$word)) in sail2_state_monad$bindS + (PACCellInvShuffle workingval : ( 64 words$word) M) (\ (w__20 : 64 bits) . + let workingval = w__20 in sail2_state_monad$bindS + (PACInvSub workingval : ( 64 words$word) M) (\ (w__21 : 64 bits) . + let workingval = w__21 in sail2_state_monad$bindS + (PACMult workingval : ( 64 words$word) M) (\ (w__22 : 64 bits) . + let workingval = w__22 in sail2_state_monad$bindS + (PACCellInvShuffle workingval : ( 64 words$word) M) (\ (w__23 : 64 bits) . + let workingval = w__23 in + let workingval = ((xor_vec workingval key0 : 64 words$word)) in + let workingval = ((xor_vec workingval runningmod : 64 words$word)) in sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 4 : int):ii) (( 1 : int):ii)) (roundkey, runningmod, workingval) + (\ i varstup . let (roundkey, runningmod, workingval) = varstup in sail2_state_monad$bindS + (PACInvSub workingval : ( 64 words$word) M) (\ (w__24 : 64 bits) . + let workingval = w__24 in sail2_state_monad$bindS + (if ((i < (( 4 : int):ii))) then sail2_state_monad$bindS + (PACMult workingval : ( 64 words$word) M) (\ (w__25 : 64 bits) . + let workingval = w__25 in + (PACCellInvShuffle workingval : ( 64 words$word) M)) + else sail2_state_monad$returnS workingval) (\ (workingval : 64 bits) . sail2_state_monad$bindS + (TweakInvShuffle ((slice runningmod (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) : ( 64 words$word) M) (\ (w__27 : 64 + bits) . + let runningmod = w__27 in + let roundkey = ((xor_vec key1 runningmod : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS RC_ref) (\ (w__28 : ( 64 bits) list) . + let (workingval : 64 bits) = + ((xor_vec workingval ((access_list_dec w__28 (((( 4 : int):ii) - i)) : 64 words$word)) + : 64 words$word)) in + let (workingval : 64 bits) = ((xor_vec workingval roundkey : 64 words$word)) in + let (workingval : 64 bits) = ((xor_vec workingval Alpha : 64 words$word)) in + sail2_state_monad$returnS (roundkey, runningmod, workingval))))))) (\ varstup . let ((roundkey : 64 bits), (runningmod : 64 + bits), (workingval : 64 bits)) = varstup in + let (workingval : 64 bits) = ((xor_vec workingval modk0 : 64 words$word)) in + sail2_state_monad$returnS workingval)))))))))))))))))))))))))))))`; + + +(*val Align__0 : ii -> ii -> ii*) + +(*val Align__1 : forall 'N . Size 'N => mword 'N -> ii -> mword 'N*) + +val _ = Define ` + ((Align__0:int -> int -> int) x y= (y * ((x / y))))`; + + +val _ = Define ` + ((Align__1:'N words$word -> int -> 'N words$word) x y= + ((GetSlice_int ((make_the_value ((int_of_num (words$word_len x))) : 'N itself)) ((Align__0 ((lem$w2ui x)) y)) (( 0 : int):ii) + : 'N words$word)))`; + + +(*val aset__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> mword 'p8_times_size_ -> M unit*) + +val _ = Define ` + ((aset__Mem:AddressDescriptor -> int -> AccessDescriptor -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) desc size1 accdesc value_name= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))") + (let (address : 52 bits) = (desc.AddressDescriptor_paddress.FullAddress_physicaladdress) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((address = ((Align__1 address size1 : 52 words$word))))) "(address == Align(address, size))") + (hex_slice "0x13000000" (( 52 : int):ii) (( 0 : int):ii) : ( 52 words$word) M)) (\ (w__0 : 52 words$word) . + if (((address = w__0))) then + if (((((lem$w2ui value_name)) = (( 4 : int):ii)))) then + let (_ : unit) = (prerr "Program exited by writing ^^D to TUBE\n") in + sail2_state_monad$exitS () + else sail2_state_monad$returnS ((putchar ((lem$w2ui ((slice value_name (( 0 : int):ii) (( 8 : int):ii) : 8 words$word)))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS Memory_ref : ( 52 words$word) M) (\ (w__1 : 52 words$word) . + WriteRAM ((make_the_value (( 52 : int):ii) : 52 itself)) size1 w__1 address value_name)))))`; + + +(*val aget__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> M (mword 'p8_times_size_)*) + +val _ = Define ` + ((aget__Mem:AddressDescriptor -> int -> AccessDescriptor ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) desc size1 accdesc= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))") + (let (address : 52 bits) = (desc.AddressDescriptor_paddress.FullAddress_physicaladdress) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((address = ((Align__1 address size1 : 52 words$word))))) "(address == Align(address, size))") + (sail2_state_monad$read_regS Memory_ref : ( 52 words$word) M)) (\ (w__0 : 52 words$word) . + (ReadRAM ((make_the_value (( 52 : int):ii) : 52 itself)) size1 w__0 address + : ( 'p8_times_size_ words$word) M)))))`; + + +(*val aset_X : forall 'width . Size 'width => ii -> mword 'width -> M unit*) + +val _ = Define ` + ((aset_X:int -> 'width words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len value_name))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len value_name))) = (( 64 : int):ii))))))) "((width == 32) || (width == 64))")) + (if (((n <> (( 31 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__0 : ( 64 words$word) list) . sail2_state_monad$bindS + (ZeroExtend__0 value_name ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . + sail2_state_monad$write_regS R_ref ((update_list_dec w__0 n w__1 : ( 64 words$word) list)))) + else sail2_state_monad$returnS () )))`; + + +(*val aarch64_integer_arithmetic_address_pcrel : ii -> mword ty64 -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_address_pcrel:int ->(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d imm page= (sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (base : 64 bits) . + let (base : 64 bits) = + (if page then + (set_slice (( 64 : int):ii) (( 12 : int):ii) base (( 0 : int):ii) + ((Zeros__0 ((make_the_value (( 12 : int):ii) : 12 itself)) : 12 words$word)) + : 64 words$word) + else base) in + aset_X d ((add_vec base imm : 64 words$word)))))`; + + +(*val integer_arithmetic_address_pcrel_decode : mword ty1 -> mword ty2 -> mword ty19 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_address_pcrel_decode:(1)words$word ->(2)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op immlo immhi Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (page : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (imm : 64 bits) . sail2_state_monad$bindS + (if page then + (SignExtend__0 + ((concat_vec ((concat_vec immhi immlo : 21 words$word)) + ((Zeros__0 ((make_the_value (( 12 : int):ii) : 12 itself)) : 12 words$word)) + : 33 words$word)) ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) + else + (SignExtend__0 ((concat_vec immhi immlo : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M)) (\ (imm : 64 bits) . + aarch64_integer_arithmetic_address_pcrel d imm page)))))`; + + +(*val AArch64_ResetGeneralRegisters : unit -> M unit*) + +val _ = Define ` + ((AArch64_ResetGeneralRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 30 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . aset_X i w__0))))`; + + +(*val aset_ELR__0 : mword ty2 -> mword ty64 -> M unit*) + +(*val aset_ELR__1 : mword ty64 -> M unit*) + +val _ = Define ` + ((aset_ELR__0:(2)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el value_name= + (let (r : 64 bits) = value_name in + let pat_0 = el in + if (((pat_0 = EL1))) then sail2_state_monad$write_regS ELR_EL1_ref r + else if (((pat_0 = EL2))) then sail2_state_monad$write_regS ELR_EL2_ref r + else if (((pat_0 = EL3))) then sail2_state_monad$write_regS ELR_EL3_ref r + else Unreachable () ))`; + + +val _ = Define ` + ((aset_ELR__1:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL0))) "") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . aset_ELR__0 w__1.ProcState_EL value_name))))`; + + +(*val aget_X : forall 'width . Size 'width => integer -> ii -> M (mword 'width)*) + +val _ = Define ` + ((aget_X:int -> int ->(regstate)sail2_state_monad$sequential_state ->((('width words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (width__tv : int) n= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 31 : int):ii)))))) "((n >= 0) && (n <= 31))") + (sail2_state_monad$assert_expS ((((((width__tv = (( 8 : int):ii)))) \/ ((((((width__tv = (( 16 : int):ii)))) \/ ((((((width__tv = (( 32 : int):ii)))) \/ (((width__tv = (( 64 : int):ii))))))))))))) "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))")) + (if (((n <> (( 31 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__0 : ( 64 bits) list) . + sail2_state_monad$returnS ((slice ((access_list_dec w__0 n : 64 words$word)) (( 0 : int):ii) width__tv : 'width words$word))) + else sail2_state_monad$returnS ((Zeros__0 ((make_the_value width__tv : 'width itself)) : 'width words$word)))))`; + + +(*val aarch64_system_sysops : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_system_sysops:bool -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t= + (if has_result then sail2_state_monad$bindS + (AArch64_SysInstrWithResult sys_op0 sys_op1 sys_crn sys_crm sys_op2 : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . + aset_X t w__0) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + AArch64_SysInstr sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1)))`; + + +(*val aarch64_system_register_system : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_system_register_system:bool -> int -> int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t= + (if read then sail2_state_monad$bindS + (AArch64_SysRegRead sys_op0 sys_op1 sys_crn sys_crm sys_op2 : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . + aset_X t w__0) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + AArch64_SysRegWrite sys_op0 sys_op1 sys_crn sys_crm sys_op2 w__1)))`; + + +(*val aarch64_integer_insext_insert_movewide : ii -> ii -> mword ty16 -> MoveWideOp -> ii -> M unit*) + +val _ = Define ` + ((aarch64_integer_insext_insert_movewide:int -> int ->(16)words$word -> MoveWideOp -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__267 imm opcode pos= + (if (((l__267 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (if (((opcode = MoveWideOp_K))) then (aget_X (( 8 : int):ii) d : ( 8 words$word) M) + else + let (result : 8 bits) = ((Zeros__1 (( 8 : int):ii) () : 8 words$word)) in + sail2_state_monad$returnS result) (\ (result : 8 bits) . + let result = ((set_slice (( 8 : int):ii) (( 16 : int):ii) result pos imm : 8 words$word)) in + let (result : 8 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result : 8 words$word) + else result) in + aset_X d result)) + else if (((l__267 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (if (((opcode = MoveWideOp_K))) then (aget_X (( 16 : int):ii) d : ( 16 words$word) M) + else + let (result : 16 bits) = ((Zeros__1 (( 16 : int):ii) () : 16 words$word)) in + sail2_state_monad$returnS result) (\ (result : 16 bits) . + let result = ((set_slice (( 16 : int):ii) (( 16 : int):ii) result pos imm : 16 words$word)) in + let (result : 16 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result : 16 words$word) + else result) in + aset_X d result)) + else if (((l__267 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (if (((opcode = MoveWideOp_K))) then (aget_X (( 32 : int):ii) d : ( 32 words$word) M) + else + let (result : 32 bits) = ((Zeros__1 (( 32 : int):ii) () : 32 words$word)) in + sail2_state_monad$returnS result) (\ (result : 32 bits) . + let result = ((set_slice (( 32 : int):ii) (( 16 : int):ii) result pos imm : 32 words$word)) in + let (result : 32 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result : 32 words$word) + else result) in + aset_X d result)) + else if (((l__267 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (if (((opcode = MoveWideOp_K))) then (aget_X (( 64 : int):ii) d : ( 64 words$word) M) + else + let (result : 64 bits) = ((Zeros__1 (( 64 : int):ii) () : 64 words$word)) in + sail2_state_monad$returnS result) (\ (result : 64 bits) . + let result = ((set_slice (( 64 : int):ii) (( 16 : int):ii) result pos imm : 64 words$word)) in + let (result : 64 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result : 64 words$word) + else result) in + aset_X d result)) + else if (((l__267 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (if (((opcode = MoveWideOp_K))) then (aget_X (( 128 : int):ii) d : ( 128 words$word) M) + else + let (result : 128 bits) = ((Zeros__1 (( 128 : int):ii) () : 128 words$word)) in + sail2_state_monad$returnS result) (\ (result : 128 bits) . + let result = ((set_slice (( 128 : int):ii) (( 16 : int):ii) result pos imm : 128 words$word)) in + let (result : 128 bits) = + (if (((opcode = MoveWideOp_N))) then (not_vec result : 128 words$word) + else result) in + aset_X d result)) + else + let dbytes = (ex_int ((l__267 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_integer_insext_extract_immediate : ii -> ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_integer_insext_extract_immediate:int -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__262 lsb m n= + (if (((l__262 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . + let (concat1 : 16 bits) = ((concat_vec operand1 operand2 : 16 words$word)) in + let result = ((slice concat1 lsb (( 8 : int):ii) : 8 words$word)) in + aset_X d result))) + else if (((l__262 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . + let (concat1 : 32 bits) = ((concat_vec operand1 operand2 : 32 words$word)) in + let result = ((slice concat1 lsb (( 16 : int):ii) : 16 words$word)) in + aset_X d result))) + else if (((l__262 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . + let (concat1 : 64 bits) = ((concat_vec operand1 operand2 : 64 words$word)) in + let result = ((slice concat1 lsb (( 32 : int):ii) : 32 words$word)) in + aset_X d result))) + else if (((l__262 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . + let (concat1 : 128 bits) = ((concat_vec operand1 operand2 : 128 words$word)) in + let result = ((slice concat1 lsb (( 64 : int):ii) : 64 words$word)) in + aset_X d result))) + else if (((l__262 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . + let (concat1 : 256 bits) = ((concat_vec operand1 operand2 : 256 words$word)) in + let result = ((slice concat1 lsb (( 128 : int):ii) : 128 words$word)) in + aset_X d result))) + else + let dbytes = (ex_int ((l__262 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_integer_arithmetic_rev : ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_rev:int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) container_size d l__257 n= + (if (((l__257 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (result : 8 bits) . + let (containers : ii) = ((( 8 : int):ii) / container_size) in + let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in + let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rev_index : ii) . + let ((index : ii), (result : 8 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ c varstup . let (index, result, rev_index) = varstup in + let (rev_index : ii) = + (((ex_int index)) + + ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in + let ((index : ii), (result : 8 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ e varstup . let (index, result, rev_index) = varstup in + let (result : 8 bits) = + ((set_slice (( 8 : int):ii) (( 8 : int):ii) result rev_index + ((slice operand index (( 8 : int):ii) : 8 words$word)) + : 8 words$word)) in + let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in + let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in + (index, result, rev_index))) in + (index, result, rev_index))) in + aset_X d result))) + else if (((l__257 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (result : 16 bits) . + let (containers : ii) = ((( 16 : int):ii) / container_size) in + let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in + let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rev_index : ii) . + let ((index : ii), (result : 16 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ c varstup . let (index, result, rev_index) = varstup in + let (rev_index : ii) = + (((ex_int index)) + + ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in + let ((index : ii), (result : 16 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ e varstup . let (index, result, rev_index) = varstup in + let (result : 16 bits) = + ((set_slice (( 16 : int):ii) (( 8 : int):ii) result rev_index + ((slice operand index (( 8 : int):ii) : 8 words$word)) + : 16 words$word)) in + let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in + let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in + (index, result, rev_index))) in + (index, result, rev_index))) in + aset_X d result))) + else if (((l__257 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . + let (containers : ii) = ((( 32 : int):ii) / container_size) in + let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in + let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rev_index : ii) . + let ((index : ii), (result : 32 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ c varstup . let (index, result, rev_index) = varstup in + let (rev_index : ii) = + (((ex_int index)) + + ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in + let ((index : ii), (result : 32 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ e varstup . let (index, result, rev_index) = varstup in + let (result : 32 bits) = + ((set_slice (( 32 : int):ii) (( 8 : int):ii) result rev_index + ((slice operand index (( 8 : int):ii) : 8 words$word)) + : 32 words$word)) in + let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in + let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in + (index, result, rev_index))) in + (index, result, rev_index))) in + aset_X d result))) + else if (((l__257 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . + let (containers : ii) = ((( 64 : int):ii) / container_size) in + let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in + let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rev_index : ii) . + let ((index : ii), (result : 64 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ c varstup . let (index, result, rev_index) = varstup in + let (rev_index : ii) = + (((ex_int index)) + + ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in + let ((index : ii), (result : 64 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ e varstup . let (index, result, rev_index) = varstup in + let (result : 64 bits) = + ((set_slice (( 64 : int):ii) (( 8 : int):ii) result rev_index + ((slice operand index (( 8 : int):ii) : 8 words$word)) + : 64 words$word)) in + let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in + let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in + (index, result, rev_index))) in + (index, result, rev_index))) in + aset_X d result))) + else if (((l__257 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (result : 128 bits) . + let (containers : ii) = ((( 128 : int):ii) / container_size) in + let (elements_per_container : ii) = (container_size / (( 8 : int):ii)) in + let (index : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rev_index : ii) . + let ((index : ii), (result : 128 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int containers)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ c varstup . let (index, result, rev_index) = varstup in + let (rev_index : ii) = + (((ex_int index)) + + ((((((ex_int elements_per_container)) - (( 1 : int):ii))) * (( 8 : int):ii)))) in + let ((index : ii), (result : 128 bits), (rev_index : ii)) = + (foreach (index_list (( 0 : int):ii) ((((ex_int elements_per_container)) - (( 1 : int):ii))) (( 1 : int):ii)) (index, + result, + rev_index) + (\ e varstup . let (index, result, rev_index) = varstup in + let (result : 128 bits) = + ((set_slice (( 128 : int):ii) (( 8 : int):ii) result rev_index + ((slice operand index (( 8 : int):ii) : 8 words$word)) + : 128 words$word)) in + let (index : ii) = (((ex_int index)) + (( 8 : int):ii)) in + let (rev_index : ii) = (((ex_int rev_index)) - (( 8 : int):ii)) in + (index, result, rev_index))) in + (index, result, rev_index))) in + aset_X d result))) + else + let dbytes = (ex_int ((l__257 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_integer_arithmetic_rbit : ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_rbit:int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__252 n= + (if (((l__252 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (result : 8 bits) . + let (result : 8 bits) = + (foreach (index_list (( 0 : int):ii) (((( 8 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice (( 8 : int):ii) (( 1 : int):ii) result (((((( 8 : int):ii) - (( 1 : int):ii))) - i)) + (vec_of_bits [access_vec_dec operand i] : 1 words$word) + : 8 words$word))) in + aset_X d result)) + else if (((l__252 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (result : 16 bits) . + let (result : 16 bits) = + (foreach (index_list (( 0 : int):ii) (((( 16 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice (( 16 : int):ii) (( 1 : int):ii) result (((((( 16 : int):ii) - (( 1 : int):ii))) - i)) + (vec_of_bits [access_vec_dec operand i] : 1 words$word) + : 16 words$word))) in + aset_X d result)) + else if (((l__252 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . + let (result : 32 bits) = + (foreach (index_list (( 0 : int):ii) (((( 32 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice (( 32 : int):ii) (( 1 : int):ii) result (((((( 32 : int):ii) - (( 1 : int):ii))) - i)) + (vec_of_bits [access_vec_dec operand i] : 1 words$word) + : 32 words$word))) in + aset_X d result)) + else if (((l__252 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . + let (result : 64 bits) = + (foreach (index_list (( 0 : int):ii) (((( 64 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice (( 64 : int):ii) (( 1 : int):ii) result (((((( 64 : int):ii) - (( 1 : int):ii))) - i)) + (vec_of_bits [access_vec_dec operand i] : 1 words$word) + : 64 words$word))) in + aset_X d result)) + else if (((l__252 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (result : 128 bits) . + let (result : 128 bits) = + (foreach (index_list (( 0 : int):ii) (((( 128 : int):ii) - (( 1 : int):ii))) (( 1 : int):ii)) result + (\ i result . + (set_slice (( 128 : int):ii) (( 1 : int):ii) result (((((( 128 : int):ii) - (( 1 : int):ii))) - i)) + (vec_of_bits [access_vec_dec operand i] : 1 words$word) + : 128 words$word))) in + aset_X d result)) + else + let dbytes = (ex_int ((l__252 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_arithmetic_rbit_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_rbit_decode:(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + aarch64_integer_arithmetic_rbit d datasize n)))`; + + +(*val aarch64_integer_arithmetic_mul_widening_64128hi : ii -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_mul_widening_64128hi:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__247 m n unsigned= + (if (((l__247 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . + let (result : ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 64 : int):ii) : 64 words$word)))) + else if (((l__247 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . + let (result : ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 64 : int):ii) : 64 words$word)))) + else if (((l__247 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . + let (result : ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 64 : int):ii) : 64 words$word)))) + else if (((l__247 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . + let (result : ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 64 : int):ii) : 64 words$word)))) + else if (((l__247 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . + let (result : ii) = + (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 64 : int):ii) : 64 words$word)))) + else + let dbytes = (ex_int ((l__247 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_arithmetic_mul_widening_64128hi_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_mul_widening_64128hi_decode:(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 U Rm o0 Ra Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (a : ii) = (lem$w2ui Ra) in + let (destsize : int) = ((( 64 : int):ii)) in + let (datasize : ii) = destsize in + let (unsigned : bool) = (U = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_arithmetic_mul_widening_64128hi d datasize m n unsigned)))`; + + +(*val aarch64_integer_arithmetic_mul_widening_3264 : ii -> ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_mul_widening_3264:int -> int -> int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__220 l__221 m n sub_op unsigned= + (if ((((((l__220 = (( 8 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if ((((((l__220 = (( 8 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__220 = (( 8 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__220 = (( 16 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if ((((((l__220 = (( 16 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__220 = (( 16 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__220 = (( 32 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if ((((((l__220 = (( 32 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__220 = (( 32 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__220 = (( 64 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if ((((((l__220 = (( 64 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__220 = (( 64 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__220 = (( 128 : int):ii)))) /\ (((l__221 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if ((((((l__220 = (( 128 : int):ii)))) /\ (((l__221 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((ex_int ((asl_Int operand3 unsigned)))) - + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned)))))) + else + ((ex_int ((asl_Int operand3 unsigned)))) + + ((((ex_int ((asl_Int operand1 unsigned)))) * + ((ex_int ((asl_Int operand2 unsigned))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__220 = (( 128 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if (((l__221 = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int ((l__220 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint") + else if (((l__221 = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int ((l__220 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint") + else sail2_state_monad$assert_expS T "destsize constraint"))`; + + +(*val integer_arithmetic_mul_widening_3264_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_mul_widening_3264_decode:(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 U Rm o0 Ra Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (a : ii) = (lem$w2ui Ra) in + let (destsize : int) = ((( 64 : int):ii)) in + let (datasize : int) = ((( 32 : int):ii)) in + let (sub_op : bool) = (o0 = (vec_of_bits [B1] : 1 words$word)) in + let (unsigned : bool) = (U = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_arithmetic_mul_widening_3264 a d datasize destsize m n sub_op unsigned)))`; + + +(*val aarch64_integer_arithmetic_mul_uniform_addsub : ii -> ii -> ii -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_mul_uniform_addsub:int -> int -> int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__193 l__194 m n sub_op= + (if ((((((l__193 = (( 8 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))))) + else if ((((((l__193 = (( 8 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__193 = (( 8 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__193 = (( 16 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))))) + else if ((((((l__193 = (( 16 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__193 = (( 16 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__193 = (( 32 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))))) + else if ((((((l__193 = (( 32 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__193 = (( 32 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__193 = (( 64 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))))) + else if ((((((l__193 = (( 64 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__193 = (( 64 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if ((((((l__193 = (( 128 : int):ii)))) /\ (((l__194 = (( 32 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) a : ( 32 words$word) M) (\ (operand3 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))))) + else if ((((((l__193 = (( 128 : int):ii)))) /\ (((l__194 = (( 64 : int):ii))))))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) a : ( 64 words$word) M) (\ (operand3 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if sub_op then + ((lem$w2ui operand3)) - ((((lem$w2ui operand1)) * ((lem$w2ui operand2)))) + else ((lem$w2ui operand3)) + ((((lem$w2ui operand1)) * ((lem$w2ui operand2))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))))) + else if (((l__193 = (( 128 : int):ii)))) then sail2_state_monad$assert_expS T "destsize constraint" + else if (((l__194 = (( 32 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int ((l__193 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint") + else if (((l__194 = (( 64 : int):ii)))) then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int ((l__193 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint") + else sail2_state_monad$assert_expS T "destsize constraint"))`; + + +(*val integer_arithmetic_mul_uniform_addsub_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_mul_uniform_addsub_decode:(1)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op54 op31 Rm o0 Ra Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (a : ii) = (lem$w2ui Ra) in + let (destsize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (datasize : ii) = destsize in + let (sub_op : bool) = (o0 = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_arithmetic_mul_uniform_addsub a d datasize destsize m n sub_op)))`; + + +(*val aarch64_integer_arithmetic_div : ii -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_div:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__188 m n unsigned= + (if (((l__188 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((IsZero operand2)) then (( 0 : int):ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) / + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d ((GetSlice_int ((make_the_value (( 8 : int):ii) : 8 itself)) result (( 0 : int):ii) : 8 words$word))))) + else if (((l__188 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((IsZero operand2)) then (( 0 : int):ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) / + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 16 : int):ii) : 16 itself)) result (( 0 : int):ii) : 16 words$word))))) + else if (((l__188 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((IsZero operand2)) then (( 0 : int):ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) / + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))) + else if (((l__188 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((IsZero operand2)) then (( 0 : int):ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) / + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))) + else if (((l__188 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((IsZero operand2)) then (( 0 : int):ii) + else + RoundTowardsZero + (((((real_of_int ((asl_Int operand1 unsigned))))) / + (((real_of_int ((asl_Int operand2 unsigned)))))))) in + aset_X d + ((GetSlice_int ((make_the_value (( 128 : int):ii) : 128 itself)) result (( 0 : int):ii) : 128 words$word))))) + else + let dbytes = (ex_int ((l__188 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_div_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 o1 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (unsigned : bool) = (o1 = (vec_of_bits [B0] : 1 words$word)) in + aarch64_integer_arithmetic_div d datasize m n unsigned)))`; + + +(*val aarch64_integer_arithmetic_cnt : ii -> ii -> ii -> CountOp -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_cnt:int -> int -> int -> CountOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__183 n opcode= + (if (((l__183 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_int () )) (\ (result : ii) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) (\ (result : ii) . + aset_X d ((GetSlice_int ((make_the_value (( 8 : int):ii) : 8 itself)) result (( 0 : int):ii) : 8 words$word))))) + else if (((l__183 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_int () )) (\ (result : ii) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) (\ (result : ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 16 : int):ii) : 16 itself)) result (( 0 : int):ii) : 16 words$word))))) + else if (((l__183 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_int () )) (\ (result : ii) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) (\ (result : ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) result (( 0 : int):ii) : 32 words$word))))) + else if (((l__183 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_int () )) (\ (result : ii) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) (\ (result : ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 64 : int):ii) : 64 itself)) result (( 0 : int):ii) : 64 words$word))))) + else if (((l__183 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_int () )) (\ (result : ii) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 + else CountLeadingSignBits operand1) (\ (result : ii) . + aset_X d + ((GetSlice_int ((make_the_value (( 128 : int):ii) : 128 itself)) result (( 0 : int):ii) : 128 words$word))))) + else + let dbytes = (ex_int ((l__183 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_arithmetic_cnt_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_cnt_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 op Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (opcode : CountOp) = + (if (((op = (vec_of_bits [B0] : 1 words$word)))) then CountOp_CLZ + else CountOp_CLS) in + aarch64_integer_arithmetic_cnt d datasize n opcode)))`; + + +(*val aarch64_integer_arithmetic_addsub_carry : ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_addsub_carry:int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__178 m n setflags sub_op= + (if (((l__178 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . + let (operand2 : 8 bits) = (if sub_op then (not_vec operand2 : 8 words$word) else operand2) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 w__0.ProcState_C : ( 8 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__178 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . + let (operand2 : 16 bits) = (if sub_op then (not_vec operand2 : 16 words$word) else operand2) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 w__5.ProcState_C : ( 16 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__178 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . + let (operand2 : 32 bits) = (if sub_op then (not_vec operand2 : 32 words$word) else operand2) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 w__10.ProcState_C : ( 32 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__178 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . + let (operand2 : 64 bits) = (if sub_op then (not_vec operand2 : 64 words$word) else operand2) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 w__15.ProcState_C : ( 64 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__178 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . + let (operand2 : 128 bits) = (if sub_op then (not_vec operand2 : 128 words$word) else operand2) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 w__20.ProcState_C : ( 128 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else + let dbytes = (ex_int ((l__178 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_arithmetic_addsub_carry_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_addsub_carry_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (setflags : bool) = (S1 = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_arithmetic_addsub_carry d datasize m n setflags sub_op)))`; + + +(*val ExtendReg : forall 'N . Size 'N => integer -> ii -> ExtendType -> ii -> M (mword 'N)*) + +val _ = Define ` + ((ExtendReg:int -> int -> ExtendType -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) reg typ shift= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((shift >= (( 0 : int):ii))) /\ ((shift <= (( 4 : int):ii)))))) "((shift >= 0) && (shift <= 4))") + (aget_X N__tv reg : ( 'N words$word) M)) (\ (val_name : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (len : ii) . + let (len : ii) = + ((case typ of + ExtendType_SXTB => + let (unsigned : bool) = F in + (( 8 : int):ii) + | ExtendType_SXTH => + let (unsigned : bool) = F in + (( 16 : int):ii) + | ExtendType_SXTW => + let (unsigned : bool) = F in + (( 32 : int):ii) + | ExtendType_SXTX => + let (unsigned : bool) = F in + (( 64 : int):ii) + | ExtendType_UXTB => + let (unsigned : bool) = T in + (( 8 : int):ii) + | ExtendType_UXTH => + let (unsigned : bool) = T in + (( 16 : int):ii) + | ExtendType_UXTW => + let (unsigned : bool) = T in + (( 32 : int):ii) + | ExtendType_UXTX => + let (unsigned : bool) = T in + (( 64 : int):ii) + )) in + let len = (int_min len ((((int_of_num (words$word_len val_name))) - shift))) in sail2_state_monad$bindS + (coerce_int_nat shift) (\ shift2 . + let (len2 : int) = (ex_int len) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "hack") + (sail2_state_monad$returnS ((place_subrange ((int_of_num (words$word_len val_name))) val_name ((len2 - (( 1 : int):ii))) (( 0 : int):ii) + ((ex_nat shift2)) + : 'N words$word)))))))))`; + + +(*val aget_ELR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_ELR__1 : unit -> M (mword ty64)*) + +val _ = Define ` + ((aget_ELR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (r : 64 bits) . + let pat_0 = el in + if (((pat_0 = EL1))) then (sail2_state_monad$read_regS ELR_EL1_ref : ( 64 words$word) M) + else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS ELR_EL2_ref : ( 64 words$word) M) + else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS ELR_EL3_ref : ( 64 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`; + + +val _ = Define ` + ((aget_ELR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL0))) "") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . + (aget_ELR__0 w__1.ProcState_EL : ( 64 words$word) M)))))`; + + +(*val ROR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) + +val _ = Define ` + ((ROR_C:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((shift <> (( 0 : int):ii)))) "(shift != 0)") + (let (m : ii) = (shift % ((int_of_num (words$word_len x)))) in sail2_state_monad$bindS + (LSR x m : ( 'N words$word) M) (\ (w__0 : 'N words$word) . sail2_state_monad$bindS + (LSL x ((((int_of_num (words$word_len x))) - ((ex_int m)))) : ( 'N words$word) M) (\ (w__1 : 'N words$word) . + let (result : 'N bits) = ((or_vec w__0 w__1 : 'N words$word)) in + let (carry_out : 1 bits) = + ((vec_of_bits [access_vec_dec result ((((int_of_num (words$word_len result))) - (( 1 : int):ii)))] : 1 words$word)) in + sail2_state_monad$returnS (result, carry_out))))))`; + + +(*val ROR : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N)*) + +val _ = Define ` + ((ROR:'N words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x shift= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((shift >= (( 0 : int):ii))) "(shift >= 0)") + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M)) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len x))) : ( 'N words$word) M) (\ (result : 'N bits) . + if (((shift = (( 0 : int):ii)))) then sail2_state_monad$returnS x + else sail2_state_monad$bindS + (ROR_C x shift : (( 'N words$word # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let (result : 'N bits) = tup__0 in + let (anon10 : 1 bits) = tup__1 in + sail2_state_monad$returnS result)))))`; + + +(*val aarch64_integer_bitfield : forall 'datasize. Size 'datasize => ii -> ii -> ii -> itself 'datasize -> bool -> bool -> ii -> mword 'datasize -> mword 'datasize -> M unit*) + +val _ = Define ` + ((aarch64_integer_bitfield:int -> int -> int -> 'datasize itself -> bool -> bool -> int -> 'datasize words$word -> 'datasize words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) R1 S1 d datasize extend inzero n tmask wmask= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (if inzero then sail2_state_monad$returnS ((Zeros__1 datasize () : 'datasize words$word)) + else (aget_X datasize d : ( 'datasize words$word) M))) (\ (dst : 'datasize bits) . sail2_state_monad$bindS + (aget_X datasize n : ( 'datasize words$word) M) (\ (src : 'datasize bits) . sail2_state_monad$bindS + (ROR src R1 : ( 'datasize words$word) M) (\ (w__1 : 'datasize words$word) . + let (bot : 'datasize bits) = + ((or_vec ((and_vec dst ((not_vec wmask : 'datasize words$word)) : 'datasize words$word)) + ((and_vec w__1 wmask : 'datasize words$word)) + : 'datasize words$word)) in sail2_state_monad$bindS + (if extend then + (Replicate ((int_of_num (words$word_len bot))) (vec_of_bits [access_vec_dec src S1] : 1 words$word) + : ( 'datasize words$word) M) + else sail2_state_monad$returnS dst) (\ (top : 'datasize bits) . + aset_X d + ((or_vec ((and_vec top ((not_vec tmask : 'datasize words$word)) : 'datasize words$word)) + ((and_vec bot tmask : 'datasize words$word)) + : 'datasize words$word))))))))`; + + +(*val ShiftReg : forall 'N . Size 'N => integer -> ii -> ShiftType -> ii -> M (mword 'N)*) + +val _ = Define ` + ((ShiftReg:int -> int -> ShiftType -> int ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) reg typ amount= (sail2_state_monad$bindS + (aget_X N__tv reg : ( 'N words$word) M) (\ (result : 'N bits) . + (case typ of + ShiftType_LSL => (LSL result amount : ( 'N words$word) M) + | ShiftType_LSR => (LSR result amount : ( 'N words$word) M) + | ShiftType_ASR => (ASR result amount : ( 'N words$word) M) + | ShiftType_ROR => (ROR result amount : ( 'N words$word) M) + ))))`; + + +(*val aarch64_integer_shift_variable : ii -> ii -> ii -> ii -> ShiftType -> M unit*) + +val _ = Define ` + ((aarch64_integer_shift_variable:int -> int -> int -> int -> ShiftType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__173 m n shift_type= + (if (((l__173 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (ShiftReg (( 8 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 8 : int):ii))) : ( 8 words$word) M) (\ (w__0 : 8 + bits) . + let result = w__0 in + aset_X d result))) + else if (((l__173 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (ShiftReg (( 16 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 16 : int):ii))) : ( 16 words$word) M) (\ (w__1 : 16 + bits) . + let result = w__1 in + aset_X d result))) + else if (((l__173 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (ShiftReg (( 32 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 32 : int):ii))) : ( 32 words$word) M) (\ (w__2 : 32 + bits) . + let result = w__2 in + aset_X d result))) + else if (((l__173 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (ShiftReg (( 64 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 64 : int):ii))) : ( 64 words$word) M) (\ (w__3 : 64 + bits) . + let result = w__3 in + aset_X d result))) + else if (((l__173 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (ShiftReg (( 128 : int):ii) n shift_type ((((lem$w2ui operand2)) % (( 128 : int):ii))) : ( 128 words$word) M) (\ (w__4 : 128 + bits) . + let result = w__4 in + aset_X d result))) + else + let dbytes = (ex_int ((l__173 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_shift_variable_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_shift_variable_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 op2 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (shift_type : ShiftType) = (DecodeShift op2) in + aarch64_integer_shift_variable d datasize m n shift_type)))`; + + +(*val aarch64_integer_logical_shiftedreg : ii -> ii -> bool -> ii -> ii -> LogicalOp -> bool -> ii -> ShiftType -> M unit*) + +val _ = Define ` + ((aarch64_integer_logical_shiftedreg:int -> int -> bool -> int -> int -> LogicalOp -> bool -> int -> ShiftType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__168 invert m n op setflags shift_amount shift_type= + (if (((l__168 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (ShiftReg (( 8 : int):ii) m shift_type shift_amount : ( 8 words$word) M) (\ (operand2 : 8 bits) . + let (operand2 : 8 bits) = (if invert then (not_vec operand2 : 8 words$word) else operand2) in sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (result : 8 bits) . + let (result : 8 bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 8 words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 8 words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 8 words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 8 : int):ii) - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))) + else if (((l__168 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (ShiftReg (( 16 : int):ii) m shift_type shift_amount : ( 16 words$word) M) (\ (operand2 : 16 bits) . + let (operand2 : 16 bits) = (if invert then (not_vec operand2 : 16 words$word) else operand2) in sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (result : 16 bits) . + let (result : 16 bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 16 words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 16 words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 16 words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 16 : int):ii) - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))) + else if (((l__168 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (ShiftReg (( 32 : int):ii) m shift_type shift_amount : ( 32 words$word) M) (\ (operand2 : 32 bits) . + let (operand2 : 32 bits) = (if invert then (not_vec operand2 : 32 words$word) else operand2) in sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . + let (result : 32 bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 32 words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 32 words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 32 words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 32 : int):ii) - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))) + else if (((l__168 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (ShiftReg (( 64 : int):ii) m shift_type shift_amount : ( 64 words$word) M) (\ (operand2 : 64 bits) . + let (operand2 : 64 bits) = (if invert then (not_vec operand2 : 64 words$word) else operand2) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . + let (result : 64 bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 64 words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 64 words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 64 words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 64 : int):ii) - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))) + else if (((l__168 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (ShiftReg (( 128 : int):ii) m shift_type shift_amount : ( 128 words$word) M) (\ (operand2 : 128 bits) . + let (operand2 : 128 bits) = (if invert then (not_vec operand2 : 128 words$word) else operand2) in sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (result : 128 bits) . + let (result : 128 bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 128 words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 128 words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 128 words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result (((( 128 : int):ii) - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))) + else + let dbytes = (ex_int ((l__168 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_integer_arithmetic_addsub_shiftedreg : ii -> ii -> ii -> ii -> bool -> ii -> ShiftType -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_addsub_shiftedreg:int -> int -> int -> int -> bool -> int -> ShiftType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__163 m n setflags shift_amount shift_type sub_op= + (if (((l__163 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (ShiftReg (( 8 : int):ii) m shift_type shift_amount : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 8 bits)) = + (if sub_op then + let (operand2 : 8 bits) = ((not_vec operand2 : 8 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 8 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__163 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (ShiftReg (( 16 : int):ii) m shift_type shift_amount : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 16 bits)) = + (if sub_op then + let (operand2 : 16 bits) = ((not_vec operand2 : 16 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 16 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__163 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (ShiftReg (( 32 : int):ii) m shift_type shift_amount : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 32 bits)) = + (if sub_op then + let (operand2 : 32 bits) = ((not_vec operand2 : 32 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 32 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__163 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (ShiftReg (( 64 : int):ii) m shift_type shift_amount : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 64 bits)) = + (if sub_op then + let (operand2 : 64 bits) = ((not_vec operand2 : 64 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 64 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else if (((l__163 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (ShiftReg (( 128 : int):ii) m shift_type shift_amount : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 128 bits)) = + (if sub_op then + let (operand2 : 128 bits) = ((not_vec operand2 : 128 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 128 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (aset_X d result)))))) + else + let dbytes = (ex_int ((l__163 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val Prefetch : mword ty64 -> mword ty5 -> M unit*) + +val _ = Define ` + ((Prefetch:(64)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address prfop= (sail2_state_monad$bindS + (undefined_PrefetchHint () ) (\ (hint : PrefetchHint) . sail2_state_monad$bindS + (undefined_int () ) (\ (target : ii) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (stream : bool) . + let b__0 = ((slice prfop (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let (hint : PrefetchHint) = + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Prefetch_READ + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Prefetch_EXEC + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then Prefetch_WRITE + else hint) in + let (target : ii) = (lem$w2ui ((slice prfop (( 1 : int):ii) (( 2 : int):ii) : 2 words$word))) in + let (stream : bool) = + ((vec_of_bits [access_vec_dec prfop (( 0 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in + let (_ : unit) = (Hint_Prefetch address hint target stream) in + sail2_state_monad$returnS () )))))`; + + +(*val IsSecondStage : FaultRecord -> M bool*) + +val _ = Define ` + ((IsSecondStage:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)") + (sail2_state_monad$returnS fault.FaultRecord_secondstage)))`; + + +(*val IsFault : AddressDescriptor -> bool*) + +val _ = Define ` + ((IsFault:AddressDescriptor -> bool) addrdesc= (addrdesc.AddressDescriptor_fault.FaultRecord_typ <> Fault_None))`; + + +(*val CombineS1S2Desc : AddressDescriptor -> AddressDescriptor -> M AddressDescriptor*) + +val _ = Define ` + ((CombineS1S2Desc:AddressDescriptor -> AddressDescriptor ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s1desc s2desc= (sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) . + let result = ((result with<| AddressDescriptor_paddress := (s2desc.AddressDescriptor_paddress)|>)) in sail2_state_monad$bindS + (if (((((IsFault s1desc)) \/ ((IsFault s2desc))))) then + let (result : AddressDescriptor) = (if ((IsFault s1desc)) then s1desc else s2desc) in + sail2_state_monad$returnS result + else if ((((((s2desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))) \/ (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) then + let (tmp_610 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let tmp_610 = ((tmp_610 with<| MemoryAttributes_typ := MemType_Device|>)) in + let result = ((result with<| AddressDescriptor_memattrs := tmp_610|>)) in + if (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Normal))) then + let (tmp_620 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let (tmp_620 : MemoryAttributes) = + ((tmp_620 with<| + MemoryAttributes_device := (s2desc.AddressDescriptor_memattrs.MemoryAttributes_device)|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_620|>)) in + sail2_state_monad$returnS result + else if (((s2desc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Normal))) then + let (tmp_630 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let (tmp_630 : MemoryAttributes) = + ((tmp_630 with<| + MemoryAttributes_device := (s1desc.AddressDescriptor_memattrs.MemoryAttributes_device)|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_630|>)) in + sail2_state_monad$returnS result + else + let (tmp_640 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS + (CombineS1S2Device s1desc.AddressDescriptor_memattrs.MemoryAttributes_device + s2desc.AddressDescriptor_memattrs.MemoryAttributes_device) (\ (w__0 : DeviceType) . + let (tmp_640 : MemoryAttributes) = ((tmp_640 with<| MemoryAttributes_device := w__0|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_640|>)) in + sail2_state_monad$returnS result) + else + let (tmp_650 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let tmp_650 = ((tmp_650 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let result = ((result with<| AddressDescriptor_memattrs := tmp_650|>)) in + let (tmp_660 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS + (undefined_DeviceType () ) (\ (w__1 : DeviceType) . + let tmp_660 = ((tmp_660 with<| MemoryAttributes_device := w__1|>)) in + let result = ((result with<| AddressDescriptor_memattrs := tmp_660|>)) in + let (tmp_670 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS + (CombineS1S2AttrHints s1desc.AddressDescriptor_memattrs.MemoryAttributes_inner + s2desc.AddressDescriptor_memattrs.MemoryAttributes_inner) (\ (w__2 : MemAttrHints) . + let tmp_670 = ((tmp_670 with<| MemoryAttributes_inner := w__2|>)) in + let result = ((result with<| AddressDescriptor_memattrs := tmp_670|>)) in + let (tmp_680 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in sail2_state_monad$bindS + (CombineS1S2AttrHints s1desc.AddressDescriptor_memattrs.MemoryAttributes_outer + s2desc.AddressDescriptor_memattrs.MemoryAttributes_outer) (\ (w__3 : MemAttrHints) . + let (tmp_680 : MemoryAttributes) = ((tmp_680 with<| MemoryAttributes_outer := w__3|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_680|>)) in + let (tmp_690 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let (tmp_690 : MemoryAttributes) = + ((tmp_690 with<| + MemoryAttributes_shareable := + (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_shareable \/ s2desc.AddressDescriptor_memattrs.MemoryAttributes_shareable)))|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_690|>)) in + let (tmp_700 : MemoryAttributes) = (result.AddressDescriptor_memattrs) in + let (tmp_700 : MemoryAttributes) = + ((tmp_700 with<| + MemoryAttributes_outershareable := + (((s1desc.AddressDescriptor_memattrs.MemoryAttributes_outershareable \/ s2desc.AddressDescriptor_memattrs.MemoryAttributes_outershareable)))|>)) in + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := tmp_700|>)) in + sail2_state_monad$returnS result)))) (\ (result : AddressDescriptor) . sail2_state_monad$bindS + (MemAttrDefaults result.AddressDescriptor_memattrs) (\ (w__4 : MemoryAttributes) . + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_memattrs := w__4|>)) in + sail2_state_monad$returnS result)))))`; + + +(*val IsExternalSyncAbort__0 : Fault -> M bool*) + +(*val IsExternalSyncAbort__1 : FaultRecord -> M bool*) + +val _ = Define ` + ((IsExternalSyncAbort__0:Fault ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((typ <> Fault_None))) "") + (sail2_state_monad$returnS ((((((typ = Fault_SyncExternal))) \/ ((((((typ = Fault_SyncParity))) \/ ((((((typ = Fault_SyncExternalOnWalk))) \/ (((typ = Fault_SyncParityOnWalk)))))))))))))))`; + + +val _ = Define ` + ((IsExternalSyncAbort__1:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (IsExternalSyncAbort__0 fault.FaultRecord_typ))`; + + +(*val IsExternalAbort__0 : Fault -> M bool*) + +(*val IsExternalAbort__1 : FaultRecord -> M bool*) + +val _ = Define ` + ((IsExternalAbort__0:Fault ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((typ <> Fault_None))) "") + (sail2_state_monad$returnS ((((((typ = Fault_SyncExternal))) \/ ((((((typ = Fault_SyncParity))) \/ ((((((typ = Fault_SyncExternalOnWalk))) \/ ((((((typ = Fault_SyncParityOnWalk))) \/ ((((((typ = Fault_AsyncExternal))) \/ (((typ = Fault_AsyncParity)))))))))))))))))))))`; + + +val _ = Define ` + ((IsExternalAbort__1:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (IsExternalAbort__0 fault.FaultRecord_typ))`; + + +(*val IsDebugException : FaultRecord -> M bool*) + +val _ = Define ` + ((IsDebugException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)") + (sail2_state_monad$returnS (((fault.FaultRecord_typ = Fault_Debug))))))`; + + +(*val IPAValid : FaultRecord -> M bool*) + +val _ = Define ` + ((IPAValid:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)") + (sail2_state_monad$returnS (if fault.FaultRecord_s2fs1walk then + ((((fault.FaultRecord_typ = Fault_AccessFlag))) \/ ((((((fault.FaultRecord_typ = Fault_Permission))) \/ ((((((fault.FaultRecord_typ = Fault_Translation))) \/ (((fault.FaultRecord_typ = Fault_AddressSize)))))))))) + else if fault.FaultRecord_secondstage then + ((((fault.FaultRecord_typ = Fault_AccessFlag))) \/ ((((((fault.FaultRecord_typ = Fault_Translation))) \/ (((fault.FaultRecord_typ = Fault_AddressSize))))))) + else F))))`; + + +(*val aarch64_integer_logical_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> LogicalOp -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_logical_immediate:int -> 'datasize itself -> 'datasize words$word -> int -> LogicalOp -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm n op setflags= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector datasize : ( 'datasize words$word) M)) (\ (result : 'datasize bits) . sail2_state_monad$bindS + (aget_X datasize n : ( 'datasize words$word) M) (\ (operand1 : 'datasize bits) . + let (operand2 : 'datasize bits) = imm in + let (result : 'datasize bits) = + ((case op of + LogicalOp_AND => (and_vec operand1 operand2 : 'datasize words$word) + | LogicalOp_ORR => (or_vec operand1 operand2 : 'datasize words$word) + | LogicalOp_EOR => (xor_vec operand1 operand2 : 'datasize words$word) + )) in sail2_state_monad$seqS + (if setflags then + let split_vec = + ((concat_vec + ((concat_vec + (vec_of_bits [access_vec_dec result ((datasize - (( 1 : int):ii)))] : 1 words$word) + ((IsZeroBit result : 1 words$word)) + : 2 words$word)) (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))`; + + +(*val aarch64_integer_arithmetic_addsub_immediate : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> ii -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_addsub_immediate:int -> 'datasize itself -> 'datasize words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm n setflags sub_op= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector datasize : ( 'datasize words$word) M)) (\ (result : 'datasize bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP datasize () : ( 'datasize words$word) M) + else (aget_X datasize n : ( 'datasize words$word) M)) (\ (operand1 : 'datasize bits) . + let (operand2 : 'datasize bits) = imm in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 'datasize bits)) = + (if sub_op then + let (operand2 : 'datasize bits) = ((not_vec operand2 : 'datasize words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 'datasize words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))))`; + + +(*val aarch64_integer_arithmetic_addsub_extendedreg : ii -> ii -> ExtendType -> ii -> ii -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_arithmetic_addsub_extendedreg:int -> int -> ExtendType -> int -> int -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__158 extend_type m n setflags shift sub_op= + (if (((l__158 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP (( 8 : int):ii) () : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (ExtendReg (( 8 : int):ii) m extend_type shift : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 8 bits)) = + (if sub_op then + let (operand2 : 8 bits) = ((not_vec operand2 : 8 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 8 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))) + else if (((l__158 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP (( 16 : int):ii) () : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (ExtendReg (( 16 : int):ii) m extend_type shift : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 16 bits)) = + (if sub_op then + let (operand2 : 16 bits) = ((not_vec operand2 : 16 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 16 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))) + else if (((l__158 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP (( 32 : int):ii) () : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (ExtendReg (( 32 : int):ii) m extend_type shift : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 32 bits)) = + (if sub_op then + let (operand2 : 32 bits) = ((not_vec operand2 : 32 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 32 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))) + else if (((l__158 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 64 bits)) = + (if sub_op then + let (operand2 : 64 bits) = ((not_vec operand2 : 64 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 64 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))) + else if (((l__158 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then (aget_SP (( 128 : int):ii) () : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (ExtendReg (( 128 : int):ii) m extend_type shift : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (nzcv1 : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (carry_in : 1 bits) . + let ((carry_in : 1 bits), (operand2 : 128 bits)) = + (if sub_op then + let (operand2 : 128 bits) = ((not_vec operand2 : 128 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 128 words$word # 4 words$word))) in + let result = tup__0 in + let nzcv1 = tup__1 in sail2_state_monad$seqS + (if setflags then + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec nzcv1 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec nzcv1 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$returnS () ) + (if ((((((d = (( 31 : int):ii)))) /\ ((~ setflags))))) then aset_SP result + else aset_X d result)))))) + else + let dbytes = (ex_int ((l__158 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val RestoredITBits : mword ty32 -> M (mword ty8)*) + +val _ = Define ` + ((RestoredITBits:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((8)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr= + (let (it : 8 bits) = + ((concat_vec ((subrange_vec_dec spsr (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) + ((subrange_vec_dec spsr (( 26 : int):ii) (( 25 : int):ii) : 2 words$word)) + : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + if (((w__0.ProcState_IL = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (ConstrainUnpredictableBool Unpredictable_ILZEROIT) (\ (w__1 : bool) . + sail2_state_monad$returnS (if w__1 then (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + else it)) + else if (((((~ ((IsZero ((subrange_vec_dec it (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)))))) /\ ((IsZero ((subrange_vec_dec it (( 3 : int):ii) (( 0 : int):ii) : 4 words$word))))))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$bindS + (if (((w__2.ProcState_EL = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS HSCTLR_ref : ( 32 words$word) M) (\ (w__3 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 7 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 7 : int):ii)] : 1 words$word))) (\ (itd : 1 bits) . + sail2_state_monad$returnS (if ((((((((((vec_of_bits [access_vec_dec spsr (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) /\ ((~ ((IsZero it))))))) \/ ((((((itd = (vec_of_bits [B1] : 1 words$word)))) /\ ((~ ((IsZero ((subrange_vec_dec it (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)))))))))))) + then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + else it))))))`; + + +(*val IsEL1TransRegimeRegs : unit -> M bool*) + +val _ = Define ` + ((IsEL1TransRegimeRegs:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL1)))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL0))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))))))`; + + +(*val CalculateTBI : mword ty64 -> bool -> M bool*) + +val _ = Define ` + ((CalculateTBI:(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr data= + (let (tbi : bool) = F in sail2_state_monad$bindS + (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . + if w__1 then + if data then + if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + else + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + else if data then + if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else if ((((vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__14 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__15 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + else + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__17 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . + if (((w__20.ProcState_EL = EL2))) then + if data then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__21 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__22 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__22 (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__23 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 29 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . + if (((w__26.ProcState_EL = EL3))) then + if data then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__27 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__27 (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + else + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__28 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__29 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__29 (( 29 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + else sail2_state_monad$returnS tbi)))))`; + + +(*val CalculateBottomPACBit : mword ty64 -> mword ty1 -> M ii*) + +val _ = Define ` + ((CalculateBottomPACBit:(64)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr top_bit= (sail2_state_monad$bindS + (undefined_int () ) (\ (tsz_field : ii) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (using64k : bool) . sail2_state_monad$bindS + (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then sail2_state_monad$bindS + (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . + if w__1 then sail2_state_monad$bindS + (if (((top_bit = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__2 (( 16 : int):ii) (( 6 : int):ii) : 6 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__3 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word)))))) (\ (w__4 : ii) . + let tsz_field = w__4 in sail2_state_monad$bindS + (if (((top_bit = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS (((((slice w__5 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS (((((slice w__6 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))) (\ (w__7 : bool) . + let (using64k : bool) = w__7 in + sail2_state_monad$returnS (tsz_field, using64k))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((HaveEL EL2)) "HaveEL(EL2)") + (if (((top_bit = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__8 (( 16 : int):ii) (( 6 : int):ii) : 6 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__9 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))))) (\ (w__10 : ii) . + let tsz_field = w__10 in sail2_state_monad$bindS + (if (((top_bit = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS (((((slice w__11 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS (((((slice w__12 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))) (\ (w__13 : bool) . + let (using64k : bool) = w__13 in + sail2_state_monad$returnS (tsz_field, using64k)))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__14 : ProcState) . sail2_state_monad$bindS + (if (((w__14.ProcState_EL = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__15 : 64 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__15 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__16 : 32 bits) . + sail2_state_monad$returnS ((lem$w2ui ((slice w__16 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word)))))) (\ (w__17 : ii) . + let tsz_field = w__17 in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__18 : ProcState) . sail2_state_monad$bindS + (if (((w__18.ProcState_EL = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__19 : 64 bits) . + sail2_state_monad$returnS (((((slice w__19 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS (((((slice w__20 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))) (\ (w__21 : bool) . + let (using64k : bool) = w__21 in + sail2_state_monad$returnS (tsz_field, using64k)))))) (\ varstup . let ((tsz_field : ii), (using64k : bool)) = varstup in + let (max_limit_tsz_field : ii) = ((( 39 : int):ii)) in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((ex_int tsz_field)) > ((ex_int max_limit_tsz_field)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FORCE) || (c == Constraint_NONE))") + (let (tsz_field : ii) = (if (((c = Constraint_FORCE))) then max_limit_tsz_field else tsz_field) in + sail2_state_monad$returnS (c, tsz_field)) + else sail2_state_monad$returnS (c, tsz_field)) (\ varstup . let ((c : Constraint), (tsz_field : ii)) = varstup in + let (tszmin : ii) = + (if (((using64k /\ (((((ex_int ((VAMax () )))) = (( 52 : int):ii))))))) then (( 12 : int):ii) + else (( 16 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int tsz_field)) < ((ex_int tszmin)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FORCE) || (c == Constraint_NONE))") + (let (tsz_field : ii) = (if (((c = Constraint_FORCE))) then tszmin else tsz_field) in + sail2_state_monad$returnS tsz_field) + else sail2_state_monad$returnS tsz_field) (\ (tsz_field : ii) . + sail2_state_monad$returnS (((( 64 : int):ii) - ((ex_int tsz_field)))))))))))))`; + + +(*val Auth : mword ty64 -> mword ty64 -> mword ty128 -> bool -> mword ty1 -> M (mword ty64)*) + +val _ = Define ` + ((Auth:(64)words$word ->(64)words$word ->(128)words$word -> bool ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr modifier K1 data keynumber= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (PAC : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (original_ptr : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (error_code : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (extfield : 64 bits) . sail2_state_monad$bindS + (CalculateTBI ptr data) (\ (tbi : bool) . sail2_state_monad$bindS + (CalculateBottomPACBit ptr (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word)) (\ (w__0 : + ii) . + let bottom_PAC_bit = (ex_int w__0) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let extfield = + ((replicate_bits (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) (( 64 : int):ii) : 64 words$word)) in + let (original_ptr : 64 bits) = + (if tbi then + (concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + ((subrange_subrange_concat + ((((((((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - + (( 1 : int):ii))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) + + + ((bottom_PAC_bit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) + extfield + ((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) + ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 56 words$word)) + : 64 words$word) + else + (subrange_subrange_concat ((int_of_num (words$word_len PAC))) extfield + ((((((~ bottom_PAC_bit)) + (( 64 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) ptr + ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 64 words$word)) in sail2_state_monad$bindS + (ComputePAC original_ptr modifier ((subrange_vec_dec K1 (( 127 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((subrange_vec_dec K1 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (PAC : 64 bits) = w__1 in + let (result : 64 bits) = + (if tbi then + if ((subrange_subrange_eq PAC + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii))) + + + bottom_PAC_bit)) bottom_PAC_bit)) then + original_ptr + else + let (error_code : 2 bits) = + ((concat_vec keynumber ((not_vec keynumber : 1 words$word)) : 2 words$word)) in + (concat_vec + ((concat_vec ((subrange_vec_dec original_ptr (( 63 : int):ii) (( 55 : int):ii) : 9 words$word)) error_code + : 11 words$word)) ((subrange_vec_dec original_ptr (( 52 : int):ii) (( 0 : int):ii) : 53 words$word)) + : 64 words$word) + else if (((((subrange_subrange_eq PAC + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) bottom_PAC_bit ptr + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) bottom_PAC_bit)) /\ (((((subrange_vec_dec PAC (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) = ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)))))))) then + original_ptr + else + let (error_code : 2 bits) = + ((concat_vec keynumber ((not_vec keynumber : 1 words$word)) : 2 words$word)) in + (concat_vec + ((concat_vec (vec_of_bits [access_vec_dec original_ptr (( 63 : int):ii)] : 1 words$word) error_code + : 3 words$word)) ((subrange_vec_dec original_ptr (( 60 : int):ii) (( 0 : int):ii) : 61 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS result)))))))))))`; + + +(*val HighestELUsingAArch32 : unit -> bool*) + +val _ = Define ` + ((HighestELUsingAArch32:unit -> bool) () = (if ((~ ((HaveAnyAArch32 () )))) then F else F))`; + + +(*val aget_SCR_GEN : unit -> M (mword ty32)*) + +val _ = Define ` + ((aget_SCR_GEN:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((HaveEL EL3)) "HaveEL(EL3)") + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (r : 32 bits) . + if ((HighestELUsingAArch32 () )) then (sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) + else (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M))))`; + + +(*val IsSecureBelowEL3 : unit -> M bool*) + +val _ = Define ` + ((IsSecureBelowEL3:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (if ((HaveEL EL3)) then sail2_state_monad$bindS + (aget_SCR_GEN () : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))) + else sail2_state_monad$returnS (if ((HaveEL EL2)) then F else F)))`; + + +(*val UsingAArch32 : unit -> M bool*) + +val _ = Define ` + ((UsingAArch32:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + let (aarch32 : bool) = (w__0.ProcState_nRW = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((~ ((HaveAnyAArch32 () )))) then sail2_state_monad$assert_expS ((~ aarch32)) "!(aarch32)" + else sail2_state_monad$returnS () ) + (if ((HighestELUsingAArch32 () )) then sail2_state_monad$assert_expS aarch32 "aarch32" + else sail2_state_monad$returnS () )) + (sail2_state_monad$returnS aarch32))))`; + + +(*val aset_SPSR : mword ty32 -> M unit*) + +val _ = Define ` + ((aset_SPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let p__298 = (w__1.ProcState_M) in + let pat_0 = p__298 in + if (((pat_0 = M32_FIQ))) then sail2_state_monad$write_regS SPSR_fiq_ref value_name + else if (((pat_0 = M32_IRQ))) then sail2_state_monad$write_regS SPSR_irq_ref value_name + else if (((pat_0 = M32_Svc))) then sail2_state_monad$write_regS SPSR_svc_ref value_name + else if (((pat_0 = M32_Monitor))) then sail2_state_monad$write_regS SPSR_mon_ref value_name + else if (((pat_0 = M32_Abort))) then sail2_state_monad$write_regS SPSR_abt_ref value_name + else if (((pat_0 = M32_Hyp))) then sail2_state_monad$write_regS SPSR_hyp_ref value_name + else if (((pat_0 = M32_Undef))) then sail2_state_monad$write_regS SPSR_und_ref value_name + else Unreachable () ) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__297 = (w__2.ProcState_EL) in + let pat_0 = p__297 in + if (((pat_0 = EL1))) then sail2_state_monad$write_regS SPSR_EL1_ref value_name + else if (((pat_0 = EL2))) then sail2_state_monad$write_regS SPSR_EL2_ref value_name + else if (((pat_0 = EL3))) then sail2_state_monad$write_regS SPSR_EL3_ref value_name + else Unreachable () ))))`; + + +(*val aget_SPSR : unit -> M (mword ty32)*) + +val _ = Define ` + ((aget_SPSR:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let p__296 = (w__1.ProcState_M) in + let pat_0 = p__296 in + if (((pat_0 = M32_FIQ))) then (sail2_state_monad$read_regS SPSR_fiq_ref : ( 32 words$word) M) + else if (((pat_0 = M32_IRQ))) then (sail2_state_monad$read_regS SPSR_irq_ref : ( 32 words$word) M) + else if (((pat_0 = M32_Svc))) then (sail2_state_monad$read_regS SPSR_svc_ref : ( 32 words$word) M) + else if (((pat_0 = M32_Monitor))) then (sail2_state_monad$read_regS SPSR_mon_ref : ( 32 words$word) M) + else if (((pat_0 = M32_Abort))) then (sail2_state_monad$read_regS SPSR_abt_ref : ( 32 words$word) M) + else if (((pat_0 = M32_Hyp))) then (sail2_state_monad$read_regS SPSR_hyp_ref : ( 32 words$word) M) + else if (((pat_0 = M32_Undef))) then (sail2_state_monad$read_regS SPSR_und_ref : ( 32 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + let p__295 = (w__9.ProcState_EL) in + let pat_0 = p__295 in + if (((pat_0 = EL1))) then (sail2_state_monad$read_regS SPSR_EL1_ref : ( 32 words$word) M) + else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS SPSR_EL2_ref : ( 32 words$word) M) + else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS SPSR_EL3_ref : ( 32 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS result))))))`; + + +(*val IsSecure : unit -> M bool*) + +val _ = Define ` + ((IsSecure:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL3)))))) (\ (w__3 : + bool) . + if w__3 then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((UsingAArch32 () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + sail2_state_monad$returnS (((w__6.ProcState_M = M32_Monitor)))))) (\ (w__7 : bool) . + if w__7 then sail2_state_monad$returnS T + else IsSecureBelowEL3 () ))))`; + + +(*val FPProcessException : FPExc -> mword ty32 -> M unit*) + +val _ = Define ` + ((FPProcessException:FPExc ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception fpcr= (sail2_state_monad$bindS + (undefined_int () ) (\ (cumul : ii) . + let (cumul : ii) = + ((case exception of + FPExc_InvalidOp => (( 0 : int):ii) + | FPExc_DivideByZero => (( 1 : int):ii) + | FPExc_Overflow => (( 2 : int):ii) + | FPExc_Underflow => (( 3 : int):ii) + | FPExc_Inexact => (( 4 : int):ii) + | FPExc_InputDenorm => (( 7 : int):ii) + )) in + let (enable : ii) = (((ex_int cumul)) + (( 8 : int):ii)) in + if ((((vec_of_bits [access_vec_dec fpcr enable] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + sail2_state_monad$throwS (Error_Implementation_Defined "floating-point trap handling") + else sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$write_regS + FPSCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__1 cumul (vec_of_bits [B1] : 1 words$word) : 32 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + sail2_state_monad$write_regS + FPSR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 cumul (vec_of_bits [B1] : 1 words$word) : 32 words$word)))))))`; + + +(*val FPRoundBase : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +val _ = Define ` + ((FPRoundBase:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr rounding= + (let p0_ = N__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) "")) + (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) "")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (F_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (E_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (minimum_exp : ii) . + let minimum_exp = (~ (( 14 : int):ii)) in + let E_mut = ((( 5 : int):ii)) in + let F_mut = ((( 10 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (undefined_real () )) (\ (mantissa : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . + let ((mantissa : real), (sign : 1 bits)) = + (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then + let (sign : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + let (mantissa : real) =((real_of_num 0) - op) in + (mantissa, sign) + else + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (mantissa : real) = op in + (mantissa, sign)) in + let (exponent : ii) = ((( 0 : int):ii)) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in + (exponent, mantissa))) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in + (exponent, mantissa))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ F))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ T)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$write_regS + FPSCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__1 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + sail2_state_monad$write_regS + FPSR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))) + (FPZero (( 16 : int):ii) sign : ( 'N words$word) M)) (\ (w__3 : 'N words$word) . + sail2_state_monad$returnS ((words$w2w w__3 : 'N words$word)))) + else + let (biased_exp : ii) = + (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii))) + (( 0 : int):ii)) in + let (mantissa : real) = + (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then + mantissa / + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + let (int_mant : ii) = + (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 10 : int):ii)))))) in + let (error : real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 10 : int):ii))))) - + (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . + let ((overflow_to_inf : bool), (round_up : bool)) = + ((case rounding of + FPRounding_TIEEVEN => + let (round_up : bool) = + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) int_mant (( 0 : int):ii) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))) in + let (overflow_to_inf : bool) = T in + (overflow_to_inf, round_up) + | FPRounding_POSINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_NEGINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_ZERO => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + | FPRounding_ODD => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + )) in + let ((biased_exp : ii), (int_mant : ii)) = + (if round_up then + let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in + let (biased_exp : ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 10 : int):ii)))))) then (( 1 : int):ii) + else biased_exp) in + let ((biased_exp : ii), (int_mant : ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 11 : int):ii)))))) then + let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in + let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + let (int_mant : ii) = + (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then + set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + else int_mant) in sail2_state_monad$bindS + (if (((F \/ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + if ((((ex_int biased_exp)) >= ((((pow2 (( 5 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS + (if overflow_to_inf then (FPInfinity (( 16 : int):ii) sign : ( 16 words$word) M) + else (FPMaxNormal (( 16 : int):ii) sign : ( 16 words$word) M)) (\ (w__6 : 16 words$word) . + let result = w__6 in sail2_state_monad$seqS + (FPProcessException FPExc_Overflow fpcr) + (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in + sail2_state_monad$returnS (error, result))) + else + let (result : 16 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 16 : int):ii) - (( 10 : int):ii))) - (( 1 : int):ii))) + : 5 itself)) biased_exp (( 0 : int):ii) + : 5 words$word)) + : 6 words$word)) + ((GetSlice_int ((make_the_value (( 10 : int):ii) : 10 itself)) int_mant (( 0 : int):ii) + : 10 words$word)) + : 16 words$word)) in + sail2_state_monad$returnS (error, result) + else if ((((ex_int biased_exp)) >= ((pow2 (( 5 : int):ii))))) then + let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 16 : int):ii) - (( 1 : int):ii))) : 15 itself)) + : 15 words$word)) + : 16 words$word)) in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) + (let (error : real) = (realFromFrac(( 0 : int))(( 10 : int))) in + sail2_state_monad$returnS (error, result)) + else + let (result : 16 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 16 : int):ii) - (( 10 : int):ii))) - (( 1 : int):ii))) + : 5 itself)) biased_exp (( 0 : int):ii) + : 5 words$word)) + : 6 words$word)) + ((GetSlice_int ((make_the_value (( 10 : int):ii) : 10 itself)) int_mant (( 0 : int):ii) + : 10 words$word)) + : 16 words$word)) in + sail2_state_monad$returnS (error, result)) (\ varstup . let ((error : real), (result : 16 bits)) = varstup in sail2_state_monad$seqS + (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS ((words$w2w result : 'N words$word)))))))))))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) "")) + (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) "")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (F_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (E_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (minimum_exp : ii) . + let minimum_exp = (~ (( 126 : int):ii)) in + let E_mut = ((( 8 : int):ii)) in + let F_mut = ((( 23 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (undefined_real () )) (\ (mantissa : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . + let ((mantissa : real), (sign : 1 bits)) = + (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then + let (sign : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + let (mantissa : real) =((real_of_num 0) - op) in + (mantissa, sign) + else + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (mantissa : real) = op in + (mantissa, sign)) in + let (exponent : ii) = ((( 0 : int):ii)) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in + (exponent, mantissa))) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in + (exponent, mantissa))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ T))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ F)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__8 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__8 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSCR_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . + sail2_state_monad$write_regS + FPSCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__9 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + sail2_state_monad$write_regS + FPSR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__10 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))) + (FPZero (( 32 : int):ii) sign : ( 'N words$word) M)) (\ (w__11 : 'N words$word) . + sail2_state_monad$returnS ((words$w2w w__11 : 'N words$word)))) + else + let (biased_exp : ii) = + (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii))) + (( 0 : int):ii)) in + let (mantissa : real) = + (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then + mantissa / + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + let (int_mant : ii) = + (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 23 : int):ii)))))) in + let (error : real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 23 : int):ii))))) - + (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . + let ((overflow_to_inf : bool), (round_up : bool)) = + ((case rounding of + FPRounding_TIEEVEN => + let (round_up : bool) = + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) int_mant (( 0 : int):ii) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))) in + let (overflow_to_inf : bool) = T in + (overflow_to_inf, round_up) + | FPRounding_POSINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_NEGINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_ZERO => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + | FPRounding_ODD => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + )) in + let ((biased_exp : ii), (int_mant : ii)) = + (if round_up then + let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in + let (biased_exp : ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 23 : int):ii)))))) then (( 1 : int):ii) + else biased_exp) in + let ((biased_exp : ii), (int_mant : ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 24 : int):ii)))))) then + let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in + let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + let (int_mant : ii) = + (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then + set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + else int_mant) in sail2_state_monad$bindS + (if ((((ex_int biased_exp)) >= ((((pow2 (( 8 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS + (if overflow_to_inf then (FPInfinity (( 32 : int):ii) sign : ( 32 words$word) M) + else (FPMaxNormal (( 32 : int):ii) sign : ( 32 words$word) M)) (\ (w__14 : 32 words$word) . + let result = w__14 in sail2_state_monad$seqS + (FPProcessException FPExc_Overflow fpcr) + (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in + sail2_state_monad$returnS (error, result))) + else + let (result : 32 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 32 : int):ii) - (( 23 : int):ii))) - (( 1 : int):ii))) + : 8 itself)) biased_exp (( 0 : int):ii) + : 8 words$word)) + : 9 words$word)) + ((GetSlice_int ((make_the_value (( 23 : int):ii) : 23 itself)) int_mant (( 0 : int):ii) + : 23 words$word)) + : 32 words$word)) in + sail2_state_monad$returnS (error, result)) (\ varstup . let ((error : real), (result : 32 bits)) = varstup in sail2_state_monad$seqS + (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS ((words$w2w result : 'N words$word)))))))))))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS (((op <> (realFromFrac(( 0 : int))(( 10 : int)))))) "")) + (sail2_state_monad$assert_expS (((rounding <> FPRounding_TIEAWAY))) "")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (F_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (E_mut : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (minimum_exp : ii) . + let minimum_exp = (~ (( 1022 : int):ii)) in + let E_mut = ((( 11 : int):ii)) in + let F_mut = ((( 52 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (undefined_real () )) (\ (mantissa : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . + let ((mantissa : real), (sign : 1 bits)) = + (if ((op < (realFromFrac(( 0 : int))(( 10 : int))))) then + let (sign : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + let (mantissa : real) =((real_of_num 0) - op) in + (mantissa, sign) + else + let (sign : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (mantissa : real) = op in + (mantissa, sign)) in + let (exponent : ii) = ((( 0 : int):ii)) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa < (realFromFrac(( 10 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa * (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) - (( 1 : int):ii)) in + (exponent, mantissa))) in + let ((exponent : ii), (mantissa : real)) = + (while (exponent, mantissa) + (\ varstup . let (exponent, mantissa) = varstup in mantissa >= (realFromFrac(( 20 : int))(( 10 : int)))) + (\ varstup . let (exponent, mantissa) = varstup in + let (mantissa : real) = (mantissa / (realFromFrac(( 20 : int))(( 10 : int)))) in + let (exponent : ii) = (((ex_int exponent)) + (( 1 : int):ii)) in + (exponent, mantissa))) in + if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ T))) \/ (((((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ F)))))) /\ ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__16 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__16 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSCR_ref : ( 32 words$word) M) (\ (w__17 : 32 words$word) . + sail2_state_monad$write_regS + FPSCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__17 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . + sail2_state_monad$write_regS + FPSR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__18 (( 3 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)))) + (FPZero (( 64 : int):ii) sign : ( 'N words$word) M)) (\ (w__19 : 'N words$word) . + sail2_state_monad$returnS ((words$w2w w__19 : 'N words$word)))) + else + let (biased_exp : ii) = + (int_max ((((((ex_int exponent)) - ((ex_int minimum_exp)))) + (( 1 : int):ii))) + (( 0 : int):ii)) in + let (mantissa : real) = + (if (((((ex_int biased_exp)) = (( 0 : int):ii)))) then + mantissa / + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) + ((((ex_int minimum_exp)) - ((ex_int exponent)))))) + else mantissa) in + let (int_mant : ii) = + (flr ((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 52 : int):ii)))))) in + let (error : real) = + (((mantissa * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 52 : int):ii))))) - + (((real_of_int int_mant)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((((((ex_int biased_exp)) = (( 0 : int):ii)))) /\ ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) \/ ((((vec_of_bits [access_vec_dec fpcr (( 11 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))))) then + FPProcessException FPExc_Underflow fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$undefined_boolS () )) (\ (overflow_to_inf : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . + let ((overflow_to_inf : bool), (round_up : bool)) = + ((case rounding of + FPRounding_TIEEVEN => + let (round_up : bool) = + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) int_mant (( 0 : int):ii) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))) in + let (overflow_to_inf : bool) = T in + (overflow_to_inf, round_up) + | FPRounding_POSINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B0] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B0] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_NEGINF => + let (round_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((sign = (vec_of_bits [B1] : 1 words$word))))) in + let (overflow_to_inf : bool) = (sign = (vec_of_bits [B1] : 1 words$word)) in + (overflow_to_inf, round_up) + | FPRounding_ZERO => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + | FPRounding_ODD => + let (round_up : bool) = F in + let (overflow_to_inf : bool) = F in + (overflow_to_inf, round_up) + )) in + let ((biased_exp : ii), (int_mant : ii)) = + (if round_up then + let (int_mant : ii) = (((ex_int int_mant)) + (( 1 : int):ii)) in + let (biased_exp : ii) = + (if (((((ex_int int_mant)) = ((pow2 (( 52 : int):ii)))))) then (( 1 : int):ii) + else biased_exp) in + let ((biased_exp : ii), (int_mant : ii)) = + (if (((((ex_int int_mant)) = ((pow2 (( 53 : int):ii)))))) then + let (biased_exp : ii) = (((ex_int biased_exp)) + (( 1 : int):ii)) in + let (int_mant : ii) = (((ex_int int_mant)) / (( 2 : int):ii)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + (biased_exp, int_mant) + else (biased_exp, int_mant)) in + let (int_mant : ii) = + (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ (((rounding = FPRounding_ODD)))))) then + set_slice_int (( 1 : int):ii) int_mant (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + else int_mant) in sail2_state_monad$bindS + (if ((((ex_int biased_exp)) >= ((((pow2 (( 11 : int):ii))) - (( 1 : int):ii))))) then sail2_state_monad$bindS + (if overflow_to_inf then (FPInfinity (( 64 : int):ii) sign : ( 64 words$word) M) + else (FPMaxNormal (( 64 : int):ii) sign : ( 64 words$word) M)) (\ (w__22 : 64 words$word) . + let result = w__22 in sail2_state_monad$seqS + (FPProcessException FPExc_Overflow fpcr) + (let (error : real) = (realFromFrac(( 10 : int))(( 10 : int))) in + sail2_state_monad$returnS (error, result))) + else + let (result : 64 bits) = + ((concat_vec + ((concat_vec sign + ((GetSlice_int + ((make_the_value (((((( 64 : int):ii) - (( 52 : int):ii))) - (( 1 : int):ii))) + : 11 itself)) biased_exp (( 0 : int):ii) + : 11 words$word)) + : 12 words$word)) + ((GetSlice_int ((make_the_value (( 52 : int):ii) : 52 itself)) int_mant (( 0 : int):ii) + : 52 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS (error, result)) (\ varstup . let ((error : real), (result : 64 bits)) = varstup in sail2_state_monad$seqS + (if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS ((words$w2w result : 'N words$word)))))))))))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "") (sail2_state_monad$exitS () )))`; + + +(*val FPRoundCV : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +val _ = Define ` + ((FPRoundCV:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr__arg rounding= + (let fpcr = fpcr__arg in + let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 19 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)) in + (FPRoundBase N__tv op fpcr rounding : ( 'N words$word) M)))`; + + +(*val FPRound__0 : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) + +(*val FPRound__1 : forall 'N . Size 'N => integer -> real -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPRound__0:int -> real ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr__arg rounding= + (let fpcr = fpcr__arg in + let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 26 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)) in + (FPRoundBase N__tv op fpcr rounding : ( 'N words$word) M)))`; + + +val _ = Define ` + ((FPRound__1:int -> real ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr= + ((FPRound__0 N__tv op fpcr ((FPRoundingMode fpcr)) : ( 'N words$word) M)))`; + + +(*val FixedToFP : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'N)*) + +val _ = Define ` + ((FixedToFP:int -> 'M words$word -> int -> bool ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fbits unsigned fpcr rounding= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((N__tv = (( 16 : int):ii)))) \/ ((((((N__tv = (( 32 : int):ii)))) \/ (((N__tv = (( 64 : int):ii)))))))))) "") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "")) + (undefined_bitvector N__tv : ( 'N words$word) M)) (\ (result : 'N bits) . sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((fbits >= (( 0 : int):ii))) "") + (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) "")) + (let (int_operand : ii) = (asl_Int op unsigned) in + let (real_operand : real) = + ((((real_of_int int_operand))) / ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) fbits))) in + if (((real_operand = (realFromFrac(( 0 : int))(( 10 : int)))))) then + (FPZero ((int_of_num (words$word_len result))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) + else (FPRound__0 ((int_of_num (words$word_len result))) real_operand fpcr rounding : ( 'N words$word) M)))))`; + + +(*val FPProcessNaN : forall 'N . Size 'N => FPType -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPProcessNaN:FPType -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ op fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$assert_expS ((((((typ = FPType_QNaN))) \/ (((typ = FPType_SNaN)))))) "((type == FPType_QNaN) || (type == FPType_SNaN))")) + (undefined_int () )) (\ (topfrac : ii) . + let p0_ = (int_of_num (words$word_len op)) in + let (topfrac : ii) = + (if (((p0_ = (( 16 : int):ii)))) then + let (op : 16 words$word) = ((words$w2w op : 16 words$word)) in + (( 9 : int):ii) + else if (((p0_ = (( 32 : int):ii)))) then + let (op : 32 words$word) = ((words$w2w op : 32 words$word)) in + (( 22 : int):ii) + else + let (op : 64 words$word) = ((words$w2w op : 64 words$word)) in + (( 51 : int):ii)) in + let (result : 'N bits) = op in sail2_state_monad$bindS + (if (((typ = FPType_SNaN))) then + let result = + ((set_slice ((int_of_num (words$word_len op))) (( 1 : int):ii) result topfrac (vec_of_bits [B1] : 1 words$word) : 'N words$word)) in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result) + else sail2_state_monad$returnS result) (\ (result : 'N bits) . + if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (FPDefaultNaN ((int_of_num (words$word_len op))) () : ( 'N words$word) M) + else sail2_state_monad$returnS result))))`; + + +(*val FPProcessNaNs3 : forall 'N . Size 'N => FPType -> FPType -> FPType -> mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*) + +val _ = Define ` + ((FPProcessNaNs3:FPType -> FPType -> FPType -> 'N words$word -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#'N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) type1 type2 type3 op1 op2 op3 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M)) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . + if (((type1 = FPType_SNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type1 op1 fpcr : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let (result : 'N bits) = w__0 in + sail2_state_monad$returnS (done, result)) + else if (((type2 = FPType_SNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type2 op2 fpcr : ( 'N words$word) M) (\ (w__1 : 'N bits) . + let (result : 'N bits) = w__1 in + sail2_state_monad$returnS (done, result)) + else if (((type3 = FPType_SNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type3 op3 fpcr : ( 'N words$word) M) (\ (w__2 : 'N bits) . + let (result : 'N bits) = w__2 in + sail2_state_monad$returnS (done, result)) + else if (((type1 = FPType_QNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type1 op1 fpcr : ( 'N words$word) M) (\ (w__3 : 'N bits) . + let (result : 'N bits) = w__3 in + sail2_state_monad$returnS (done, result)) + else if (((type2 = FPType_QNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type2 op2 fpcr : ( 'N words$word) M) (\ (w__4 : 'N bits) . + let (result : 'N bits) = w__4 in + sail2_state_monad$returnS (done, result)) + else if (((type3 = FPType_QNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type3 op3 fpcr : ( 'N words$word) M) (\ (w__5 : 'N bits) . + let (result : 'N bits) = w__5 in + sail2_state_monad$returnS (done, result)) + else + let (done : bool) = F in + let (result : 'N bits) = ((Zeros__1 ((int_of_num (words$word_len op1))) () : 'N words$word)) in + sail2_state_monad$returnS (done, result)))))`; + + +(*val FPProcessNaNs : forall 'N . Size 'N => FPType -> FPType -> mword 'N -> mword 'N -> mword ty32 -> M (bool * mword 'N)*) + +val _ = Define ` + ((FPProcessNaNs:FPType -> FPType -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#'N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) type1 type2 op1 op2 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M)) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . + if (((type1 = FPType_SNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type1 op1 fpcr : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let (result : 'N bits) = w__0 in + sail2_state_monad$returnS (done, result)) + else if (((type2 = FPType_SNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type2 op2 fpcr : ( 'N words$word) M) (\ (w__1 : 'N bits) . + let (result : 'N bits) = w__1 in + sail2_state_monad$returnS (done, result)) + else if (((type1 = FPType_QNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type1 op1 fpcr : ( 'N words$word) M) (\ (w__2 : 'N bits) . + let (result : 'N bits) = w__2 in + sail2_state_monad$returnS (done, result)) + else if (((type2 = FPType_QNaN))) then + let done = T in sail2_state_monad$bindS + (FPProcessNaN type2 op2 fpcr : ( 'N words$word) M) (\ (w__3 : 'N bits) . + let (result : 'N bits) = w__3 in + sail2_state_monad$returnS (done, result)) + else + let (done : bool) = F in + let (result : 'N bits) = ((Zeros__1 ((int_of_num (words$word_len op1))) () : 'N words$word)) in + sail2_state_monad$returnS (done, result)))))`; + + +(*val CurrentInstrSet : unit -> M InstrSet*) + +val _ = Define ` + ((CurrentInstrSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((InstrSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_InstrSet () ) (\ (result : InstrSet) . sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let (result : InstrSet) = + (if (((w__1.ProcState_T = (vec_of_bits [B0] : 1 words$word)))) then InstrSet_A32 + else InstrSet_T32) in + sail2_state_monad$returnS result) + else sail2_state_monad$returnS InstrSet_A64))))`; + + +(*val AArch32_ExecutingLSMInstr : unit -> M bool*) + +val _ = Define ` + ((AArch32_ExecutingLSMInstr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (ThisInstr0 () : ( 32 words$word) M) (\ (instr : 32 bits) . sail2_state_monad$bindS + (CurrentInstrSet () ) (\ (instr_set : InstrSet) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((instr_set = InstrSet_A32))) \/ (((instr_set = InstrSet_T32)))))) "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))") + (if (((instr_set = InstrSet_A32))) then + sail2_state_monad$returnS ((((((((slice instr (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) <> (vec_of_bits [B1;B1;B1;B1] : 4 words$word)))) /\ (((((slice instr (( 25 : int):ii) (( 3 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) + else sail2_state_monad$bindS + (ThisInstrLength () ) (\ (w__0 : ii) . + sail2_state_monad$returnS (if (((((ex_int w__0)) = (( 16 : int):ii)))) then + (((slice instr (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B1;B0;B0] : 4 words$word)) + else + ((((((slice instr (( 25 : int):ii) (( 7 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0] : 7 words$word)))) /\ ((((vec_of_bits [access_vec_dec instr (( 22 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))))))))`; + + +(*val AArch32_ExecutingCP10or11Instr : unit -> M bool*) + +val _ = Define ` + ((AArch32_ExecutingCP10or11Instr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (ThisInstr0 () : ( 32 words$word) M) (\ (instr : 32 bits) . sail2_state_monad$bindS + (CurrentInstrSet () ) (\ (instr_set : InstrSet) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((instr_set = InstrSet_A32))) \/ (((instr_set = InstrSet_T32)))))) "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))") + (sail2_state_monad$returnS (if (((instr_set = InstrSet_A32))) then + (((((((((slice instr (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B1;B1;B0] : 4 words$word)))) \/ (((((slice instr (( 25 : int):ii) (( 3 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) /\ (((((and_vec ((slice instr (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) + (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 4 words$word)) = (vec_of_bits [B1;B0;B1;B0] : 4 words$word))))) + else + (((((((((and_vec ((slice instr (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) + (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 4 words$word)) = (vec_of_bits [B1;B1;B1;B0] : 4 words$word)))) /\ ((((((((slice instr (( 24 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B1;B1;B0] : 4 words$word)))) \/ (((((slice instr (( 25 : int):ii) (( 3 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))))))))) /\ (((((and_vec ((slice instr (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) + (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 4 words$word)) = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))))))))))`; + + +(*val HaveAnyAArch64 : unit -> bool*) + +val _ = Define ` + ((HaveAnyAArch64:unit -> bool) () = (~ ((HighestELUsingAArch32 () ))))`; + + +(*val AArch32_ReportDeferredSError : mword ty2 -> mword ty1 -> M (mword ty32)*) + +val _ = Define ` + ((AArch32_ReportDeferredSError:(2)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) AET ExT= (sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (target : 32 bits) . + let (target : 32 bits) = + ((set_slice (( 32 : int):ii) (( 1 : int):ii) target (( 31 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word)) in + let (syndrome : 16 bits) = ((Zeros__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (if (((w__0.ProcState_EL = EL2))) then + let (syndrome : 16 bits) = + ((update_subrange_vec_dec syndrome (( 11 : int):ii) (( 10 : int):ii) AET : 16 words$word)) in + let (syndrome : 16 bits) = + ((update_subrange_vec_dec syndrome (( 9 : int):ii) (( 9 : int):ii) ExT : 16 words$word)) in + let (syndrome : 16 bits) = + ((update_subrange_vec_dec syndrome (( 5 : int):ii) (( 0 : int):ii) + (vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word) + : 16 words$word)) in + sail2_state_monad$returnS syndrome + else + let syndrome = ((update_subrange_vec_dec syndrome (( 15 : int):ii) (( 14 : int):ii) AET : 16 words$word)) in + let syndrome = ((update_subrange_vec_dec syndrome (( 12 : int):ii) (( 12 : int):ii) ExT : 16 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS TTBCR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + let syndrome = + ((update_subrange_vec_dec syndrome (( 9 : int):ii) (( 9 : int):ii) + (vec_of_bits [access_vec_dec w__1 (( 31 : int):ii)] : 1 words$word) + : 16 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS TTBCR_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + let (syndrome : 16 bits) = + (if ((((vec_of_bits [access_vec_dec w__2 (( 31 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (update_subrange_vec_dec syndrome (( 5 : int):ii) (( 0 : int):ii) + (vec_of_bits [B0;B1;B0;B0;B0;B1] : 6 words$word) + : 16 words$word) + else + let (tup__0, tup__1) = + ((vec_of_bits [B1] : 1 words$word), (vec_of_bits [B0;B1;B1;B0] : 4 words$word)) in + let (syndrome : 16 bits) = + ((update_subrange_vec_dec syndrome (( 10 : int):ii) (( 10 : int):ii) tup__0 : 16 words$word)) in + (update_subrange_vec_dec syndrome (( 3 : int):ii) (( 0 : int):ii) tup__1 : 16 words$word)) in + sail2_state_monad$returnS syndrome))) (\ (syndrome : 16 bits) . + if ((HaveAnyAArch64 () )) then sail2_state_monad$bindS + (ZeroExtend__0 syndrome ((make_the_value (( 25 : int):ii) : 25 itself)) : ( 25 words$word) M) (\ (w__3 : + 25 words$word) . + let (target : 32 bits) = ((update_subrange_vec_dec target (( 24 : int):ii) (( 0 : int):ii) w__3 : 32 words$word)) in + sail2_state_monad$returnS target) + else + let (target : 32 bits) = + ((update_subrange_vec_dec target (( 15 : int):ii) (( 0 : int):ii) syndrome : 32 words$word)) in + sail2_state_monad$returnS target)))))`; + + +(*val HaveAArch32EL : mword ty2 -> bool*) + +val _ = Define ` + ((HaveAArch32EL:(2)words$word -> bool) el= + (if ((~ ((HaveEL el)))) then F + else if ((~ ((HaveAnyAArch32 () )))) then F + else if ((HighestELUsingAArch32 () )) then T + else if (((el = ((HighestEL () : 2 words$word))))) then F + else if (((el = EL0))) then T + else T))`; + + +(*val AArch64_ResetSpecialRegisters : unit -> M unit*) + +val _ = Define ` + ((AArch64_ResetSpecialRegisters:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL0_ref w__0) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__1 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL1_ref w__1) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__2 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL1_ref w__2) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__3 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_EL1_ref w__3) + (if ((HaveEL EL2)) then sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__4 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL2_ref w__4) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__5 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL2_ref w__5) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__6 : 64 bits) . + sail2_state_monad$write_regS ELR_EL2_ref w__6))) + else sail2_state_monad$returnS () )) + (if ((HaveEL EL3)) then sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__7 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL3_ref w__7) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__8 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL3_ref w__8) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__9 : 64 bits) . + sail2_state_monad$write_regS ELR_EL3_ref w__9))) + else sail2_state_monad$returnS () )) + (if ((HaveAArch32EL EL1)) then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__10 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_fiq_ref w__10) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__11 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_irq_ref w__11) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__12 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_abt_ref w__12) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__13 : 32 bits) . + sail2_state_monad$write_regS SPSR_und_ref w__13)))) + else sail2_state_monad$returnS () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__14 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_EL0_ref w__14) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__15 : 32 bits) . + sail2_state_monad$write_regS DSPSR_EL0_ref w__15))))))))`; + + +(*val Halted : unit -> M bool*) + +val _ = Define ` + ((Halted:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS (((((slice w__0 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (((((slice w__1 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) (\ (w__2 : bool) . + sail2_state_monad$returnS ((~ w__2)))))`; + + +(*val FPUnpackBase : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +val _ = Define ` + ((FPUnpackBase:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len fpval))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len fpval))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len fpval))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M)) (\ (frac64 : 52 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 11 : int):ii) : ( 11 words$word) M) (\ (exp64 : 11 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 23 : int):ii) : ( 23 words$word) M) (\ (frac32 : 23 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (exp32 : 8 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (undefined_bitvector (( 10 : int):ii) : ( 10 words$word) M) (\ (frac16 : 10 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 5 : int):ii) : ( 5 words$word) M) (\ (exp16 : 5 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (if (((((int_of_num (words$word_len fpval))) = (( 16 : int):ii)))) then + let (sign : 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 : int):ii)] : 1 words$word)) in + let (exp16 : 5 bits) = ((slice fpval (( 10 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (frac16 : 10 bits) = ((slice fpval (( 0 : int):ii) (( 10 : int):ii) : 10 words$word)) in + let ((typ : FPType), (value_name : real)) = + (if ((IsZero exp16)) then + let ((typ : FPType), (value_name : real)) = + (if (((((IsZero frac16)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let (typ : FPType) = FPType_Zero in + let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in + (typ, value_name) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 14 : int):ii))))) * + (((((real_of_int ((lem$w2ui frac16))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 10 : int):ii)))))))) in + (typ, value_name)) in + (typ, value_name) + else + let ((typ : FPType), (value_name : real)) = + (if (((((IsOnes exp16)) /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + let ((typ : FPType), (value_name : real)) = + (if ((IsZero frac16)) then + let (typ : FPType) = FPType_Infinity in + let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in + (typ, value_name) + else + let (typ : FPType) = + (if ((((vec_of_bits [access_vec_dec frac16 (( 9 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + FPType_QNaN + else FPType_SNaN) in + let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in + (typ, value_name)) in + (typ, value_name) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp16)) - (( 15 : int):ii))))) + * + (((realFromFrac(( 10 : int))(( 10 : int))) + + (((((real_of_int ((lem$w2ui frac16))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 10 : int):ii)))))))))) in + (typ, value_name)) in + (typ, value_name)) in + sail2_state_monad$returnS (sign, typ, value_name) + else if (((((int_of_num (words$word_len fpval))) = (( 32 : int):ii)))) then + let sign = ((vec_of_bits [access_vec_dec fpval (( 31 : int):ii)] : 1 words$word)) in + let exp32 = ((slice fpval (( 23 : int):ii) (( 8 : int):ii) : 8 words$word)) in + let frac32 = ((slice fpval (( 0 : int):ii) (( 23 : int):ii) : 23 words$word)) in sail2_state_monad$bindS + (if ((IsZero exp32)) then + if (((((IsZero frac32)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let typ = FPType_Zero in + let value_name = (realFromFrac(( 0 : int))(( 10 : int))) in sail2_state_monad$seqS + (if ((~ ((IsZero frac32)))) then FPProcessException FPExc_InputDenorm fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS (typ, value_name)) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 126 : int):ii))))) * + (((((real_of_int ((lem$w2ui frac32))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 23 : int):ii)))))))) in + sail2_state_monad$returnS (typ, value_name) + else + let ((typ : FPType), (value_name : real)) = + (if ((IsOnes exp32)) then + let ((typ : FPType), (value_name : real)) = + (if ((IsZero frac32)) then + let (typ : FPType) = FPType_Infinity in + let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in + (typ, value_name) + else + let (typ : FPType) = + (if ((((vec_of_bits [access_vec_dec frac32 (( 22 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + FPType_QNaN + else FPType_SNaN) in + let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in + (typ, value_name)) in + (typ, value_name) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp32)) - (( 127 : int):ii))))) + * + (((realFromFrac(( 10 : int))(( 10 : int))) + + (((((real_of_int ((lem$w2ui frac32))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 23 : int):ii)))))))))) in + (typ, value_name)) in + sail2_state_monad$returnS (typ, value_name)) (\ varstup . let ((typ : FPType), (value_name : real)) = varstup in + sail2_state_monad$returnS (sign, typ, value_name)) + else + let sign = ((vec_of_bits [access_vec_dec fpval (( 63 : int):ii)] : 1 words$word)) in + let exp64 = ((slice fpval (( 52 : int):ii) (( 11 : int):ii) : 11 words$word)) in + let frac64 = ((slice fpval (( 0 : int):ii) (( 52 : int):ii) : 52 words$word)) in sail2_state_monad$bindS + (if ((IsZero exp64)) then + if (((((IsZero frac64)) \/ ((((vec_of_bits [access_vec_dec fpcr (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let typ = FPType_Zero in + let value_name = (realFromFrac(( 0 : int))(( 10 : int))) in sail2_state_monad$seqS + (if ((~ ((IsZero frac64)))) then FPProcessException FPExc_InputDenorm fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS (typ, value_name)) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 1022 : int):ii))))) * + (((((real_of_int ((lem$w2ui frac64))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 52 : int):ii)))))))) in + sail2_state_monad$returnS (typ, value_name) + else + let ((typ : FPType), (value_name : real)) = + (if ((IsOnes exp64)) then + let ((typ : FPType), (value_name : real)) = + (if ((IsZero frac64)) then + let (typ : FPType) = FPType_Infinity in + let (value_name : real) = (realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) (( 1000000 : int):ii)) in + (typ, value_name) + else + let (typ : FPType) = + (if ((((vec_of_bits [access_vec_dec frac64 (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + FPType_QNaN + else FPType_SNaN) in + let (value_name : real) = (realFromFrac(( 0 : int))(( 10 : int))) in + (typ, value_name)) in + (typ, value_name) + else + let (typ : FPType) = FPType_Nonzero in + let (value_name : real) = + (((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((((lem$w2ui exp64)) - (( 1023 : int):ii))))) + * + (((realFromFrac(( 10 : int))(( 10 : int))) + + (((((real_of_int ((lem$w2ui frac64))))) * + ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) ((~ (( 52 : int):ii)))))))))) in + (typ, value_name)) in + sail2_state_monad$returnS (typ, value_name)) (\ varstup . let ((typ : FPType), (value_name : real)) = varstup in + sail2_state_monad$returnS (sign, typ, value_name))) (\ varstup . let ((sign : 1 bits), (typ : FPType), (value_name : + real)) = varstup in + let (value_name : real) = + (if (((sign = (vec_of_bits [B1] : 1 words$word)))) then(real_of_num 0) - value_name + else value_name) in + sail2_state_monad$returnS (typ, sign, value_name)))))))))))))`; + + +(*val FPUnpackCV : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +val _ = Define ` + ((FPUnpackCV:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr__arg= + (let fpcr = fpcr__arg in + let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 19 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)) in sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (fp_type : FPType) . sail2_state_monad$bindS + (FPUnpackBase fpval fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let (fp_type : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + sail2_state_monad$returnS (fp_type, sign, value_name)))))))`; + + +(*val FPConvert__0 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> FPRounding -> M (mword 'M)*) + +(*val FPConvert__1 : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> mword ty32 -> M (mword 'M)*) + +val _ = Define ` + ((FPConvert__0:int -> 'N words$word ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fpcr rounding= + (let p0_ = M__tv in + if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpackCV op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in + let (alt_hp : bool) = + (T /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) in sail2_state_monad$bindS + (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS + (if alt_hp then (FPZero (( 16 : int):ii) sign : ( 16 words$word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (FPDefaultNaN (( 16 : int):ii) () : ( 16 words$word) M) + else (FPConvertNaN (( 16 : int):ii) op : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$seqS + (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result)) + else if (((typ = FPType_Infinity))) then + if alt_hp then + let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 16 : int):ii) - (( 1 : int):ii))) : 15 itself)) + : 15 words$word)) + : 16 words$word)) in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result) + else (FPInfinity (( 16 : int):ii) sign : ( 16 words$word) M) + else if (((typ = FPType_Zero))) then (FPZero (( 16 : int):ii) sign : ( 16 words$word) M) + else (FPRoundCV (( 16 : int):ii) value_name fpcr rounding : ( 16 words$word) M)) (\ (result : 16 + bits) . + sail2_state_monad$returnS ((words$w2w result : 'M words$word)))))))) + else if (((p0_ = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpackCV op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in + let (alt_hp : bool) = + (F /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) in sail2_state_monad$bindS + (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS + (if alt_hp then (FPZero (( 32 : int):ii) sign : ( 32 words$word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (FPDefaultNaN (( 32 : int):ii) () : ( 32 words$word) M) + else (FPConvertNaN (( 32 : int):ii) op : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$seqS + (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result)) + else if (((typ = FPType_Infinity))) then + if alt_hp then + let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 : int):ii) - (( 1 : int):ii))) : 31 itself)) + : 31 words$word)) + : 32 words$word)) in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result) + else (FPInfinity (( 32 : int):ii) sign : ( 32 words$word) M) + else if (((typ = FPType_Zero))) then (FPZero (( 32 : int):ii) sign : ( 32 words$word) M) + else (FPRoundCV (( 32 : int):ii) value_name fpcr rounding : ( 32 words$word) M)) (\ (result : 32 + bits) . + sail2_state_monad$returnS ((words$w2w result : 'M words$word)))))))) + else if (((p0_ = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpackCV op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in + let (alt_hp : bool) = + (F /\ ((((vec_of_bits [access_vec_dec fpcr (( 26 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) in sail2_state_monad$bindS + (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$bindS + (if alt_hp then (FPZero (( 64 : int):ii) sign : ( 64 words$word) M) + else if ((((vec_of_bits [access_vec_dec fpcr (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (FPDefaultNaN (( 64 : int):ii) () : ( 64 words$word) M) + else (FPConvertNaN (( 64 : int):ii) op : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$seqS + (if ((((((typ = FPType_SNaN))) \/ alt_hp))) then FPProcessException FPExc_InvalidOp fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result)) + else if (((typ = FPType_Infinity))) then + if alt_hp then + let result = + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 : int):ii) - (( 1 : int):ii))) : 63 itself)) + : 63 words$word)) + : 64 words$word)) in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result) + else (FPInfinity (( 64 : int):ii) sign : ( 64 words$word) M) + else if (((typ = FPType_Zero))) then (FPZero (( 64 : int):ii) sign : ( 64 words$word) M) + else (FPRoundCV (( 64 : int):ii) value_name fpcr rounding : ( 64 words$word) M)) (\ (result : 64 + bits) . + sail2_state_monad$returnS ((words$w2w result : 'M words$word)))))))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "") (sail2_state_monad$exitS () )))`; + + +val _ = Define ` + ((FPConvert__1:int -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fpcr= + ((FPConvert__0 M__tv op fpcr ((FPRoundingMode fpcr)) : ( 'M words$word) M)))`; + + +(*val FPUnpack : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (FPType * mword ty1 * real)*) + +val _ = Define ` + ((FPUnpack:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((FPType#(1)words$word#real),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fpval fpcr__arg= + (let fpcr = fpcr__arg in + let fpcr = ((set_slice (( 32 : int):ii) (( 1 : int):ii) fpcr (( 26 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)) in sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (fp_type : FPType) . sail2_state_monad$bindS + (FPUnpackBase fpval fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let (fp_type : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + sail2_state_monad$returnS (fp_type, sign, value_name)))))))`; + + +(*val FPToFixedJS : forall 'M 'N . Size 'M, Size 'N => integer -> mword 'M -> mword ty32 -> bool -> M (mword 'N)*) + +val _ = Define ` + ((FPToFixedJS:int -> 'M words$word ->(32)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (N__tv : int) op fpcr Is64= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 64 : int):ii)))) /\ (((N__tv = (( 32 : int):ii))))))) "((M == 64) && (N == 32))") + (undefined_real () )) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpack op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in + let (Z : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) + (let (Z : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS Z) + else sail2_state_monad$returnS Z) (\ (Z : 1 bits) . + let (int_result : ii) = (flr value_name) in + let (error : real) = (value_name - (((real_of_int int_result)))) in + let (round_it_up : bool) = + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii)))) in + let (int_result : ii) = + (if round_it_up then ((ex_int int_result)) + (( 1 : int):ii) + else int_result) in sail2_state_monad$bindS + (undefined_int () ) (\ (result : ii) . + let (result : ii) = + (if ((((ex_int int_result)) < (( 0 : int):ii))) then + ((ex_int int_result)) - + ((((pow2 (( 32 : int):ii))) * + ((ex_int + ((clg + (((((real_of_int int_result))) / (((real_of_int ((pow2 (( 32 : int):ii)))))))))))))) + else + ((ex_int int_result)) - + ((((pow2 (( 32 : int):ii))) * + ((ex_int + ((flr + (((((real_of_int int_result))) / (((real_of_int ((pow2 (( 32 : int):ii))))))))))))))) in sail2_state_monad$bindS + (if (((((((ex_int int_result)) < ((~ ((pow2 (( 31 : int):ii))))))) \/ ((((ex_int int_result)) > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) + (let (Z : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS Z) + else if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then sail2_state_monad$seqS + (FPProcessException FPExc_Inexact fpcr) + (let (Z : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS Z) + else sail2_state_monad$returnS Z) (\ (Z : 1 bits) . + let (Z : 1 bits) = + (if ((((((sign = (vec_of_bits [B1] : 1 words$word)))) /\ (((value_name = (realFromFrac(( 0 : int))(( 10 : int))))))))) then + (vec_of_bits [B0] : 1 words$word) + else Z) in + let (result : ii) = (if (((typ = FPType_Infinity))) then (( 0 : int):ii) else result) in sail2_state_monad$seqS + (if Is64 then + let split_vec = + ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) Z : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_V := tup__3|>))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPSCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + sail2_state_monad$write_regS + FPSCR_ref + ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__4 (( 28 : int):ii) + ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) Z : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word)) + : 32 words$word)))) + (sail2_state_monad$returnS ((words$w2w + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 'N itself)) result (( 0 : int):ii) : 'N words$word)) + : 'N words$word))))))))))))`; + + +(*val FPToFixed : forall 'N 'M . Size 'M, Size 'N => integer -> mword 'N -> ii -> bool -> mword ty32 -> FPRounding -> M (mword 'M)*) + +val _ = Define ` + ((FPToFixed:int -> 'N words$word -> int -> bool ->(32)words$word -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->((('M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) op fbits unsigned fpcr rounding= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (sail2_state_monad$assert_expS ((((((M__tv = (( 16 : int):ii)))) \/ ((((((M__tv = (( 32 : int):ii)))) \/ (((M__tv = (( 64 : int):ii)))))))))) "((M == 16) || ((M == 32) || (M == 64)))")) + (sail2_state_monad$assert_expS ((fbits >= (( 0 : int):ii))) "(fbits >= 0)")) + (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) "(rounding != FPRounding_ODD)")) + (undefined_real () )) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpack op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in sail2_state_monad$seqS + (if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then + FPProcessException FPExc_InvalidOp fpcr + else sail2_state_monad$returnS () ) + (let value_name = (value_name * ((realPowInteger (realFromFrac(( 20 : int))(( 10 : int))) fbits))) in + let (int_result : ii) = (flr value_name) in + let (error : real) = (value_name - (((real_of_int int_result)))) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . + let (round_up : bool) = + ((case rounding of + FPRounding_TIEEVEN => + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) int_result (( 0 : int):ii) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))) + | FPRounding_POSINF => (error <> (realFromFrac(( 0 : int))(( 10 : int)))) + | FPRounding_NEGINF => F + | FPRounding_ZERO => + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii)))) + | FPRounding_TIEAWAY => + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) >= (( 0 : int):ii))))))) + )) in + let (int_result : ii) = (if round_up then ((ex_int int_result)) + (( 1 : int):ii) else int_result) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (overflow : bool) . sail2_state_monad$bindS + (undefined_bitvector M__tv : ( 'M words$word) M) (\ (result : 'M bits) . sail2_state_monad$bindS + (SatQ int_result ((make_the_value ((int_of_num (words$word_len result))) : 'M itself)) unsigned + : (( 'M words$word # bool)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let result = tup__0 in + let overflow = tup__1 in sail2_state_monad$seqS + (if overflow then FPProcessException FPExc_InvalidOp fpcr + else if (((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) then FPProcessException FPExc_Inexact fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result))))))))))))`; + + +(*val FPSqrt : forall 'N . Size 'N => mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPSqrt:'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpack op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op))) : ( 'N words$word) M) (\ (result : 'N bits) . + if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then + (FPProcessNaN typ op fpcr : ( 'N words$word) M) + else if (((typ = FPType_Zero))) then (FPZero ((int_of_num (words$word_len op))) sign : ( 'N words$word) M) + else if ((((((typ = FPType_Infinity))) /\ (((sign = (vec_of_bits [B0] : 1 words$word))))))) + then + (FPInfinity ((int_of_num (words$word_len op))) sign : ( 'N words$word) M) + else if (((sign = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len op))) () : ( 'N words$word) M) (\ (w__3 : 'N bits) . + let result = w__3 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else (FPRound__1 ((int_of_num (words$word_len op))) ((sqrt value_name)) fpcr : ( 'N words$word) M))))))))`; + + +(*val FPRoundInt : forall 'N . Size 'N => mword 'N -> mword ty32 -> FPRounding -> bool -> M (mword 'N)*) + +val _ = Define ` + ((FPRoundInt:'N words$word ->(32)words$word -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op fpcr rounding exact= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((rounding <> FPRounding_ODD))) "(rounding != FPRounding_ODD)") + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))")) + (undefined_real () )) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . sail2_state_monad$bindS + (FPUnpack op fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typ = tup__0 in + let sign = tup__1 in + let value_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (real_result : real) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (round_up : bool) . sail2_state_monad$bindS + (undefined_real () ) (\ (error : real) . sail2_state_monad$bindS + (undefined_int () ) (\ (int_result : ii) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op))) : ( 'N words$word) M) (\ (result : 'N bits) . + if ((((((typ = FPType_SNaN))) \/ (((typ = FPType_QNaN)))))) then + (FPProcessNaN typ op fpcr : ( 'N words$word) M) + else if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op))) sign : ( 'N words$word) M) + else if (((typ = FPType_Zero))) then (FPZero ((int_of_num (words$word_len op))) sign : ( 'N words$word) M) + else + let int_result = (flr value_name) in + let error = (value_name - (((real_of_int int_result)))) in + let (round_up : bool) = + ((case rounding of + FPRounding_TIEEVEN => + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) int_result (( 0 : int):ii) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))) + | FPRounding_POSINF => (error <> (realFromFrac(( 0 : int))(( 10 : int)))) + | FPRounding_NEGINF => F + | FPRounding_ZERO => + ((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) < (( 0 : int):ii)))) + | FPRounding_TIEAWAY => + (((error > (realFromFrac(( 5 : int))(( 10 : int))))) \/ ((((((error = (realFromFrac(( 5 : int))(( 10 : int)))))) /\ ((((ex_int int_result)) >= (( 0 : int):ii))))))) + )) in + let (int_result : ii) = + (if round_up then ((ex_int int_result)) + (( 1 : int):ii) + else int_result) in + let real_result = ((real_of_int int_result)) in sail2_state_monad$bindS + (if (((real_result = (realFromFrac(( 0 : int))(( 10 : int)))))) then (FPZero ((int_of_num (words$word_len op))) sign : ( 'N words$word) M) + else (FPRound__0 ((int_of_num (words$word_len op))) real_result fpcr FPRounding_ZERO : ( 'N words$word) M)) (\ (result : 'N + bits) . sail2_state_monad$seqS + (if ((((((error <> (realFromFrac(( 0 : int))(( 10 : int)))))) /\ exact))) then + FPProcessException FPExc_Inexact fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result)))))))))))))`; + + +(*val FPCompare : forall 'N . Size 'N => mword 'N -> mword 'N -> bool -> mword ty32 -> M (mword ty4)*) + +val _ = Define ` + ((FPCompare:'N words$word -> 'N words$word -> bool ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((4)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 signal_nans fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (result : 4 bits) . + if ((((((((((((type1 = FPType_SNaN))) \/ (((type1 = FPType_QNaN)))))) \/ (((type2 = FPType_SNaN)))))) \/ (((type2 = FPType_QNaN)))))) then + let result = ((vec_of_bits [B0;B0;B1;B1] : 4 words$word)) in sail2_state_monad$seqS + (if (((((((((type1 = FPType_SNaN))) \/ (((type2 = FPType_SNaN)))))) \/ signal_nans))) then + FPProcessException FPExc_InvalidOp fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result) + else + let (result : 4 bits) = + (if (((value1_name = value2_name))) then (vec_of_bits [B0;B1;B1;B0] : 4 words$word) + else if ((value1_name < value2_name)) then (vec_of_bits [B1;B0;B0;B0] : 4 words$word) + else (vec_of_bits [B0;B0;B1;B0] : 4 words$word)) in + sail2_state_monad$returnS result)))))))))))`; + + +(*val FPSub : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPSub:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS + (undefined_real () ) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (result_sign : 1 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (result_value : real) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . + if ((~ done)) then + let inf1 = (type1 = FPType_Infinity) in + let inf2 = (type2 = FPType_Infinity) in + let zero1 = (type1 = FPType_Zero) in + let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 /\ inf2))) /\ (((sign1 = sign2)))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len op1))) () : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let result = w__0 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B0] : 1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B1] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) + else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B1] : 1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B0] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1] : 1 words$word) : ( 'N words$word) M) + else if ((((((zero1 /\ zero2))) /\ (((sign1 = ((not_vec sign2 : 1 words$word)))))))) + then + (FPZero ((int_of_num (words$word_len op1))) sign1 : ( 'N words$word) M) + else + let result_value = (value1_name - value2_name) in + if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then + let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in + (FPZero ((int_of_num (words$word_len op1))) result_sign : ( 'N words$word) M) + else (FPRound__0 ((int_of_num (words$word_len op1))) result_value fpcr rounding : ( 'N words$word) M) + else sail2_state_monad$returnS result))))))))))))))))))))`; + + +(*val FPMulAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMulAdd:'N words$word -> 'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addend op1 op2 fpcr= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len addend))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len addend))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len addend))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS + (undefined_real () ) (\ (valueA_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (signA : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typeA : FPType) . sail2_state_monad$bindS + (FPUnpack addend fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let typeA = tup__0 in + let signA = tup__1 in + let valueA_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in + let (inf1 : bool) = (type1 = FPType_Infinity) in + let (zero1 : bool) = (type1 = FPType_Zero) in + let (inf2 : bool) = (type2 = FPType_Infinity) in + let (zero2 : bool) = (type2 = FPType_Zero) in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len addend))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs3 typeA type1 type2 addend op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (if ((((((typeA = FPType_QNaN))) /\ ((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2))))))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len addend))) () : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let result = w__0 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else sail2_state_monad$returnS result) (\ (result : 'N bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (result_sign : 1 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (result_value : real) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zeroP : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (infP : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (signP : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zeroA : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (infA : bool) . + if ((~ done)) then + let infA = (typeA = FPType_Infinity) in + let zeroA = (typeA = FPType_Zero) in + let signP = ((xor_vec sign1 sign2 : 1 words$word)) in + let infP = (inf1 \/ inf2) in + let zeroP = (zero1 \/ zero2) in + if (((((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2)))))) \/ ((((((infA /\ infP))) /\ (((signA <> signP))))))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len addend))) () : ( 'N words$word) M) (\ (w__1 : 'N bits) . + let result = w__1 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else if ((((((infA /\ (((signA = (vec_of_bits [B0] : 1 words$word))))))) \/ (((infP /\ (((signP = (vec_of_bits [B0] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len addend))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) + else if ((((((infA /\ (((signA = (vec_of_bits [B1] : 1 words$word))))))) \/ (((infP /\ (((signP = (vec_of_bits [B1] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len addend))) (vec_of_bits [B1] : 1 words$word) : ( 'N words$word) M) + else if ((((((zeroA /\ zeroP))) /\ (((signA = signP)))))) then + (FPZero ((int_of_num (words$word_len addend))) signA : ( 'N words$word) M) + else + let result_value = (valueA_name + ((value1_name * value2_name))) in + if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then + let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in + (FPZero ((int_of_num (words$word_len addend))) result_sign : ( 'N words$word) M) + else (FPRound__1 ((int_of_num (words$word_len addend))) result_value fpcr : ( 'N words$word) M) + else sail2_state_monad$returnS result))))))))))))))))))))))))))`; + + +(*val FPMul : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMul:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . + if ((~ done)) then + let inf1 = (type1 = FPType_Infinity) in + let inf2 = (type2 = FPType_Infinity) in + let zero1 = (type1 = FPType_Zero) in + let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 /\ zero2))) \/ (((zero1 /\ inf2)))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len op1))) () : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let result = w__0 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else if (((inf1 \/ inf2))) then + (FPInfinity ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2 : 1 words$word)) : ( 'N words$word) M) + else if (((zero1 \/ zero2))) then + (FPZero ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2 : 1 words$word)) : ( 'N words$word) M) + else (FPRound__1 ((int_of_num (words$word_len op1))) ((value1_name * value2_name)) fpcr : ( 'N words$word) M) + else sail2_state_monad$returnS result)))))))))))))))))`; + + +(*val FPMin : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMin:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . + if ((~ done)) then + let ((sign : 1 bits), (typ : FPType), (value_name : real)) = + (if ((value1_name < value2_name)) then + let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in + let (typ : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + (sign, typ, value_name) + else + let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in + let (typ : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + (sign, typ, value_name)) in + if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op1))) sign : ( 'N words$word) M) + else if (((typ = FPType_Zero))) then + let sign = ((or_vec sign1 sign2 : 1 words$word)) in + (FPZero ((int_of_num (words$word_len op1))) sign : ( 'N words$word) M) + else (FPRound__1 ((int_of_num (words$word_len op1))) value_name fpcr : ( 'N words$word) M) + else sail2_state_monad$returnS result))))))))))))))))`; + + +(*val FPMinNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMinNum:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1__arg op2__arg fpcr= + (let op1 = op1__arg in + let op2 = op2__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (anon20 : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let anon10 = tup__1 in + let anon20 = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (anon40 : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (anon30 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let anon30 = tup__1 in + let anon40 = tup__2 in sail2_state_monad$bindS + (if ((((((type1 = FPType_QNaN))) /\ (((type2 <> FPType_QNaN)))))) then sail2_state_monad$bindS + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) (\ (w__0 : + 'N words$word) . + let (op1 : 'N words$word) = w__0 in + sail2_state_monad$returnS (op1, op2)) + else sail2_state_monad$bindS + (if ((((((type1 <> FPType_QNaN))) /\ (((type2 = FPType_QNaN)))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) + else sail2_state_monad$returnS op2) (\ (op2 : 'N words$word) . + sail2_state_monad$returnS (op1, op2))) (\ varstup . let ((op1 : 'N words$word), (op2 : 'N words$word)) = varstup in + (FPMin op1 op2 fpcr : ( 'N words$word) M))))))))))))`; + + +(*val FPMax : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMax:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (undefined_real () ) (\ (value_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (typ : FPType) . + if ((~ done)) then + let ((sign : 1 bits), (typ : FPType), (value_name : real)) = + (if ((value1_name > value2_name)) then + let (tup__0, tup__1, tup__2) = (type1, sign1, value1_name) in + let (typ : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + (sign, typ, value_name) + else + let (tup__0, tup__1, tup__2) = (type2, sign2, value2_name) in + let (typ : FPType) = tup__0 in + let (sign : 1 bits) = tup__1 in + let (value_name : real) = tup__2 in + (sign, typ, value_name)) in + if (((typ = FPType_Infinity))) then (FPInfinity ((int_of_num (words$word_len op1))) sign : ( 'N words$word) M) + else if (((typ = FPType_Zero))) then + let sign = ((and_vec sign1 sign2 : 1 words$word)) in + (FPZero ((int_of_num (words$word_len op1))) sign : ( 'N words$word) M) + else (FPRound__1 ((int_of_num (words$word_len op1))) value_name fpcr : ( 'N words$word) M) + else sail2_state_monad$returnS result))))))))))))))))`; + + +(*val FPMaxNum : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPMaxNum:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1__arg op2__arg fpcr= + (let op1 = op1__arg in + let op2 = op2__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (anon20 : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (anon10 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let anon10 = tup__1 in + let anon20 = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (anon40 : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (anon30 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let anon30 = tup__1 in + let anon40 = tup__2 in sail2_state_monad$bindS + (if ((((((type1 = FPType_QNaN))) /\ (((type2 <> FPType_QNaN)))))) then sail2_state_monad$bindS + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1] : 1 words$word) : ( 'N words$word) M) (\ (w__0 : + 'N words$word) . + let (op1 : 'N words$word) = w__0 in + sail2_state_monad$returnS (op1, op2)) + else sail2_state_monad$bindS + (if ((((((type1 <> FPType_QNaN))) /\ (((type2 = FPType_QNaN)))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1] : 1 words$word) : ( 'N words$word) M) + else sail2_state_monad$returnS op2) (\ (op2 : 'N words$word) . + sail2_state_monad$returnS (op1, op2))) (\ varstup . let ((op1 : 'N words$word), (op2 : 'N words$word)) = varstup in + (FPMax op1 op2 fpcr : ( 'N words$word) M))))))))))))`; + + +(*val FPDiv : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPDiv:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (undefined_real () )) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . + if ((~ done)) then + let inf1 = (type1 = FPType_Infinity) in + let inf2 = (type2 = FPType_Infinity) in + let zero1 = (type1 = FPType_Zero) in + let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 /\ inf2))) \/ (((zero1 /\ zero2)))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len op1))) () : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let result = w__0 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else if (((inf1 \/ zero2))) then sail2_state_monad$bindS + (FPInfinity ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2 : 1 words$word)) : ( 'N words$word) M) (\ (w__1 : 'N + bits) . + let result = w__1 in sail2_state_monad$seqS + (if ((~ inf1)) then FPProcessException FPExc_DivideByZero fpcr + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS result)) + else if (((zero1 \/ inf2))) then + (FPZero ((int_of_num (words$word_len op1))) ((xor_vec sign1 sign2 : 1 words$word)) : ( 'N words$word) M) + else (FPRound__1 ((int_of_num (words$word_len op1))) ((value1_name / value2_name)) fpcr : ( 'N words$word) M) + else sail2_state_monad$returnS result)))))))))))))))))`; + + +(*val FPAdd : forall 'N . Size 'N => mword 'N -> mword 'N -> mword ty32 -> M (mword 'N)*) + +val _ = Define ` + ((FPAdd:'N words$word -> 'N words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((('N words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op1 op2 fpcr= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((((int_of_num (words$word_len op1))) = (( 16 : int):ii)))) \/ ((((((((int_of_num (words$word_len op1))) = (( 32 : int):ii)))) \/ (((((int_of_num (words$word_len op1))) = (( 64 : int):ii)))))))))) "((N == 16) || ((N == 32) || (N == 64)))") + (let (rounding : FPRounding) = (FPRoundingMode fpcr) in sail2_state_monad$bindS + (undefined_real () ) (\ (value1_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign1 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type1 : FPType) . sail2_state_monad$bindS + (FPUnpack op1 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type1 = tup__0 in + let sign1 = tup__1 in + let value1_name = tup__2 in sail2_state_monad$bindS + (undefined_real () ) (\ (value2_name : real) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (sign2 : 1 bits) . sail2_state_monad$bindS + (undefined_FPType () ) (\ (type2 : FPType) . sail2_state_monad$bindS + (FPUnpack op2 fpcr : ((FPType # 1 words$word # real)) M) (\ varstup . let (tup__0, tup__1, tup__2) = varstup in + let type2 = tup__0 in + let sign2 = tup__1 in + let value2_name = tup__2 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len op1))) : ( 'N words$word) M) (\ (result : 'N bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (done : bool) . sail2_state_monad$bindS + (FPProcessNaNs type1 type2 op1 op2 fpcr : ((bool # 'N words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let done = tup__0 in + let result = tup__1 in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (result_sign : 1 bits) . sail2_state_monad$bindS + (undefined_real () ) (\ (result_value : real) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (zero1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inf1 : bool) . + if ((~ done)) then + let inf1 = (type1 = FPType_Infinity) in + let inf2 = (type2 = FPType_Infinity) in + let zero1 = (type1 = FPType_Zero) in + let zero2 = (type2 = FPType_Zero) in + if ((((((inf1 /\ inf2))) /\ (((sign1 = ((not_vec sign2 : 1 words$word)))))))) then sail2_state_monad$bindS + (FPDefaultNaN ((int_of_num (words$word_len op1))) () : ( 'N words$word) M) (\ (w__0 : 'N bits) . + let result = w__0 in sail2_state_monad$seqS + (FPProcessException FPExc_InvalidOp fpcr) (sail2_state_monad$returnS result)) + else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B0] : 1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B0] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B0] : 1 words$word) : ( 'N words$word) M) + else if ((((((inf1 /\ (((sign1 = (vec_of_bits [B1] : 1 words$word))))))) \/ (((inf2 /\ (((sign2 = (vec_of_bits [B1] : 1 words$word)))))))))) then + (FPInfinity ((int_of_num (words$word_len op1))) (vec_of_bits [B1] : 1 words$word) : ( 'N words$word) M) + else if ((((((zero1 /\ zero2))) /\ (((sign1 = sign2)))))) then + (FPZero ((int_of_num (words$word_len op1))) sign1 : ( 'N words$word) M) + else + let result_value = (value1_name + value2_name) in + if (((result_value = (realFromFrac(( 0 : int))(( 10 : int)))))) then + let result_sign = + (if (((rounding = FPRounding_NEGINF))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in + (FPZero ((int_of_num (words$word_len op1))) result_sign : ( 'N words$word) M) + else (FPRound__0 ((int_of_num (words$word_len op1))) result_value fpcr rounding : ( 'N words$word) M) + else sail2_state_monad$returnS result))))))))))))))))))))`; + + +(*val ExternalSecureInvasiveDebugEnabled : unit -> M bool*) + +val _ = Define ` + ((ExternalSecureInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) . + if w__1 then sail2_state_monad$returnS F + else + sail2_state$and_boolS ((ExternalInvasiveDebugEnabled () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SPIDEN_ref) (\ (w__3 : signal) . sail2_state_monad$returnS (((w__3 = HIGH))))))))`; + + +(*val ExternalDebugInterruptsDisabled : mword ty2 -> M bool*) + +val _ = Define ` + ((ExternalDebugInterruptsDisabled:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (int_dis : bool) . + let pat_0 = target in + if (((pat_0 = EL3))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS (((((slice w__0 (( 22 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))) ((ExternalSecureInvasiveDebugEnabled () )) + else if (((pat_0 = EL2))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__3 : 32 bits) . + sail2_state_monad$returnS (((((and_vec ((slice w__3 (( 22 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))) + ((ExternalInvasiveDebugEnabled () )) + else sail2_state_monad$bindS + (IsSecure () ) (\ (w__6 : bool) . + if w__6 then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (((((and_vec ((slice w__7 (( 22 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))) + ((ExternalSecureInvasiveDebugEnabled () )) + else + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__10 : 32 bits) . + sail2_state_monad$returnS (((((slice w__10 (( 22 : int):ii) (( 2 : int):ii) : 2 words$word)) <> (vec_of_bits [B0;B0] : 2 words$word)))))) ((ExternalInvasiveDebugEnabled () ))))))`; + + +(*val ELStateUsingAArch32K : mword ty2 -> bool -> M (bool * bool)*) + +val _ = Define ` + ((ELStateUsingAArch32K:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el secure= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (aarch32 : bool) . + let (known : bool) = T in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (aarch32_at_el1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (aarch32_below_el3 : bool) . sail2_state_monad$bindS + (if ((~ ((HaveAArch32EL el)))) then + let (aarch32 : bool) = F in + sail2_state_monad$returnS (aarch32, known) + else if ((HighestELUsingAArch32 () )) then + let (aarch32 : bool) = T in + sail2_state_monad$returnS (aarch32, known) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 10 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__1 : bool) . + let aarch32_below_el3 = w__1 in sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS aarch32_below_el3) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ ((~ secure)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 31 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state$and_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (sail2_state_monad$returnS ((HaveVirtHostExt () )))) (\ (w__7 : + bool) . + sail2_state_monad$returnS ((~ w__7)))))) (\ (w__9 : bool) . + let aarch32_at_el1 = w__9 in + if ((((((el = EL0))) /\ ((~ aarch32_at_el1))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + if (((w__10.ProcState_EL = EL0))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + let (aarch32 : bool) = (w__11.ProcState_nRW = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (aarch32, known)) + else + let (known : bool) = F in + sail2_state_monad$returnS (aarch32, known)) + else + let (aarch32 : bool) = + ((((aarch32_below_el3 /\ (((el <> EL3)))))) \/ (((aarch32_at_el1 /\ ((((((el = EL1))) \/ (((el = EL0)))))))))) in + sail2_state_monad$returnS (aarch32, known)))) (\ varstup . let ((aarch32 : bool), (known : bool)) = varstup in sail2_state_monad$bindS + (if ((~ known)) then sail2_state_monad$undefined_boolS () + else sail2_state_monad$returnS aarch32) (\ (aarch32 : bool) . + sail2_state_monad$returnS (known, aarch32))))))))`; + + +(*val ELUsingAArch32K : mword ty2 -> M (bool * bool)*) + +val _ = Define ` + ((ELUsingAArch32K:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el= (sail2_state_monad$bindS (IsSecureBelowEL3 () ) (\ (w__0 : bool) . ELStateUsingAArch32K el w__0)))`; + + +(*val ELStateUsingAArch32 : mword ty2 -> bool -> M bool*) + +val _ = Define ` + ((ELStateUsingAArch32:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el secure= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (aarch32 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (known : bool) . sail2_state_monad$bindS + (ELStateUsingAArch32K el secure) (\ varstup . let (tup__0, tup__1) = varstup in + let known = tup__0 in + let aarch32 = tup__1 in sail2_state_monad$seqS + (sail2_state_monad$assert_expS known "known") (sail2_state_monad$returnS aarch32))))))`; + + +(*val ELUsingAArch32 : mword ty2 -> M bool*) + +val _ = Define ` + ((ELUsingAArch32:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el= (sail2_state_monad$bindS (IsSecureBelowEL3 () ) (\ (w__0 : bool) . ELStateUsingAArch32 el w__0)))`; + + +(*val UpdateEDSCRFields : unit -> M unit*) + +val _ = Define ` + ((UpdateEDSCRFields:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (Halted () ) (\ (w__0 : bool) . + if ((~ w__0)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + EDSCR_ref + ((set_slice (( 32 : int):ii) (( 2 : int):ii) w__1 (( 8 : int):ii) (vec_of_bits [B0;B0] : 2 words$word) : 32 words$word))) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__3 : 1 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__2 (( 18 : int):ii) w__3 : 32 words$word))) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__4 : 32 words$word) . + sail2_state_monad$write_regS + EDSCR_ref + ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__4 (( 10 : int):ii) (vec_of_bits [B1;B1;B1;B1] : 4 words$word) + : 32 words$word)))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 2 : int):ii) w__5 (( 8 : int):ii) w__6.ProcState_EL : 32 words$word))) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__7 : 32 words$word) . sail2_state_monad$bindS + (IsSecure () ) (\ (w__8 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + EDSCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__7 (( 18 : int):ii) + (if w__8 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 32 words$word))) + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M)) (\ (RW : 4 bits) . sail2_state_monad$bindS + (ELUsingAArch32 EL1) (\ (w__9 : bool) . + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 1 : int):ii) + (if w__9 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 4 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$bindS + (if (((w__10.ProcState_EL <> EL0))) then + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii) (vec_of_bits [access_vec_dec RW (( 1 : int):ii)] : 1 words$word) + : 4 words$word)) in + sail2_state_monad$returnS RW + else sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__11 : bool) . + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii) + (if w__11 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 4 words$word)) in + sail2_state_monad$returnS RW)) (\ (RW : 4 bits) . sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(aget_SCR_GEN () : ( 32 words$word) M) (\ (w__12 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__14 : bool) . sail2_state_monad$bindS + (if w__14 then + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 2 : int):ii) (vec_of_bits [access_vec_dec RW (( 1 : int):ii)] : 1 words$word) + : 4 words$word)) in + sail2_state_monad$returnS RW + else sail2_state_monad$bindS + (ELUsingAArch32 EL2) (\ (w__15 : bool) . + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 2 : int):ii) + (if w__15 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 4 words$word)) in + sail2_state_monad$returnS RW)) (\ (RW : 4 bits) . sail2_state_monad$bindS + (if ((~ ((HaveEL EL3)))) then + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 3 : int):ii) (vec_of_bits [access_vec_dec RW (( 2 : int):ii)] : 1 words$word) + : 4 words$word)) in + sail2_state_monad$returnS RW + else sail2_state_monad$bindS + (ELUsingAArch32 EL3) (\ (w__16 : bool) . + let (RW : 4 bits) = + ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 3 : int):ii) + (if w__16 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 4 words$word)) in + sail2_state_monad$returnS RW)) (\ (RW : 4 bits) . sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec RW (( 3 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M) (\ (w__17 : 3 words$word) . + let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 3 : int):ii) RW (( 0 : int):ii) w__17 : 4 words$word)) in + sail2_state_monad$returnS RW) + else if ((((vec_of_bits [access_vec_dec RW (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__18 : 2 words$word) . + let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 2 : int):ii) RW (( 0 : int):ii) w__18 : 4 words$word)) in + sail2_state_monad$returnS RW) + else if ((((vec_of_bits [access_vec_dec RW (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__19 : 1 words$word) . + let (RW : 4 bits) = ((set_slice (( 4 : int):ii) (( 1 : int):ii) RW (( 0 : int):ii) w__19 : 4 words$word)) in + sail2_state_monad$returnS RW) + else sail2_state_monad$returnS RW) (\ (RW : 4 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__20 : 32 words$word) . + sail2_state_monad$write_regS EDSCR_ref ((set_slice (( 32 : int):ii) (( 4 : int):ii) w__20 (( 10 : int):ii) RW : 32 words$word))))))))))))))))))`; + + +(*val Halt : mword ty6 -> M unit*) + +val _ = Define ` + ((Halt:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) reason= (sail2_state_monad$bindS (sail2_state_monad$seqS + (CTI_SignalEvent CrossTriggerIn_CrossHalt) + (UsingAArch32 () )) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__0 then sail2_state_monad$bindS + (ThisInstrAddr (( 32 : int):ii) () : ( 32 words$word) M) (\ (w__1 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_ref w__1) + (GetPSRFromPSTATE () : ( 32 words$word) M)) (\ (w__2 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DSPSR_ref w__2) + (sail2_state_monad$read_regS DSPSR_ref : ( 32 words$word) M)) (\ (w__3 : 32 words$word) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$write_regS + DSPSR_ref + ((update_subrange_vec_dec w__3 (( 21 : int):ii) (( 21 : int):ii) w__4.ProcState_SS : 32 words$word)))))) + else sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__5 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_EL0_ref w__5) + (GetPSRFromPSTATE () : ( 32 words$word) M)) (\ (w__6 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DSPSR_EL0_ref w__6) + (sail2_state_monad$read_regS DSPSR_EL0_ref : ( 32 words$word) M)) (\ (w__7 : 32 words$word) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + sail2_state_monad$write_regS + DSPSR_EL0_ref + ((update_subrange_vec_dec w__7 (( 21 : int):ii) (( 21 : int):ii) w__8.ProcState_SS : 32 words$word))))))) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__9 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + EDSCR_ref + ((update_subrange_vec_dec w__9 (( 24 : int):ii) (( 24 : int):ii) (vec_of_bits [B1] : 1 words$word) : 32 words$word))) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__10 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + EDSCR_ref + ((update_subrange_vec_dec w__10 (( 28 : int):ii) (( 28 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) + (IsSecure () )) (\ (w__11 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__11 then sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . + sail2_state_monad$write_regS + EDSCR_ref + ((update_subrange_vec_dec w__12 (( 16 : int):ii) (( 16 : int):ii) (vec_of_bits [B0] : 1 words$word) + : 32 words$word))) + else if ((HaveEL EL3)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__13 : 32 words$word) . sail2_state_monad$bindS + (ExternalSecureInvasiveDebugEnabled () ) (\ (w__14 : bool) . + sail2_state_monad$write_regS + EDSCR_ref + ((update_subrange_vec_dec w__13 (( 16 : int):ii) (( 16 : int):ii) + (if w__14 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) + : 32 words$word)))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + sail2_state_monad$assert_expS ((((vec_of_bits [access_vec_dec w__15 (( 16 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) "((EDSCR).SDD == '1')")) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__16 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + EDSCR_ref + ((update_subrange_vec_dec w__16 (( 20 : int):ii) (( 20 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) + (UsingAArch32 () )) (\ (w__17 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__17 then sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__18 : 4 bits) . + let split_vec = w__18 in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_SS := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_A := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_I := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_F := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__23 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_T := ((vec_of_bits [B1] : 1 words$word))|>)))))))) + else sail2_state_monad$bindS + (undefined_bitvector (( 5 : int):ii) : ( 5 words$word) M) (\ (w__25 : 5 bits) . + let split_vec = w__25 in + let (tup__0, tup__1, tup__2, tup__3, tup__4) = + ((subrange_vec_dec split_vec (( 4 : int):ii) (( 4 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_SS := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_D := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_A := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_I := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__30 with<| ProcState_F := tup__4|>)))))))) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__31 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_IL := ((vec_of_bits [B0] : 1 words$word))|>)) + (StopInstructionPrefetchAndEnableITR () )) + (sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M)) (\ (w__32 : 32 words$word) . sail2_state_monad$seqS + (sail2_state_monad$write_regS EDSCR_ref ((update_subrange_vec_dec w__32 (( 5 : int):ii) (( 0 : int):ii) reason : 32 words$word))) + (UpdateEDSCRFields () )))))))))))`; + + +(*val aarch64_system_exceptions_debug_halt : unit -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_debug_halt:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (Halt DebugHalt_HaltInstruction))`; + + +(*val S2CacheDisabled : AccType -> M bool*) + +val _ = Define ` + ((S2CacheDisabled:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (disable : 1 bits) . sail2_state_monad$bindS + (ELUsingAArch32 EL2) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then + if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR2_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 1 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR2_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)] : 1 words$word)) + else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 33 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__5 (( 32 : int):ii)] : 1 words$word))) (\ (disable : 1 bits) . + sail2_state_monad$returnS (((disable = (vec_of_bits [B1] : 1 words$word)))))))))`; + + +(*val S2ConvertAttrsHints : mword ty2 -> AccType -> M MemAttrHints*) + +val _ = Define ` + ((S2ConvertAttrsHints:(2)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) attr acctype= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ ((IsZero attr)))) "!(IsZero(attr))") + (undefined_MemAttrHints () )) (\ (result : MemAttrHints) . sail2_state_monad$bindS + (S2CacheDisabled acctype) (\ (w__0 : bool) . + let (result : MemAttrHints) = + (if w__0 then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + (result with<| MemAttrHints_hints := MemHint_No|>) + else + let b__0 = attr in + if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + (result with<| MemAttrHints_hints := MemHint_No|>) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in + (result with<| MemAttrHints_hints := MemHint_RWA|>) + else + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in + (result with<| MemAttrHints_hints := MemHint_RWA|>)) in + let (result : MemAttrHints) = ((result with<| MemAttrHints_transient := F|>)) in + sail2_state_monad$returnS result))))`; + + +(*val S2AttrDecode : mword ty2 -> mword ty4 -> AccType -> M MemoryAttributes*) + +val _ = Define ` + ((S2AttrDecode:(2)words$word ->(4)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH attr acctype= (sail2_state_monad$bindS + (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . sail2_state_monad$bindS + (if (((((slice attr (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_typ := MemType_Device|>)) in + let b__0 = ((slice attr (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let (memattrs : MemoryAttributes) = + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (memattrs with<| MemoryAttributes_device := DeviceType_nGnRnE|>) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (memattrs with<| MemoryAttributes_device := DeviceType_nGnRE|>) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (memattrs with<| MemoryAttributes_device := DeviceType_nGRE|>) + else (memattrs with<| MemoryAttributes_device := DeviceType_GRE|>)) in + sail2_state_monad$returnS memattrs + else if (((((slice attr (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) <> (vec_of_bits [B0;B0] : 2 words$word)))) + then + let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS + (S2ConvertAttrsHints ((slice attr (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) acctype) (\ (w__0 : + MemAttrHints) . + let memattrs = ((memattrs with<| MemoryAttributes_outer := w__0|>)) in sail2_state_monad$bindS + (S2ConvertAttrsHints ((slice attr (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) acctype) (\ (w__1 : + MemAttrHints) . + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_inner := w__1|>)) in + let (memattrs : MemoryAttributes) = + ((memattrs with<| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))|>)) in + let (memattrs : MemoryAttributes) = + ((memattrs with<| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0] : 2 words$word))))|>)) in + sail2_state_monad$returnS memattrs)) + else undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . + MemAttrDefaults memattrs))))`; + + +(*val ELIsInHost : mword ty2 -> M bool*) + +val _ = Define ` + ((ELIsInHost:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el= + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS ( sail2_state_monad$bindS(IsSecureBelowEL3 () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0)))) + (sail2_state_monad$returnS ((HaveVirtHostExt () )))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + (sail2_state$or_boolS (sail2_state_monad$returnS (((el = EL2)))) + (sail2_state$and_boolS (sail2_state_monad$returnS (((el = EL0)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))))))`; + + +(*val S1TranslationRegime__0 : mword ty2 -> M (mword ty2)*) + +(*val S1TranslationRegime__1 : unit -> M (mword ty2)*) + +val _ = Define ` + ((S1TranslationRegime__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) el= + (if (((el <> EL0))) then sail2_state_monad$returnS el + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((ELUsingAArch32 EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__3 : bool) . + if w__3 then sail2_state_monad$returnS EL3 + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () ))) ((ELIsInHost el))) (\ (w__5 : bool) . + sail2_state_monad$returnS (if w__5 then EL2 + else EL1)))))`; + + +val _ = Define ` + ((S1TranslationRegime__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + (S1TranslationRegime__0 w__0.ProcState_EL : ( 2 words$word) M))))`; + + +(*val aset_FAR__0 : mword ty2 -> mword ty64 -> M unit*) + +(*val aset_FAR__1 : mword ty64 -> M unit*) + +val _ = Define ` + ((aset_FAR__0:(2)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime value_name= + (let (r : 64 bits) = value_name in + let pat_0 = regime in + if (((pat_0 = EL1))) then sail2_state_monad$write_regS FAR_EL1_ref r + else if (((pat_0 = EL2))) then sail2_state_monad$write_regS FAR_EL2_ref r + else if (((pat_0 = EL3))) then sail2_state_monad$write_regS FAR_EL3_ref r + else Unreachable () ))`; + + +val _ = Define ` + ((aset_FAR__1:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . + aset_FAR__0 w__0 value_name)))`; + + +(*val aset_ESR__0 : mword ty2 -> mword ty32 -> M unit*) + +(*val aset_ESR__1 : mword ty32 -> M unit*) + +val _ = Define ` + ((aset_ESR__0:(2)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime value_name= + (let (r : 32 bits) = value_name in + let pat_0 = regime in + if (((pat_0 = EL1))) then sail2_state_monad$write_regS ESR_EL1_ref r + else if (((pat_0 = EL2))) then sail2_state_monad$write_regS ESR_EL2_ref r + else if (((pat_0 = EL3))) then sail2_state_monad$write_regS ESR_EL3_ref r + else Unreachable () ))`; + + +val _ = Define ` + ((aset_ESR__1:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . + aset_ESR__0 w__0 value_name)))`; + + +(*val aget_VBAR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_VBAR__1 : unit -> M (mword ty64)*) + +val _ = Define ` + ((aget_VBAR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (r : 64 bits) . + let pat_0 = regime in + if (((pat_0 = EL1))) then (sail2_state_monad$read_regS VBAR_EL1_ref : ( 64 words$word) M) + else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS VBAR_EL2_ref : ( 64 words$word) M) + else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS VBAR_EL3_ref : ( 64 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`; + + +val _ = Define ` + ((aget_VBAR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . + (aget_VBAR__0 w__0 : ( 64 words$word) M))))`; + + +(*val aget_SCTLR__0 : mword ty2 -> M (mword ty32)*) + +(*val aget_SCTLR__1 : unit -> M (mword ty32)*) + +val _ = Define ` + ((aget_SCTLR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime= (sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (r : 32 bits) . + let pat_0 = regime in + if (((pat_0 = EL1))) then (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) + else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) + else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`; + + +val _ = Define ` + ((aget_SCTLR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . + (aget_SCTLR__0 w__0 : ( 32 words$word) M))))`; + + +(*val BigEndian : unit -> M bool*) + +val _ = Define ` + ((BigEndian:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (bigend : bool) . sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let (bigend : bool) = (w__1.ProcState_E <> (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS bigend) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + if (((w__2.ProcState_EL = EL0))) then sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + let (bigend : bool) = + ((vec_of_bits [access_vec_dec w__3 (( 24 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS bigend) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + let (bigend : bool) = + ((vec_of_bits [access_vec_dec w__4 (( 25 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS bigend))))))`; + + +(*val aget_MAIR__0 : mword ty2 -> M (mword ty64)*) + +(*val aget_MAIR__1 : unit -> M (mword ty64)*) + +val _ = Define ` + ((aget_MAIR__0:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regime= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (r : 64 bits) . + let pat_0 = regime in + if (((pat_0 = EL1))) then (sail2_state_monad$read_regS MAIR_EL1_ref : ( 64 words$word) M) + else if (((pat_0 = EL2))) then (sail2_state_monad$read_regS MAIR_EL2_ref : ( 64 words$word) M) + else if (((pat_0 = EL3))) then (sail2_state_monad$read_regS MAIR_EL3_ref : ( 64 words$word) M) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS r))))`; + + +val _ = Define ` + ((aget_MAIR__1:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . + (aget_MAIR__0 w__0 : ( 64 words$word) M))))`; + + +(*val S1CacheDisabled : AccType -> M bool*) + +val _ = Define ` + ((S1CacheDisabled:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (enable : 1 bits) . sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS + (if w__1 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + if (((w__2.ProcState_EL = EL2))) then + if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS HSCTLR_ref : ( 32 words$word) M) (\ (w__3 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 12 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HSCTLR_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 2 : int):ii)] : 1 words$word)) + else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 12 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 2 : int):ii)] : 1 words$word))) + else if (((acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__9 : 32 words$word) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__9 (( 12 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__10 (( 2 : int):ii)] : 1 words$word))) (\ (enable : 1 bits) . + sail2_state_monad$returnS (((enable = (vec_of_bits [B0] : 1 words$word))))))))))`; + + +(*val ShortConvertAttrsHints : mword ty2 -> AccType -> bool -> M MemAttrHints*) + +val _ = Define ` + ((ShortConvertAttrsHints:(2)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) RGN acctype secondstage= (sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (result : MemAttrHints) . sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((~ secondstage))) ((S1CacheDisabled acctype))) + (sail2_state$and_boolS (sail2_state_monad$returnS secondstage) ((S2CacheDisabled acctype)))) (\ (w__4 : bool) . + let (result : MemAttrHints) = + (if w__4 then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + (result with<| MemAttrHints_hints := MemHint_No|>) + else + let b__0 = RGN in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + (result with<| MemAttrHints_hints := MemHint_No|>) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in + (result with<| MemAttrHints_hints := MemHint_RWA|>) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in + (result with<| MemAttrHints_hints := MemHint_RA|>) + else + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WB|>)) in + (result with<| MemAttrHints_hints := MemHint_RA|>)) in + let (result : MemAttrHints) = ((result with<| MemAttrHints_transient := F|>)) in + sail2_state_monad$returnS result))))`; + + +(*val WalkAttrDecode : mword ty2 -> mword ty2 -> mword ty2 -> bool -> M MemoryAttributes*) + +val _ = Define ` + ((WalkAttrDecode:(2)words$word ->(2)words$word ->(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH ORGN IRGN secondstage= (sail2_state_monad$bindS + (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . + let (acctype : AccType) = AccType_NORMAL in + let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS + (ShortConvertAttrsHints IRGN acctype secondstage) (\ (w__0 : MemAttrHints) . + let memattrs = ((memattrs with<| MemoryAttributes_inner := w__0|>)) in sail2_state_monad$bindS + (ShortConvertAttrsHints ORGN acctype secondstage) (\ (w__1 : MemAttrHints) . + let memattrs = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in + let memattrs = + ((memattrs with<| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))|>)) in + let memattrs = + ((memattrs with<| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0] : 2 words$word))))|>)) in + MemAttrDefaults memattrs)))))`; + + +(*val LongConvertAttrsHints : mword ty4 -> AccType -> M MemAttrHints*) + +val _ = Define ` + ((LongConvertAttrsHints:(4)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemAttrHints),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) attrfield acctype= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ ((IsZero attrfield)))) "!(IsZero(attrfield))") + (undefined_MemAttrHints () )) (\ (result : MemAttrHints) . sail2_state_monad$bindS + (S1CacheDisabled acctype) (\ (w__0 : bool) . + let (result : MemAttrHints) = + (if w__0 then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + (result with<| MemAttrHints_hints := MemHint_No|>) + else if (((((slice attrfield (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_WT|>)) in + let (result : MemAttrHints) = + ((result with<| MemAttrHints_hints := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii) : 2 words$word))|>)) in + (result with<| MemAttrHints_transient := T|>) + else if (((((slice attrfield (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (result : MemAttrHints) = ((result with<| MemAttrHints_attrs := MemAttr_NC|>)) in + let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := MemHint_No|>)) in + (result with<| MemAttrHints_transient := F|>) + else if (((((slice attrfield (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (result : MemAttrHints) = + ((result with<| MemAttrHints_attrs := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii) : 2 words$word))|>)) in + let (result : MemAttrHints) = ((result with<| MemAttrHints_hints := MemAttr_WB|>)) in + (result with<| MemAttrHints_transient := T|>) + else + let (result : MemAttrHints) = + ((result with<| MemAttrHints_attrs := ((slice attrfield (( 2 : int):ii) (( 2 : int):ii) : 2 words$word))|>)) in + let (result : MemAttrHints) = + ((result with<| MemAttrHints_hints := ((slice attrfield (( 0 : int):ii) (( 2 : int):ii) : 2 words$word))|>)) in + (result with<| MemAttrHints_transient := F|>)) in + sail2_state_monad$returnS result))))`; + + +(*val AArch64_S1AttrDecode : mword ty2 -> mword ty3 -> AccType -> M MemoryAttributes*) + +val _ = Define ` + ((AArch64_S1AttrDecode:(2)words$word ->(3)words$word -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((MemoryAttributes),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SH attr acctype= + (let uattr = (ex_nat ((lem$w2ui attr))) in sail2_state_monad$bindS + (undefined_MemoryAttributes () ) (\ (memattrs : MemoryAttributes) . sail2_state_monad$bindS + (aget_MAIR__1 () : ( 64 words$word) M) (\ (mair : 64 bits) . + let (index : int) = ((( 8 : int):ii) * uattr) in + let (attrfield : 8 bits) = + ((subrange_vec_dec mair (((( 7 : int):ii) + index)) index : 8 words$word)) in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (anon10 : Constraint) . sail2_state_monad$bindS + (if (((((((((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) <> (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word))))))) \/ ((((((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((and_vec ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + (vec_of_bits [B0;B0;B1;B1] : 4 words$word) + : 4 words$word)) <> (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))))))))) then sail2_state_monad$bindS + (ConstrainUnpredictableBits (( 8 : int):ii) Unpredictable_RESMAIR : ((Constraint # 8 words$word)) M) (\ (w__0 : + (Constraint # 8 bits)) . + let (tup__0, tup__1) = w__0 in + let (anon10 : Constraint) = tup__0 in + sail2_state_monad$returnS tup__1) + else sail2_state_monad$returnS attrfield) (\ (attrfield : 8 bits) . sail2_state_monad$bindS + (if (((((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Device|>)) in + let b__0 = ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in + if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (memattrs : MemoryAttributes) = + ((memattrs with<| MemoryAttributes_device := DeviceType_nGnRnE|>)) in + sail2_state_monad$returnS memattrs + else if (((b__0 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (memattrs : MemoryAttributes) = + ((memattrs with<| MemoryAttributes_device := DeviceType_nGnRE|>)) in + sail2_state_monad$returnS memattrs + else if (((b__0 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (memattrs : MemoryAttributes) = + ((memattrs with<| MemoryAttributes_device := DeviceType_nGRE|>)) in + sail2_state_monad$returnS memattrs + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0] : 4 words$word)))) then + let (memattrs : MemoryAttributes) = + ((memattrs with<| MemoryAttributes_device := DeviceType_GRE|>)) in + sail2_state_monad$returnS memattrs + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS memattrs) + else if (((((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) <> (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let memattrs = ((memattrs with<| MemoryAttributes_typ := MemType_Normal|>)) in sail2_state_monad$bindS + (LongConvertAttrsHints ((subrange_vec_dec attrfield (( 7 : int):ii) (( 4 : int):ii) : 4 words$word)) acctype) (\ (w__1 : + MemAttrHints) . + let memattrs = ((memattrs with<| MemoryAttributes_outer := w__1|>)) in sail2_state_monad$bindS + (LongConvertAttrsHints ((subrange_vec_dec attrfield (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) acctype) (\ (w__2 : + MemAttrHints) . + let (memattrs : MemoryAttributes) = ((memattrs with<| MemoryAttributes_inner := w__2|>)) in + let (memattrs : MemoryAttributes) = + ((memattrs with<| + MemoryAttributes_shareable := + ((((vec_of_bits [access_vec_dec SH (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))|>)) in + let (memattrs : MemoryAttributes) = + ((memattrs with<| + MemoryAttributes_outershareable := (((SH = (vec_of_bits [B1;B0] : 2 words$word))))|>)) in + sail2_state_monad$returnS memattrs)) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS memattrs)) (\ (memattrs : MemoryAttributes) . + MemAttrDefaults memattrs)))))))`; + + +(*val IsInHost : unit -> M bool*) + +val _ = Define ` + ((IsInHost:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . ELIsInHost w__0.ProcState_EL)))`; + + +(*val aget_CPACR : unit -> M (mword ty32)*) + +val _ = Define ` + ((aget_CPACR:unit ->(regstate)sail2_state_monad$sequential_state ->((((32)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (IsInHost () ) (\ (w__0 : bool) . + if w__0 then (sail2_state_monad$read_regS CPTR_EL2_ref : ( 32 words$word) M) + else (sail2_state_monad$read_regS CPACR_EL1_ref : ( 32 words$word) M))))`; + + +(*val HasS2Translation : unit -> M bool*) + +val _ = Define ` + ((HasS2Translation:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(IsInHost () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$returnS (((w__4.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . sail2_state_monad$returnS (((w__5.ProcState_EL = EL1))))))))`; + + +(*val AArch64_SecondStageWalk : AddressDescriptor -> mword ty64 -> AccType -> bool -> ii -> bool -> M AddressDescriptor*) + +val _ = Define ` + ((AArch64_CheckAndUpdateDescriptor_SecondStage:DescriptorUpdate -> FaultRecord ->(64)words$word -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) result fault vaddress acctype iswrite s2fs1walk hwupdatewalk__arg= + (let hwupdatewalk = hwupdatewalk__arg in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (hw_update_AF : bool) . + let (hw_update_AF : bool) = + (if result.DescriptorUpdate_AF then + if (((fault.FaultRecord_typ = Fault_None))) then T + else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then T + else F + else hw_update_AF) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (hw_update_AP : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (write_perm_req : bool) . + let (hw_update_AP : bool) = + (if (((result.DescriptorUpdate_AP /\ (((fault.FaultRecord_typ = Fault_None)))))) then + let (write_perm_req : bool) = + ((((iswrite \/ ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW))))))))) /\ ((~ s2fs1walk))) in + ((((write_perm_req /\ ((~ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_DC))))))))))) \/ hwupdatewalk) + else F) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (desc : 64 bits) . sail2_state_monad$bindS + (undefined_AccessDescriptor () ) (\ (accdesc : AccessDescriptor) . sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (descaddr2 : AddressDescriptor) . sail2_state_monad$seqS + (if (((hw_update_AF \/ hw_update_AP))) then + let descaddr2 = (result.DescriptorUpdate_descaddr) in sail2_state_monad$bindS + (CreateAccessDescriptor AccType_ATOMICRW) (\ (w__0 : AccessDescriptor) . + let accdesc = w__0 in sail2_state_monad$bindS + (aget__Mem descaddr2 (( 8 : int):ii) accdesc : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let desc = w__1 in + let (desc : 64 bits) = + (if hw_update_AF then + (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 10 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word) + else desc) in + let (desc : 64 bits) = + (if hw_update_AP then + (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word) + else desc) in + aset__Mem descaddr2 (( 8 : int):ii) accdesc desc)) + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS fault)))))))))`; + + +(*val AArch64_CheckS2Permission : Permissions -> mword ty64 -> mword ty52 -> ii -> AccType -> bool -> bool -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CheckS2Permission:Permissions ->(64)words$word ->(52)words$word -> int -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) perms vaddress ipaddress level acctype iswrite s2fs1walk hwupdatewalk= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) ((HasS2Translation () ))) (\ (w__5 : + bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__5 "(((HaveEL(EL2) && !(IsSecure())) && !(ELUsingAArch32(EL2))) && HasS2Translation())") + (let (r : bool) = + ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (w : bool) = + ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (xn : bool) . sail2_state_monad$bindS + (if ((HaveExtendedExecuteNeverExt () )) then + let b__0 = ((concat_vec perms.Permissions_xn perms.Permissions_xxn : 2 words$word)) in + if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS F + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + let (xn : bool) = (w__6.ProcState_EL = EL1) in + sail2_state_monad$returnS xn) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . + let (xn : bool) = (w__7.ProcState_EL = EL0) in + sail2_state_monad$returnS xn) + else + let (xn : bool) = (perms.Permissions_xn = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS xn) (\ (xn : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (failedread : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (fail1 : bool) . + let ((fail1 : bool), (failedread : bool)) = + (if ((((((acctype = AccType_IFETCH))) /\ ((~ s2fs1walk))))) then + let (fail1 : bool) = xn in + let (failedread : bool) = T in + (fail1, failedread) + else + let ((fail1 : bool), (failedread : bool)) = + (if (((((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW)))))) /\ ((~ s2fs1walk))))) then + let (fail1 : bool) = (((~ r)) \/ ((~ w))) in + let (failedread : bool) = (~ r) in + (fail1, failedread) + else + let ((fail1 : bool), (failedread : bool)) = + (if (((iswrite /\ ((~ s2fs1walk))))) then + let (fail1 : bool) = (~ w) in + let (failedread : bool) = F in + (fail1, failedread) + else + let ((fail1 : bool), (failedread : bool)) = + (if hwupdatewalk then + let (fail1 : bool) = (~ w) in + let (failedread : bool) = (~ iswrite) in + (fail1, failedread) + else + let (fail1 : bool) = (~ r) in + let (failedread : bool) = (~ iswrite) in + (fail1, failedread)) in + (fail1, failedread)) in + (fail1, failedread)) in + (fail1, failedread)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (domain1 : 4 bits) . + if fail1 then sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__8 : 4 bits) . + let domain1 = w__8 in + let secondstage = T in + AArch64_PermissionFault ipaddress level acctype ((~ failedread)) secondstage s2fs1walk) + else AArch64_NoFault () ))))))))))`; + + +(*val IsZero_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +val _ = Define ` + ((IsZero_slice:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$returnS ((IsZero ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)))))))`; + + +(*val ZeroExtend_slice_append : forall 'n 'm 'o . Size 'm, Size 'n, Size 'o => integer -> mword 'n -> ii -> ii -> mword 'm -> M (mword 'o)*) + +val _ = Define ` + ((ZeroExtend_slice_append:int -> 'n words$word -> int -> int -> 'm words$word ->(regstate)sail2_state_monad$sequential_state ->((('o words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (o__tv : int) xs i l ys= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let xs = ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) in + let (xs : 'o bits) = + ((shiftl ((extzv o__tv ((shiftr xs i : 'n words$word)) : 'o words$word)) ((int_of_num (words$word_len ys))) : 'o words$word)) in + let (ys : 'o bits) = ((extzv ((int_of_num (words$word_len xs))) ys : 'o words$word)) in + sail2_state_monad$returnS ((or_vec xs ys : 'o words$word)))))`; + + +val _ = Define ` + ((AArch64_TranslationTableWalk_SecondStage:(52)words$word ->(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress vaddress acctype iswrite s2fs1walk size1= + (sail2_state_monad$catch_early_returnS + ( sail2_state_monad$bindS(sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsSecure () )) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL2)) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + (sail2_state_monad$liftRS ((HasS2Translation () )))) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS w__5 "")) + (sail2_state_monad$liftRS (undefined_TLBRecord () ))) (\ (result : TLBRecord) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (baseregister : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (inputaddr : 64 bits) . + let (tmp_180 : MemoryAttributes) = (descaddr.AddressDescriptor_memattrs) in + let tmp_180 = ((tmp_180 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := tmp_180|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (startsizecheck : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsizecheck : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (startlevel : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (level : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (stride : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (firstblocklevel : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (grainsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hierattrsdisabled : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AP : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AF : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (singlepriv : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (lookupsecure : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (reversedescriptors : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (disabled : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (basefound : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M))) (\ (ps : 3 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_min : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_max : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (midgrain : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (largegrain : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (top : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) ipaddress : ( 64 words$word) M))) (\ (w__6 : 64 bits) . + let inputaddr = w__6 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__7 : 32 bits) . + let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__7 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__8 : 32 bits) . + let largegrain = + (((slice w__8 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__9 : 32 bits) . + let midgrain = + (((slice w__9 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in + let inputsize_max = (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__10 : 32 bits) . + let ps = ((slice w__10 (( 16 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((~ ((ex_int inputsize)))) + (( 64 : int):ii))))))) (\ (w__12 : + bool) . + let basefound = w__12 in + let disabled = F in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTTBR_EL2_ref : ( 64 words$word) M))) (\ (w__13 : 64 bits) . + let baseregister = w__13 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__14 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__15 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__16 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__14 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__15 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__16 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) T)) (\ (w__17 : MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__17|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M))) (\ (w__18 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__18 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let lookupsecure = F in + let singlepriv = T in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__19 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__19 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__20 : bool) . + let update_AF = w__20 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__21 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 22 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__22 : bool) . + let update_AP = w__22 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__23 : 32 bits) . + let startlevel = (lem$w2ui ((slice w__23 (( 6 : int):ii) (( 2 : int):ii) : 2 words$word))) in + let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) = + (if largegrain then + let (grainsize : ii) = ((( 16 : int):ii)) in + let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in + (firstblocklevel, grainsize, level) + else + let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) = + (if midgrain then + let (grainsize : ii) = ((( 14 : int):ii)) in + let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = ((( 2 : int):ii)) in + (firstblocklevel, grainsize, level) + else + let (grainsize : ii) = ((( 12 : int):ii)) in + let (level : ii) = ((( 2 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = ((( 1 : int):ii)) in + (firstblocklevel, grainsize, level)) in + (firstblocklevel, grainsize, level)) in + let stride = (((ex_int grainsize)) - (( 3 : int):ii)) in + let (basefound : bool) = + (if largegrain then + if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) + then + F + else basefound + else if midgrain then + if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 40 : int):ii))))))))) + then + F + else basefound + else if (((((((ex_int level)) < (( 0 : int):ii))) \/ ((((((((ex_int level)) = (( 0 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then + F + else basefound) in + let inputsizecheck = inputsize in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int inputsize)) > ((ex_int ((PAMax () ))))))) + (sail2_state$or_boolS ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL1)) (\ (w__24 : bool) . sail2_state_monad$returnS ((~ w__24)))) + (sail2_state_monad$returnS ((((ex_int inputsize)) > (( 40 : int):ii)))))) (\ (w__26 : bool) . sail2_state_monad$bindS + (if w__26 then + (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of + Constraint_FORCE => + let (inputsize : ii) = (PAMax () ) in + let (inputsizecheck : ii) = (PAMax () ) in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | Constraint_FORCENOSLCHECK => + let (inputsize : ii) = (PAMax () ) in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | Constraint_FAULT => + let (basefound : bool) = F in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | _ => sail2_state_monad$seqS (sail2_state_monad$liftRS (Unreachable () )) (sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) + ) + else sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) (\ varstup . let ((basefound : bool), (inputsize : + ii), (inputsizecheck : ii)) = varstup in + let startsizecheck = + (((ex_int inputsizecheck)) - + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + ((ex_int grainsize))))) in + let (basefound : bool) = + (if (((((((ex_int startsizecheck)) < (( 1 : int):ii))) \/ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 : int):ii)))))))) then + F + else basefound) in + if (((((~ basefound)) \/ disabled))) then + let level = ((( 0 : int):ii)) in + let (tmp_190 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__27 : + FaultRecord) . + let (tmp_190 : AddressDescriptor) = ((tmp_190 with<| AddressDescriptor_fault := w__27|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_190|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (outputsize : ii) . + let b__0 = ps in + let (outputsize : ii) = + (if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then (( 36 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then (( 40 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then (( 42 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then (( 44 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then (( 48 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + if (((((Have52BitPAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii) + else (( 48 : int):ii)) in + let (outputsize : ii) = + (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () + else outputsize) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice baseregister outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__28 : + bool) . + sail2_state_monad$returnS ((~ w__28))))) (\ (w__29 : bool) . + if w__29 then + let level = ((( 0 : int):ii)) in + let (tmp_200 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__30 : + FaultRecord) . + let (tmp_200 : AddressDescriptor) = ((tmp_200 with<| AddressDescriptor_fault := w__30|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_200|>)) in + sail2_state_monad$returnS result) + else + let baselowerbound = + ((((( 3 : int):ii) + ((ex_int inputsize)))) - + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M)))) (\ (baseaddress : 52 bits) . sail2_state_monad$bindS + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + let z = (if ((baselowerbound < (( 6 : int):ii))) then (( 6 : int):ii) else baselowerbound) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (baseaddress : 52 bits) = + ((concat_vec ((slice baseregister (( 2 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_zeros_concat ((((((~ z)) + (( 48 : int):ii))) + z)) + baseregister z ((((~ z)) + (( 48 : int):ii))) z + : 48 words$word)) + : 52 words$word)) in + sail2_state_monad$returnS baseaddress) + else + let (baseaddress : 52 bits) = + ((place_slice (( 52 : int):ii) baseregister baselowerbound + ((((~ baselowerbound)) + (( 48 : int):ii))) baselowerbound + : 52 words$word)) in + sail2_state_monad$returnS baseaddress) (\ (baseaddress : 52 bits) . + let (ns_table : 1 bits) = + (if lookupsecure then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + let (ap_table : 2 bits) = ((vec_of_bits [B0;B0] : 2 words$word)) in + let (xn_table : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (pxn_table : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (addrselecttop : ii) = (((ex_int inputsize)) - (( 1 : int):ii)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M))) (\ (w__31 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__31 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M))) (\ (w__33 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__33 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (apply_nvnv1_effect : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (blocktranslate : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (desc : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hwupdatewalk : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (addrselectbottom : ii) . sail2_state_monad$bindS + (sail2_state$untilS (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) + (\ varstup . + let (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) = varstup in + sail2_state_monad$returnS blocktranslate) + (\ varstup . + let (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) = varstup in + let addrselectbottom = + ((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend_slice_append (( 52 : int):ii) inputaddr addrselectbottom + ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom)))) + + + (( 1 : int):ii))) (vec_of_bits [B0;B0;B0] : 3 words$word) + : ( 52 words$word) M))) (\ (index : 52 bits) . + let (tmp_210 : FullAddress) = (descaddr.AddressDescriptor_paddress) in + let tmp_210 = + ((tmp_210 with<| + FullAddress_physicaladdress := ((or_vec baseaddress index : 52 words$word))|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_210|>)) in + let (tmp_220 : FullAddress) = (descaddr.AddressDescriptor_paddress) in + let tmp_220 = ((tmp_220 with<| FullAddress_NS := ns_table|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_220|>)) in + let descaddr2 = descaddr in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress : ( 64 words$word) M))) (\ (w__34 : 64 bits) . + let descaddr2 = ((descaddr2 with<| AddressDescriptor_vaddress := w__34|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (CreateAccessDescriptorPTW acctype T s2fs1walk level)) (\ (w__35 : + AccessDescriptor) . + let accdesc = w__35 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc : ( 64 words$word) M))) (\ (w__36 : 64 + bits) . + let desc = w__36 in sail2_state_monad$bindS + (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc : ( 64 words$word) M)) + else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . sail2_state_monad$bindS + (if (((((((vec_of_bits [access_vec_dec desc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) \/ ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((ex_int level)) = (( 3 : int):ii)))))))))) + then + let (tmp_240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__38 : + FaultRecord) . + let tmp_240 = ((tmp_240 with<| AddressDescriptor_fault := w__38|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_240|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) + (sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result))) + else if ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ (((((ex_int level)) = (( 3 : int):ii))))))) + then + let (blocktranslate : bool) = T in + sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result) + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__39 : + bool) . + sail2_state_monad$returnS ((~ w__39)))))) (\ (w__41 : bool) . + if w__41 then + let (tmp_250 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__42 : + FaultRecord) . + let tmp_250 = ((tmp_250 with<| AddressDescriptor_fault := w__42|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_250|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) + (sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result))) + else + let gsz = grainsize in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (baseaddress : 52 bits) = + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_zeros_concat + ((((((~ gsz)) + (( 48 : int):ii))) + gsz)) desc + gsz ((((~ gsz)) + (( 48 : int):ii))) gsz + : 48 words$word)) + : 52 words$word) + else + (place_slice (( 52 : int):ii) desc gsz ((((~ gsz)) + (( 48 : int):ii))) + gsz + : 52 words$word)) in + let (level : ii) = (((ex_int level)) + (( 1 : int):ii)) in + let (addrselecttop : ii) = (((ex_int addrselectbottom)) - (( 1 : int):ii)) in + let (blocktranslate : bool) = F in + sail2_state_monad$returnS (addrselecttop, baseaddress, blocktranslate, level, result)))) (\ varstup . let ((addrselecttop : + ii), (baseaddress : 52 bits), (blocktranslate : bool), (level : ii), (result : + TLBRecord)) = varstup in + sail2_state_monad$returnS (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result))))))))) (\ varstup . let ((accdesc : AccessDescriptor), (addrselectbottom : + ii), (addrselecttop : ii), (baseaddress : 52 bits), (blocktranslate : bool), (desc : 64 + bits), (descaddr : AddressDescriptor), (descaddr2 : AddressDescriptor), (level : ii), (result : + TLBRecord)) = varstup in + if ((((ex_int level)) < ((ex_int firstblocklevel)))) then + let (tmp_260 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__43 : + FaultRecord) . + let (tmp_260 : AddressDescriptor) = ((tmp_260 with<| AddressDescriptor_fault := w__43|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_260|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (contiguousbitcheck : bool) . + let (contiguousbitcheck : bool) = + (if largegrain then + ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii)))) + else if midgrain then + ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 30 : int):ii)))) + else ((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))) in sail2_state_monad$bindS + (if (((contiguousbitcheck /\ ((((vec_of_bits [access_vec_dec desc (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (w__44 : bool) . + if w__44 then + let (tmp_270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__45 : + FaultRecord) . + let tmp_270 = ((tmp_270 with<| AddressDescriptor_fault := w__45|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_270|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result)) + else sail2_state_monad$returnS result) + else sail2_state_monad$returnS result) (\ (result : TLBRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__46 : + bool) . + sail2_state_monad$returnS ((~ w__46)))))) (\ (w__48 : bool) . + if w__48 then + let (tmp_280 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__49 : + FaultRecord) . + let (tmp_280 : AddressDescriptor) = ((tmp_280 with<| AddressDescriptor_fault := w__49|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_280|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M))) (\ (outputaddress : 52 + bits) . + let asb = addrselectbottom in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (outputaddress : 52 bits) = + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_slice_concat (( 48 : int):ii) desc asb + ((((~ asb)) + (( 48 : int):ii))) inputaddr (( 0 : int):ii) asb + : 48 words$word)) + : 52 words$word) + else + (slice_slice_concat (( 52 : int):ii) desc asb ((((~ asb)) + (( 48 : int):ii))) + inputaddr (( 0 : int):ii) asb + : 52 words$word)) in sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec desc (( 10 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + if ((~ update_AF)) then + let (tmp_290 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AccessFlagFault ipaddress level acctype iswrite T s2fs1walk)) (\ (w__50 : + FaultRecord) . + let tmp_290 = ((tmp_290 with<| AddressDescriptor_fault := w__50|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_290|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result)) + else + let (tmp_300 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let (tmp_300 : DescriptorUpdate) = ((tmp_300 with<| DescriptorUpdate_AF := T|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_300|>)) in + sail2_state_monad$returnS result + else sail2_state_monad$returnS result) (\ (result : TLBRecord) . + let ((desc : 64 bits), (result : TLBRecord)) = + (if (((update_AP /\ ((((vec_of_bits [access_vec_dec desc (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let ((desc : 64 bits), (result : TLBRecord)) = + (if ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + let (desc : 64 bits) = + ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 64 words$word)) in + let (tmp_320 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let (tmp_320 : DescriptorUpdate) = + ((tmp_320 with<| DescriptorUpdate_AP := T|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_320|>)) in + (desc, result) + else (desc, result)) in + (desc, result) + else (desc, result)) in + let (tmp_330 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let tmp_330 = ((tmp_330 with<| DescriptorUpdate_descaddr := descaddr|>)) in + let result = ((result with<| TLBRecord_descupdate := tmp_330|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M))) (\ (xn : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M))) (\ (pxn : 1 bits) . + let (xn : 1 bits) = + (if apply_nvnv1_effect then + let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)] : 1 words$word)) in + (vec_of_bits [B0] : 1 words$word) + else + let (xn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)] : 1 words$word)) in + let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)] : 1 words$word)) in + xn) in + let (contiguousbit : 1 bits) = + ((vec_of_bits [access_vec_dec desc (( 52 : int):ii)] : 1 words$word)) in + let (nG : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 : int):ii)] : 1 words$word)) in + let (sh : 2 bits) = ((slice desc (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M))) (\ (ap : 3 bits) . + let (ap : 3 bits) = + (if apply_nvnv1_effect then + (concat_vec (vec_of_bits [access_vec_dec desc (( 7 : int):ii)] : 1 words$word) + (vec_of_bits [B0;B1] : 2 words$word) + : 3 words$word) + else + (concat_vec ((slice desc (( 6 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (memattr : 4 bits) = ((slice desc (( 2 : int):ii) (( 4 : int):ii) : 4 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M))) (\ (w__51 : 4 bits) . + let result = ((result with<| TLBRecord_domain := w__51|>)) in + let result = ((result with<| TLBRecord_level := level|>)) in + let result = + ((result with<| + TLBRecord_blocksize := + ((pow2 + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))))|>)) in + let (tmp_480 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_480 = + ((set_slice (( 3 : int):ii) (( 2 : int):ii) tmp_480 (( 1 : int):ii) ((slice ap (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) + : 3 words$word)) in + let (tmp_490 : Permissions) = (result.TLBRecord_perms) in + let tmp_490 = ((tmp_490 with<| Permissions_ap := tmp_480|>)) in + let result = ((result with<| TLBRecord_perms := tmp_490|>)) in + let (tmp_500 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_500 = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_500 (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (tmp_510 : Permissions) = (result.TLBRecord_perms) in + let tmp_510 = ((tmp_510 with<| Permissions_ap := tmp_500|>)) in + let result = ((result with<| TLBRecord_perms := tmp_510|>)) in + let (tmp_520 : Permissions) = (result.TLBRecord_perms) in + let tmp_520 = ((tmp_520 with<| Permissions_xn := xn|>)) in + let result = ((result with<| TLBRecord_perms := tmp_520|>)) in + let (result : TLBRecord) = + (if ((HaveExtendedExecuteNeverExt () )) then + let (tmp_530 : Permissions) = (result.TLBRecord_perms) in + let (tmp_530 : Permissions) = + ((tmp_530 with<| + Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)] : 1 words$word))|>)) in + (result with<| TLBRecord_perms := tmp_530|>) + else result) in + let (tmp_540 : Permissions) = (result.TLBRecord_perms) in + let tmp_540 = ((tmp_540 with<| Permissions_pxn := ((vec_of_bits [B0] : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_540|>)) in + let result = ((result with<| TLBRecord_nG := ((vec_of_bits [B0] : 1 words$word))|>)) in + let (tmp_550 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (S2AttrDecode sh memattr acctype)) (\ (w__52 : MemoryAttributes) . + let tmp_550 = ((tmp_550 with<| AddressDescriptor_memattrs := w__52|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_550|>)) in + let (tmp_560 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let tmp_560 = ((tmp_560 with<| FullAddress_NS := ((vec_of_bits [B1] : 1 words$word))|>)) in + let (tmp_570 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_570 = ((tmp_570 with<| AddressDescriptor_paddress := tmp_560|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_570|>)) in + let (tmp_580 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let tmp_580 = ((tmp_580 with<| FullAddress_physicaladdress := outputaddress|>)) in + let (tmp_590 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_590 = ((tmp_590 with<| AddressDescriptor_paddress := tmp_580|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_590|>)) in + let (tmp_600 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_NoFault () )) (\ (w__53 : FaultRecord) . + let (tmp_600 : AddressDescriptor) = ((tmp_600 with<| AddressDescriptor_fault := w__53|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_600|>)) in + let (result : TLBRecord) = + ((result with<| + TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1] : 1 words$word))))|>)) in + let (result : TLBRecord) = + (if ((HaveCommonNotPrivateTransExt () )) then + (result with<| + TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 : int):ii)] : 1 words$word))|>) + else result) in + sail2_state_monad$returnS result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +val _ = Define ` + ((AArch64_SecondStageTranslate:AddressDescriptor ->(64)words$word -> AccType -> bool -> bool -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk= (sail2_state_monad$bindS + (HasS2Translation () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__0 "HasS2Translation()") + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 12 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (s2_enabled : bool) . + let (secondstage : bool) = T in sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) . sail2_state_monad$bindS + (undefined_TLBRecord () ) (\ (S2 : TLBRecord) . sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . + if s2_enabled then + let ipaddress = + ((slice S1.AddressDescriptor_paddress.FullAddress_physicaladdress (( 0 : int):ii) (( 52 : int):ii) : 52 words$word)) in sail2_state_monad$bindS + (AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1) (\ (w__3 : + TLBRecord) . + let S2 = w__3 in sail2_state_monad$bindS + (if ((((((((((((((~ wasaligned)) /\ (((acctype <> AccType_IFETCH)))))) \/ (((acctype = AccType_DCZVA)))))) /\ (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ ((~ ((IsFault S2.TLBRecord_addrdesc))))))) then + let (tmp_710 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__4 : FaultRecord) . + let (tmp_710 : AddressDescriptor) = ((tmp_710 with<| AddressDescriptor_fault := w__4|>)) in + let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_710|>)) in + sail2_state_monad$returnS S2) + else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) . sail2_state_monad$bindS + (if ((~ ((IsFault S2.TLBRecord_addrdesc)))) then + let (tmp_720 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_CheckS2Permission S2.TLBRecord_perms vaddress ipaddress S2.TLBRecord_level acctype + iswrite s2fs1walk hwupdatewalk) (\ (w__5 : FaultRecord) . + let (tmp_720 : AddressDescriptor) = ((tmp_720 with<| AddressDescriptor_fault := w__5|>)) in + let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_720|>)) in + sail2_state_monad$returnS S2) + else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) . sail2_state_monad$bindS + (if (((((((((((~ s2fs1walk)) /\ ((~ ((IsFault S2.TLBRecord_addrdesc))))))) /\ (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ (((acctype = AccType_IFETCH)))))) then sail2_state_monad$bindS + (AArch64_InstructionDevice S2.TLBRecord_addrdesc vaddress ipaddress S2.TLBRecord_level + acctype iswrite secondstage s2fs1walk) (\ (w__6 : AddressDescriptor) . + let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := w__6|>)) in + sail2_state_monad$returnS S2) + else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((s2fs1walk /\ ((~ ((IsFault S2.TLBRecord_addrdesc)))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + (sail2_state_monad$returnS (((S2.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))))) (\ (w__9 : bool) . sail2_state_monad$bindS + (if w__9 then + let (tmp_730 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_PermissionFault ipaddress S2.TLBRecord_level acctype iswrite secondstage s2fs1walk) (\ (w__10 : + FaultRecord) . + let (tmp_730 : AddressDescriptor) = ((tmp_730 with<| AddressDescriptor_fault := w__10|>)) in + let (S2 : TLBRecord) = ((S2 with<| TLBRecord_addrdesc := tmp_730|>)) in + sail2_state_monad$returnS S2) + else sail2_state_monad$returnS S2) (\ (S2 : TLBRecord) . + let (tmp_740 : AddressDescriptor) = (S2.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_CheckAndUpdateDescriptor_SecondStage S2.TLBRecord_descupdate + S2.TLBRecord_addrdesc.AddressDescriptor_fault vaddress acctype iswrite s2fs1walk hwupdatewalk) (\ (w__11 : + FaultRecord) . + let tmp_740 = ((tmp_740 with<| AddressDescriptor_fault := w__11|>)) in + let S2 = ((S2 with<| TLBRecord_addrdesc := tmp_740|>)) in + CombineS1S2Desc S1 S2.TLBRecord_addrdesc))))))) + else sail2_state_monad$returnS S1)))))))`; + + +val _ = Define ` + ((AArch64_SecondStageWalk:AddressDescriptor ->(64)words$word -> AccType -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) S1 vaddress acctype iswrite size1 hwupdatewalk= (sail2_state_monad$bindS + (HasS2Translation () ) (\ (w__0 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__0 "HasS2Translation()") + (let (s2fs1walk : bool) = T in + let (wasaligned : bool) = T in + AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk))))`; + + +(*val DoubleLockStatus : unit -> M bool*) + +val _ = Define ` + ((DoubleLockStatus:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (ELUsingAArch32 EL1) (\ (w__0 : bool) . + if w__0 then + sail2_state$and_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGOSDLR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGPRCR_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(Halted () ) (\ (w__4 : bool) . sail2_state_monad$returnS ((~ w__4)))) + else + sail2_state$and_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSDLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGPRCR_EL1_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(Halted () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9)))))))`; + + +(*val HaltingAllowed : unit -> M bool*) + +val _ = Define ` + ((HaltingAllowed:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$or_boolS ((Halted () )) ((DoubleLockStatus () ))) (\ (w__2 : bool) . + if w__2 then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (IsSecure () ) (\ (w__3 : bool) . + if w__3 then ExternalSecureInvasiveDebugEnabled () + else ExternalInvasiveDebugEnabled () ))))`; + + +(*val system_exceptions_debug_halt_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_debug_halt_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 14 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + ( sail2_state_monad$bindS(HaltingAllowed () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1)))))) (\ (w__2 : bool) . sail2_state_monad$seqS + (if w__2 then UndefinedFault () else sail2_state_monad$returnS () ) (aarch64_system_exceptions_debug_halt () ))))`; + + +(*val HaltOnBreakpointOrWatchpoint : unit -> M bool*) + +val _ = Define ` + ((HaltOnBreakpointOrWatchpoint:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$and_boolS + (sail2_state$and_boolS ((HaltingAllowed () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 14 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSLSR_EL1_ref : ( 32 words$word) M) (\ (w__3 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))))`; + + +(*val DebugTargetFrom : bool -> M (mword ty2)*) + +val _ = Define ` + ((DebugTargetFrom:bool ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) secure= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (if (((((HaveEL EL2)) /\ ((~ secure))))) then sail2_state_monad$bindS + (ELUsingAArch32 EL2) (\ (w__0 : bool) . + if w__0 then + sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HDCR_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + else + sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + else sail2_state_monad$returnS F) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (target : 2 bits) . + let (target : 2 bits) = + (if route_to_el2 then EL2 + else if ((((((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () ))))) /\ secure))) then EL3 + else EL1) in + sail2_state_monad$returnS target)))))`; + + +(*val DebugTarget : unit -> M (mword ty2)*) + +val _ = Define ` + ((DebugTarget:unit ->(regstate)sail2_state_monad$sequential_state ->((((2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (IsSecure () ) (\ (secure : bool) . (DebugTargetFrom secure : ( 2 words$word) M))))`; + + +(*val SSAdvance : unit -> M unit*) + +val _ = Define ` + ((SSAdvance:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (DebugTarget () : ( 2 words$word) M) (\ (target : 2 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS ( sail2_state_monad$bindS(ELUsingAArch32 target) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (step_enabled : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS step_enabled) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + sail2_state_monad$returnS (((w__2.ProcState_SS = (vec_of_bits [B1] : 1 words$word))))))) (\ (active_not_pending : + bool) . + if active_not_pending then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + else sail2_state_monad$returnS () )))))`; + + +(*val ConditionHolds : mword ty4 -> M bool*) + +val _ = Define ` + ((ConditionHolds:(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cond= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (result : bool) . + let b__0 = ((slice cond (( 1 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + let (result : bool) = (w__0.ProcState_Z = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS result) + else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let (result : bool) = (w__1.ProcState_C = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS result) + else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let (result : bool) = (w__2.ProcState_N = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS result) + else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + let (result : bool) = (w__3.ProcState_V = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS result) + else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_C = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_Z = (vec_of_bits [B0] : 1 words$word)))))) + else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + let (result : bool) = (w__7.ProcState_N = w__8.ProcState_V) in + sail2_state_monad$returnS result)) + else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + sail2_state_monad$returnS (((w__9.ProcState_N = w__10.ProcState_V)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + sail2_state_monad$returnS (((w__11.ProcState_Z = (vec_of_bits [B0] : 1 words$word)))))) + else sail2_state_monad$returnS T) (\ (result : bool) . + let (result : bool) = + (if (((((((vec_of_bits [access_vec_dec cond (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) /\ (((cond <> (vec_of_bits [B1;B1;B1;B1] : 4 words$word))))))) then + ~ result + else result) in + sail2_state_monad$returnS result))))`; + + +(*val aarch64_integer_conditional_select : mword ty4 -> ii -> ii -> bool -> bool -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_integer_conditional_select:(4)words$word -> int -> int -> bool -> bool -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition d l__153 else_inc else_inv m n= + (if (((l__153 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__0 : bool) . + let (result : 8 bits) = + (if w__0 then operand1 + else + let (result : 8 bits) = operand2 in + let (result : 8 bits) = (if else_inv then (not_vec result : 8 words$word) else result) in + if else_inc then (add_vec_int result (( 1 : int):ii) : 8 words$word) + else result) in + aset_X d result)))) + else if (((l__153 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__1 : bool) . + let (result : 16 bits) = + (if w__1 then operand1 + else + let (result : 16 bits) = operand2 in + let (result : 16 bits) = (if else_inv then (not_vec result : 16 words$word) else result) in + if else_inc then (add_vec_int result (( 1 : int):ii) : 16 words$word) + else result) in + aset_X d result)))) + else if (((l__153 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__2 : bool) . + let (result : 32 bits) = + (if w__2 then operand1 + else + let (result : 32 bits) = operand2 in + let (result : 32 bits) = (if else_inv then (not_vec result : 32 words$word) else result) in + if else_inc then (add_vec_int result (( 1 : int):ii) : 32 words$word) + else result) in + aset_X d result)))) + else if (((l__153 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__3 : bool) . + let (result : 64 bits) = + (if w__3 then operand1 + else + let (result : 64 bits) = operand2 in + let (result : 64 bits) = (if else_inv then (not_vec result : 64 words$word) else result) in + if else_inc then (add_vec_int result (( 1 : int):ii) : 64 words$word) + else result) in + aset_X d result)))) + else if (((l__153 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__4 : bool) . + let (result : 128 bits) = + (if w__4 then operand1 + else + let (result : 128 bits) = operand2 in + let (result : 128 bits) = (if else_inv then (not_vec result : 128 words$word) else result) in + if else_inc then (add_vec_int result (( 1 : int):ii) : 128 words$word) + else result) in + aset_X d result)))) + else + let dbytes = (ex_int ((l__153 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_conditional_select_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_conditional_select_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm cond o2 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (condition : 4 bits) = cond in + let (else_inv : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (else_inc : bool) = (o2 = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_conditional_select condition d datasize else_inc else_inv m n)))`; + + +(*val aarch64_integer_conditional_compare_register : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_conditional_compare_register:(4)words$word -> int ->(4)words$word -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition l__148 flags__arg m n sub_op= + (if (((l__148 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (anon10 : 8 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__0 : bool) . + let (flags : 4 words$word) = + (if w__0 then + let ((carry_in : 1 bits), (operand2 : 8 bits)) = + (if sub_op then + let (operand2 : 8 bits) = ((not_vec operand2 : 8 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in : ( 8 words$word # 4 words$word))) in + let (anon10 : 8 bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__148 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (anon10 : 16 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__5 : bool) . + let (flags : 4 words$word) = + (if w__5 then + let ((carry_in : 1 bits), (operand2 : 16 bits)) = + (if sub_op then + let (operand2 : 16 bits) = ((not_vec operand2 : 16 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in : ( 16 words$word # 4 words$word))) in + let (anon10 : 16 bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__148 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (anon10 : 32 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__10 : bool) . + let (flags : 4 words$word) = + (if w__10 then + let ((carry_in : 1 bits), (operand2 : 32 bits)) = + (if sub_op then + let (operand2 : 32 bits) = ((not_vec operand2 : 32 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in : ( 32 words$word # 4 words$word))) in + let (anon10 : 32 bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__148 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (anon10 : 64 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__15 : bool) . + let (flags : 4 words$word) = + (if w__15 then + let ((carry_in : 1 bits), (operand2 : 64 bits)) = + (if sub_op then + let (operand2 : 64 bits) = ((not_vec operand2 : 64 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in : ( 64 words$word # 4 words$word))) in + let (anon10 : 64 bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__148 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (anon10 : 128 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__20 : bool) . + let (flags : 4 words$word) = + (if w__20 then + let ((carry_in : 1 bits), (operand2 : 128 bits)) = + (if sub_op then + let (operand2 : 128 bits) = ((not_vec operand2 : 128 words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in : ( 128 words$word # 4 words$word))) in + let (anon10 : 128 bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_V := tup__3|>)))))))))) + else + let dbytes = (ex_int ((l__148 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val integer_conditional_compare_register_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +val _ = Define ` + ((integer_conditional_compare_register_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm cond o2 Rn o3 nzcv1= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (condition : 4 bits) = cond in + let (flags : 4 bits) = nzcv1 in + aarch64_integer_conditional_compare_register condition datasize flags m n sub_op)))`; + + +(*val aarch64_integer_conditional_compare_immediate : forall 'datasize. Size 'datasize => mword ty4 -> itself 'datasize -> mword ty4 -> mword 'datasize -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_conditional_compare_immediate:(4)words$word -> 'datasize itself ->(4)words$word -> 'datasize words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition datasize flags__arg imm n sub_op= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS + (aget_X datasize n : ( 'datasize words$word) M) (\ (operand1 : 'datasize bits) . + let (operand2 : 'datasize bits) = imm in + let (carry_in : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (anon10 : 'datasize bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__0 : bool) . + let (flags : 4 words$word) = + (if w__0 then + let ((carry_in : 1 bits), (operand2 : 'datasize bits)) = + (if sub_op then + let (operand2 : 'datasize bits) = ((not_vec operand2 : 'datasize words$word)) in + let (carry_in : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + (carry_in, operand2) + else (carry_in, operand2)) in + let (tup__0, tup__1) = + ((AddWithCarry operand1 operand2 carry_in : ( 'datasize words$word # 4 words$word))) in + let (anon10 : 'datasize bits) = tup__0 in + tup__1 + else flags) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_V := tup__3|>)))))))))))`; + + +(*val integer_conditional_compare_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +val _ = Define ` + ((integer_conditional_compare_immediate_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 op S1 imm5 cond o2 Rn o3 nzcv1= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (condition : 4 bits) = cond in + let (flags : 4 bits) = nzcv1 in sail2_state_monad$bindS + (ZeroExtend__0 imm5 ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (imm : 32 + bits) . + aarch64_integer_conditional_compare_immediate condition + ((make_the_value (( 32 : int):ii) : 32 itself)) flags imm n sub_op)) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (condition : 4 bits) = cond in + let (flags : 4 bits) = nzcv1 in sail2_state_monad$bindS + (ZeroExtend__0 imm5 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (imm : 64 + bits) . + aarch64_integer_conditional_compare_immediate condition + ((make_the_value (( 64 : int):ii) : 64 itself)) flags imm n sub_op))))`; + + +(*val ConditionSyndrome : unit -> M (mword ty5)*) + +val _ = Define ` + ((ConditionSyndrome:unit ->(regstate)sail2_state_monad$sequential_state ->((((5)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector (( 5 : int):ii) : ( 5 words$word) M) (\ (syndrome : 5 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (cond : 4 bits) . sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (AArch32_CurrentCond () : ( 4 words$word) M) (\ (w__1 : 4 bits) . + let cond = w__1 in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + if (((w__2.ProcState_T = (vec_of_bits [B0] : 1 words$word)))) then + let syndrome = + ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1] : 1 words$word) : 5 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS ((ConditionHolds cond)) ((ConstrainUnpredictableBool Unpredictable_ESRCONDPASS))) (\ (w__5 : + bool) . + let (syndrome : 5 bits) = + (if w__5 then + (set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 5 words$word) + else (set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) cond : 5 words$word)) in + sail2_state_monad$returnS syndrome) + else if ((IMPDEF_boolean "Condition valid for trapped T32")) then + let (syndrome : 5 bits) = + ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1] : 1 words$word) : 5 words$word)) in + let (syndrome : 5 bits) = ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) cond : 5 words$word)) in + sail2_state_monad$returnS syndrome + else + let syndrome = + ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B0] : 1 words$word) : 5 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__6 : 4 words$word) . + let (syndrome : 5 bits) = ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) w__6 : 5 words$word)) in + sail2_state_monad$returnS syndrome))) + else + let (syndrome : 5 bits) = + ((set_slice (( 5 : int):ii) (( 1 : int):ii) syndrome (( 4 : int):ii) (vec_of_bits [B1] : 1 words$word) : 5 words$word)) in + let (syndrome : 5 bits) = + ((set_slice (( 5 : int):ii) (( 4 : int):ii) syndrome (( 0 : int):ii) (vec_of_bits [B1;B1;B1;B0] : 4 words$word) + : 5 words$word)) in + sail2_state_monad$returnS syndrome)))))`; + + +(*val BranchToAddr : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*) + +val _ = Define ` + ((BranchToAddr:'N words$word -> BranchType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target branch_type= (sail2_state_monad$seqS + (sail2_state_monad$write_regS BranchTaken_ref T) + (let (_ : unit) = (Hint_Branch branch_type) in + if (((((int_of_num (words$word_len target))) = (( 32 : int):ii)))) then sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__0 "UsingAArch32()") + (ZeroExtend__1 (( 64 : int):ii) target : ( 64 words$word) M)) (\ (w__1 : 64 bits) . + sail2_state_monad$write_regS PC_ref w__1)) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((int_of_num (words$word_len target))) = (( 64 : int):ii))))) + ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__3 "((N == 64) && !(UsingAArch32()))") + (sail2_state_monad$write_regS PC_ref ((slice target (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)))))))`; + + +(*val BadMode : mword ty5 -> M bool*) + +val _ = Define ` + ((BadMode:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . + let pat_0 = mode in + let (valid_name : bool) = + (if (((pat_0 = M32_Monitor))) then HaveAArch32EL EL3 + else if (((pat_0 = M32_Hyp))) then HaveAArch32EL EL2 + else if (((pat_0 = M32_FIQ))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_IRQ))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_Svc))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_Abort))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_Undef))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_System))) then HaveAArch32EL EL1 + else if (((pat_0 = M32_User))) then HaveAArch32EL EL0 + else F) in + sail2_state_monad$returnS ((~ valid_name)))))`; + + +(*val aset_Rmode : ii -> mword ty5 -> mword ty32 -> M unit*) + +val _ = Define ` + ((aset_Rmode:int ->(5)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n mode value_name= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((n >= (( 0 : int):ii))) /\ ((n <= (( 14 : int):ii)))))) "((n >= 0) && (n <= 14))") + (IsSecure () )) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ w__0)) then sail2_state_monad$assert_expS (((mode <> M32_Monitor))) "(mode != M32_Monitor)" + else sail2_state_monad$returnS () ) + (BadMode mode)) (\ (w__1 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(BadMode(mode))") + (if (((mode = M32_Monitor))) then + if (((n = (( 13 : int):ii)))) then sail2_state_monad$write_regS SP_mon_ref value_name + else if (((n = (( 14 : int):ii)))) then sail2_state_monad$write_regS LR_mon_ref value_name + else sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__2 : ( 64 bits) list) . + let (tmp_10 : 64 bits) = ((access_list_dec w__2 n : 64 words$word)) in + let tmp_10 = ((update_subrange_vec_dec tmp_10 (( 31 : int):ii) (( 0 : int):ii) value_name : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__3 : ( 64 words$word) list) . + sail2_state_monad$write_regS R_ref ((update_list_dec w__3 n tmp_10 : ( 64 words$word) list)))) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HighestELUsingAArch32 () ))))) + ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER))) (\ (w__5 : bool) . + if w__5 then sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__6 : ( 64 words$word) list) . sail2_state_monad$bindS + (LookUpRIndex n mode) (\ (w__7 : ii) . sail2_state_monad$bindS + (ZeroExtend__0 value_name ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__8 : + 64 words$word) . + sail2_state_monad$write_regS R_ref ((update_list_dec w__6 w__7 w__8 : ( 64 words$word) list))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__9 : ( 64 bits) list) . sail2_state_monad$bindS + (LookUpRIndex n mode) (\ (w__10 : ii) . + let (tmp_20 : 64 bits) = ((access_list_dec w__9 w__10 : 64 words$word)) in + let tmp_20 = ((update_subrange_vec_dec tmp_20 (( 31 : int):ii) (( 0 : int):ii) value_name : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__11 : ( 64 words$word) list) . sail2_state_monad$bindS + (LookUpRIndex n mode) (\ (w__12 : ii) . + sail2_state_monad$write_regS R_ref ((update_list_dec w__11 w__12 tmp_20 : ( 64 words$word) list))))))))))))`; + + +(*val aset_R : ii -> mword ty32 -> M unit*) + +val _ = Define ` + ((aset_R:int ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n value_name= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . aset_Rmode n w__0.ProcState_M value_name)))`; + + +(*val set_LR : mword ty32 -> M unit*) + +val _ = Define ` + ((set_LR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) value_name= (aset_R (( 14 : int):ii) value_name))`; + + +(*val ELFromM32 : mword ty5 -> M (bool * mword ty2)*) + +val _ = Define ` + ((ELFromM32:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode= (sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (el : 2 bits) . sail2_state_monad$bindS + (BadMode mode) (\ (w__0 : bool) . + let (valid_name : bool) = (~ w__0) in + let pat_0 = mode in sail2_state_monad$bindS + (if (((pat_0 = M32_Monitor))) then + let (el : 2 bits) = EL3 in + sail2_state_monad$returnS (el, valid_name) + else if (((pat_0 = M32_Hyp))) then + let el = EL2 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS valid_name) + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(aget_SCR_GEN () : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (w__3 : bool) . + let (valid_name : bool) = w__3 in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_FIQ))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__5 : bool) . + let (el : 2 bits) = (if w__5 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_IRQ))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__7 : bool) . + let (el : 2 bits) = (if w__7 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_Svc))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__8 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__9 : bool) . + let (el : 2 bits) = (if w__9 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_Abort))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__10 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__11 : bool) . + let (el : 2 bits) = (if w__11 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_Undef))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__12 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__13 : bool) . + let (el : 2 bits) = (if w__13 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else if (((pat_0 = M32_System))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL3)) /\ ((HighestELUsingAArch32 () )))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__14 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__15 : bool) . + let (el : 2 bits) = (if w__15 then EL3 else EL1) in + sail2_state_monad$returnS (el, valid_name)) + else + let ((el : 2 bits), (valid_name : bool)) = + (if (((pat_0 = M32_User))) then + let (el : 2 bits) = EL0 in + (el, valid_name) + else + let (valid_name : bool) = F in + (el, valid_name)) in + sail2_state_monad$returnS (el, valid_name)) (\ varstup . let ((el : 2 bits), (valid_name : bool)) = varstup in sail2_state_monad$bindS + (if ((~ valid_name)) then (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) + else sail2_state_monad$returnS el) (\ (el : 2 bits) . + sail2_state_monad$returnS (valid_name, el)))))))`; + + +(*val ELFromSPSR : mword ty32 -> M (bool * mword ty2)*) + +val _ = Define ` + ((ELFromSPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(2)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (el : 2 bits) . sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + let el = ((slice spsr (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) in sail2_state_monad$bindS + (if ((HighestELUsingAArch32 () )) then sail2_state_monad$returnS F + else if ((~ ((HaveEL el)))) then sail2_state_monad$returnS F + else if ((((vec_of_bits [access_vec_dec spsr (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + sail2_state_monad$returnS F + else if ((((((el = EL0))) /\ ((((vec_of_bits [access_vec_dec spsr (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + sail2_state_monad$returnS F + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((el = EL2))) /\ ((HaveEL EL3)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__1 : bool) . + let (valid_name : bool) = (if w__1 then F else T) in + sail2_state_monad$returnS valid_name)) (\ (valid_name : bool) . + sail2_state_monad$returnS (el, valid_name)) + else if ((~ ((HaveAnyAArch32 () )))) then + let (valid_name : bool) = F in + sail2_state_monad$returnS (el, valid_name) + else sail2_state_monad$bindS + (ELFromM32 ((slice spsr (( 0 : int):ii) (( 5 : int):ii) : 5 words$word)) : ((bool # 2 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let (valid_name : bool) = tup__0 in + let (el : 2 bits) = tup__1 in + sail2_state_monad$returnS (el, valid_name))) (\ varstup . let ((el : 2 bits), (valid_name : bool)) = varstup in sail2_state_monad$bindS + (if ((~ valid_name)) then (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) + else sail2_state_monad$returnS el) (\ (el : 2 bits) . + sail2_state_monad$returnS (valid_name, el)))))))`; + + +(*val IllegalExceptionReturn : mword ty32 -> M bool*) + +val _ = Define ` + ((IllegalExceptionReturn:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr= (sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (target : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . sail2_state_monad$bindS + (ELFromSPSR spsr : ((bool # 2 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let valid_name = tup__0 in + let target = tup__1 in + if ((~ valid_name)) then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + if ((((lem$w2ui target)) > ((lem$w2ui w__0.ProcState_EL)))) then sail2_state_monad$returnS T + else + let (spsr_mode_is_aarch32 : bool) = + ((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (target_el_is_aarch32 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (known : bool) . sail2_state_monad$bindS + (ELUsingAArch32K target) (\ varstup . let (tup__0, tup__1) = varstup in + let known = tup__0 in + let target_el_is_aarch32 = tup__1 in sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS known) + (sail2_state$and_boolS (sail2_state_monad$returnS (((target = EL0)))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1)))))) (\ (w__3 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__3 "(known || ((target == EL0) && !(ELUsingAArch32(EL1))))") + (if (((known /\ ((neq_bool spsr_mode_is_aarch32 target_el_is_aarch32))))) then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((~ spsr_mode_is_aarch32)))) (\ (w__5 : bool) . + if w__5 then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ (((target = EL1))))))) + ( sail2_state_monad$bindS(IsSecureBelowEL3 () ) (\ (w__6 : bool) . sail2_state_monad$returnS ((~ w__6))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__9 : bool) . + sail2_state_monad$returnS (if w__9 then T + else F))))))))))))))`; + + +(*val AArch32_WriteMode : mword ty5 -> M unit*) + +val _ = Define ` + ((AArch32_WriteMode:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) mode= (sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (el : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . sail2_state_monad$bindS + (ELFromM32 mode : ((bool # 2 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let valid_name = tup__0 in + let el = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS valid_name "valid") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_M := mode|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_EL := el|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_nRW := ((vec_of_bits [B1] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__3 with<| + ProcState_SP := + (if ((((((mode = M32_User))) \/ (((mode = M32_System)))))) then + (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word))|>))))))))))`; + + +(*val AddrTop : mword ty64 -> bool -> mword ty2 -> M ii*) + +val _ = Define ` + ((AddrTop:(64)words$word -> bool ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address IsInstr el= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((HaveEL el)) "HaveEL(el)") + (S1TranslationRegime__0 el : ( 2 words$word) M)) (\ (regime : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (tbid : 1 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (tbi : 1 bits) . sail2_state_monad$bindS + (ELUsingAArch32 regime) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$returnS (( 31 : int):ii) + else + let pat_0 = regime in sail2_state_monad$bindS + (if (((pat_0 = EL1))) then sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 38 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__2 (( 37 : int):ii)] : 1 words$word))) (\ (w__3 : + 1 words$word) . + let tbi = w__3 in sail2_state_monad$bindS + (if ((HavePACExt () )) then + if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 52 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__5 (( 51 : int):ii)] : 1 words$word)) + else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . + sail2_state_monad$returnS (tbi, tbid))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () ))) ((ELIsInHost el))) (\ (w__8 : bool) . + if w__8 then sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__9 (( 38 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__10 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__10 (( 37 : int):ii)] : 1 words$word))) (\ (w__11 : + 1 words$word) . + let tbi = w__11 in sail2_state_monad$bindS + (if ((HavePACExt () )) then + if ((((vec_of_bits [access_vec_dec address (( 55 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__12 (( 52 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__13 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__13 (( 51 : int):ii)] : 1 words$word)) + else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . + sail2_state_monad$returnS (tbi, tbid))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__15 : 64 bits) . + let tbi = ((vec_of_bits [access_vec_dec w__15 (( 20 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (if ((HavePACExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__16 : 64 bits) . + let (tbid : 1 bits) = ((vec_of_bits [access_vec_dec w__16 (( 29 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS tbid) + else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . + sail2_state_monad$returnS (tbi, tbid)))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__17 : 32 bits) . + let tbi = ((vec_of_bits [access_vec_dec w__17 (( 20 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (if ((HavePACExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M) (\ (w__18 : 32 bits) . + let (tbid : 1 bits) = ((vec_of_bits [access_vec_dec w__18 (( 29 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS tbid) + else sail2_state_monad$returnS tbid) (\ (tbid : 1 bits) . + sail2_state_monad$returnS (tbi, tbid)))) (\ varstup . let ((tbi : 1 bits), (tbid : 1 bits)) = varstup in + sail2_state_monad$returnS (if ((((((tbi = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((~ ((HavePACExt () )))) \/ (((tbid = (vec_of_bits [B0] : 1 words$word))))))) \/ ((~ IsInstr)))))))) + then + (( 55 : int):ii) + else (( 63 : int):ii)))))))))`; + + +(*val AddPAC : mword ty64 -> mword ty64 -> mword ty128 -> bool -> M (mword ty64)*) + +val _ = Define ` + ((AddPAC:(64)words$word ->(64)words$word ->(128)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ptr modifier K1 data= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (PAC : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (ext_ptr : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (extfield : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (selbit : 1 bits) . sail2_state_monad$bindS + (CalculateTBI ptr data) (\ (tbi : bool) . + let (top_bit : int) = (if tbi then (( 55 : int):ii) else (( 63 : int):ii)) in sail2_state_monad$bindS + (PtrHasUpperAndLowerAddRanges () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then sail2_state_monad$bindS + (IsEL1TransRegimeRegs () ) (\ (w__1 : bool) . + if w__1 then + if data then sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__4 : bool) . + let (selbit : 1 bits) = + (if w__4 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) + else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS selbit) + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__11 : bool) . + let (selbit : 1 bits) = + (if w__11 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) + else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS selbit) + else if data then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__14 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (w__16 : bool) . + let (selbit : 1 bits) = + (if w__16 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) + else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS selbit) + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__17 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 38 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__19 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__19 (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M) (\ (w__21 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__21 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M) (\ (w__23 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__25 : bool) . + let (selbit : 1 bits) = + (if w__25 then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) + else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS selbit)) + else + let (selbit : 1 bits) = + (if tbi then (vec_of_bits [access_vec_dec ptr (( 55 : int):ii)] : 1 words$word) + else (vec_of_bits [access_vec_dec ptr (( 63 : int):ii)] : 1 words$word)) in + sail2_state_monad$returnS selbit) (\ (selbit : 1 bits) . sail2_state_monad$bindS + (CalculateBottomPACBit ptr selbit) (\ (w__26 : ii) . + let (bottom_PAC_bit : int) = (ex_int w__26) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let extfield = ((replicate_bits selbit (( 64 : int):ii) : 64 words$word)) in + let (ext_ptr : 64 bits) = + (if tbi then + (concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + ((subrange_subrange_concat + ((((((((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - + (( 1 : int):ii))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) + + + ((bottom_PAC_bit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) + extfield + ((((((~ bottom_PAC_bit)) + (( 56 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) + ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 56 words$word)) + : 64 words$word) + else + (subrange_subrange_concat ((int_of_num (words$word_len PAC))) extfield + ((((((~ bottom_PAC_bit)) + (( 64 : int):ii))) - (( 1 : int):ii))) (( 0 : int):ii) ptr + ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 64 words$word)) in sail2_state_monad$bindS + (ComputePAC ext_ptr modifier ((subrange_vec_dec K1 (( 127 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((subrange_vec_dec K1 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : ( 64 words$word) M) (\ (w__27 : 64 bits) . + let (PAC : 64 bits) = w__27 in + let (PAC : 64 bits) = + (if (((((~ ((is_zero_subrange ptr + ((((((((top_bit - bottom_PAC_bit)) + (( 1 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) bottom_PAC_bit)))) /\ ((~ ((is_ones_subrange ptr + ((((((((top_bit - bottom_PAC_bit)) + (( 1 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) bottom_PAC_bit))))))) then + (update_subrange_vec_dec PAC ((top_bit - (( 1 : int):ii))) ((top_bit - (( 1 : int):ii))) + ((not_vec (vec_of_bits [access_vec_dec PAC ((top_bit - (( 1 : int):ii)))] : 1 words$word) + : 1 words$word)) + : 64 words$word) + else PAC) in + let (result : 64 bits) = + (if tbi then + (concat_vec + ((concat_vec ((subrange_vec_dec ptr (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) selbit : 9 words$word)) + ((subrange_subrange_concat + ((((((((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) + - ((bottom_PAC_bit - (( 1 : int):ii))))) + + + ((bottom_PAC_bit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) PAC + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 55 words$word)) + : 64 words$word) + else + (concat_vec + ((concat_vec ((subrange_vec_dec PAC (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) selbit : 9 words$word)) + ((subrange_subrange_concat + ((((((((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - + (( 1 : int):ii))) + + bottom_PAC_bit)) + - ((bottom_PAC_bit - (( 1 : int):ii))))) + + + ((bottom_PAC_bit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) PAC + ((((((((~ bottom_PAC_bit)) + (( 55 : int):ii))) - (( 1 : int):ii))) + + + bottom_PAC_bit)) bottom_PAC_bit ptr ((bottom_PAC_bit - (( 1 : int):ii))) (( 0 : int):ii) + : 55 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS result)))))))))))))`; + + +(*val AArch64_vESBOperation : unit -> M unit*) + +val _ = Define ` + ((AArch64_vESBOperation:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL = EL1))))))) (\ (w__5 : + bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__5 "((HaveEL(EL2) && !(IsSecure())) && (((PSTATE).EL == EL0) || ((PSTATE).EL == EL1)))") + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (vSEI_enabled : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS vSEI_enabled) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (vSEI_pending : bool) . sail2_state_monad$bindS + (sail2_state$or_boolS ((Halted () )) ((ExternalDebugInterruptsDisabled EL1))) (\ (vintdis : bool) . sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS vintdis) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + sail2_state_monad$returnS (((w__11.ProcState_A = (vec_of_bits [B1] : 1 words$word))))))) (\ (vmasked : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (VDISR_EL2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (VDISR : 32 bits) . + if (((vSEI_pending /\ vmasked))) then sail2_state_monad$bindS + (ELUsingAArch32 EL1) (\ (w__12 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__12 then sail2_state_monad$bindS + (sail2_state_monad$read_regS VDFSR_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS VDFSR_ref : ( 32 words$word) M) (\ (w__14 : 32 bits) . sail2_state_monad$bindS + (AArch32_ReportDeferredSError ((slice w__13 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [access_vec_dec w__14 (( 12 : int):ii)] : 1 words$word) + : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let (VDISR : 32 bits) = w__15 in + sail2_state_monad$returnS () ))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS VSESR_EL2_ref : ( 32 words$word) M) (\ (w__16 : 32 bits) . sail2_state_monad$bindS + (AArch64_ReportDeferredSError ((slice w__16 (( 0 : int):ii) (( 25 : int):ii) : 25 words$word)) : ( 64 words$word) M) (\ (w__17 : 64 + bits) . + let (VDISR_EL2 : 64 bits) = w__17 in + sail2_state_monad$returnS () ))) + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M)) (\ (w__18 : 64 words$word) . + sail2_state_monad$write_regS + HCR_EL2_ref + ((set_slice (( 64 : int):ii) (( 1 : int):ii) w__18 (( 8 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + else sail2_state_monad$returnS () )))))))))`; + + +(*val AArch64_WatchpointByteMatch : ii -> mword ty64 -> M bool*) + +val _ = Define ` + ((AArch64_WatchpointByteMatch:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress= + (sail2_state_monad$catch_early_returnS + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (AddrTop vaddress F w__0.ProcState_EL)) (\ (top : int) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__1 : ( 64 bits) list) . + let (bottom : ii) = + (if ((((vec_of_bits [access_vec_dec ((access_list_dec w__1 n : 64 words$word)) (( 2 : int):ii)] + : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + (( 2 : int):ii) + else (( 3 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__2 : ( 32 bits) list) . + let (byte_select_match : bool) = + ((vec_of_bits [access_vec_dec + ((subrange_vec_dec ((access_list_dec w__2 n : 32 words$word)) (( 12 : int):ii) (( 5 : int):ii) + : 8 words$word)) + ((unsigned_subrange vaddress ((((ex_int bottom)) - (( 1 : int):ii))) + (( 0 : int):ii)))] + : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . + let (mask : ii) = + (lem$w2ui ((subrange_vec_dec ((access_list_dec w__3 n : 32 words$word)) (( 28 : int):ii) (( 24 : int):ii) : 5 words$word))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M))) (\ (MSB : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M))) (\ (LSB1 : 8 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int mask)) > (( 0 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__4 : ( 32 bits) list) . + sail2_state_monad$returnS ((~ ((IsOnes + ((subrange_vec_dec ((access_list_dec w__4 n : 32 words$word)) (( 12 : int):ii) (( 5 : int):ii) + : 8 words$word))))))))) (\ (w__5 : bool) . sail2_state_monad$bindS + (if w__5 then sail2_state_monad$bindS + (sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPMASKANDBAS)) (\ (w__6 : bool) . + let (byte_select_match : bool) = w__6 in + sail2_state_monad$returnS (bottom, byte_select_match)) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__7 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__8 : ( 32 bits) list) . + let LSB1 = + ((and_vec + ((subrange_vec_dec ((access_list_dec w__7 n : 32 words$word)) (( 12 : int):ii) (( 5 : int):ii) + : 8 words$word)) + ((not_vec + ((sub_vec_int + ((subrange_vec_dec ((access_list_dec w__8 n : 32 words$word)) (( 12 : int):ii) (( 5 : int):ii) + : 8 words$word)) (( 1 : int):ii) + : 8 words$word)) + : 8 words$word)) + : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__9 : ( 32 bits) list) . + let MSB = + ((add_vec + ((subrange_vec_dec ((access_list_dec w__9 n : 32 words$word)) (( 12 : int):ii) (( 5 : int):ii) + : 8 words$word)) LSB1 + : 8 words$word)) in + if ((~ ((IsZero ((and_vec MSB ((sub_vec_int MSB (( 1 : int):ii) : 8 words$word)) : 8 words$word)))))) + then sail2_state_monad$bindS + (sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPBASCONTIGUOUS)) (\ (w__10 : bool) . + let (byte_select_match : bool) = w__10 in + let (bottom : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (bottom, byte_select_match)) + else sail2_state_monad$returnS (bottom, byte_select_match))))) (\ varstup . let ((bottom : ii), (byte_select_match : + bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) . sail2_state_monad$bindS + (if (((((((ex_int mask)) > (( 0 : int):ii))) /\ ((((ex_int mask)) <= (( 2 : int):ii)))))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS (ConstrainUnpredictableInteger (( 3 : int):ii) (( 31 : int):ii) Unpredictable_RESWPMASK)) (\ varstup . let (tup__0, tup__1) = varstup in + let c = tup__0 in + let mask = tup__1 in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ ((((((c = Constraint_NONE))) \/ (((c = Constraint_UNKNOWN))))))))) "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))")) + (case c of + Constraint_DISABLED => sail2_state_monad$seqS (sail2_state_monad$early_returnS F : (unit, bool) MR) (sail2_state_monad$returnS mask) + | Constraint_NONE => sail2_state_monad$returnS (( 0 : int):ii) + )) + else sail2_state_monad$returnS mask) (\ (mask : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (WVR_match : bool) . + let (mask2 : int) = (ex_int mask) in + let (bottom2 : int) = (ex_int bottom) in sail2_state_monad$bindS + (if ((((ex_int mask)) > ((ex_int bottom)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref))) (\ (w__11 : ( 64 bits) list) . + let WVR_match = + (subrange_subrange_eq vaddress + ((((((((top - mask2)) + (( 1 : int):ii))) - (( 1 : int):ii))) + + mask2)) mask2 ((access_list_dec w__11 n : 64 words$word)) + ((((((((top - mask2)) + (( 1 : int):ii))) - (( 1 : int):ii))) + + mask2)) mask2) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS WVR_match) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__12 : ( 64 bits) list) . + sail2_state_monad$returnS ((~ ((is_zero_subrange ((access_list_dec w__12 n : 64 words$word)) + ((((((mask2 - bottom2)) - (( 1 : int):ii))) + + bottom2)) bottom2))))))) (\ (w__13 : bool) . + if w__13 then sail2_state_monad$liftRS (ConstrainUnpredictableBool Unpredictable_WPMASKEDBITS) + else sail2_state_monad$returnS WVR_match)) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS DBGWVR_EL1_ref)) (\ (w__15 : ( 64 bits) list) . + let (WVR_match : bool) = + (subrange_subrange_eq vaddress + ((((((((top - bottom2)) + (( 1 : int):ii))) - (( 1 : int):ii))) + + bottom2)) bottom2 ((access_list_dec w__15 n : 64 words$word)) + ((((((((top - bottom2)) + (( 1 : int):ii))) - (( 1 : int):ii))) + + bottom2)) bottom2) in + sail2_state_monad$returnS WVR_match)) (\ (WVR_match : bool) . + sail2_state_monad$returnS (((WVR_match /\ byte_select_match)))))))))))))))))))`; + + +(*val IsOnes_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +val _ = Define ` + ((IsOnes_slice:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) in + sail2_state_monad$returnS (((((and_vec xs m : 'n words$word)) = m))))))`; + + +(*val AArch64_TranslationTableWalk : mword ty52 -> mword ty64 -> AccType -> bool -> bool -> bool -> ii -> M TLBRecord*) + +val _ = Define ` + ((AArch64_TranslationTableWalk:(52)words$word ->(64)words$word -> AccType -> bool -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ipaddress vaddress acctype iswrite secondstage s2fs1walk size1= + (sail2_state_monad$catch_early_returnS + ( sail2_state_monad$bindS (sail2_state_monad$seqS(if ((~ secondstage)) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((S1TranslationRegime__1 () : ( 2 words$word) M))) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (ELUsingAArch32 w__0)) (\ (w__1 : bool) . sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((~ w__1)) ""))) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsSecure () )) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL2)) (\ (w__4 : bool) . sail2_state_monad$returnS ((~ w__4))))) + (sail2_state_monad$liftRS ((HasS2Translation () )))) (\ (w__7 : bool) . + sail2_state_monad$liftRS (sail2_state_monad$assert_expS w__7 ""))) + (sail2_state_monad$liftRS (undefined_TLBRecord () ))) (\ (result : TLBRecord) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (baseregister : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (inputaddr : 64 bits) . + let (tmp_170 : FaultRecord) = (descaddr.AddressDescriptor_fault) in + let tmp_170 = ((tmp_170 with<| FaultRecord_typ := Fault_None|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_fault := tmp_170|>)) in + let (tmp_180 : MemoryAttributes) = (descaddr.AddressDescriptor_memattrs) in + let tmp_180 = ((tmp_180 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := tmp_180|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (startsizecheck : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsizecheck : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (startlevel : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (level : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (stride : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (firstblocklevel : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (grainsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hierattrsdisabled : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AP : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (update_AF : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (singlepriv : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (lookupsecure : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (reversedescriptors : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (disabled : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (basefound : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M))) (\ (ps : 3 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_min : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize_max : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (midgrain : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (largegrain : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (top : ii) . sail2_state_monad$bindS + (if ((~ secondstage)) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress : ( 64 words$word) M))) (\ (w__8 : 64 bits) . + let inputaddr = w__8 in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (AddrTop inputaddr (((acctype = AccType_IFETCH))) w__9.ProcState_EL)) (\ (w__10 : + ii) . + let top = w__10 in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . sail2_state_monad$bindS + (if (((w__11.ProcState_EL = EL3))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__12 : 32 bits) . + let largegrain = + (((slice w__12 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__13 : 32 bits) . + let midgrain = + (((slice w__13 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__14 : 32 bits) . + let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__14 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__15 : 32 bits) . + let ps = ((slice w__15 (( 16 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + (( 1 : int):ii))))))) (\ (w__17 : + bool) . + let basefound = w__17 in + let disabled = F in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL3_ref : ( 64 words$word) M))) (\ (w__18 : 64 bits) . + let baseregister = w__18 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__19 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__20 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__21 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__19 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__20 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__21 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__22 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__22|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M))) (\ (w__23 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__23 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let lookupsecure = T in + let singlepriv = T in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__24 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__24 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__25 : bool) . + let update_AF = w__25 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__26 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__26 (( 22 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__27 : bool) . + let update_AP = w__27 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL3_ref : ( 32 words$word) M))) (\ (w__28 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__29 : bool) . + let (hierattrsdisabled : bool) = w__29 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP))))))))))))))))) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (IsInHost () )) (\ (w__30 : bool) . + if w__30 then sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec inputaddr top] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__31 : 64 bits) . + let largegrain = + (((slice w__31 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__32 : 64 bits) . + let midgrain = + (((slice w__32 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__33 : 64 bits) . + let inputsize = + ((( 64 : int):ii) - ((lem$w2ui ((slice w__33 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : + ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + + (( 1 : int):ii))))))) (\ (w__35 : bool) . + let basefound = w__35 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__36 : 64 bits) . + let disabled = + ((vec_of_bits [access_vec_dec w__36 (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL2_ref : ( 64 words$word) M))) (\ (w__37 : 64 bits) . + let baseregister = w__37 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__38 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__39 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__40 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__38 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__39 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__40 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__41 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__41|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__42 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__43 : bool) . + let (hierattrsdisabled : bool) = w__43 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain)))))))))))))) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__44 : 64 bits) . + let inputsize = + ((( 64 : int):ii) - ((lem$w2ui ((slice w__44 (( 16 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__45 : 64 bits) . + let largegrain = + (((slice w__45 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__46 : 64 bits) . + let midgrain = + (((slice w__46 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : + ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsOnes_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + + (( 1 : int):ii))))))) (\ (w__48 : bool) . + let basefound = w__48 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__49 : 64 bits) . + let disabled = + ((vec_of_bits [access_vec_dec w__49 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR1_EL2_ref : ( 64 words$word) M))) (\ (w__50 : 64 bits) . + let baseregister = w__50 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__51 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__52 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__53 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__51 (( 28 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__52 (( 26 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__53 (( 24 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__54 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__54|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__55 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__55 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__56 : bool) . + let (hierattrsdisabled : bool) = w__56 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain))))))))))))))) (\ varstup . let ((basefound : bool), (baseregister : 64 + bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled : + bool), (inputsize : ii), (largegrain : bool), (midgrain : bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__57 : 64 bits) . + let ps = ((slice w__57 (( 32 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M))) (\ (w__58 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__58 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let lookupsecure = F in + let singlepriv = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__59 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__59 (( 39 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__60 : bool) . + let update_AF = w__60 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__61 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__61 (( 40 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__62 : bool) . + let (update_AP : bool) = w__62 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP)))))) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__63 : ProcState) . + if (((w__63.ProcState_EL = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__64 : 64 bits) . + let inputsize = + ((( 64 : int):ii) - ((lem$w2ui ((slice w__64 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__65 : 64 bits) . + let largegrain = + (((slice w__65 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__66 : 64 bits) . + let midgrain = + (((slice w__66 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : + ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__67 : 64 bits) . + let ps = ((slice w__67 (( 16 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + + (( 1 : int):ii))))))) (\ (w__69 : bool) . + let basefound = w__69 in + let disabled = F in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL2_ref : ( 64 words$word) M))) (\ (w__70 : 64 bits) . + let baseregister = w__70 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__71 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__72 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__73 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__71 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__72 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__73 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__74 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__74|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M))) (\ (w__75 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__75 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let lookupsecure = F in + let singlepriv = T in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__76 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__76 (( 39 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__77 : bool) . + let update_AF = w__77 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__78 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__78 (( 40 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__79 : bool) . + let update_AP = w__79 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL2_ref : ( 64 words$word) M))) (\ (w__80 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__80 (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__81 : bool) . + let (hierattrsdisabled : bool) = w__81 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP))))))))))))))))) + else sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec inputaddr top] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__82 : 64 bits) . + let inputsize = + ((( 64 : int):ii) - ((lem$w2ui ((slice w__82 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__83 : 64 bits) . + let largegrain = + (((slice w__83 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__84 : 64 bits) . + let midgrain = + (((slice w__84 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : + ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + + (( 1 : int):ii))))))) (\ (w__86 : bool) . + let basefound = w__86 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__87 : 64 bits) . + let disabled = + ((vec_of_bits [access_vec_dec w__87 (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR0_EL1_ref : ( 64 words$word) M))) (\ (w__88 : 64 bits) . + let baseregister = w__88 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__89 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__90 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__91 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__89 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__90 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__91 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__92 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__92|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__93 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__93 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__94 : bool) . + let (hierattrsdisabled : bool) = w__94 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain)))))))))))))) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__95 : 64 bits) . + let inputsize = + ((( 64 : int):ii) - ((lem$w2ui ((slice w__95 (( 16 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__96 : 64 bits) . + let largegrain = + (((slice w__96 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__97 : 64 bits) . + let midgrain = + (((slice w__97 (( 30 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_max + else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : + ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = + (if (((c = Constraint_FORCE))) then inputsize_min + else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsOnes_slice inputaddr inputsize + ((((((ex_int top)) - ((ex_int inputsize)))) + + (( 1 : int):ii))))))) (\ (w__99 : bool) . + let basefound = w__99 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__100 : 64 bits) . + let disabled = + ((vec_of_bits [access_vec_dec w__100 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TTBR1_EL1_ref : ( 64 words$word) M))) (\ (w__101 : 64 bits) . + let baseregister = w__101 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__102 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__103 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__104 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__102 (( 28 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__103 (( 26 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__104 (( 24 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__105 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__105|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((AArch64_HaveHPDExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__106 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__106 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__107 : bool) . + let (hierattrsdisabled : bool) = w__107 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + midgrain))))))))))))))) (\ varstup . let ((basefound : bool), (baseregister : 64 + bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled : + bool), (inputsize : ii), (largegrain : bool), (midgrain : bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__108 : 64 bits) . + let ps = ((slice w__108 (( 32 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M))) (\ (w__109 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__109 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (IsSecure () )) (\ (w__110 : bool) . + let lookupsecure = w__110 in + let singlepriv = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__111 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__111 (( 39 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__112 : bool) . + let update_AF = w__112 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS TCR_EL1_ref : ( 64 words$word) M))) (\ (w__113 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__113 (( 40 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__114 : bool) . + let (update_AP : bool) = w__114 in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + hierattrsdisabled, + inputsize, + largegrain, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + update_AF, + update_AP)))))))))) (\ varstup . let ((basefound : bool), (baseregister : 64 + bits), (descaddr : AddressDescriptor), (disabled : bool), (hierattrsdisabled : bool), (inputsize : + ii), (largegrain : bool), (lookupsecure : bool), (midgrain : bool), (ps : 3 bits), (reversedescriptors : + bool), (singlepriv : bool), (update_AF : bool), (update_AP : bool)) = varstup in + let ((firstblocklevel : ii), (grainsize : ii)) = + (if largegrain then + let (grainsize : ii) = ((( 16 : int):ii)) in + let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in + (firstblocklevel, grainsize) + else + let ((firstblocklevel : ii), (grainsize : ii)) = + (if midgrain then + let (grainsize : ii) = ((( 14 : int):ii)) in + let (firstblocklevel : ii) = ((( 2 : int):ii)) in + (firstblocklevel, grainsize) + else + let (grainsize : ii) = ((( 12 : int):ii)) in + let (firstblocklevel : ii) = ((( 1 : int):ii)) in + (firstblocklevel, grainsize)) in + (firstblocklevel, grainsize)) in + let (stride : ii) = (((ex_int grainsize)) - (( 3 : int):ii)) in + let (level : ii) = + ((( 4 : int):ii) - + ((ex_int + ((clg + (((((real_of_int ((((ex_int inputsize)) - ((ex_int grainsize))))))) + / + (((real_of_int stride)))))))))) in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + firstblocklevel, + grainsize, + hierattrsdisabled, + inputaddr, + inputsize, + largegrain, + level, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + stride, + update_AF, + update_AP)))))) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) ipaddress : ( 64 words$word) M))) (\ (w__115 : 64 bits) . + let inputaddr = w__115 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__116 : 32 bits) . + let inputsize = ((( 64 : int):ii) - ((lem$w2ui ((slice w__116 (( 0 : int):ii) (( 6 : int):ii) : 6 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__117 : 32 bits) . + let largegrain = + (((slice w__117 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__118 : 32 bits) . + let midgrain = + (((slice w__118 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)) in + let inputsize_max = + (if (((((Have52BitVAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_max else inputsize) in + sail2_state_monad$returnS (c, inputsize)) + else sail2_state_monad$returnS (c, inputsize)) (\ varstup . let ((c : Constraint), (inputsize : ii)) = varstup in + let inputsize_min = ((( 64 : int):ii) - (( 39 : int):ii)) in sail2_state_monad$bindS + (if ((((ex_int inputsize)) < ((ex_int inputsize_min)))) then + let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_FORCE))) \/ (((c = Constraint_FAULT)))))) "")) + (let (inputsize : ii) = (if (((c = Constraint_FORCE))) then inputsize_min else inputsize) in + sail2_state_monad$returnS inputsize) + else sail2_state_monad$returnS inputsize) (\ (inputsize : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__119 : 32 bits) . + let ps = ((slice w__119 (( 16 : int):ii) (( 3 : int):ii) : 3 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((((ex_int inputsize)) >= ((ex_int inputsize_min)))) /\ ((((ex_int inputsize)) <= ((ex_int inputsize_max)))))))) + (sail2_state_monad$liftRS ((IsZero_slice inputaddr inputsize + ((((~ ((ex_int inputsize)))) + (( 64 : int):ii))))))) (\ (w__121 : + bool) . + let basefound = w__121 in + let disabled = F in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTTBR_EL2_ref : ( 64 words$word) M))) (\ (w__122 : 64 bits) . + let baseregister = w__122 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__123 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__124 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__125 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (WalkAttrDecode ((slice w__123 (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__124 (( 10 : int):ii) (( 2 : int):ii) : 2 words$word)) + ((slice w__125 (( 12 : int):ii) (( 2 : int):ii) : 2 words$word)) secondstage)) (\ (w__126 : + MemoryAttributes) . + let descaddr = ((descaddr with<| AddressDescriptor_memattrs := w__126|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M))) (\ (w__127 : 32 bits) . + let reversedescriptors = + ((vec_of_bits [access_vec_dec w__127 (( 25 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let lookupsecure = F in + let singlepriv = T in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveAccessFlagUpdateExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__128 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__128 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__129 : bool) . + let update_AF = w__129 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveDirtyBitModifierExt () )) /\ update_AF)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__130 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__130 (( 22 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__131 : bool) . + let update_AP = w__131 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS VTCR_EL2_ref : ( 32 words$word) M))) (\ (w__132 : 32 bits) . + let startlevel = (lem$w2ui ((slice w__132 (( 6 : int):ii) (( 2 : int):ii) : 2 words$word))) in + let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) = + (if largegrain then + let (grainsize : ii) = ((( 16 : int):ii)) in + let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = (if ((Have52BitPAExt () )) then (( 1 : int):ii) else (( 2 : int):ii)) in + (firstblocklevel, grainsize, level) + else + let ((firstblocklevel : ii), (grainsize : ii), (level : ii)) = + (if midgrain then + let (grainsize : ii) = ((( 14 : int):ii)) in + let (level : ii) = ((( 3 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = ((( 2 : int):ii)) in + (firstblocklevel, grainsize, level) + else + let (grainsize : ii) = ((( 12 : int):ii)) in + let (level : ii) = ((( 2 : int):ii) - ((ex_int startlevel))) in + let (firstblocklevel : ii) = ((( 1 : int):ii)) in + (firstblocklevel, grainsize, level)) in + (firstblocklevel, grainsize, level)) in + let stride = (((ex_int grainsize)) - (( 3 : int):ii)) in + let (basefound : bool) = + (if largegrain then + if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then + F + else basefound + else if midgrain then + if ((((((((ex_int level)) = (( 0 : int):ii)))) \/ ((((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 40 : int):ii))))))))) then + F + else basefound + else if (((((((ex_int level)) < (( 0 : int):ii))) \/ ((((((((ex_int level)) = (( 0 : int):ii)))) /\ ((((ex_int ((PAMax () )))) <= (( 42 : int):ii))))))))) then + F + else basefound) in + let inputsizecheck = inputsize in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int inputsize)) > ((ex_int ((PAMax () ))))))) + (sail2_state$or_boolS ( sail2_state_monad$bindS(sail2_state_monad$liftRS (ELUsingAArch32 EL1)) (\ (w__133 : bool) . sail2_state_monad$returnS ((~ w__133)))) + (sail2_state_monad$returnS ((((ex_int inputsize)) > (( 40 : int):ii)))))) (\ (w__135 : bool) . sail2_state_monad$bindS + (if w__135 then + (case ((ConstrainUnpredictable Unpredictable_LARGEIPA)) of + Constraint_FORCE => + let (inputsize : ii) = (PAMax () ) in + let (inputsizecheck : ii) = (PAMax () ) in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | Constraint_FORCENOSLCHECK => + let (inputsize : ii) = (PAMax () ) in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | Constraint_FAULT => + let (basefound : bool) = F in + sail2_state_monad$returnS (basefound, inputsize, inputsizecheck) + | _ => sail2_state_monad$seqS (sail2_state_monad$liftRS (Unreachable () )) (sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) + ) + else sail2_state_monad$returnS (basefound, inputsize, inputsizecheck)) (\ varstup . let ((basefound : + bool), (inputsize : ii), (inputsizecheck : ii)) = varstup in + let (startsizecheck : ii) = + (((ex_int inputsizecheck)) - + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + ((ex_int grainsize))))) in + let (basefound : bool) = + (if (((((((ex_int startsizecheck)) < (( 1 : int):ii))) \/ ((((ex_int startsizecheck)) > ((((ex_int stride)) + (( 4 : int):ii)))))))) then + F + else basefound) in + sail2_state_monad$returnS (basefound, + baseregister, + descaddr, + disabled, + firstblocklevel, + grainsize, + hierattrsdisabled, + inputaddr, + inputsize, + largegrain, + level, + lookupsecure, + midgrain, + ps, + reversedescriptors, + singlepriv, + stride, + update_AF, + update_AP))))))))))))))))))))) (\ varstup . let ((basefound : bool), (baseregister : 64 bits), (descaddr : + AddressDescriptor), (disabled : bool), (firstblocklevel : ii), (grainsize : ii), (hierattrsdisabled : + bool), (inputaddr : 64 bits), (inputsize : ii), (largegrain : bool), (level : ii), (lookupsecure : + bool), (midgrain : bool), (ps : 3 bits), (reversedescriptors : bool), (singlepriv : bool), (stride : + ii), (update_AF : bool), (update_AP : bool)) = varstup in + if (((((~ basefound)) \/ disabled))) then + let level = ((( 0 : int):ii)) in + let (tmp_190 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__136 : + FaultRecord) . + let (tmp_190 : AddressDescriptor) = ((tmp_190 with<| AddressDescriptor_fault := w__136|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_190|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (outputsize : ii) . + let b__0 = ps in + let (outputsize : ii) = + (if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then (( 36 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then (( 40 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then (( 42 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then (( 44 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then (( 48 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + if (((((Have52BitPAExt () )) /\ largegrain))) then (( 52 : int):ii) + else (( 48 : int):ii) + else (( 48 : int):ii)) in + let (outputsize : ii) = + (if ((((ex_int outputsize)) > ((ex_int ((PAMax () )))))) then PAMax () + else outputsize) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice baseregister outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__137 : + bool) . + sail2_state_monad$returnS ((~ w__137))))) (\ (w__138 : bool) . + if w__138 then + let level = ((( 0 : int):ii)) in + let (tmp_200 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__139 : + FaultRecord) . + let (tmp_200 : AddressDescriptor) = ((tmp_200 with<| AddressDescriptor_fault := w__139|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_200|>)) in + sail2_state_monad$returnS result) + else + let baselowerbound = + ((((( 3 : int):ii) + ((ex_int inputsize)))) - + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M)))) (\ (baseaddress : 52 bits) . sail2_state_monad$bindS + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + let z = (if ((baselowerbound < (( 6 : int):ii))) then (( 6 : int):ii) else baselowerbound) in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (baseaddress : 52 bits) = + ((concat_vec ((slice baseregister (( 2 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_zeros_concat ((((((~ z)) + (( 48 : int):ii))) + z)) + baseregister z ((((~ z)) + (( 48 : int):ii))) z + : 48 words$word)) + : 52 words$word)) in + sail2_state_monad$returnS baseaddress) + else + let (baseaddress : 52 bits) = + ((place_slice (( 52 : int):ii) baseregister baselowerbound + ((((~ baselowerbound)) + (( 48 : int):ii))) baselowerbound + : 52 words$word)) in + sail2_state_monad$returnS baseaddress) (\ (baseaddress : 52 bits) . + let (ns_table : 1 bits) = + (if lookupsecure then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word)) in + let (ap_table : 2 bits) = ((vec_of_bits [B0;B0] : 2 words$word)) in + let (xn_table : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (pxn_table : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + let (addrselecttop : ii) = (((ex_int inputsize)) - (( 1 : int):ii)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M))) (\ (w__140 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__140 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M))) (\ (w__142 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__142 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (apply_nvnv1_effect : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (blocktranslate : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (desc : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hwupdatewalk : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (addrselectbottom : ii) . sail2_state_monad$bindS + (sail2_state$untilS (accdesc, + addrselectbottom, + addrselecttop, + ap_table, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + hwupdatewalk, + level, + ns_table, + pxn_table, + result, + xn_table) + (\ varstup . + let (accdesc, + addrselectbottom, + addrselecttop, + ap_table, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + hwupdatewalk, + level, + ns_table, + pxn_table, + result, + xn_table) = varstup in + sail2_state_monad$returnS blocktranslate) + (\ varstup . + let (accdesc, + addrselectbottom, + addrselecttop, + ap_table, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + hwupdatewalk, + level, + ns_table, + pxn_table, + result, + xn_table) = varstup in + let addrselectbottom = + ((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend_slice_append (( 52 : int):ii) inputaddr addrselectbottom + ((((((ex_int addrselecttop)) - ((ex_int addrselectbottom)))) + + + (( 1 : int):ii))) (vec_of_bits [B0;B0;B0] : 3 words$word) + : ( 52 words$word) M))) (\ (index : 52 bits) . + let (tmp_210 : FullAddress) = (descaddr.AddressDescriptor_paddress) in + let tmp_210 = + ((tmp_210 with<| + FullAddress_physicaladdress := ((or_vec baseaddress index : 52 words$word))|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_210|>)) in + let (tmp_220 : FullAddress) = (descaddr.AddressDescriptor_paddress) in + let tmp_220 = ((tmp_220 with<| FullAddress_NS := ns_table|>)) in + let descaddr = ((descaddr with<| AddressDescriptor_paddress := tmp_220|>)) in sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS secondstage) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (HasS2Translation () )) (\ (w__143 : bool) . sail2_state_monad$returnS ((~ w__143))))) (\ (w__144 : + bool) . sail2_state_monad$bindS + (if w__144 then + let (descaddr2 : AddressDescriptor) = descaddr in + sail2_state_monad$returnS (descaddr2, hwupdatewalk, result) + else + let hwupdatewalk = F in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_SecondStageWalk descaddr vaddress acctype iswrite (( 8 : int):ii) + hwupdatewalk)) (\ (w__145 : AddressDescriptor) . + let descaddr2 = w__145 in sail2_state_monad$bindS + (if ((IsFault descaddr2)) then + let (tmp_230 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_230 = + ((tmp_230 with<| AddressDescriptor_fault := (descaddr2.AddressDescriptor_fault)|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_230|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result) + else sail2_state_monad$returnS result) (\ (result : TLBRecord) . + sail2_state_monad$returnS (descaddr2, hwupdatewalk, result)))) (\ varstup . let ((descaddr2 : + AddressDescriptor), (hwupdatewalk : bool), (result : TLBRecord)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ZeroExtend__1 (( 64 : int):ii) vaddress : ( 64 words$word) M))) (\ (w__146 : 64 bits) . + let descaddr2 = ((descaddr2 with<| AddressDescriptor_vaddress := w__146|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level)) (\ (w__147 : + AccessDescriptor) . + let accdesc = w__147 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc : ( 64 words$word) M))) (\ (w__148 : 64 + bits) . + let desc = w__148 in sail2_state_monad$bindS + (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc : ( 64 words$word) M)) + else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . sail2_state_monad$bindS + (if (((((((vec_of_bits [access_vec_dec desc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) \/ ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((ex_int level)) = (( 3 : int):ii)))))))))) + then + let (tmp_240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage + s2fs1walk)) (\ (w__150 : FaultRecord) . + let tmp_240 = ((tmp_240 with<| AddressDescriptor_fault := w__150|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_240|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) + (sail2_state_monad$returnS (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table))) + else if ((((((((slice desc (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ (((((ex_int level)) = (( 3 : int):ii))))))) + then + let (blocktranslate : bool) = T in + sail2_state_monad$returnS (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table) + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__151 : + bool) . + sail2_state_monad$returnS ((~ w__151)))))) (\ (w__153 : bool) . + if w__153 then + let (tmp_250 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage + s2fs1walk)) (\ (w__154 : FaultRecord) . + let tmp_250 = ((tmp_250 with<| AddressDescriptor_fault := w__154|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_250|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) + (sail2_state_monad$returnS (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table))) + else + let gsz = grainsize in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (baseaddress : 52 bits) = + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_zeros_concat + ((((((~ gsz)) + (( 48 : int):ii))) + gsz)) desc + gsz ((((~ gsz)) + (( 48 : int):ii))) gsz + : 48 words$word)) + : 52 words$word) + else + (place_slice (( 52 : int):ii) desc gsz ((((~ gsz)) + (( 48 : int):ii))) + gsz + : 52 words$word)) in + let (ns_table : 1 bits) = + (if ((~ secondstage)) then + (or_vec ns_table (vec_of_bits [access_vec_dec desc (( 63 : int):ii)] : 1 words$word) + : 1 words$word) + else ns_table) in + let ((ap_table : 2 bits), (pxn_table : 1 bits), (xn_table : 1 bits)) = + (if (((((~ secondstage)) /\ ((~ hierattrsdisabled))))) then + let (ap_table : 2 bits) = + ((set_slice (( 2 : int):ii) (( 1 : int):ii) ap_table (( 1 : int):ii) + ((or_vec (vec_of_bits [access_vec_dec ap_table (( 1 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec desc (( 62 : int):ii)] : 1 words$word) + : 1 words$word)) + : 2 words$word)) in + let ((pxn_table : 1 bits), (xn_table : 1 bits)) = + (if apply_nvnv1_effect then + let (pxn_table : 1 bits) = + ((or_vec pxn_table + (vec_of_bits [access_vec_dec desc (( 60 : int):ii)] : 1 words$word) + : 1 words$word)) in + (pxn_table, xn_table) + else + let (xn_table : 1 bits) = + ((or_vec xn_table + (vec_of_bits [access_vec_dec desc (( 60 : int):ii)] : 1 words$word) + : 1 words$word)) in + (pxn_table, xn_table)) in + let ((ap_table : 2 bits), (pxn_table : 1 bits)) = + (if ((~ singlepriv)) then + let ((ap_table : 2 bits), (pxn_table : 1 bits)) = + (if ((~ apply_nvnv1_effect)) then + let (pxn_table : 1 bits) = + ((or_vec pxn_table + (vec_of_bits [access_vec_dec desc (( 59 : int):ii)] : 1 words$word) + : 1 words$word)) in + let (ap_table : 2 bits) = + ((set_slice (( 2 : int):ii) (( 1 : int):ii) ap_table (( 0 : int):ii) + ((or_vec + (vec_of_bits [access_vec_dec ap_table (( 0 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec desc (( 61 : int):ii)] : 1 words$word) + : 1 words$word)) + : 2 words$word)) in + (ap_table, pxn_table) + else (ap_table, pxn_table)) in + (ap_table, pxn_table) + else (ap_table, pxn_table)) in + (ap_table, pxn_table, xn_table) + else (ap_table, pxn_table, xn_table)) in + let (level : ii) = (((ex_int level)) + (( 1 : int):ii)) in + let (addrselecttop : ii) = (((ex_int addrselectbottom)) - (( 1 : int):ii)) in + let (blocktranslate : bool) = F in + sail2_state_monad$returnS (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table)))) (\ varstup . let ((addrselecttop : ii), (ap_table : 2 + bits), (baseaddress : 52 bits), (blocktranslate : bool), (level : ii), (ns_table : 1 + bits), (pxn_table : 1 bits), (result : TLBRecord), (xn_table : 1 bits)) = varstup in + sail2_state_monad$returnS (accdesc, + addrselectbottom, + addrselecttop, + ap_table, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + hwupdatewalk, + level, + ns_table, + pxn_table, + result, + xn_table))))))))))) (\ varstup . let ((accdesc : AccessDescriptor), (addrselectbottom : + ii), (addrselecttop : ii), (ap_table : 2 bits), (baseaddress : 52 bits), (blocktranslate : + bool), (desc : 64 bits), (descaddr : AddressDescriptor), (descaddr2 : + AddressDescriptor), (hwupdatewalk : bool), (level : ii), (ns_table : 1 bits), (pxn_table : 1 + bits), (result : TLBRecord), (xn_table : 1 bits)) = varstup in + if ((((ex_int level)) < ((ex_int firstblocklevel)))) then + let (tmp_260 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__155 : + FaultRecord) . + let (tmp_260 : AddressDescriptor) = ((tmp_260 with<| AddressDescriptor_fault := w__155|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_260|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (contiguousbitcheck : bool) . + let (contiguousbitcheck : bool) = + (if largegrain then + ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii)))) + else if midgrain then + ((((((ex_int level)) = (( 2 : int):ii)))) /\ ((((ex_int inputsize)) < (( 30 : int):ii)))) + else ((((((ex_int level)) = (( 1 : int):ii)))) /\ ((((ex_int inputsize)) < (( 34 : int):ii))))) in sail2_state_monad$bindS + (if (((contiguousbitcheck /\ ((((vec_of_bits [access_vec_dec desc (( 52 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (w__156 : bool) . + if w__156 then + let (tmp_270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_TranslationFault ipaddress level acctype iswrite secondstage + s2fs1walk)) (\ (w__157 : FaultRecord) . + let tmp_270 = ((tmp_270 with<| AddressDescriptor_fault := w__157|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_270|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result)) + else sail2_state_monad$returnS result) + else sail2_state_monad$returnS result) (\ (result : TLBRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS ((((((((((ex_int outputsize)) < (( 52 : int):ii))) /\ largegrain))) /\ ((~ ((IsZero ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS ((((ex_int outputsize)) < (( 48 : int):ii)))) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (IsZero_slice desc outputsize + ((((~ ((ex_int outputsize)))) + (( 48 : int):ii))))) (\ (w__158 : + bool) . + sail2_state_monad$returnS ((~ w__158)))))) (\ (w__160 : bool) . + if w__160 then + let (tmp_280 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)) (\ (w__161 : + FaultRecord) . + let (tmp_280 : AddressDescriptor) = + ((tmp_280 with<| AddressDescriptor_fault := w__161|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_280|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M))) (\ (outputaddress : 52 + bits) . + let asb = addrselectbottom in sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS T "")) + (let (outputaddress : 52 bits) = + (if (((((ex_int outputsize)) = (( 52 : int):ii)))) then + (concat_vec ((slice desc (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) + ((slice_slice_concat (( 48 : int):ii) desc asb + ((((~ asb)) + (( 48 : int):ii))) inputaddr (( 0 : int):ii) asb + : 48 words$word)) + : 52 words$word) + else + (slice_slice_concat (( 52 : int):ii) desc asb ((((~ asb)) + (( 48 : int):ii))) + inputaddr (( 0 : int):ii) asb + : 52 words$word)) in + let (tmp_330 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let tmp_330 = ((tmp_330 with<| DescriptorUpdate_AF := F|>)) in + let tmp_330 = ((tmp_330 with<| DescriptorUpdate_AP := F|>)) in + let tmp_330 = ((tmp_330 with<| DescriptorUpdate_descaddr := descaddr|>)) in + let result = ((result with<| TLBRecord_descupdate := tmp_330|>)) in sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec desc (( 10 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + if ((~ update_AF)) then + let (tmp_290 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_AccessFlagFault ipaddress level acctype iswrite secondstage + s2fs1walk)) (\ (w__162 : FaultRecord) . + let tmp_290 = ((tmp_290 with<| AddressDescriptor_fault := w__162|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_290|>)) in sail2_state_monad$seqS + (sail2_state_monad$early_returnS result : (unit, TLBRecord) MR) (sail2_state_monad$returnS result)) + else + let (tmp_300 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let (tmp_300 : DescriptorUpdate) = ((tmp_300 with<| DescriptorUpdate_AF := T|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_300|>)) in + sail2_state_monad$returnS result + else sail2_state_monad$returnS result) (\ (result : TLBRecord) . + let ((desc : 64 bits), (result : TLBRecord)) = + (if (((update_AP /\ ((((vec_of_bits [access_vec_dec desc (( 51 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let ((desc : 64 bits), (result : TLBRecord)) = + (if (((((~ secondstage)) /\ ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + let (desc : 64 bits) = + ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B0] : 1 words$word) + : 64 words$word)) in + let (tmp_310 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let (tmp_310 : DescriptorUpdate) = + ((tmp_310 with<| DescriptorUpdate_AP := T|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_310|>)) in + (desc, result) + else + let ((desc : 64 bits), (result : TLBRecord)) = + (if (((secondstage /\ ((((vec_of_bits [access_vec_dec desc (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + let (desc : 64 bits) = + ((set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 64 words$word)) in + let (tmp_320 : DescriptorUpdate) = (result.TLBRecord_descupdate) in + let (tmp_320 : DescriptorUpdate) = + ((tmp_320 with<| DescriptorUpdate_AP := T|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_descupdate := tmp_320|>)) in + (desc, result) + else (desc, result)) in + (desc, result)) in + (desc, result) + else (desc, result)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M))) (\ (xn : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M))) (\ (pxn : 1 bits) . + let ((pxn : 1 bits), (xn : 1 bits)) = + (if apply_nvnv1_effect then + let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)] : 1 words$word)) in + let (xn : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in + (pxn, xn) + else + let (xn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 54 : int):ii)] : 1 words$word)) in + let (pxn : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)] : 1 words$word)) in + (pxn, xn)) in + let (contiguousbit : 1 bits) = + ((vec_of_bits [access_vec_dec desc (( 52 : int):ii)] : 1 words$word)) in + let (nG : 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 : int):ii)] : 1 words$word)) in + let (sh : 2 bits) = ((slice desc (( 8 : int):ii) (( 2 : int):ii) : 2 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M))) (\ (ap : 3 bits) . + let (ap : 3 bits) = + (if apply_nvnv1_effect then + (concat_vec (vec_of_bits [access_vec_dec desc (( 7 : int):ii)] : 1 words$word) + (vec_of_bits [B0;B1] : 2 words$word) + : 3 words$word) + else + (concat_vec ((slice desc (( 6 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (memattr : 4 bits) = ((slice desc (( 2 : int):ii) (( 4 : int):ii) : 4 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M))) (\ (w__163 : 4 bits) . + let result = ((result with<| TLBRecord_domain := w__163|>)) in + let result = ((result with<| TLBRecord_level := level|>)) in + let result = + ((result with<| + TLBRecord_blocksize := + ((pow2 + (((((((( 3 : int):ii) - ((ex_int level)))) * ((ex_int stride)))) + + + ((ex_int grainsize))))))|>)) in sail2_state_monad$bindS + (if ((~ secondstage)) then + let (tmp_340 : Permissions) = (result.TLBRecord_perms) in + let tmp_340 = + ((tmp_340 with<| Permissions_xn := ((or_vec xn xn_table : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_340|>)) in + let (tmp_350 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_350 = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_350 (( 2 : int):ii) + ((or_vec (vec_of_bits [access_vec_dec ap (( 2 : int):ii)] : 1 words$word) + (vec_of_bits [access_vec_dec ap_table (( 1 : int):ii)] : 1 words$word) + : 1 words$word)) + : 3 words$word)) in + let (tmp_360 : Permissions) = (result.TLBRecord_perms) in + let tmp_360 = ((tmp_360 with<| Permissions_ap := tmp_350|>)) in + let result = ((result with<| TLBRecord_perms := tmp_360|>)) in sail2_state_monad$bindS + (if ((~ singlepriv)) then + let (tmp_370 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_370 = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_370 (( 1 : int):ii) + ((and_vec (vec_of_bits [access_vec_dec ap (( 1 : int):ii)] : 1 words$word) + ((not_vec (vec_of_bits [access_vec_dec ap_table (( 0 : int):ii)] : 1 words$word) + : 1 words$word)) + : 1 words$word)) + : 3 words$word)) in + let (tmp_380 : Permissions) = (result.TLBRecord_perms) in + let tmp_380 = ((tmp_380 with<| Permissions_ap := tmp_370|>)) in + let result = ((result with<| TLBRecord_perms := tmp_380|>)) in + let (tmp_390 : Permissions) = (result.TLBRecord_perms) in + let tmp_390 = + ((tmp_390 with<| Permissions_pxn := ((or_vec pxn pxn_table : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_390|>)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (IsSecure () )) (\ (w__164 : bool) . + let (result : TLBRecord) = + (if w__164 then + (result with<| TLBRecord_nG := ((or_vec nG ns_table : 1 words$word))|>) + else (result with<| TLBRecord_nG := nG|>)) in + sail2_state_monad$returnS result) + else + let (tmp_400 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let (tmp_400 : 3 bits) = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_400 (( 1 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (tmp_410 : Permissions) = (result.TLBRecord_perms) in + let (tmp_410 : Permissions) = ((tmp_410 with<| Permissions_ap := tmp_400|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_perms := tmp_410|>)) in + let (tmp_420 : Permissions) = (result.TLBRecord_perms) in + let (tmp_420 : Permissions) = + ((tmp_420 with<| Permissions_pxn := ((vec_of_bits [B0] : 1 words$word))|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_perms := tmp_420|>)) in + let (result : TLBRecord) = + ((result with<| TLBRecord_nG := ((vec_of_bits [B0] : 1 words$word))|>)) in + sail2_state_monad$returnS result) (\ (result : TLBRecord) . + let (tmp_430 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_430 = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_430 (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (tmp_440 : Permissions) = (result.TLBRecord_perms) in + let tmp_440 = ((tmp_440 with<| Permissions_ap := tmp_430|>)) in + let result = ((result with<| TLBRecord_perms := tmp_440|>)) in + let (tmp_450 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_S1AttrDecode sh ((slice memattr (( 0 : int):ii) (( 3 : int):ii) : 3 words$word)) acctype)) (\ (w__165 : + MemoryAttributes) . + let (tmp_450 : AddressDescriptor) = + ((tmp_450 with<| AddressDescriptor_memattrs := w__165|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_450|>)) in + let (tmp_460 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let (tmp_460 : FullAddress) = + ((tmp_460 with<| + FullAddress_NS := + ((or_vec (vec_of_bits [access_vec_dec memattr (( 3 : int):ii)] : 1 words$word) ns_table + : 1 words$word))|>)) in + let (tmp_470 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_470 : AddressDescriptor) = + ((tmp_470 with<| AddressDescriptor_paddress := tmp_460|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_470|>)) in + sail2_state_monad$returnS result)) + else + let (tmp_480 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_480 = + ((set_slice (( 3 : int):ii) (( 2 : int):ii) tmp_480 (( 1 : int):ii) ((slice ap (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) + : 3 words$word)) in + let (tmp_490 : Permissions) = (result.TLBRecord_perms) in + let tmp_490 = ((tmp_490 with<| Permissions_ap := tmp_480|>)) in + let result = ((result with<| TLBRecord_perms := tmp_490|>)) in + let (tmp_500 : 3 bits) = (result.TLBRecord_perms.Permissions_ap) in + let tmp_500 = + ((set_slice (( 3 : int):ii) (( 1 : int):ii) tmp_500 (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 3 words$word)) in + let (tmp_510 : Permissions) = (result.TLBRecord_perms) in + let tmp_510 = ((tmp_510 with<| Permissions_ap := tmp_500|>)) in + let result = ((result with<| TLBRecord_perms := tmp_510|>)) in + let (tmp_520 : Permissions) = (result.TLBRecord_perms) in + let tmp_520 = ((tmp_520 with<| Permissions_xn := xn|>)) in + let result = ((result with<| TLBRecord_perms := tmp_520|>)) in + let (result : TLBRecord) = + (if ((HaveExtendedExecuteNeverExt () )) then + let (tmp_530 : Permissions) = (result.TLBRecord_perms) in + let (tmp_530 : Permissions) = + ((tmp_530 with<| + Permissions_xxn := ((vec_of_bits [access_vec_dec desc (( 53 : int):ii)] : 1 words$word))|>)) in + (result with<| TLBRecord_perms := tmp_530|>) + else result) in + let (tmp_540 : Permissions) = (result.TLBRecord_perms) in + let tmp_540 = ((tmp_540 with<| Permissions_pxn := ((vec_of_bits [B0] : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_540|>)) in + let result = ((result with<| TLBRecord_nG := ((vec_of_bits [B0] : 1 words$word))|>)) in + let (tmp_550 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (S2AttrDecode sh memattr acctype)) (\ (w__166 : MemoryAttributes) . + let (tmp_550 : AddressDescriptor) = + ((tmp_550 with<| AddressDescriptor_memattrs := w__166|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_550|>)) in + let (tmp_560 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let (tmp_560 : FullAddress) = + ((tmp_560 with<| FullAddress_NS := ((vec_of_bits [B1] : 1 words$word))|>)) in + let (tmp_570 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_570 : AddressDescriptor) = + ((tmp_570 with<| AddressDescriptor_paddress := tmp_560|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_570|>)) in + sail2_state_monad$returnS result)) (\ (result : TLBRecord) . + let (tmp_580 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let tmp_580 = ((tmp_580 with<| FullAddress_physicaladdress := outputaddress|>)) in + let (tmp_590 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_590 = ((tmp_590 with<| AddressDescriptor_paddress := tmp_580|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_590|>)) in + let (tmp_600 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_NoFault () )) (\ (w__167 : FaultRecord) . + let (tmp_600 : AddressDescriptor) = + ((tmp_600 with<| AddressDescriptor_fault := w__167|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_600|>)) in + let (result : TLBRecord) = + ((result with<| + TLBRecord_contiguous := (((contiguousbit = (vec_of_bits [B1] : 1 words$word))))|>)) in + let (result : TLBRecord) = + (if ((HaveCommonNotPrivateTransExt () )) then + (result with<| + TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 : int):ii)] : 1 words$word))|>) + else result) in + sail2_state_monad$returnS result)))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +(*val IsZero_slice2 : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) + +val _ = Define ` + ((IsZero_slice2:'n words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) xs i l= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$returnS ((IsZero ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)))))))`; + + +(*val AArch64_TranslateAddressS1Off : mword ty64 -> AccType -> bool -> M TLBRecord*) + +val _ = Define ` + ((AArch64_TranslateAddressS1Off:(64)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((TLBRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "") + (undefined_TLBRecord () )) (\ (result : TLBRecord) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$bindS + (AddrTop vaddress F w__2.ProcState_EL) (\ (Top : ii) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (level : ii) . sail2_state_monad$bindS + (IsZero_slice2 vaddress ((PAMax () )) + ((((((ex_int Top)) + (( 1 : int):ii))) - ((ex_int ((PAMax () ))))))) (\ (w__3 : + bool) . + if ((~ w__3)) then + let level = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (w__4 : 52 bits) . + let ipaddress = w__4 in + let secondstage = F in + let s2fs1walk = F in + let (tmp_1980 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk) (\ (w__5 : + FaultRecord) . + let (tmp_1980 : AddressDescriptor) = ((tmp_1980 with<| AddressDescriptor_fault := w__5|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_1980|>)) in + sail2_state_monad$returnS result)) + else sail2_state_monad$bindS + (sail2_state$and_boolS ((HasS2Translation () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 12 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (default_cacheable : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (cacheable : bool) . sail2_state_monad$bindS + (if default_cacheable then + let (tmp_1990 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_1990 : MemoryAttributes) = + ((tmp_1990 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let (tmp_2000 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2000 : AddressDescriptor) = + ((tmp_2000 with<| AddressDescriptor_memattrs := tmp_1990|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2000|>)) in + let (tmp_2010 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2010 : MemAttrHints) = ((tmp_2010 with<| MemAttrHints_attrs := MemAttr_WB|>)) in + let (tmp_2020 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2020 : MemoryAttributes) = ((tmp_2020 with<| MemoryAttributes_inner := tmp_2010|>)) in + let (tmp_2030 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2030 : AddressDescriptor) = + ((tmp_2030 with<| AddressDescriptor_memattrs := tmp_2020|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2030|>)) in + let (tmp_2040 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2040 : MemAttrHints) = ((tmp_2040 with<| MemAttrHints_hints := MemHint_RWA|>)) in + let (tmp_2050 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2050 : MemoryAttributes) = ((tmp_2050 with<| MemoryAttributes_inner := tmp_2040|>)) in + let (tmp_2060 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2060 : AddressDescriptor) = + ((tmp_2060 with<| AddressDescriptor_memattrs := tmp_2050|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2060|>)) in + let (tmp_2070 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2070 : MemoryAttributes) = ((tmp_2070 with<| MemoryAttributes_shareable := F|>)) in + let (tmp_2080 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2080 : AddressDescriptor) = + ((tmp_2080 with<| AddressDescriptor_memattrs := tmp_2070|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2080|>)) in + let (tmp_2090 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2090 : MemoryAttributes) = + ((tmp_2090 with<| MemoryAttributes_outershareable := F|>)) in + let (tmp_2100 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2100 : AddressDescriptor) = + ((tmp_2100 with<| AddressDescriptor_memattrs := tmp_2090|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2100|>)) in + sail2_state_monad$returnS result + else if (((acctype <> AccType_IFETCH))) then + let (tmp_2110 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let tmp_2110 = ((tmp_2110 with<| MemoryAttributes_typ := MemType_Device|>)) in + let (tmp_2120 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_2120 = ((tmp_2120 with<| AddressDescriptor_memattrs := tmp_2110|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2120|>)) in + let (tmp_2130 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let tmp_2130 = ((tmp_2130 with<| MemoryAttributes_device := DeviceType_nGnRnE|>)) in + let (tmp_2140 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_2140 = ((tmp_2140 with<| AddressDescriptor_memattrs := tmp_2130|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2140|>)) in + let (tmp_2150 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in sail2_state_monad$bindS + (undefined_MemAttrHints () ) (\ (w__8 : MemAttrHints) . + let (tmp_2150 : MemoryAttributes) = ((tmp_2150 with<| MemoryAttributes_inner := w__8|>)) in + let (tmp_2160 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2160 : AddressDescriptor) = + ((tmp_2160 with<| AddressDescriptor_memattrs := tmp_2150|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2160|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__9 : 32 words$word) . + let (cacheable : bool) = + ((vec_of_bits [access_vec_dec w__9 (( 12 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (tmp_2170 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2170 : MemoryAttributes) = + ((tmp_2170 with<| MemoryAttributes_typ := MemType_Normal|>)) in + let (tmp_2180 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2180 : AddressDescriptor) = + ((tmp_2180 with<| AddressDescriptor_memattrs := tmp_2170|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2180|>)) in + let (result : TLBRecord) = + (if cacheable then + let (tmp_2190 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2190 : MemAttrHints) = ((tmp_2190 with<| MemAttrHints_attrs := MemAttr_WT|>)) in + let (tmp_2200 : MemoryAttributes) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2200 : MemoryAttributes) = + ((tmp_2200 with<| MemoryAttributes_inner := tmp_2190|>)) in + let (tmp_2210 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2210 : AddressDescriptor) = + ((tmp_2210 with<| AddressDescriptor_memattrs := tmp_2200|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2210|>)) in + let (tmp_2220 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2220 : MemAttrHints) = ((tmp_2220 with<| MemAttrHints_hints := MemHint_RA|>)) in + let (tmp_2230 : MemoryAttributes) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2230 : MemoryAttributes) = + ((tmp_2230 with<| MemoryAttributes_inner := tmp_2220|>)) in + let (tmp_2240 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2240 : AddressDescriptor) = + ((tmp_2240 with<| AddressDescriptor_memattrs := tmp_2230|>)) in + (result with<| TLBRecord_addrdesc := tmp_2240|>) + else + let (tmp_2250 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2250 : MemAttrHints) = ((tmp_2250 with<| MemAttrHints_attrs := MemAttr_NC|>)) in + let (tmp_2260 : MemoryAttributes) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2260 : MemoryAttributes) = + ((tmp_2260 with<| MemoryAttributes_inner := tmp_2250|>)) in + let (tmp_2270 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2270 : AddressDescriptor) = + ((tmp_2270 with<| AddressDescriptor_memattrs := tmp_2260|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2270|>)) in + let (tmp_2280 : MemAttrHints) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner) in + let (tmp_2280 : MemAttrHints) = ((tmp_2280 with<| MemAttrHints_hints := MemHint_No|>)) in + let (tmp_2290 : MemoryAttributes) = + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2290 : MemoryAttributes) = + ((tmp_2290 with<| MemoryAttributes_inner := tmp_2280|>)) in + let (tmp_2300 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2300 : AddressDescriptor) = + ((tmp_2300 with<| AddressDescriptor_memattrs := tmp_2290|>)) in + (result with<| TLBRecord_addrdesc := tmp_2300|>)) in + let (tmp_2310 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2310 : MemoryAttributes) = ((tmp_2310 with<| MemoryAttributes_shareable := T|>)) in + let (tmp_2320 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2320 : AddressDescriptor) = + ((tmp_2320 with<| AddressDescriptor_memattrs := tmp_2310|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2320|>)) in + let (tmp_2330 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let (tmp_2330 : MemoryAttributes) = + ((tmp_2330 with<| MemoryAttributes_outershareable := T|>)) in + let (tmp_2340 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let (tmp_2340 : AddressDescriptor) = + ((tmp_2340 with<| AddressDescriptor_memattrs := tmp_2330|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2340|>)) in + sail2_state_monad$returnS result)) (\ (result : TLBRecord) . + let (tmp_2350 : MemoryAttributes) = (result.TLBRecord_addrdesc.AddressDescriptor_memattrs) in + let tmp_2350 = + ((tmp_2350 with<| + MemoryAttributes_outer := + (result.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_inner)|>)) in + let (tmp_2360 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_2360 = ((tmp_2360 with<| AddressDescriptor_memattrs := tmp_2350|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2360|>)) in + let (tmp_2370 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (MemAttrDefaults result.TLBRecord_addrdesc.AddressDescriptor_memattrs) (\ (w__10 : + MemoryAttributes) . + let tmp_2370 = ((tmp_2370 with<| AddressDescriptor_memattrs := w__10|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2370|>)) in + let (tmp_2380 : Permissions) = (result.TLBRecord_perms) in sail2_state_monad$bindS + (undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M) (\ (w__11 : 3 bits) . + let tmp_2380 = ((tmp_2380 with<| Permissions_ap := w__11|>)) in + let result = ((result with<| TLBRecord_perms := tmp_2380|>)) in + let (tmp_2390 : Permissions) = (result.TLBRecord_perms) in + let tmp_2390 = ((tmp_2390 with<| Permissions_xn := ((vec_of_bits [B0] : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_2390|>)) in + let (tmp_2400 : Permissions) = (result.TLBRecord_perms) in + let tmp_2400 = ((tmp_2400 with<| Permissions_pxn := ((vec_of_bits [B0] : 1 words$word))|>)) in + let result = ((result with<| TLBRecord_perms := tmp_2400|>)) in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__12 : 1 bits) . + let result = ((result with<| TLBRecord_nG := w__12|>)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__13 : bool) . + let result = ((result with<| TLBRecord_contiguous := w__13|>)) in sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (w__14 : 4 bits) . + let result = ((result with<| TLBRecord_domain := w__14|>)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__15 : ii) . + let result = ((result with<| TLBRecord_level := w__15|>)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__16 : ii) . + let result = ((result with<| TLBRecord_blocksize := w__16|>)) in + let (tmp_2410 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in + let tmp_2410 = + ((tmp_2410 with<| + FullAddress_physicaladdress := ((slice vaddress (( 0 : int):ii) (( 52 : int):ii) : 52 words$word))|>)) in + let (tmp_2420 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_2420 = ((tmp_2420 with<| AddressDescriptor_paddress := tmp_2410|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2420|>)) in + let (tmp_2430 : FullAddress) = (result.TLBRecord_addrdesc.AddressDescriptor_paddress) in sail2_state_monad$bindS + (IsSecure () ) (\ (w__17 : bool) . + let tmp_2430 = + ((tmp_2430 with<| + FullAddress_NS := + (if w__17 then (vec_of_bits [B0] : 1 words$word) + else (vec_of_bits [B1] : 1 words$word))|>)) in + let (tmp_2440 : AddressDescriptor) = (result.TLBRecord_addrdesc) in + let tmp_2440 = ((tmp_2440 with<| AddressDescriptor_paddress := tmp_2430|>)) in + let result = ((result with<| TLBRecord_addrdesc := tmp_2440|>)) in + let (tmp_2450 : AddressDescriptor) = (result.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_NoFault () ) (\ (w__18 : FaultRecord) . + let (tmp_2450 : AddressDescriptor) = ((tmp_2450 with<| AddressDescriptor_fault := w__18|>)) in + let (result : TLBRecord) = ((result with<| TLBRecord_addrdesc := tmp_2450|>)) in + sail2_state_monad$returnS result))))))))))))))))))))))))`; + + +(*val AArch64_MaybeZeroRegisterUppers : unit -> M unit*) + +val _ = Define ` + ((AArch64_MaybeZeroRegisterUppers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__0 "UsingAArch32()") + (sail2_state_monad$undefined_boolS () )) (\ (include_R15_name : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (last : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (first : ii) . sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) . sail2_state_monad$bindS + (if w__3 then + let (first : ii) = ((( 0 : int):ii)) in + let (last : ii) = ((( 14 : int):ii)) in + let (include_R15_name : bool) = F in + sail2_state_monad$returnS (first, include_R15_name, last) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_EL = EL1)))))) (sail2_state_monad$returnS ((HaveEL EL2)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__8 : bool) . sail2_state_monad$returnS ((~ w__8))))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__10 : bool) . sail2_state_monad$returnS ((~ w__10))))) (\ (w__11 : bool) . + let ((first : ii), (include_R15_name : bool), (last : ii)) = + (if w__11 then + let (first : ii) = ((( 0 : int):ii)) in + let (last : ii) = ((( 30 : int):ii)) in + let (include_R15_name : bool) = F in + (first, include_R15_name, last) + else + let (first : ii) = ((( 0 : int):ii)) in + let (last : ii) = ((( 30 : int):ii)) in + let (include_R15_name : bool) = T in + (first, include_R15_name, last)) in + sail2_state_monad$returnS (first, include_R15_name, last))) (\ varstup . let ((first : ii), (include_R15_name : + bool), (last : ii)) = varstup in + (sail2_state$foreachS (index_list first last (( 1 : int):ii)) () + (\ n unit_var . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((n <> (( 15 : int):ii)))) \/ include_R15_name)))) + ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER))) (\ (w__13 : bool) . + if w__13 then sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__14 : ( 64 bits) list) . + let (tmp_30 : 64 bits) = ((access_list_dec w__14 n : 64 words$word)) in + let tmp_30 = + ((set_slice (( 64 : int):ii) (( 32 : int):ii) tmp_30 (( 32 : int):ii) ((Zeros__1 (( 32 : int):ii) () : 32 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS R_ref) (\ (w__15 : ( 64 words$word) list) . + sail2_state_monad$write_regS R_ref ((update_list_dec w__15 n tmp_30 : ( 64 words$word) list)))) + else sail2_state_monad$returnS () )))))))))))`; + + +(*val DCPSInstruction : mword ty2 -> M unit*) + +val _ = Define ` + ((DCPSInstruction:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el= + (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (handle_el : 2 bits) . + let pat_0 = target_el in sail2_state_monad$bindS + (if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL2))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + sail2_state_monad$returnS (((w__1.ProcState_EL = EL3))))) + ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . + if w__4 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + let (handle_el : 2 bits) = (w__5.ProcState_EL) in + sail2_state_monad$returnS handle_el) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__6 : bool) . sail2_state_monad$returnS ((~ w__6))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__9 : bool) . + if w__9 then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el) + else sail2_state_monad$returnS EL1)) + else if (((pat_0 = EL2))) then + if ((~ ((HaveEL EL2)))) then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el) + else sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + sail2_state_monad$returnS (((w__10.ProcState_EL = EL3))))) + ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__11 : bool) . sail2_state_monad$returnS ((~ w__11))))) (\ (w__12 : bool) . + if w__12 then sail2_state_monad$returnS EL3 + else sail2_state_monad$bindS + (IsSecure () ) (\ (w__13 : bool) . + if w__13 then sail2_state_monad$seqS (UndefinedFault () ) (sail2_state_monad$returnS handle_el) + else sail2_state_monad$returnS EL2)) + else if (((pat_0 = EL3))) then sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS EDSCR_ref : ( 32 words$word) M) (\ (w__14 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 16 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) (sail2_state_monad$returnS ((~ ((HaveEL EL3)))))) (\ (w__15 : + bool) . sail2_state_monad$seqS + (if w__15 then UndefinedFault () else sail2_state_monad$returnS () ) (sail2_state_monad$returnS EL3)) + else sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS handle_el)) (\ (handle_el : 2 bits) . sail2_state_monad$bindS + (IsSecure () ) (\ (from_secure : bool) . sail2_state_monad$bindS + (ELUsingAArch32 handle_el) (\ (w__16 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if w__16 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__17.ProcState_M = M32_Monitor))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . + sail2_state_monad$write_regS + SCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__18 (( 0 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) + else sail2_state_monad$returnS () ) + (UsingAArch32 () )) (\ (w__19 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__19 "UsingAArch32()") + (let pat_0 = handle_el in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((pat_0 = EL1))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (AArch32_WriteMode M32_Svc) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__21 : bool) . + if w__21 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_PAN := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + else if (((pat_0 = EL2))) then AArch32_WriteMode M32_Hyp + else sail2_state_monad$seqS + (AArch32_WriteMode M32_Monitor) + (if ((HavePANExt () )) then + if ((~ from_secure)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__23 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_PAN := ((vec_of_bits [B0] : 1 words$word))|>)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__24 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__24 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__25 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_PAN := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + else sail2_state_monad$returnS () )) + (if (((handle_el = EL2))) then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__26 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_hyp_ref w__26) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__27 : 32 bits) . + sail2_state_monad$write_regS HSR_ref w__27)) + else sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__28 : 32 words$word) . + set_LR w__28))) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__29 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_SPSR w__29) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) . sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__31 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__30 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__31 (( 25 : int):ii)] : 1 words$word))|>)) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__32 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_ref w__32) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__33 : 32 bits) . + sail2_state_monad$write_regS DSPSR_ref w__33)))))))) + else sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__34 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__34 then AArch64_MaybeZeroRegisterUppers () + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__35 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__35 with<| ProcState_nRW := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__36 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__36 with<| ProcState_SP := ((vec_of_bits [B1] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__37 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__37 with<| ProcState_EL := handle_el|>)) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () ))) + (sail2_state$or_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((handle_el = EL1)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__38 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((handle_el = EL2)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__40 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__40 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__42 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__44 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__44 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))))) (\ (w__47 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__47 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__48 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__48 with<| ProcState_PAN := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__49 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_ELR__1 w__49) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__50 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_SPSR w__50) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__51 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_ESR__1 w__51) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__52 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_EL0_ref w__52) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__53 : 32 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS DSPSR_EL0_ref w__53) + (if ((HaveUAOExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__54 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__54 with<| ProcState_UAO := ((vec_of_bits [B0] : 1 words$word))|>)) + else sail2_state_monad$returnS () )))))))))))) + (UpdateEDSCRFields () )) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__55 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__55 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ((ConstrainUnpredictableBool Unpredictable_IESBinDebug)))) (\ (w__58 : bool) . + let (_ : unit) = + (if w__58 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All + else () ) in + sail2_state_monad$returnS () )))))))`; + + +(*val aarch64_system_exceptions_debug_exception : mword ty2 -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_debug_exception:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_level= (DCPSInstruction target_level))`; + + +(*val AArch64_GenerateDebugExceptionsFrom : mword ty2 -> bool -> mword ty1 -> M bool*) + +val _ = Define ` + ((AArch64_GenerateDebugExceptionsFrom:(2)words$word -> bool ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) from secure mask= (sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS OSLSR_EL1_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) ((DoubleLockStatus () ))) ((Halted () ))) (\ (w__4 : + bool) . + if w__4 then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ ((~ secure)))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (route_to_el2 : bool) . + let (target : 2 bits) = (if route_to_el2 then EL2 else EL1) in sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS (((((~ ((HaveEL EL3)))) \/ ((~ secure)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL3_ref : ( 32 words$word) M) (\ (w__8 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 16 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (enabled : bool) . + if (((from = target))) then + sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS enabled) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__9 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 13 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + (sail2_state_monad$returnS (((mask = (vec_of_bits [B0] : 1 words$word))))) + else + let (enabled : bool) = (enabled /\ ((((lem$w2ui target)) > ((lem$w2ui from))))) in + sail2_state_monad$returnS enabled)))))`; + + +(*val AArch64_GenerateDebugExceptions : unit -> M bool*) + +val _ = Define ` + ((AArch64_GenerateDebugExceptions:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + AArch64_GenerateDebugExceptionsFrom w__0.ProcState_EL w__1 w__2.ProcState_D)))))`; + + +(*val AArch64_FaultSyndrome : bool -> FaultRecord -> M (mword ty25)*) + +val _ = Define ` + ((AArch64_FaultSyndrome:bool -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->((((25)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d_side fault= (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((fault.FaultRecord_typ <> Fault_None))) "((fault).type != Fault_None)") + (let (iss : 25 bits) = ((Zeros__1 (( 25 : int):ii) () : 25 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) ((IsExternalSyncAbort__1 fault))) (\ (w__1 : bool) . + let (iss : 25 bits) = + (if w__1 then (set_slice (( 25 : int):ii) (( 2 : int):ii) iss (( 11 : int):ii) fault.FaultRecord_errortype : 25 words$word) + else iss) in sail2_state_monad$bindS + (if d_side then sail2_state_monad$bindS + (sail2_state$and_boolS ((IsSecondStage fault)) (sail2_state_monad$returnS ((~ fault.FaultRecord_s2fs1walk)))) (\ (w__3 : + bool) . sail2_state_monad$bindS + (if w__3 then sail2_state_monad$bindS + (LSInstructionSyndrome () : ( 11 words$word) M) (\ (w__4 : 11 words$word) . + let (iss : 25 bits) = ((set_slice (( 25 : int):ii) (( 11 : int):ii) iss (( 14 : int):ii) w__4 : 25 words$word)) in + sail2_state_monad$returnS iss) + else sail2_state_monad$returnS iss) (\ (iss : 25 bits) . + let (iss : 25 bits) = + (if ((((((fault.FaultRecord_acctype = AccType_DC))) \/ ((((((fault.FaultRecord_acctype = AccType_IC))) \/ (((fault.FaultRecord_acctype = AccType_AT))))))))) then + let (iss : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 8 : int):ii) (vec_of_bits [B1] : 1 words$word) : 25 words$word)) in + (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 6 : int):ii) (vec_of_bits [B1] : 1 words$word) : 25 words$word) + else + (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 6 : int):ii) + (if fault.FaultRecord_write then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 25 words$word)) in + sail2_state_monad$returnS iss)) + else sail2_state_monad$returnS iss) (\ (iss : 25 bits) . sail2_state_monad$bindS + (IsExternalAbort__1 fault) (\ (w__5 : bool) . + let (iss : 25 bits) = + (if w__5 then (set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 9 : int):ii) fault.FaultRecord_extflag : 25 words$word) + else iss) in + let iss = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) iss (( 7 : int):ii) + (if fault.FaultRecord_s2fs1walk then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 25 words$word)) in sail2_state_monad$bindS + (EncodeLDFSC fault.FaultRecord_typ fault.FaultRecord_level : ( 6 words$word) M) (\ (w__6 : + 6 words$word) . + let (iss : 25 bits) = ((set_slice (( 25 : int):ii) (( 6 : int):ii) iss (( 0 : int):ii) w__6 : 25 words$word)) in + sail2_state_monad$returnS iss)))))))`; + + +(*val AArch64_AbortSyndrome : Exception -> FaultRecord -> mword ty64 -> M ExceptionRecord*) + +val _ = Define ` + ((AArch64_AbortSyndrome:Exception -> FaultRecord ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((ExceptionRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ fault vaddress= (sail2_state_monad$bindS + (ExceptionSyndrome typ) (\ (exception : ExceptionRecord) . + let (d_side : bool) = ((((typ = Exception_DataAbort))) \/ (((typ = Exception_Watchpoint)))) in sail2_state_monad$bindS + (AArch64_FaultSyndrome d_side fault : ( 25 words$word) M) (\ (w__0 : 25 bits) . + let exception = ((exception with<| ExceptionRecord_syndrome := w__0|>)) in sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) vaddress : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let exception = ((exception with<| ExceptionRecord_vaddress := w__1|>)) in sail2_state_monad$bindS + (IPAValid fault) (\ (w__2 : bool) . + let (exception : ExceptionRecord) = + (if w__2 then + let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_ipavalid := T|>)) in + (exception with<| ExceptionRecord_ipaddress := (fault.FaultRecord_ipaddress)|>) + else (exception with<| ExceptionRecord_ipavalid := F|>)) in + sail2_state_monad$returnS exception))))))`; + + +(*val AArch64_ExecutingATS1xPInstr : unit -> M bool*) + +val _ = Define ` + ((AArch64_ExecutingATS1xPInstr:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (if ((~ ((HavePrivATExt () )))) then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (ThisInstr0 () : ( 32 words$word) M) (\ (instr : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M) (\ (op2 : 3 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (CRm : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M) (\ (CRn : 4 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 3 : int):ii) : ( 3 words$word) M) (\ (op1 : 3 bits) . + let (w__0 : bool) = + (if (((((slice instr (( 22 : int):ii) (( 10 : int):ii) : 10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0] : 10 words$word)))) then + let (op1 : 3 bits) = ((slice instr (( 16 : int):ii) (( 3 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((slice instr (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((slice instr (( 8 : int):ii) (( 4 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((slice instr (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in + ((((((((((op1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((CRn = (vec_of_bits [B0;B1;B1;B1] : 4 words$word))))))) /\ (((CRm = (vec_of_bits [B1;B0;B0;B1] : 4 words$word))))))) /\ ((((((op2 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) \/ (((op2 = (vec_of_bits [B0;B0;B1] : 3 words$word)))))))) + else F) in + sail2_state_monad$returnS w__0)))))))`; + + +(*val AArch64_ExceptionClass : Exception -> mword ty2 -> M (ii * mword ty1)*) + +val _ = Define ` + ((AArch64_ExceptionClass:Exception ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((int#(1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ target_el= (sail2_state_monad$bindS + (ThisInstrLength () ) (\ (w__0 : ii) . + let (il : 1 bits) = + (if (((((ex_int w__0)) = (( 32 : int):ii)))) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (UsingAArch32 () ) (\ (from_32 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((from_32 \/ (((il = (vec_of_bits [B1] : 1 words$word))))))) "(from_32 || (il == '1'))") + (undefined_int () )) (\ (ec : ii) . sail2_state_monad$bindS + (case typ of + Exception_Uncategorized => + let (ec : ii) = ((( 0 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_WFxTrap => + let (ec : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP15RTTrap => + let ec = ((( 3 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | Exception_CP15RRTTrap => + let ec = ((( 4 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | Exception_CP14RTTrap => + let ec = ((( 5 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | Exception_CP14DTTrap => + let ec = ((( 6 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | Exception_AdvSIMDFPAccessTrap => + let (ec : ii) = ((( 7 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_FPIDTrap => + let (ec : ii) = ((( 8 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_CP14RRTTrap => + let ec = ((( 12 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | Exception_IllegalState => + let (ec : ii) = ((( 14 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_SupervisorCall => + let (ec : ii) = ((( 17 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_HypervisorCall => + let (ec : ii) = ((( 18 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_MonitorCall => + let (ec : ii) = ((( 19 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_SystemRegisterTrap => + let ec = ((( 24 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ from_32)) "!(from_32)") (sail2_state_monad$returnS (ec, il)) + | Exception_InstructionAbort => + let (ec : ii) = ((( 32 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_PCAlignment => + let (ec : ii) = ((( 34 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_DataAbort => + let (ec : ii) = ((( 36 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_SPAlignment => + let ec = ((( 38 : int):ii)) in + let il = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ from_32)) "!(from_32)") (sail2_state_monad$returnS (ec, il)) + | Exception_FPTrappedException => + let (ec : ii) = ((( 40 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_SError => + let (ec : ii) = ((( 47 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_Breakpoint => + let (ec : ii) = ((( 48 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_SoftwareStep => + let (ec : ii) = ((( 50 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_Watchpoint => + let (ec : ii) = ((( 52 : int):ii)) in + let (il : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS (ec, il) + | Exception_SoftwareBreakpoint => + let (ec : ii) = ((( 56 : int):ii)) in + sail2_state_monad$returnS (ec, il) + | Exception_VectorCatch => + let ec = ((( 58 : int):ii)) in + let il = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS from_32 "from_32") (sail2_state_monad$returnS (ec, il)) + | _ => sail2_state_monad$seqS (Unreachable () ) (sail2_state_monad$returnS (ec, il)) + ) (\ varstup . let ((ec : ii), (il : 1 bits)) = varstup in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS ((((((((ex_int ec)) = (( 32 : int):ii)))) \/ ((((((((ex_int ec)) = (( 36 : int):ii)))) \/ ((((((((ex_int ec)) = (( 48 : int):ii)))) \/ ((((((((ex_int ec)) = (( 50 : int):ii)))) \/ (((((ex_int ec)) = (( 52 : int):ii))))))))))))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + sail2_state_monad$returnS (((target_el = w__1.ProcState_EL)))))) (\ (w__2 : bool) . + let (ec : ii) = (if w__2 then ((ex_int ec)) + (( 1 : int):ii) else ec) in + let (ec : ii) = + (if (((((((((((ex_int ec)) = (( 17 : int):ii)))) \/ ((((((((ex_int ec)) = (( 18 : int):ii)))) \/ ((((((((ex_int ec)) = (( 19 : int):ii)))) \/ ((((((((ex_int ec)) = (( 40 : int):ii)))) \/ (((((ex_int ec)) = (( 56 : int):ii)))))))))))))))) /\ ((~ from_32))))) then + ((ex_int ec)) + (( 4 : int):ii) + else ec) in + sail2_state_monad$returnS (ec, il))))))))`; + + +(*val AArch64_ReportException : ExceptionRecord -> mword ty2 -> M unit*) + +val _ = Define ` + ((AArch64_ReportException:ExceptionRecord ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception target_el= + (let (typ : Exception) = (exception.ExceptionRecord_typ) in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (il : 1 bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (ec : ii) . sail2_state_monad$bindS + (AArch64_ExceptionClass typ target_el : ((ii # 1 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let ec = tup__0 in + let il = tup__1 in + let (iss : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (il : 1 bits) = + (if (((((((((((ex_int ec)) = (( 36 : int):ii)))) \/ (((((ex_int ec)) = (( 37 : int):ii))))))) /\ ((((vec_of_bits [access_vec_dec iss (( 24 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + (vec_of_bits [B1] : 1 words$word) + else il) in sail2_state_monad$seqS (sail2_state_monad$seqS + (aset_ESR__0 target_el + ((concat_vec + ((concat_vec + ((GetSlice_int ((make_the_value (( 6 : int):ii) : 6 itself)) ec (( 0 : int):ii) : 6 words$word)) il + : 7 words$word)) iss + : 32 words$word))) + (if ((((((typ = Exception_InstructionAbort))) \/ ((((((typ = Exception_PCAlignment))) \/ ((((((typ = Exception_DataAbort))) \/ (((typ = Exception_Watchpoint)))))))))))) then + aset_FAR__0 target_el exception.ExceptionRecord_vaddress + else sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + aset_FAR__0 target_el w__0))) + (if (((target_el = EL2))) then + if exception.ExceptionRecord_ipavalid then sail2_state_monad$bindS + (sail2_state_monad$read_regS HPFAR_EL2_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + sail2_state_monad$write_regS + HPFAR_EL2_ref + ((set_slice (( 64 : int):ii) (( 40 : int):ii) w__1 (( 4 : int):ii) + ((slice exception.ExceptionRecord_ipaddress (( 12 : int):ii) (( 40 : int):ii) : 40 words$word)) + : 64 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HPFAR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS + (undefined_bitvector (( 40 : int):ii) : ( 40 words$word) M) (\ (w__3 : 40 words$word) . + sail2_state_monad$write_regS HPFAR_EL2_ref ((set_slice (( 64 : int):ii) (( 40 : int):ii) w__2 (( 4 : int):ii) w__3 : 64 words$word)))) + else sail2_state_monad$returnS () ))))))`; + + +(*val AArch64_ESBOperation : unit -> M unit*) + +val _ = Define ` + ((AArch64_ESBOperation:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_el3 : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (route_to_el2 : bool) . + let (target : 2 bits) = (if route_to_el3 then EL3 else if route_to_el2 then EL2 else EL1) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (mask_active : bool) . sail2_state_monad$bindS + (if (((target = EL1))) then + sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . sail2_state_monad$returnS (((w__6.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . sail2_state_monad$returnS (((w__7.ProcState_EL = EL1))))) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveVirtHostExt () )) /\ (((target = EL2))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__10 : 64 bits) . + sail2_state_monad$returnS ((((access_vec_dec w__9 (( 34 : int):ii), access_vec_dec w__10 (( 27 : int):ii)) = (B1, B1)))))))) (\ (w__11 : + bool) . + if w__11 then + sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . + sail2_state_monad$returnS (((w__12.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . + sail2_state_monad$returnS (((w__13.ProcState_EL = EL2))))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . + let (mask_active : bool) = (w__15.ProcState_EL = target) in + sail2_state_monad$returnS mask_active))) (\ (mask_active : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . + let (mask_set : bool) = (w__16.ProcState_A = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$or_boolS ((Halted () )) ((ExternalDebugInterruptsDisabled target))) (\ (intdis : bool) . sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . + sail2_state_monad$returnS ((((lem$w2ui target)) < ((lem$w2ui w__19.ProcState_EL)))))) (sail2_state_monad$returnS intdis)) + (sail2_state_monad$returnS (((mask_active /\ mask_set))))) (\ (masked : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (DISR_EL1 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 25 : int):ii) : ( 25 words$word) M) (\ (syndrome64 : 25 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (implicit_esb : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (DISR : 32 bits) . sail2_state_monad$bindS + (undefined_AArch32_SErrorSyndrome () ) (\ (syndrome32 : AArch32_SErrorSyndrome) . sail2_state_monad$bindS + (sail2_state$and_boolS ((SErrorPending () )) (sail2_state_monad$returnS masked)) (\ (w__22 : bool) . + if w__22 then sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__23 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__23) (\ (w__24 : bool) . sail2_state_monad$seqS + (if w__24 then sail2_state_monad$bindS + (AArch32_PhysicalSErrorSyndrome () ) (\ (w__25 : AArch32_SErrorSyndrome) . + let syndrome32 = w__25 in sail2_state_monad$bindS + (AArch32_ReportDeferredSError syndrome32.AArch32_SErrorSyndrome_AET + syndrome32.AArch32_SErrorSyndrome_ExT + : ( 32 words$word) M) (\ (w__26 : 32 bits) . + let (DISR : 32 bits) = w__26 in + sail2_state_monad$returnS () )) + else + let implicit_esb = F in sail2_state_monad$bindS + (AArch64_PhysicalSErrorSyndrome implicit_esb : ( 25 words$word) M) (\ (w__27 : 25 bits) . + let syndrome64 = w__27 in sail2_state_monad$bindS + (AArch64_ReportDeferredSError syndrome64 : ( 64 words$word) M) (\ (w__28 : 64 bits) . + let (DISR_EL1 : 64 bits) = w__28 in + sail2_state_monad$returnS () ))) + (ClearPendingPhysicalSError () ))) + else sail2_state_monad$returnS () )))))))))))))))`; + + +val _ = Define ` + ((AArch64_CheckAndUpdateDescriptor:DescriptorUpdate -> FaultRecord -> bool ->(64)words$word -> AccType -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) result fault secondstage vaddress acctype iswrite s2fs1walk hwupdatewalk__arg= + (sail2_state_monad$catch_early_returnS + ( sail2_state_monad$bindS(sail2_state_monad$liftRS ((aget_SCTLR__1 () : ( 32 words$word) M))) (\ (w__0 : 32 words$word) . + let reversedescriptors = (((access_vec_dec w__0 (( 25 : int):ii))) = B1) in + let hwupdatewalk = hwupdatewalk__arg in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hw_update_AF : bool) . + let (hw_update_AF : bool) = + (if result.DescriptorUpdate_AF then + if (((fault.FaultRecord_typ = Fault_None))) then T + else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then T + else F + else F) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (hw_update_AP : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (write_perm_req : bool) . + let (hw_update_AP : bool) = + (if (((result.DescriptorUpdate_AP /\ (((fault.FaultRecord_typ = Fault_None)))))) then + let (write_perm_req : bool) = + ((((iswrite \/ ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW))))))))) /\ ((~ s2fs1walk))) in + ((((write_perm_req /\ ((~ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_DC))))))))))) \/ hwupdatewalk) + else F) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (desc : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AccessDescriptor () )) (\ (accdesc : AccessDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_AddressDescriptor () )) (\ (descaddr2 : AddressDescriptor) . sail2_state_monad$seqS + (if (((hw_update_AF \/ hw_update_AP))) then sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS secondstage) + ( sail2_state_monad$bindS(sail2_state_monad$liftRS (HasS2Translation () )) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : + bool) . sail2_state_monad$bindS + (if w__2 then + let (descaddr2 : AddressDescriptor) = (result.DescriptorUpdate_descaddr) in + sail2_state_monad$returnS descaddr2 + else + let hwupdatewalk = T in sail2_state_monad$bindS + (sail2_state_monad$liftRS (AArch64_SecondStageWalk result.DescriptorUpdate_descaddr vaddress acctype iswrite + (( 8 : int):ii) hwupdatewalk)) (\ (w__3 : AddressDescriptor) . + let descaddr2 = w__3 in sail2_state_monad$seqS + (if ((IsFault descaddr2)) then + (sail2_state_monad$early_returnS descaddr2.AddressDescriptor_fault : (unit, FaultRecord) MR) + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS descaddr2))) (\ (descaddr2 : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (CreateAccessDescriptor AccType_ATOMICRW)) (\ (w__4 : AccessDescriptor) . + let accdesc = w__4 in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((aget__Mem descaddr2 (( 8 : int):ii) accdesc : ( 64 words$word) M))) (\ (w__5 : 64 bits) . + let desc = w__5 in sail2_state_monad$bindS + (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc : ( 64 words$word) M)) + else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . + let (desc : 64 bits) = + (if hw_update_AF then + (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 10 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word) + else desc) in + let (desc : 64 bits) = + (if hw_update_AP then + (set_slice (( 64 : int):ii) (( 1 : int):ii) desc (( 7 : int):ii) + (if secondstage then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word) + else desc) in sail2_state_monad$bindS + (if reversedescriptors then sail2_state_monad$liftRS ((BigEndianReverse desc : ( 64 words$word) M)) + else sail2_state_monad$returnS desc) (\ (desc : 64 bits) . + sail2_state_monad$liftRS (aset__Mem descaddr2 (( 8 : int):ii) accdesc desc))))))) + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS fault)))))))))))`; + + +(*val AArch64_BreakpointValueMatch : ii -> mword ty64 -> bool -> bool*) + +val _ = Define ` + ((AArch64_BreakpointValueMatch:int ->(64)words$word -> bool -> bool) n__arg vaddress linked_to= F)`; + + +(*val AArch64_StateMatch : mword ty2 -> mword ty1 -> mword ty2 -> bool -> mword ty4 -> bool -> bool -> M bool*) + +val _ = Define ` + ((AArch64_StateMatch:(2)words$word ->(1)words$word ->(2)words$word -> bool ->(4)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) SSC__arg HMC__arg PxC__arg linked__arg LBN isbreakpnt ispriv= + (sail2_state_monad$catch_early_returnS + (let HMC = HMC__arg in + let PxC = PxC__arg in + let SSC = SSC__arg in + let linked = linked__arg in sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_Constraint () )) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((((((((((and_vec + ((concat_vec ((concat_vec HMC SSC : 3 words$word)) PxC + : 5 words$word)) (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word) + : 5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) \/ ((((((((and_vec + ((concat_vec ((concat_vec HMC SSC : 3 words$word)) PxC + : 5 words$word)) + (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word) + : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) \/ ((((((((and_vec + ((concat_vec ((concat_vec HMC SSC : 3 words$word)) PxC + : 5 words$word)) + (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word) + : 5 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) \/ ((((((((concat_vec ((concat_vec HMC SSC : 3 words$word)) PxC + : 5 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))) \/ ((((((((concat_vec ((concat_vec HMC SSC : 3 words$word)) + PxC + : 5 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) \/ (((((and_vec + ((concat_vec + ((concat_vec HMC SSC : 3 words$word)) PxC + : 5 words$word)) + (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word) + : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word))))))))))))))))))) \/ (((((((((HMC = (vec_of_bits [B0] : 1 words$word)))) /\ (((PxC = (vec_of_bits [B0;B0] : 2 words$word))))))) /\ (((((~ isbreakpnt)) \/ ((~ ((HaveAArch32EL EL1))))))))))))) \/ (((((((((SSC = (vec_of_bits [B0;B1] : 2 words$word)))) \/ (((SSC = (vec_of_bits [B1;B0] : 2 words$word))))))) /\ ((~ ((HaveEL EL3)))))))))) \/ ((((((((((((((concat_vec HMC SSC : 3 words$word)) <> (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((concat_vec HMC SSC : 3 words$word)) <> (vec_of_bits [B1;B1;B1] : 3 words$word))))))) /\ ((~ ((HaveEL EL3))))))) /\ ((~ ((HaveEL EL2)))))))))) \/ ((((((((concat_vec ((concat_vec HMC SSC : 3 words$word)) PxC : 5 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))) /\ ((~ ((HaveEL EL2)))))))))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 5 : int):ii) : ( 5 words$word) M))) (\ (tmp_50 : 5 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((ConstrainUnpredictableBits (( 5 : int):ii) Unpredictable_RESBPWPCTRL + : ((Constraint # 5 words$word)) M))) (\ (w__0 : (Constraint # 5 bits)) . + let (tup__0, tup__1) = w__0 in + let c = tup__0 in + let tmp_50 = tup__1 in + let (tmp_60 : 5 bits) = tmp_50 in + let HMC = ((vec_of_bits [access_vec_dec tmp_60 (( 4 : int):ii)] : 1 words$word)) in + let (tmp_70 : 4 bits) = ((slice tmp_60 (( 0 : int):ii) (( 4 : int):ii) : 4 words$word)) in + let SSC = ((slice tmp_70 (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let PxC = ((slice tmp_70 (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ (((c = Constraint_UNKNOWN)))))) "((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))")) + (if (((c = Constraint_DISABLED))) then (sail2_state_monad$early_returnS F : (unit, bool) MR) + else sail2_state_monad$returnS () )) + (sail2_state_monad$returnS (HMC, PxC, SSC, c)))) + else sail2_state_monad$returnS (HMC, PxC, SSC, c)) (\ varstup . let ((HMC : 1 words$word), (PxC : 2 words$word), (SSC : + 2 words$word), (c : Constraint)) = varstup in + let (EL3_match : bool) = + ((((((HaveEL EL3)) /\ (((HMC = (vec_of_bits [B1] : 1 words$word))))))) /\ ((((vec_of_bits [access_vec_dec SSC (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))) in + let (EL2_match : bool) = (((HaveEL EL2)) /\ (((HMC = (vec_of_bits [B1] : 1 words$word))))) in + let (EL1_match : bool) = + ((vec_of_bits [access_vec_dec PxC (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (EL0_match : bool) = + ((vec_of_bits [access_vec_dec PxC (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (priv_match : bool) . sail2_state_monad$bindS + (if (((((~ ispriv)) /\ ((~ isbreakpnt))))) then sail2_state_monad$returnS EL0_match + else sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . + let p__294 = (w__1.ProcState_EL) in + let pat_0 = p__294 in + let (priv_match : bool) = + (if (((pat_0 = EL3))) then EL3_match + else if (((pat_0 = EL2))) then EL2_match + else if (((pat_0 = EL1))) then EL1_match + else EL0_match) in + sail2_state_monad$returnS priv_match)) (\ (priv_match : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (security_state_match : bool) . + let b__0 = SSC in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS T + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS (IsSecure () )) (\ (w__2 : bool) . + let (security_state_match : bool) = (~ w__2) in + sail2_state_monad$returnS security_state_match) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$liftRS (IsSecure () ) + else sail2_state_monad$returnS T) (\ (security_state_match : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (last_ctx_cmp : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (first_ctx_cmp : ii) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (undefined_int () )) (\ (lbn : ii) . sail2_state_monad$bindS + (if linked then + let lbn = (lem$w2ui LBN) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M))) (\ (w__4 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M))) (\ (w__5 : 64 bits) . + let first_ctx_cmp = + (((lem$w2ui ((slice w__4 (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))) - + ((lem$w2ui ((slice w__5 (( 28 : int):ii) (( 4 : int):ii) : 4 words$word))))) in sail2_state_monad$bindS + (sail2_state_monad$liftRS ((sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M))) (\ (w__6 : 64 bits) . + let last_ctx_cmp = (lem$w2ui ((slice w__6 (( 12 : int):ii) (( 4 : int):ii) : 4 words$word))) in + if (((((((ex_int lbn)) < ((ex_int first_ctx_cmp)))) \/ ((((ex_int lbn)) > ((ex_int last_ctx_cmp))))))) then sail2_state_monad$bindS + (sail2_state_monad$liftRS (ConstrainUnpredictableInteger first_ctx_cmp last_ctx_cmp Unpredictable_BPNOTCTXCMP)) (\ varstup . let (tup__0, tup__1) = varstup in + let c = tup__0 in + let lbn = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$liftRS (sail2_state_monad$assert_expS ((((((c = Constraint_DISABLED))) \/ ((((((c = Constraint_NONE))) \/ (((c = Constraint_UNKNOWN))))))))) "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))")) + (case c of + Constraint_DISABLED => sail2_state_monad$seqS (sail2_state_monad$early_returnS F : (unit, bool) MR) (sail2_state_monad$returnS linked) + | Constraint_NONE => sail2_state_monad$returnS F + )) (\ (linked : bool) . + sail2_state_monad$returnS (lbn, linked))) + else sail2_state_monad$returnS (lbn, linked)))) + else sail2_state_monad$returnS (lbn, linked)) (\ varstup . let ((lbn : ii), (linked : bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (linked_match : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$undefined_boolS () )) (\ (linked_to : bool) . sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (vaddress : 64 bits) . sail2_state_monad$bindS + (if linked then sail2_state_monad$bindS + (sail2_state_monad$liftRS ((undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M))) (\ (w__7 : 64 bits) . + let (vaddress : 64 bits) = w__7 in + let (linked_to : bool) = T in + let (linked_match : bool) = (AArch64_BreakpointValueMatch lbn vaddress linked_to) in + sail2_state_monad$returnS linked_match) + else sail2_state_monad$returnS linked_match) (\ (linked_match : bool) . + sail2_state_monad$returnS ((((((priv_match /\ security_state_match))) /\ (((((~ linked)) \/ linked_match)))))))))))))))))))))))`; + + +(*val AArch64_WatchpointMatch : ii -> mword ty64 -> ii -> bool -> bool -> M bool*) + +val _ = Define ` + ((AArch64_WatchpointMatch:int ->(64)words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress size1 ispriv iswrite= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))") + (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M)) (\ (w__2 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((n <= ((lem$w2ui ((slice w__2 (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)))))) "(n <= UInt((ID_AA64DFR0_EL1).WRPs))") + (sail2_state_monad$read_regS DBGWCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . + let (enabled : bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n : 32 words$word)) (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__4 : ( 32 bits) list) . + let (linked : bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__4 n : 32 words$word)) (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (isbreakpnt : bool) = F in sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__5 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__6 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__7 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__8 : ( 32 bits) list) . sail2_state_monad$bindS + (AArch64_StateMatch ((slice ((access_list_dec w__5 n : 32 words$word)) (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [access_vec_dec ((access_list_dec w__6 n : 32 words$word)) (( 13 : int):ii)] : 1 words$word) + ((slice ((access_list_dec w__7 n : 32 words$word)) (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) linked + ((slice ((access_list_dec w__8 n : 32 words$word)) (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) isbreakpnt + ispriv) (\ (state_match : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGWCR_EL1_ref) (\ (w__9 : ( 32 bits) list) . + let (ls_match : bool) = + ((vec_of_bits [access_vec_dec + ((slice ((access_list_dec w__9 n : 32 words$word)) (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) + (if iswrite then (( 1 : int):ii) + else (( 0 : int):ii))] + : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (value_match_name : bool) = F in sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) value_match_name + (\ byte value_match_name . + sail2_state$or_boolS (sail2_state_monad$returnS value_match_name) + ((AArch64_WatchpointByteMatch n ((add_vec_int vaddress byte : 64 words$word)))))) (\ (value_match_name : + bool) . + sail2_state_monad$returnS (((((((((value_match_name /\ state_match))) /\ ls_match))) /\ enabled)))))))))))))))))`; + + +(*val AArch64_BreakpointMatch : ii -> mword ty64 -> ii -> M bool*) + +val _ = Define ` + ((AArch64_BreakpointMatch:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n vaddress size1= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))") + (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M)) (\ (w__2 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((n <= ((lem$w2ui ((slice w__2 (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))))) "(n <= UInt((ID_AA64DFR0_EL1).BRPs))") + (sail2_state_monad$read_regS DBGBCR_EL1_ref)) (\ (w__3 : ( 32 bits) list) . + let (enabled : bool) = + ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n : 32 words$word)) (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + let (ispriv : bool) = (w__4.ProcState_EL <> EL0) in sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__5 : ( 32 bits) list) . + let (linked : bool) = + (((and_vec ((slice ((access_list_dec w__5 n : 32 words$word)) (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)) + (vec_of_bits [B1;B0;B1;B1] : 4 words$word) + : 4 words$word)) = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)) in + let (isbreakpnt : bool) = T in + let (linked_to : bool) = F in sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__6 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__7 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__8 : ( 32 bits) list) . sail2_state_monad$bindS + (sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__9 : ( 32 bits) list) . sail2_state_monad$bindS + (AArch64_StateMatch ((slice ((access_list_dec w__6 n : 32 words$word)) (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)) + (vec_of_bits [access_vec_dec ((access_list_dec w__7 n : 32 words$word)) (( 13 : int):ii)] : 1 words$word) + ((slice ((access_list_dec w__8 n : 32 words$word)) (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) linked + ((slice ((access_list_dec w__9 n : 32 words$word)) (( 16 : int):ii) (( 4 : int):ii) : 4 words$word)) isbreakpnt + ispriv) (\ (state_match : bool) . + let (value_match_name : bool) = (AArch64_BreakpointValueMatch n vaddress linked_to) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (match_i : bool) . sail2_state_monad$bindS + (if (((((HaveAnyAArch32 () )) /\ (((size1 = (( 4 : int):ii))))))) then + let match_i = + (AArch64_BreakpointValueMatch n ((add_vec_int vaddress (( 2 : int):ii) : 64 words$word)) linked_to) in + if (((((~ value_match_name)) /\ match_i))) then + ConstrainUnpredictableBool Unpredictable_BPMATCHHALF + else sail2_state_monad$returnS value_match_name + else sail2_state_monad$returnS value_match_name) (\ (value_match_name : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec vaddress (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGBCR_EL1_ref) (\ (w__11 : ( 32 bits) list) . + sail2_state_monad$returnS (((((slice ((access_list_dec w__11 n : 32 words$word)) (( 5 : int):ii) (( 4 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B1;B1;B1] : 4 words$word))))))) (\ (w__12 : bool) . sail2_state_monad$bindS + (if w__12 then + if value_match_name then ConstrainUnpredictableBool Unpredictable_BPMATCHHALF + else sail2_state_monad$returnS value_match_name + else sail2_state_monad$returnS value_match_name) (\ (value_match_name : bool) . + let (val_match : bool) = ((((value_match_name /\ state_match))) /\ enabled) in + sail2_state_monad$returnS val_match)))))))))))))))))`; + + +(*val AArch64_CheckBreakpoint : mword ty64 -> ii -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CheckBreakpoint:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress size1= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))") + (sail2_state$or_boolS + (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((((((size1 = (( 2 : int):ii)))) \/ (((size1 = (( 4 : int):ii))))))))) + (sail2_state_monad$returnS (((size1 = (( 4 : int):ii))))))) (\ (w__4 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__4 "((UsingAArch32() && ((size == 2) || (size == 4))) || (size == 4))") + (let (val_match : bool) = F in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (match_i : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((lem$w2ui ((slice w__5 (( 12 : int):ii) (( 4 : int):ii) : 4 words$word)))) (( 1 : int):ii)) (match_i, + val_match) + (\ i varstup . let (match_i, val_match) = varstup in sail2_state_monad$bindS + (AArch64_BreakpointMatch i vaddress size1) (\ (w__6 : bool) . + let (match_i : bool) = w__6 in + let (val_match : bool) = (val_match \/ match_i) in + sail2_state_monad$returnS (match_i, val_match)))) (\ varstup . let ((match_i : bool), (val_match : bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . sail2_state_monad$bindS + (undefined_AccType () ) (\ (acctype : AccType) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (reason : 6 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS val_match) ((HaltOnBreakpointOrWatchpoint () ))) (\ (w__8 : bool) . + if w__8 then + let reason = DebugHalt_Breakpoint in sail2_state_monad$bindS (sail2_state_monad$seqS + (Halt reason) (undefined_FaultRecord () )) (\ (w__9 : FaultRecord) . sail2_state_monad$returnS w__9) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS val_match) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__10 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 15 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((AArch64_GenerateDebugExceptions () ))) (\ (w__13 : + bool) . + if w__13 then + let acctype = AccType_IFETCH in + let iswrite = F in + AArch64_DebugFault acctype iswrite + else AArch64_NoFault () ))))))))))))))`; + + +(*val AArch64_BranchAddr : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AArch64_BranchAddr:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress= (sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__0)) "!(UsingAArch32())") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$bindS + (AddrTop vaddress T w__1.ProcState_EL) (\ (w__2 : ii) . sail2_state_monad$bindS + (coerce_int_nat w__2) (\ (msbit : ii) . + if (((((ex_nat msbit)) = (( 63 : int):ii)))) then sail2_state_monad$returnS vaddress + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$returnS (((w__3.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_EL = EL1)))))) ((IsInHost () ))) + (sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec vaddress msbit] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) (\ (w__8 : bool) . + sail2_state_monad$returnS (if w__8 then + (sext_slice (( 64 : int):ii) vaddress (( 0 : int):ii) ((((ex_nat msbit)) + (( 1 : int):ii))) + : 64 words$word) + else + (zext_slice (( 64 : int):ii) vaddress (( 0 : int):ii) ((((ex_nat msbit)) + (( 1 : int):ii))) + : 64 words$word)))))))))`; + + +(*val BranchTo : forall 'N . Size 'N => mword 'N -> BranchType -> M unit*) + +val _ = Define ` + ((BranchTo:'N words$word -> BranchType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target branch_type= (sail2_state_monad$seqS + (sail2_state_monad$write_regS BranchTaken_ref T) + (let (_ : unit) = (Hint_Branch branch_type) in + if (((((int_of_num (words$word_len target))) = (( 32 : int):ii)))) then sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__0 "UsingAArch32()") + (ZeroExtend__1 (( 64 : int):ii) target : ( 64 words$word) M)) (\ (w__1 : 64 bits) . + sail2_state_monad$write_regS PC_ref w__1)) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((int_of_num (words$word_len target))) = (( 64 : int):ii))))) + ( sail2_state_monad$bindS(UsingAArch32 () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) (\ (w__3 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__3 "((N == 64) && !(UsingAArch32()))") + (AArch64_BranchAddr ((slice target (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) : ( 64 words$word) M)) (\ (w__4 : 64 + bits) . + sail2_state_monad$write_regS PC_ref w__4)))))`; + + +(*val aarch64_branch_unconditional_immediate : BranchType -> mword ty64 -> M unit*) + +val _ = Define ` + ((aarch64_branch_unconditional_immediate:BranchType ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) branch_type offset= (sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((branch_type = BranchType_CALL))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + aset_X (( 30 : int):ii) ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ) + (aget_PC () : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + BranchTo ((add_vec w__1 offset : 64 words$word)) branch_type)))`; + + +(*val branch_unconditional_immediate_decode : mword ty1 -> mword ty26 -> M unit*) + +val _ = Define ` + ((branch_unconditional_immediate_decode:(1)words$word ->(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op imm26= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (branch_type : BranchType) = + (if (((op = (vec_of_bits [B1] : 1 words$word)))) then BranchType_CALL + else BranchType_JMP) in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm26 (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_branch_unconditional_immediate branch_type offset))))`; + + +(*val aarch64_branch_conditional_test : ii -> mword ty1 -> ii -> mword ty64 -> ii -> M unit*) + +val _ = Define ` + ((aarch64_branch_conditional_test:int ->(1)words$word -> int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) bit_pos bit_val l__143 offset t= + (if (((l__143 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (operand : 8 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] : 1 words$word) = bit_val))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + BranchTo ((add_vec w__0 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__143 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (operand : 16 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] : 1 words$word) = bit_val))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + BranchTo ((add_vec w__1 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__143 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (operand : 32 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] : 1 words$word) = bit_val))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + BranchTo ((add_vec w__2 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__143 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (operand : 64 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] : 1 words$word) = bit_val))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + BranchTo ((add_vec w__3 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__143 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (operand : 128 bits) . + if ((((vec_of_bits [access_vec_dec operand bit_pos] : 1 words$word) = bit_val))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + BranchTo ((add_vec w__4 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else + let dbytes = (ex_int ((l__143 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val branch_conditional_test_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty14 -> mword ty5 -> M unit*) + +val _ = Define ` + ((branch_conditional_test_decode:(1)words$word ->(1)words$word ->(5)words$word ->(14)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b5 op b40 imm14 Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (datasize : int) = + (if (((b5 = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (bit_pos : ii) = (lem$w2ui ((concat_vec b5 b40 : 6 words$word))) in + let (bit_val : 1 bits) = op in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm14 (vec_of_bits [B0;B0] : 2 words$word) : 16 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_branch_conditional_test bit_pos bit_val datasize offset t))))`; + + +(*val aarch64_branch_conditional_cond : mword ty4 -> mword ty64 -> M unit*) + +val _ = Define ` + ((aarch64_branch_conditional_cond:(4)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition offset= (sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__0 : bool) . + if w__0 then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + BranchTo ((add_vec w__1 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () )))`; + + +(*val branch_conditional_cond_decode : mword ty1 -> mword ty19 -> mword ty1 -> mword ty4 -> M unit*) + +val _ = Define ` + ((branch_conditional_cond_decode:(1)words$word ->(19)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) o1 imm19 o0 cond= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M)) (\ (offset : 64 bits) . + let (condition : 4 bits) = cond in + aarch64_branch_conditional_cond condition offset)))`; + + +(*val aarch64_branch_conditional_compare : ii -> bool -> mword ty64 -> ii -> M unit*) + +val _ = Define ` + ((aarch64_branch_conditional_compare:int -> bool ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__138 iszero offset t= + (if (((l__138 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (operand1 : 8 bits) . + if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + BranchTo ((add_vec w__0 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__138 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (operand1 : 16 bits) . + if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + BranchTo ((add_vec w__1 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__138 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (operand1 : 32 bits) . + if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + BranchTo ((add_vec w__2 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__138 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (operand1 : 64 bits) . + if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + BranchTo ((add_vec w__3 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else if (((l__138 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (operand1 : 128 bits) . + if (((((IsZero operand1)) = iszero))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + BranchTo ((add_vec w__4 offset : 64 words$word)) BranchType_JMP) + else sail2_state_monad$returnS () ) + else + let dbytes = (ex_int ((l__138 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val branch_conditional_compare_decode : mword ty1 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +val _ = Define ` + ((branch_conditional_compare_decode:(1)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op imm19 Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (iszero : bool) = (op = (vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_branch_conditional_compare datasize iszero offset t))))`; + + +(*val AArch64_TakeReset : bool -> M unit*) + +val _ = Define ` + ((AArch64_TakeReset:bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cold_reset= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ ((HighestELUsingAArch32 () )))) "!(HighestELUsingAArch32())") + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_nRW := ((vec_of_bits [B0] : 1 words$word))|>)) + (if ((HaveEL EL3)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_EL := EL3|>)) + else if ((HaveEL EL2)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__2 with<| ProcState_EL := EL2|>)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_EL := EL1|>)))) + (let (_ : unit) = (AArch64_ResetControlRegisters cold_reset) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_SP := ((vec_of_bits [B1] : 1 words$word))|>)) + (let split_vec = ((vec_of_bits [B1;B1;B1;B1] : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_D := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_A := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_I := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_F := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_IL := ((vec_of_bits [B0] : 1 words$word))|>)) + (AArch64_ResetGeneralRegisters () )) + (AArch64_ResetSIMDFPRegisters () )) + (AArch64_ResetSpecialRegisters () )) + (let (_ : unit) = (ResetExternalDebugRegisters cold_reset) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (rv : 64 bits) . sail2_state_monad$bindS + (if ((HaveEL EL3)) then (sail2_state_monad$read_regS RVBAR_EL3_ref : ( 64 words$word) M) + else if ((HaveEL EL2)) then (sail2_state_monad$read_regS RVBAR_EL2_ref : ( 64 words$word) M) + else (sail2_state_monad$read_regS RVBAR_EL1_ref : ( 64 words$word) M)) (\ (rv : 64 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS ((IsZero_slice rv ((PAMax () )) (((( 64 : int):ii) - ((ex_int ((PAMax () )))))))) + ((IsZero_slice rv (( 0 : int):ii) (( 2 : int):ii)))) (\ (w__16 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__16 "(IsZero((rv)<PAMax()+:((63 - PAMax()) + 1)>) && IsZero((rv)<0+:((1 - 0) + 1)>))") + (BranchTo rv BranchType_UNKNOWN)))))))))))))))))`; + + +(*val __TakeColdReset : unit -> M unit*) + +val _ = Define ` + ((TakeColdReset:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_nRW := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__1 : ProcState) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__1 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + (ResetInterruptState () )) + (ResetMemoryState () )) (ResetExecuteState () )) (AArch64_TakeReset T)))))`; + + +(*val AArch64_TakeException : mword ty2 -> ExceptionRecord -> mword ty64 -> ii -> M unit*) + +val _ = Define ` + ((AArch64_TakeException:(2)words$word -> ExceptionRecord ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el exception preferred_exception_return vect_offset__arg= + (let (vect_offset : ii) = vect_offset__arg in + let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL target_el))) + ( sail2_state_monad$bindS(ELUsingAArch32 target_el) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + sail2_state_monad$returnS ((((lem$w2ui target_el)) >= ((lem$w2ui w__2.ProcState_EL))))))) (\ (w__3 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__3 "((HaveEL(target_el) && !(ELUsingAArch32(target_el))) && (UInt(target_el) >= UInt((PSTATE).EL)))") + (UsingAArch32 () )) (\ (from_32 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if from_32 then AArch64_MaybeZeroRegisterUppers () + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS + (if ((((lem$w2ui target_el)) > ((lem$w2ui w__4.ProcState_EL)))) then sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (lower_32 : bool) . sail2_state_monad$bindS + (if (((target_el = EL3))) then sail2_state_monad$bindS + (sail2_state$and_boolS ( sail2_state_monad$bindS(IsSecure () ) (\ (w__5 : bool) . sail2_state_monad$returnS ((~ w__5)))) + (sail2_state_monad$returnS ((HaveEL EL2)))) (\ (w__6 : bool) . + if w__6 then ELUsingAArch32 EL2 + else ELUsingAArch32 EL1) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS ((IsInHost () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + sail2_state_monad$returnS (((w__10.ProcState_EL = EL0)))))) (sail2_state_monad$returnS (((target_el = EL2))))) (\ (w__12 : + bool) . + if w__12 then ELUsingAArch32 EL0 + else ELUsingAArch32 ((sub_vec_int target_el (( 1 : int):ii) : 2 words$word)))) (\ (lower_32 : bool) . + let (vect_offset : ii) = (vect_offset + (if lower_32 then (( 1536 : int):ii) else (( 1024 : int):ii))) in + sail2_state_monad$returnS vect_offset)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . + let (vect_offset : ii) = + (if (((w__15.ProcState_SP = (vec_of_bits [B1] : 1 words$word)))) then + ((ex_int vect_offset)) + (( 512 : int):ii) + else vect_offset) in + sail2_state_monad$returnS vect_offset)) (\ (vect_offset : ii) . sail2_state_monad$bindS + (GetPSRFromPSTATE () : ( 32 words$word) M) (\ (spsr : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((HaveUAOExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_UAO := ((vec_of_bits [B0] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (if ((~ ((((((exception.ExceptionRecord_typ = Exception_IRQ))) \/ (((exception.ExceptionRecord_typ = Exception_FIQ)))))))) then + AArch64_ReportException exception target_el + else sail2_state_monad$returnS () )) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_EL := target_el|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_nRW := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_SP := ((vec_of_bits [B1] : 1 words$word))|>)) + (aset_SPSR spsr)) + (aset_ELR__1 preferred_exception_return)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + (let split_vec = ((vec_of_bits [B1;B1;B1;B1] : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__21 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__21 with<| ProcState_D := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_A := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_I := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_F := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_IL := ((vec_of_bits [B0] : 1 words$word))|>)) + (if from_32 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__26 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_T := ((vec_of_bits [B0] : 1 words$word))|>))) + else sail2_state_monad$returnS () )) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () ))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__28 : ProcState) . + sail2_state_monad$returnS (((w__28.ProcState_EL = EL1))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__29 : ProcState) . + sail2_state_monad$returnS (((w__29.ProcState_EL = EL2))))) ((ELIsInHost EL0))))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__34 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__34 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__35 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__35 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__36 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__36 with<| ProcState_PAN := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (aget_VBAR__1 () : ( 64 words$word) M)) (\ (w__37 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (BranchTo + ((concat_vec ((slice w__37 (( 11 : int):ii) (( 53 : int):ii) : 53 words$word)) + ((GetSlice_int ((make_the_value (( 11 : int):ii) : 11 itself)) vect_offset (( 0 : int):ii) : 11 words$word)) + : 64 words$word)) BranchType_EXCEPTION) + (sail2_state_monad$undefined_boolS () )) (\ (iesb_req : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__38 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__39 : bool) . sail2_state_monad$seqS + (if w__39 then + let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in + let iesb_req = T in + TakeUnmaskedPhysicalSErrorInterrupts iesb_req + else sail2_state_monad$returnS () ) + (EndOfInstruction () ))))))))))))))))))))))`; + + +(*val TrapPACUse : mword ty2 -> M unit*) + +val _ = Define ` + ((TrapPACUse:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el= (sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL target_el)) /\ (((target_el <> EL0))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + sail2_state_monad$returnS ((((lem$w2ui target_el)) >= ((lem$w2ui w__0.ProcState_EL))))))) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__1 "((HaveEL(target_el) && (target_el != EL0)) && (UInt(target_el) >= UInt((PSTATE).EL)))") + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . sail2_state_monad$bindS + (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_PACTrap) (\ (w__2 : ExceptionRecord) . + let exception = w__2 in + AArch64_TakeException target_el exception preferred_exception_return vect_offset))))))`; + + +(*val Strip : mword ty64 -> bool -> M (mword ty64)*) + +val _ = Define ` + ((Strip:(64)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) A data= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (original_ptr : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (extfield : 64 bits) . sail2_state_monad$bindS + (CalculateTBI A data) (\ (tbi : bool) . sail2_state_monad$bindS + (CalculateBottomPACBit A (vec_of_bits [access_vec_dec A (( 55 : int):ii)] : 1 words$word)) (\ (w__0 : ii) . + let bottom_PAC_bit = (ex_int w__0) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let extfield = + ((replicate_bits (vec_of_bits [access_vec_dec A (( 55 : int):ii)] : 1 words$word) (( 64 : int):ii) : 64 words$word)) in + let (original_ptr : 64 bits) = + (if tbi then + (concat_vec ((slice A (( 56 : int):ii) (( 8 : int):ii) : 8 words$word)) + ((slice_slice_concat (( 56 : int):ii) extfield (( 0 : int):ii) + ((((~ bottom_PAC_bit)) + (( 56 : int):ii))) A (( 0 : int):ii) bottom_PAC_bit + : 56 words$word)) + : 64 words$word) + else + (slice_slice_concat (( 64 : int):ii) extfield (( 0 : int):ii) + ((((~ bottom_PAC_bit)) + (( 64 : int):ii))) A (( 0 : int):ii) bottom_PAC_bit + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + let p__293 = (w__1.ProcState_EL) in + let pat_0 = p__293 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__5 : bool) . sail2_state_monad$returnS ((~ w__5))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__8 : bool) . + let TrapEL2 = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__9 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__10 : bool) . + let (TrapEL3 : bool) = w__10 in + sail2_state_monad$returnS (TrapEL2, TrapEL3)))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__11 : bool) . sail2_state_monad$returnS ((~ w__11))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__13 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let TrapEL2 = w__14 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__16 : bool) . + let (TrapEL3 : bool) = w__16 in + sail2_state_monad$returnS (TrapEL2, TrapEL3))) + else if (((pat_0 = EL2))) then + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__17 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__18 : bool) . + let (TrapEL3 : bool) = w__18 in + sail2_state_monad$returnS (TrapEL2, TrapEL3)) + else + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (TrapEL2, TrapEL3)) (\ varstup . let ((TrapEL2 : bool), (TrapEL3 : bool)) = varstup in + if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else sail2_state_monad$returnS original_ptr)))))))))))`; + + +(*val aarch64_integer_pac_strip_dp_1src : ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_strip_dp_1src:int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d data= + (if ((HavePACExt () )) then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (Strip w__0 data : ( 64 words$word) M) (\ (w__1 : 64 words$word) . aset_X d w__1)) + else sail2_state_monad$returnS () ))`; + + +(*val integer_pac_strip_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_strip_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = ((( 30 : int):ii)) in + let (data : bool) = F in + aarch64_integer_pac_strip_dp_1src d data)))`; + + +(*val AuthIB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AuthIB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIBKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIBKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APIBKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__292 = (w__2.ProcState_EL) in + let pat_0 = p__292 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 30 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (Auth X Y APIBKey_EL1 F (vec_of_bits [B1] : 1 words$word) : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_autib_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_autib_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if ((HavePACExt () )) then + if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AuthIB w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AuthIB w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5))) + else sail2_state_monad$returnS () ))`; + + +(*val integer_pac_autib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autib_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_int () )) (\ (d : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (n : ii) . + let (source_is_sp : bool) = F in + let b__0 = ((concat_vec CRm op2 : 7 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (n : ii) = ((( 31 : int):ii)) in + sail2_state_monad$returnS (d, n, source_is_sp) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (source_is_sp : bool) = T in + sail2_state_monad$returnS (d, n, source_is_sp) + else sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0] : 7 words$word)))) then + let (d : ii) = ((( 17 : int):ii)) in + let (n : ii) = ((( 16 : int):ii)) in + sail2_state_monad$returnS (d, n) + else sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else sail2_state_monad$throwS (Error_See "XPACLRI")) + (sail2_state_monad$returnS (d, n))) (\ varstup . let ((d : ii), (n : ii)) = varstup in + sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup . let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in + aarch64_integer_pac_autib_dp_1src d n source_is_sp)))))`; + + +(*val AuthIA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AuthIA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIAKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIAKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APIAKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__291 = (w__2.ProcState_EL) in + let pat_0 = p__291 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 31 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 31 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (Auth X Y APIAKey_EL1 F (vec_of_bits [B0] : 1 words$word) : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_autia_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_autia_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if ((HavePACExt () )) then + if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AuthIA w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AuthIA w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5))) + else sail2_state_monad$returnS () ))`; + + +(*val integer_pac_autia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autia_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_int () )) (\ (d : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (n : ii) . + let (source_is_sp : bool) = F in + let b__0 = ((concat_vec CRm op2 : 7 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B0] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (n : ii) = ((( 31 : int):ii)) in + sail2_state_monad$returnS (d, n, source_is_sp) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (source_is_sp : bool) = T in + sail2_state_monad$returnS (d, n, source_is_sp) + else sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0] : 7 words$word)))) then + let (d : ii) = ((( 17 : int):ii)) in + let (n : ii) = ((( 16 : int):ii)) in + sail2_state_monad$returnS (d, n) + else sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "XPACLRI") + else sail2_state_monad$throwS (Error_See "HINT")) + (sail2_state_monad$returnS (d, n))) (\ varstup . let ((d : ii), (n : ii)) = varstup in + sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup . let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in + aarch64_integer_pac_autia_dp_1src d n source_is_sp)))))`; + + +(*val aarch64_branch_unconditional_register : BranchType -> ii -> ii -> bool -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_branch_unconditional_register:BranchType -> int -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) branch_type m n pac source_is_sp use_key_a= (sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (target : 64 bits) . sail2_state_monad$bindS + (if pac then sail2_state_monad$bindS + (if source_is_sp then (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) m : ( 64 words$word) M)) (\ (modifier : 64 bits) . + if use_key_a then (AuthIA target modifier : ( 64 words$word) M) + else (AuthIB target modifier : ( 64 words$word) M)) + else sail2_state_monad$returnS target) (\ (target : 64 bits) . sail2_state_monad$seqS + (if (((branch_type = BranchType_CALL))) then sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + aset_X (( 30 : int):ii) ((add_vec_int w__4 (( 4 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ) + (BranchTo target branch_type)))))`; + + +(*val AuthDB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AuthDB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDBKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDBKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APDBKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__290 = (w__2.ProcState_EL) in + let pat_0 = p__290 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 13 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (Auth X Y APDBKey_EL1 T (vec_of_bits [B1] : 1 words$word) : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_autdb_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_autdb_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AuthDB w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AuthDB w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5)))))`; + + +(*val AuthDA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AuthDA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDAKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDAKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APDAKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__289 = (w__2.ProcState_EL) in + let pat_0 = p__289 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (Auth X Y APDAKey_EL1 T (vec_of_bits [B0] : 1 words$word) : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_autda_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_autda_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AuthDA w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AuthDA w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5)))))`; + + +(*val AddPACIB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AddPACIB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIBKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIBKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APIBKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__288 = (w__2.ProcState_EL) in + let pat_0 = p__288 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 30 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (AddPAC X Y APIBKey_EL1 F : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_pacib_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_pacib_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if ((HavePACExt () )) then + if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AddPACIB w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AddPACIB w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5))) + else sail2_state_monad$returnS () ))`; + + +(*val integer_pac_pacib_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacib_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_int () )) (\ (d : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (n : ii) . + let (source_is_sp : bool) = F in + let b__0 = ((concat_vec CRm op2 : 7 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (n : ii) = ((( 31 : int):ii)) in + sail2_state_monad$returnS (d, n, source_is_sp) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (source_is_sp : bool) = T in + sail2_state_monad$returnS (d, n, source_is_sp) + else sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0] : 7 words$word)))) then + let (d : ii) = ((( 17 : int):ii)) in + let (n : ii) = ((( 16 : int):ii)) in + sail2_state_monad$returnS (d, n) + else sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else sail2_state_monad$throwS (Error_See "XPACLRI")) + (sail2_state_monad$returnS (d, n))) (\ varstup . let ((d : ii), (n : ii)) = varstup in + sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup . let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in + aarch64_integer_pac_pacib_dp_1src d n source_is_sp)))))`; + + +(*val AddPACIA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AddPACIA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIAKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APIAKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APIAKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__287 = (w__2.ProcState_EL) in + let pat_0 = p__287 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 31 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 31 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (AddPAC X Y APIAKey_EL1 F : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_pacia_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_pacia_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if ((HavePACExt () )) then + if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AddPACIA w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AddPACIA w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5))) + else sail2_state_monad$returnS () ))`; + + +(*val integer_pac_pacia_hint_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacia_hint_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_int () )) (\ (d : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (n : ii) . + let (source_is_sp : bool) = F in + let b__0 = ((concat_vec CRm op2 : 7 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (n : ii) = ((( 31 : int):ii)) in + sail2_state_monad$returnS (d, n, source_is_sp) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B1] : 7 words$word)))) then + let (d : ii) = ((( 30 : int):ii)) in + let (source_is_sp : bool) = T in + sail2_state_monad$returnS (d, n, source_is_sp) + else sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))) then + let (d : ii) = ((( 17 : int):ii)) in + let (n : ii) = ((( 16 : int):ii)) in + sail2_state_monad$returnS (d, n) + else sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B1;B0] : 7 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIB") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIA") + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 1 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word)))) then + sail2_state_monad$throwS (Error_See "AUTIB") + else sail2_state_monad$throwS (Error_See "XPACLRI")) + (sail2_state_monad$returnS (d, n))) (\ varstup . let ((d : ii), (n : ii)) = varstup in + sail2_state_monad$returnS (d, n, source_is_sp))) (\ varstup . let ((d : ii), (n : ii), (source_is_sp : bool)) = varstup in + aarch64_integer_pac_pacia_dp_1src d n source_is_sp)))))`; + + +(*val AddPACGA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AddPACGA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APGAKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APGAKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APGAKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__286 = (w__2.ProcState_EL) in + let pat_0 = p__286 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__6 : bool) . sail2_state_monad$returnS ((~ w__6))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__9 : bool) . + let TrapEL2 = w__9 in sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__10 : 32 bits) . + let (TrapEL3 : bool) = + ((vec_of_bits [access_vec_dec w__10 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS (TrapEL2, TrapEL3)))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__11 : bool) . sail2_state_monad$returnS ((~ w__11))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__13 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let TrapEL2 = w__14 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__15 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__16 : bool) . + let (TrapEL3 : bool) = w__16 in + sail2_state_monad$returnS (TrapEL2, TrapEL3))) + else if (((pat_0 = EL2))) then + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__17 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__18 : bool) . + let (TrapEL3 : bool) = w__18 in + sail2_state_monad$returnS (TrapEL2, TrapEL3)) + else + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (TrapEL2, TrapEL3)) (\ varstup . let ((TrapEL2 : bool), (TrapEL3 : bool)) = varstup in + if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else sail2_state_monad$bindS + (ComputePAC X Y ((slice APGAKey_EL1 (( 64 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice APGAKey_EL1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : ( 64 words$word) M) (\ (w__21 : 64 words$word) . + sail2_state_monad$returnS ((concat_vec ((slice w__21 (( 32 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 64 words$word)))))))))))`; + + +(*val aarch64_integer_pac_pacga_dp_2src : ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_pacga_dp_2src:int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d m n source_is_sp= + (if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AddPACGA w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AddPACGA w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5)))))`; + + +(*val AddPACDB : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AddPACDB:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDBKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDBKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APDBKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__285 = (w__2.ProcState_EL) in + let pat_0 = p__285 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 13 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (AddPAC X Y APDBKey_EL1 T : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_pacdb_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_pacdb_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AddPACDB w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AddPACDB w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5)))))`; + + +(*val AddPACDA : mword ty64 -> mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((AddPACDA:(64)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) X Y= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL2 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (TrapEL3 : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (Enable : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDAKeyHi_EL1_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS APDAKeyLo_EL1_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (APDAKey_EL1 : 128 bits) = + ((concat_vec ((slice w__0 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((slice w__1 (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + : 128 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + let p__284 = (w__2.ProcState_EL) in + let pat_0 = p__284 in sail2_state_monad$bindS + (if (((pat_0 = EL0))) then sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (IsEL1Regime : bool) . sail2_state_monad$bindS + (if IsEL1Regime then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let Enable = w__8 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveEL EL2)) /\ IsEL1Regime)))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__12 : bool) . + let TrapEL2 = w__12 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__14 : bool) . + let (TrapEL3 : bool) = w__14 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))))) + else if (((pat_0 = EL1))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 : int):ii)] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__16 : bool) . sail2_state_monad$returnS ((~ w__16))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 41 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__19 : bool) . + let TrapEL2 = w__19 in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__20 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__21 : bool) . + let (TrapEL3 : bool) = w__21 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3)))) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__22 : 32 bits) . + let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 : int):ii)] : 1 words$word)) in + let TrapEL2 = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__23 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__23 (( 17 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) (\ (w__24 : bool) . + let (TrapEL3 : bool) = w__24 in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + let (Enable : 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 : int):ii)] : 1 words$word)) in + let (TrapEL2 : bool) = F in + let (TrapEL3 : bool) = F in + sail2_state_monad$returnS (Enable, TrapEL2, TrapEL3))) (\ varstup . let ((Enable : 1 bits), (TrapEL2 : + bool), (TrapEL3 : bool)) = varstup in + if (((Enable = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$returnS X + else if TrapEL2 then sail2_state_monad$seqS (TrapPACUse EL2) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if TrapEL3 then sail2_state_monad$seqS (TrapPACUse EL3) (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (AddPAC X Y APDAKey_EL1 T : ( 64 words$word) M))))))))))`; + + +(*val aarch64_integer_pac_pacda_dp_1src : ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_integer_pac_pacda_dp_1src:int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d n source_is_sp= + (if source_is_sp then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (AddPACDA w__0 w__1 : ( 64 words$word) M) (\ (w__2 : 64 words$word) . aset_X d w__2))) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) d : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) n : ( 64 words$word) M) (\ (w__4 : 64 words$word) . sail2_state_monad$bindS + (AddPACDA w__3 w__4 : ( 64 words$word) M) (\ (w__5 : 64 words$word) . aset_X d w__5)))))`; + + +(*val AArch64_WatchpointException : mword ty64 -> FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_WatchpointException:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL3))) "((PSTATE).EL != EL3)") + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$returnS (((w__3.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_EL = EL1))))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__8 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (AArch64_AbortSyndrome Exception_Watchpoint fault vaddress) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$returnS (((w__10.ProcState_EL = EL2))))) + (sail2_state_monad$returnS route_to_el2)) (\ (w__11 : bool) . + if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))`; + + +(*val AArch64_WFxTrap : mword ty2 -> bool -> M unit*) + +val _ = Define ` + ((AArch64_WFxTrap:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el is_wfe= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((lem$w2ui target_el)) > ((lem$w2ui w__0.ProcState_EL)))) "(UInt(target_el) > UInt((PSTATE).EL))") + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_WFxTrap) (\ (exception : ExceptionRecord) . + let (tmp_2720 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS + (ConditionSyndrome () : ( 5 words$word) M) (\ (w__1 : 5 words$word) . + let tmp_2720 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2720 (( 20 : int):ii) w__1 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2720|>)) in + let (tmp_2730 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2730 = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2730 (( 0 : int):ii) + (if is_wfe then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2730|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__5 : bool) . + if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))`; + + +(*val AArch64_CheckForWFxTrap : mword ty2 -> bool -> M unit*) + +val _ = Define ` + ((AArch64_CheckForWFxTrap:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el is_wfe= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((HaveEL target_el)) "HaveEL(target_el)") + (sail2_state_monad$undefined_boolS () )) (\ (trap : bool) . + let pat_0 = target_el in sail2_state_monad$bindS + (if (((pat_0 = EL1))) then sail2_state_monad$bindS + (if is_wfe then sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__0 (( 18 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__1 (( 16 : int):ii)] : 1 words$word))) (\ (w__2 : 1 words$word) . + let (trap : bool) = (w__2 = (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS trap) + else if (((pat_0 = EL2))) then sail2_state_monad$bindS + (if is_wfe then sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__3 (( 14 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__4 (( 13 : int):ii)] : 1 words$word))) (\ (w__5 : 1 words$word) . + let (trap : bool) = (w__5 = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS trap) + else sail2_state_monad$bindS + (if is_wfe then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 13 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__7 (( 12 : int):ii)] : 1 words$word))) (\ (w__8 : 1 words$word) . + let (trap : bool) = (w__8 = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS trap)) (\ (trap : bool) . + if trap then AArch64_WFxTrap target_el is_wfe + else sail2_state_monad$returnS () ))))`; + + +(*val aarch64_system_hints : SystemHintOp -> M unit*) + +val _ = Define ` + ((aarch64_system_hints:SystemHintOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op= + ((case op of + SystemHintOp_YIELD => sail2_state_monad$returnS ((Hint_Yield () )) + | SystemHintOp_WFE => sail2_state_monad$bindS + (IsEventRegisterSet () ) (\ (w__0 : bool) . + if w__0 then ClearEventRegister () + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__1.ProcState_EL = EL0))) then AArch64_CheckForWFxTrap EL1 T + else sail2_state_monad$returnS () ) + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_EL = EL1))))))) + ( sail2_state_monad$bindS(IsInHost () ) (\ (w__8 : bool) . sail2_state_monad$returnS ((~ w__8)))))) (\ (w__9 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__9 then AArch64_CheckForWFxTrap EL2 T + else sail2_state_monad$returnS () ) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + sail2_state_monad$returnS (((w__10.ProcState_EL <> EL3))))))) (\ (w__11 : bool) . sail2_state_monad$seqS + (if w__11 then AArch64_CheckForWFxTrap EL3 T else sail2_state_monad$returnS () ) (WaitForEvent () ))))) + | SystemHintOp_WFI => sail2_state_monad$bindS + (InterruptPending () ) (\ (w__12 : bool) . + if ((~ w__12)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__13.ProcState_EL = EL0))) then AArch64_CheckForWFxTrap EL1 F + else sail2_state_monad$returnS () ) + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__14 : bool) . sail2_state_monad$returnS ((~ w__14))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__16 : ProcState) . + sail2_state_monad$returnS (((w__16.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . + sail2_state_monad$returnS (((w__17.ProcState_EL = EL1))))))) + ( sail2_state_monad$bindS(IsInHost () ) (\ (w__20 : bool) . sail2_state_monad$returnS ((~ w__20)))))) (\ (w__21 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__21 then AArch64_CheckForWFxTrap EL2 F + else sail2_state_monad$returnS () ) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . + sail2_state_monad$returnS (((w__22.ProcState_EL <> EL3))))))) (\ (w__23 : bool) . sail2_state_monad$seqS + (if w__23 then AArch64_CheckForWFxTrap EL3 F else sail2_state_monad$returnS () ) (WaitForInterrupt () )))) + else sail2_state_monad$returnS () ) + | SystemHintOp_SEV => SendEvent () + | SystemHintOp_SEVL => SendEventLocal () + | SystemHintOp_ESB => + let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in sail2_state_monad$bindS (sail2_state_monad$seqS + (AArch64_ESBOperation () ) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__24 : bool) . sail2_state_monad$returnS ((~ w__24))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . + sail2_state_monad$returnS (((w__26.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__27 : ProcState) . + sail2_state_monad$returnS (((w__27.ProcState_EL = EL1)))))))) (\ (w__29 : bool) . sail2_state_monad$seqS + (if w__29 then AArch64_vESBOperation () else sail2_state_monad$returnS () ) (TakeUnmaskedSErrorInterrupts () )) + | SystemHintOp_PSB => sail2_state_monad$returnS ((ProfilingSynchronizationBarrier () )) + | _ => sail2_state_monad$returnS () + )))`; + + +(*val system_hints_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_hints_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_SystemHintOp () )) (\ (op : SystemHintOp) . + let b__0 = ((concat_vec CRm op2 : 7 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_NOP + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_YIELD + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_WFE + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_WFI + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B0;B0] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_SEV + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B0;B1] : 7 words$word)))) then + sail2_state_monad$returnS SystemHintOp_SEVL + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1] : 7 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$throwS (Error_See "XPACLRI")) (sail2_state_monad$returnS op) + else if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 3 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$throwS (Error_See "PACIA1716, PACIB1716, AUTIA1716, AUTIB1716")) (sail2_state_monad$returnS op) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0] : 7 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HaveRASExt () )))) then EndOfInstruction () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS SystemHintOp_ESB) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1] : 7 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HaveStatisticalProfiling () )))) then EndOfInstruction () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS SystemHintOp_PSB) + else sail2_state_monad$seqS + (if (((((subrange_vec_dec b__0 (( 6 : int):ii) (( 3 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + sail2_state_monad$throwS (Error_See "PACIAZ, PACIASP, PACIBZ, PACIBSP, AUTIAZ, AUTIASP, AUTIBZ, AUTIBSP") + else EndOfInstruction () ) + (sail2_state_monad$returnS op)) (\ (op : SystemHintOp) . + aarch64_system_hints op))))`; + + +(*val AArch64_VectorCatchException : FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_VectorCatchException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL2))) "((PSTATE).EL != EL2)") + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))))) (\ (w__6 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__6 "((HaveEL(EL2) && !(IsSecure())) && (((HCR_EL2).TGE == '1') || ((MDCR_EL2).TDE == '1')))") + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (vaddress : 64 bits) . sail2_state_monad$bindS + (AArch64_AbortSyndrome Exception_VectorCatch fault vaddress) (\ (exception : ExceptionRecord) . + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))`; + + +(*val AArch64_UndefinedFault : unit -> M unit*) + +val _ = Define ` + ((AArch64_UndefinedFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL0)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_Uncategorized) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + if ((((lem$w2ui w__5.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + AArch64_TakeException w__6.ProcState_EL exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`; + + +(*val AArch64_SystemRegisterTrap : mword ty2 -> mword ty2 -> mword ty3 -> mword ty3 -> mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> M unit*) + +val _ = Define ` + ((AArch64_SystemRegisterTrap:(2)words$word ->(2)words$word ->(3)words$word ->(3)words$word ->(4)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el op0 op2 op1 crn rt crm dir= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((lem$w2ui target_el)) >= ((lem$w2ui w__0.ProcState_EL)))) "(UInt(target_el) >= UInt((PSTATE).EL))") + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_SystemRegisterTrap) (\ (exception : ExceptionRecord) . + let (tmp_2800 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2800 = ((set_slice (( 25 : int):ii) (( 2 : int):ii) tmp_2800 (( 20 : int):ii) op0 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2800|>)) in + let (tmp_2810 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2810 = ((set_slice (( 25 : int):ii) (( 3 : int):ii) tmp_2810 (( 17 : int):ii) op2 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2810|>)) in + let (tmp_2820 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2820 = ((set_slice (( 25 : int):ii) (( 3 : int):ii) tmp_2820 (( 14 : int):ii) op1 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2820|>)) in + let (tmp_2830 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2830 = ((set_slice (( 25 : int):ii) (( 4 : int):ii) tmp_2830 (( 10 : int):ii) crn : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2830|>)) in + let (tmp_2840 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2840 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2840 (( 5 : int):ii) rt : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2840|>)) in + let (tmp_2850 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2850 = ((set_slice (( 25 : int):ii) (( 4 : int):ii) tmp_2850 (( 1 : int):ii) crm : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2850|>)) in + let (tmp_2860 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2860 = ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2860 (( 0 : int):ii) dir : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2860|>)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__4 : bool) . + if w__4 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException target_el exception preferred_exception_return vect_offset))))))`; + + +(*val AArch64_SoftwareBreakpoint : mword ty16 -> M unit*) + +val _ = Define ` + ((AArch64_SoftwareBreakpoint:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . + sail2_state_monad$returnS (((w__2.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$returnS (((w__3.ProcState_EL = EL1))))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__7 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_SoftwareBreakpoint) (\ (exception : ExceptionRecord) . + let (tmp_2710 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2710 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2710 (( 0 : int):ii) immediate : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2710|>)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + if ((((lem$w2ui w__9.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . + AArch64_TakeException w__10.ProcState_EL exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`; + + +(*val aarch64_system_exceptions_debug_breakpoint : mword ty16 -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_debug_breakpoint:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) comment= (AArch64_SoftwareBreakpoint comment))`; + + +(*val system_exceptions_debug_breakpoint_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_debug_breakpoint_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (comment : 16 bits) = imm16 in + aarch64_system_exceptions_debug_breakpoint comment)))`; + + +(*val AArch64_SPAlignmentFault : unit -> M unit*) + +val _ = Define ` + ((AArch64_SPAlignmentFault:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_SPAlignment) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + if ((((lem$w2ui w__0.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + AArch64_TakeException w__1.ProcState_EL exception preferred_exception_return vect_offset) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__5 : bool) . + if w__5 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))`; + + +(*val CheckSPAlignment : unit -> M unit*) + +val _ = Define ` + ((CheckSPAlignment:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (sp : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (stack_align_check : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (if (((w__0.ProcState_EL = EL0))) then sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + let (stack_align_check : bool) = + ((vec_of_bits [access_vec_dec w__1 (( 4 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS stack_align_check) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + let (stack_align_check : bool) = + ((vec_of_bits [access_vec_dec w__2 (( 3 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)) in + sail2_state_monad$returnS stack_align_check)) (\ (stack_align_check : bool) . + if (((stack_align_check /\ (((sp <> ((Align__1 sp (( 16 : int):ii) : 64 words$word)))))))) then + AArch64_SPAlignmentFault () + else sail2_state_monad$returnS () ))))))`; + + +(*val AArch64_InstructionAbort : mword ty64 -> FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_InstructionAbort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((IsExternalAbort__1 fault))) (\ (route_to_el3 : + bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) . sail2_state_monad$returnS ((~ w__3))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + sail2_state_monad$returnS (((w__6.ProcState_EL = EL1))))))) + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) ((IsSecondStage fault))) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((IsExternalAbort__1 fault))))) (\ (route_to_el2 : + bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (AArch64_AbortSyndrome Exception_InstructionAbort fault vaddress) (\ (exception : + ExceptionRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$returnS (((w__17.ProcState_EL = EL3))))) + (sail2_state_monad$returnS route_to_el3)) (\ (w__18 : bool) . + if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . sail2_state_monad$returnS (((w__19.ProcState_EL = EL2))))) + (sail2_state_monad$returnS route_to_el2)) (\ (w__20 : bool) . + if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`; + + +(*val AArch64_DataAbort : mword ty64 -> FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_DataAbort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__0 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 3 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((IsExternalAbort__1 fault))) (\ (route_to_el3 : + bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) . sail2_state_monad$returnS ((~ w__3))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + sail2_state_monad$returnS (((w__6.ProcState_EL = EL1))))))) + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) ((IsSecondStage fault))) + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 37 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((IsExternalAbort__1 fault))))) (\ (route_to_el2 : + bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (AArch64_AbortSyndrome Exception_DataAbort fault vaddress) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$returnS (((w__17.ProcState_EL = EL3))))) + (sail2_state_monad$returnS route_to_el3)) (\ (w__18 : bool) . + if w__18 then AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__19 : ProcState) . sail2_state_monad$returnS (((w__19.ProcState_EL = EL2))))) + (sail2_state_monad$returnS route_to_el2)) (\ (w__20 : bool) . + if w__20 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`; + + +(*val AArch64_CheckForERetTrap : bool -> bool -> M unit*) + +val _ = Define ` + ((AArch64_CheckForERetTrap:bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) eret_with_pac pac_uses_key_a= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL1)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (vect_offset : ii) . + if route_to_el2 then sail2_state_monad$bindS + (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let vect_offset = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_ERetTrap) (\ (w__5 : ExceptionRecord) . + let exception = w__5 in + let (tmp_2550 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS + (ZeroExtend__0 (vec_of_bits [B0] : 1 words$word) ((make_the_value (( 23 : int):ii) : 23 itself)) + : ( 23 words$word) M) (\ (w__6 : 23 words$word) . + let tmp_2550 = ((set_slice (( 25 : int):ii) (( 23 : int):ii) tmp_2550 (( 2 : int):ii) w__6 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2550|>)) in + let (exception : ExceptionRecord) = + (if ((~ eret_with_pac)) then + let (tmp_2560 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (tmp_2560 : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2560 (( 1 : int):ii) (vec_of_bits [B0] : 1 words$word) : 25 words$word)) in + let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_syndrome := tmp_2560|>)) in + let (tmp_2570 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (tmp_2570 : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2570 (( 0 : int):ii) (vec_of_bits [B0] : 1 words$word) : 25 words$word)) in + (exception with<| ExceptionRecord_syndrome := tmp_2570|>) + else + let (tmp_2580 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (tmp_2580 : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2580 (( 1 : int):ii) (vec_of_bits [B1] : 1 words$word) : 25 words$word)) in + let (exception : ExceptionRecord) = ((exception with<| ExceptionRecord_syndrome := tmp_2580|>)) in + if pac_uses_key_a then + let (tmp_2590 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (tmp_2590 : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2590 (( 0 : int):ii) (vec_of_bits [B0] : 1 words$word) + : 25 words$word)) in + (exception with<| ExceptionRecord_syndrome := tmp_2590|>) + else + let (tmp_2600 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let (tmp_2600 : 25 bits) = + ((set_slice (( 25 : int):ii) (( 1 : int):ii) tmp_2600 (( 0 : int):ii) (vec_of_bits [B1] : 1 words$word) + : 25 words$word)) in + (exception with<| ExceptionRecord_syndrome := tmp_2600|>)) in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))) + else sail2_state_monad$returnS () ))))`; + + +(*val AArch64_CallSupervisor : mword ty16 -> M unit*) + +val _ = Define ` + ((AArch64_CallSupervisor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate= (sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if w__0 then AArch32_ITAdvance () + else sail2_state_monad$returnS () ) + (SSAdvance () )) + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL = EL0)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (NextInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_SupervisorCall) (\ (exception : ExceptionRecord) . + let (tmp_2770 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2770 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2770 (( 0 : int):ii) immediate : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2770|>)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + if ((((lem$w2ui w__6.ProcState_EL)) > ((lem$w2ui EL1)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . + AArch64_TakeException w__7.ProcState_EL exception preferred_exception_return vect_offset) + else if route_to_el2 then + AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset)))))))`; + + +(*val aarch64_system_exceptions_runtime_svc : mword ty16 -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_runtime_svc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm= (AArch64_CallSupervisor imm))`; + + +(*val system_exceptions_runtime_svc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_runtime_svc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (imm : 16 bits) = imm16 in + aarch64_system_exceptions_runtime_svc imm)))`; + + +(*val AArch64_CallSecureMonitor : mword ty16 -> M unit*) + +val _ = Define ` + ((AArch64_CallSecureMonitor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate= (sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL3) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__1 "(HaveEL(EL3) && !(ELUsingAArch32(EL3)))") + (UsingAArch32 () )) (\ (w__2 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if w__2 then AArch32_ITAdvance () + else sail2_state_monad$returnS () ) + (SSAdvance () )) + (NextInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_MonitorCall) (\ (exception : ExceptionRecord) . + let (tmp_2930 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2930 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2930 (( 0 : int):ii) immediate : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2930|>)) in + AArch64_TakeException EL3 exception preferred_exception_return vect_offset))))))`; + + +(*val AArch64_CallHypervisor : mword ty16 -> M unit*) + +val _ = Define ` + ((AArch64_CallHypervisor:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) immediate= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((HaveEL EL2)) "HaveEL(EL2)") + (UsingAArch32 () )) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if w__0 then AArch32_ITAdvance () + else sail2_state_monad$returnS () ) + (SSAdvance () )) + (NextInstrAddr (( 64 : int):ii) () : ( 64 words$word) M)) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_HypervisorCall) (\ (exception : ExceptionRecord) . + let (tmp_2890 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_2890 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_2890 (( 0 : int):ii) immediate : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2890|>)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + if (((w__1.ProcState_EL = EL3))) then + AArch64_TakeException EL3 exception preferred_exception_return vect_offset + else AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))))`; + + +(*val AArch64_BreakpointException : FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_BreakpointException:FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) fault= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((w__0.ProcState_EL <> EL3))) "((PSTATE).EL != EL3)") + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$returnS (((w__3.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + sail2_state_monad$returnS (((w__4.ProcState_EL = EL1))))))) + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDCR_EL2_ref : ( 32 words$word) M) (\ (w__8 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 8 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (vaddress : 64 bits) . sail2_state_monad$bindS + (AArch64_AbortSyndrome Exception_Breakpoint fault vaddress) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$returnS (((w__10.ProcState_EL = EL2))))) + (sail2_state_monad$returnS route_to_el2)) (\ (w__11 : bool) . + if w__11 then AArch64_TakeException EL2 exception preferred_exception_return vect_offset + else AArch64_TakeException EL1 exception preferred_exception_return vect_offset))))))))`; + + +(*val AArch64_Abort : mword ty64 -> FaultRecord -> M unit*) + +val _ = Define ` + ((AArch64_Abort:(64)words$word -> FaultRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress fault= (sail2_state_monad$bindS + (IsDebugException fault) (\ (w__0 : bool) . + if w__0 then + if (((fault.FaultRecord_acctype = AccType_IFETCH))) then sail2_state_monad$bindS + (sail2_state$and_boolS ((UsingAArch32 () )) + (sail2_state_monad$returnS (((fault.FaultRecord_debugmoe = DebugException_VectorCatch))))) (\ (w__2 : + bool) . + if w__2 then AArch64_VectorCatchException fault + else AArch64_BreakpointException fault) + else AArch64_WatchpointException vaddress fault + else if (((fault.FaultRecord_acctype = AccType_IFETCH))) then + AArch64_InstructionAbort vaddress fault + else AArch64_DataAbort vaddress fault)))`; + + +(*val AArch64_CheckAlignment : mword ty64 -> ii -> AccType -> bool -> M bool*) + +val _ = Define ` + ((AArch64_CheckAlignment:(64)words$word -> int -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address alignment acctype iswrite= + (let (aligned : bool) = (address = ((Align__1 address alignment : 64 words$word))) in + let (atomic : bool) = ((((acctype = AccType_ATOMIC))) \/ (((acctype = AccType_ATOMICRW)))) in + let (ordered : bool) = + ((((acctype = AccType_ORDERED))) \/ ((((((acctype = AccType_ORDEREDRW))) \/ (((acctype = AccType_LIMITEDORDERED))))))) in + let (vector_name : bool) = (acctype = AccType_VEC) in sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state_monad$returnS (((atomic \/ ordered)))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (check' : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$seqS + (if (((check' /\ ((~ aligned))))) then + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__1 : FaultRecord) . + AArch64_Abort address w__1) + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS aligned)))))`; + + +(*val AArch32_EnterMode : mword ty5 -> mword ty32 -> ii -> ii -> M unit*) + +val _ = Define ` + ((AArch32_EnterMode:(5)words$word ->(32)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_mode preferred_exception_return lr_offset vect_offset= + (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (sail2_state$and_boolS ((ELUsingAArch32 EL1)) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL <> EL2)))))) (\ (w__2 : + bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__2 "(ELUsingAArch32(EL1) && ((PSTATE).EL != EL2))") + (GetPSRFromPSTATE () : ( 32 words$word) M)) (\ (spsr : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((w__3.ProcState_M = M32_Monitor))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + sail2_state_monad$write_regS + SCR_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__4 (( 0 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) + else sail2_state_monad$returnS () ) + (AArch32_WriteMode target_mode)) + (aset_SPSR spsr)) + (aset_R (( 14 : int):ii) ((add_vec_int preferred_exception_return lr_offset : 32 words$word)))) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__5 with<| ProcState_T := ((vec_of_bits [access_vec_dec w__6 (( 30 : int):ii)] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + (if (((target_mode = M32_FIQ))) then + let split_vec = ((vec_of_bits [B1;B1;B1] : 3 words$word)) in + let (tup__0, tup__1, tup__2) = + ((subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_A := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_I := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_F := tup__2|>)))) + else if ((((((target_mode = M32_Abort))) \/ (((target_mode = M32_IRQ)))))) then + let split_vec = ((vec_of_bits [B1;B1] : 2 words$word)) in + let (tup__0, tup__1) = + ((subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_A := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_I := tup__1|>))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__13 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_I := ((vec_of_bits [B1] : 1 words$word))|>)))) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__14 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__15 (( 25 : int):ii)] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_IL := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__17 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + (sail2_state$and_boolS (sail2_state_monad$returnS ((HavePANExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_ref : ( 32 words$word) M) (\ (w__18 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 23 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__19 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__19 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__20 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_PAN := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (ExcVectorBase () : ( 32 words$word) M)) (\ (w__21 : 32 words$word) . sail2_state_monad$seqS + (BranchTo + ((concat_vec ((slice w__21 (( 5 : int):ii) (( 27 : int):ii) : 27 words$word)) + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) vect_offset (( 0 : int):ii) : 5 words$word)) + : 32 words$word)) BranchType_UNKNOWN) + (EndOfInstruction () )))))))))))))))`; + + +(*val AArch64_AdvSIMDFPAccessTrap : mword ty2 -> M unit*) + +val _ = Define ` + ((AArch64_AdvSIMDFPAccessTrap:(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) target_el= (sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let (vect_offset : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((((((target_el = EL1))) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . + if route_to_el2 then sail2_state_monad$bindS + (ExceptionSyndrome Exception_Uncategorized) (\ (w__3 : ExceptionRecord) . + let exception = w__3 in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset) + else sail2_state_monad$bindS + (ExceptionSyndrome Exception_AdvSIMDFPAccessTrap) (\ (w__4 : ExceptionRecord) . + let exception = w__4 in + let (tmp_2610 : 25 bits) = (exception.ExceptionRecord_syndrome) in sail2_state_monad$bindS + (ConditionSyndrome () : ( 5 words$word) M) (\ (w__5 : 5 words$word) . + let tmp_2610 = ((set_slice (( 25 : int):ii) (( 5 : int):ii) tmp_2610 (( 20 : int):ii) w__5 : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_2610|>)) in + AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))`; + + +(*val AArch64_CheckFPAdvSIMDTrap : unit -> M unit*) + +val _ = Define ` + ((AArch64_CheckFPAdvSIMDTrap:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (disabled : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : + bool) . sail2_state_monad$seqS + (if w__1 then sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveVirtHostExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 34 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__3 : bool) . + if w__3 then sail2_state_monad$bindS + (sail2_state_monad$read_regS CPTR_EL2_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + let p__283 = ((slice w__4 (( 20 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let v__94 = p__283 in sail2_state_monad$bindS + (if (((((subrange_vec_dec v__94 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . + sail2_state_monad$returnS (((w__5.ProcState_EL = EL1))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__7 : bool) . + let (disabled : bool) = (~ w__7) in + sail2_state_monad$returnS disabled) + else if (((v__94 = (vec_of_bits [B0;B1] : 2 words$word)))) then + sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + sail2_state_monad$returnS (((w__8.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__9 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__9 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + else sail2_state_monad$returnS F) (\ (disabled : bool) . + if disabled then AArch64_AdvSIMDFPAccessTrap EL2 + else sail2_state_monad$returnS () )) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CPTR_EL2_ref : ( 32 words$word) M) (\ (w__11 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__11 (( 10 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + AArch64_AdvSIMDFPAccessTrap EL2 + else sail2_state_monad$returnS () )) + else sail2_state_monad$returnS () ) + (if ((HaveEL EL3)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CPTR_EL3_ref : ( 32 words$word) M) (\ (w__12 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__12 (( 10 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + AArch64_AdvSIMDFPAccessTrap EL3 + else sail2_state_monad$returnS () ) + else sail2_state_monad$returnS () )))))`; + + +(*val AArch64_CheckFPAdvSIMDEnabled : unit -> M unit*) + +val _ = Define ` + ((AArch64_CheckFPAdvSIMDEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (disabled : bool) . sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL = EL1)))))) (\ (w__2 : + bool) . sail2_state_monad$seqS + (if w__2 then sail2_state_monad$bindS + (aget_CPACR () : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + let p__282 = ((slice w__3 (( 20 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let v__96 = p__282 in sail2_state_monad$bindS + (if (((((subrange_vec_dec v__96 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then + sail2_state_monad$returnS T + else if (((v__96 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . + let (disabled : bool) = (w__4.ProcState_EL = EL0) in + sail2_state_monad$returnS disabled) + else sail2_state_monad$returnS F) (\ (disabled : bool) . + if disabled then AArch64_AdvSIMDFPAccessTrap EL1 + else sail2_state_monad$returnS () )) + else sail2_state_monad$returnS () ) + (AArch64_CheckFPAdvSIMDTrap () )))))`; + + +(*val CheckFPAdvSIMDEnabled64 : unit -> M unit*) + +val _ = Define ` + ((CheckFPAdvSIMDEnabled64:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (AArch64_CheckFPAdvSIMDEnabled () ))`; + + +(*val aarch64_float_move_fp_select : mword ty4 -> ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_float_move_fp_select:(4)words$word -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition d l__133 m n= + (if (((l__133 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (ConditionHolds condition)) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then (aget_V (( 8 : int):ii) n : ( 8 words$word) M) + else (aget_V (( 8 : int):ii) m : ( 8 words$word) M)) (\ (result : 8 bits) . + aset_V d result)) + else if (((l__133 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (ConditionHolds condition)) (\ (w__3 : bool) . sail2_state_monad$bindS + (if w__3 then (aget_V (( 16 : int):ii) n : ( 16 words$word) M) + else (aget_V (( 16 : int):ii) m : ( 16 words$word) M)) (\ (result : 16 bits) . + aset_V d result)) + else if (((l__133 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (ConditionHolds condition)) (\ (w__6 : bool) . sail2_state_monad$bindS + (if w__6 then (aget_V (( 32 : int):ii) n : ( 32 words$word) M) + else (aget_V (( 32 : int):ii) m : ( 32 words$word) M)) (\ (result : 32 bits) . + aset_V d result)) + else if (((l__133 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (ConditionHolds condition)) (\ (w__9 : bool) . sail2_state_monad$bindS + (if w__9 then (aget_V (( 64 : int):ii) n : ( 64 words$word) M) + else (aget_V (( 64 : int):ii) m : ( 64 words$word) M)) (\ (result : 64 bits) . + aset_V d result)) + else if (((l__133 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (ConditionHolds condition)) (\ (w__12 : bool) . sail2_state_monad$bindS + (if w__12 then (aget_V (( 128 : int):ii) n : ( 128 words$word) M) + else (aget_V (( 128 : int):ii) m : ( 128 words$word) M)) (\ (result : 128 bits) . + aset_V d result)) + else + let dbytes = (ex_int ((l__133 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_move_fp_imm : forall 'datasize. Size 'datasize => ii -> itself 'datasize -> mword 'datasize -> M unit*) + +val _ = Define ` + ((aarch64_float_move_fp_imm:int -> 'datasize itself -> 'datasize words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d datasize imm= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) (CheckFPAdvSIMDEnabled64 () )) (aset_V d imm)))`; + + +(*val aarch64_float_convert_int : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> itself 'intsize -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_convert_int:int -> 'fltsize itself -> 'intsize itself -> int -> FPConvOp -> int -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d fltsize intsize n op part rounding unsigned= + (let intsize = (size_itself_int intsize) in + let fltsize = (size_itself_int fltsize) in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector fltsize : ( 'fltsize words$word) M)) (\ (fltval : 'fltsize bits) . sail2_state_monad$bindS + (undefined_bitvector intsize : ( 'intsize words$word) M) (\ (intval : 'intsize bits) . + (case op of + FPConvOp_CVT_FtoI => sail2_state_monad$bindS + (aget_V fltsize n : ( 'fltsize words$word) M) (\ (w__0 : 'fltsize bits) . + let fltval = w__0 in sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . sail2_state_monad$bindS + (FPToFixed intsize fltval (( 0 : int):ii) unsigned w__1 rounding : ( 'intsize words$word) M) (\ (w__2 : 'intsize + bits) . + let intval = w__2 in + aset_X d intval))) + | FPConvOp_CVT_ItoF => sail2_state_monad$bindS + (aget_X intsize n : ( 'intsize words$word) M) (\ (w__3 : 'intsize bits) . + let intval = w__3 in sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS + (FixedToFP fltsize intval (( 0 : int):ii) unsigned w__4 rounding : ( 'fltsize words$word) M) (\ (w__5 : 'fltsize + bits) . + let fltval = w__5 in + aset_V d fltval))) + | FPConvOp_MOV_FtoI => sail2_state_monad$bindS + (aget_Vpart fltsize n part : ( 'fltsize words$word) M) (\ (w__6 : 'fltsize bits) . + let fltval = w__6 in sail2_state_monad$bindS + (ZeroExtend__0 fltval ((make_the_value intsize : 'intsize itself)) : ( 'intsize words$word) M) (\ (w__7 : 'intsize + bits) . + let intval = w__7 in + aset_X d intval)) + | FPConvOp_MOV_ItoF => sail2_state_monad$bindS + (aget_X intsize n : ( 'intsize words$word) M) (\ (w__8 : 'intsize bits) . + let intval = w__8 in + let fltval = ((slice intval (( 0 : int):ii) fltsize : 'fltsize words$word)) in + aset_Vpart d part fltval) + | FPConvOp_CVT_FtoI_JS => sail2_state_monad$bindS + (aget_V fltsize n : ( 'fltsize words$word) M) (\ (w__9 : 'fltsize bits) . + let fltval = w__9 in sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . sail2_state_monad$bindS + (FPToFixedJS intsize fltval w__10 T : ( 'intsize words$word) M) (\ (w__11 : 'intsize bits) . + let intval = w__11 in sail2_state_monad$bindS + (ZeroExtend__0 ((slice intval (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__12 : 64 words$word) . + aset_X d w__12)))) + )))))`; + + +(*val aarch64_float_convert_fp : forall 'dstsize 'srcsize . Size 'dstsize, Size 'srcsize => ii -> itself 'dstsize -> ii -> itself 'srcsize -> M unit*) + +val _ = Define ` + ((aarch64_float_convert_fp:int -> 'dstsize itself -> int -> 'srcsize itself ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d dstsize n srcsize= + (let srcsize = (size_itself_int srcsize) in + let dstsize = (size_itself_int dstsize) in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector dstsize : ( 'dstsize words$word) M)) (\ (result : 'dstsize bits) . sail2_state_monad$bindS + (aget_V srcsize n : ( 'srcsize words$word) M) (\ (operand : 'srcsize bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS + (FPConvert__1 dstsize operand w__0 : ( 'dstsize words$word) M) (\ (w__1 : 'dstsize bits) . + let result = w__1 in + aset_V d result))))))`; + + +(*val aarch64_float_convert_fix : forall 'fltsize 'intsize . Size 'fltsize, Size 'intsize => ii -> itself 'fltsize -> ii -> itself 'intsize -> ii -> FPConvOp -> FPRounding -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_convert_fix:int -> 'fltsize itself -> int -> 'intsize itself -> int -> FPConvOp -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d fltsize fracbits intsize n op rounding unsigned= + (let intsize = (size_itself_int intsize) in + let fltsize = (size_itself_int fltsize) in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector fltsize : ( 'fltsize words$word) M)) (\ (fltval : 'fltsize bits) . sail2_state_monad$bindS + (undefined_bitvector intsize : ( 'intsize words$word) M) (\ (intval : 'intsize bits) . + (case op of + FPConvOp_CVT_FtoI => sail2_state_monad$bindS + (aget_V fltsize n : ( 'fltsize words$word) M) (\ (w__0 : 'fltsize bits) . + let fltval = w__0 in sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . sail2_state_monad$bindS + (FPToFixed intsize fltval fracbits unsigned w__1 rounding : ( 'intsize words$word) M) (\ (w__2 : 'intsize + bits) . + let intval = w__2 in + aset_X d intval))) + | FPConvOp_CVT_ItoF => sail2_state_monad$bindS + (aget_X intsize n : ( 'intsize words$word) M) (\ (w__3 : 'intsize bits) . + let intval = w__3 in sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS + (FixedToFP fltsize intval fracbits unsigned w__4 rounding : ( 'fltsize words$word) M) (\ (w__5 : 'fltsize + bits) . + let fltval = w__5 in + aset_V d fltval))) + )))))`; + + +(*val aarch64_float_compare_uncond : bool -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_compare_uncond:bool -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cmp_with_zero l__128 m n signal_all_nans= + (if (((l__128 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (aget_V (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (if cmp_with_zero then (FPZero (( 8 : int):ii) (vec_of_bits [B0] : 1 words$word) : ( 8 words$word) M) + else (aget_V (( 8 : int):ii) m : ( 8 words$word) M)) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS + (FPCompare operand1 operand2 signal_all_nans w__2 : ( 4 words$word) M) (\ split_vec . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_V := tup__3|>))))))))) + else if (((l__128 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (aget_V (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (if cmp_with_zero then (FPZero (( 16 : int):ii) (vec_of_bits [B0] : 1 words$word) : ( 16 words$word) M) + else (aget_V (( 16 : int):ii) m : ( 16 words$word) M)) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . sail2_state_monad$bindS + (FPCompare operand1 operand2 signal_all_nans w__9 : ( 4 words$word) M) (\ split_vec . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_V := tup__3|>))))))))) + else if (((l__128 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (aget_V (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (if cmp_with_zero then (FPZero (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : ( 32 words$word) M) + else (aget_V (( 32 : int):ii) m : ( 32 words$word) M)) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__16 : 32 words$word) . sail2_state_monad$bindS + (FPCompare operand1 operand2 signal_all_nans w__16 : ( 4 words$word) M) (\ split_vec . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_V := tup__3|>))))))))) + else if (((l__128 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (aget_V (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (if cmp_with_zero then (FPZero (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : ( 64 words$word) M) + else (aget_V (( 64 : int):ii) m : ( 64 words$word) M)) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__23 : 32 words$word) . sail2_state_monad$bindS + (FPCompare operand1 operand2 signal_all_nans w__23 : ( 4 words$word) M) (\ split_vec . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_V := tup__3|>))))))))) + else if (((l__128 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (aget_V (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (if cmp_with_zero then (FPZero (( 128 : int):ii) (vec_of_bits [B0] : 1 words$word) : ( 128 words$word) M) + else (aget_V (( 128 : int):ii) m : ( 128 words$word) M)) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__30 : 32 words$word) . sail2_state_monad$bindS + (FPCompare operand1 operand2 signal_all_nans w__30 : ( 4 words$word) M) (\ split_vec . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__32 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__32 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__33 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__33 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__34 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__34 with<| ProcState_V := tup__3|>))))))))) + else + let dbytes = (ex_int ((l__128 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_compare_cond : mword ty4 -> ii -> mword ty4 -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_compare_cond:(4)words$word -> int ->(4)words$word -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) condition l__123 flags__arg m n signal_all_nans= + (if (((l__123 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_V (( 8 : int):ii) n : ( 8 words$word) M)) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + (FPCompare operand1 operand2 signal_all_nans w__1 : ( 4 words$word) M)) + else sail2_state_monad$returnS flags) (\ (flags : 4 words$word) . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__4 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__123 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_V (( 16 : int):ii) n : ( 16 words$word) M)) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__7 : bool) . sail2_state_monad$bindS + (if w__7 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . + (FPCompare operand1 operand2 signal_all_nans w__8 : ( 4 words$word) M)) + else sail2_state_monad$returnS flags) (\ (flags : 4 words$word) . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__123 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_V (( 32 : int):ii) n : ( 32 words$word) M)) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__14 : bool) . sail2_state_monad$bindS + (if w__14 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__15 : 32 words$word) . + (FPCompare operand1 operand2 signal_all_nans w__15 : ( 4 words$word) M)) + else sail2_state_monad$returnS flags) (\ (flags : 4 words$word) . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__17 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__19 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__123 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_V (( 64 : int):ii) n : ( 64 words$word) M)) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__21 : bool) . sail2_state_monad$bindS + (if w__21 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__22 : 32 words$word) . + (FPCompare operand1 operand2 signal_all_nans w__22 : ( 4 words$word) M)) + else sail2_state_monad$returnS flags) (\ (flags : 4 words$word) . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__24 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_V := tup__3|>)))))))))) + else if (((l__123 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let flags = flags__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_V (( 128 : int):ii) n : ( 128 words$word) M)) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (ConditionHolds condition) (\ (w__28 : bool) . sail2_state_monad$bindS + (if w__28 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__29 : 32 words$word) . + (FPCompare operand1 operand2 signal_all_nans w__29 : ( 4 words$word) M)) + else sail2_state_monad$returnS flags) (\ (flags : 4 words$word) . + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec flags (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec flags (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__31 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__32 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__32 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__33 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__33 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__34 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__34 with<| ProcState_V := tup__3|>)))))))))) + else + let dbytes = (ex_int ((l__123 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_unary : ii -> ii -> FPUnaryOp -> ii -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_unary:int -> int -> FPUnaryOp -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__118 fpop n= + (if (((l__118 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand : 8 bits) . sail2_state_monad$bindS + (case fpop of + FPUnaryOp_MOV => sail2_state_monad$returnS operand + | FPUnaryOp_ABS => (FPAbs operand : ( 8 words$word) M) + | FPUnaryOp_NEG => (FPNeg operand : ( 8 words$word) M) + | FPUnaryOp_SQRT => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + (FPSqrt operand w__2 : ( 8 words$word) M)) + ) (\ (result : 8 bits) . + aset_V d result))) + else if (((l__118 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand : 16 bits) . sail2_state_monad$bindS + (case fpop of + FPUnaryOp_MOV => sail2_state_monad$returnS operand + | FPUnaryOp_ABS => (FPAbs operand : ( 16 words$word) M) + | FPUnaryOp_NEG => (FPNeg operand : ( 16 words$word) M) + | FPUnaryOp_SQRT => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + (FPSqrt operand w__6 : ( 16 words$word) M)) + ) (\ (result : 16 bits) . + aset_V d result))) + else if (((l__118 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand : 32 bits) . sail2_state_monad$bindS + (case fpop of + FPUnaryOp_MOV => sail2_state_monad$returnS operand + | FPUnaryOp_ABS => (FPAbs operand : ( 32 words$word) M) + | FPUnaryOp_NEG => (FPNeg operand : ( 32 words$word) M) + | FPUnaryOp_SQRT => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + (FPSqrt operand w__10 : ( 32 words$word) M)) + ) (\ (result : 32 bits) . + aset_V d result))) + else if (((l__118 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand : 64 bits) . sail2_state_monad$bindS + (case fpop of + FPUnaryOp_MOV => sail2_state_monad$returnS operand + | FPUnaryOp_ABS => (FPAbs operand : ( 64 words$word) M) + | FPUnaryOp_NEG => (FPNeg operand : ( 64 words$word) M) + | FPUnaryOp_SQRT => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__14 : 32 words$word) . + (FPSqrt operand w__14 : ( 64 words$word) M)) + ) (\ (result : 64 bits) . + aset_V d result))) + else if (((l__118 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand : 128 bits) . sail2_state_monad$bindS + (case fpop of + FPUnaryOp_MOV => sail2_state_monad$returnS operand + | FPUnaryOp_ABS => (FPAbs operand : ( 128 words$word) M) + | FPUnaryOp_NEG => (FPNeg operand : ( 128 words$word) M) + | FPUnaryOp_SQRT => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . + (FPSqrt operand w__18 : ( 128 words$word) M)) + ) (\ (result : 128 bits) . + aset_V d result))) + else + let dbytes = (ex_int ((l__118 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_round : ii -> ii -> bool -> ii -> FPRounding -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_round:int -> int -> bool -> int -> FPRounding ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__113 exact n rounding= + (if (((l__113 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS + (FPRoundInt operand w__0 rounding exact : ( 8 words$word) M) (\ (w__1 : 8 bits) . + let result = w__1 in + aset_V d result)))) + else if (((l__113 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand : 16 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS + (FPRoundInt operand w__2 rounding exact : ( 16 words$word) M) (\ (w__3 : 16 bits) . + let result = w__3 in + aset_V d result)))) + else if (((l__113 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS + (FPRoundInt operand w__4 rounding exact : ( 32 words$word) M) (\ (w__5 : 32 bits) . + let result = w__5 in + aset_V d result)))) + else if (((l__113 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS + (FPRoundInt operand w__6 rounding exact : ( 64 words$word) M) (\ (w__7 : 64 bits) . + let result = w__7 in + aset_V d result)))) + else if (((l__113 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand : 128 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . sail2_state_monad$bindS + (FPRoundInt operand w__8 rounding exact : ( 128 words$word) M) (\ (w__9 : 128 bits) . + let result = w__9 in + aset_V d result)))) + else + let dbytes = (ex_int ((l__113 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_mul_product : ii -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_mul_product:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__108 m n negated= + (if (((l__108 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS + (FPMul operand1 operand2 w__0 : ( 8 words$word) M) (\ (w__1 : 8 bits) . + let result = w__1 in sail2_state_monad$bindS + (if negated then (FPNeg result : ( 8 words$word) M) + else sail2_state_monad$returnS result) (\ (result : 8 bits) . + aset_V d result)))))) + else if (((l__108 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__3 : 32 words$word) . sail2_state_monad$bindS + (FPMul operand1 operand2 w__3 : ( 16 words$word) M) (\ (w__4 : 16 bits) . + let result = w__4 in sail2_state_monad$bindS + (if negated then (FPNeg result : ( 16 words$word) M) + else sail2_state_monad$returnS result) (\ (result : 16 bits) . + aset_V d result)))))) + else if (((l__108 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS + (FPMul operand1 operand2 w__6 : ( 32 words$word) M) (\ (w__7 : 32 bits) . + let result = w__7 in sail2_state_monad$bindS + (if negated then (FPNeg result : ( 32 words$word) M) + else sail2_state_monad$returnS result) (\ (result : 32 bits) . + aset_V d result)))))) + else if (((l__108 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__9 : 32 words$word) . sail2_state_monad$bindS + (FPMul operand1 operand2 w__9 : ( 64 words$word) M) (\ (w__10 : 64 bits) . + let result = w__10 in sail2_state_monad$bindS + (if negated then (FPNeg result : ( 64 words$word) M) + else sail2_state_monad$returnS result) (\ (result : 64 bits) . + aset_V d result)))))) + else if (((l__108 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . sail2_state_monad$bindS + (FPMul operand1 operand2 w__12 : ( 128 words$word) M) (\ (w__13 : 128 bits) . + let result = w__13 in sail2_state_monad$bindS + (if negated then (FPNeg result : ( 128 words$word) M) + else sail2_state_monad$returnS result) (\ (result : 128 bits) . + aset_V d result)))))) + else + let dbytes = (ex_int ((l__108 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_mul_addsub : ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_mul_addsub:int -> int -> int -> int -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) a d l__103 m n op1_neg opa_neg= + (if (((l__103 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) a : ( 8 words$word) M) (\ (operanda : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (if opa_neg then (FPNeg operanda : ( 8 words$word) M) + else sail2_state_monad$returnS operanda) (\ (operanda : 8 bits) . sail2_state_monad$bindS + (if op1_neg then (FPNeg operand1 : ( 8 words$word) M) + else sail2_state_monad$returnS operand1) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS + (FPMulAdd operanda operand1 operand2 w__2 : ( 8 words$word) M) (\ (w__3 : 8 bits) . + let result = w__3 in + aset_V d result)))))))) + else if (((l__103 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) a : ( 16 words$word) M) (\ (operanda : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (if opa_neg then (FPNeg operanda : ( 16 words$word) M) + else sail2_state_monad$returnS operanda) (\ (operanda : 16 bits) . sail2_state_monad$bindS + (if op1_neg then (FPNeg operand1 : ( 16 words$word) M) + else sail2_state_monad$returnS operand1) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS + (FPMulAdd operanda operand1 operand2 w__6 : ( 16 words$word) M) (\ (w__7 : 16 bits) . + let result = w__7 in + aset_V d result)))))))) + else if (((l__103 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) a : ( 32 words$word) M) (\ (operanda : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (if opa_neg then (FPNeg operanda : ( 32 words$word) M) + else sail2_state_monad$returnS operanda) (\ (operanda : 32 bits) . sail2_state_monad$bindS + (if op1_neg then (FPNeg operand1 : ( 32 words$word) M) + else sail2_state_monad$returnS operand1) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . sail2_state_monad$bindS + (FPMulAdd operanda operand1 operand2 w__10 : ( 32 words$word) M) (\ (w__11 : 32 bits) . + let result = w__11 in + aset_V d result)))))))) + else if (((l__103 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) a : ( 64 words$word) M) (\ (operanda : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (if opa_neg then (FPNeg operanda : ( 64 words$word) M) + else sail2_state_monad$returnS operanda) (\ (operanda : 64 bits) . sail2_state_monad$bindS + (if op1_neg then (FPNeg operand1 : ( 64 words$word) M) + else sail2_state_monad$returnS operand1) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__14 : 32 words$word) . sail2_state_monad$bindS + (FPMulAdd operanda operand1 operand2 w__14 : ( 64 words$word) M) (\ (w__15 : 64 bits) . + let result = w__15 in + aset_V d result)))))))) + else if (((l__103 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) a : ( 128 words$word) M) (\ (operanda : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (if opa_neg then (FPNeg operanda : ( 128 words$word) M) + else sail2_state_monad$returnS operanda) (\ (operanda : 128 bits) . sail2_state_monad$bindS + (if op1_neg then (FPNeg operand1 : ( 128 words$word) M) + else sail2_state_monad$returnS operand1) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . sail2_state_monad$bindS + (FPMulAdd operanda operand1 operand2 w__18 : ( 128 words$word) M) (\ (w__19 : 128 bits) . + let result = w__19 in + aset_V d result)))))))) + else + let dbytes = (ex_int ((l__103 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_maxmin : ii -> ii -> ii -> ii -> FPMaxMinOp -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_maxmin:int -> int -> int -> int -> FPMaxMinOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__98 m n operation= + (if (((l__98 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (case operation of + FPMaxMinOp_MAX => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + (FPMax operand1 operand2 w__0 : ( 8 words$word) M)) + | FPMaxMinOp_MIN => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + (FPMin operand1 operand2 w__2 : ( 8 words$word) M)) + | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + (FPMaxNum operand1 operand2 w__4 : ( 8 words$word) M)) + | FPMaxMinOp_MINNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + (FPMinNum operand1 operand2 w__6 : ( 8 words$word) M)) + ) (\ (result : 8 bits) . + aset_V d result)))) + else if (((l__98 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (case operation of + FPMaxMinOp_MAX => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . + (FPMax operand1 operand2 w__8 : ( 16 words$word) M)) + | FPMaxMinOp_MIN => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + (FPMin operand1 operand2 w__10 : ( 16 words$word) M)) + | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . + (FPMaxNum operand1 operand2 w__12 : ( 16 words$word) M)) + | FPMaxMinOp_MINNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__14 : 32 words$word) . + (FPMinNum operand1 operand2 w__14 : ( 16 words$word) M)) + ) (\ (result : 16 bits) . + aset_V d result)))) + else if (((l__98 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (case operation of + FPMaxMinOp_MAX => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__16 : 32 words$word) . + (FPMax operand1 operand2 w__16 : ( 32 words$word) M)) + | FPMaxMinOp_MIN => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . + (FPMin operand1 operand2 w__18 : ( 32 words$word) M)) + | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__20 : 32 words$word) . + (FPMaxNum operand1 operand2 w__20 : ( 32 words$word) M)) + | FPMaxMinOp_MINNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__22 : 32 words$word) . + (FPMinNum operand1 operand2 w__22 : ( 32 words$word) M)) + ) (\ (result : 32 bits) . + aset_V d result)))) + else if (((l__98 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (case operation of + FPMaxMinOp_MAX => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__24 : 32 words$word) . + (FPMax operand1 operand2 w__24 : ( 64 words$word) M)) + | FPMaxMinOp_MIN => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__26 : 32 words$word) . + (FPMin operand1 operand2 w__26 : ( 64 words$word) M)) + | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__28 : 32 words$word) . + (FPMaxNum operand1 operand2 w__28 : ( 64 words$word) M)) + | FPMaxMinOp_MINNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__30 : 32 words$word) . + (FPMinNum operand1 operand2 w__30 : ( 64 words$word) M)) + ) (\ (result : 64 bits) . + aset_V d result)))) + else if (((l__98 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (case operation of + FPMaxMinOp_MAX => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__32 : 32 words$word) . + (FPMax operand1 operand2 w__32 : ( 128 words$word) M)) + | FPMaxMinOp_MIN => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__34 : 32 words$word) . + (FPMin operand1 operand2 w__34 : ( 128 words$word) M)) + | FPMaxMinOp_MAXNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__36 : 32 words$word) . + (FPMaxNum operand1 operand2 w__36 : ( 128 words$word) M)) + | FPMaxMinOp_MINNUM => sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__38 : 32 words$word) . + (FPMinNum operand1 operand2 w__38 : ( 128 words$word) M)) + ) (\ (result : 128 bits) . + aset_V d result)))) + else + let dbytes = (ex_int ((l__98 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_div : ii -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_div:int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__93 m n= + (if (((l__93 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . sail2_state_monad$bindS + (FPDiv operand1 operand2 w__0 : ( 8 words$word) M) (\ (w__1 : 8 bits) . + let result = w__1 in + aset_V d result))))) + else if (((l__93 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . sail2_state_monad$bindS + (FPDiv operand1 operand2 w__2 : ( 16 words$word) M) (\ (w__3 : 16 bits) . + let result = w__3 in + aset_V d result))))) + else if (((l__93 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS + (FPDiv operand1 operand2 w__4 : ( 32 words$word) M) (\ (w__5 : 32 bits) . + let result = w__5 in + aset_V d result))))) + else if (((l__93 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS + (FPDiv operand1 operand2 w__6 : ( 64 words$word) M) (\ (w__7 : 64 bits) . + let result = w__7 in + aset_V d result))))) + else if (((l__93 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . sail2_state_monad$bindS + (FPDiv operand1 operand2 w__8 : ( 128 words$word) M) (\ (w__9 : 128 bits) . + let result = w__9 in + aset_V d result))))) + else + let dbytes = (ex_int ((l__93 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_float_arithmetic_addsub : ii -> ii -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_arithmetic_addsub:int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__88 m n sub_op= + (if (((l__88 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M)) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) n : ( 8 words$word) M) (\ (operand1 : 8 bits) . sail2_state_monad$bindS + (aget_V (( 8 : int):ii) m : ( 8 words$word) M) (\ (operand2 : 8 bits) . sail2_state_monad$bindS + (if sub_op then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + (FPSub operand1 operand2 w__0 : ( 8 words$word) M)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + (FPAdd operand1 operand2 w__2 : ( 8 words$word) M))) (\ (result : 8 bits) . + aset_V d result)))) + else if (((l__88 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M)) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) n : ( 16 words$word) M) (\ (operand1 : 16 bits) . sail2_state_monad$bindS + (aget_V (( 16 : int):ii) m : ( 16 words$word) M) (\ (operand2 : 16 bits) . sail2_state_monad$bindS + (if sub_op then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + (FPSub operand1 operand2 w__4 : ( 16 words$word) M)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + (FPAdd operand1 operand2 w__6 : ( 16 words$word) M))) (\ (result : 16 bits) . + aset_V d result)))) + else if (((l__88 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) n : ( 32 words$word) M) (\ (operand1 : 32 bits) . sail2_state_monad$bindS + (aget_V (( 32 : int):ii) m : ( 32 words$word) M) (\ (operand2 : 32 bits) . sail2_state_monad$bindS + (if sub_op then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__8 : 32 words$word) . + (FPSub operand1 operand2 w__8 : ( 32 words$word) M)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + (FPAdd operand1 operand2 w__10 : ( 32 words$word) M))) (\ (result : 32 bits) . + aset_V d result)))) + else if (((l__88 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) n : ( 64 words$word) M) (\ (operand1 : 64 bits) . sail2_state_monad$bindS + (aget_V (( 64 : int):ii) m : ( 64 words$word) M) (\ (operand2 : 64 bits) . sail2_state_monad$bindS + (if sub_op then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__12 : 32 words$word) . + (FPSub operand1 operand2 w__12 : ( 64 words$word) M)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__14 : 32 words$word) . + (FPAdd operand1 operand2 w__14 : ( 64 words$word) M))) (\ (result : 64 bits) . + aset_V d result)))) + else if (((l__88 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) n : ( 128 words$word) M) (\ (operand1 : 128 bits) . sail2_state_monad$bindS + (aget_V (( 128 : int):ii) m : ( 128 words$word) M) (\ (operand2 : 128 bits) . sail2_state_monad$bindS + (if sub_op then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__16 : 32 words$word) . + (FPSub operand1 operand2 w__16 : ( 128 words$word) M)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__18 : 32 words$word) . + (FPAdd operand1 operand2 w__18 : ( 128 words$word) M))) (\ (result : 128 bits) . + aset_V d result)))) + else + let dbytes = (ex_int ((l__88 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val AArch64_AccessIsPrivileged : AccType -> M bool*) + +val _ = Define ` + ((AArch64_AccessIsPrivileged:AccType ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (ispriv : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . + if (((w__0.ProcState_EL = EL0))) then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . + if (((w__1.ProcState_EL = EL3))) then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL2))))) + (sail2_state$or_boolS ( sail2_state_monad$bindS(IsInHost () ) (\ (w__3 : bool) . sail2_state_monad$returnS ((~ w__3)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__6 : bool) . + if w__6 then sail2_state_monad$returnS T + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveUAOExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . + sail2_state_monad$returnS (((w__7.ProcState_UAO = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__8 : + bool) . + let (ispriv : bool) = (if w__8 then T else (acctype <> AccType_UNPRIV)) in + sail2_state_monad$returnS ispriv)))))))`; + + +(*val AArch64_CheckWatchpoint : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CheckWatchpoint:(64)words$word -> AccType -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite size1= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))") + (let (val_match : bool) = F in sail2_state_monad$bindS + (AArch64_AccessIsPrivileged acctype) (\ (ispriv : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS ID_AA64DFR0_EL1_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((lem$w2ui ((slice w__2 (( 20 : int):ii) (( 4 : int):ii) : 4 words$word)))) (( 1 : int):ii)) val_match + (\ i val_match . + sail2_state$or_boolS (sail2_state_monad$returnS val_match) ((AArch64_WatchpointMatch i vaddress size1 ispriv iswrite)))) (\ (val_match : + bool) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (reason : 6 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS val_match) ((HaltOnBreakpointOrWatchpoint () ))) (\ (w__6 : bool) . + if w__6 then + let reason = DebugHalt_Watchpoint in sail2_state_monad$seqS + (Halt reason) (undefined_FaultRecord () ) + else sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS val_match) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__8 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 15 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) ((AArch64_GenerateDebugExceptions () ))) (\ (w__11 : + bool) . + if w__11 then AArch64_DebugFault acctype iswrite + else AArch64_NoFault () )))))))))))`; + + +(*val AArch64_CheckDebug : mword ty64 -> AccType -> bool -> ii -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CheckDebug:(64)words$word -> AccType -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite size1= (sail2_state_monad$bindS + (AArch64_NoFault () ) (\ (fault : FaultRecord) . + let (d_side : bool) = (acctype <> AccType_IFETCH) in sail2_state_monad$bindS + (sail2_state$and_boolS ((AArch64_GenerateDebugExceptions () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 15 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (generate_exception : bool) . sail2_state_monad$bindS + (HaltOnBreakpointOrWatchpoint () ) (\ (halt : bool) . + if (((generate_exception \/ halt))) then + if d_side then AArch64_CheckWatchpoint vaddress acctype iswrite size1 + else AArch64_CheckBreakpoint vaddress size1 + else sail2_state_monad$returnS fault)))))`; + + +(*val AArch64_CheckPermission : Permissions -> mword ty64 -> ii -> mword ty1 -> AccType -> bool -> M FaultRecord*) + +val _ = Define ` + ((AArch64_CheckPermission:Permissions ->(64)words$word -> int ->(1)words$word -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((FaultRecord),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) perms vaddress level NS acctype iswrite= (sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__0 : 2 words$word) . sail2_state_monad$bindS + (ELUsingAArch32 w__0) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((~ w__1)) "!(ELUsingAArch32(S1TranslationRegime()))") + (aget_SCTLR__1 () : ( 32 words$word) M)) (\ (w__2 : 32 words$word) . + let (wxn : bool) = + ((vec_of_bits [access_vec_dec w__2 (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (xn : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (r : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (priv_xn : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (user_xn : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (pan : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (ispriv : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (user_w : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (user_r : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (priv_w : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (priv_r : bool) . sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$returnS (((w__4.ProcState_EL = EL1)))))) + ((IsInHost () ))) (\ (w__7 : bool) . sail2_state_monad$bindS + (if w__7 then + let priv_r = T in + let priv_w = + ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)) in + let user_r = + ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let user_w = + (((slice perms.Permissions_ap (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)) in sail2_state_monad$bindS + (AArch64_AccessIsPrivileged acctype) (\ (w__8 : bool) . + let ispriv = w__8 in sail2_state_monad$bindS + (if ((HavePANExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . sail2_state_monad$returnS w__9.ProcState_PAN) + else sail2_state_monad$returnS (vec_of_bits [B0] : 1 words$word)) (\ (w__10 : 1 words$word) . + let pan = w__10 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__11 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__11 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__13 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__15 : bool) . sail2_state_monad$returnS ((~ w__15))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$returnS (((w__17.ProcState_EL = EL1)))))) (\ (w__18 : + bool) . + let (pan : 1 bits) = (if w__18 then (vec_of_bits [B0] : 1 words$word) else pan) in sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS ((((((((((((pan = (vec_of_bits [B1] : 1 words$word)))) /\ user_r))) /\ ispriv))) /\ ((~ ((((((acctype = AccType_DC))) \/ ((((((acctype = AccType_AT))) \/ (((acctype = AccType_IFETCH))))))))))))))) + (sail2_state$and_boolS (sail2_state_monad$returnS (((acctype = AccType_AT)))) ((AArch64_ExecutingATS1xPInstr () )))) (\ (w__21 : + bool) . + let ((priv_r : bool), (priv_w : bool)) = + (if w__21 then + let (priv_r : bool) = F in + let (priv_w : bool) = F in + (priv_r, priv_w) + else (priv_r, priv_w)) in + let (user_xn : bool) = + ((((perms.Permissions_xn = (vec_of_bits [B1] : 1 words$word)))) \/ (((user_w /\ wxn)))) in + let (priv_xn : bool) = + (((((((perms.Permissions_pxn = (vec_of_bits [B1] : 1 words$word)))) \/ (((priv_w /\ wxn)))))) \/ user_w) in + let ((r : bool), (w : bool), (xn : bool)) = + (if ispriv then + let (tup__0, tup__1, tup__2) = (priv_r, priv_w, priv_xn) in + let (r : bool) = tup__0 in + let (w : bool) = tup__1 in + let (xn : bool) = tup__2 in + (r, w, xn) + else + let (tup__0, tup__1, tup__2) = (user_r, user_w, user_xn) in + let (r : bool) = tup__0 in + let (w : bool) = tup__1 in + let (xn : bool) = tup__2 in + (r, w, xn)) in + sail2_state_monad$returnS (r, w, xn))))) + else + let (r : bool) = T in + let (w : bool) = + ((vec_of_bits [access_vec_dec perms.Permissions_ap (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)) in + let (xn : bool) = + ((((perms.Permissions_xn = (vec_of_bits [B1] : 1 words$word)))) \/ (((w /\ wxn)))) in + sail2_state_monad$returnS (r, w, xn)) (\ varstup . let ((r : bool), (w : bool), (xn : bool)) = varstup in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL3))) ((IsSecure () ))) + (sail2_state_monad$returnS (((NS = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__25 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__25 (( 9 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__26 : bool) . + let (xn : bool) = (if w__26 then T else xn) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (failedread : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (fail1 : bool) . + let ((fail1 : bool), (failedread : bool)) = + (if (((acctype = AccType_IFETCH))) then + let (fail1 : bool) = xn in + let (failedread : bool) = T in + (fail1, failedread) + else + let ((fail1 : bool), (failedread : bool)) = + (if ((((((acctype = AccType_ATOMICRW))) \/ (((acctype = AccType_ORDEREDRW)))))) then + let (fail1 : bool) = (((~ r)) \/ ((~ w))) in + let (failedread : bool) = (~ r) in + (fail1, failedread) + else + let ((fail1 : bool), (failedread : bool)) = + (if iswrite then + let (fail1 : bool) = (~ w) in + let (failedread : bool) = F in + (fail1, failedread) + else + let (fail1 : bool) = (~ r) in + let (failedread : bool) = T in + (fail1, failedread)) in + (fail1, failedread)) in + (fail1, failedread)) in sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . + if fail1 then + let secondstage = F in + let s2fs1walk = F in sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (w__27 : 52 bits) . + let ipaddress = w__27 in + AArch64_PermissionFault ipaddress level acctype ((~ failedread)) secondstage s2fs1walk) + else AArch64_NoFault () ))))))))))))))))))))))))`; + + +(*val AArch64_FirstStageTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +val _ = Define ` + ((AArch64_FirstStageTranslate:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1= (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (s1_enabled : bool) . sail2_state_monad$bindS + (HasS2Translation () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then + sail2_state$and_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__1 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 12 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + else sail2_state_monad$bindS + (aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + let (s1_enabled : bool) = + ((vec_of_bits [access_vec_dec w__6 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS s1_enabled)) (\ (s1_enabled : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M) (\ (ipaddress : 52 bits) . + let (secondstage : bool) = F in + let (s2fs1walk : bool) = F in sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (nTLSMD : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (permissioncheck : bool) . sail2_state_monad$bindS + (undefined_TLBRecord () ) (\ (S1 : TLBRecord) . sail2_state_monad$bindS + (if s1_enabled then sail2_state_monad$bindS + (AArch64_TranslationTableWalk ipaddress vaddress acctype iswrite secondstage s2fs1walk size1) (\ (w__7 : + TLBRecord) . + let (S1 : TLBRecord) = w__7 in + let (permissioncheck : bool) = T in + sail2_state_monad$returnS (S1, permissioncheck)) + else sail2_state_monad$bindS + (AArch64_TranslateAddressS1Off vaddress acctype iswrite) (\ (w__8 : TLBRecord) . + let S1 = w__8 in + let permissioncheck = F in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state$and_boolS ((UsingAArch32 () )) (sail2_state_monad$returnS ((HaveTrapLoadStoreMultipleDeviceExt () )))) + ((AArch32_ExecutingLSMInstr () ))) (\ (w__12 : bool) . sail2_state_monad$bindS + (if w__12 then + if ((((((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_device <> DeviceType_GRE)))))) then sail2_state_monad$bindS + (S1TranslationRegime__1 () : ( 2 words$word) M) (\ (w__13 : 2 words$word) . sail2_state_monad$bindS + (if (((w__13 = EL2))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL2_ref : ( 32 words$word) M) (\ (w__14 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__14 (( 28 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__15 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__15 (( 28 : int):ii)] : 1 words$word))) (\ (w__16 : + 1 words$word) . + let nTLSMD = w__16 in + if (((nTLSMD = (vec_of_bits [B0] : 1 words$word)))) then + let (tmp_2460 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__17 : FaultRecord) . + let (tmp_2460 : AddressDescriptor) = + ((tmp_2460 with<| AddressDescriptor_fault := w__17|>)) in + let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2460|>)) in + sail2_state_monad$returnS S1) + else sail2_state_monad$returnS S1)) + else sail2_state_monad$returnS S1 + else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . + sail2_state_monad$returnS (S1, permissioncheck))))) (\ varstup . let ((S1 : TLBRecord), (permissioncheck : + bool)) = varstup in sail2_state_monad$bindS + (if ((((((((((((((~ wasaligned)) /\ (((acctype <> AccType_IFETCH)))))) \/ (((acctype = AccType_DCZVA)))))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ ((~ ((IsFault S1.TLBRecord_addrdesc))))))) then + let (tmp_2470 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__18 : FaultRecord) . + let (tmp_2470 : AddressDescriptor) = ((tmp_2470 with<| AddressDescriptor_fault := w__18|>)) in + let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2470|>)) in + sail2_state_monad$returnS S1) + else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . sail2_state_monad$bindS + (if (((((~ ((IsFault S1.TLBRecord_addrdesc)))) /\ permissioncheck))) then + let (tmp_2480 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_CheckPermission S1.TLBRecord_perms vaddress S1.TLBRecord_level + S1.TLBRecord_addrdesc.AddressDescriptor_paddress.FullAddress_NS acctype iswrite) (\ (w__19 : + FaultRecord) . + let (tmp_2480 : AddressDescriptor) = ((tmp_2480 with<| AddressDescriptor_fault := w__19|>)) in + let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2480|>)) in + sail2_state_monad$returnS S1) + else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . sail2_state_monad$bindS + (if ((((((((~ ((IsFault S1.TLBRecord_addrdesc)))) /\ (((S1.TLBRecord_addrdesc.AddressDescriptor_memattrs.MemoryAttributes_typ = MemType_Device)))))) /\ (((acctype = AccType_IFETCH)))))) then sail2_state_monad$bindS + (AArch64_InstructionDevice S1.TLBRecord_addrdesc vaddress ipaddress S1.TLBRecord_level acctype + iswrite secondstage s2fs1walk) (\ (w__20 : AddressDescriptor) . + let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := w__20|>)) in + sail2_state_monad$returnS S1) + else sail2_state_monad$returnS S1) (\ (S1 : TLBRecord) . + let (hwupdatewalk : bool) = F in + let s2fs1walk = F in + let (tmp_2490 : AddressDescriptor) = (S1.TLBRecord_addrdesc) in sail2_state_monad$bindS + (AArch64_CheckAndUpdateDescriptor S1.TLBRecord_descupdate + S1.TLBRecord_addrdesc.AddressDescriptor_fault secondstage vaddress acctype iswrite s2fs1walk + hwupdatewalk) (\ (w__21 : FaultRecord) . + let (tmp_2490 : AddressDescriptor) = ((tmp_2490 with<| AddressDescriptor_fault := w__21|>)) in + let (S1 : TLBRecord) = ((S1 with<| TLBRecord_addrdesc := tmp_2490|>)) in + sail2_state_monad$returnS S1.TLBRecord_addrdesc))))))))))))))`; + + +(*val AArch64_FullTranslate : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +val _ = Define ` + ((AArch64_FullTranslate:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1= (sail2_state_monad$bindS + (AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size1) (\ (S1 : + AddressDescriptor) . sail2_state_monad$bindS + (undefined_AddressDescriptor () ) (\ (result : AddressDescriptor) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (hwupdatewalk : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (s2fs1walk : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((IsFault S1))))) ((HasS2Translation () ))) (\ (w__1 : bool) . + if w__1 then + let s2fs1walk = F in + let hwupdatewalk = F in + AArch64_SecondStageTranslate S1 vaddress acctype iswrite wasaligned s2fs1walk size1 hwupdatewalk + else sail2_state_monad$returnS S1)))))))`; + + +(*val AArch64_TranslateAddress : mword ty64 -> AccType -> bool -> bool -> ii -> M AddressDescriptor*) + +val _ = Define ` + ((AArch64_TranslateAddress:(64)words$word -> AccType -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((AddressDescriptor),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddress acctype iswrite wasaligned size1= (sail2_state_monad$bindS + (AArch64_FullTranslate vaddress acctype iswrite wasaligned size1) (\ (result : + AddressDescriptor) . sail2_state_monad$bindS + (if (((((~ ((((((acctype = AccType_PTW))) \/ ((((((acctype = AccType_IC))) \/ (((acctype = AccType_AT))))))))))) /\ ((~ ((IsFault result))))))) then sail2_state_monad$bindS + (AArch64_CheckDebug vaddress acctype iswrite size1) (\ (w__0 : FaultRecord) . + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_fault := w__0|>)) in + sail2_state_monad$returnS result) + else sail2_state_monad$returnS result) (\ (result : AddressDescriptor) . sail2_state_monad$bindS + (ZeroExtend__1 (( 64 : int):ii) vaddress : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let (result : AddressDescriptor) = ((result with<| AddressDescriptor_vaddress := w__1|>)) in + sail2_state_monad$returnS result)))))`; + + +(*val AArch64_aset_MemSingle : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> mword 'p8_times_size_ -> M unit*) + +val _ = Define ` + ((AArch64_aset_MemSingle:(64)words$word -> int -> AccType -> bool -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype wasaligned value_name= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))") + (sail2_state_monad$assert_expS (((address = ((Align__1 address size1 : 64 words$word))))) "(address == Align(address, size))")) + (undefined_AddressDescriptor () )) (\ (memaddrdesc : AddressDescriptor) . + let (iswrite : bool) = T in sail2_state_monad$bindS + (AArch64_TranslateAddress address acctype iswrite wasaligned size1) (\ (w__0 : + AddressDescriptor) . + let memaddrdesc = w__0 in sail2_state_monad$seqS + (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault + else sail2_state_monad$returnS () ) + (let (_ : unit) = + (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then + ClearExclusiveByAddress memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1 + else () ) in sail2_state_monad$bindS + (CreateAccessDescriptor acctype) (\ (accdesc : AccessDescriptor) . + aset__Mem memaddrdesc size1 accdesc value_name))))))`; + + +(*val aset_Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> mword 'p8_times_size_ -> M unit*) + +val _ = Define ` + ((aset_Mem:(64)words$word -> int -> AccType -> 'p8_times_size_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype value_name__arg= + (let value_name = value_name__arg in sail2_state_monad$bindS + (undefined_int () ) (\ (i : ii) . + let (iswrite : bool) = T in sail2_state_monad$bindS + (BigEndian () ) (\ (w__0 : bool) . sail2_state_monad$bindS + (if w__0 then (BigEndianReverse value_name : ( 'p8_times_size_ words$word) M) + else sail2_state_monad$returnS value_name) (\ value_name . sail2_state_monad$bindS + (AArch64_CheckAlignment address size1 acctype iswrite) (\ (aligned : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (atomic : bool) . + let (atomic : bool) = + (if ((((((size1 <> (( 16 : int):ii)))) \/ ((~ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))))) then + aligned + else (address = ((Align__1 address (( 8 : int):ii) : 64 words$word)))) in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . + if ((~ atomic)) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((size1 > (( 1 : int):ii))) "(size > 1)") + (AArch64_aset_MemSingle address (( 1 : int):ii) acctype aligned + ((slice value_name (( 0 : int):ii) (( 8 : int):ii) : 8 words$word)))) + (if ((~ aligned)) then + let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_FAULT))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FAULT) || (c == Constraint_NONE))") + (let (aligned : bool) = (if (((c = Constraint_NONE))) then T else aligned) in + sail2_state_monad$returnS aligned) + else sail2_state_monad$returnS aligned)) (\ (aligned : bool) . + (sail2_state$foreachS (index_list (( 1 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) () + (\ i unit_var . + AArch64_aset_MemSingle ((add_vec_int address i : 64 words$word)) (( 1 : int):ii) acctype aligned + ((slice value_name (((( 8 : int):ii) * i)) (( 8 : int):ii) : 8 words$word))))) + else if ((((((size1 = (( 16 : int):ii)))) /\ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))) then sail2_state_monad$seqS + (AArch64_aset_MemSingle address (( 8 : int):ii) acctype aligned + ((slice value_name (( 0 : int):ii) (( 64 : int):ii) : 64 words$word))) + (AArch64_aset_MemSingle ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype aligned + ((slice value_name (( 64 : int):ii) (( 64 : int):ii) : 64 words$word))) + else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))`; + + +(*val AArch64_aget_MemSingle : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> bool -> M (mword 'p8_times_size_)*) + +val _ = Define ` + ((AArch64_aget_MemSingle:(64)words$word -> int -> AccType -> bool ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype wasaligned= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))") + (sail2_state_monad$assert_expS (((address = ((Align__1 address size1 : 64 words$word))))) "(address == Align(address, size))")) + (undefined_AddressDescriptor () )) (\ (memaddrdesc : AddressDescriptor) . sail2_state_monad$bindS + (undefined_bitvector (((( 8 : int):ii) * size1)) : ( 'p8_times_size_ words$word) M) (\ value_name . + let (iswrite : bool) = F in sail2_state_monad$bindS + (AArch64_TranslateAddress address acctype iswrite wasaligned size1) (\ (w__0 : + AddressDescriptor) . + let memaddrdesc = w__0 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault + else sail2_state_monad$returnS () ) + (CreateAccessDescriptor acctype)) (\ (accdesc : AccessDescriptor) . + (aget__Mem memaddrdesc size1 accdesc : ( 'p8_times_size_ words$word) M)))))))`; + + +(*val aget_Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => mword ty64 -> integer -> AccType -> M (mword 'p8_times_size_)*) + +val _ = Define ` + ((aget_Mem:(64)words$word -> int -> AccType ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_size_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1 acctype= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((size1 = (( 1 : int):ii)))) \/ ((((((size1 = (( 2 : int):ii)))) \/ ((((((size1 = (( 4 : int):ii)))) \/ ((((((size1 = (( 8 : int):ii)))) \/ (((size1 = (( 16 : int):ii)))))))))))))))) "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))") + (undefined_bitvector (((( 8 : int):ii) * size1)) : ( 'p8_times_size_ words$word) M)) (\ value_name . sail2_state_monad$bindS + (undefined_int () ) (\ (i : ii) . + let (iswrite : bool) = F in sail2_state_monad$bindS + (AArch64_CheckAlignment address size1 acctype iswrite) (\ (aligned : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (atomic : bool) . + let (atomic : bool) = + (if ((((((size1 <> (( 16 : int):ii)))) \/ ((~ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))))) then + aligned + else (address = ((Align__1 address (( 8 : int):ii) : 64 words$word)))) in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((~ atomic)) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((size1 > (( 1 : int):ii))) "(size > 1)") + (AArch64_aget_MemSingle address (( 1 : int):ii) acctype aligned : ( 8 words$word) M)) (\ (w__0 : + 8 words$word) . + let value_name = + ((set_slice (((( 8 : int):ii) * size1)) (( 8 : int):ii) value_name (( 0 : int):ii) w__0 + : 'p8_times_size_ words$word)) in sail2_state_monad$bindS + (if ((~ aligned)) then + let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_FAULT))) \/ (((c = Constraint_NONE)))))) "((c == Constraint_FAULT) || (c == Constraint_NONE))") + (let (aligned : bool) = (if (((c = Constraint_NONE))) then T else aligned) in + sail2_state_monad$returnS aligned) + else sail2_state_monad$returnS aligned) (\ (aligned : bool) . + (sail2_state$foreachS (index_list (( 1 : int):ii) ((size1 - (( 1 : int):ii))) (( 1 : int):ii)) value_name + (\ i value_name . sail2_state_monad$bindS + (AArch64_aget_MemSingle ((add_vec_int address i : 64 words$word)) (( 1 : int):ii) acctype aligned + : ( 8 words$word) M) (\ (w__1 : 8 words$word) . + let value_name = + ((set_slice (((( 8 : int):ii) * size1)) (( 8 : int):ii) value_name (((( 8 : int):ii) * i)) w__1 + : 'p8_times_size_ words$word)) in + sail2_state_monad$returnS value_name))))) + else if ((((((size1 = (( 16 : int):ii)))) /\ ((((((acctype = AccType_VEC))) \/ (((acctype = AccType_VECSTREAM))))))))) then sail2_state_monad$bindS + (AArch64_aget_MemSingle address (( 8 : int):ii) acctype aligned : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . + let value_name = + ((set_slice (((( 8 : int):ii) * (( 16 : int):ii))) (( 64 : int):ii) value_name (( 0 : int):ii) w__2 + : 'p8_times_size_ words$word)) in sail2_state_monad$bindS + (AArch64_aget_MemSingle ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype aligned + : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + let value_name = + ((set_slice (((( 8 : int):ii) * (( 16 : int):ii))) (( 64 : int):ii) value_name (( 64 : int):ii) w__3 + : 'p8_times_size_ words$word)) in + sail2_state_monad$returnS value_name)) + else (AArch64_aget_MemSingle address size1 acctype aligned : ( 'p8_times_size_ words$word) M)) (\ value_name . sail2_state_monad$bindS + (BigEndian () ) (\ (w__5 : bool) . + if w__5 then (BigEndianReverse value_name : ( 'p8_times_size_ words$word) M) + else sail2_state_monad$returnS value_name)))))))))`; + + +(*val aarch64_memory_vector_single_nowb : forall 'datasize 'esize . Size 'datasize, Size 'esize => itself 'datasize -> itself 'esize -> ii -> ii -> MemOp -> ii -> bool -> integer -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_vector_single_nowb:'datasize itself -> 'esize itself -> int -> int -> MemOp -> int -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) datasize esize index m memop n replicate selem t__arg wback= + (let esize = (size_itself_int esize) in + let datasize = (size_itself_int datasize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let (t : ii) = t__arg in sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offs : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (rval : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector esize : ( 'esize words$word) M) (\ (element1 : 'esize bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (s : ii) . + let (ebytes : int) = (ex_int ((esize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M))) (\ (address : 64 bits) . + let offs = ((Zeros__1 (( 64 : int):ii) () : 64 words$word)) in sail2_state_monad$bindS + (if replicate then sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (element1, offs, t) + (\ s varstup . let (element1, offs, t) = varstup in sail2_state_monad$bindS + (aget_Mem ((add_vec address offs : 64 words$word)) ebytes AccType_VEC : ( 'esize words$word) M) (\ (w__2 : 'esize + bits) . + let element1 = w__2 in + let (v : int) = (ex_int ((datasize / esize))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aset_V t ((replicate_bits element1 v : 'datasize words$word)))) + (let (offs : 64 bits) = ((add_vec_int offs ebytes : 64 words$word)) in + let (t : ii) = (((((ex_int t)) + (( 1 : int):ii))) % (( 32 : int):ii)) in + sail2_state_monad$returnS (element1, offs, t))))) (\ varstup . let ((element1 : 'esize bits), (offs : 64 + bits), (t : ii)) = varstup in + sail2_state_monad$returnS offs) + else sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, t) + (\ s varstup . let (offs, rval, t) = varstup in sail2_state_monad$bindS + (aget_V (( 128 : int):ii) t : ( 128 words$word) M) (\ (w__3 : 128 bits) . + let rval = w__3 in sail2_state_monad$bindS + (if (((memop = MemOp_LOAD))) then sail2_state_monad$bindS + (aget_Mem ((add_vec address offs : 64 words$word)) ebytes AccType_VEC : ( 'esize words$word) M) (\ (w__4 : + 'esize words$word) . sail2_state_monad$bindS + (aset_Elem__0 rval index ((make_the_value esize : 'esize itself)) w__4 + : ( 128 words$word) M) (\ (w__5 : 128 bits) . + let rval = w__5 in sail2_state_monad$seqS + (aset_V t rval) (sail2_state_monad$returnS rval))) + else sail2_state_monad$bindS + (aget_Elem__0 rval index ((make_the_value esize : 'esize itself)) : ( 'esize words$word) M) (\ w__6 . sail2_state_monad$seqS + (aset_Mem ((add_vec address offs : 64 words$word)) ebytes AccType_VEC w__6) (sail2_state_monad$returnS rval))) (\ (rval : 128 + bits) . + let (offs : 64 bits) = ((add_vec_int offs ebytes : 64 words$word)) in + let (t : ii) = (((((ex_int t)) + (( 1 : int):ii))) % (( 32 : int):ii)) in + sail2_state_monad$returnS (offs, rval, t))))) (\ varstup . let ((offs : 64 bits), (rval : 128 bits), (t : + ii)) = varstup in + sail2_state_monad$returnS offs)) (\ (offs : 64 bits) . + if wback then sail2_state_monad$bindS + (if (((m <> (( 31 : int):ii)))) then (aget_X (( 64 : int):ii) m : ( 64 words$word) M) + else sail2_state_monad$returnS offs) (\ (offs : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP ((add_vec address offs : 64 words$word)) + else aset_X n ((add_vec address offs : 64 words$word))) + else sail2_state_monad$returnS () ))))))))))`; + + +(*val aarch64_memory_vector_multiple_nowb : forall 'datasize 'esize . Size 'datasize, Size 'esize => itself 'datasize -> integer -> itself 'esize -> ii -> MemOp -> ii -> integer -> integer -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_vector_multiple_nowb:'datasize itself -> int -> 'esize itself -> int -> MemOp -> int -> int -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) datasize elements esize m memop n rpt selem t wback= + (let esize = (size_itself_int esize) in + let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offs : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (rval : 'datasize bits) . sail2_state_monad$bindS + (undefined_int () ) (\ (e : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (r : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (s : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (tt : ii) . + let ebytes = (ex_int ((esize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M))) (\ (address : 64 bits) . + let offs = ((Zeros__1 (( 64 : int):ii) () : 64 words$word)) in sail2_state_monad$bindS + (sail2_state$foreachS (index_list (( 0 : int):ii) ((rpt - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt) + (\ r varstup . let (offs, rval, tt) = varstup in + (sail2_state$foreachS (index_list (( 0 : int):ii) ((elements - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt) + (\ e varstup . let (offs, rval, tt) = varstup in + let tt = (((t + r)) % (( 32 : int):ii)) in + (sail2_state$foreachS (index_list (( 0 : int):ii) ((selem - (( 1 : int):ii))) (( 1 : int):ii)) (offs, rval, tt) + (\ s varstup . let (offs, rval, tt) = varstup in sail2_state_monad$bindS + (aget_V datasize tt : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . + let rval = w__2 in sail2_state_monad$bindS + (if (((memop = MemOp_LOAD))) then sail2_state_monad$bindS + (aget_Mem ((add_vec address offs : 64 words$word)) ebytes AccType_VEC + : ( 'esize words$word) M) (\ (w__3 : 'esize words$word) . sail2_state_monad$bindS + (aset_Elem__0 rval e ((make_the_value esize : 'esize itself)) w__3 + : ( 'datasize words$word) M) (\ (w__4 : 'datasize bits) . + let rval = w__4 in sail2_state_monad$seqS + (aset_V tt rval) (sail2_state_monad$returnS rval))) + else sail2_state_monad$bindS + (aget_Elem__0 rval e ((make_the_value esize : 'esize itself)) : ( 'esize words$word) M) (\ w__5 . sail2_state_monad$seqS + (aset_Mem ((add_vec address offs : 64 words$word)) ebytes AccType_VEC w__5) + (sail2_state_monad$returnS rval))) (\ (rval : 'datasize bits) . + let (offs : 64 bits) = ((add_vec_int offs ebytes : 64 words$word)) in + let (tt : ii) = (((((ex_int tt)) + (( 1 : int):ii))) % (( 32 : int):ii)) in + sail2_state_monad$returnS (offs, rval, tt))))))))) (\ varstup . let ((offs : 64 bits), (rval : 'datasize + bits), (tt : ii)) = varstup in + if wback then sail2_state_monad$bindS + (if (((m <> (( 31 : int):ii)))) then (aget_X (( 64 : int):ii) m : ( 64 words$word) M) + else sail2_state_monad$returnS offs) (\ (offs : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP ((add_vec address offs : 64 words$word)) + else aset_X n ((add_vec address offs : 64 words$word))) + else sail2_state_monad$returnS () )))))))))))`; + + +(*val aarch64_memory_single_simdfp_register : AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_simdfp_register:AccType -> int -> ExtendType -> int -> MemOp -> int -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__83 extend_type m memop n postindex shift t wback= + (if (((l__83 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M)) (\ (offset : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 8 : int):ii) t : ( 8 words$word) M) (\ (w__2 : 8 bits) . + let data = w__2 in + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__3 : 8 + bits) . + let data = w__3 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))) + else if (((l__83 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M)) (\ (offset : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 16 : int):ii) t : ( 16 words$word) M) (\ (w__6 : 16 bits) . + let data = w__6 in + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__7 : 16 + bits) . + let data = w__7 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))) + else if (((l__83 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M)) (\ (offset : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 32 : int):ii) t : ( 32 words$word) M) (\ (w__10 : 32 bits) . + let data = w__10 in + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__11 : 32 + bits) . + let data = w__11 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))) + else if (((l__83 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M)) (\ (offset : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__14 : 64 bits) . + let data = w__14 in + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__15 : 64 + bits) . + let data = w__15 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))) + else if (((l__83 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M)) (\ (offset : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 128 : int):ii) t : ( 128 words$word) M) (\ (w__18 : 128 bits) . + let data = w__18 in + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__19 : 128 + bits) . + let data = w__19 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))) + else + let dbytes = (ex_int ((l__83 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_memory_single_simdfp_immediate_signed_postidx : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_simdfp_immediate_signed_postidx:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__78 memop n offset postindex t wback= + (if (((l__78 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 8 : int):ii) t : ( 8 words$word) M) (\ (w__2 : 8 bits) . + let data = w__2 in + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__3 : 8 + bits) . + let data = w__3 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__78 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 16 : int):ii) t : ( 16 words$word) M) (\ (w__6 : 16 bits) . + let data = w__6 in + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__7 : 16 + bits) . + let data = w__7 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__78 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 32 : int):ii) t : ( 32 words$word) M) (\ (w__10 : 32 bits) . + let data = w__10 in + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__11 : 32 + bits) . + let data = w__11 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__78 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__14 : 64 bits) . + let data = w__14 in + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__15 : 64 + bits) . + let data = w__15 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__78 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 128 : int):ii) t : ( 128 words$word) M) (\ (w__18 : 128 bits) . + let data = w__18 in + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__19 : 128 + bits) . + let data = w__19 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else + let dbytes = (ex_int ((l__78 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_memory_single_simdfp_immediate_signed_offset_normal : AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_simdfp_immediate_signed_offset_normal:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__73 memop n offset postindex t wback= + (if (((l__73 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 8 : int):ii) t : ( 8 words$word) M) (\ (w__2 : 8 bits) . + let data = w__2 in + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__3 : 8 + bits) . + let data = w__3 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__73 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 16 : int):ii) t : ( 16 words$word) M) (\ (w__6 : 16 bits) . + let data = w__6 in + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__7 : 16 + bits) . + let data = w__7 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__73 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 32 : int):ii) t : ( 32 words$word) M) (\ (w__10 : 32 bits) . + let data = w__10 in + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__11 : 32 + bits) . + let data = w__11 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__73 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__14 : 64 bits) . + let data = w__14 in + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__15 : 64 + bits) . + let data = w__15 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else if (((l__73 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V (( 128 : int):ii) t : ( 128 words$word) M) (\ (w__18 : 128 bits) . + let data = w__18 in + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__19 : 128 + bits) . + let data = w__19 in + aset_V t data) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () )))) + else + let dbytes = (ex_int ((l__73 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_memory_ordered : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> MemOp -> ii -> itself 'regsize -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_ordered:AccType -> 'datasize itself -> MemOp -> int -> 'regsize itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n regsize t= + (let regsize = (size_itself_int regsize) in + let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data : 'datasize bits) . + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M))) (\ (address : 64 bits) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len data))) t : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . + let data = w__2 in + aset_Mem address dbytes acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . + let data = w__3 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__4 : + 'regsize words$word) . + aset_X t w__4)) + ))))))`; + + +(*val memory_ordered_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_ordered_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B0] : 1 words$word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 8 : int):ii) : 8 itself)) memop n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B0] : 1 words$word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 16 : int):ii) : 16 itself)) memop n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B0] : 1 words$word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 32 : int):ii) : 32 itself)) memop n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B0] : 1 words$word)))) then AccType_LIMITEDORDERED + else AccType_ORDERED) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_ordered acctype ((make_the_value (( 64 : int):ii) : 64 itself)) memop n + ((make_the_value (( 64 : int):ii) : 64 itself)) t)))`; + + +(*val aarch64_memory_orderedrcpc : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> ii -> itself 'regsize -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_orderedrcpc:AccType -> 'datasize itself -> int -> 'regsize itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize n regsize t= + (let regsize = (size_itself_int regsize) in + let datasize = (size_itself_int datasize) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data : 'datasize bits) . + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M))) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . + let data = w__2 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__3 : + 'regsize words$word) . + aset_X t w__3)))))))`; + + +(*val memory_orderedrcpc_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_orderedrcpc_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = AccType_ORDERED in + let (elsize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 8 : int):ii) : 8 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = AccType_ORDERED in + let (elsize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 16 : int):ii) : 16 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = AccType_ORDERED in + let (elsize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)) t) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = AccType_ORDERED in + let (elsize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_orderedrcpc AccType_ORDERED ((make_the_value (( 64 : int):ii) : 64 itself)) n + ((make_the_value (( 64 : int):ii) : 64 itself)) t)))`; + + +(*val aarch64_memory_literal_simdfp : mword ty64 -> integer -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_literal_simdfp:(64)words$word -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset l__70 t= + (if (((l__70 = (( 4 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS T "")) + (aget_PC () : ( 64 words$word) M)) (\ (w__0 : 64 words$word) . + let (address : 64 bits) = ((add_vec w__0 offset : 64 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_Mem address (( 4 : int):ii) AccType_VEC : ( 32 words$word) M)) (\ (w__1 : 32 bits) . + let data = w__1 in + aset_V t data))) + else if (((l__70 = (( 8 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS T "")) + (aget_PC () : ( 64 words$word) M)) (\ (w__2 : 64 words$word) . + let (address : 64 bits) = ((add_vec w__2 offset : 64 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_Mem address (( 8 : int):ii) AccType_VEC : ( 64 words$word) M)) (\ (w__3 : 64 bits) . + let data = w__3 in + aset_V t data))) + else if (((l__70 = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (sail2_state_monad$assert_expS T "")) + (aget_PC () : ( 64 words$word) M)) (\ (w__4 : 64 words$word) . + let (address : 64 bits) = ((add_vec w__4 offset : 64 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (CheckFPAdvSIMDEnabled64 () ) + (aget_Mem address (( 16 : int):ii) AccType_VEC : ( 128 words$word) M)) (\ (w__5 : 128 bits) . + let data = w__5 in + aset_V t data))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS T "") (sail2_state_monad$assert_expS T "")))`; + + +(*val aarch64_memory_literal_general : forall 'size. Size 'size => MemOp -> mword ty64 -> bool -> itself 'size -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_literal_general:MemOp ->(64)words$word -> bool -> 'size itself -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) memop offset signed size1 t= + (let size1 = (size_itself_int size1) in sail2_state_monad$bindS + (aget_PC () : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (address : 64 bits) = ((add_vec w__0 offset : 64 words$word)) in sail2_state_monad$bindS + (undefined_bitvector size1 : ( 'size words$word) M) (\ (data : 'size bits) . + (case memop of + MemOp_LOAD => sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (let bytes = (size1 / (( 8 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_Mem address bytes AccType_NORMAL : ( 'size words$word) M)) (\ (w__1 : 'size bits) . + let data = w__1 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . + aset_X t w__2) + else aset_X t data)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + )))))`; + + +(*val memory_literal_general_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_literal_general_decode:(2)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 imm19 Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (memop : MemOp) = MemOp_LOAD in + let (signed : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (size1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let size1 = ((( 4 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let offset = w__0 in + aarch64_memory_literal_general MemOp_LOAD offset F + ((make_the_value (( 32 : int):ii) : 32 itself)) t)))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (memop : MemOp) = MemOp_LOAD in + let (signed : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (size1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let size1 = ((( 8 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__1 : 64 bits) . + let offset = w__1 in + aarch64_memory_literal_general MemOp_LOAD offset F + ((make_the_value (( 64 : int):ii) : 64 itself)) t)))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (memop : MemOp) = MemOp_LOAD in + let (signed : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (size1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let size1 = ((( 4 : int):ii)) in + let signed = T in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let offset = w__2 in + aarch64_memory_literal_general MemOp_LOAD offset T ((make_the_value (( 32 : int):ii) : 32 itself)) + t)))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (memop : MemOp) = MemOp_LOAD in + let (signed : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (size1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let memop = MemOp_PREFETCH in sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__3 : 64 bits) . + let offset = w__3 in + aarch64_memory_literal_general MemOp_PREFETCH offset F + ((make_the_value (((( 8 : int):ii) * (( 32 : int):ii))) : 256 itself)) t))))))`; + + +(*val aarch64_memory_atomicops_swp : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_atomicops_swp:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__65 ldacctype n regsize s stacctype t= + (if (((l__65 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype : ( 8 words$word) M) (\ (w__2 : 8 + bits) . + let data = w__2 in sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len data))) s : ( 8 words$word) M) (\ w__3 . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype w__3) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__4 : + 'regsize words$word) . + aset_X t w__4))))))) + else if (((l__65 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype : ( 16 words$word) M) (\ (w__7 : 16 + bits) . + let data = w__7 in sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len data))) s : ( 16 words$word) M) (\ w__8 . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype w__8) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__9 : + 'regsize words$word) . + aset_X t w__9))))))) + else if (((l__65 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype : ( 32 words$word) M) (\ (w__12 : 32 + bits) . + let data = w__12 in sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len data))) s : ( 32 words$word) M) (\ w__13 . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype w__13) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14))))))) + else if (((l__65 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype : ( 64 words$word) M) (\ (w__17 : 64 + bits) . + let data = w__17 in sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len address))) s : ( 64 words$word) M) (\ w__18 . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype w__18) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__19 : + 'regsize words$word) . + aset_X t w__19))))))) + else if (((l__65 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype : ( 128 words$word) M) (\ (w__22 : 128 + bits) . + let data = w__22 in sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len data))) s : ( 128 words$word) M) (\ w__23 . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype w__23) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__24 : + 'regsize words$word) . + aset_X t w__24))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__65 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_atomicops_st : ii -> AccType -> ii -> MemAtomicOp -> ii -> AccType -> M unit*) + +val _ = Define ` + ((aarch64_memory_atomicops_st:int -> AccType -> int -> MemAtomicOp -> int -> AccType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__60 ldacctype n op s stacctype= + (if (((l__60 = (( 8 : int):ii)))) then + let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (value_name : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) s : ( 8 words$word) M) (\ (w__0 : 8 bits) . + let value_name = w__0 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype : ( 8 words$word) M) (\ (w__3 : 8 + bits) . + let data = w__3 in + let (result : 8 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 8 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 8 words$word)) : 8 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 8 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 8 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype result))))))) + else if (((l__60 = (( 16 : int):ii)))) then + let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (value_name : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) s : ( 16 words$word) M) (\ (w__4 : 16 bits) . + let value_name = w__4 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype : ( 16 words$word) M) (\ (w__7 : 16 + bits) . + let data = w__7 in + let (result : 16 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 16 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 16 words$word)) : 16 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 16 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 16 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype result))))))) + else if (((l__60 = (( 32 : int):ii)))) then + let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (value_name : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) s : ( 32 words$word) M) (\ (w__8 : 32 bits) . + let value_name = w__8 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype : ( 32 words$word) M) (\ (w__11 : 32 + bits) . + let data = w__11 in + let (result : 32 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 32 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 32 words$word)) : 32 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 32 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 32 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype result))))))) + else if (((l__60 = (( 64 : int):ii)))) then + let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (value_name : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) s : ( 64 words$word) M) (\ (w__12 : 64 bits) . + let value_name = w__12 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype : ( 64 words$word) M) (\ (w__15 : 64 + bits) . + let data = w__15 in + let (result : 64 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 64 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 64 words$word)) : 64 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 64 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 64 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype result))))))) + else if (((l__60 = (( 128 : int):ii)))) then + let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (value_name : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) s : ( 128 words$word) M) (\ (w__16 : 128 bits) . + let value_name = w__16 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype : ( 128 words$word) M) (\ (w__19 : 128 + bits) . + let data = w__19 in + let (result : 128 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 128 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 128 words$word)) : 128 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 128 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 128 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype result))))))) + else + let dbytes = (ex_int ((l__60 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint"))`; + + +(*val aarch64_memory_atomicops_ld : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> MemAtomicOp -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_atomicops_ld:int -> AccType -> int -> MemAtomicOp -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__55 ldacctype n op regsize s stacctype t= + (if (((l__55 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (value_name : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (result : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) s : ( 8 words$word) M) (\ (w__0 : 8 bits) . + let value_name = w__0 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype : ( 8 words$word) M) (\ (w__3 : 8 + bits) . + let data = w__3 in + let (result : 8 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 8 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 8 words$word)) : 8 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 8 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 8 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype result) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__4 : + 'regsize words$word) . + aset_X t w__4))))))))) + else if (((l__55 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (value_name : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (result : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) s : ( 16 words$word) M) (\ (w__5 : 16 bits) . + let value_name = w__5 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype : ( 16 words$word) M) (\ (w__8 : 16 + bits) . + let data = w__8 in + let (result : 16 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 16 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 16 words$word)) : 16 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 16 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 16 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype result) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__9 : + 'regsize words$word) . + aset_X t w__9))))))))) + else if (((l__55 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (value_name : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (result : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) s : ( 32 words$word) M) (\ (w__10 : 32 bits) . + let value_name = w__10 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype : ( 32 words$word) M) (\ (w__13 : 32 + bits) . + let data = w__13 in + let (result : 32 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 32 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 32 words$word)) : 32 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 32 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 32 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype result) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14))))))))) + else if (((l__55 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (value_name : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (result : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) s : ( 64 words$word) M) (\ (w__15 : 64 bits) . + let value_name = w__15 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype : ( 64 words$word) M) (\ (w__18 : 64 + bits) . + let data = w__18 in + let (result : 64 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 64 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 64 words$word)) : 64 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 64 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 64 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype result) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__19 : + 'regsize words$word) . + aset_X t w__19))))))))) + else if (((l__55 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (value_name : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (result : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) s : ( 128 words$word) M) (\ (w__20 : 128 bits) . + let value_name = w__20 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype : ( 128 words$word) M) (\ (w__23 : 128 + bits) . + let data = w__23 in + let (result : 128 bits) = + ((case op of + MemAtomicOp_ADD => (add_vec data value_name : 128 words$word) + | MemAtomicOp_BIC => (and_vec data ((not_vec value_name : 128 words$word)) : 128 words$word) + | MemAtomicOp_EOR => (xor_vec data value_name : 128 words$word) + | MemAtomicOp_ORR => (or_vec data value_name : 128 words$word) + | MemAtomicOp_SMAX => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then data else value_name + | MemAtomicOp_SMIN => if ((((integer_word$w2i data)) > ((integer_word$w2i value_name)))) then value_name else data + | MemAtomicOp_UMAX => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then data else value_name + | MemAtomicOp_UMIN => if ((((lem$w2ui data)) > ((lem$w2ui value_name)))) then value_name else data + )) in sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype result) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__24 : + 'regsize words$word) . + aset_X t w__24))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__55 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_atomicops_cas_single : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_atomicops_cas_single:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__50 ldacctype n regsize s stacctype t= + (if (((l__50 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (comparevalue : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (newvalue : 8 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) s : ( 8 words$word) M) (\ (w__0 : 8 bits) . + let comparevalue = w__0 in sail2_state_monad$bindS + (aget_X (( 8 : int):ii) t : ( 8 words$word) M) (\ (w__1 : 8 bits) . + let newvalue = w__1 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) ldacctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__5 : + 'regsize words$word) . + aset_X s w__5)))))))))) + else if (((l__50 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (comparevalue : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (newvalue : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) s : ( 16 words$word) M) (\ (w__6 : 16 bits) . + let comparevalue = w__6 in sail2_state_monad$bindS + (aget_X (( 16 : int):ii) t : ( 16 words$word) M) (\ (w__7 : 16 bits) . + let newvalue = w__7 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype : ( 16 words$word) M) (\ (w__10 : 16 + bits) . + let data = w__10 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__11 : + 'regsize words$word) . + aset_X s w__11)))))))))) + else if (((l__50 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (comparevalue : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (newvalue : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) s : ( 32 words$word) M) (\ (w__12 : 32 bits) . + let comparevalue = w__12 in sail2_state_monad$bindS + (aget_X (( 32 : int):ii) t : ( 32 words$word) M) (\ (w__13 : 32 bits) . + let newvalue = w__13 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype : ( 32 words$word) M) (\ (w__16 : 32 + bits) . + let data = w__16 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__17 : + 'regsize words$word) . + aset_X s w__17)))))))))) + else if (((l__50 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (comparevalue : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (newvalue : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) s : ( 64 words$word) M) (\ (w__18 : 64 bits) . + let comparevalue = w__18 in sail2_state_monad$bindS + (aget_X (( 64 : int):ii) t : ( 64 words$word) M) (\ (w__19 : 64 bits) . + let newvalue = w__19 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype : ( 64 words$word) M) (\ (w__22 : 64 + bits) . + let data = w__22 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__23 : + 'regsize words$word) . + aset_X s w__23)))))))))) + else if (((l__50 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (comparevalue : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (newvalue : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) s : ( 128 words$word) M) (\ (w__24 : 128 bits) . + let comparevalue = w__24 in sail2_state_monad$bindS + (aget_X (( 128 : int):ii) t : ( 128 words$word) M) (\ (w__25 : 128 bits) . + let newvalue = w__25 in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype : ( 128 words$word) M) (\ (w__28 : 128 + bits) . + let data = w__28 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M)) (\ (w__29 : + 'regsize words$word) . + aset_X s w__29)))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__50 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_atomicops_cas_pair : forall 'regsize. Size 'regsize => ii -> AccType -> ii -> itself 'regsize -> ii -> AccType -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_atomicops_cas_pair:int -> AccType -> int -> 'regsize itself -> int -> AccType -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) l__45 ldacctype n regsize s stacctype t= + (if (((l__45 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (comparevalue : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (newvalue : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) s : ( 8 words$word) M) (\ (s1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) ((s + (( 1 : int):ii))) : ( 8 words$word) M) (\ (s2 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) t : ( 8 words$word) M) (\ (t1 : 8 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) ((t + (( 1 : int):ii))) : ( 8 words$word) M) (\ (t2 : 8 bits) . sail2_state_monad$bindS + (BigEndian () ) (\ (w__0 : bool) . + let comparevalue = + (if w__0 then (concat_vec s1 s2 : 16 words$word) + else (concat_vec s2 s1 : 16 words$word)) in sail2_state_monad$bindS + (BigEndian () ) (\ (w__1 : bool) . + let newvalue = + (if w__1 then (concat_vec t1 t2 : 16 words$word) + else (concat_vec t2 t1 : 16 words$word)) in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) ldacctype : ( 16 words$word) M) (\ (w__4 : 16 + bits) . + let data = w__4 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (BigEndian () )) (\ (w__5 : bool) . + if w__5 then sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 8 : int):ii) (( 8 : int):ii) : 8 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__6 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__6) + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 8 : int):ii) : 8 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__7 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__7)) + else sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 8 : int):ii) : 8 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__8 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__8) + (ZeroExtend__0 ((slice data (( 8 : int):ii) (( 8 : int):ii) : 8 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__9 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__9)))))))))))))))) + else if (((l__45 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (comparevalue : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (newvalue : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) s : ( 16 words$word) M) (\ (s1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) ((s + (( 1 : int):ii))) : ( 16 words$word) M) (\ (s2 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) t : ( 16 words$word) M) (\ (t1 : 16 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) ((t + (( 1 : int):ii))) : ( 16 words$word) M) (\ (t2 : 16 bits) . sail2_state_monad$bindS + (BigEndian () ) (\ (w__10 : bool) . + let comparevalue = + (if w__10 then (concat_vec s1 s2 : 32 words$word) + else (concat_vec s2 s1 : 32 words$word)) in sail2_state_monad$bindS + (BigEndian () ) (\ (w__11 : bool) . + let newvalue = + (if w__11 then (concat_vec t1 t2 : 32 words$word) + else (concat_vec t2 t1 : 32 words$word)) in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) ldacctype : ( 32 words$word) M) (\ (w__14 : 32 + bits) . + let data = w__14 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (BigEndian () )) (\ (w__15 : bool) . + if w__15 then sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 16 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__16 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__16) + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__17 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__17)) + else sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__18 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__18) + (ZeroExtend__0 ((slice data (( 16 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__19 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__19)))))))))))))))) + else if (((l__45 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (comparevalue : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (newvalue : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) s : ( 32 words$word) M) (\ (s1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) ((s + (( 1 : int):ii))) : ( 32 words$word) M) (\ (s2 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) t : ( 32 words$word) M) (\ (t1 : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) ((t + (( 1 : int):ii))) : ( 32 words$word) M) (\ (t2 : 32 bits) . sail2_state_monad$bindS + (BigEndian () ) (\ (w__20 : bool) . + let comparevalue = + (if w__20 then (concat_vec s1 s2 : 64 words$word) + else (concat_vec s2 s1 : 64 words$word)) in sail2_state_monad$bindS + (BigEndian () ) (\ (w__21 : bool) . + let newvalue = + (if w__21 then (concat_vec t1 t2 : 64 words$word) + else (concat_vec t2 t1 : 64 words$word)) in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) ldacctype : ( 64 words$word) M) (\ (w__24 : 64 + bits) . + let data = w__24 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (BigEndian () )) (\ (w__25 : bool) . + if w__25 then sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 32 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__26 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__26) + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__27 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__27)) + else sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__28 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__28) + (ZeroExtend__0 ((slice data (( 32 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__29 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__29)))))))))))))))) + else if (((l__45 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (comparevalue : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (newvalue : 128 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) s : ( 64 words$word) M) (\ (s1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) ((s + (( 1 : int):ii))) : ( 64 words$word) M) (\ (s2 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) t : ( 64 words$word) M) (\ (t1 : 64 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) ((t + (( 1 : int):ii))) : ( 64 words$word) M) (\ (t2 : 64 bits) . sail2_state_monad$bindS + (BigEndian () ) (\ (w__30 : bool) . + let comparevalue = + (if w__30 then (concat_vec s1 s2 : 128 words$word) + else (concat_vec s2 s1 : 128 words$word)) in sail2_state_monad$bindS + (BigEndian () ) (\ (w__31 : bool) . + let newvalue = + (if w__31 then (concat_vec t1 t2 : 128 words$word) + else (concat_vec t2 t1 : 128 words$word)) in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) ldacctype : ( 128 words$word) M) (\ (w__34 : 128 + bits) . + let data = w__34 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (BigEndian () )) (\ (w__35 : bool) . + if w__35 then sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 64 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__36 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__36) + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__37 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__37)) + else sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__38 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__38) + (ZeroExtend__0 ((slice data (( 64 : int):ii) (( 64 : int):ii) : 64 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__39 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__39)))))))))))))))) + else if (((l__45 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 256 : int):ii) : ( 256 words$word) M) (\ (comparevalue : 256 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 256 : int):ii) : ( 256 words$word) M) (\ (newvalue : 256 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 256 : int):ii) : ( 256 words$word) M) (\ (data : 256 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) s : ( 128 words$word) M) (\ (s1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) ((s + (( 1 : int):ii))) : ( 128 words$word) M) (\ (s2 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) t : ( 128 words$word) M) (\ (t1 : 128 bits) . sail2_state_monad$bindS + (aget_X (( 128 : int):ii) ((t + (( 1 : int):ii))) : ( 128 words$word) M) (\ (t2 : 128 bits) . sail2_state_monad$bindS + (BigEndian () ) (\ (w__40 : bool) . + let comparevalue = + (if w__40 then (concat_vec s1 s2 : 256 words$word) + else (concat_vec s2 s1 : 256 words$word)) in sail2_state_monad$bindS + (BigEndian () ) (\ (w__41 : bool) . + let newvalue = + (if w__41 then (concat_vec t1 t2 : 256 words$word) + else (concat_vec t2 t1 : 256 words$word)) in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (aget_Mem address (((( 256 : int):ii) / (( 8 : int):ii))) ldacctype : ( 256 words$word) M) (\ (w__44 : 256 + bits) . + let data = w__44 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((data = comparevalue))) then + aset_Mem address (((( 256 : int):ii) / (( 8 : int):ii))) stacctype newvalue + else sail2_state_monad$returnS () ) + (BigEndian () )) (\ (w__45 : bool) . + if w__45 then sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 128 : int):ii) (( 128 : int):ii) : 128 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__46 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__46) + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 128 : int):ii) : 128 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__47 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__47)) + else sail2_state_monad$bindS + (ZeroExtend__0 ((slice data (( 0 : int):ii) (( 128 : int):ii) : 128 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M) (\ (w__48 : 'regsize words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X s w__48) + (ZeroExtend__0 ((slice data (( 128 : int):ii) (( 128 : int):ii) : 128 words$word)) + ((make_the_value regsize : 'regsize itself)) + : ( 'regsize words$word) M)) (\ (w__49 : 'regsize words$word) . + aset_X ((s + (( 1 : int):ii))) w__49)))))))))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__45 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val AArch64_SetExclusiveMonitors : mword ty64 -> ii -> M unit*) + +val _ = Define ` + ((AArch64_SetExclusiveMonitors:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1= + (let (acctype : AccType) = AccType_ATOMIC in + let (iswrite : bool) = F in + let (aligned : bool) = (address <> ((Align__1 address size1 : 64 words$word))) in sail2_state_monad$bindS + (AArch64_TranslateAddress address acctype iswrite aligned size1) (\ (memaddrdesc : + AddressDescriptor) . + let (_ : unit) = (if ((IsFault memaddrdesc)) then () else () ) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then + MarkExclusiveGlobal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1 + else sail2_state_monad$returnS () ) + (MarkExclusiveLocal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1)) + (AArch64_MarkExclusiveVA address ((ProcessorID () )) size1))))`; + + +(*val AArch64_ExclusiveMonitorsPass : mword ty64 -> ii -> M bool*) + +val _ = Define ` + ((AArch64_ExclusiveMonitorsPass:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) address size1= + (let (acctype : AccType) = AccType_ATOMIC in + let (iswrite : bool) = T in + let (aligned : bool) = (address = ((Align__1 address size1 : 64 words$word))) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ aligned)) then + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype iswrite secondstage) (\ (w__0 : FaultRecord) . + AArch64_Abort address w__0) + else sail2_state_monad$returnS () ) + (AArch64_IsExclusiveVA address ((ProcessorID () )) size1)) (\ (passed : bool) . + if ((~ passed)) then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (AArch64_TranslateAddress address acctype iswrite aligned size1) (\ (memaddrdesc : + AddressDescriptor) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((IsFault memaddrdesc)) then AArch64_Abort address memaddrdesc.AddressDescriptor_fault + else sail2_state_monad$returnS () ) + (IsExclusiveLocal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1)) (\ (w__1 : + bool) . + let passed = w__1 in + if passed then sail2_state_monad$seqS + (ClearExclusiveLocal ((ProcessorID () ))) + (if memaddrdesc.AddressDescriptor_memattrs.MemoryAttributes_shareable then + IsExclusiveGlobal memaddrdesc.AddressDescriptor_paddress ((ProcessorID () )) size1 + else sail2_state_monad$returnS passed) + else sail2_state_monad$returnS passed))))))`; + + +(*val AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled : unit -> M bool*) + +val _ = Define ` + ((AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : bool) . + if w__1 then sail2_state_monad$returnS F + else + sail2_state$and_boolS ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGEN_ref) (\ (w__2 : signal) . sail2_state_monad$returnS (((w__2 = HIGH))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SPIDEN_ref) (\ (w__3 : signal) . sail2_state_monad$returnS (((w__3 = HIGH))))))))`; + + +(*val AArch32_GenerateDebugExceptionsFrom : mword ty2 -> bool -> M bool*) + +val _ = Define ` + ((AArch32_GenerateDebugExceptionsFrom:(2)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) from secure= (sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (mask : 1 bits) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((from = EL0)))) + ( sail2_state_monad$bindS(ELStateUsingAArch32 EL1 secure) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) (\ (w__1 : + bool) . + if w__1 then sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (w__2 : 1 bits) . + let mask = w__2 in + AArch64_GenerateDebugExceptionsFrom from secure mask) + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS DBGOSLSR_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) ((DoubleLockStatus () ))) ((Halted () ))) (\ (w__8 : + bool) . + if w__8 then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (enabled : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (spd : 2 bits) . + if (((((HaveEL EL3)) /\ secure))) then sail2_state_monad$bindS + (ELUsingAArch32 EL3) (\ (w__9 : bool) . sail2_state_monad$bindS + (if w__9 then sail2_state_monad$bindS + (sail2_state_monad$read_regS SDCR_ref : ( 32 words$word) M) (\ (w__10 : 32 bits) . + sail2_state_monad$returnS ((slice w__10 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS MDCR_EL3_ref : ( 32 words$word) M) (\ (w__11 : 32 bits) . + sail2_state_monad$returnS ((slice w__11 (( 14 : int):ii) (( 2 : int):ii) : 2 words$word)))) (\ (w__12 : 2 words$word) . + let spd = w__12 in sail2_state_monad$bindS + (if ((((vec_of_bits [access_vec_dec spd (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + let (enabled : bool) = + ((vec_of_bits [access_vec_dec spd (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + sail2_state_monad$returnS enabled + else AArch32_SelfHostedSecurePrivilegedInvasiveDebugEnabled () ) (\ (enabled : bool) . + if (((from = EL0))) then + sail2_state$or_boolS (sail2_state_monad$returnS enabled) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SDER_ref : ( 32 words$word) M) (\ (w__14 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))) + else sail2_state_monad$returnS enabled))) + else + let (enabled : bool) = (from <> EL2) in + sail2_state_monad$returnS enabled)))))))`; + + +(*val AArch32_GenerateDebugExceptions : unit -> M bool*) + +val _ = Define ` + ((AArch32_GenerateDebugExceptions:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (IsSecure () ) (\ (w__1 : bool) . AArch32_GenerateDebugExceptionsFrom w__0.ProcState_EL w__1))))`; + + +(*val DebugExceptionReturnSS : mword ty32 -> M (mword ty1)*) + +val _ = Define ` + ((DebugExceptionReturnSS:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->((((1)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr= (sail2_state_monad$bindS + (sail2_state$or_boolS (sail2_state$or_boolS ((Halted () )) ((Restarting () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL <> EL0)))))) (\ (w__4 : + bool) . sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__4 "((Halted() || Restarting()) || ((PSTATE).EL != EL0))") + (let (SS_bit : 1 bits) = ((vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (ELd : 2 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M) (\ (mask : 1 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (enabled_at_dest : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secure : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (valid_name : bool) . sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (dest : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (enabled_at_source : bool) . sail2_state_monad$bindS + (sail2_state_monad$read_regS MDSCR_EL1_ref : ( 32 words$word) M) (\ (w__5 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__5 (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (Restarting () ) (\ (w__6 : bool) . sail2_state_monad$bindS + (if w__6 then sail2_state_monad$returnS F + else sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__7 : bool) . + if w__7 then AArch32_GenerateDebugExceptions () + else AArch64_GenerateDebugExceptions () )) (\ (enabled_at_source : bool) . sail2_state_monad$bindS + (IllegalExceptionReturn spsr) (\ (w__10 : bool) . sail2_state_monad$bindS + (if w__10 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + let (dest : 2 bits) = (w__11.ProcState_EL) in + sail2_state_monad$returnS dest) + else sail2_state_monad$bindS + (ELFromSPSR spsr : ((bool # 2 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let valid_name = tup__0 in + let dest = tup__1 in sail2_state_monad$seqS + (sail2_state_monad$assert_expS valid_name "valid") (sail2_state_monad$returnS dest))) (\ (dest : 2 bits) . sail2_state_monad$bindS + (sail2_state$or_boolS ((IsSecureBelowEL3 () )) (sail2_state_monad$returnS (((dest = EL3))))) (\ (w__13 : bool) . + let secure = w__13 in sail2_state_monad$bindS + (ELUsingAArch32 dest) (\ (w__14 : bool) . sail2_state_monad$bindS + (if w__14 then AArch32_GenerateDebugExceptionsFrom dest secure + else + let mask = ((vec_of_bits [access_vec_dec spsr (( 9 : int):ii)] : 1 words$word)) in + AArch64_GenerateDebugExceptionsFrom dest secure mask) (\ (enabled_at_dest : bool) . sail2_state_monad$bindS + (DebugTargetFrom secure : ( 2 words$word) M) (\ (w__17 : 2 bits) . + let ELd = w__17 in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS ( sail2_state_monad$bindS(ELUsingAArch32 ELd) (\ (w__18 : bool) . sail2_state_monad$returnS ((~ w__18)))) + (sail2_state_monad$returnS ((~ enabled_at_source)))) (sail2_state_monad$returnS enabled_at_dest)) (\ (w__20 : bool) . + let (SS_bit : 1 bits) = + (if w__20 then (vec_of_bits [access_vec_dec spsr (( 21 : int):ii)] : 1 words$word) + else SS_bit) in + sail2_state_monad$returnS SS_bit))))))))) + else sail2_state_monad$returnS SS_bit))))))))))))`; + + +(*val SetPSTATEFromPSR : mword ty32 -> M unit*) + +val _ = Define ` + ((SetPSTATEFromPSR:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) spsr__arg= + (let spsr = spsr__arg in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS + (DebugExceptionReturnSS spsr : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__0 with<| ProcState_SS := w__1|>)) + (IllegalExceptionReturn spsr)) (\ (w__2 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__2 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__3 with<| ProcState_IL := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__4 : ProcState) . sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__4 with<| ProcState_IL := ((vec_of_bits [access_vec_dec spsr (( 20 : int):ii)] : 1 words$word))|>)) + (if ((((vec_of_bits [access_vec_dec spsr (( 4 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + AArch32_WriteMode ((slice spsr (( 0 : int):ii) (( 5 : int):ii) : 5 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__5 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__5 with<| ProcState_nRW := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_EL := ((slice spsr (( 2 : int):ii) (( 2 : int):ii) : 2 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__7 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__7 with<| ProcState_SP := ((vec_of_bits [access_vec_dec spsr (( 0 : int):ii)] : 1 words$word))|>))))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__8 : ProcState) . + sail2_state_monad$returnS (((w__8.ProcState_IL = (vec_of_bits [B1] : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + sail2_state_monad$returnS (((w__9.ProcState_nRW = (vec_of_bits [B1] : 1 words$word)))))))) (\ (w__10 : bool) . sail2_state_monad$bindS + (if w__10 then sail2_state_monad$bindS + (ConstrainUnpredictableBool Unpredictable_ILZEROT) (\ (w__11 : bool) . + let (spsr : 32 words$word) = + (if w__11 then + (set_slice (( 32 : int):ii) (( 1 : int):ii) spsr (( 5 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word) + else spsr) in + sail2_state_monad$returnS spsr) + else sail2_state_monad$returnS spsr) (\ (spsr : 32 words$word) . + let split_vec = ((slice spsr (( 28 : int):ii) (( 4 : int):ii) : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_V := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) . sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((w__16.ProcState_nRW = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__17 with<| ProcState_Q := ((vec_of_bits [access_vec_dec spsr (( 27 : int):ii)] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS + (RestoredITBits spsr : ( 8 words$word) M) (\ (w__19 : 8 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_IT := w__19|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__20 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__20 with<| ProcState_GE := ((slice spsr (( 16 : int):ii) (( 4 : int):ii) : 4 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__21 : ProcState) . sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__21 with<| ProcState_E := ((vec_of_bits [access_vec_dec spsr (( 9 : int):ii)] : 1 words$word))|>)) + (let split_vec = ((slice spsr (( 6 : int):ii) (( 3 : int):ii) : 3 words$word)) in + let (tup__0, tup__1, tup__2) = + ((subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_A := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_I := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_F := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__25 with<| ProcState_T := ((vec_of_bits [access_vec_dec spsr (( 5 : int):ii)] : 1 words$word))|>))))))))))) + else + let split_vec = ((slice spsr (( 6 : int):ii) (( 4 : int):ii) : 4 words$word)) in + let (tup__0, tup__1, tup__2, tup__3) = + ((subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_D := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_A := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_I := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_F := tup__3|>)))))) + (if ((HavePANExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__30 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__30 with<| ProcState_PAN := ((vec_of_bits [access_vec_dec spsr (( 22 : int):ii)] : 1 words$word))|>)) + else sail2_state_monad$returnS () )) + (if ((HaveUAOExt () )) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__31 : ProcState) . + sail2_state_monad$write_regS + PSTATE_ref + (w__31 with<| ProcState_UAO := ((vec_of_bits [access_vec_dec spsr (( 23 : int):ii)] : 1 words$word))|>)) + else sail2_state_monad$returnS () )))))))))))))`; + + +(*val DRPSInstruction : unit -> M unit*) + +val _ = Define ` + ((DRPSInstruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ((ConstrainUnpredictableBool Unpredictable_IESBinDebug))) (\ (w__3 : bool) . + let (_ : unit) = + (if w__3 then ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All + else () ) in sail2_state_monad$bindS + (aget_SPSR () : ( 32 words$word) M) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (SetPSTATEFromPSR w__4) + (UsingAArch32 () )) (\ (w__5 : bool) . sail2_state_monad$seqS + (if w__5 then sail2_state_monad$bindS + (undefined_bitvector (( 13 : int):ii) : ( 13 words$word) M) (\ (w__6 : 13 bits) . + let split_vec = w__6 in + let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8, tup__9) = + ((subrange_vec_dec split_vec (( 12 : int):ii) (( 12 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 11 : int):ii) (( 11 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 10 : int):ii) (( 10 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 9 : int):ii) (( 9 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 8 : int):ii) (( 8 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 7 : int):ii) (( 4 : int):ii) : 4 words$word), + (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__7 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__8 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__8 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__9 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__10 with<| ProcState_V := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__11 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__11 with<| ProcState_Q := tup__4|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__12 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_GE := tup__5|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__13 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__13 with<| ProcState_SS := tup__6|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__14 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__14 with<| ProcState_A := tup__7|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__15 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_I := tup__8|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__16 with<| ProcState_F := tup__9|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__17 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__17 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_T := ((vec_of_bits [B1] : 1 words$word))|>)) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__19 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_ref w__19) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__20 : 32 bits) . + sail2_state_monad$write_regS DSPSR_ref w__20))))))))))))))) + else sail2_state_monad$bindS + (undefined_bitvector (( 9 : int):ii) : ( 9 words$word) M) (\ (w__21 : 9 bits) . + let split_vec = w__21 in + let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8) = + ((subrange_vec_dec split_vec (( 8 : int):ii) (( 8 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 7 : int):ii) (( 7 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 6 : int):ii) (( 6 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 5 : int):ii) (( 5 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 4 : int):ii) (( 4 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 3 : int):ii) (( 3 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 2 : int):ii) (( 2 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 1 : int):ii) (( 1 : int):ii) : 1 words$word), + (subrange_vec_dec split_vec (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__22 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__22 with<| ProcState_N := tup__0|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__23 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__23 with<| ProcState_Z := tup__1|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__24 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__24 with<| ProcState_C := tup__2|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__25 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__25 with<| ProcState_V := tup__3|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__26 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__26 with<| ProcState_SS := tup__4|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__27 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__27 with<| ProcState_D := tup__5|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__28 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__28 with<| ProcState_A := tup__6|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__29 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__29 with<| ProcState_I := tup__7|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__30 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__30 with<| ProcState_F := tup__8|>)) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__31 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_EL0_ref w__31) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__32 : 32 bits) . + sail2_state_monad$write_regS DSPSR_EL0_ref w__32))))))))))))) + (UpdateEDSCRFields () ))))))`; + + +(*val aarch64_branch_unconditional_dret : unit -> M unit*) + +val _ = Define ` + ((aarch64_branch_unconditional_dret:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (DRPSInstruction () ))`; + + +(*val AArch64_ExceptionReturn : mword ty64 -> mword ty32 -> M unit*) + +val _ = Define ` + ((AArch64_ExceptionReturn:(64)words$word ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) new_pc__arg spsr= + (let new_pc = new_pc__arg in + let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iesb_req : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveRASExt () ))) + ( sail2_state_monad$bindS(aget_SCTLR__1 () : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 21 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__1 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if w__1 then + let (_ : unit) = (ErrorSynchronizationBarrier MBReqDomain_FullSystem MBReqTypes_All) in + let iesb_req = T in + TakeUnmaskedPhysicalSErrorInterrupts iesb_req + else sail2_state_monad$returnS () ) + (SetPSTATEFromPSR spsr)) + (ClearExclusiveLocal ((ProcessorID () )))) + (SendEventLocal () )) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__2 : ProcState) . sail2_state_monad$bindS + (if (((w__2.ProcState_IL = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + let new_pc = ((set_slice (( 64 : int):ii) (( 32 : int):ii) new_pc (( 32 : int):ii) w__3 : 64 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (w__4 : 2 words$word) . + let (new_pc : 64 words$word) = ((set_slice (( 64 : int):ii) (( 2 : int):ii) new_pc (( 0 : int):ii) w__4 : 64 words$word)) in + sail2_state_monad$returnS new_pc)) + else sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__5 : bool) . + if w__5 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + let (new_pc : 64 words$word) = + (if (((w__6.ProcState_T = (vec_of_bits [B0] : 1 words$word)))) then + (set_slice (( 64 : int):ii) (( 1 : int):ii) new_pc (( 0 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word) + else + (set_slice (( 64 : int):ii) (( 2 : int):ii) new_pc (( 0 : int):ii) (vec_of_bits [B0;B0] : 2 words$word) : 64 words$word)) in + sail2_state_monad$returnS new_pc) + else (AArch64_BranchAddr new_pc : ( 64 words$word) M))) (\ (new_pc : 64 words$word) . sail2_state_monad$bindS + (UsingAArch32 () ) (\ (w__8 : bool) . + if w__8 then BranchTo ((slice new_pc (( 0 : int):ii) (( 32 : int):ii) : 32 words$word)) BranchType_UNKNOWN + else BranchToAddr new_pc BranchType_ERET)))))))`; + + +(*val aarch64_branch_unconditional_eret : bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_branch_unconditional_eret:bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pac use_key_a= (sail2_state_monad$bindS (sail2_state_monad$seqS + (AArch64_CheckForERetTrap pac use_key_a) + (aget_ELR__1 () : ( 64 words$word) M)) (\ (target : 64 bits) . sail2_state_monad$bindS + (if pac then + if use_key_a then sail2_state_monad$bindS + (aget_ELR__1 () : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + (AuthIA w__0 w__1 : ( 64 words$word) M))) + else sail2_state_monad$bindS + (aget_ELR__1 () : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + (AuthIB w__3 w__4 : ( 64 words$word) M))) + else sail2_state_monad$returnS target) (\ (target : 64 bits) . sail2_state_monad$bindS + (aget_SPSR () : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + AArch64_ExceptionReturn target w__6)))))`; + + +(*val AArch32_GeneralExceptionsToAArch64 : unit -> M bool*) + +val _ = Define ` + ((AArch32_GeneralExceptionsToAArch64:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$or_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL0))))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL1) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__3 : bool) . sail2_state_monad$returnS ((~ w__3))))) + ( sail2_state_monad$bindS(ELUsingAArch32 EL2) (\ (w__5 : bool) . sail2_state_monad$returnS ((~ w__5))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))))))))`; + + +(*val AArch32_EnterHypMode : ExceptionRecord -> mword ty32 -> ii -> M unit*) + +val _ = Define ` + ((AArch32_EnterHypMode:ExceptionRecord ->(32)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception preferred_exception_return vect_offset= + (let (_ : unit) = (SynchronizeContext () ) in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ((ELUsingAArch32 EL2))) (\ (w__3 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS w__3 "((HaveEL(EL2) && !(IsSecure())) && ELUsingAArch32(EL2))") + (GetPSRFromPSTATE () : ( 32 words$word) M)) (\ (spsr : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((~ ((((((exception.ExceptionRecord_typ = Exception_IRQ))) \/ (((exception.ExceptionRecord_typ = Exception_FIQ)))))))) then + AArch32_ReportHypEntry exception + else sail2_state_monad$returnS () ) + (AArch32_WriteMode M32_Hyp)) + (aset_SPSR spsr)) + (sail2_state_monad$write_regS ELR_hyp_ref preferred_exception_return)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__4 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HSCTLR_ref : ( 32 words$word) M) (\ (w__5 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__4 with<| ProcState_T := ((vec_of_bits [access_vec_dec w__5 (( 30 : int):ii)] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__6 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__6 with<| ProcState_SS := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(aget_SCR_GEN () : ( 32 words$word) M) (\ (w__7 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 3 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__8 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__8 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__9 with<| ProcState_A := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(aget_SCR_GEN () : ( 32 words$word) M) (\ (w__10 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__11 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__11 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__12 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__12 with<| ProcState_I := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL3))))) + ( sail2_state_monad$bindS(aget_SCR_GEN () : ( 32 words$word) M) (\ (w__13 : 32 words$word) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 2 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__14 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__14 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__15 : ProcState) . + sail2_state_monad$write_regS PSTATE_ref (w__15 with<| ProcState_F := ((vec_of_bits [B1] : 1 words$word))|>)) + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__16 : ProcState) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HSCTLR_ref : ( 32 words$word) M) (\ (w__17 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__16 with<| ProcState_E := ((vec_of_bits [access_vec_dec w__17 (( 25 : int):ii)] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__18 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref (w__18 with<| ProcState_IL := ((vec_of_bits [B0] : 1 words$word))|>)) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__19 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + PSTATE_ref + (w__19 with<| ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))|>)) + (sail2_state_monad$read_regS HVBAR_ref : ( 32 words$word) M)) (\ (w__20 : 32 bits) . sail2_state_monad$seqS + (BranchTo + ((concat_vec ((slice w__20 (( 5 : int):ii) (( 27 : int):ii) : 27 words$word)) + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) vect_offset (( 0 : int):ii) : 5 words$word)) + : 32 words$word)) BranchType_UNKNOWN) + (EndOfInstruction () ))))))))))))))))`; + + +(*val AArch32_TakeUndefInstrException__0 : unit -> M unit*) + +(*val AArch32_TakeUndefInstrException__1 : ExceptionRecord -> M unit*) + +val _ = Define ` + ((AArch32_TakeUndefInstrException__1:ExceptionRecord ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) exception= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL0)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_ref : ( 32 words$word) M) (\ (w__4 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 27 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_hyp : bool) . sail2_state_monad$bindS + (ThisInstrAddr (( 32 : int):ii) () : ( 32 words$word) M) (\ (preferred_exception_return : 32 bits) . + let (vect_offset : ii) = ((( 4 : int):ii)) in sail2_state_monad$bindS + (CurrentInstrSet () ) (\ (w__5 : InstrSet) . + let (lr_offset : ii) = (if (((w__5 = InstrSet_A32))) then (( 4 : int):ii) else (( 2 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__6 : ProcState) . + if (((w__6.ProcState_EL = EL2))) then + AArch32_EnterHypMode exception preferred_exception_return vect_offset + else if route_to_hyp then AArch32_EnterHypMode exception preferred_exception_return (( 20 : int):ii) + else AArch32_EnterMode M32_Undef preferred_exception_return lr_offset vect_offset))))))`; + + +val _ = Define ` + ((AArch32_TakeUndefInstrException__0:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (ExceptionSyndrome Exception_Uncategorized) (\ (exception : ExceptionRecord) . + AArch32_TakeUndefInstrException__1 exception)))`; + + +(*val UnallocatedEncoding : unit -> M unit*) + +val _ = Define ` + ((UnallocatedEncoding:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS ((UsingAArch32 () )) ((AArch32_ExecutingCP10or11Instr () ))) (\ (w__2 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__2 then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPEXC_ref : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + sail2_state_monad$write_regS + FPEXC_ref + ((set_slice (( 32 : int):ii) (( 1 : int):ii) w__3 (( 29 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word))) + else sail2_state_monad$returnS () ) + (sail2_state$and_boolS ((UsingAArch32 () )) + ( sail2_state_monad$bindS(AArch32_GeneralExceptionsToAArch64 () ) (\ (w__5 : bool) . sail2_state_monad$returnS ((~ w__5)))))) (\ (w__6 : + bool) . + if w__6 then AArch32_TakeUndefInstrException__0 () + else AArch64_UndefinedFault () ))))`; + + +(*val aarch64_system_exceptions_runtime_hvc : mword ty16 -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_runtime_hvc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm= (sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state$or_boolS (sail2_state_monad$returnS ((~ ((HaveEL EL2))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL0)))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__2 : ProcState) . sail2_state_monad$returnS (((w__2.ProcState_EL = EL1))))) + ((IsSecure () )))) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if w__5 then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((HaveEL EL3)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M) (\ (w__6 : 32 bits) . + sail2_state_monad$returnS (vec_of_bits [access_vec_dec w__6 (( 8 : int):ii)] : 1 words$word)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((not_vec (vec_of_bits [access_vec_dec w__7 (( 29 : int):ii)] : 1 words$word) : 1 words$word))))) (\ (hvc_enable : 1 + bits) . + if (((hvc_enable = (vec_of_bits [B0] : 1 words$word)))) then AArch64_UndefinedFault () + else AArch64_CallHypervisor imm))))`; + + +(*val system_exceptions_runtime_hvc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_runtime_hvc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (imm : 16 bits) = imm16 in + aarch64_system_exceptions_runtime_hvc imm)))`; + + +(*val aarch64_memory_single_general_register : forall 'regsize. Size 'regsize => AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> itself 'regsize -> ii -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_register:AccType -> int -> ExtendType -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__40 extend_type m memop n postindex regsize shift signed t wback__arg= + (if (((l__40 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (offset : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__5 : + 'regsize words$word) . + aset_X t w__5) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__6 : + 'regsize words$word) . + aset_X t w__6)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))) + else if (((l__40 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (offset : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__12 : 16 + bits) . + let data = w__12 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__13 : + 'regsize words$word) . + aset_X t w__13) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))) + else if (((l__40 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (offset : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__20 : 32 + bits) . + let data = w__20 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__21 : + 'regsize words$word) . + aset_X t w__21) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__22 : + 'regsize words$word) . + aset_X t w__22)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))) + else if (((l__40 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (offset : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__28 : 64 + bits) . + let data = w__28 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__30 : + 'regsize words$word) . + aset_X t w__30)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))) + else if (((l__40 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (ExtendReg (( 64 : int):ii) m extend_type shift : ( 64 words$word) M) (\ (offset : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__36 : 128 + bits) . + let data = w__36 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__37 : + 'regsize words$word) . + aset_X t w__37) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__38 : + 'regsize words$word) . + aset_X t w__38)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__40 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_single_general_immediate_unsigned : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_immediate_unsigned:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__35 memop n offset postindex regsize signed t wback__arg= + (if (((l__35 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__5 : + 'regsize words$word) . + aset_X t w__5) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__6 : + 'regsize words$word) . + aset_X t w__6)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__35 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__12 : 16 + bits) . + let data = w__12 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__13 : + 'regsize words$word) . + aset_X t w__13) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__35 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__20 : 32 + bits) . + let data = w__20 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__21 : + 'regsize words$word) . + aset_X t w__21) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__22 : + 'regsize words$word) . + aset_X t w__22)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__35 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__28 : 64 + bits) . + let data = w__28 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__30 : + 'regsize words$word) . + aset_X t w__30)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__35 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__36 : 128 + bits) . + let data = w__36 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__37 : + 'regsize words$word) . + aset_X t w__37) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__38 : + 'regsize words$word) . + aset_X t w__38)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__35 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_single_general_immediate_signed_postidx : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_immediate_signed_postidx:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__30 memop n offset postindex regsize signed t wback__arg= + (if (((l__30 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__5 : + 'regsize words$word) . + aset_X t w__5) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__6 : + 'regsize words$word) . + aset_X t w__6)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__30 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__12 : 16 + bits) . + let data = w__12 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__13 : + 'regsize words$word) . + aset_X t w__13) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__30 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__20 : 32 + bits) . + let data = w__20 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__21 : + 'regsize words$word) . + aset_X t w__21) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__22 : + 'regsize words$word) . + aset_X t w__22)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__30 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__28 : 64 + bits) . + let data = w__28 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__30 : + 'regsize words$word) . + aset_X t w__30)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__30 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__36 : 128 + bits) . + let data = w__36 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__37 : + 'regsize words$word) . + aset_X t w__37) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__38 : + 'regsize words$word) . + aset_X t w__38)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__30 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_single_general_immediate_signed_pac : ii -> mword ty64 -> ii -> bool -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_immediate_signed_pac:int ->(64)words$word -> int -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n offset t use_key_a wback__arg= + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((wback /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_WBSUPPRESS))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (case c of + Constraint_WBSUPPRESS => + let (wback : bool) = F in + sail2_state_monad$returnS (wb_unknown, wback) + | Constraint_UNKNOWN => + let (wb_unknown : bool) = T in + sail2_state_monad$returnS (wb_unknown, wback) + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (wb_unknown, wback)) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS (wb_unknown, wback)) + ) + else sail2_state_monad$returnS (wb_unknown, wback)) (\ varstup . let ((wb_unknown : bool), (wback : bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (if use_key_a then sail2_state_monad$bindS + (aget_X (( 64 : int):ii) (( 31 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + (AuthDA address w__2 : ( 64 words$word) M)) + else sail2_state_monad$bindS + (aget_X (( 64 : int):ii) (( 31 : int):ii) : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + (AuthDB address w__4 : ( 64 words$word) M))) (\ (address : 64 bits) . + let address = ((add_vec address offset : 64 words$word)) in sail2_state_monad$bindS + (aget_Mem address (( 8 : int):ii) AccType_NORMAL : ( 64 words$word) M) (\ (w__6 : 64 bits) . + let data = w__6 in sail2_state_monad$seqS + (aset_X t data) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))))`; + + +(*val aarch64_memory_single_general_immediate_signed_offset_unpriv : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_immediate_signed_offset_unpriv:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__25 memop n offset postindex regsize signed t wback__arg= + (if (((l__25 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__5 : + 'regsize words$word) . + aset_X t w__5) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__6 : + 'regsize words$word) . + aset_X t w__6)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__25 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__12 : 16 + bits) . + let data = w__12 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__13 : + 'regsize words$word) . + aset_X t w__13) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__25 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__20 : 32 + bits) . + let data = w__20 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__21 : + 'regsize words$word) . + aset_X t w__21) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__22 : + 'regsize words$word) . + aset_X t w__22)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__25 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__28 : 64 + bits) . + let data = w__28 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__30 : + 'regsize words$word) . + aset_X t w__30)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__25 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__36 : 128 + bits) . + let data = w__36 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__37 : + 'regsize words$word) . + aset_X t w__37) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__38 : + 'regsize words$word) . + aset_X t w__38)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__25 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_single_general_immediate_signed_offset_normal : forall 'regsize. Size 'regsize => AccType -> ii -> MemOp -> ii -> mword ty64 -> bool -> itself 'regsize -> bool -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_single_general_immediate_signed_offset_normal:AccType -> int -> MemOp -> int ->(64)words$word -> bool -> 'regsize itself -> bool -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype l__20 memop n offset postindex regsize signed t wback__arg= + (if (((l__20 = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + aset_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 8 : int):ii) / (( 8 : int):ii))) acctype : ( 8 words$word) M) (\ (w__4 : 8 + bits) . + let data = w__4 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__5 : + 'regsize words$word) . + aset_X t w__5) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__6 : + 'regsize words$word) . + aset_X t w__6)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__20 = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + aset_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 16 : int):ii) / (( 8 : int):ii))) acctype : ( 16 words$word) M) (\ (w__12 : 16 + bits) . + let data = w__12 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__13 : + 'regsize words$word) . + aset_X t w__13) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__20 = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + aset_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 32 : int):ii) / (( 8 : int):ii))) acctype : ( 32 words$word) M) (\ (w__20 : 32 + bits) . + let data = w__20 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__21 : + 'regsize words$word) . + aset_X t w__21) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__22 : + 'regsize words$word) . + aset_X t w__22)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__20 = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + aset_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 64 : int):ii) / (( 8 : int):ii))) acctype : ( 64 words$word) M) (\ (w__28 : 64 + bits) . + let data = w__28 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__30 : + 'regsize words$word) . + aset_X t w__30)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else if (((l__20 = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (wb_unknown : bool) = F in + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (undefined_Constraint () ) (\ (c : Constraint) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_WBSUPPRESS in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_WBSUPPRESS = Constraint_WBSUPPRESS))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNKNOWN))) \/ ((((((Constraint_WBSUPPRESS = Constraint_UNDEF))) \/ (((Constraint_WBSUPPRESS = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS wback) (\ (wback : bool) . sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ (((n = t)))))) /\ (((n <> (( 31 : int):ii))))))) then + let c = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS + (if (((memop <> MemOp_PREFETCH))) then CheckSPAlignment () + else sail2_state_monad$returnS () ) + (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + aset_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype data) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem address (((( 128 : int):ii) / (( 8 : int):ii))) acctype : ( 128 words$word) M) (\ (w__36 : 128 + bits) . + let data = w__36 in + if signed then sail2_state_monad$bindS + (SignExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__37 : + 'regsize words$word) . + aset_X t w__37) + else sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__38 : + 'regsize words$word) . + aset_X t w__38)) + | MemOp_PREFETCH => + Prefetch address + ((GetSlice_int ((make_the_value (( 5 : int):ii) : 5 itself)) t (( 0 : int):ii) : 5 words$word)) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () ))))))))) + else + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((l__20 / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val aarch64_memory_pair_simdfp_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_pair_simdfp_postidx:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (case c of + Constraint_UNKNOWN => sail2_state_monad$returnS T + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown) + ) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V ((int_of_num (words$word_len data1))) t : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . + let data1 = w__2 in sail2_state_monad$bindS + (aget_V ((int_of_num (words$word_len data1))) t2 : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . + let data2 = w__3 in sail2_state_monad$seqS + (aset_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype data1) + (aset_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype data2))) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__4 : 'datasize + bits) . + let data1 = w__4 in sail2_state_monad$bindS + (aget_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__5 : 'datasize + bits) . + let data2 = w__5 in sail2_state_monad$bindS + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__6 : 'datasize + bits) . + let data1 = w__6 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__7 : 'datasize + bits) . + let (data2 : 'datasize bits) = w__7 in + sail2_state_monad$returnS (data1, data2))) + else sail2_state_monad$returnS (data1, data2)) (\ varstup . let ((data1 : 'datasize bits), (data2 : 'datasize + bits)) = varstup in sail2_state_monad$seqS + (aset_V t data1) (aset_V t2 data2)))) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))))))`; + + +(*val aarch64_memory_pair_simdfp_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_pair_simdfp_noalloc:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (CheckFPAdvSIMDEnabled64 () )) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (case c of + Constraint_UNKNOWN => sail2_state_monad$returnS T + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown) + ) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (aget_V ((int_of_num (words$word_len data1))) t : ( 'datasize words$word) M) (\ (w__2 : 'datasize bits) . + let data1 = w__2 in sail2_state_monad$bindS + (aget_V ((int_of_num (words$word_len data1))) t2 : ( 'datasize words$word) M) (\ (w__3 : 'datasize bits) . + let data2 = w__3 in sail2_state_monad$seqS + (aset_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype data1) + (aset_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype data2))) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__4 : 'datasize + bits) . + let data1 = w__4 in sail2_state_monad$bindS + (aget_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__5 : 'datasize + bits) . + let data2 = w__5 in sail2_state_monad$bindS + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__6 : 'datasize + bits) . + let data1 = w__6 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__7 : 'datasize + bits) . + let (data2 : 'datasize bits) = w__7 in + sail2_state_monad$returnS (data1, data2))) + else sail2_state_monad$returnS (data1, data2)) (\ varstup . let ((data1 : 'datasize bits), (data2 : 'datasize + bits)) = varstup in sail2_state_monad$seqS + (aset_V t data1) (aset_V t2 data2)))) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))))))`; + + +(*val aarch64_memory_pair_general_postidx : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> bool -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_pair_general_postidx:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex signed t t2 wback__arg= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (let wback = wback__arg in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . + let (rt_unknown : bool) = F in + let (wb_unknown : bool) = F in sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_LOAD))) /\ wback))) /\ ((((((t = n))) \/ (((t2 = n))))))))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPLD) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_WBSUPPRESS))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (case c of + Constraint_WBSUPPRESS => + let (wback : bool) = F in + sail2_state_monad$returnS (wb_unknown, wback) + | Constraint_UNKNOWN => + let (wb_unknown : bool) = T in + sail2_state_monad$returnS (wb_unknown, wback) + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (wb_unknown, wback)) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS (wb_unknown, wback)) + ) + else sail2_state_monad$returnS (wb_unknown, wback)) (\ varstup . let ((wb_unknown : bool), (wback : bool)) = varstup in sail2_state_monad$bindS + (if ((((((((((((memop = MemOp_STORE))) /\ wback))) /\ ((((((t = n))) \/ (((t2 = n))))))))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_WBOVERLAPST) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_NONE))) \/ ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP)))))))))))) "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (case c of + Constraint_NONE => sail2_state_monad$returnS F + | Constraint_UNKNOWN => sail2_state_monad$returnS T + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown) + ) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (case c of + Constraint_UNKNOWN => sail2_state_monad$returnS T + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown) + ) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if (((rt_unknown /\ (((t = n)))))) then + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) + else (aget_X ((int_of_num (words$word_len data1))) t : ( 'datasize words$word) M)) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (if (((rt_unknown /\ (((t2 = n)))))) then + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) + else (aget_X ((int_of_num (words$word_len data1))) t2 : ( 'datasize words$word) M)) (\ (data2 : 'datasize bits) . sail2_state_monad$seqS + (aset_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype data1) + (aset_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype data2))) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__6 : 'datasize + bits) . + let data1 = w__6 in sail2_state_monad$bindS + (aget_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__7 : 'datasize + bits) . + let data2 = w__7 in sail2_state_monad$bindS + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__8 : 'datasize + bits) . + let data1 = w__8 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__9 : 'datasize + bits) . + let (data2 : 'datasize bits) = w__9 in + sail2_state_monad$returnS (data1, data2))) + else sail2_state_monad$returnS (data1, data2)) (\ varstup . let ((data1 : 'datasize bits), (data2 : 'datasize + bits)) = varstup in + if signed then sail2_state_monad$bindS + (SignExtend__0 data1 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__10 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__10) + (SignExtend__0 data2 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M)) (\ (w__11 : + 64 words$word) . + aset_X t2 w__11)) + else sail2_state_monad$seqS (aset_X t data1) (aset_X t2 data2)))) + ) + (if wback then sail2_state_monad$bindS + (if wb_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + sail2_state_monad$returnS address) (\ (address : 64 bits) . + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address) + else sail2_state_monad$returnS () )))))))))))`; + + +(*val aarch64_memory_pair_general_noalloc : forall 'datasize. Size 'datasize => AccType -> itself 'datasize -> MemOp -> ii -> mword ty64 -> bool -> ii -> ii -> bool -> M unit*) + +val _ = Define ` + ((aarch64_memory_pair_general_noalloc:AccType -> 'datasize itself -> MemOp -> int ->(64)words$word -> bool -> int -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype datasize memop n offset postindex t t2 wback= + (let datasize = (size_itself_int datasize) in + let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector datasize : ( 'datasize words$word) M) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (data2 : 'datasize bits) . + let (rt_unknown : bool) = F in sail2_state_monad$bindS + (if ((((((memop = MemOp_LOAD))) /\ (((t = t2)))))) then + let (c : Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((c = Constraint_UNKNOWN))) \/ ((((((c = Constraint_UNDEF))) \/ (((c = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (case c of + Constraint_UNKNOWN => sail2_state_monad$returnS T + | Constraint_UNDEF => sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS rt_unknown) + | Constraint_NOP => sail2_state_monad$seqS (EndOfInstruction () ) (sail2_state_monad$returnS rt_unknown) + ) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . + let (address : 64 bits) = + (if ((~ postindex)) then (add_vec address offset : 64 words$word) + else address) in sail2_state_monad$seqS + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if (((rt_unknown /\ (((t = n)))))) then + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) + else (aget_X ((int_of_num (words$word_len data1))) t : ( 'datasize words$word) M)) (\ (data1 : 'datasize bits) . sail2_state_monad$bindS + (if (((rt_unknown /\ (((t2 = n)))))) then + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) + else (aget_X ((int_of_num (words$word_len data1))) t2 : ( 'datasize words$word) M)) (\ (data2 : 'datasize bits) . sail2_state_monad$seqS + (aset_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype data1) + (aset_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype data2))) + | MemOp_LOAD => sail2_state_monad$bindS + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__6 : 'datasize + bits) . + let data1 = w__6 in sail2_state_monad$bindS + (aget_Mem ((add_vec_int address dbytes : 64 words$word)) dbytes acctype : ( 'datasize words$word) M) (\ (w__7 : 'datasize + bits) . + let data2 = w__7 in sail2_state_monad$bindS + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__8 : 'datasize + bits) . + let data1 = w__8 in sail2_state_monad$bindS + (undefined_bitvector ((int_of_num (words$word_len data1))) : ( 'datasize words$word) M) (\ (w__9 : 'datasize + bits) . + let (data2 : 'datasize bits) = w__9 in + sail2_state_monad$returnS (data1, data2))) + else sail2_state_monad$returnS (data1, data2)) (\ varstup . let ((data1 : 'datasize bits), (data2 : 'datasize + bits)) = varstup in sail2_state_monad$seqS + (aset_X t data1) (aset_X t2 data2)))) + ) + (if wback then + let (address : 64 bits) = + (if postindex then (add_vec address offset : 64 words$word) + else address) in + if (((n = (( 31 : int):ii)))) then aset_SP address + else aset_X n address + else sail2_state_monad$returnS () ))))))))`; + + +(*val aarch64_memory_exclusive_single : forall 'datasize 'regsize. Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_exclusive_single:AccType -> 'datasize itself -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype p_1 elsize memop n pair regsize s t t2= + (if (((((size_itself_int p_1)) = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else if pair then + let v = (ex_int (((( 8 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t : ( 4 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t2 : ( 4 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__4 : bool) . + let (data : 8 bits) = + (if w__4 then (concat_vec el1 el2 : 8 words$word) + else (concat_vec el2 el1 : 8 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__6 : bool) . sail2_state_monad$bindS + (if w__6 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__8 : + 32 words$word) . + aset_X s w__8)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__9 : 32 bits) . + aset_X t w__9) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__10 : FaultRecord) . + AArch64_Abort address w__10) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__11 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__11) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__12 : + 64 words$word) . + aset_X t2 w__12))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 8 words$word) M) (\ (w__13 : 8 bits) . + let data = w__13 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14))) + )))))))) + else if (((((size_itself_int p_1)) = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else if pair then + let v = (ex_int (((( 16 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 8 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 8 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__19 : bool) . + let (data : 16 bits) = + (if w__19 then (concat_vec el1 el2 : 16 words$word) + else (concat_vec el2 el1 : 16 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__21 : bool) . sail2_state_monad$bindS + (if w__21 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__23 : + 32 words$word) . + aset_X s w__23)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__24 : 32 bits) . + aset_X t w__24) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__25 : FaultRecord) . + AArch64_Abort address w__25) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__26 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__26) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__27 : + 64 words$word) . + aset_X t2 w__27))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 16 words$word) M) (\ (w__28 : 16 bits) . + let data = w__28 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29))) + )))))))) + else if (((((size_itself_int p_1)) = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else if pair then + let v = (ex_int (((( 32 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 16 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 16 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__34 : bool) . + let (data : 32 bits) = + (if w__34 then (concat_vec el1 el2 : 32 words$word) + else (concat_vec el2 el1 : 32 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__36 : bool) . sail2_state_monad$bindS + (if w__36 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__38 : + 32 words$word) . + aset_X s w__38)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__39 : 32 bits) . + aset_X t w__39) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__40 : FaultRecord) . + AArch64_Abort address w__40) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__41 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__41) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__42 : + 64 words$word) . + aset_X t2 w__42))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 32 words$word) M) (\ (w__43 : 32 bits) . + let data = w__43 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__44 : + 'regsize words$word) . + aset_X t w__44))) + )))))))) + else if (((((size_itself_int p_1)) = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if pair then + let v = (ex_int (((( 64 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 32 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 32 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__49 : bool) . + let (data : 64 bits) = + (if w__49 then (concat_vec el1 el2 : 64 words$word) + else (concat_vec el2 el1 : 64 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__51 : bool) . sail2_state_monad$bindS + (if w__51 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__53 : + 32 words$word) . + aset_X s w__53)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__54 : 32 bits) . + aset_X t w__54) + else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 64 words$word) M) (\ (w__55 : 64 bits) . + let data = w__55 in sail2_state_monad$bindS + (BigEndian () ) (\ (w__56 : bool) . + if w__56 then sail2_state_monad$seqS + (aset_X t + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii))) : 32 words$word))) + (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + else sail2_state_monad$seqS + (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + (aset_X t2 + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii))) : 32 words$word))))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__57 : FaultRecord) . + AArch64_Abort address w__57) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__58 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__58) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__59 : + 64 words$word) . + aset_X t2 w__59))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 64 words$word) M) (\ (w__60 : 64 bits) . + let data = w__60 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__61 : + 'regsize words$word) . + aset_X t w__61))) + )))))))) + else if (((((size_itself_int p_1)) = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else if pair then + let v = (ex_int (((( 128 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X ((int_of_num (words$word_len address))) t : ( 64 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len address))) t2 : ( 64 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__66 : bool) . + let (data : 128 bits) = + (if w__66 then (concat_vec el1 el2 : 128 words$word) + else (concat_vec el2 el1 : 128 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__68 : bool) . sail2_state_monad$bindS + (if w__68 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__70 : + 32 words$word) . + aset_X s w__70)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__71 : 32 bits) . + aset_X t w__71) + else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 128 words$word) M) (\ (w__72 : 128 bits) . + let data = w__72 in sail2_state_monad$bindS + (BigEndian () ) (\ (w__73 : bool) . + if w__73 then sail2_state_monad$seqS + (aset_X t + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii))) : 96 words$word))) + (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + else sail2_state_monad$seqS + (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + (aset_X t2 + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii))) : 96 words$word))))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__74 : FaultRecord) . + AArch64_Abort address w__74) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__75 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__75) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__76 : + 64 words$word) . + aset_X t2 w__76))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 128 words$word) M) (\ (w__77 : 128 bits) . + let data = w__77 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__78 : + 'regsize words$word) . + aset_X t w__78))) + )))))))) + else + let regsize = (size_itself_int regsize) in + let datasize = (size_itself_int p_1) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "destsize constraint") + (let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val memory_exclusive_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_exclusive_single_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 8 : int):ii) : 8 itself)) (( 8 : int):ii) memop n + F ((make_the_value (( 32 : int):ii) : 32 itself)) s t t2) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 16 : int):ii) : 16 itself)) (( 16 : int):ii) memop + n F ((make_the_value (( 32 : int):ii) : 32 itself)) s t t2) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 32 : int):ii) : 32 itself)) (( 32 : int):ii) memop + n F ((make_the_value (( 32 : int):ii) : 32 itself)) s t t2) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_exclusive_single acctype ((make_the_value (( 64 : int):ii) : 64 itself)) (( 64 : int):ii) memop + n F ((make_the_value (( 64 : int):ii) : 64 itself)) s t t2)))`; + + +(*val aarch64_memory_exclusive_pair : forall 'datasize 'regsize . Size 'datasize, Size 'regsize => AccType -> itself 'datasize -> integer -> MemOp -> ii -> bool -> itself 'regsize -> ii -> ii -> ii -> M unit*) + +val _ = Define ` + ((aarch64_memory_exclusive_pair:AccType -> 'datasize itself -> int -> MemOp -> int -> bool -> 'regsize itself -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) acctype p_1 elsize memop n pair regsize s t t2= + (if (((((size_itself_int p_1)) = (( 8 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 8 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) (\ (data : 8 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 8 : int):ii) : ( 8 words$word) M) + else if pair then + let v = (ex_int (((( 8 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t : ( 4 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len DebugException_VectorCatch))) t2 : ( 4 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__4 : bool) . + let (data : 8 bits) = + (if w__4 then (concat_vec el1 el2 : 8 words$word) + else (concat_vec el2 el1 : 8 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 8 : int):ii) t : ( 8 words$word) M)) (\ (data : 8 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__6 : bool) . sail2_state_monad$bindS + (if w__6 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__8 : + 32 words$word) . + aset_X s w__8)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__9 : 32 bits) . + aset_X t w__9) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__10 : FaultRecord) . + AArch64_Abort address w__10) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__11 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__11) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__12 : + 64 words$word) . + aset_X t2 w__12))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 8 words$word) M) (\ (w__13 : 8 bits) . + let data = w__13 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__14 : + 'regsize words$word) . + aset_X t w__14))) + )))))))) + else if (((((size_itself_int p_1)) = (( 16 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 16 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) (\ (data : 16 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 16 : int):ii) : ( 16 words$word) M) + else if pair then + let v = (ex_int (((( 16 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 8 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 8 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__19 : bool) . + let (data : 16 bits) = + (if w__19 then (concat_vec el1 el2 : 16 words$word) + else (concat_vec el2 el1 : 16 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 16 : int):ii) t : ( 16 words$word) M)) (\ (data : 16 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__21 : bool) . sail2_state_monad$bindS + (if w__21 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__23 : + 32 words$word) . + aset_X s w__23)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__24 : 32 bits) . + aset_X t w__24) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__25 : FaultRecord) . + AArch64_Abort address w__25) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__26 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__26) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__27 : + 64 words$word) . + aset_X t2 w__27))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 16 words$word) M) (\ (w__28 : 16 bits) . + let data = w__28 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__29 : + 'regsize words$word) . + aset_X t w__29))) + )))))))) + else if (((((size_itself_int p_1)) = (( 32 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 32 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (data : 32 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) + else if pair then + let v = (ex_int (((( 32 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 16 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 16 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__34 : bool) . + let (data : 32 bits) = + (if w__34 then (concat_vec el1 el2 : 32 words$word) + else (concat_vec el2 el1 : 32 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 32 : int):ii) t : ( 32 words$word) M)) (\ (data : 32 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__36 : bool) . sail2_state_monad$bindS + (if w__36 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__38 : + 32 words$word) . + aset_X s w__38)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__39 : 32 bits) . + aset_X t w__39) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__40 : FaultRecord) . + AArch64_Abort address w__40) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__41 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__41) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__42 : + 64 words$word) . + aset_X t2 w__42))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 32 words$word) M) (\ (w__43 : 32 bits) . + let data = w__43 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__44 : + 'regsize words$word) . + aset_X t w__44))) + )))))))) + else if (((((size_itself_int p_1)) = (( 64 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 64 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (data : 64 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else if pair then + let v = (ex_int (((( 64 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X v t : ( 32 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len el1))) t2 : ( 32 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__49 : bool) . + let (data : 64 bits) = + (if w__49 then (concat_vec el1 el2 : 64 words$word) + else (concat_vec el2 el1 : 64 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 64 : int):ii) t : ( 64 words$word) M)) (\ (data : 64 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__51 : bool) . sail2_state_monad$bindS + (if w__51 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__53 : + 32 words$word) . + aset_X s w__53)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__54 : 32 bits) . + aset_X t w__54) + else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 64 words$word) M) (\ (w__55 : 64 bits) . + let data = w__55 in sail2_state_monad$bindS + (BigEndian () ) (\ (w__56 : bool) . + if w__56 then sail2_state_monad$seqS + (aset_X t + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii))) : 32 words$word))) + (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + else sail2_state_monad$seqS + (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + (aset_X t2 + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 64 : int):ii))) : 32 words$word))))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__57 : FaultRecord) . + AArch64_Abort address w__57) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__58 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__58) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__59 : + 64 words$word) . + aset_X t2 w__59))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 64 words$word) M) (\ (w__60 : 64 bits) . + let data = w__60 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__61 : + 'regsize words$word) . + aset_X t w__61))) + )))))))) + else if (((((size_itself_int p_1)) = (( 128 : int):ii)))) then + let regsize = (size_itself_int regsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int (((( 128 : int):ii) / (( 8 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (sail2_state_monad$assert_expS T "dbytes constraint")) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) (\ (data : 128 bits) . + let (rt_unknown : bool) = F in + let (rn_unknown : bool) = F in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((((((((memop = MemOp_LOAD))) /\ pair))) /\ (((t = t2)))))) then + let (c : Constraint) = Constraint_UNDEF in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_UNDEF = Constraint_UNKNOWN))) \/ ((((((Constraint_UNDEF = Constraint_UNDEF))) \/ (((Constraint_UNDEF = Constraint_NOP))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP)))") + (UnallocatedEncoding () ) + else sail2_state_monad$returnS () ) + (if (((memop = MemOp_STORE))) then sail2_state_monad$bindS + (if ((((((s = t))) \/ (((pair /\ (((s = t2))))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rt_unknown) (\ (rt_unknown : bool) . sail2_state_monad$bindS + (if ((((((s = n))) /\ (((n <> (( 31 : int):ii))))))) then + let (c : Constraint) = Constraint_NONE in sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((((((Constraint_NONE = Constraint_UNKNOWN))) \/ ((((((Constraint_NONE = Constraint_NONE))) \/ ((((((Constraint_NONE = Constraint_UNDEF))) \/ (((Constraint_NONE = Constraint_NOP)))))))))))) "((c == Constraint_UNKNOWN) || ((c == Constraint_NONE) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))") + (sail2_state_monad$returnS F) + else sail2_state_monad$returnS rn_unknown) (\ (rn_unknown : bool) . + sail2_state_monad$returnS (rn_unknown, rt_unknown))) + else sail2_state_monad$returnS (rn_unknown, rt_unknown))) (\ varstup . let ((rn_unknown : bool), (rt_unknown : + bool)) = varstup in sail2_state_monad$bindS + (if (((n = (( 31 : int):ii)))) then sail2_state_monad$seqS (CheckSPAlignment () ) (aget_SP (( 64 : int):ii) () : ( 64 words$word) M) + else if rn_unknown then (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) + else (aget_X (( 64 : int):ii) n : ( 64 words$word) M)) (\ (address : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (secondstage : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (iswrite : bool) . + (case memop of + MemOp_STORE => sail2_state_monad$bindS + (if rt_unknown then (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M) + else if pair then + let v = (ex_int (((( 128 : int):ii) / (( 2 : int):ii)))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aget_X ((int_of_num (words$word_len address))) t : ( 64 words$word) M)) (\ el1 . sail2_state_monad$bindS + (aget_X ((int_of_num (words$word_len address))) t2 : ( 64 words$word) M) (\ el2 . sail2_state_monad$bindS + (BigEndian () ) (\ (w__66 : bool) . + let (data : 128 bits) = + (if w__66 then (concat_vec el1 el2 : 128 words$word) + else (concat_vec el2 el1 : 128 words$word)) in + sail2_state_monad$returnS data))) + else (aget_X (( 128 : int):ii) t : ( 128 words$word) M)) (\ (data : 128 bits) . + let (status : 1 bits) = ((vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (AArch64_ExclusiveMonitorsPass address dbytes) (\ (w__68 : bool) . sail2_state_monad$bindS + (if w__68 then sail2_state_monad$seqS + (aset_Mem address dbytes acctype data) (ExclusiveMonitorsStatus () : ( 1 words$word) M) + else sail2_state_monad$returnS status) (\ (status : 1 bits) . sail2_state_monad$bindS + (ZeroExtend__0 status ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) (\ (w__70 : + 32 words$word) . + aset_X s w__70)))) + | MemOp_LOAD => sail2_state_monad$seqS + (AArch64_SetExclusiveMonitors address dbytes) + (if pair then sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "datasize constraint") + (if rt_unknown then sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (w__71 : 32 bits) . + aset_X t w__71) + else if (((elsize = (( 32 : int):ii)))) then sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 128 words$word) M) (\ (w__72 : 128 bits) . + let data = w__72 in sail2_state_monad$bindS + (BigEndian () ) (\ (w__73 : bool) . + if w__73 then sail2_state_monad$seqS + (aset_X t + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii))) : 96 words$word))) + (aset_X t2 ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + else sail2_state_monad$seqS + (aset_X t ((slice data (( 0 : int):ii) (( 32 : int):ii) : 32 words$word))) + (aset_X t2 + ((slice data (( 32 : int):ii) ((((~ (( 32 : int):ii))) + (( 128 : int):ii))) : 96 words$word))))) + else sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((address <> ((Align__1 address dbytes : 64 words$word))))) then + let iswrite = F in + let secondstage = F in sail2_state_monad$bindS + (AArch64_AlignmentFault acctype F F) (\ (w__74 : FaultRecord) . + AArch64_Abort address w__74) + else sail2_state_monad$returnS () ) + (aget_Mem ((add_vec_int address (( 0 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__75 : + 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (aset_X t w__75) + (aget_Mem ((add_vec_int address (( 8 : int):ii) : 64 words$word)) (( 8 : int):ii) acctype : ( 64 words$word) M)) (\ (w__76 : + 64 words$word) . + aset_X t2 w__76))) + else sail2_state_monad$bindS + (aget_Mem address dbytes acctype : ( 128 words$word) M) (\ (w__77 : 128 bits) . + let data = w__77 in sail2_state_monad$bindS + (ZeroExtend__0 data ((make_the_value regsize : 'regsize itself)) : ( 'regsize words$word) M) (\ (w__78 : + 'regsize words$word) . + aset_X t w__78))) + )))))))) + else + let regsize = (size_itself_int regsize) in + let datasize = (size_itself_int p_1) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "regsize constraint") + (let dbytes = (ex_int ((datasize / (( 8 : int):ii)))) in + sail2_state_monad$assert_expS T "datasize constraint")))`; + + +(*val memory_exclusive_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_exclusive_pair_decode:(1)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_exclusive_pair acctype ((make_the_value (( 64 : int):ii) : 64 itself)) (( 32 : int):ii) memop n + T ((make_the_value (( 32 : int):ii) : 32 itself)) s t t2) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (s : ii) = (lem$w2ui Rs) in + let (acctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDERED + else AccType_ATOMIC) in + let (pair : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (elsize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (datasize : ii) = ((( 128 : int):ii)) in + aarch64_memory_exclusive_pair acctype ((make_the_value (( 128 : int):ii) : 128 itself)) (( 64 : int):ii) memop + n T ((make_the_value (( 64 : int):ii) : 64 itself)) s t t2)))`; + + +(*val aarch64_integer_crc : bool -> ii -> ii -> ii -> integer -> M unit*) + +val _ = Define ` + ((aarch64_integer_crc:bool -> int -> int -> int -> int ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) crc32c d m n l__16= + (if (((l__16 = (( 8 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (acc : 32 bits) . sail2_state_monad$bindS + (aget_X (( 8 : int):ii) m : ( 8 words$word) M) (\ (val_name : 8 bits) . + let (poly : 32 bits) = + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) + (if crc32c then (( 517762881 : int):ii) + else (( 79764919 : int):ii)) (( 0 : int):ii) + : 32 words$word)) in sail2_state_monad$bindS + (BitReverse acc : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + let (tempacc : 40 bits) = + ((concat_vec w__0 ((Zeros__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) + : 40 words$word)) in sail2_state_monad$bindS + (BitReverse val_name : ( 8 words$word) M) (\ (w__1 : 8 words$word) . + let (tempval : 40 bits) = + ((concat_vec w__1 ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 40 words$word)) in sail2_state_monad$bindS + (Poly32Mod2 ((xor_vec tempacc tempval : 40 words$word)) poly : ( 32 words$word) M) (\ (w__2 : + 32 words$word) . sail2_state_monad$bindS + (BitReverse w__2 : ( 32 words$word) M) (\ (w__3 : 32 words$word) . aset_X d w__3)))))) + else if (((l__16 = (( 16 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (acc : 32 bits) . sail2_state_monad$bindS + (aget_X (( 16 : int):ii) m : ( 16 words$word) M) (\ (val_name : 16 bits) . + let (poly : 32 bits) = + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) + (if crc32c then (( 517762881 : int):ii) + else (( 79764919 : int):ii)) (( 0 : int):ii) + : 32 words$word)) in sail2_state_monad$bindS + (BitReverse acc : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + let (tempacc : 48 bits) = + ((concat_vec w__4 ((Zeros__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + : 48 words$word)) in sail2_state_monad$bindS + (BitReverse val_name : ( 16 words$word) M) (\ (w__5 : 16 words$word) . + let (tempval : 48 bits) = + ((concat_vec w__5 ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 48 words$word)) in sail2_state_monad$bindS + (Poly32Mod2 ((xor_vec tempacc tempval : 48 words$word)) poly : ( 32 words$word) M) (\ (w__6 : + 32 words$word) . sail2_state_monad$bindS + (BitReverse w__6 : ( 32 words$word) M) (\ (w__7 : 32 words$word) . aset_X d w__7)))))) + else if (((l__16 = (( 32 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (acc : 32 bits) . sail2_state_monad$bindS + (aget_X (( 32 : int):ii) m : ( 32 words$word) M) (\ (val_name : 32 bits) . + let (poly : 32 bits) = + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) + (if crc32c then (( 517762881 : int):ii) + else (( 79764919 : int):ii)) (( 0 : int):ii) + : 32 words$word)) in sail2_state_monad$bindS + (BitReverse acc : ( 32 words$word) M) (\ (w__8 : 32 words$word) . + let (tempacc : 64 bits) = + ((concat_vec w__8 ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (BitReverse val_name : ( 32 words$word) M) (\ (w__9 : 32 words$word) . + let (tempval : 64 bits) = + ((concat_vec w__9 ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (Poly32Mod2 ((xor_vec tempacc tempval : 64 words$word)) poly : ( 32 words$word) M) (\ (w__10 : + 32 words$word) . sail2_state_monad$bindS + (BitReverse w__10 : ( 32 words$word) M) (\ (w__11 : 32 words$word) . aset_X d w__11)))))) + else if (((l__16 = (( 64 : int):ii)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (if ((~ ((HaveCRCExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aget_X (( 32 : int):ii) n : ( 32 words$word) M)) (\ (acc : 32 bits) . sail2_state_monad$bindS + (aget_X (( 64 : int):ii) m : ( 64 words$word) M) (\ (val_name : 64 bits) . + let (poly : 32 bits) = + ((GetSlice_int ((make_the_value (( 32 : int):ii) : 32 itself)) + (if crc32c then (( 517762881 : int):ii) + else (( 79764919 : int):ii)) (( 0 : int):ii) + : 32 words$word)) in sail2_state_monad$bindS + (BitReverse acc : ( 32 words$word) M) (\ (w__12 : 32 words$word) . + let (tempacc : 96 bits) = + ((concat_vec w__12 ((Zeros__0 ((make_the_value (( 64 : int):ii) : 64 itself)) : 64 words$word)) + : 96 words$word)) in sail2_state_monad$bindS + (BitReverse val_name : ( 64 words$word) M) (\ (w__13 : 64 words$word) . + let (tempval : 96 bits) = + ((concat_vec w__13 ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 96 words$word)) in sail2_state_monad$bindS + (Poly32Mod2 ((xor_vec tempacc tempval : 96 words$word)) poly : ( 32 words$word) M) (\ (w__14 : + 32 words$word) . sail2_state_monad$bindS + (BitReverse w__14 : ( 32 words$word) M) (\ (w__15 : 32 words$word) . aset_X d w__15)))))) + else sail2_state_monad$assert_expS T ""))`; + + +(*val system_exceptions_debug_exception_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_debug_exception_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (target_level : 2 bits) = LL in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((LL = (vec_of_bits [B0;B0] : 2 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (Halted () )) (\ (w__0 : bool) . sail2_state_monad$seqS + (if ((~ w__0)) then AArch64_UndefinedFault () + else sail2_state_monad$returnS () ) + (aarch64_system_exceptions_debug_exception target_level)))))`; + + +(*val system_barriers_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty2 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_barriers_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm opc Rt= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (undefined_MemBarrierOp () )) (\ (op : MemBarrierOp) . sail2_state_monad$bindS + (undefined_MBReqDomain () ) (\ (domain1 : MBReqDomain) . sail2_state_monad$bindS + (undefined_MBReqTypes () ) (\ (types : MBReqTypes) . + let b__0 = opc in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_DSB + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_DMB + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS MemBarrierOp_ISB + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS op)) (\ (op : MemBarrierOp) . + let b__3 = ((slice CRm (( 2 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let (domain1 : MBReqDomain) = + (if (((b__3 = (vec_of_bits [B0;B0] : 2 words$word)))) then MBReqDomain_OuterShareable + else if (((b__3 = (vec_of_bits [B0;B1] : 2 words$word)))) then MBReqDomain_Nonshareable + else if (((b__3 = (vec_of_bits [B1;B0] : 2 words$word)))) then MBReqDomain_InnerShareable + else MBReqDomain_FullSystem) in + let b__7 = ((slice CRm (( 0 : int):ii) (( 2 : int):ii) : 2 words$word)) in + let ((domain1 : MBReqDomain), (types : MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (types : MBReqTypes) = MBReqTypes_Reads in + (domain1, types) + else + let ((domain1 : MBReqDomain), (types : MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (types : MBReqTypes) = MBReqTypes_Writes in + (domain1, types) + else + let ((domain1 : MBReqDomain), (types : MBReqTypes)) = + (if (((b__7 = (vec_of_bits [B1;B1] : 2 words$word)))) then + let (types : MBReqTypes) = MBReqTypes_All in + (domain1, types) + else + let (types : MBReqTypes) = MBReqTypes_All in + let (domain1 : MBReqDomain) = MBReqDomain_FullSystem in + (domain1, types)) in + (domain1, types)) in + (domain1, types)) in + sail2_state_monad$returnS ((aarch64_system_barriers domain1 op types))))))))`; + + +(*val memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L R1 Rm b__1 S1 b__2 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__0 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__0 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__1 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__1 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__2 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__2 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__3 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__3 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__4 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__4 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__5 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__5 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__6 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__6 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__7 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__7 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T)) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) m memop n F ((ex_int selem)) t T))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__8 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__8 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__9 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__9 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__10 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__10 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__11 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__11 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__12 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__12 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__13 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__13 m memop n T ((ex_int selem)) t T)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__14 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__14 m memop n T ((ex_int selem)) t T)))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__15 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__15 m memop n T ((ex_int selem)) t T))))))`; + + +(*val memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode:(1)words$word ->(1)words$word ->(1)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L R1 b__1 S1 b__2 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__0 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__0 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__1 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__1 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__2 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__2 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__3 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__3 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__4 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__4 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__5 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__5 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__6 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__6 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__7 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__7 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__8 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__8 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__9 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__9 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__10 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__10 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__11 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__11 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__12 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__12 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__13 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__13 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__14 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__14 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__15 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__15 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__16 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__16 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__17 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) w__17 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__18 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__18 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__19 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) w__19 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__20 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__20 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__21 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) w__21 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__22 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__22 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 0 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__23 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 0 : int):ii) w__23 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__24 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__25 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__24 w__25 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__26 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__27 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__26 w__27 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__28 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__29 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__28 w__29 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__30 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__31 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__30 w__31 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__32 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__33 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__32 w__33 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__34 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__35 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__34 w__35 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__36 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__37 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__36 w__37 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__38 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__39 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__38 w__39 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__40 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__40 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__41 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__41 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__42 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__42 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__43 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__43 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__44 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__44 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__45 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__45 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B0] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__46 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__46 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1;B1] : 2 words$word) + : 4 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__47 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) index w__47 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__48 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__48 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__49 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__49 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__50 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__50 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__51 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__51 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__52 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__52 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B0] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__53 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__53 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__54 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__54 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = + (lem$w2ui ((concat_vec ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word)) + (vec_of_bits [B1] : 1 words$word) + : 3 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__55 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) index w__55 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__56 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__56 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__57 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) w__57 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__58 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__58 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__59 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) w__59 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . + let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__60 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__60 memop n F ((ex_int selem)) t F)))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__61 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) w__61 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let index = (lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) S1 : 2 words$word))) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__62 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) index w__62 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let index = ((( 1 : int):ii)) in + let scale = ((( 3 : int):ii)) in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__63 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) (( 1 : int):ii) w__63 memop n F ((ex_int selem)) t F))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__64 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__65 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__64 w__65 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__66 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__67 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__66 w__67 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__68 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__69 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__68 w__69 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B0] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__70 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__71 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__70 w__71 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 0 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__72 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__73 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 8 : int):ii) : 8 itself)) w__72 w__73 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 1 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__74 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__75 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 16 : int):ii) : 16 itself)) w__74 w__75 memop n T ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((b__1 = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((b__2 = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 2 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__76 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__77 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) w__76 w__77 memop n T ((ex_int selem)) t F)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (selem : ii) = + (((lem$w2ui ((concat_vec (vec_of_bits [B1] : 1 words$word) R1 : 2 words$word)))) + (( 1 : int):ii)) in + let (replicate : bool) = F in sail2_state_monad$bindS + (undefined_int () ) (\ (index : ii) . sail2_state_monad$seqS + (if ((((((L = (vec_of_bits [B0] : 1 words$word)))) \/ (((S1 = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let scale = ((( 3 : int):ii)) in + let replicate = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (w__78 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (w__79 : ii) . + aarch64_memory_vector_single_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) w__78 w__79 memop n T ((ex_int selem)) t F))))))))`; + + +(*val memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode:(2)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc Rm option_name S1 Rn Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = + (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) size1 : 3 words$word))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then scale else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + MemOp_LOAD + else MemOp_STORE) in + let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in + aarch64_memory_single_simdfp_register acctype datasize extend_type m memop n postindex shift t + wback))))`; + + +(*val memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm12 Rn Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = + (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) size1 : 3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M)) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 scale : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + MemOp_LOAD + else MemOp_STORE) in + let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback)))))`; + + +(*val memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = + (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) size1 : 3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M)) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + MemOp_LOAD + else MemOp_STORE) in + let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback))))`; + + +(*val memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = + (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) size1 : 3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M)) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + MemOp_LOAD + else MemOp_STORE) in + let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t + wback))))`; + + +(*val memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 opc imm9 Rn Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = + (lem$w2ui ((concat_vec (vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) size1 : 3 words$word))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((ex_int scale)) > (( 4 : int):ii))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M)) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if ((((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + MemOp_LOAD + else MemOp_STORE) in + let (datasize : ii) = (shl_int (( 8 : int):ii) scale) in + aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype datasize memop n offset + postindex t wback))))`; + + +(*val memory_single_general_register_aarch64_memory_single_general_register__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_register_aarch64_memory_single_general_register__decode:(2)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 Rm option_name S1 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_STORE n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 64 : int):ii) : 64 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 0 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 8 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_STORE n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 64 : int):ii) : 64 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 1 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 16 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_STORE n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 64 : int):ii) : 64 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 2 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 32 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 32 : int):ii) : 32 itself)) shift T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_STORE n F + ((make_the_value (( 64 : int):ii) : 64 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_LOAD n F + ((make_the_value (( 64 : int):ii) : 64 itself)) shift F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . + aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_PREFETCH n + F ((make_the_value (( 32 : int):ii) : 32 itself)) shift w__0 t F)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$seqS + (if ((((vec_of_bits [access_vec_dec option_name (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (if (((S1 = (vec_of_bits [B1] : 1 words$word)))) then (( 3 : int):ii) else (( 0 : int):ii)) in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (m : ii) = (lem$w2ui Rm) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . + aarch64_memory_single_general_register AccType_NORMAL (( 64 : int):ii) extend_type m MemOp_PREFETCH n + F ((make_the_value (( 32 : int):ii) : 32 itself)) shift w__1 t F)))))))))`; + + +(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm12 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_STORE n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__4 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__4 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_STORE n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__5 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__5 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__6 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__6 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__7 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__7 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__8 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__8 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_STORE n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__9 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__9 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__10 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__10 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__11 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__11 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__12 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__12 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_STORE n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__13 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__13 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__14 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__14 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__15 : bool) . + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_PREFETCH n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__15 t F))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__16 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__16 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__17 : bool) . + aarch64_memory_single_general_immediate_unsigned AccType_NORMAL (( 64 : int):ii) MemOp_PREFETCH n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__17 t F))))))))))`; + + +(*val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm12 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 0 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__4 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__4 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__5 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__5 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__6 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__6 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__7 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__7 (( 1 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__8 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__8 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__9 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__9 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__10 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__10 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__11 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__11 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__12 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__12 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__13 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__13 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__14 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__14 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__15 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__16 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__15 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__16 t F))))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__17 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__17 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__18 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__19 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__18 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__19 t F)))))))))))`; + + +(*val memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__0 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__0 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__1 t T)))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__2 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__2 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__3 t T))))))))))`; + + +(*val memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_STORE n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_STORE n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 16 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_STORE n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 64 : int):ii) : 64 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 32 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 32 : int):ii) : 32 itself)) T t T)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_STORE n + offset T ((make_the_value (( 64 : int):ii) : 64 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) MemOp_LOAD n + offset T ((make_the_value (( 64 : int):ii) : 64 itself)) F t T))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__0 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__0 n offset + T ((make_the_value (( 32 : int):ii) : 32 itself)) w__1 t T)))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__2 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__3 : bool) . + aarch64_memory_single_general_immediate_signed_postidx AccType_NORMAL (( 64 : int):ii) w__2 n offset + T ((make_the_value (( 32 : int):ii) : 32 itself)) w__3 t T))))))))))`; + + +(*val memory_single_general_immediate_signed_pac_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty9 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_signed_pac_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(9)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 M S1 imm9 W1 Rn Rt= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if (((((~ ((HavePACExt () )))) \/ (((size1 <> (vec_of_bits [B1;B1] : 2 words$word))))))) + then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (wback : bool) = (W1 = (vec_of_bits [B1] : 1 words$word)) in + let (use_key_a : bool) = (M = (vec_of_bits [B0] : 1 words$word)) in + let (S10 : 10 bits) = ((concat_vec S1 imm9 : 10 words$word)) in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 S10 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 scale : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_single_general_immediate_signed_pac n offset t use_key_a wback)))))`; + + +(*val memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__0 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__3 : bool) . + let (acctype : AccType) = (if w__3 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__4 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__4 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__6 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__6 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__7 : bool) . + let (acctype : AccType) = (if w__7 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__8 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__8 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__10 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__10 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__11 : bool) . + let (acctype : AccType) = (if w__11 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__12 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__12 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__14 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__14 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__15 : bool) . + let (acctype : AccType) = (if w__15 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 8 : int):ii) MemOp_LOAD n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__16 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__16 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__18 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__18 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__19 : bool) . + let (acctype : AccType) = (if w__19 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__20 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__20 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__22 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__22 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__23 : bool) . + let (acctype : AccType) = (if w__23 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__24 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__24 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__26 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__26 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__27 : bool) . + let (acctype : AccType) = (if w__27 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__28 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__28 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__30 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__30 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__31 : bool) . + let (acctype : AccType) = (if w__31 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 16 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__32 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__32 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__34 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__34 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__35 : bool) . + let (acctype : AccType) = (if w__35 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__36 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__36 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__38 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__38 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__39 : bool) . + let (acctype : AccType) = (if w__39 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__40 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__40 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__42 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__42 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__43 : bool) . + let (acctype : AccType) = (if w__43 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__44 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__44 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__46 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__46 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__47 : bool) . + let (acctype : AccType) = (if w__47 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 32 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F))))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__48 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__48 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__50 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__50 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__51 : bool) . + let (acctype : AccType) = (if w__51 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) MemOp_STORE n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__52 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__52 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__54 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__54 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__55 : bool) . + let (acctype : AccType) = (if w__55 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__56 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__56 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__58 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__58 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__59 : bool) . + let (acctype : AccType) = (if w__59 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__60 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__61 : bool) . + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) w__60 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__61 t F))))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_UNPRIV in sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((HaveNVExt () )) /\ ((HaveEL EL2)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__62 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__62 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__64 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__64 (( 43 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__65 : bool) . + let (acctype : AccType) = (if w__65 then AccType_NORMAL else acctype) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (w__66 : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__67 : bool) . + aarch64_memory_single_general_immediate_signed_offset_unpriv acctype (( 64 : int):ii) w__66 n offset + F ((make_the_value (( 32 : int):ii) : 32 itself)) w__67 t F)))))))))))`; + + +(*val memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode : mword ty2 -> mword ty1 -> mword ty2 -> mword ty9 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode:(2)words$word ->(1)words$word ->(2)words$word ->(9)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 b__1 imm9 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_STORE + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 8 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 8 : int):ii) MemOp_LOAD n + offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_STORE + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 1 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((F /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 16 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 16 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_STORE + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 32 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ F))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 64 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 64 : int):ii) : 64 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in sail2_state_monad$seqS + (if (((T /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let regsize = ((( 32 : int):ii)) in + let signed = T in + let (datasize : ii) = ((( 32 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 32 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) T t F)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_STORE in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) MemOp_STORE + n offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_LOAD in + let regsize = ((( 64 : int):ii)) in + let signed = F in + let (datasize : ii) = ((( 64 : int):ii)) in + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) MemOp_LOAD + n offset F ((make_the_value (( 64 : int):ii) : 64 itself)) F t F))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) + MemOp_PREFETCH n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) w__0 t F)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm9 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (offset : 64 + bits) . + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (acctype : AccType) = AccType_NORMAL in sail2_state_monad$bindS + (undefined_MemOp () ) (\ (memop : MemOp) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (signed : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (regsize : ii) . + let memop = MemOp_PREFETCH in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__1 : bool) . + aarch64_memory_single_general_immediate_signed_offset_normal AccType_NORMAL (( 64 : int):ii) + MemOp_PREFETCH n offset F ((make_the_value (( 32 : int):ii) : 32 itself)) w__1 t F)))))))))`; + + +(*val memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii) : 32 itself)) memop + n offset F t t2 T))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii) : 64 itself)) memop + n offset F t t2 T))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 4 : int):ii)) in + let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 4 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii) : 128 itself)) + memop n offset F t t2 T))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 5 : int):ii)) in + let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 5 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii) : 256 itself)) + memop n offset F t t2 T))))))`; + + +(*val memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii) : 32 itself)) memop + n offset T t t2 T))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii) : 64 itself)) memop + n offset T t t2 T))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 4 : int):ii)) in + let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 4 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii) : 128 itself)) + memop n offset T t t2 T))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 5 : int):ii)) in + let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 5 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii) : 256 itself)) + memop n offset T t t2 T))))))`; + + +(*val memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 32 : int):ii) : 32 itself)) memop + n offset F t t2 F))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 64 : int):ii) : 64 itself)) memop + n offset F t t2 F))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 4 : int):ii)) in + let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 4 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 128 : int):ii) : 128 itself)) + memop n offset F t t2 F))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VEC in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 5 : int):ii)) in + let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 5 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_postidx AccType_VEC ((make_the_value (( 256 : int):ii) : 256 itself)) + memop n offset F t t2 F))))))`; + + +(*val memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VECSTREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F t t2 F))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VECSTREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F t t2 F))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VECSTREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 4 : int):ii)) in + let (datasize : ii) = ((( 128 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 4 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM + ((make_the_value (( 128 : int):ii) : 128 itself)) memop n offset F t t2 F))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_VECSTREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 5 : int):ii)) in + let (datasize : ii) = ((( 256 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 5 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_simdfp_noalloc AccType_VECSTREAM + ((make_the_value (( 256 : int):ii) : 256 itself)) memop n offset F t t2 F))))))`; + + +(*val memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F F t t2 T)))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F T t t2 T)))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F F t t2 T)))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ T))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F T t t2 T))))))`; + + +(*val memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset T F t t2 T)))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset T T t t2 T)))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset T F t t2 T)))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = T in + let (postindex : bool) = T in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ T))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset T T t t2 T))))))`; + + +(*val memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F F t t2 F)))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F T t t2 F)))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B0] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = F in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F F t t2 F)))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_NORMAL in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (if ((((((((concat_vec L (vec_of_bits [B1] : 1 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) \/ T))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (signed : bool) = T in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_postidx AccType_NORMAL ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F T t t2 F))))))`; + + +(*val memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty7 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode:(2)words$word ->(1)words$word ->(1)words$word ->(7)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 L imm7 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_STREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__0 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__0 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F t t2 F))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_STREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 2 : int):ii)) in + let (datasize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__1 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__1 (( 2 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 32 : int):ii) : 32 itself)) + memop n offset F t t2 F)))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_STREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__2 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F t t2 F))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (wback : bool) = F in + let (postindex : bool) = F in + let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (t2 : ii) = (lem$w2ui Rt2) in + let (acctype : AccType) = AccType_STREAM in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in sail2_state_monad$seqS + (UnallocatedEncoding () ) + (let (scale : ii) = ((( 3 : int):ii)) in + let (datasize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (SignExtend__0 imm7 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) (\ (w__3 : + 64 words$word) . sail2_state_monad$bindS + (LSL w__3 (( 3 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + aarch64_memory_pair_general_noalloc AccType_STREAM ((make_the_value (( 64 : int):ii) : 64 itself)) + memop n offset F t t2 F))))))`; + + +(*val memory_literal_simdfp_decode : mword ty2 -> mword ty1 -> mword ty19 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_literal_simdfp_decode:(2)words$word ->(1)words$word ->(19)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc V1 imm19 Rt= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in sail2_state_monad$bindS + (undefined_int () ) (\ (size1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (offset : 64 bits) . + let b__0 = opc in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 4 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 8 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS size1)) (\ (size1 : ii) . sail2_state_monad$bindS + (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0;B0] : 2 words$word) : 21 words$word)) + ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let offset = w__0 in + aarch64_memory_literal_simdfp offset ((ex_int size1)) t)))))))`; + + +(*val memory_atomicops_swp_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_atomicops_swp_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 8 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 16 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 32 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t) + else sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_swp (( 64 : int):ii) ldacctype n ((make_the_value (( 64 : int):ii) : 64 itself)) s + stacctype t)))`; + + +(*val memory_atomicops_st_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_atomicops_st_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) size1 V1 A R1 Rs o3 opc Rn Rt= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = (shl_int (( 8 : int):ii) ((lem$w2ui size1))) in + let (regsize : ii) = (if (((((ex_int datasize)) = (( 64 : int):ii)))) then (( 64 : int):ii) else (( 32 : int):ii)) in + let (ldacctype : AccType) = AccType_ATOMICRW in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in sail2_state_monad$bindS + (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . + let b__0 = opc in + let (op : MemAtomicOp) = + (if (((b__0 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then MemAtomicOp_ADD + else if (((b__0 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then MemAtomicOp_BIC + else if (((b__0 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then MemAtomicOp_EOR + else if (((b__0 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then MemAtomicOp_ORR + else if (((b__0 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then MemAtomicOp_SMAX + else if (((b__0 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then MemAtomicOp_SMIN + else if (((b__0 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_st datasize ldacctype n op s stacctype))))`; + + +(*val memory_atomicops_ld_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_atomicops_ld_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 V1 A R1 Rs o3 opc Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in sail2_state_monad$bindS + (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . + let b__1 = opc in + let (op : MemAtomicOp) = + (if (((b__1 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then MemAtomicOp_ADD + else if (((b__1 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then MemAtomicOp_BIC + else if (((b__1 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then MemAtomicOp_EOR + else if (((b__1 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then MemAtomicOp_ORR + else if (((b__1 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then MemAtomicOp_SMAX + else if (((b__1 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then MemAtomicOp_SMIN + else if (((b__1 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 8 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t)) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in sail2_state_monad$bindS + (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . + let b__10 = opc in + let (op : MemAtomicOp) = + (if (((b__10 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then MemAtomicOp_ADD + else if (((b__10 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then MemAtomicOp_BIC + else if (((b__10 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then MemAtomicOp_EOR + else if (((b__10 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then MemAtomicOp_ORR + else if (((b__10 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then MemAtomicOp_SMAX + else if (((b__10 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then MemAtomicOp_SMIN + else if (((b__10 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 16 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t)) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in sail2_state_monad$bindS + (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . + let b__19 = opc in + let (op : MemAtomicOp) = + (if (((b__19 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then MemAtomicOp_ADD + else if (((b__19 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then MemAtomicOp_BIC + else if (((b__19 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then MemAtomicOp_EOR + else if (((b__19 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then MemAtomicOp_ORR + else if (((b__19 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then MemAtomicOp_SMAX + else if (((b__19 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then MemAtomicOp_SMIN + else if (((b__19 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 32 : int):ii) ldacctype n op ((make_the_value (( 32 : int):ii) : 32 itself)) s + stacctype t)) + else sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (ldacctype : AccType) = + (if ((((((A = (vec_of_bits [B1] : 1 words$word)))) /\ (((Rt <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((R1 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in sail2_state_monad$bindS + (undefined_MemAtomicOp () ) (\ (op : MemAtomicOp) . + let b__28 = opc in + let (op : MemAtomicOp) = + (if (((b__28 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then MemAtomicOp_ADD + else if (((b__28 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then MemAtomicOp_BIC + else if (((b__28 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then MemAtomicOp_EOR + else if (((b__28 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then MemAtomicOp_ORR + else if (((b__28 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then MemAtomicOp_SMAX + else if (((b__28 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then MemAtomicOp_SMIN + else if (((b__28 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then MemAtomicOp_UMAX + else MemAtomicOp_UMIN) in + aarch64_memory_atomicops_ld (( 64 : int):ii) ldacctype n op ((make_the_value (( 64 : int):ii) : 64 itself)) s + stacctype t))))`; + + +(*val memory_atomicops_cas_single_decode : mword ty2 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_atomicops_cas_single_decode:(2)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 8 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 8 : int):ii) ldacctype n + ((make_the_value (( 32 : int):ii) : 32 itself)) s stacctype t) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 16 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 16 : int):ii) ldacctype n + ((make_the_value (( 32 : int):ii) : 32 itself)) s stacctype t) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 32 : int):ii) ldacctype n + ((make_the_value (( 32 : int):ii) : 32 itself)) s stacctype t) + else sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_single (( 64 : int):ii) ldacctype n + ((make_the_value (( 64 : int):ii) : 64 itself)) s stacctype t)))`; + + +(*val memory_atomicops_cas_pair_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_atomicops_cas_pair_decode:(1)words$word ->(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 o2 L o1 Rs o0 Rt2 Rn Rt= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (if ((((vec_of_bits [access_vec_dec Rs (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (if ((((vec_of_bits [access_vec_dec Rt (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 32 : int):ii)) in + let (regsize : ii) = ((( 32 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_pair (( 32 : int):ii) ldacctype n ((make_the_value (( 32 : int):ii) : 32 itself)) + s stacctype t) + else sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (if ((~ ((HaveAtomicExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (if ((((vec_of_bits [access_vec_dec Rs (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (if ((((vec_of_bits [access_vec_dec Rt (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (n : ii) = (lem$w2ui Rn) in + let (t : ii) = (lem$w2ui Rt) in + let (s : ii) = (lem$w2ui Rs) in + let (datasize : ii) = ((( 64 : int):ii)) in + let (regsize : ii) = ((( 64 : int):ii)) in + let (ldacctype : AccType) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + let (stacctype : AccType) = + (if (((o0 = (vec_of_bits [B1] : 1 words$word)))) then AccType_ORDEREDRW + else AccType_ATOMICRW) in + aarch64_memory_atomicops_cas_pair (( 64 : int):ii) ldacctype n ((make_the_value (( 64 : int):ii) : 64 itself)) + s stacctype t)))`; + + +(*val integer_pac_strip_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_strip_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 D Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (data : bool) = (D = (vec_of_bits [B1] : 1 words$word)) in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aarch64_integer_pac_strip_dp_1src d data))))`; + + +(*val integer_pac_pacib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacib_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_pacib_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_pacia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacia_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_pacia_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_pacga_dp_2src_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacga_dp_2src_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (source_is_sp : bool) = (if (((((ex_int m)) = (( 31 : int):ii)))) then T else source_is_sp) in + aarch64_integer_pac_pacga_dp_2src d m n source_is_sp))))`; + + +(*val integer_pac_pacdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacdb_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_pacdb_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_pacda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_pacda_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_pacda_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_autib_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autib_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_autib_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_autia_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autia_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_autia_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_autdb_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autdb_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_autdb_dp_1src d n source_is_sp))))`; + + +(*val integer_pac_autda_dp_1src_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_pac_autda_dp_1src_decode:(1)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 Z Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (source_is_sp : bool) = F in + let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((HavePACExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Z = (vec_of_bits [B0] : 1 words$word)))) then + let (source_is_sp : bool) = (if (((((ex_int n)) = (( 31 : int):ii)))) then T else source_is_sp) in + sail2_state_monad$returnS source_is_sp + else sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS source_is_sp))) (\ (source_is_sp : bool) . + aarch64_integer_pac_autda_dp_1src d n source_is_sp))))`; + + +(*val integer_insext_insert_movewide_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty16 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_insext_insert_movewide_decode:(1)words$word ->(2)words$word ->(2)words$word ->(16)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf opc hw imm16 Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (imm : 16 bits) = imm16 in sail2_state_monad$bindS + (undefined_int () ) (\ (pos : ii) . sail2_state_monad$bindS + (undefined_MoveWideOp () ) (\ (opcode : MoveWideOp) . + let b__0 = opc in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS MoveWideOp_N + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS MoveWideOp_Z + else if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then sail2_state_monad$returnS MoveWideOp_K + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS opcode)) (\ (opcode : MoveWideOp) . sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ ((((vec_of_bits [access_vec_dec hw (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let pos = (lem$w2ui ((concat_vec hw (vec_of_bits [B0;B0;B0;B0] : 4 words$word) : 6 words$word))) in + aarch64_integer_insext_insert_movewide d datasize imm opcode pos)))))))`; + + +(*val integer_crc_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty3 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_crc_decode:(1)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(3)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 Rm opcode2 C b__0 Rn Rd= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B1] : 1 words$word)))) /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (size1 : ii) = ((( 8 : int):ii)) in + let (crc32c : bool) = (C = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_crc crc32c d m n (( 8 : int):ii))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B1] : 1 words$word)))) /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (size1 : ii) = ((( 16 : int):ii)) in + let (crc32c : bool) = (C = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_crc crc32c d m n (( 16 : int):ii))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B1] : 1 words$word)))) /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (size1 : ii) = ((( 32 : int):ii)) in + let (crc32c : bool) = (C = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_crc crc32c d m n (( 32 : int):ii))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B1] : 1 words$word)))) /\ F))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ T))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (size1 : ii) = ((( 64 : int):ii)) in + let (crc32c : bool) = (C = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_crc crc32c d m n (( 64 : int):ii)))))`; + + +(*val integer_arithmetic_rev_decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_rev_decode:(1)words$word ->(1)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 opcode2 opc Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (container_size : ii) . + let b__0 = opc in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (Unreachable () ) (sail2_state_monad$returnS container_size) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 16 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else sail2_state_monad$seqS + (if (((sf = (vec_of_bits [B0] : 1 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS (( 64 : int):ii))) (\ (container_size : ii) . + aarch64_integer_arithmetic_rev container_size d datasize n)))))`; + + +(*val float_move_fp_select_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_move_fp_select_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm cond Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (condition : 4 bits) = cond in + aarch64_float_move_fp_select condition d datasize m n)))))`; + + +(*val float_move_fp_imm_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty8 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_move_fp_imm_decode:(1)words$word ->(1)words$word ->(2)words$word ->(8)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 b__0 imm8 imm5 Rd= + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let datasize = ((( 32 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (VFPExpandImm (( 32 : int):ii) imm8 : ( 32 words$word) M)) (\ (imm : 32 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 32 : int):ii) : 32 itself)) imm))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let datasize = ((( 64 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (VFPExpandImm (( 64 : int):ii) imm8 : ( 64 words$word) M)) (\ (imm : 64 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 64 : int):ii) : 64 itself)) imm))) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (sail2_state_monad$assert_expS T "")) + (VFPExpandImm (( 32 : int):ii) imm8 : ( 32 words$word) M)) (\ (imm : 32 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 32 : int):ii) : 32 itself)) imm))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let datasize = ((( 16 : int):ii)) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (VFPExpandImm (( 16 : int):ii) imm8 : ( 16 words$word) M)) (\ (imm : 16 bits) . + aarch64_float_move_fp_imm d ((make_the_value (( 16 : int):ii) : 16 itself)) imm)))))`; + + +(*val aarch64_float_convert_int_split : ii -> ii -> ii -> ii -> FPConvOp -> ii -> FPRounding -> bool -> M unit*) + +val _ = Define ` + ((aarch64_float_convert_int_split:int -> int -> int -> int -> FPConvOp -> int -> FPRounding -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) d l__0 l__1 n op part rounding unsigned= + (if ((((((l__0 = (( 16 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 16 : int):ii) : 16 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 16 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 16 : int):ii) : 16 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 32 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 32 : int):ii) : 32 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 32 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 32 : int):ii) : 32 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 64 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 64 : int):ii)))) /\ (((l__1 = (( 64 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 64 : int):ii) : 64 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) n op part rounding unsigned + else if ((((((l__0 = (( 128 : int):ii)))) /\ (((l__1 = (( 32 : int):ii))))))) then + aarch64_float_convert_int d ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 32 : int):ii) : 32 itself)) n op part rounding unsigned + else + aarch64_float_convert_int d ((make_the_value (( 128 : int):ii) : 128 itself)) + ((make_the_value (( 64 : int):ii) : 64 itself)) n op part rounding unsigned))`; + + +(*val float_convert_int_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_convert_int_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf S1 typ rmode opcode Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (part : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (if (((((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) <> (vec_of_bits [B1;B1;B0;B1] : 4 words$word)))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS (( 128 : int):ii)) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS fltsize)) (\ (fltsize : ii) . + let v__98 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((((subrange_vec_dec v__98 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (rounding : FPRounding) = (FPDecodeRounding rmode) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned) + else if (((v__98 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__0) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned)) + else if (((v__98 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_TIEAWAY in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned) + else if (((v__98 = (vec_of_bits [B1;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$seqS + (if ((((((((ex_int fltsize)) <> (( 16 : int):ii)))) /\ (((((ex_int fltsize)) <> intsize)))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (op : FPConvOp) = + (if ((((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + FPConvOp_MOV_ItoF + else FPConvOp_MOV_FtoI) in + let (part : ii) = ((( 0 : int):ii)) in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned)) + else if (((v__98 = (vec_of_bits [B1;B1;B0;B1] : 4 words$word)))) then sail2_state_monad$seqS + (if ((((((((ex_int intsize)) <> (( 64 : int):ii)))) \/ (((((ex_int fltsize)) <> (( 128 : int):ii))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (op : FPConvOp) = + (if ((((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + FPConvOp_MOV_ItoF + else FPConvOp_MOV_FtoI) in + let (part : ii) = ((( 1 : int):ii)) in + let (fltsize : ii) = ((( 64 : int):ii)) in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned)) + else sail2_state_monad$bindS + (if (((v__98 = (vec_of_bits [B1;B1;B1;B1] : 4 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HaveFJCVTZSExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI_JS in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in + sail2_state_monad$returnS (fltsize, op, part, rounding, unsigned))) (\ varstup . let ((fltsize : ii), (op : + FPConvOp), (part : ii), (rounding : FPRounding), (unsigned : bool)) = varstup in + let fltsize2 = (ex_int fltsize) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_int_split d fltsize2 intsize n op part rounding unsigned)))))))))))`; + + +(*val float_convert_fp_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_convert_fp_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 b__0 b__1 Rn Rd= + (if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (srcsize : ii) . + let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii) : 64 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (sail2_state_monad$assert_expS T "")) + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii) : 16 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 64 : int):ii) : 64 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (srcsize : ii) . + let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii) : 64 itself)) n + ((make_the_value (( 64 : int):ii) : 64 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (sail2_state_monad$assert_expS T "")) + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 64 : int):ii) : 64 itself)))))) + else if ((((((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii) : 16 itself)) n + ((make_the_value (( 64 : int):ii) : 64 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (dstsize : ii) . + let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (dstsize : ii) . + let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii) : 64 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (srcsize : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (dstsize : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (sail2_state_monad$assert_expS T "")) + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (dstsize : ii) . + let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii) : 16 itself)) n + ((make_the_value (( 32 : int):ii) : 32 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 16 : int):ii) : 16 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 64 : int):ii) : 64 itself)) n + ((make_the_value (( 16 : int):ii) : 16 itself)))))) + else if ((((((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (srcsize : ii) . + let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (sail2_state_monad$assert_expS T "")) + (aarch64_float_convert_fp d ((make_the_value (( 32 : int):ii) : 32 itself)) n + ((make_the_value (( 16 : int):ii) : 16 itself)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (undefined_int () )) (\ (srcsize : ii) . + let srcsize = ((( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (dstsize : ii) . + let dstsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fp d ((make_the_value (( 16 : int):ii) : 16 itself)) n + ((make_the_value (( 16 : int):ii) : 16 itself))))))))`; + + +(*val float_convert_fix_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty3 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_convert_fix_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(3)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 S1 b__1 rmode opcode scale Rn Rd= + (if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__2 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__2 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__2 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__0) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii) : 32 itself)) fracbits + ((make_the_value (( 32 : int):ii) : 32 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__6 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__6 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__6 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__1) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 64 : int):ii) : 64 itself)) fracbits + ((make_the_value (( 32 : int):ii) : 32 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__10 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__10 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__10 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__2) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii) : 32 itself)) fracbits + ((make_the_value (( 32 : int):ii) : 32 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (if (((T /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__14 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__14 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__14 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__3 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__3) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 16 : int):ii) : 16 itself)) fracbits + ((make_the_value (( 32 : int):ii) : 32 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 32 : int):ii)) in sail2_state_monad$seqS + (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__18 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__18 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__18 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__4 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__4) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii) : 32 itself)) fracbits + ((make_the_value (( 64 : int):ii) : 64 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 64 : int):ii)) in sail2_state_monad$seqS + (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__22 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__22 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__22 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__5 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__5) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 64 : int):ii) : 64 itself)) fracbits + ((make_the_value (( 64 : int):ii) : 64 itself)) n op rounding unsigned)))))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . sail2_state_monad$seqS (sail2_state_monad$seqS + (UnallocatedEncoding () ) + (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__26 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__26 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__26 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__6) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 32 : int):ii) : 32 itself)) fracbits + ((make_the_value (( 64 : int):ii) : 64 itself)) n op rounding unsigned)))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (intsize : ii) = ((( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (fltsize : ii) . sail2_state_monad$bindS + (undefined_FPConvOp () ) (\ (op : FPConvOp) . sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (unsigned : bool) . + let fltsize = ((( 16 : int):ii)) in sail2_state_monad$seqS + (if (((F /\ ((((vec_of_bits [access_vec_dec scale (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (fracbits : ii) = ((( 64 : int):ii) - ((lem$w2ui scale))) in + let b__30 = ((concat_vec ((slice opcode (( 1 : int):ii) (( 2 : int):ii) : 2 words$word)) rmode : 4 words$word)) in sail2_state_monad$bindS + (if (((b__30 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) then + let (rounding : FPRounding) = FPRounding_ZERO in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_FtoI in + sail2_state_monad$returnS (op, rounding, unsigned) + else if (((b__30 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__7 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__7) in + let (unsigned : bool) = + ((vec_of_bits [access_vec_dec opcode (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (op : FPConvOp) = FPConvOp_CVT_ItoF in + sail2_state_monad$returnS (op, rounding, unsigned)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (op, rounding, unsigned))) (\ varstup . let ((op : + FPConvOp), (rounding : FPRounding), (unsigned : bool)) = varstup in sail2_state_monad$seqS + (sail2_state_monad$assert_expS T "") + (aarch64_float_convert_fix d ((make_the_value (( 16 : int):ii) : 16 itself)) fracbits + ((make_the_value (( 64 : int):ii) : 64 itself)) n op rounding unsigned))))))))))`; + + +(*val float_compare_uncond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty2 -> M unit*) + +val _ = Define ` + ((float_compare_uncond_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn opc= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (signal_all_nans : bool) = + ((vec_of_bits [access_vec_dec opc (( 1 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + let (cmp_with_zero : bool) = + ((vec_of_bits [access_vec_dec opc (( 0 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)) in + aarch64_float_compare_uncond cmp_with_zero datasize m n signal_all_nans)))))`; + + +(*val float_compare_cond_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty5 -> mword ty1 -> mword ty4 -> M unit*) + +val _ = Define ` + ((float_compare_cond_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(5)words$word ->(1)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm cond Rn op nzcv1= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (signal_all_nans : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (condition : 4 bits) = cond in + let (flags : 4 bits) = nzcv1 in + aarch64_float_compare_cond condition datasize flags m n signal_all_nans)))))`; + + +(*val float_arithmetic_unary_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_unary_decode:(1)words$word ->(1)words$word ->(2)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ opc Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . sail2_state_monad$bindS + (undefined_FPUnaryOp () ) (\ (fpop : FPUnaryOp) . + let b__4 = opc in + let (fpop : FPUnaryOp) = + (if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then FPUnaryOp_MOV + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then FPUnaryOp_ABS + else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then FPUnaryOp_NEG + else FPUnaryOp_SQRT) in + aarch64_float_arithmetic_unary d datasize fpop n))))))`; + + +(*val float_arithmetic_round_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_round_decode:(1)words$word ->(1)words$word ->(2)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ rmode Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (exact : bool) = F in sail2_state_monad$bindS + (undefined_FPRounding () ) (\ (rounding : FPRounding) . + let v__101 = rmode in sail2_state_monad$bindS + (if (((((subrange_vec_dec v__101 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) then + let (rounding : FPRounding) = (FPDecodeRounding ((slice rmode (( 0 : int):ii) (( 2 : int):ii) : 2 words$word))) in + sail2_state_monad$returnS (exact, rounding) + else if (((v__101 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + let (rounding : FPRounding) = FPRounding_TIEAWAY in + sail2_state_monad$returnS (exact, rounding) + else if (((v__101 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS (exact, rounding)) + else if (((v__101 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__0) in + let (exact : bool) = T in + sail2_state_monad$returnS (exact, rounding)) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS FPCR_ref : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + let (rounding : FPRounding) = (FPRoundingMode w__1) in + sail2_state_monad$returnS (exact, rounding))) (\ varstup . let ((exact : bool), (rounding : FPRounding)) = varstup in + aarch64_float_arithmetic_round d datasize exact n rounding)))))))`; + + +(*val float_arithmetic_mul_product_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_mul_product_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (negated : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + aarch64_float_arithmetic_mul_product d datasize m n negated)))))`; + + +(*val float_arithmetic_mul_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_mul_addsub_decode:(1)words$word ->(1)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ o1 Rm o0 Ra Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (a : ii) = (lem$w2ui Ra) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (opa_neg : bool) = (o1 = (vec_of_bits [B1] : 1 words$word)) in + let (op1_neg : bool) = (o0 <> o1) in + aarch64_float_arithmetic_mul_addsub a d datasize m n op1_neg opa_neg)))))`; + + +(*val float_arithmetic_maxmin_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_maxmin_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . sail2_state_monad$bindS + (undefined_FPMaxMinOp () ) (\ (operation : FPMaxMinOp) . + let b__4 = op in + let (operation : FPMaxMinOp) = + (if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then FPMaxMinOp_MAX + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then FPMaxMinOp_MIN + else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then FPMaxMinOp_MAXNUM + else FPMaxMinOp_MINNUM) in + aarch64_float_arithmetic_maxmin d datasize m n operation))))))`; + + +(*val float_arithmetic_div_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_div_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + aarch64_float_arithmetic_div d datasize m n)))))`; + + +(*val float_arithmetic_addsub_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((float_arithmetic_addsub_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) M S1 typ Rm op Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in sail2_state_monad$bindS + (undefined_int () ) (\ (datasize : ii) . + let b__0 = typ in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS (( 32 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS (( 64 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$seqS + (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize) + else if ((HaveFP16Ext () )) then sail2_state_monad$returnS (( 16 : int):ii) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS datasize)) (\ (datasize : ii) . + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + aarch64_float_arithmetic_addsub d datasize m n sub_op)))))`; + + +(*val branch_unconditional_register_decode : mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((branch_unconditional_register_decode:(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) Z opc op op2 op3 A M Rn Rm= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_BranchType () ) (\ (branch_type : BranchType) . + let (m : ii) = (lem$w2ui Rm) in + let (pac : bool) = (A = (vec_of_bits [B1] : 1 words$word)) in + let (use_key_a : bool) = (M = (vec_of_bits [B0] : 1 words$word)) in + let (source_is_sp : bool) = + ((((Z = (vec_of_bits [B1] : 1 words$word)))) /\ (((((ex_int m)) = (( 31 : int):ii))))) in sail2_state_monad$seqS + (if (((((~ pac)) /\ (((((ex_int m)) <> (( 0 : int):ii))))))) then UnallocatedEncoding () + else if (((pac /\ ((~ ((HavePACExt () ))))))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let b__0 = op in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then sail2_state_monad$returnS BranchType_JMP + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then sail2_state_monad$returnS BranchType_CALL + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then sail2_state_monad$returnS BranchType_RET + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS branch_type)) (\ (branch_type : BranchType) . sail2_state_monad$bindS + (if pac then sail2_state_monad$seqS + (if ((((((Z = (vec_of_bits [B0] : 1 words$word)))) /\ (((((ex_int m)) <> (( 31 : int):ii))))))) + then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((branch_type = BranchType_RET))) then sail2_state_monad$seqS + (if (((((ex_int n)) <> (( 31 : int):ii)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (n : ii) = ((( 30 : int):ii)) in + let (source_is_sp : bool) = T in + sail2_state_monad$returnS (n, source_is_sp)) + else sail2_state_monad$returnS (n, source_is_sp)) + else sail2_state_monad$returnS (n, source_is_sp)) (\ varstup . let ((n : ii), (source_is_sp : bool)) = varstup in + aarch64_branch_unconditional_register branch_type m n pac source_is_sp use_key_a)))))))`; + + +(*val branch_unconditional_eret_decode : mword ty4 -> mword ty5 -> mword ty4 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((branch_unconditional_eret_decode:(4)words$word ->(5)words$word ->(4)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc op2 op3 A M Rn op4= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (sail2_state_monad$read_regS PSTATE_ref)) (\ (w__0 : ProcState) . sail2_state_monad$seqS + (if (((w__0.ProcState_EL = EL0))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (pac : bool) = (A = (vec_of_bits [B1] : 1 words$word)) in + let (use_key_a : bool) = (M = (vec_of_bits [B0] : 1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((((~ pac)) /\ (((op4 <> (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + UnallocatedEncoding () + else if (((pac /\ (((((~ ((HavePACExt () )))) \/ (((op4 <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))))))) then + UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if (((Rn <> (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))) then UnallocatedEncoding () + else sail2_state_monad$returnS () )) + (aarch64_branch_unconditional_eret pac use_key_a)))))`; + + +(*val branch_unconditional_dret_decode : mword ty4 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((branch_unconditional_dret_decode:(4)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc op2 op3 Rt op4= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (sail2_state$or_boolS ( sail2_state_monad$bindS(Halted () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__1 : ProcState) . sail2_state_monad$returnS (((w__1.ProcState_EL = EL0))))))) (\ (w__2 : + bool) . sail2_state_monad$seqS + (if w__2 then UnallocatedEncoding () else sail2_state_monad$returnS () ) (aarch64_branch_unconditional_dret () ))))`; + + +(*val AArch64_CheckSystemAccess : mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> mword ty1 -> M unit*) + +val _ = Define ` + ((AArch64_CheckSystemAccess:(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op0 op1 crn crm op2 rt read= + (let (unallocated : bool) = F in + let (need_secure : bool) = F in sail2_state_monad$bindS + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M) (\ (min_EL : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (rcs_el0_trap : bool) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__2 (( 20 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + (sail2_state_monad$returnS (((((and_vec op0 (vec_of_bits [B0;B1] : 2 words$word) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))) + (sail2_state_monad$returnS (((((and_vec crn (vec_of_bits [B1;B0;B1;B1] : 4 words$word) : 4 words$word)) = (vec_of_bits [B1;B0;B1;B1] : 4 words$word)))))) (\ (w__5 : bool) . sail2_state_monad$seqS + (if w__5 then sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__6 : bool) . + let rcs_el0_trap = w__6 in sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__7 : ProcState) . sail2_state_monad$returnS (((w__7.ProcState_EL = EL0))))) + (sail2_state_monad$returnS rcs_el0_trap)) (\ (w__8 : bool) . + if w__8 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__9 : ProcState) . + if (((w__9.ProcState_EL = EL1))) then + AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else sail2_state_monad$returnS () ))) + else sail2_state_monad$returnS () ) + (let v__103 = op1 in sail2_state_monad$bindS + (if (((((subrange_vec_dec v__103 (( 2 : int):ii) (( 1 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (min_EL : 2 bits) = EL1 in + sail2_state_monad$returnS (min_EL, need_secure) + else if (((v__103 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + let (min_EL : 2 bits) = EL1 in + sail2_state_monad$returnS (min_EL, need_secure) + else if (((v__103 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + let (min_EL : 2 bits) = EL0 in + sail2_state_monad$returnS (min_EL, need_secure) + else if (((v__103 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + let (min_EL : 2 bits) = EL2 in + sail2_state_monad$returnS (min_EL, need_secure) + else if (((v__103 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HaveVirtHostExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (let (min_EL : 2 bits) = EL2 in + sail2_state_monad$returnS (min_EL, need_secure)) + else + let ((min_EL : 2 bits), (need_secure : bool)) = + (if (((v__103 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + let (min_EL : 2 bits) = EL3 in + (min_EL, need_secure) + else + let (min_EL : 2 bits) = EL1 in + let (need_secure : bool) = T in + (min_EL, need_secure)) in + sail2_state_monad$returnS (min_EL, need_secure)) (\ varstup . let ((min_EL : 2 bits), (need_secure : bool)) = varstup in sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__10 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((((lem$w2ui w__10.ProcState_EL)) < ((lem$w2ui min_EL)))) then sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + sail2_state_monad$returnS (((w__11.ProcState_EL = EL1))))) (sail2_state_monad$returnS (((min_EL = EL2))))) + (sail2_state_monad$returnS ((HaveNVExt () )))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__14 : bool) . sail2_state_monad$returnS ((~ w__14))))) (sail2_state_monad$returnS ((HaveEL EL2)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__17 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__17 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__18 : bool) . + if w__18 then AArch64_SystemRegisterTrap EL2 op0 op2 op1 crn rt crm read + else UnallocatedEncoding () ) + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS need_secure) ( sail2_state_monad$bindS(IsSecure () ) (\ (w__19 : bool) . sail2_state_monad$returnS ((~ w__19))))) (\ (w__20 : + bool) . + if w__20 then UnallocatedEncoding () + else sail2_state_monad$bindS + (AArch64_CheckUnallocatedSystemAccess op0 op1 crn crm op2 read) (\ (w__21 : bool) . + if w__21 then UnallocatedEncoding () + else sail2_state_monad$returnS () ))) + (undefined_bitvector (( 2 : int):ii) : ( 2 words$word) M)) (\ (target_el : 2 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (take_trap : bool) . sail2_state_monad$bindS + (AArch64_CheckAdvSIMDFPSystemRegisterTraps op0 op1 crn crm op2 read : ((bool # 2 words$word)) M) (\ varstup . let (tup__0, tup__1) = varstup in + let take_trap = tup__0 in + let target_el = tup__1 in sail2_state_monad$bindS (sail2_state_monad$seqS + (if take_trap then AArch64_AdvSIMDFPAccessTrap target_el + else sail2_state_monad$returnS () ) + (AArch64_CheckSystemRegisterTraps op0 op1 crn crm op2 read : ((bool # 2 words$word)) M)) (\ varstup . let (tup__0, tup__1) = varstup in + let take_trap = tup__0 in + let target_el = tup__1 in + if take_trap then AArch64_SystemRegisterTrap target_el op0 op2 op1 crn rt crm read + else sail2_state_monad$returnS () ))))))))))))`; + + +(*val system_sysops_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_sysops_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (AArch64_CheckSystemAccess (vec_of_bits [B0;B1] : 2 words$word) op1 CRn CRm op2 Rt L)) + (let (t : ii) = (lem$w2ui Rt) in + let (sys_op0 : ii) = ((( 1 : int):ii)) in + let (sys_op1 : ii) = (lem$w2ui op1) in + let (sys_op2 : ii) = (lem$w2ui op2) in + let (sys_crn : ii) = (lem$w2ui CRn) in + let (sys_crm : ii) = (lem$w2ui CRm) in + let (has_result : bool) = (L = (vec_of_bits [B1] : 1 words$word)) in + aarch64_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))`; + + +(*val system_register_system_decode : mword ty1 -> mword ty1 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_register_system_decode:(1)words$word ->(1)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L o0 op1 CRn CRm op2 Rt= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (AArch64_CheckSystemAccess ((concat_vec (vec_of_bits [B1] : 1 words$word) o0 : 2 words$word)) op1 CRn + CRm op2 Rt L)) + (let (t : ii) = (lem$w2ui Rt) in + let (sys_op0 : ii) = ((( 2 : int):ii) + ((lem$w2ui o0))) in + let (sys_op1 : ii) = (lem$w2ui op1) in + let (sys_op2 : ii) = (lem$w2ui op2) in + let (sys_crn : ii) = (lem$w2ui CRn) in + let (sys_crm : ii) = (lem$w2ui CRm) in + let (read : bool) = (L = (vec_of_bits [B1] : 1 words$word)) in + aarch64_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t)))`; + + +(*val system_register_cpsr_decode : mword ty1 -> mword ty2 -> mword ty3 -> mword ty4 -> mword ty4 -> mword ty3 -> mword ty5 -> M unit*) + +val _ = Define ` + ((system_register_cpsr_decode:(1)words$word ->(2)words$word ->(3)words$word ->(4)words$word ->(4)words$word ->(3)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) L op0 op1 CRn CRm op2 Rt= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (AArch64_CheckSystemAccess (vec_of_bits [B0;B0] : 2 words$word) op1 + (vec_of_bits [B0;B1;B0;B0] : 4 words$word) CRm op2 (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) + (vec_of_bits [B0] : 1 words$word))) + (let (operand : 4 bits) = CRm in sail2_state_monad$bindS + (undefined_PSTATEField () ) (\ (field' : PSTATEField) . + let b__0 = ((concat_vec op1 op2 : 6 words$word)) in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HaveUAOExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS PSTATEField_UAO) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word)))) then sail2_state_monad$seqS + (if ((~ ((HavePANExt () )))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS PSTATEField_PAN) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word)))) then + sail2_state_monad$returnS PSTATEField_SP + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0] : 6 words$word)))) then + sail2_state_monad$returnS PSTATEField_DAIFSet + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B1] : 6 words$word)))) then + sail2_state_monad$returnS PSTATEField_DAIFClr + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS field')) (\ (field' : PSTATEField) . sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((op1 = (vec_of_bits [B0;B1;B1] : 3 words$word))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$returnS (((w__0.ProcState_EL = EL0)))))) + (sail2_state$or_boolS ((IsInHost () )) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS SCTLR_EL1_ref : ( 32 words$word) M) (\ (w__3 : 32 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__3 (( 9 : int):ii)] : 1 words$word) = (vec_of_bits [B0] : 1 words$word)))))))) (\ (w__5 : bool) . sail2_state_monad$seqS + (if w__5 then + AArch64_SystemRegisterTrap EL1 (vec_of_bits [B0;B0] : 2 words$word) op2 op1 + (vec_of_bits [B0;B1;B0;B0] : 4 words$word) (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) CRm + (vec_of_bits [B0] : 1 words$word) + else sail2_state_monad$returnS () ) + (aarch64_system_register_cpsr field' operand)))))))`; + + +(*val AArch64_CheckForSMCUndefOrTrap : mword ty16 -> M unit*) + +val _ = Define ` + ((AArch64_CheckForSMCUndefOrTrap:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PSTATE_ref) (\ (w__0 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__0.ProcState_EL = EL0))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (sail2_state_monad$undefined_boolS () )) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (if ((~ ((HaveEL EL3)))) then sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__3 : ProcState) . sail2_state_monad$returnS (((w__3.ProcState_EL = EL1)))))) (\ (w__4 : + bool) . + if w__4 then sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveNVExt () ))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__5 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__5 (( 42 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__7 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__7 (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (w__8 : bool) . + if w__8 then sail2_state_monad$returnS T + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS route_to_el2)) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS route_to_el2)) + else + sail2_state$and_boolS + (sail2_state$and_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS ((HaveEL EL2))) + ( sail2_state_monad$bindS(IsSecure () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PSTATE_ref) (\ (w__11 : ProcState) . + sail2_state_monad$returnS (((w__11.ProcState_EL = EL1)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS HCR_EL2_ref : ( 64 words$word) M) (\ (w__13 : 64 bits) . + sail2_state_monad$returnS ((((vec_of_bits [access_vec_dec w__13 (( 19 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) (\ (route_to_el2 : bool) . sail2_state_monad$bindS + (undefined_ExceptionRecord () ) (\ (exception : ExceptionRecord) . sail2_state_monad$bindS + (undefined_int () ) (\ (vect_offset : ii) . + if route_to_el2 then sail2_state_monad$bindS + (ThisInstrAddr (( 64 : int):ii) () : ( 64 words$word) M) (\ (preferred_exception_return : 64 bits) . + let vect_offset = ((( 0 : int):ii)) in sail2_state_monad$bindS + (ExceptionSyndrome Exception_MonitorCall) (\ (w__15 : ExceptionRecord) . + let exception = w__15 in + let (tmp_40 : 25 bits) = (exception.ExceptionRecord_syndrome) in + let tmp_40 = ((set_slice (( 25 : int):ii) (( 16 : int):ii) tmp_40 (( 0 : int):ii) imm : 25 words$word)) in + let exception = ((exception with<| ExceptionRecord_syndrome := tmp_40|>)) in + AArch64_TakeException EL2 exception preferred_exception_return vect_offset)) + else sail2_state_monad$returnS () )))))))`; + + +(*val aarch64_system_exceptions_runtime_smc : mword ty16 -> M unit*) + +val _ = Define ` + ((aarch64_system_exceptions_runtime_smc:(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm= (sail2_state_monad$bindS (sail2_state_monad$seqS + (AArch64_CheckForSMCUndefOrTrap imm) + (sail2_state_monad$read_regS SCR_EL3_ref : ( 32 words$word) M)) (\ (w__0 : 32 bits) . + if ((((vec_of_bits [access_vec_dec w__0 (( 7 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word)))) then + AArch64_UndefinedFault () + else AArch64_CallSecureMonitor imm)))`; + + +(*val system_exceptions_runtime_smc_decode : mword ty3 -> mword ty16 -> mword ty3 -> mword ty2 -> M unit*) + +val _ = Define ` + ((system_exceptions_runtime_smc_decode:(3)words$word ->(16)words$word ->(3)words$word ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) opc imm16 op2 LL= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (imm : 16 bits) = imm16 in + aarch64_system_exceptions_runtime_smc imm)))`; + + +(*val ReservedValue : unit -> M unit*) + +val _ = Define ` + ((ReservedValue:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$and_boolS ((UsingAArch32 () )) + ( sail2_state_monad$bindS(AArch32_GeneralExceptionsToAArch64 () ) (\ (w__1 : bool) . sail2_state_monad$returnS ((~ w__1))))) (\ (w__2 : + bool) . + if w__2 then AArch32_TakeUndefInstrException__0 () + else AArch64_UndefinedFault () )))`; + + +(*val memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty5 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode:(1)words$word ->(1)words$word ->(5)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L Rm opcode b__1 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__2 = opcode in sail2_state_monad$bindS + (if (((b__2 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 8 : int):ii) : 8 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__11 = opcode in sail2_state_monad$bindS + (if (((b__11 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 16 : int):ii) : 16 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__20 = opcode in sail2_state_monad$bindS + (if (((b__20 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 32 : int):ii) : 32 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__29 = opcode in sail2_state_monad$bindS + (if (((b__29 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((T /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 64 : int):ii) : 64 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__38 = opcode in sail2_state_monad$bindS + (if (((b__38 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 8 : int):ii) : 8 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__47 = opcode in sail2_state_monad$bindS + (if (((b__47 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 16 : int):ii) : 16 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__56 = opcode in sail2_state_monad$bindS + (if (((b__56 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 32 : int):ii) : 32 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (wback : bool) = T in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__65 = opcode in sail2_state_monad$bindS + (if (((b__65 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 64 : int):ii) : 64 itself)) m memop n ((ex_int rpt)) + ((ex_int selem)) t T)))))))`; + + +(*val memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode : mword ty1 -> mword ty1 -> mword ty4 -> mword ty2 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode:(1)words$word ->(1)words$word ->(4)words$word ->(2)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 L opcode b__1 Rn Rt= + (if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__2 = opcode in sail2_state_monad$bindS + (if (((b__2 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__2 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__0 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 8 : int):ii) : 8 itself)) w__0 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__11 = opcode in sail2_state_monad$bindS + (if (((b__11 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__11 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__1 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 16 : int):ii) : 16 itself)) w__1 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__20 = opcode in sail2_state_monad$bindS + (if (((b__20 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__20 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__2 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 32 : int):ii) : 32 itself)) w__2 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B0] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + let (elements : ii) = ((( 64 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__29 = opcode in sail2_state_monad$bindS + (if (((b__29 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__29 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((T /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__3 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 64 : int):ii) : 64 itself)) + ((ex_int elements)) ((make_the_value (( 64 : int):ii) : 64 itself)) w__3 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 8 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 8 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__38 = opcode in sail2_state_monad$bindS + (if (((b__38 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__38 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__4 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 8 : int):ii) : 8 itself)) w__4 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B0;B1] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 16 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 16 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__47 = opcode in sail2_state_monad$bindS + (if (((b__47 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__47 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__5 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 16 : int):ii) : 16 itself)) w__5 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else if ((((((b__0 = (vec_of_bits [B1] : 1 words$word)))) /\ (((b__1 = (vec_of_bits [B1;B0] : 2 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 32 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__56 = opcode in sail2_state_monad$bindS + (if (((b__56 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__56 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__6 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 32 : int):ii) : 32 itself)) w__6 memop n ((ex_int rpt)) + ((ex_int selem)) t F)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (t : ii) = (lem$w2ui Rt) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (undefined_int () ) (\ (m : ii) . + let (wback : bool) = F in + let (memop : MemOp) = + (if (((L = (vec_of_bits [B1] : 1 words$word)))) then MemOp_LOAD + else MemOp_STORE) in + let (esize : ii) = ((( 64 : int):ii)) in + let (elements : ii) = ((( 128 : int):ii) / (( 64 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (rpt : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (selem : ii) . + let b__65 = opcode in sail2_state_monad$bindS + (if (((b__65 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 4 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 4 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 3 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 3 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B0;B1;B1;B1] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 1 : int):ii)) in + let (selem : ii) = ((( 2 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else if (((b__65 = (vec_of_bits [B1;B0;B1;B0] : 4 words$word)))) then + let (rpt : ii) = ((( 2 : int):ii)) in + let (selem : ii) = ((( 1 : int):ii)) in + sail2_state_monad$returnS (rpt, selem) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (rpt, selem))) (\ varstup . let ((rpt : ii), (selem : + ii)) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((((ex_int selem)) <> (( 1 : int):ii))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_int () )) (\ (w__7 : ii) . + aarch64_memory_vector_multiple_nowb ((make_the_value (( 128 : int):ii) : 128 itself)) + ((ex_int elements)) ((make_the_value (( 64 : int):ii) : 64 itself)) w__7 memop n ((ex_int rpt)) + ((ex_int selem)) t F))))))))`; + + +(*val integer_logical_shiftedreg_decode : mword ty1 -> mword ty2 -> mword ty2 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_logical_shiftedreg_decode:(1)words$word ->(2)words$word ->(2)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf opc shift N Rm imm6 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) . sail2_state_monad$bindS + (undefined_LogicalOp () ) (\ (op : LogicalOp) . + let b__0 = opc in + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_ORR in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_EOR in + let (setflags : bool) = F in + (op, setflags) + else + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = T in + (op, setflags)) in + (op, setflags)) in + (op, setflags)) in sail2_state_monad$seqS + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imm6 (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + ReservedValue () + else sail2_state_monad$returnS () ) + (let (shift_type : ShiftType) = (DecodeShift shift) in + let (shift_amount : ii) = (lem$w2ui imm6) in + let (invert : bool) = (N = (vec_of_bits [B1] : 1 words$word)) in + aarch64_integer_logical_shiftedreg d datasize invert m n op setflags shift_amount shift_type))))))`; + + +(*val integer_insext_extract_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty1 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_insext_extract_immediate_decode:(1)words$word ->(2)words$word ->(1)words$word ->(1)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op21 N o0 Rm imms Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in sail2_state_monad$bindS + (undefined_int () ) (\ (lsb : ii) . sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((N <> sf))) then UnallocatedEncoding () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + ReservedValue () + else sail2_state_monad$returnS () )) + (let lsb = (lem$w2ui imms) in + aarch64_integer_insext_extract_immediate d datasize lsb m n)))))`; + + +(*val integer_arithmetic_addsub_shiftedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_addsub_shiftedreg_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 shift Rm imm6 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (setflags : bool) = (S1 = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((shift = (vec_of_bits [B1;B1] : 2 words$word)))) then ReservedValue () + else sail2_state_monad$returnS () ) + (if ((((((sf = (vec_of_bits [B0] : 1 words$word)))) /\ ((((vec_of_bits [access_vec_dec imm6 (( 5 : int):ii)] : 1 words$word) = (vec_of_bits [B1] : 1 words$word))))))) then + ReservedValue () + else sail2_state_monad$returnS () )) + (let (shift_type : ShiftType) = (DecodeShift shift) in + let (shift_amount : ii) = (lem$w2ui imm6) in + aarch64_integer_arithmetic_addsub_shiftedreg d datasize m n setflags shift_amount shift_type + sub_op))))`; + + +(*val integer_arithmetic_addsub_immediate_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_addsub_immediate_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 op S1 shift imm12 Rn Rd= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (setflags : bool) = (S1 = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (imm : 32 bits) . + let b__1 = shift in sail2_state_monad$bindS + (if (((b__1 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (ZeroExtend__0 imm12 ((make_the_value (( 32 : int):ii) : 32 itself)) : ( 32 words$word) M) + else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (ZeroExtend__0 + ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 : int):ii) : 12 itself)) : 12 words$word)) + : 24 words$word)) ((make_the_value (( 32 : int):ii) : 32 itself)) + : ( 32 words$word) M) + else sail2_state_monad$seqS (ReservedValue () ) (sail2_state_monad$returnS imm)) (\ (imm : 32 bits) . + aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 32 : int):ii) : 32 itself)) imm n + setflags sub_op))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (setflags : bool) = (S1 = (vec_of_bits [B1] : 1 words$word)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (imm : 64 bits) . + let b__4 = shift in sail2_state_monad$bindS + (if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (ZeroExtend__0 imm12 ((make_the_value (( 64 : int):ii) : 64 itself)) : ( 64 words$word) M) + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (ZeroExtend__0 + ((concat_vec imm12 ((Zeros__0 ((make_the_value (( 12 : int):ii) : 12 itself)) : 12 words$word)) + : 24 words$word)) ((make_the_value (( 64 : int):ii) : 64 itself)) + : ( 64 words$word) M) + else sail2_state_monad$seqS (ReservedValue () ) (sail2_state_monad$returnS imm)) (\ (imm : 64 bits) . + aarch64_integer_arithmetic_addsub_immediate d ((make_the_value (( 64 : int):ii) : 64 itself)) imm n + setflags sub_op)))))`; + + +(*val integer_arithmetic_addsub_extendedreg_decode : mword ty1 -> mword ty1 -> mword ty1 -> mword ty2 -> mword ty5 -> mword ty3 -> mword ty3 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_arithmetic_addsub_extendedreg_decode:(1)words$word ->(1)words$word ->(1)words$word ->(2)words$word ->(5)words$word ->(3)words$word ->(3)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) sf op S1 opt Rm option_name imm3 Rn Rd= (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in + let (m : ii) = (lem$w2ui Rm) in + let (datasize : int) = + (if (((sf = (vec_of_bits [B1] : 1 words$word)))) then (( 64 : int):ii) + else (( 32 : int):ii)) in + let (sub_op : bool) = (op = (vec_of_bits [B1] : 1 words$word)) in + let (setflags : bool) = (S1 = (vec_of_bits [B1] : 1 words$word)) in + let (extend_type : ExtendType) = (DecodeRegExtend option_name) in + let (shift : ii) = (lem$w2ui imm3) in sail2_state_monad$seqS + (if ((((ex_int shift)) > (( 4 : int):ii))) then ReservedValue () + else sail2_state_monad$returnS () ) + (aarch64_integer_arithmetic_addsub_extendedreg d datasize extend_type m n setflags shift sub_op))))`; + + +(*val DecodeBitMasks : forall 'M . Size 'M => integer -> mword ty1 -> mword ty6 -> mword ty6 -> bool -> M (mword 'M * mword 'M)*) + +val _ = Define ` + ((DecodeBitMasks:int ->(1)words$word ->(6)words$word ->(6)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->((('M words$word#'M words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (M__tv : int) immN imms immr immediate= (sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (tmask : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (wmask : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (tmask_and : 6 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (wmask_and : 6 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (tmask_or : 6 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (wmask_or : 6 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 6 : int):ii) : ( 6 words$word) M) (\ (levels : 6 bits) . sail2_state_monad$bindS + (HighestSetBit ((concat_vec immN ((not_vec imms : 6 words$word)) : 7 words$word))) (\ len . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS ((len >= (( 0 : int):ii))) "") + (if ((len < (( 1 : int):ii))) then ReservedValue () + else sail2_state_monad$returnS () )) + (sail2_state_monad$assert_expS ((M__tv >= ((ex_int ((shl_int (( 1 : int):ii) len)))))) "(M >= (1 << len))")) + (let levels = ((zext_ones (( 6 : int):ii) len : 6 words$word)) in sail2_state_monad$seqS + (if (((immediate /\ (((((and_vec imms levels : 6 words$word)) = levels)))))) then + ReservedValue () + else sail2_state_monad$returnS () ) + (let (S1 : ii) = (lem$w2ui ((and_vec imms levels : 6 words$word))) in + let (R1 : ii) = (lem$w2ui ((and_vec immr levels : 6 words$word))) in + let (diff : ii) = (((ex_int S1)) - ((ex_int R1))) in + let (tmask_and : 6 bits) = + ((or_vec ((GetSlice_int ((make_the_value (( 6 : int):ii) : 6 itself)) diff (( 0 : int):ii) : 6 words$word)) + ((not_vec levels : 6 words$word)) + : 6 words$word)) in + let (tmask_or : 6 bits) = + ((and_vec ((GetSlice_int ((make_the_value (( 6 : int):ii) : 6 itself)) diff (( 0 : int):ii) : 6 words$word)) + levels + : 6 words$word)) in + let (tmask : 64 bits) = ((Ones__0 ((make_the_value (( 64 : int):ii) : 64 itself)) : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 0 : int):ii)] : 1 words$word) + (( 1 : int):ii) + : 1 words$word)) + ((Ones__0 ((make_the_value (( 1 : int):ii) : 1 itself)) : 1 words$word)) + : 2 words$word)) (( 32 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 1 : int):ii) : 1 itself)) : 1 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 0 : int):ii)] : 1 words$word) (( 1 : int):ii) + : 1 words$word)) + : 2 words$word)) (( 32 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 1 : int):ii)] : 1 words$word) + (( 2 : int):ii) + : 2 words$word)) + ((Ones__0 ((make_the_value (( 2 : int):ii) : 2 itself)) : 2 words$word)) + : 4 words$word)) (( 16 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 2 : int):ii) : 2 itself)) : 2 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 1 : int):ii)] : 1 words$word) (( 2 : int):ii) + : 2 words$word)) + : 4 words$word)) (( 16 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 2 : int):ii)] : 1 words$word) + (( 4 : int):ii) + : 4 words$word)) + ((Ones__0 ((make_the_value (( 4 : int):ii) : 4 itself)) : 4 words$word)) + : 8 words$word)) (( 8 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 4 : int):ii) : 4 itself)) : 4 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 2 : int):ii)] : 1 words$word) (( 4 : int):ii) + : 4 words$word)) + : 8 words$word)) (( 8 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 3 : int):ii)] : 1 words$word) + (( 8 : int):ii) + : 8 words$word)) + ((Ones__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) + : 16 words$word)) (( 4 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 3 : int):ii)] : 1 words$word) (( 8 : int):ii) + : 8 words$word)) + : 16 words$word)) (( 4 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 4 : int):ii)] : 1 words$word) + (( 16 : int):ii) + : 16 words$word)) + ((Ones__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + : 32 words$word)) (( 2 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 4 : int):ii)] : 1 words$word) (( 16 : int):ii) + : 16 words$word)) + : 32 words$word)) (( 2 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (tmask : 64 bits) = + ((or_vec + ((and_vec tmask + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec tmask_and (( 5 : int):ii)] : 1 words$word) + (( 32 : int):ii) + : 32 words$word)) + ((Ones__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 64 words$word)) (( 1 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec tmask_or (( 5 : int):ii)] : 1 words$word) (( 32 : int):ii) + : 32 words$word)) + : 64 words$word)) (( 1 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask_and : 6 bits) = ((or_vec immr ((not_vec levels : 6 words$word)) : 6 words$word)) in + let (wmask_or : 6 bits) = ((and_vec immr levels : 6 words$word)) in + let (wmask : 64 bits) = ((Zeros__0 ((make_the_value (( 64 : int):ii) : 64 itself)) : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 1 : int):ii) : 1 itself)) : 1 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 0 : int):ii)] : 1 words$word) + (( 1 : int):ii) + : 1 words$word)) + : 2 words$word)) (( 32 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 0 : int):ii)] : 1 words$word) (( 1 : int):ii) + : 1 words$word)) ((Zeros__0 ((make_the_value (( 1 : int):ii) : 1 itself)) : 1 words$word)) + : 2 words$word)) (( 32 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 2 : int):ii) : 2 itself)) : 2 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 1 : int):ii)] : 1 words$word) + (( 2 : int):ii) + : 2 words$word)) + : 4 words$word)) (( 16 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 1 : int):ii)] : 1 words$word) (( 2 : int):ii) + : 2 words$word)) ((Zeros__0 ((make_the_value (( 2 : int):ii) : 2 itself)) : 2 words$word)) + : 4 words$word)) (( 16 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 4 : int):ii) : 4 itself)) : 4 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 2 : int):ii)] : 1 words$word) + (( 4 : int):ii) + : 4 words$word)) + : 8 words$word)) (( 8 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 2 : int):ii)] : 1 words$word) (( 4 : int):ii) + : 4 words$word)) ((Zeros__0 ((make_the_value (( 4 : int):ii) : 4 itself)) : 4 words$word)) + : 8 words$word)) (( 8 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 3 : int):ii)] : 1 words$word) + (( 8 : int):ii) + : 8 words$word)) + : 16 words$word)) (( 4 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 3 : int):ii)] : 1 words$word) (( 8 : int):ii) + : 8 words$word)) ((Zeros__0 ((make_the_value (( 8 : int):ii) : 8 itself)) : 8 words$word)) + : 16 words$word)) (( 4 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 4 : int):ii)] : 1 words$word) + (( 16 : int):ii) + : 16 words$word)) + : 32 words$word)) (( 2 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 4 : int):ii)] : 1 words$word) (( 16 : int):ii) + : 16 words$word)) + ((Zeros__0 ((make_the_value (( 16 : int):ii) : 16 itself)) : 16 words$word)) + : 32 words$word)) (( 2 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + ((or_vec + ((and_vec wmask + ((replicate_bits + ((concat_vec ((Ones__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + ((replicate_bits (vec_of_bits [access_vec_dec wmask_and (( 5 : int):ii)] : 1 words$word) + (( 32 : int):ii) + : 32 words$word)) + : 64 words$word)) (( 1 : int):ii) + : 64 words$word)) + : 64 words$word)) + ((replicate_bits + ((concat_vec + ((replicate_bits (vec_of_bits [access_vec_dec wmask_or (( 5 : int):ii)] : 1 words$word) (( 32 : int):ii) + : 32 words$word)) + ((Zeros__0 ((make_the_value (( 32 : int):ii) : 32 itself)) : 32 words$word)) + : 64 words$word)) (( 1 : int):ii) + : 64 words$word)) + : 64 words$word)) in + let (wmask : 64 bits) = + (if (((((GetSlice_int ((make_the_value (( 1 : int):ii) : 1 itself)) diff (( 6 : int):ii) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))) then + (and_vec wmask tmask : 64 words$word) + else (or_vec wmask tmask : 64 words$word)) in + sail2_state_monad$returnS ((slice wmask (( 0 : int):ii) M__tv : 'M words$word), (slice tmask (( 0 : int):ii) M__tv : 'M words$word))))))))))))))`; + + +(*val integer_logical_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_logical_immediate_decode:(1)words$word ->(2)words$word ->(1)words$word ->(6)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 opc N immr imms Rn Rd= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) . sail2_state_monad$bindS + (undefined_LogicalOp () ) (\ (op : LogicalOp) . + let b__1 = opc in + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__1 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_ORR in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_EOR in + let (setflags : bool) = F in + (op, setflags) + else + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = T in + (op, setflags)) in + (op, setflags)) in + (op, setflags)) in sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (imm : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((T /\ (((N <> (vec_of_bits [B0] : 1 words$word))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (anon10 : 32 bits) . sail2_state_monad$bindS + (DecodeBitMasks (( 32 : int):ii) N imms immr T : (( 32 words$word # 32 words$word)) M) (\ (w__0 : + ( 32 bits # 32 bits)) . + let (tup__0, tup__1) = w__0 in + let imm = tup__0 in + let anon10 = tup__1 in + aarch64_integer_logical_immediate d ((make_the_value (( 32 : int):ii) : 32 itself)) imm n op setflags)))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (setflags : bool) . sail2_state_monad$bindS + (undefined_LogicalOp () ) (\ (op : LogicalOp) . + let b__6 = opc in + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__6 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__6 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_ORR in + let (setflags : bool) = F in + (op, setflags) + else + let ((op : LogicalOp), (setflags : bool)) = + (if (((b__6 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (op : LogicalOp) = LogicalOp_EOR in + let (setflags : bool) = F in + (op, setflags) + else + let (op : LogicalOp) = LogicalOp_AND in + let (setflags : bool) = T in + (op, setflags)) in + (op, setflags)) in + (op, setflags)) in sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (imm : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((F /\ (((N <> (vec_of_bits [B0] : 1 words$word))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (anon10 : 64 bits) . sail2_state_monad$bindS + (DecodeBitMasks (( 64 : int):ii) N imms immr T : (( 64 words$word # 64 words$word)) M) (\ (w__1 : + ( 64 bits # 64 bits)) . + let (tup__0, tup__1) = w__1 in + let imm = tup__0 in + let anon10 = tup__1 in + aarch64_integer_logical_immediate d ((make_the_value (( 64 : int):ii) : 64 itself)) imm n op setflags))))))))`; + + +(*val integer_bitfield_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((integer_bitfield_decode:(1)words$word ->(2)words$word ->(1)words$word ->(6)words$word ->(6)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) b__0 opc N immr imms Rn Rd= + (if (((b__0 = (vec_of_bits [B0] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inzero : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (extend : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (R1 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (S1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (wmask : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M) (\ (tmask : 32 bits) . + let b__1 = opc in sail2_state_monad$bindS + (if (((b__1 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (inzero : bool) = T in + let (extend : bool) = T in + sail2_state_monad$returnS (extend, inzero) + else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (inzero : bool) = F in + let (extend : bool) = F in + sail2_state_monad$returnS (extend, inzero) + else if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (inzero : bool) = T in + let (extend : bool) = F in + sail2_state_monad$returnS (extend, inzero) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (extend, inzero))) (\ varstup . let ((extend : bool), (inzero : + bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((F /\ (((N <> (vec_of_bits [B1] : 1 words$word))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (if (((T /\ (((((((((N <> (vec_of_bits [B0] : 1 words$word)))) \/ ((((vec_of_bits [access_vec_dec immr (( 5 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word))))))) \/ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)))))))))) then + ReservedValue () + else sail2_state_monad$returnS () )) + (let R1 = (lem$w2ui immr) in + let S1 = (lem$w2ui imms) in sail2_state_monad$bindS + (DecodeBitMasks (( 32 : int):ii) N imms immr F : (( 32 words$word # 32 words$word)) M) (\ (w__0 : + ( 32 bits # 32 bits)) . + let (tup__0, tup__1) = w__0 in + let wmask = tup__0 in + let tmask = tup__1 in + aarch64_integer_bitfield R1 S1 d ((make_the_value (( 32 : int):ii) : 32 itself)) extend inzero n tmask + wmask)))))))))) + else sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref T) + (let (d : ii) = (lem$w2ui Rd) in + let (n : ii) = (lem$w2ui Rn) in sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (inzero : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (extend : bool) . sail2_state_monad$bindS + (undefined_int () ) (\ (R1 : ii) . sail2_state_monad$bindS + (undefined_int () ) (\ (S1 : ii) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (wmask : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M) (\ (tmask : 64 bits) . + let b__6 = opc in sail2_state_monad$bindS + (if (((b__6 = (vec_of_bits [B0;B0] : 2 words$word)))) then + let (inzero : bool) = T in + let (extend : bool) = T in + sail2_state_monad$returnS (extend, inzero) + else if (((b__6 = (vec_of_bits [B0;B1] : 2 words$word)))) then + let (inzero : bool) = F in + let (extend : bool) = F in + sail2_state_monad$returnS (extend, inzero) + else if (((b__6 = (vec_of_bits [B1;B0] : 2 words$word)))) then + let (inzero : bool) = T in + let (extend : bool) = F in + sail2_state_monad$returnS (extend, inzero) + else sail2_state_monad$seqS (UnallocatedEncoding () ) (sail2_state_monad$returnS (extend, inzero))) (\ varstup . let ((extend : bool), (inzero : + bool)) = varstup in sail2_state_monad$seqS (sail2_state_monad$seqS + (if (((T /\ (((N <> (vec_of_bits [B1] : 1 words$word))))))) then ReservedValue () + else sail2_state_monad$returnS () ) + (if (((F /\ (((((((((N <> (vec_of_bits [B0] : 1 words$word)))) \/ ((((vec_of_bits [access_vec_dec immr (( 5 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word))))))) \/ ((((vec_of_bits [access_vec_dec imms (( 5 : int):ii)] : 1 words$word) <> (vec_of_bits [B0] : 1 words$word)))))))))) then + ReservedValue () + else sail2_state_monad$returnS () )) + (let R1 = (lem$w2ui immr) in + let S1 = (lem$w2ui imms) in sail2_state_monad$bindS + (DecodeBitMasks (( 64 : int):ii) N imms immr F : (( 64 words$word # 64 words$word)) M) (\ (w__1 : + ( 64 bits # 64 bits)) . + let (tup__0, tup__1) = w__1 in + let wmask = tup__0 in + let tmask = tup__1 in + aarch64_integer_bitfield R1 S1 d ((make_the_value (( 64 : int):ii) : 64 itself)) extend inzero n tmask + wmask))))))))))))`; + + +(*val decode : mword ty32 -> M unit*) + +val _ = Define ` + ((decode:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op_code= + (if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B1] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (U : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_mul_widening_64128hi_decode sf op54 U Rm o0 Ra Rn Rd + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0;B1] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_general_postidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1;B1] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_general_preidx_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1;B0] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_general_offset_aarch64_memory_pair_general_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_simdfp_register_aarch64_memory_single_simdfp_register__decode size1 V1 opc Rm + option_name S1 Rn Rt + else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1] : 8 words$word)))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_mul_addsub_decode M S1 typ o1 Rm o0 Ra Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_atomicops_ld_decode size1 V1 A R1 Rs o3 opc Rn Rt + else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 11 : int):ii) : 21 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0] + : 21 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (D : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_strip_dp_1src_decode sf S1 opcode2 D Rn Rd + else if (((op_code = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0;B0;B0;B0;B0; + B1;B1;B1;B1;B1;B1;B1;B1] + : 32 words$word)))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_strip_hint_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacda_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B1] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1] : 8 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_monitors_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_signed_offset_normal_aarch64_memory_single_general_immediate_signed_offset_normal__decode + size1 V1 opc imm9 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0;B0] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_general_noalloc_aarch64_memory_pair_general_noalloc__decode opc V1 L imm7 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_mul_product_decode M S1 typ Rm op Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B0;B1;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode2 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacga_dp_2src_decode sf op S1 Rm opcode2 Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_atomicops_cas_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 19 : int):ii) : 13 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0] : 13 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B1;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_register_cpsr_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B0;B0] : 8 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)] : 1 words$word)) in + let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii) : 19 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)] : 1 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in + branch_conditional_cond_decode o1 imm19 o0 cond + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_runtime_hvc_decode opc imm16 op2 LL + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))))) then + let (sz : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_exclusive_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autdb_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 10 : int):ii) : 21 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_rbit_decode sf S1 opcode2 Rn Rd + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1] : 6 words$word)))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii) : 12 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode + size1 V1 opc imm12 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autia_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autia_hint_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_runtime_svc_decode opc imm16 op2 LL + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0;B0;B0;B0] : 9 words$word)))))))))) then + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)] : 1 words$word)) in + let (opc : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (op : 2 bits) = ((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii) : 2 words$word)) in + let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op3 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)] : 1 words$word)) in + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + branch_unconditional_register_decode Z opc op op2 op3 A M Rn Rm + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 5 : int):ii) : 8 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm8 : 8 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 13 : int):ii) : 8 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_move_fp_imm_decode M S1 typ imm8 imm5 Rd + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word)))) then + let (b5 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)] : 1 words$word)) in + let (b40 : 5 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 19 : int):ii) : 5 words$word)) in + let (imm14 : 14 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 5 : int):ii) : 14 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + branch_conditional_test_decode b5 op b40 imm14 Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1] : 6 words$word)))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii) : 12 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode + size1 V1 opc imm12 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii) : 19 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_literal_general_decode opc V1 imm19 Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0;B1] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_simdfp_postidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B1] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_simdfp_preidx_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_simdfp_offset_aarch64_memory_pair_simdfp_postidx__decode opc V1 L imm7 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 24 : int):ii)] : 1 words$word)) in + let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii) : 19 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + branch_conditional_compare_decode sf op imm19 Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_single_simdfp_immediate_signed_offset_normal__decode + size1 V1 opc imm9 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacib_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacib_hint_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm9 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B1] : 6 words$word)))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii) : 12 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_immediate_signed_postidx__decode + size1 V1 opc imm12 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then + let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (opcode : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_vector_multiple_nowb_aarch64_memory_vector_multiple_nowb__decode Q L opcode size1 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))))))))) then + let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_vector_multiple_postinc_aarch64_memory_vector_multiple_nowb__decode Q L Rm opcode size1 + Rn Rt + else if (((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1;B0;B1;B0;B0;B1;B1;B1;B1;B1;B0;B0;B0;B0] + : 20 words$word)))) then + let (opc : 4 bits) = ((subrange_vec_dec op_code (( 24 : int):ii) (( 21 : int):ii) : 4 words$word)) in + let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op3 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)] : 1 words$word)) in + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (op4 : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + branch_unconditional_eret_decode opc op2 op3 A M Rn op4 + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 14 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op : 2 bits) = ((subrange_vec_dec op_code (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_maxmin_decode M S1 typ Rm op Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 17 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_unary_decode M S1 typ opc Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_runtime_smc_decode opc imm16 op2 LL + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_ordered_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_register_aarch64_memory_single_general_register__decode size1 V1 opc Rm + option_name S1 Rn Rt + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0] : 7 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm7 : 7 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 15 : int):ii) : 7 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_pair_simdfp_noalloc_aarch64_memory_pair_simdfp_noalloc__decode opc V1 L imm7 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_debug_breakpoint_decode opc imm16 op2 LL + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii) : 10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B0;B0;B0] : 10 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (op31 : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_mul_uniform_addsub_decode sf op54 op31 Rm o0 Ra Rn Rd + else if (((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) then + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (imm19 : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii) : 19 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_literal_simdfp_decode opc V1 imm19 Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 22 : int):ii) : 10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_sysops_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm6 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_addsub_shiftedreg_decode sf op S1 shift Rm imm6 Rn Rd + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (immr : 6 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii) : 6 words$word)) in + let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_logical_immediate_decode sf opc N immr imms Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii) : 9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0;B1;B0] : 9 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)] : 1 words$word)) in + let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in + integer_conditional_compare_register_decode sf op S1 Rm cond o2 Rn o3 nzcv1 + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0] : 6 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (immr : 6 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 16 : int):ii) : 6 words$word)) in + let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_bitfield_decode sf opc N immr imms Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 22 : int):ii) : 10 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 19 : int):ii)] : 1 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_register_system_decode L o0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii) : 9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0;B0;B1;B0] : 9 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)] : 1 words$word)) in + let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in + integer_conditional_compare_immediate_decode sf op S1 imm5 cond o2 Rn o3 nzcv1 + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_div_decode M S1 typ Rm Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_atomicops_swp_decode size1 V1 A R1 Rs o3 opc Rn Rt + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm12 : 12 bits) = ((subrange_vec_dec op_code (( 21 : int):ii) (( 10 : int):ii) : 12 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_addsub_immediate_decode sf op S1 shift imm12 Rn Rd + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 26 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) then + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (imm26 : 26 bits) = ((subrange_vec_dec op_code (( 25 : int):ii) (( 0 : int):ii) : 26 words$word)) in + branch_unconditional_immediate_decode op imm26 + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autda_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 11 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] + : 20 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_cnt_decode sf S1 opcode2 op Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 27 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 25 : int):ii) (( 24 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))))))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_atomicops_st_decode size1 V1 A R1 Rs o3 opc Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B1] + : 20 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_barriers_decode L op0 op1 CRn CRm opc Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))))) then + let (sz : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_atomicops_cas_pair_decode sz o2 L o1 Rs o0 Rt2 Rn Rt + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 23 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (hw : 2 bits) = ((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii) : 2 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_insext_insert_movewide_decode sf opc hw imm16 Rd + else if (((op_code = (vec_of_bits [B1;B1;B0;B1;B0;B1;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1; + B1;B1;B1;B0;B0;B0;B0;B0] + : 32 words$word)))) then + let (opc : 4 bits) = ((subrange_vec_dec op_code (( 24 : int):ii) (( 21 : int):ii) : 4 words$word)) in + let (op2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op3 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (op4 : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + branch_unconditional_dret_decode opc op2 op3 Rt op4 + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_move_fp_select_decode M S1 typ Rm cond Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_debug_exception_decode opc imm16 op2 LL + else if (((((subrange_vec_dec op_code (( 30 : int):ii) (( 12 : int):ii) : 19 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 19 words$word)))) + then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_rev_decode sf S1 opcode2 opc Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 17 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_convert_fp_decode M S1 typ opc Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacia_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacia_hint_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 24 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (rmode : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_convert_int_decode sf S1 typ rmode opcode Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii) : 9 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0;B1;B0;B0] : 9 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_conditional_select_decode sf op S1 Rm cond o2 Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 21 : int):ii) : 9 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0;B1;B0;B1] : 9 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (A : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o3 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_orderedrcpc_decode size1 V1 A R1 Rs o3 opc Rn Rt + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 21 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0;B0;B1] : 8 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opt : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (option_name : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (imm3 : 3 bits) = ((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_addsub_extendedreg_decode sf op S1 opt Rm option_name imm3 Rn Rd + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) then + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (immlo : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (immhi : 19 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 5 : int):ii) : 19 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_address_pcrel_decode op immlo immhi Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))))))) then + let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_vector_single_nowb_aarch64_memory_vector_single_nowb__decode Q L R1 opcode S1 size1 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))) then + let (Q : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (R1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_vector_single_postinc_aarch64_memory_vector_single_nowb__decode Q L R1 Rm opcode S1 size1 + Rn Rt + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (W1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 11 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_signed_pac_decode size1 V1 M S1 imm9 W1 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autib_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_autib_hint_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (cond : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 4 : int):ii)] : 1 words$word)) in + let (nzcv1 : 4 bits) = ((subrange_vec_dec op_code (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) in + float_compare_cond_decode M S1 typ Rm cond Rn op nzcv1 + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 23 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (o2 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rs : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Rt2 : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_exclusive_single_decode size1 o2 L o1 Rs o0 Rt2 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 24 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0] : 7 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (rmode : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (opcode : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (scale : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_convert_fix_decode sf S1 typ rmode opcode scale Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 18 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (rmode : 3 bits) = ((subrange_vec_dec op_code (( 17 : int):ii) (( 15 : int):ii) : 3 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_round_decode M S1 typ rmode Rn Rd + else if (((((subrange_vec_dec op_code (( 28 : int):ii) (( 24 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (shift : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm6 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_logical_shiftedreg_decode sf opc shift N Rm imm6 Rn Rd + else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii) : 10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B1;B1;B0] : 10 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode2 : 3 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) in + let (C : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (sz : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_crc_decode sf op S1 Rm opcode2 C sz Rn Rd + else if ((((((((subrange_vec_dec op_code (( 28 : int):ii) (( 21 : int):ii) : 8 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0] : 8 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode2 : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_addsub_carry_decode sf op S1 Rm opcode2 Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec op_code (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word))))))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op : 2 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 14 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + float_compare_uncond_decode M S1 typ Rm op Rn opc + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1;B0] + : 20 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word))))))) then + let (L : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (op0 : 2 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 19 : int):ii) : 2 words$word)) in + let (op1 : 3 bits) = ((subrange_vec_dec op_code (( 18 : int):ii) (( 16 : int):ii) : 3 words$word)) in + let (CRn : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (CRm : 4 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 7 : int):ii) (( 5 : int):ii) : 3 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + system_hints_decode L op0 op1 CRn CRm op2 Rt + else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 21 : int):ii) : 10 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B1;B1;B0] : 10 words$word)))) /\ (((((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode2 : 4 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) in + let (op2 : 2 bits) = ((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_shift_variable_decode sf op S1 Rm opcode2 op2 Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 14 : int):ii) : 18 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0;B1;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] + : 18 words$word)))) /\ (((((subrange_vec_dec op_code (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (Z : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 13 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_pac_pacdb_dp_1src_decode sf S1 opcode2 Z Rn Rd + else if ((((((((subrange_vec_dec op_code (( 29 : int):ii) (( 24 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))))))))) then + let (size1 : 2 bits) = ((subrange_vec_dec op_code (( 31 : int):ii) (( 30 : int):ii) : 2 words$word)) in + let (V1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 26 : int):ii)] : 1 words$word)) in + let (opc : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (imm9 : 9 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 12 : int):ii) : 9 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rt : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + memory_single_general_immediate_signed_offset_unpriv_aarch64_memory_single_general_immediate_signed_offset_unpriv__decode + size1 V1 opc imm9 Rn Rt + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B0] : 8 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) /\ ((((((((subrange_vec_dec op_code (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec op_code (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))))))))) then + let (M : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (typ : 2 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 22 : int):ii) : 2 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 12 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + float_arithmetic_addsub_decode M S1 typ Rm op Rn Rd + else if ((((((((subrange_vec_dec op_code (( 30 : int):ii) (( 23 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1] : 8 words$word)))) /\ (((((subrange_vec_dec op_code (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op21 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (N : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 22 : int):ii)] : 1 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 21 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imms : 6 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_insext_extract_immediate_decode sf op21 N o0 Rm imms Rn Rd + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B1;B0;B0;B0;B1;B0] : 11 words$word)))) /\ (((((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (opc : 3 bits) = ((subrange_vec_dec op_code (( 23 : int):ii) (( 21 : int):ii) : 3 words$word)) in + let (imm16 : 16 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 5 : int):ii) : 16 words$word)) in + let (op2 : 3 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let (LL : 2 bits) = ((subrange_vec_dec op_code (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + system_exceptions_debug_halt_decode opc imm16 op2 LL + else if ((((((((subrange_vec_dec op_code (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0;B1;B1] : 8 words$word)))) /\ (((((subrange_vec_dec op_code (( 22 : int):ii) (( 21 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op54 : 2 bits) = ((subrange_vec_dec op_code (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) in + let (U : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 23 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (o0 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 15 : int):ii)] : 1 words$word)) in + let (Ra : 5 bits) = ((subrange_vec_dec op_code (( 14 : int):ii) (( 10 : int):ii) : 5 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_mul_widening_3264_decode sf op54 U Rm o0 Ra Rn Rd + else + let (sf : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 31 : int):ii)] : 1 words$word)) in + let (op : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 30 : int):ii)] : 1 words$word)) in + let (S1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 29 : int):ii)] : 1 words$word)) in + let (Rm : 5 bits) = ((subrange_vec_dec op_code (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (opcode2 : 5 bits) = ((subrange_vec_dec op_code (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (o1 : 1 bits) = ((vec_of_bits [access_vec_dec op_code (( 10 : int):ii)] : 1 words$word)) in + let (Rn : 5 bits) = ((subrange_vec_dec op_code (( 9 : int):ii) (( 5 : int):ii) : 5 words$word)) in + let (Rd : 5 bits) = ((subrange_vec_dec op_code (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + integer_arithmetic_div_decode sf op S1 Rm opcode2 o1 Rn Rd))`; + + +(*val initialize_registers : unit -> M unit*) + +val _ = Define ` + ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS unconditional_ref w__0) + (undefined_bitvector (( 4 : int):ii) : ( 4 words$word) M)) (\ (w__1 : 4 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS currentCond_ref w__1) + (undefined___InstrEnc () )) (\ (w__2 : InstrEnc) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ThisInstrEnc_ref w__2) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__3 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ThisInstr_ref w__3) + (sail2_state_monad$undefined_boolS () )) (\ (w__4 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS Sleeping_ref w__4) + (sail2_state_monad$undefined_boolS () )) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PendingPhysicalSError_ref w__5) + (sail2_state_monad$undefined_boolS () )) (\ (w__6 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PendingInterrupt_ref w__6) + (undefined_bitvector (( 52 : int):ii) : ( 52 words$word) M)) (\ (w__7 : 52 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS Memory_ref w__7) + (sail2_state_monad$undefined_boolS () )) (\ (w__8 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ExclusiveLocal_ref w__8) + (sail2_state_monad$undefined_boolS () )) (\ (w__9 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS BranchTaken_ref w__9) + (undefined_bitvector (( 128 : int):ii) : ( 128 words$word) M)) (\ (w__10 : 128 words$word) . sail2_state_monad$bindS + (undefined_vector (( 32 : int):ii) w__10 : ( ( 128 words$word)list) M) (\ (w__11 : ( 128 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS V_ref w__11) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__12 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 31 : int):ii) w__12 : ( ( 64 words$word)list) M) (\ (w__13 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS R_ref w__13) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__14 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PC_ref w__14) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__15 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VTTBR_EL2_ref w__15) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__16 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VTCR_EL2_ref w__16) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__17 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VSESR_EL2_ref w__17) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__18 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VDFSR_ref w__18) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__19 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VBAR_EL3_ref w__19) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__20 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VBAR_EL2_ref w__20) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__21 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VBAR_EL1_ref w__21) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__22 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS VBAR_ref w__22) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__23 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBR1_EL2_ref w__23) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__24 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBR1_EL1_ref w__24) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__25 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBR0_EL3_ref w__25) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__26 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBR0_EL2_ref w__26) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__27 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBR0_EL1_ref w__27) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__28 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TTBCR_ref w__28) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__29 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TCR_EL3_ref w__29) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__30 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TCR_EL2_ref w__30) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__31 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TCR_EL1_ref w__31) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__32 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_mon_ref w__32) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__33 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL3_ref w__33) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__34 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL2_ref w__34) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__35 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL1_ref w__35) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__36 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SP_EL0_ref w__36) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__37 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_und_ref w__37) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__38 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_svc_ref w__38) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__39 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_mon_ref w__39) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__40 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_irq_ref w__40) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__41 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_hyp_ref w__41) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__42 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_fiq_ref w__42) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__43 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_abt_ref w__43) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__44 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL3_ref w__44) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__45 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL2_ref w__45) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__46 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPSR_EL1_ref w__46) + (undefined_signal () )) (\ (w__47 : signal) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SPIDEN_ref w__47) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__48 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SDER_ref w__48) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__49 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SDCR_ref w__49) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__50 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCTLR_EL3_ref w__50) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__51 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCTLR_EL2_ref w__51) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__52 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCTLR_EL1_ref w__52) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__53 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCTLR_ref w__53) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__54 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCR_EL3_ref w__54) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__55 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS SCR_ref w__55) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__56 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RVBAR_EL3_ref w__56) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__57 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RVBAR_EL2_ref w__57) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__58 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RVBAR_EL1_ref w__58) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__59 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 5 : int):ii) w__59 : ( ( 64 words$word)list) M) (\ (w__60 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS RC_ref w__60) + (undefined_ProcState () )) (\ (w__61 : ProcState) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PSTATE_ref w__61) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__62 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS OSLSR_EL1_ref w__62) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__63 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS OSDLR_EL1_ref w__63) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__64 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MDSCR_EL1_ref w__64) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__65 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MDCR_EL3_ref w__65) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__66 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MDCR_EL2_ref w__66) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__67 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MAIR_EL3_ref w__67) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__68 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MAIR_EL2_ref w__68) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__69 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS MAIR_EL1_ref w__69) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__70 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS LR_mon_ref w__70) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__71 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ID_AA64DFR0_EL1_ref w__71) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__72 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HVBAR_ref w__72) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__73 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HSR_ref w__73) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__74 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HSCTLR_ref w__74) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__75 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HPFAR_EL2_ref w__75) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__76 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HPFAR_ref w__76) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__77 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HIFAR_ref w__77) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__78 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HDFAR_ref w__78) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__79 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HDCR_ref w__79) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__80 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HCR_EL2_ref w__80) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__81 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HCR2_ref w__81) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__82 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HCR_ref w__82) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__83 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FPSR_ref w__83) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__84 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FPSCR_ref w__84) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__85 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FPEXC_ref w__85) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__86 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FPCR_ref w__86) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__87 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FAR_EL3_ref w__87) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__88 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FAR_EL2_ref w__88) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__89 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS FAR_EL1_ref w__89) + (undefined_bitvector (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__90 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS EventRegister_ref w__90) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__91 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ESR_EL3_ref w__91) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__92 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ESR_EL2_ref w__92) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__93 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ESR_EL1_ref w__93) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__94 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_hyp_ref w__94) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__95 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_EL3_ref w__95) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__96 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_EL2_ref w__96) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__97 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS ELR_EL1_ref w__97) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__98 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS EDSCR_ref w__98) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__99 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DSPSR_EL0_ref w__99) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__100 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DSPSR_ref w__100) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__101 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_EL0_ref w__101) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__102 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DLR_ref w__102) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__103 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 16 : int):ii) w__103 : ( ( 64 words$word)list) M) (\ (w__104 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGWVR_EL1_ref w__104) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__105 : 32 words$word) . sail2_state_monad$bindS + (undefined_vector (( 16 : int):ii) w__105 : ( ( 32 words$word)list) M) (\ (w__106 : ( 32 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGWCR_EL1_ref w__106) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__107 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGPRCR_EL1_ref w__107) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__108 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGPRCR_ref w__108) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__109 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGOSLSR_ref w__109) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__110 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGOSDLR_ref w__110) + (undefined_signal () )) (\ (w__111 : signal) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGEN_ref w__111) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__112 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 16 : int):ii) w__112 : ( ( 64 words$word)list) M) (\ (w__113 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGBVR_EL1_ref w__113) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__114 : 32 words$word) . sail2_state_monad$bindS + (undefined_vector (( 16 : int):ii) w__114 : ( ( 32 words$word)list) M) (\ (w__115 : ( 32 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DBGBCR_EL1_ref w__115) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__116 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CPTR_EL3_ref w__116) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__117 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CPTR_EL2_ref w__117) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__118 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CPACR_EL1_ref w__118) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__119 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CONTEXTIDR_EL2_ref w__119) + (undefined_bitvector (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__120 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CONTEXTIDR_EL1_ref w__120) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__121 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APIBKeyLo_EL1_ref w__121) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__122 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APIBKeyHi_EL1_ref w__122) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__123 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APIAKeyLo_EL1_ref w__123) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__124 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APIAKeyHi_EL1_ref w__124) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__125 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APGAKeyLo_EL1_ref w__125) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__126 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APGAKeyHi_EL1_ref w__126) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__127 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APDBKeyLo_EL1_ref w__127) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__128 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APDBKeyHi_EL1_ref w__128) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__129 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS APDAKeyLo_EL1_ref w__129) + (undefined_bitvector (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__130 : 64 bits) . + sail2_state_monad$write_regS APDAKeyHi_EL1_ref w__130)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +val _ = Define ` +((initial_regstate:regstate)= + (<| APDAKeyHi_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APDAKeyLo_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APDBKeyHi_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APDBKeyLo_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APGAKeyHi_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APGAKeyLo_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APIAKeyHi_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APIAKeyLo_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APIBKeyHi_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + APIBKeyLo_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CONTEXTIDR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CONTEXTIDR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CPACR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CPTR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CPTR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DBGBCR_EL1 := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)]); + DBGBVR_EL1 := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + DBGEN := LOW; + DBGOSDLR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DBGOSLSR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DBGPRCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DBGPRCR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DBGWCR_EL1 := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)]); + DBGWVR_EL1 := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + DLR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DLR_EL0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + DSPSR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + DSPSR_EL0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + EDSCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ELR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + ELR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + ELR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + ELR_hyp := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ESR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ESR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ESR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + EventRegister := ((vec_of_bits [B0] : 1 words$word)); + FAR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + FAR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + FAR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + FPCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + FPEXC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + FPSCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + FPSR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HCR2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HCR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + HDCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HDFAR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HIFAR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HPFAR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HPFAR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + HSCTLR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HSR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + HVBAR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ID_AA64DFR0_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + LR_mon := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + MAIR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + MAIR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + MAIR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + MDCR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + MDCR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + MDSCR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + OSDLR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + OSLSR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + PSTATE := + (<| ProcState_N := ((vec_of_bits [B0] : 1 words$word)); + ProcState_Z := ((vec_of_bits [B0] : 1 words$word)); + ProcState_C := ((vec_of_bits [B0] : 1 words$word)); + ProcState_V := ((vec_of_bits [B0] : 1 words$word)); + ProcState_D := ((vec_of_bits [B0] : 1 words$word)); + ProcState_A := ((vec_of_bits [B0] : 1 words$word)); + ProcState_I := ((vec_of_bits [B0] : 1 words$word)); + ProcState_F := ((vec_of_bits [B0] : 1 words$word)); + ProcState_PAN := ((vec_of_bits [B0] : 1 words$word)); + ProcState_UAO := ((vec_of_bits [B0] : 1 words$word)); + ProcState_SS := ((vec_of_bits [B0] : 1 words$word)); + ProcState_IL := ((vec_of_bits [B0] : 1 words$word)); + ProcState_EL := ((vec_of_bits [B0;B0] : 2 words$word)); + ProcState_nRW := ((vec_of_bits [B0] : 1 words$word)); + ProcState_SP := ((vec_of_bits [B0] : 1 words$word)); + ProcState_Q := ((vec_of_bits [B0] : 1 words$word)); + ProcState_GE := ((vec_of_bits [B0;B0;B0;B0] : 4 words$word)); + ProcState_IT := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)); + ProcState_J := ((vec_of_bits [B0] : 1 words$word)); + ProcState_T := ((vec_of_bits [B0] : 1 words$word)); + ProcState_E := ((vec_of_bits [B0] : 1 words$word)); + ProcState_M := ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)) |>); + RC0 := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + RVBAR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + RVBAR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + RVBAR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + SCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SCR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SCTLR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SCTLR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SCTLR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SCTLR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SDCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SDER := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPIDEN := LOW; + SPSR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_abt := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_fiq := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_hyp := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_irq := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_mon := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_svc := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SPSR_und := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + SP_EL0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + SP_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + SP_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + SP_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + SP_mon := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + TCR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TCR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TCR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + TTBCR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + TTBR0_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TTBR0_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TTBR0_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TTBR1_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + TTBR1_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + VBAR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + VBAR_EL1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + VBAR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + VBAR_EL3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + VDFSR := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + VSESR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + VTCR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + VTTBR_EL2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + PC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + R := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + V := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 128 words$word)]); + BranchTaken := F; + ExclusiveLocal := F; + Memory := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 52 words$word)); + PendingInterrupt := F; + PendingPhysicalSError := F; + Sleeping := F; + ThisInstr := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + ThisInstrEnc := A64; + currentCond := ((vec_of_bits [B0;B0;B0;B0] : 4 words$word)); + unconditional := F |>))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml b/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml new file mode 100644 index 00000000..1c379bba --- /dev/null +++ b/snapshots/hol4/sail/aarch64/aarch64_mono_typesScript.sml @@ -0,0 +1,2421 @@ +(*Generated by Lem from aarch64_mono_types.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "aarch64_mono_types" + +(*Generated by Sail from aarch64_mono.*) +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) +val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); + +val _ = Hol_datatype ` + exception = + Error_Undefined of (unit) + | Error_See of (string) + | Error_Implementation_Defined of (string) + | Error_ReservedEncoding of (unit) + | Error_ExceptionTaken of (unit)`; + + + + +val _ = Hol_datatype ` + boolean = FALSE | TRUE`; + + + + +val _ = Hol_datatype ` + signal = LOW | HIGH`; + + + + +val _ = Hol_datatype ` + RetCode = + RC_OK + | RC_UNDEFINED + | RC_UNPREDICTABLE + | RC_SEE + | RC_IMPLEMENTATION_DEFINED + | RC_SUBARCHITECTURE_DEFINED + | RC_EXCEPTION_TAKEN + | RC_ASSERT_FAILED + | RC_UNMATCHED_CASE`; + + + + +val _ = type_abbrev( "CPACRType" , ``: 32 bits``); + +val _ = type_abbrev( "CNTKCTLType" , ``: 32 bits``); + +val _ = type_abbrev( "ESRType" , ``: 32 bits``); + +val _ = type_abbrev( "FPCRType" , ``: 32 bits``); + +val _ = type_abbrev( "MAIRType" , ``: 64 bits``); + +val _ = type_abbrev( "SCRType" , ``: 32 bits``); + +val _ = type_abbrev( "SCTLRType" , ``: 32 bits``); + +val _ = Hol_datatype ` + FPConvOp = + FPConvOp_CVT_FtoI + | FPConvOp_CVT_ItoF + | FPConvOp_MOV_FtoI + | FPConvOp_MOV_ItoF + | FPConvOp_CVT_FtoI_JS`; + + + + +val _ = Hol_datatype ` + Exception = + Exception_Uncategorized + | Exception_WFxTrap + | Exception_CP15RTTrap + | Exception_CP15RRTTrap + | Exception_CP14RTTrap + | Exception_CP14DTTrap + | Exception_AdvSIMDFPAccessTrap + | Exception_FPIDTrap + | Exception_PACTrap + | Exception_CP14RRTTrap + | Exception_IllegalState + | Exception_SupervisorCall + | Exception_HypervisorCall + | Exception_MonitorCall + | Exception_SystemRegisterTrap + | Exception_ERetTrap + | Exception_InstructionAbort + | Exception_PCAlignment + | Exception_DataAbort + | Exception_SPAlignment + | Exception_FPTrappedException + | Exception_SError + | Exception_Breakpoint + | Exception_SoftwareStep + | Exception_Watchpoint + | Exception_SoftwareBreakpoint + | Exception_VectorCatch + | Exception_IRQ + | Exception_FIQ`; + + + + +val _ = Hol_datatype ` + ArchVersion = ARMv8p0 | ARMv8p1 | ARMv8p2 | ARMv8p3`; + + + + +val _ = Hol_datatype ` + Unpredictable = + Unpredictable_WBOVERLAPLD + | Unpredictable_WBOVERLAPST + | Unpredictable_LDPOVERLAP + | Unpredictable_BASEOVERLAP + | Unpredictable_DATAOVERLAP + | Unpredictable_DEVPAGE2 + | Unpredictable_INSTRDEVICE + | Unpredictable_RESCPACR + | Unpredictable_RESMAIR + | Unpredictable_RESTEXCB + | Unpredictable_RESPRRR + | Unpredictable_RESDACR + | Unpredictable_RESVTCRS + | Unpredictable_RESTnSZ + | Unpredictable_OORTnSZ + | Unpredictable_LARGEIPA + | Unpredictable_ESRCONDPASS + | Unpredictable_ILZEROIT + | Unpredictable_ILZEROT + | Unpredictable_BPVECTORCATCHPRI + | Unpredictable_VCMATCHHALF + | Unpredictable_VCMATCHDAPA + | Unpredictable_WPMASKANDBAS + | Unpredictable_WPBASCONTIGUOUS + | Unpredictable_RESWPMASK + | Unpredictable_WPMASKEDBITS + | Unpredictable_RESBPWPCTRL + | Unpredictable_BPNOTIMPL + | Unpredictable_RESBPTYPE + | Unpredictable_BPNOTCTXCMP + | Unpredictable_BPMATCHHALF + | Unpredictable_BPMISMATCHHALF + | Unpredictable_RESTARTALIGNPC + | Unpredictable_RESTARTZEROUPPERPC + | Unpredictable_ZEROUPPER + | Unpredictable_ERETZEROUPPERPC + | Unpredictable_A32FORCEALIGNPC + | Unpredictable_SMD + | Unpredictable_AFUPDATE + | Unpredictable_IESBinDebug + | Unpredictable_ZEROPMSEVFR + | Unpredictable_NOOPTYPES + | Unpredictable_ZEROMINLATENCY + | Unpredictable_CLEARERRITEZERO + | Unpredictable_TBD`; + + + + +val _ = Hol_datatype ` + Constraint = + Constraint_NONE + | Constraint_UNKNOWN + | Constraint_UNDEF + | Constraint_UNDEFEL0 + | Constraint_NOP + | Constraint_TRUE + | Constraint_FALSE + | Constraint_DISABLED + | Constraint_UNCOND + | Constraint_COND + | Constraint_ADDITIONAL_DECODE + | Constraint_WBSUPPRESS + | Constraint_FAULT + | Constraint_FORCE + | Constraint_FORCENOSLCHECK`; + + + + +val _ = Hol_datatype ` + InstrSet = InstrSet_A64 | InstrSet_A32 | InstrSet_T32`; + + + + +val _ = Hol_datatype ` + ProcState = + <| ProcState_N : 1 bits; + ProcState_Z : 1 bits; + ProcState_C : 1 bits; + ProcState_V : 1 bits; + ProcState_D : 1 bits; + ProcState_A : 1 bits; + ProcState_I : 1 bits; + ProcState_F : 1 bits; + ProcState_PAN : 1 bits; + ProcState_UAO : 1 bits; + ProcState_SS : 1 bits; + ProcState_IL : 1 bits; + ProcState_EL : 2 bits; + ProcState_nRW : 1 bits; + ProcState_SP : 1 bits; + ProcState_Q : 1 bits; + ProcState_GE : 4 bits; + ProcState_IT : 8 bits; + ProcState_J : 1 bits; + ProcState_T : 1 bits; + ProcState_E : 1 bits; + ProcState_M : 5 bits |>`; + + + +val _ = Hol_datatype ` + BranchType = + BranchType_CALL + | BranchType_ERET + | BranchType_DBGEXIT + | BranchType_RET + | BranchType_JMP + | BranchType_EXCEPTION + | BranchType_UNKNOWN`; + + + + +val _ = Hol_datatype ` + ExceptionRecord = + <| ExceptionRecord_typ : Exception; + ExceptionRecord_syndrome : 25 bits; + ExceptionRecord_vaddress : 64 bits; + ExceptionRecord_ipavalid : bool; + ExceptionRecord_ipaddress : 52 bits |>`; + + + +val _ = Hol_datatype ` + Fault = + Fault_None + | Fault_AccessFlag + | Fault_Alignment + | Fault_Background + | Fault_Domain + | Fault_Permission + | Fault_Translation + | Fault_AddressSize + | Fault_SyncExternal + | Fault_SyncExternalOnWalk + | Fault_SyncParity + | Fault_SyncParityOnWalk + | Fault_AsyncParity + | Fault_AsyncExternal + | Fault_Debug + | Fault_TLBConflict + | Fault_Lockdown + | Fault_Exclusive + | Fault_ICacheMaint`; + + + + +val _ = Hol_datatype ` + AccType = + AccType_NORMAL + | AccType_VEC + | AccType_STREAM + | AccType_VECSTREAM + | AccType_ATOMIC + | AccType_ATOMICRW + | AccType_ORDERED + | AccType_ORDEREDRW + | AccType_LIMITEDORDERED + | AccType_UNPRIV + | AccType_IFETCH + | AccType_PTW + | AccType_DC + | AccType_IC + | AccType_DCZVA + | AccType_AT`; + + + + +val _ = Hol_datatype ` + FaultRecord = + <| FaultRecord_typ : Fault; + FaultRecord_acctype : AccType; + FaultRecord_ipaddress : 52 bits; + FaultRecord_s2fs1walk : bool; + FaultRecord_write : bool; + FaultRecord_level : ii; + FaultRecord_extflag : 1 bits; + FaultRecord_secondstage : bool; + FaultRecord_domain : 4 bits; + FaultRecord_errortype : 2 bits; + FaultRecord_debugmoe : 4 bits |>`; + + + +val _ = Hol_datatype ` + MBReqDomain = + MBReqDomain_Nonshareable + | MBReqDomain_InnerShareable + | MBReqDomain_OuterShareable + | MBReqDomain_FullSystem`; + + + + +val _ = Hol_datatype ` + MBReqTypes = MBReqTypes_Reads | MBReqTypes_Writes | MBReqTypes_All`; + + + + +val _ = Hol_datatype ` + MemType = MemType_Normal | MemType_Device`; + + + + +val _ = Hol_datatype ` + DeviceType = DeviceType_GRE | DeviceType_nGRE | DeviceType_nGnRE | DeviceType_nGnRnE`; + + + + +val _ = Hol_datatype ` + MemAttrHints = + <| MemAttrHints_attrs : 2 bits; MemAttrHints_hints : 2 bits; MemAttrHints_transient : bool |>`; + + + +val _ = Hol_datatype ` + MemoryAttributes = + <| MemoryAttributes_typ : MemType; + MemoryAttributes_device : DeviceType; + MemoryAttributes_inner : MemAttrHints; + MemoryAttributes_outer : MemAttrHints; + MemoryAttributes_shareable : bool; + MemoryAttributes_outershareable : bool |>`; + + + +val _ = Hol_datatype ` + FullAddress = <| FullAddress_physicaladdress : 52 bits; FullAddress_NS : 1 bits |>`; + + + +val _ = Hol_datatype ` + AddressDescriptor = + <| AddressDescriptor_fault : FaultRecord; + AddressDescriptor_memattrs : MemoryAttributes; + AddressDescriptor_paddress : FullAddress; + AddressDescriptor_vaddress : 64 bits |>`; + + + +val _ = Hol_datatype ` + DescriptorUpdate = + <| DescriptorUpdate_AF : bool; + DescriptorUpdate_AP : bool; + DescriptorUpdate_descaddr : AddressDescriptor |>`; + + + +val _ = Hol_datatype ` + MemAtomicOp = + MemAtomicOp_ADD + | MemAtomicOp_BIC + | MemAtomicOp_EOR + | MemAtomicOp_ORR + | MemAtomicOp_SMAX + | MemAtomicOp_SMIN + | MemAtomicOp_UMAX + | MemAtomicOp_UMIN + | MemAtomicOp_SWP`; + + + + +val _ = Hol_datatype ` + FPType = FPType_Nonzero | FPType_Zero | FPType_Infinity | FPType_QNaN | FPType_SNaN`; + + + + +val _ = Hol_datatype ` + FPExc = + FPExc_InvalidOp + | FPExc_DivideByZero + | FPExc_Overflow + | FPExc_Underflow + | FPExc_Inexact + | FPExc_InputDenorm`; + + + + +val _ = Hol_datatype ` + FPRounding = + FPRounding_TIEEVEN + | FPRounding_POSINF + | FPRounding_NEGINF + | FPRounding_ZERO + | FPRounding_TIEAWAY + | FPRounding_ODD`; + + + + +val _ = Hol_datatype ` + SysRegAccess = + SysRegAccess_OK + | SysRegAccess_UNDEFINED + | SysRegAccess_TrapToEL1 + | SysRegAccess_TrapToEL2 + | SysRegAccess_TrapToEL3`; + + + + +val _ = Hol_datatype ` + SRType = SRType_LSL | SRType_LSR | SRType_ASR | SRType_ROR | SRType_RRX`; + + + + +val _ = Hol_datatype ` + ShiftType = ShiftType_LSL | ShiftType_LSR | ShiftType_ASR | ShiftType_ROR`; + + + + +val _ = Hol_datatype ` + PrefetchHint = Prefetch_READ | Prefetch_WRITE | Prefetch_EXEC`; + + + + +val _ = Hol_datatype ` + InterruptID = + InterruptID_PMUIRQ + | InterruptID_COMMIRQ + | InterruptID_CTIIRQ + | InterruptID_COMMRX + | InterruptID_COMMTX`; + + + + +val _ = Hol_datatype ` + CrossTriggerOut = + CrossTriggerOut_DebugRequest + | CrossTriggerOut_RestartRequest + | CrossTriggerOut_IRQ + | CrossTriggerOut_RSVD3 + | CrossTriggerOut_TraceExtIn0 + | CrossTriggerOut_TraceExtIn1 + | CrossTriggerOut_TraceExtIn2 + | CrossTriggerOut_TraceExtIn3`; + + + + +val _ = Hol_datatype ` + CrossTriggerIn = + CrossTriggerIn_CrossHalt + | CrossTriggerIn_PMUOverflow + | CrossTriggerIn_RSVD2 + | CrossTriggerIn_RSVD3 + | CrossTriggerIn_TraceExtOut0 + | CrossTriggerIn_TraceExtOut1 + | CrossTriggerIn_TraceExtOut2 + | CrossTriggerIn_TraceExtOut3`; + + + + +val _ = Hol_datatype ` + MemBarrierOp = MemBarrierOp_DSB | MemBarrierOp_DMB | MemBarrierOp_ISB`; + + + + +val _ = Hol_datatype ` + AccessDescriptor = + <| AccessDescriptor_acctype : AccType; + AccessDescriptor_page_table_walk : bool; + AccessDescriptor_secondstage : bool; + AccessDescriptor_s2fs1walk : bool; + AccessDescriptor_level : ii |>`; + + + +val _ = Hol_datatype ` + Permissions = + <| Permissions_ap : 3 bits; + Permissions_xn : 1 bits; + Permissions_xxn : 1 bits; + Permissions_pxn : 1 bits |>`; + + + +val _ = Hol_datatype ` + TLBRecord = + <| TLBRecord_perms : Permissions; + TLBRecord_nG : 1 bits; + TLBRecord_domain : 4 bits; + TLBRecord_contiguous : bool; + TLBRecord_level : ii; + TLBRecord_blocksize : ii; + TLBRecord_descupdate : DescriptorUpdate; + TLBRecord_CnP : 1 bits; + TLBRecord_addrdesc : AddressDescriptor |>`; + + + +val _ = Hol_datatype ` + ImmediateOp = ImmediateOp_MOVI | ImmediateOp_MVNI | ImmediateOp_ORR | ImmediateOp_BIC`; + + + + +val _ = Hol_datatype ` + MoveWideOp = MoveWideOp_N | MoveWideOp_Z | MoveWideOp_K`; + + + + +val _ = Hol_datatype ` + SystemAccessType = SystemAccessType_RT | SystemAccessType_RRT | SystemAccessType_DT`; + + + + +val _ = Hol_datatype ` + VBitOp = VBitOp_VBIF | VBitOp_VBIT | VBitOp_VBSL | VBitOp_VEOR`; + + + + +val _ = Hol_datatype ` + TimeStamp = TimeStamp_None | TimeStamp_Virtual | TimeStamp_Physical`; + + + + +val _ = Hol_datatype ` + PrivilegeLevel = PL3 | PL2 | PL1 | PL0`; + + + + +val _ = Hol_datatype ` + AArch32_SErrorSyndrome = + <| AArch32_SErrorSyndrome_AET : 2 bits; AArch32_SErrorSyndrome_ExT : 1 bits |>`; + + + +val _ = Hol_datatype ` + SystemOp = Sys_AT | Sys_DC | Sys_IC | Sys_TLBI | Sys_SYS`; + + + + +val _ = Hol_datatype ` + PCSample = + <| PCSample_valid_name : bool; + PCSample_pc : 64 bits; + PCSample_el : 2 bits; + PCSample_rw : 1 bits; + PCSample_ns : 1 bits; + PCSample_contextidr : 32 bits; + PCSample_contextidr_el2 : 32 bits; + PCSample_vmid : 16 bits |>`; + + + +val _ = Hol_datatype ` + ReduceOp = + ReduceOp_FMINNUM | ReduceOp_FMAXNUM | ReduceOp_FMIN | ReduceOp_FMAX | ReduceOp_FADD | ReduceOp_ADD`; + + + + +val _ = Hol_datatype ` + LogicalOp = LogicalOp_AND | LogicalOp_EOR | LogicalOp_ORR`; + + + + +val _ = Hol_datatype ` + ExtendType = + ExtendType_SXTB + | ExtendType_SXTH + | ExtendType_SXTW + | ExtendType_SXTX + | ExtendType_UXTB + | ExtendType_UXTH + | ExtendType_UXTW + | ExtendType_UXTX`; + + + + +val _ = Hol_datatype ` + SystemHintOp = + SystemHintOp_NOP + | SystemHintOp_YIELD + | SystemHintOp_WFE + | SystemHintOp_WFI + | SystemHintOp_SEV + | SystemHintOp_SEVL + | SystemHintOp_ESB + | SystemHintOp_PSB`; + + + + +val _ = Hol_datatype ` + MemOp = MemOp_LOAD | MemOp_STORE | MemOp_PREFETCH`; + + + + +val _ = Hol_datatype ` + OpType = OpType_Load | OpType_Store | OpType_LoadAtomic | OpType_Branch | OpType_Other`; + + + + +val _ = Hol_datatype ` + FPUnaryOp = FPUnaryOp_ABS | FPUnaryOp_MOV | FPUnaryOp_NEG | FPUnaryOp_SQRT`; + + + + +val _ = Hol_datatype ` + CompareOp = CompareOp_GT | CompareOp_GE | CompareOp_EQ | CompareOp_LE | CompareOp_LT`; + + + + +val _ = Hol_datatype ` + PSTATEField = + PSTATEField_DAIFSet | PSTATEField_DAIFClr | PSTATEField_PAN | PSTATEField_UAO | PSTATEField_SP`; + + + + +val _ = Hol_datatype ` + FPMaxMinOp = FPMaxMinOp_MAX | FPMaxMinOp_MIN | FPMaxMinOp_MAXNUM | FPMaxMinOp_MINNUM`; + + + + +val _ = Hol_datatype ` + CountOp = CountOp_CLZ | CountOp_CLS | CountOp_CNT`; + + + + +val _ = Hol_datatype ` + VFPNegMul = VFPNegMul_VNMLA | VFPNegMul_VNMLS | VFPNegMul_VNMUL`; + + + + +val _ = Hol_datatype ` + VBitOps = VBitOps_VBIF | VBitOps_VBIT | VBitOps_VBSL`; + + + + +val _ = Hol_datatype ` + VCGEtype = VCGEtype_signed | VCGEtype_unsigned | VCGEtype_fp`; + + + + +val _ = Hol_datatype ` + VCGTtype = VCGTtype_signed | VCGTtype_unsigned | VCGTtype_fp`; + + + + +val _ = Hol_datatype ` + InstrEnc = A64 | A32 | T16 | T32`; + + + + + + +val _ = Hol_datatype ` + register_value = + Regval_vector of ((ii # bool # register_value list)) + | Regval_list of ( register_value list) + | Regval_option of ( register_value option) + | Regval_ProcState of (ProcState) + | Regval___InstrEnc of (InstrEnc) + | Regval_bool of (bool) + | Regval_signal of (signal) + | Regval_vector_128_dec_bit of ( 128 words$word) + | Regval_vector_1_dec_bit of ( 1 words$word) + | Regval_vector_32_dec_bit of ( 32 words$word) + | Regval_vector_4_dec_bit of ( 4 words$word) + | Regval_vector_52_dec_bit of ( 52 words$word) + | Regval_vector_64_dec_bit of ( 64 words$word)`; + + + + +val _ = Hol_datatype ` + regstate = + <| APDAKeyHi_EL1 : 64 words$word; + APDAKeyLo_EL1 : 64 words$word; + APDBKeyHi_EL1 : 64 words$word; + APDBKeyLo_EL1 : 64 words$word; + APGAKeyHi_EL1 : 64 words$word; + APGAKeyLo_EL1 : 64 words$word; + APIAKeyHi_EL1 : 64 words$word; + APIAKeyLo_EL1 : 64 words$word; + APIBKeyHi_EL1 : 64 words$word; + APIBKeyLo_EL1 : 64 words$word; + CONTEXTIDR_EL1 : 32 words$word; + CONTEXTIDR_EL2 : 32 words$word; + CPACR_EL1 : 32 words$word; + CPTR_EL2 : 32 words$word; + CPTR_EL3 : 32 words$word; + DBGBCR_EL1 : ( 32 words$word) list; + DBGBVR_EL1 : ( 64 words$word) list; + DBGEN : signal; + DBGOSDLR : 32 words$word; + DBGOSLSR : 32 words$word; + DBGPRCR : 32 words$word; + DBGPRCR_EL1 : 32 words$word; + DBGWCR_EL1 : ( 32 words$word) list; + DBGWVR_EL1 : ( 64 words$word) list; + DLR : 32 words$word; + DLR_EL0 : 64 words$word; + DSPSR : 32 words$word; + DSPSR_EL0 : 32 words$word; + EDSCR : 32 words$word; + ELR_EL1 : 64 words$word; + ELR_EL2 : 64 words$word; + ELR_EL3 : 64 words$word; + ELR_hyp : 32 words$word; + ESR_EL1 : 32 words$word; + ESR_EL2 : 32 words$word; + ESR_EL3 : 32 words$word; + EventRegister : 1 words$word; + FAR_EL1 : 64 words$word; + FAR_EL2 : 64 words$word; + FAR_EL3 : 64 words$word; + FPCR : 32 words$word; + FPEXC : 32 words$word; + FPSCR : 32 words$word; + FPSR : 32 words$word; + HCR : 32 words$word; + HCR2 : 32 words$word; + HCR_EL2 : 64 words$word; + HDCR : 32 words$word; + HDFAR : 32 words$word; + HIFAR : 32 words$word; + HPFAR : 32 words$word; + HPFAR_EL2 : 64 words$word; + HSCTLR : 32 words$word; + HSR : 32 words$word; + HVBAR : 32 words$word; + ID_AA64DFR0_EL1 : 64 words$word; + LR_mon : 32 words$word; + MAIR_EL1 : 64 words$word; + MAIR_EL2 : 64 words$word; + MAIR_EL3 : 64 words$word; + MDCR_EL2 : 32 words$word; + MDCR_EL3 : 32 words$word; + MDSCR_EL1 : 32 words$word; + OSDLR_EL1 : 32 words$word; + OSLSR_EL1 : 32 words$word; + PSTATE : ProcState; + RC0 : ( 64 words$word) list; + RVBAR_EL1 : 64 words$word; + RVBAR_EL2 : 64 words$word; + RVBAR_EL3 : 64 words$word; + SCR : 32 words$word; + SCR_EL3 : 32 words$word; + SCTLR : 32 words$word; + SCTLR_EL1 : 32 words$word; + SCTLR_EL2 : 32 words$word; + SCTLR_EL3 : 32 words$word; + SDCR : 32 words$word; + SDER : 32 words$word; + SPIDEN : signal; + SPSR_EL1 : 32 words$word; + SPSR_EL2 : 32 words$word; + SPSR_EL3 : 32 words$word; + SPSR_abt : 32 words$word; + SPSR_fiq : 32 words$word; + SPSR_hyp : 32 words$word; + SPSR_irq : 32 words$word; + SPSR_mon : 32 words$word; + SPSR_svc : 32 words$word; + SPSR_und : 32 words$word; + SP_EL0 : 64 words$word; + SP_EL1 : 64 words$word; + SP_EL2 : 64 words$word; + SP_EL3 : 64 words$word; + SP_mon : 32 words$word; + TCR_EL1 : 64 words$word; + TCR_EL2 : 64 words$word; + TCR_EL3 : 32 words$word; + TTBCR : 32 words$word; + TTBR0_EL1 : 64 words$word; + TTBR0_EL2 : 64 words$word; + TTBR0_EL3 : 64 words$word; + TTBR1_EL1 : 64 words$word; + TTBR1_EL2 : 64 words$word; + VBAR : 32 words$word; + VBAR_EL1 : 64 words$word; + VBAR_EL2 : 64 words$word; + VBAR_EL3 : 64 words$word; + VDFSR : 32 words$word; + VSESR_EL2 : 32 words$word; + VTCR_EL2 : 32 words$word; + VTTBR_EL2 : 64 words$word; + PC : 64 words$word; + R : ( 64 words$word) list; + V : ( 128 words$word) list; + BranchTaken : bool; + ExclusiveLocal : bool; + Memory : 52 words$word; + PendingInterrupt : bool; + PendingPhysicalSError : bool; + Sleeping : bool; + ThisInstr : 32 words$word; + ThisInstrEnc : InstrEnc; + currentCond : 4 words$word; + unconditional : bool |>`; + + + + + +(*val ProcState_of_regval : register_value -> maybe ProcState*) + +val _ = Define ` + ((ProcState_of_regval:register_value ->(ProcState)option) merge_var= + ((case merge_var of Regval_ProcState (v) => SOME v | g__281 => NONE )))`; + + +(*val regval_of_ProcState : ProcState -> register_value*) + +val _ = Define ` + ((regval_of_ProcState:ProcState -> register_value) v= (Regval_ProcState v))`; + + +(*val __InstrEnc_of_regval : register_value -> maybe __InstrEnc*) + +val _ = Define ` + ((InstrEnc_of_regval:register_value ->(InstrEnc)option) merge_var= + ((case merge_var of Regval___InstrEnc (v) => SOME v | g__280 => NONE )))`; + + +(*val regval_of___InstrEnc : __InstrEnc -> register_value*) + +val _ = Define ` + ((regval_of___InstrEnc:InstrEnc -> register_value) v= (Regval___InstrEnc v))`; + + +(*val bool_of_regval : register_value -> maybe bool*) + +val _ = Define ` + ((bool_of_regval:register_value ->(bool)option) merge_var= + ((case merge_var of Regval_bool (v) => SOME v | g__279 => NONE )))`; + + +(*val regval_of_bool : bool -> register_value*) + +val _ = Define ` + ((regval_of_bool:bool -> register_value) v= (Regval_bool v))`; + + +(*val signal_of_regval : register_value -> maybe signal*) + +val _ = Define ` + ((signal_of_regval:register_value ->(signal)option) merge_var= + ((case merge_var of Regval_signal (v) => SOME v | g__278 => NONE )))`; + + +(*val regval_of_signal : signal -> register_value*) + +val _ = Define ` + ((regval_of_signal:signal -> register_value) v= (Regval_signal v))`; + + +(*val vector_128_dec_bit_of_regval : register_value -> maybe (mword ty128)*) + +val _ = Define ` + ((vector_128_dec_bit_of_regval:register_value ->((128)words$word)option) merge_var= + ((case merge_var of Regval_vector_128_dec_bit (v) => SOME v | g__277 => NONE )))`; + + +(*val regval_of_vector_128_dec_bit : mword ty128 -> register_value*) + +val _ = Define ` + ((regval_of_vector_128_dec_bit:(128)words$word -> register_value) v= (Regval_vector_128_dec_bit v))`; + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +val _ = Define ` + ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= + ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__276 => NONE )))`; + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +val _ = Define ` + ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v= (Regval_vector_1_dec_bit v))`; + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +val _ = Define ` + ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= + ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__275 => NONE )))`; + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +val _ = Define ` + ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`; + + +(*val vector_4_dec_bit_of_regval : register_value -> maybe (mword ty4)*) + +val _ = Define ` + ((vector_4_dec_bit_of_regval:register_value ->((4)words$word)option) merge_var= + ((case merge_var of Regval_vector_4_dec_bit (v) => SOME v | g__274 => NONE )))`; + + +(*val regval_of_vector_4_dec_bit : mword ty4 -> register_value*) + +val _ = Define ` + ((regval_of_vector_4_dec_bit:(4)words$word -> register_value) v= (Regval_vector_4_dec_bit v))`; + + +(*val vector_52_dec_bit_of_regval : register_value -> maybe (mword ty52)*) + +val _ = Define ` + ((vector_52_dec_bit_of_regval:register_value ->((52)words$word)option) merge_var= + ((case merge_var of Regval_vector_52_dec_bit (v) => SOME v | g__273 => NONE )))`; + + +(*val regval_of_vector_52_dec_bit : mword ty52 -> register_value*) + +val _ = Define ` + ((regval_of_vector_52_dec_bit:(52)words$word -> register_value) v= (Regval_vector_52_dec_bit v))`; + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +val _ = Define ` + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__272 => NONE )))`; + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +val _ = Define ` + ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +val _ = Define ` + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= + (\x . (case x of + Regval_vector (_, _, v) => just_list (MAP of_regval1 v) + | _ => NONE + )))`; + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`; + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +val _ = Define ` + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= + (\x . (case x of + Regval_list v => just_list (MAP of_regval1 v) + | _ => NONE + )))`; + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`; + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +val _ = Define ` + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= + (\x . (case x of + Regval_option v => SOME (OPTION_BIND v of_regval1) + | _ => NONE + )))`; + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +val _ = Define ` + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`; + + + +val _ = Define ` + ((APDAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APDAKeyHi_EL1"; + read_from := (\ s . s.APDAKeyHi_EL1); + write_to := (\ v s . (( s with<| APDAKeyHi_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APDAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APDAKeyLo_EL1"; + read_from := (\ s . s.APDAKeyLo_EL1); + write_to := (\ v s . (( s with<| APDAKeyLo_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APDBKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APDBKeyHi_EL1"; + read_from := (\ s . s.APDBKeyHi_EL1); + write_to := (\ v s . (( s with<| APDBKeyHi_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APDBKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APDBKeyLo_EL1"; + read_from := (\ s . s.APDBKeyLo_EL1); + write_to := (\ v s . (( s with<| APDBKeyLo_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APGAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APGAKeyHi_EL1"; + read_from := (\ s . s.APGAKeyHi_EL1); + write_to := (\ v s . (( s with<| APGAKeyHi_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APGAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APGAKeyLo_EL1"; + read_from := (\ s . s.APGAKeyLo_EL1); + write_to := (\ v s . (( s with<| APGAKeyLo_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APIAKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APIAKeyHi_EL1"; + read_from := (\ s . s.APIAKeyHi_EL1); + write_to := (\ v s . (( s with<| APIAKeyHi_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APIAKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APIAKeyLo_EL1"; + read_from := (\ s . s.APIAKeyLo_EL1); + write_to := (\ v s . (( s with<| APIAKeyLo_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APIBKeyHi_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APIBKeyHi_EL1"; + read_from := (\ s . s.APIBKeyHi_EL1); + write_to := (\ v s . (( s with<| APIBKeyHi_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((APIBKeyLo_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "APIBKeyLo_EL1"; + read_from := (\ s . s.APIBKeyLo_EL1); + write_to := (\ v s . (( s with<| APIBKeyLo_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CONTEXTIDR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CONTEXTIDR_EL1"; + read_from := (\ s . s.CONTEXTIDR_EL1); + write_to := (\ v s . (( s with<| CONTEXTIDR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CONTEXTIDR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CONTEXTIDR_EL2"; + read_from := (\ s . s.CONTEXTIDR_EL2); + write_to := (\ v s . (( s with<| CONTEXTIDR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CPACR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CPACR_EL1"; + read_from := (\ s . s.CPACR_EL1); + write_to := (\ v s . (( s with<| CPACR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CPTR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CPTR_EL2"; + read_from := (\ s . s.CPTR_EL2); + write_to := (\ v s . (( s with<| CPTR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CPTR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CPTR_EL3"; + read_from := (\ s . s.CPTR_EL3); + write_to := (\ v s . (( s with<| CPTR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DBGBCR_EL1_ref:((regstate),(register_value),(((32)words$word)list))register_ref)= (<| + name := "DBGBCR_EL1"; + read_from := (\ s . s.DBGBCR_EL1); + write_to := (\ v s . (( s with<| DBGBCR_EL1 := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_32_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_32_dec_bit v)(( 16 : int)) F v) |>))`; + + +val _ = Define ` + ((DBGBVR_EL1_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| + name := "DBGBVR_EL1"; + read_from := (\ s . s.DBGBVR_EL1); + write_to := (\ v s . (( s with<| DBGBVR_EL1 := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 16 : int)) F v) |>))`; + + +val _ = Define ` + ((DBGEN_ref:((regstate),(register_value),(signal))register_ref)= (<| + name := "DBGEN"; + read_from := (\ s . s.DBGEN); + write_to := (\ v s . (( s with<| DBGEN := v |>))); + of_regval := (\ v . signal_of_regval v); + regval_of := (\ v . regval_of_signal v) |>))`; + + +val _ = Define ` + ((DBGOSDLR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DBGOSDLR"; + read_from := (\ s . s.DBGOSDLR); + write_to := (\ v s . (( s with<| DBGOSDLR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DBGOSLSR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DBGOSLSR"; + read_from := (\ s . s.DBGOSLSR); + write_to := (\ v s . (( s with<| DBGOSLSR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DBGPRCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DBGPRCR"; + read_from := (\ s . s.DBGPRCR); + write_to := (\ v s . (( s with<| DBGPRCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DBGPRCR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DBGPRCR_EL1"; + read_from := (\ s . s.DBGPRCR_EL1); + write_to := (\ v s . (( s with<| DBGPRCR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DBGWCR_EL1_ref:((regstate),(register_value),(((32)words$word)list))register_ref)= (<| + name := "DBGWCR_EL1"; + read_from := (\ s . s.DBGWCR_EL1); + write_to := (\ v s . (( s with<| DBGWCR_EL1 := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_32_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_32_dec_bit v)(( 16 : int)) F v) |>))`; + + +val _ = Define ` + ((DBGWVR_EL1_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| + name := "DBGWVR_EL1"; + read_from := (\ s . s.DBGWVR_EL1); + write_to := (\ v s . (( s with<| DBGWVR_EL1 := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 16 : int)) F v) |>))`; + + +val _ = Define ` + ((DLR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DLR"; + read_from := (\ s . s.DLR); + write_to := (\ v s . (( s with<| DLR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DLR_EL0_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "DLR_EL0"; + read_from := (\ s . s.DLR_EL0); + write_to := (\ v s . (( s with<| DLR_EL0 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((DSPSR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DSPSR"; + read_from := (\ s . s.DSPSR); + write_to := (\ v s . (( s with<| DSPSR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((DSPSR_EL0_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "DSPSR_EL0"; + read_from := (\ s . s.DSPSR_EL0); + write_to := (\ v s . (( s with<| DSPSR_EL0 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((EDSCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "EDSCR"; + read_from := (\ s . s.EDSCR); + write_to := (\ v s . (( s with<| EDSCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ELR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "ELR_EL1"; + read_from := (\ s . s.ELR_EL1); + write_to := (\ v s . (( s with<| ELR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((ELR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "ELR_EL2"; + read_from := (\ s . s.ELR_EL2); + write_to := (\ v s . (( s with<| ELR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((ELR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "ELR_EL3"; + read_from := (\ s . s.ELR_EL3); + write_to := (\ v s . (( s with<| ELR_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((ELR_hyp_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "ELR_hyp"; + read_from := (\ s . s.ELR_hyp); + write_to := (\ v s . (( s with<| ELR_hyp := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ESR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "ESR_EL1"; + read_from := (\ s . s.ESR_EL1); + write_to := (\ v s . (( s with<| ESR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ESR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "ESR_EL2"; + read_from := (\ s . s.ESR_EL2); + write_to := (\ v s . (( s with<| ESR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ESR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "ESR_EL3"; + read_from := (\ s . s.ESR_EL3); + write_to := (\ v s . (( s with<| ESR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((EventRegister_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "EventRegister"; + read_from := (\ s . s.EventRegister); + write_to := (\ v s . (( s with<| EventRegister := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((FAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "FAR_EL1"; + read_from := (\ s . s.FAR_EL1); + write_to := (\ v s . (( s with<| FAR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((FAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "FAR_EL2"; + read_from := (\ s . s.FAR_EL2); + write_to := (\ v s . (( s with<| FAR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((FAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "FAR_EL3"; + read_from := (\ s . s.FAR_EL3); + write_to := (\ v s . (( s with<| FAR_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((FPCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "FPCR"; + read_from := (\ s . s.FPCR); + write_to := (\ v s . (( s with<| FPCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((FPEXC_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "FPEXC"; + read_from := (\ s . s.FPEXC); + write_to := (\ v s . (( s with<| FPEXC := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((FPSCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "FPSCR"; + read_from := (\ s . s.FPSCR); + write_to := (\ v s . (( s with<| FPSCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((FPSR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "FPSR"; + read_from := (\ s . s.FPSR); + write_to := (\ v s . (( s with<| FPSR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HCR"; + read_from := (\ s . s.HCR); + write_to := (\ v s . (( s with<| HCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HCR2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HCR2"; + read_from := (\ s . s.HCR2); + write_to := (\ v s . (( s with<| HCR2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HCR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "HCR_EL2"; + read_from := (\ s . s.HCR_EL2); + write_to := (\ v s . (( s with<| HCR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((HDCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HDCR"; + read_from := (\ s . s.HDCR); + write_to := (\ v s . (( s with<| HDCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HDFAR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HDFAR"; + read_from := (\ s . s.HDFAR); + write_to := (\ v s . (( s with<| HDFAR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HIFAR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HIFAR"; + read_from := (\ s . s.HIFAR); + write_to := (\ v s . (( s with<| HIFAR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HPFAR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HPFAR"; + read_from := (\ s . s.HPFAR); + write_to := (\ v s . (( s with<| HPFAR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HPFAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "HPFAR_EL2"; + read_from := (\ s . s.HPFAR_EL2); + write_to := (\ v s . (( s with<| HPFAR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((HSCTLR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HSCTLR"; + read_from := (\ s . s.HSCTLR); + write_to := (\ v s . (( s with<| HSCTLR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HSR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HSR"; + read_from := (\ s . s.HSR); + write_to := (\ v s . (( s with<| HSR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((HVBAR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "HVBAR"; + read_from := (\ s . s.HVBAR); + write_to := (\ v s . (( s with<| HVBAR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ID_AA64DFR0_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "ID_AA64DFR0_EL1"; + read_from := (\ s . s.ID_AA64DFR0_EL1); + write_to := (\ v s . (( s with<| ID_AA64DFR0_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((LR_mon_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "LR_mon"; + read_from := (\ s . s.LR_mon); + write_to := (\ v s . (( s with<| LR_mon := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((MAIR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "MAIR_EL1"; + read_from := (\ s . s.MAIR_EL1); + write_to := (\ v s . (( s with<| MAIR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((MAIR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "MAIR_EL2"; + read_from := (\ s . s.MAIR_EL2); + write_to := (\ v s . (( s with<| MAIR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((MAIR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "MAIR_EL3"; + read_from := (\ s . s.MAIR_EL3); + write_to := (\ v s . (( s with<| MAIR_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((MDCR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "MDCR_EL2"; + read_from := (\ s . s.MDCR_EL2); + write_to := (\ v s . (( s with<| MDCR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((MDCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "MDCR_EL3"; + read_from := (\ s . s.MDCR_EL3); + write_to := (\ v s . (( s with<| MDCR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((MDSCR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "MDSCR_EL1"; + read_from := (\ s . s.MDSCR_EL1); + write_to := (\ v s . (( s with<| MDSCR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((OSDLR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "OSDLR_EL1"; + read_from := (\ s . s.OSDLR_EL1); + write_to := (\ v s . (( s with<| OSDLR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((OSLSR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "OSLSR_EL1"; + read_from := (\ s . s.OSLSR_EL1); + write_to := (\ v s . (( s with<| OSLSR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((PSTATE_ref:((regstate),(register_value),(ProcState))register_ref)= (<| + name := "PSTATE"; + read_from := (\ s . s.PSTATE); + write_to := (\ v s . (( s with<| PSTATE := v |>))); + of_regval := (\ v . ProcState_of_regval v); + regval_of := (\ v . regval_of_ProcState v) |>))`; + + +val _ = Define ` + ((RC_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| + name := "RC"; + read_from := (\ s . s.RC0); + write_to := (\ v s . (( s with<| RC0 := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 5 : int)) F v) |>))`; + + +val _ = Define ` + ((RVBAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "RVBAR_EL1"; + read_from := (\ s . s.RVBAR_EL1); + write_to := (\ v s . (( s with<| RVBAR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((RVBAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "RVBAR_EL2"; + read_from := (\ s . s.RVBAR_EL2); + write_to := (\ v s . (( s with<| RVBAR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((RVBAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "RVBAR_EL3"; + read_from := (\ s . s.RVBAR_EL3); + write_to := (\ v s . (( s with<| RVBAR_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((SCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCR"; + read_from := (\ s . s.SCR); + write_to := (\ v s . (( s with<| SCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCR_EL3"; + read_from := (\ s . s.SCR_EL3); + write_to := (\ v s . (( s with<| SCR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SCTLR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCTLR"; + read_from := (\ s . s.SCTLR); + write_to := (\ v s . (( s with<| SCTLR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SCTLR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCTLR_EL1"; + read_from := (\ s . s.SCTLR_EL1); + write_to := (\ v s . (( s with<| SCTLR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SCTLR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCTLR_EL2"; + read_from := (\ s . s.SCTLR_EL2); + write_to := (\ v s . (( s with<| SCTLR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SCTLR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SCTLR_EL3"; + read_from := (\ s . s.SCTLR_EL3); + write_to := (\ v s . (( s with<| SCTLR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SDCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SDCR"; + read_from := (\ s . s.SDCR); + write_to := (\ v s . (( s with<| SDCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SDER_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SDER"; + read_from := (\ s . s.SDER); + write_to := (\ v s . (( s with<| SDER := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPIDEN_ref:((regstate),(register_value),(signal))register_ref)= (<| + name := "SPIDEN"; + read_from := (\ s . s.SPIDEN); + write_to := (\ v s . (( s with<| SPIDEN := v |>))); + of_regval := (\ v . signal_of_regval v); + regval_of := (\ v . regval_of_signal v) |>))`; + + +val _ = Define ` + ((SPSR_EL1_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_EL1"; + read_from := (\ s . s.SPSR_EL1); + write_to := (\ v s . (( s with<| SPSR_EL1 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_EL2"; + read_from := (\ s . s.SPSR_EL2); + write_to := (\ v s . (( s with<| SPSR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_EL3"; + read_from := (\ s . s.SPSR_EL3); + write_to := (\ v s . (( s with<| SPSR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_abt_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_abt"; + read_from := (\ s . s.SPSR_abt); + write_to := (\ v s . (( s with<| SPSR_abt := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_fiq_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_fiq"; + read_from := (\ s . s.SPSR_fiq); + write_to := (\ v s . (( s with<| SPSR_fiq := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_hyp_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_hyp"; + read_from := (\ s . s.SPSR_hyp); + write_to := (\ v s . (( s with<| SPSR_hyp := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_irq_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_irq"; + read_from := (\ s . s.SPSR_irq); + write_to := (\ v s . (( s with<| SPSR_irq := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_mon_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_mon"; + read_from := (\ s . s.SPSR_mon); + write_to := (\ v s . (( s with<| SPSR_mon := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_svc_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_svc"; + read_from := (\ s . s.SPSR_svc); + write_to := (\ v s . (( s with<| SPSR_svc := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SPSR_und_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SPSR_und"; + read_from := (\ s . s.SPSR_und); + write_to := (\ v s . (( s with<| SPSR_und := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((SP_EL0_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "SP_EL0"; + read_from := (\ s . s.SP_EL0); + write_to := (\ v s . (( s with<| SP_EL0 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((SP_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "SP_EL1"; + read_from := (\ s . s.SP_EL1); + write_to := (\ v s . (( s with<| SP_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((SP_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "SP_EL2"; + read_from := (\ s . s.SP_EL2); + write_to := (\ v s . (( s with<| SP_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((SP_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "SP_EL3"; + read_from := (\ s . s.SP_EL3); + write_to := (\ v s . (( s with<| SP_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((SP_mon_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "SP_mon"; + read_from := (\ s . s.SP_mon); + write_to := (\ v s . (( s with<| SP_mon := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((TCR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TCR_EL1"; + read_from := (\ s . s.TCR_EL1); + write_to := (\ v s . (( s with<| TCR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TCR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TCR_EL2"; + read_from := (\ s . s.TCR_EL2); + write_to := (\ v s . (( s with<| TCR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TCR_EL3_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "TCR_EL3"; + read_from := (\ s . s.TCR_EL3); + write_to := (\ v s . (( s with<| TCR_EL3 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBCR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "TTBCR"; + read_from := (\ s . s.TTBCR); + write_to := (\ v s . (( s with<| TTBCR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBR0_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TTBR0_EL1"; + read_from := (\ s . s.TTBR0_EL1); + write_to := (\ v s . (( s with<| TTBR0_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBR0_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TTBR0_EL2"; + read_from := (\ s . s.TTBR0_EL2); + write_to := (\ v s . (( s with<| TTBR0_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBR0_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TTBR0_EL3"; + read_from := (\ s . s.TTBR0_EL3); + write_to := (\ v s . (( s with<| TTBR0_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBR1_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TTBR1_EL1"; + read_from := (\ s . s.TTBR1_EL1); + write_to := (\ v s . (( s with<| TTBR1_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((TTBR1_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "TTBR1_EL2"; + read_from := (\ s . s.TTBR1_EL2); + write_to := (\ v s . (( s with<| TTBR1_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((VBAR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "VBAR"; + read_from := (\ s . s.VBAR); + write_to := (\ v s . (( s with<| VBAR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((VBAR_EL1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "VBAR_EL1"; + read_from := (\ s . s.VBAR_EL1); + write_to := (\ v s . (( s with<| VBAR_EL1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((VBAR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "VBAR_EL2"; + read_from := (\ s . s.VBAR_EL2); + write_to := (\ v s . (( s with<| VBAR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((VBAR_EL3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "VBAR_EL3"; + read_from := (\ s . s.VBAR_EL3); + write_to := (\ v s . (( s with<| VBAR_EL3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((VDFSR_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "VDFSR"; + read_from := (\ s . s.VDFSR); + write_to := (\ v s . (( s with<| VDFSR := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((VSESR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "VSESR_EL2"; + read_from := (\ s . s.VSESR_EL2); + write_to := (\ v s . (( s with<| VSESR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((VTCR_EL2_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "VTCR_EL2"; + read_from := (\ s . s.VTCR_EL2); + write_to := (\ v s . (( s with<| VTCR_EL2 := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((VTTBR_EL2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "VTTBR_EL2"; + read_from := (\ s . s.VTTBR_EL2); + write_to := (\ v s . (( s with<| VTTBR_EL2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "_PC"; + read_from := (\ s . s.PC); + write_to := (\ v s . (( s with<| PC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((R_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| + name := "_R"; + read_from := (\ s . s.R); + write_to := (\ v s . (( s with<| R := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 31 : int)) F v) |>))`; + + +val _ = Define ` + ((V_ref:((regstate),(register_value),(((128)words$word)list))register_ref)= (<| + name := "_V"; + read_from := (\ s . s.V); + write_to := (\ v s . (( s with<| V := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_128_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_128_dec_bit v)(( 32 : int)) F v) |>))`; + + +val _ = Define ` + ((BranchTaken_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__BranchTaken"; + read_from := (\ s . s.BranchTaken); + write_to := (\ v s . (( s with<| BranchTaken := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((ExclusiveLocal_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__ExclusiveLocal"; + read_from := (\ s . s.ExclusiveLocal); + write_to := (\ v s . (( s with<| ExclusiveLocal := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((Memory_ref:((regstate),(register_value),((52)words$word))register_ref)= (<| + name := "__Memory"; + read_from := (\ s . s.Memory); + write_to := (\ v s . (( s with<| Memory := v |>))); + of_regval := (\ v . vector_52_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_52_dec_bit v) |>))`; + + +val _ = Define ` + ((PendingInterrupt_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__PendingInterrupt"; + read_from := (\ s . s.PendingInterrupt); + write_to := (\ v s . (( s with<| PendingInterrupt := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((PendingPhysicalSError_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__PendingPhysicalSError"; + read_from := (\ s . s.PendingPhysicalSError); + write_to := (\ v s . (( s with<| PendingPhysicalSError := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((Sleeping_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__Sleeping"; + read_from := (\ s . s.Sleeping); + write_to := (\ v s . (( s with<| Sleeping := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((ThisInstr_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "__ThisInstr"; + read_from := (\ s . s.ThisInstr); + write_to := (\ v s . (( s with<| ThisInstr := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((ThisInstrEnc_ref:((regstate),(register_value),(InstrEnc))register_ref)= (<| + name := "__ThisInstrEnc"; + read_from := (\ s . s.ThisInstrEnc); + write_to := (\ v s . (( s with<| ThisInstrEnc := v |>))); + of_regval := (\ v . InstrEnc_of_regval v); + regval_of := (\ v . regval_of___InstrEnc v) |>))`; + + +val _ = Define ` + ((currentCond_ref:((regstate),(register_value),((4)words$word))register_ref)= (<| + name := "__currentCond"; + read_from := (\ s . s.currentCond); + write_to := (\ v s . (( s with<| currentCond := v |>))); + of_regval := (\ v . vector_4_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_4_dec_bit v) |>))`; + + +val _ = Define ` + ((unconditional_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "__unconditional"; + read_from := (\ s . s.unconditional); + write_to := (\ v s . (( s with<| unconditional := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +(*val get_regval : string -> regstate -> maybe register_value*) +val _ = Define ` + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "APDAKeyHi_EL1" then SOME (APDAKeyHi_EL1_ref.regval_of (APDAKeyHi_EL1_ref.read_from s)) else + if reg_name = "APDAKeyLo_EL1" then SOME (APDAKeyLo_EL1_ref.regval_of (APDAKeyLo_EL1_ref.read_from s)) else + if reg_name = "APDBKeyHi_EL1" then SOME (APDBKeyHi_EL1_ref.regval_of (APDBKeyHi_EL1_ref.read_from s)) else + if reg_name = "APDBKeyLo_EL1" then SOME (APDBKeyLo_EL1_ref.regval_of (APDBKeyLo_EL1_ref.read_from s)) else + if reg_name = "APGAKeyHi_EL1" then SOME (APGAKeyHi_EL1_ref.regval_of (APGAKeyHi_EL1_ref.read_from s)) else + if reg_name = "APGAKeyLo_EL1" then SOME (APGAKeyLo_EL1_ref.regval_of (APGAKeyLo_EL1_ref.read_from s)) else + if reg_name = "APIAKeyHi_EL1" then SOME (APIAKeyHi_EL1_ref.regval_of (APIAKeyHi_EL1_ref.read_from s)) else + if reg_name = "APIAKeyLo_EL1" then SOME (APIAKeyLo_EL1_ref.regval_of (APIAKeyLo_EL1_ref.read_from s)) else + if reg_name = "APIBKeyHi_EL1" then SOME (APIBKeyHi_EL1_ref.regval_of (APIBKeyHi_EL1_ref.read_from s)) else + if reg_name = "APIBKeyLo_EL1" then SOME (APIBKeyLo_EL1_ref.regval_of (APIBKeyLo_EL1_ref.read_from s)) else + if reg_name = "CONTEXTIDR_EL1" then SOME (CONTEXTIDR_EL1_ref.regval_of (CONTEXTIDR_EL1_ref.read_from s)) else + if reg_name = "CONTEXTIDR_EL2" then SOME (CONTEXTIDR_EL2_ref.regval_of (CONTEXTIDR_EL2_ref.read_from s)) else + if reg_name = "CPACR_EL1" then SOME (CPACR_EL1_ref.regval_of (CPACR_EL1_ref.read_from s)) else + if reg_name = "CPTR_EL2" then SOME (CPTR_EL2_ref.regval_of (CPTR_EL2_ref.read_from s)) else + if reg_name = "CPTR_EL3" then SOME (CPTR_EL3_ref.regval_of (CPTR_EL3_ref.read_from s)) else + if reg_name = "DBGBCR_EL1" then SOME (DBGBCR_EL1_ref.regval_of (DBGBCR_EL1_ref.read_from s)) else + if reg_name = "DBGBVR_EL1" then SOME (DBGBVR_EL1_ref.regval_of (DBGBVR_EL1_ref.read_from s)) else + if reg_name = "DBGEN" then SOME (DBGEN_ref.regval_of (DBGEN_ref.read_from s)) else + if reg_name = "DBGOSDLR" then SOME (DBGOSDLR_ref.regval_of (DBGOSDLR_ref.read_from s)) else + if reg_name = "DBGOSLSR" then SOME (DBGOSLSR_ref.regval_of (DBGOSLSR_ref.read_from s)) else + if reg_name = "DBGPRCR" then SOME (DBGPRCR_ref.regval_of (DBGPRCR_ref.read_from s)) else + if reg_name = "DBGPRCR_EL1" then SOME (DBGPRCR_EL1_ref.regval_of (DBGPRCR_EL1_ref.read_from s)) else + if reg_name = "DBGWCR_EL1" then SOME (DBGWCR_EL1_ref.regval_of (DBGWCR_EL1_ref.read_from s)) else + if reg_name = "DBGWVR_EL1" then SOME (DBGWVR_EL1_ref.regval_of (DBGWVR_EL1_ref.read_from s)) else + if reg_name = "DLR" then SOME (DLR_ref.regval_of (DLR_ref.read_from s)) else + if reg_name = "DLR_EL0" then SOME (DLR_EL0_ref.regval_of (DLR_EL0_ref.read_from s)) else + if reg_name = "DSPSR" then SOME (DSPSR_ref.regval_of (DSPSR_ref.read_from s)) else + if reg_name = "DSPSR_EL0" then SOME (DSPSR_EL0_ref.regval_of (DSPSR_EL0_ref.read_from s)) else + if reg_name = "EDSCR" then SOME (EDSCR_ref.regval_of (EDSCR_ref.read_from s)) else + if reg_name = "ELR_EL1" then SOME (ELR_EL1_ref.regval_of (ELR_EL1_ref.read_from s)) else + if reg_name = "ELR_EL2" then SOME (ELR_EL2_ref.regval_of (ELR_EL2_ref.read_from s)) else + if reg_name = "ELR_EL3" then SOME (ELR_EL3_ref.regval_of (ELR_EL3_ref.read_from s)) else + if reg_name = "ELR_hyp" then SOME (ELR_hyp_ref.regval_of (ELR_hyp_ref.read_from s)) else + if reg_name = "ESR_EL1" then SOME (ESR_EL1_ref.regval_of (ESR_EL1_ref.read_from s)) else + if reg_name = "ESR_EL2" then SOME (ESR_EL2_ref.regval_of (ESR_EL2_ref.read_from s)) else + if reg_name = "ESR_EL3" then SOME (ESR_EL3_ref.regval_of (ESR_EL3_ref.read_from s)) else + if reg_name = "EventRegister" then SOME (EventRegister_ref.regval_of (EventRegister_ref.read_from s)) else + if reg_name = "FAR_EL1" then SOME (FAR_EL1_ref.regval_of (FAR_EL1_ref.read_from s)) else + if reg_name = "FAR_EL2" then SOME (FAR_EL2_ref.regval_of (FAR_EL2_ref.read_from s)) else + if reg_name = "FAR_EL3" then SOME (FAR_EL3_ref.regval_of (FAR_EL3_ref.read_from s)) else + if reg_name = "FPCR" then SOME (FPCR_ref.regval_of (FPCR_ref.read_from s)) else + if reg_name = "FPEXC" then SOME (FPEXC_ref.regval_of (FPEXC_ref.read_from s)) else + if reg_name = "FPSCR" then SOME (FPSCR_ref.regval_of (FPSCR_ref.read_from s)) else + if reg_name = "FPSR" then SOME (FPSR_ref.regval_of (FPSR_ref.read_from s)) else + if reg_name = "HCR" then SOME (HCR_ref.regval_of (HCR_ref.read_from s)) else + if reg_name = "HCR2" then SOME (HCR2_ref.regval_of (HCR2_ref.read_from s)) else + if reg_name = "HCR_EL2" then SOME (HCR_EL2_ref.regval_of (HCR_EL2_ref.read_from s)) else + if reg_name = "HDCR" then SOME (HDCR_ref.regval_of (HDCR_ref.read_from s)) else + if reg_name = "HDFAR" then SOME (HDFAR_ref.regval_of (HDFAR_ref.read_from s)) else + if reg_name = "HIFAR" then SOME (HIFAR_ref.regval_of (HIFAR_ref.read_from s)) else + if reg_name = "HPFAR" then SOME (HPFAR_ref.regval_of (HPFAR_ref.read_from s)) else + if reg_name = "HPFAR_EL2" then SOME (HPFAR_EL2_ref.regval_of (HPFAR_EL2_ref.read_from s)) else + if reg_name = "HSCTLR" then SOME (HSCTLR_ref.regval_of (HSCTLR_ref.read_from s)) else + if reg_name = "HSR" then SOME (HSR_ref.regval_of (HSR_ref.read_from s)) else + if reg_name = "HVBAR" then SOME (HVBAR_ref.regval_of (HVBAR_ref.read_from s)) else + if reg_name = "ID_AA64DFR0_EL1" then SOME (ID_AA64DFR0_EL1_ref.regval_of (ID_AA64DFR0_EL1_ref.read_from s)) else + if reg_name = "LR_mon" then SOME (LR_mon_ref.regval_of (LR_mon_ref.read_from s)) else + if reg_name = "MAIR_EL1" then SOME (MAIR_EL1_ref.regval_of (MAIR_EL1_ref.read_from s)) else + if reg_name = "MAIR_EL2" then SOME (MAIR_EL2_ref.regval_of (MAIR_EL2_ref.read_from s)) else + if reg_name = "MAIR_EL3" then SOME (MAIR_EL3_ref.regval_of (MAIR_EL3_ref.read_from s)) else + if reg_name = "MDCR_EL2" then SOME (MDCR_EL2_ref.regval_of (MDCR_EL2_ref.read_from s)) else + if reg_name = "MDCR_EL3" then SOME (MDCR_EL3_ref.regval_of (MDCR_EL3_ref.read_from s)) else + if reg_name = "MDSCR_EL1" then SOME (MDSCR_EL1_ref.regval_of (MDSCR_EL1_ref.read_from s)) else + if reg_name = "OSDLR_EL1" then SOME (OSDLR_EL1_ref.regval_of (OSDLR_EL1_ref.read_from s)) else + if reg_name = "OSLSR_EL1" then SOME (OSLSR_EL1_ref.regval_of (OSLSR_EL1_ref.read_from s)) else + if reg_name = "PSTATE" then SOME (PSTATE_ref.regval_of (PSTATE_ref.read_from s)) else + if reg_name = "RC" then SOME (RC_ref.regval_of (RC_ref.read_from s)) else + if reg_name = "RVBAR_EL1" then SOME (RVBAR_EL1_ref.regval_of (RVBAR_EL1_ref.read_from s)) else + if reg_name = "RVBAR_EL2" then SOME (RVBAR_EL2_ref.regval_of (RVBAR_EL2_ref.read_from s)) else + if reg_name = "RVBAR_EL3" then SOME (RVBAR_EL3_ref.regval_of (RVBAR_EL3_ref.read_from s)) else + if reg_name = "SCR" then SOME (SCR_ref.regval_of (SCR_ref.read_from s)) else + if reg_name = "SCR_EL3" then SOME (SCR_EL3_ref.regval_of (SCR_EL3_ref.read_from s)) else + if reg_name = "SCTLR" then SOME (SCTLR_ref.regval_of (SCTLR_ref.read_from s)) else + if reg_name = "SCTLR_EL1" then SOME (SCTLR_EL1_ref.regval_of (SCTLR_EL1_ref.read_from s)) else + if reg_name = "SCTLR_EL2" then SOME (SCTLR_EL2_ref.regval_of (SCTLR_EL2_ref.read_from s)) else + if reg_name = "SCTLR_EL3" then SOME (SCTLR_EL3_ref.regval_of (SCTLR_EL3_ref.read_from s)) else + if reg_name = "SDCR" then SOME (SDCR_ref.regval_of (SDCR_ref.read_from s)) else + if reg_name = "SDER" then SOME (SDER_ref.regval_of (SDER_ref.read_from s)) else + if reg_name = "SPIDEN" then SOME (SPIDEN_ref.regval_of (SPIDEN_ref.read_from s)) else + if reg_name = "SPSR_EL1" then SOME (SPSR_EL1_ref.regval_of (SPSR_EL1_ref.read_from s)) else + if reg_name = "SPSR_EL2" then SOME (SPSR_EL2_ref.regval_of (SPSR_EL2_ref.read_from s)) else + if reg_name = "SPSR_EL3" then SOME (SPSR_EL3_ref.regval_of (SPSR_EL3_ref.read_from s)) else + if reg_name = "SPSR_abt" then SOME (SPSR_abt_ref.regval_of (SPSR_abt_ref.read_from s)) else + if reg_name = "SPSR_fiq" then SOME (SPSR_fiq_ref.regval_of (SPSR_fiq_ref.read_from s)) else + if reg_name = "SPSR_hyp" then SOME (SPSR_hyp_ref.regval_of (SPSR_hyp_ref.read_from s)) else + if reg_name = "SPSR_irq" then SOME (SPSR_irq_ref.regval_of (SPSR_irq_ref.read_from s)) else + if reg_name = "SPSR_mon" then SOME (SPSR_mon_ref.regval_of (SPSR_mon_ref.read_from s)) else + if reg_name = "SPSR_svc" then SOME (SPSR_svc_ref.regval_of (SPSR_svc_ref.read_from s)) else + if reg_name = "SPSR_und" then SOME (SPSR_und_ref.regval_of (SPSR_und_ref.read_from s)) else + if reg_name = "SP_EL0" then SOME (SP_EL0_ref.regval_of (SP_EL0_ref.read_from s)) else + if reg_name = "SP_EL1" then SOME (SP_EL1_ref.regval_of (SP_EL1_ref.read_from s)) else + if reg_name = "SP_EL2" then SOME (SP_EL2_ref.regval_of (SP_EL2_ref.read_from s)) else + if reg_name = "SP_EL3" then SOME (SP_EL3_ref.regval_of (SP_EL3_ref.read_from s)) else + if reg_name = "SP_mon" then SOME (SP_mon_ref.regval_of (SP_mon_ref.read_from s)) else + if reg_name = "TCR_EL1" then SOME (TCR_EL1_ref.regval_of (TCR_EL1_ref.read_from s)) else + if reg_name = "TCR_EL2" then SOME (TCR_EL2_ref.regval_of (TCR_EL2_ref.read_from s)) else + if reg_name = "TCR_EL3" then SOME (TCR_EL3_ref.regval_of (TCR_EL3_ref.read_from s)) else + if reg_name = "TTBCR" then SOME (TTBCR_ref.regval_of (TTBCR_ref.read_from s)) else + if reg_name = "TTBR0_EL1" then SOME (TTBR0_EL1_ref.regval_of (TTBR0_EL1_ref.read_from s)) else + if reg_name = "TTBR0_EL2" then SOME (TTBR0_EL2_ref.regval_of (TTBR0_EL2_ref.read_from s)) else + if reg_name = "TTBR0_EL3" then SOME (TTBR0_EL3_ref.regval_of (TTBR0_EL3_ref.read_from s)) else + if reg_name = "TTBR1_EL1" then SOME (TTBR1_EL1_ref.regval_of (TTBR1_EL1_ref.read_from s)) else + if reg_name = "TTBR1_EL2" then SOME (TTBR1_EL2_ref.regval_of (TTBR1_EL2_ref.read_from s)) else + if reg_name = "VBAR" then SOME (VBAR_ref.regval_of (VBAR_ref.read_from s)) else + if reg_name = "VBAR_EL1" then SOME (VBAR_EL1_ref.regval_of (VBAR_EL1_ref.read_from s)) else + if reg_name = "VBAR_EL2" then SOME (VBAR_EL2_ref.regval_of (VBAR_EL2_ref.read_from s)) else + if reg_name = "VBAR_EL3" then SOME (VBAR_EL3_ref.regval_of (VBAR_EL3_ref.read_from s)) else + if reg_name = "VDFSR" then SOME (VDFSR_ref.regval_of (VDFSR_ref.read_from s)) else + if reg_name = "VSESR_EL2" then SOME (VSESR_EL2_ref.regval_of (VSESR_EL2_ref.read_from s)) else + if reg_name = "VTCR_EL2" then SOME (VTCR_EL2_ref.regval_of (VTCR_EL2_ref.read_from s)) else + if reg_name = "VTTBR_EL2" then SOME (VTTBR_EL2_ref.regval_of (VTTBR_EL2_ref.read_from s)) else + if reg_name = "_PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else + if reg_name = "_R" then SOME (R_ref.regval_of (R_ref.read_from s)) else + if reg_name = "_V" then SOME (V_ref.regval_of (V_ref.read_from s)) else + if reg_name = "__BranchTaken" then SOME (BranchTaken_ref.regval_of (BranchTaken_ref.read_from s)) else + if reg_name = "__ExclusiveLocal" then SOME (ExclusiveLocal_ref.regval_of (ExclusiveLocal_ref.read_from s)) else + if reg_name = "__Memory" then SOME (Memory_ref.regval_of (Memory_ref.read_from s)) else + if reg_name = "__PendingInterrupt" then SOME (PendingInterrupt_ref.regval_of (PendingInterrupt_ref.read_from s)) else + if reg_name = "__PendingPhysicalSError" then SOME (PendingPhysicalSError_ref.regval_of (PendingPhysicalSError_ref.read_from s)) else + if reg_name = "__Sleeping" then SOME (Sleeping_ref.regval_of (Sleeping_ref.read_from s)) else + if reg_name = "__ThisInstr" then SOME (ThisInstr_ref.regval_of (ThisInstr_ref.read_from s)) else + if reg_name = "__ThisInstrEnc" then SOME (ThisInstrEnc_ref.regval_of (ThisInstrEnc_ref.read_from s)) else + if reg_name = "__currentCond" then SOME (currentCond_ref.regval_of (currentCond_ref.read_from s)) else + if reg_name = "__unconditional" then SOME (unconditional_ref.regval_of (unconditional_ref.read_from s)) else + NONE))`; + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +val _ = Define ` + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "APDAKeyHi_EL1" then OPTION_MAP (\ v . APDAKeyHi_EL1_ref.write_to v s) (APDAKeyHi_EL1_ref.of_regval v) else + if reg_name = "APDAKeyLo_EL1" then OPTION_MAP (\ v . APDAKeyLo_EL1_ref.write_to v s) (APDAKeyLo_EL1_ref.of_regval v) else + if reg_name = "APDBKeyHi_EL1" then OPTION_MAP (\ v . APDBKeyHi_EL1_ref.write_to v s) (APDBKeyHi_EL1_ref.of_regval v) else + if reg_name = "APDBKeyLo_EL1" then OPTION_MAP (\ v . APDBKeyLo_EL1_ref.write_to v s) (APDBKeyLo_EL1_ref.of_regval v) else + if reg_name = "APGAKeyHi_EL1" then OPTION_MAP (\ v . APGAKeyHi_EL1_ref.write_to v s) (APGAKeyHi_EL1_ref.of_regval v) else + if reg_name = "APGAKeyLo_EL1" then OPTION_MAP (\ v . APGAKeyLo_EL1_ref.write_to v s) (APGAKeyLo_EL1_ref.of_regval v) else + if reg_name = "APIAKeyHi_EL1" then OPTION_MAP (\ v . APIAKeyHi_EL1_ref.write_to v s) (APIAKeyHi_EL1_ref.of_regval v) else + if reg_name = "APIAKeyLo_EL1" then OPTION_MAP (\ v . APIAKeyLo_EL1_ref.write_to v s) (APIAKeyLo_EL1_ref.of_regval v) else + if reg_name = "APIBKeyHi_EL1" then OPTION_MAP (\ v . APIBKeyHi_EL1_ref.write_to v s) (APIBKeyHi_EL1_ref.of_regval v) else + if reg_name = "APIBKeyLo_EL1" then OPTION_MAP (\ v . APIBKeyLo_EL1_ref.write_to v s) (APIBKeyLo_EL1_ref.of_regval v) else + if reg_name = "CONTEXTIDR_EL1" then OPTION_MAP (\ v . CONTEXTIDR_EL1_ref.write_to v s) (CONTEXTIDR_EL1_ref.of_regval v) else + if reg_name = "CONTEXTIDR_EL2" then OPTION_MAP (\ v . CONTEXTIDR_EL2_ref.write_to v s) (CONTEXTIDR_EL2_ref.of_regval v) else + if reg_name = "CPACR_EL1" then OPTION_MAP (\ v . CPACR_EL1_ref.write_to v s) (CPACR_EL1_ref.of_regval v) else + if reg_name = "CPTR_EL2" then OPTION_MAP (\ v . CPTR_EL2_ref.write_to v s) (CPTR_EL2_ref.of_regval v) else + if reg_name = "CPTR_EL3" then OPTION_MAP (\ v . CPTR_EL3_ref.write_to v s) (CPTR_EL3_ref.of_regval v) else + if reg_name = "DBGBCR_EL1" then OPTION_MAP (\ v . DBGBCR_EL1_ref.write_to v s) (DBGBCR_EL1_ref.of_regval v) else + if reg_name = "DBGBVR_EL1" then OPTION_MAP (\ v . DBGBVR_EL1_ref.write_to v s) (DBGBVR_EL1_ref.of_regval v) else + if reg_name = "DBGEN" then OPTION_MAP (\ v . DBGEN_ref.write_to v s) (DBGEN_ref.of_regval v) else + if reg_name = "DBGOSDLR" then OPTION_MAP (\ v . DBGOSDLR_ref.write_to v s) (DBGOSDLR_ref.of_regval v) else + if reg_name = "DBGOSLSR" then OPTION_MAP (\ v . DBGOSLSR_ref.write_to v s) (DBGOSLSR_ref.of_regval v) else + if reg_name = "DBGPRCR" then OPTION_MAP (\ v . DBGPRCR_ref.write_to v s) (DBGPRCR_ref.of_regval v) else + if reg_name = "DBGPRCR_EL1" then OPTION_MAP (\ v . DBGPRCR_EL1_ref.write_to v s) (DBGPRCR_EL1_ref.of_regval v) else + if reg_name = "DBGWCR_EL1" then OPTION_MAP (\ v . DBGWCR_EL1_ref.write_to v s) (DBGWCR_EL1_ref.of_regval v) else + if reg_name = "DBGWVR_EL1" then OPTION_MAP (\ v . DBGWVR_EL1_ref.write_to v s) (DBGWVR_EL1_ref.of_regval v) else + if reg_name = "DLR" then OPTION_MAP (\ v . DLR_ref.write_to v s) (DLR_ref.of_regval v) else + if reg_name = "DLR_EL0" then OPTION_MAP (\ v . DLR_EL0_ref.write_to v s) (DLR_EL0_ref.of_regval v) else + if reg_name = "DSPSR" then OPTION_MAP (\ v . DSPSR_ref.write_to v s) (DSPSR_ref.of_regval v) else + if reg_name = "DSPSR_EL0" then OPTION_MAP (\ v . DSPSR_EL0_ref.write_to v s) (DSPSR_EL0_ref.of_regval v) else + if reg_name = "EDSCR" then OPTION_MAP (\ v . EDSCR_ref.write_to v s) (EDSCR_ref.of_regval v) else + if reg_name = "ELR_EL1" then OPTION_MAP (\ v . ELR_EL1_ref.write_to v s) (ELR_EL1_ref.of_regval v) else + if reg_name = "ELR_EL2" then OPTION_MAP (\ v . ELR_EL2_ref.write_to v s) (ELR_EL2_ref.of_regval v) else + if reg_name = "ELR_EL3" then OPTION_MAP (\ v . ELR_EL3_ref.write_to v s) (ELR_EL3_ref.of_regval v) else + if reg_name = "ELR_hyp" then OPTION_MAP (\ v . ELR_hyp_ref.write_to v s) (ELR_hyp_ref.of_regval v) else + if reg_name = "ESR_EL1" then OPTION_MAP (\ v . ESR_EL1_ref.write_to v s) (ESR_EL1_ref.of_regval v) else + if reg_name = "ESR_EL2" then OPTION_MAP (\ v . ESR_EL2_ref.write_to v s) (ESR_EL2_ref.of_regval v) else + if reg_name = "ESR_EL3" then OPTION_MAP (\ v . ESR_EL3_ref.write_to v s) (ESR_EL3_ref.of_regval v) else + if reg_name = "EventRegister" then OPTION_MAP (\ v . EventRegister_ref.write_to v s) (EventRegister_ref.of_regval v) else + if reg_name = "FAR_EL1" then OPTION_MAP (\ v . FAR_EL1_ref.write_to v s) (FAR_EL1_ref.of_regval v) else + if reg_name = "FAR_EL2" then OPTION_MAP (\ v . FAR_EL2_ref.write_to v s) (FAR_EL2_ref.of_regval v) else + if reg_name = "FAR_EL3" then OPTION_MAP (\ v . FAR_EL3_ref.write_to v s) (FAR_EL3_ref.of_regval v) else + if reg_name = "FPCR" then OPTION_MAP (\ v . FPCR_ref.write_to v s) (FPCR_ref.of_regval v) else + if reg_name = "FPEXC" then OPTION_MAP (\ v . FPEXC_ref.write_to v s) (FPEXC_ref.of_regval v) else + if reg_name = "FPSCR" then OPTION_MAP (\ v . FPSCR_ref.write_to v s) (FPSCR_ref.of_regval v) else + if reg_name = "FPSR" then OPTION_MAP (\ v . FPSR_ref.write_to v s) (FPSR_ref.of_regval v) else + if reg_name = "HCR" then OPTION_MAP (\ v . HCR_ref.write_to v s) (HCR_ref.of_regval v) else + if reg_name = "HCR2" then OPTION_MAP (\ v . HCR2_ref.write_to v s) (HCR2_ref.of_regval v) else + if reg_name = "HCR_EL2" then OPTION_MAP (\ v . HCR_EL2_ref.write_to v s) (HCR_EL2_ref.of_regval v) else + if reg_name = "HDCR" then OPTION_MAP (\ v . HDCR_ref.write_to v s) (HDCR_ref.of_regval v) else + if reg_name = "HDFAR" then OPTION_MAP (\ v . HDFAR_ref.write_to v s) (HDFAR_ref.of_regval v) else + if reg_name = "HIFAR" then OPTION_MAP (\ v . HIFAR_ref.write_to v s) (HIFAR_ref.of_regval v) else + if reg_name = "HPFAR" then OPTION_MAP (\ v . HPFAR_ref.write_to v s) (HPFAR_ref.of_regval v) else + if reg_name = "HPFAR_EL2" then OPTION_MAP (\ v . HPFAR_EL2_ref.write_to v s) (HPFAR_EL2_ref.of_regval v) else + if reg_name = "HSCTLR" then OPTION_MAP (\ v . HSCTLR_ref.write_to v s) (HSCTLR_ref.of_regval v) else + if reg_name = "HSR" then OPTION_MAP (\ v . HSR_ref.write_to v s) (HSR_ref.of_regval v) else + if reg_name = "HVBAR" then OPTION_MAP (\ v . HVBAR_ref.write_to v s) (HVBAR_ref.of_regval v) else + if reg_name = "ID_AA64DFR0_EL1" then OPTION_MAP (\ v . ID_AA64DFR0_EL1_ref.write_to v s) (ID_AA64DFR0_EL1_ref.of_regval v) else + if reg_name = "LR_mon" then OPTION_MAP (\ v . LR_mon_ref.write_to v s) (LR_mon_ref.of_regval v) else + if reg_name = "MAIR_EL1" then OPTION_MAP (\ v . MAIR_EL1_ref.write_to v s) (MAIR_EL1_ref.of_regval v) else + if reg_name = "MAIR_EL2" then OPTION_MAP (\ v . MAIR_EL2_ref.write_to v s) (MAIR_EL2_ref.of_regval v) else + if reg_name = "MAIR_EL3" then OPTION_MAP (\ v . MAIR_EL3_ref.write_to v s) (MAIR_EL3_ref.of_regval v) else + if reg_name = "MDCR_EL2" then OPTION_MAP (\ v . MDCR_EL2_ref.write_to v s) (MDCR_EL2_ref.of_regval v) else + if reg_name = "MDCR_EL3" then OPTION_MAP (\ v . MDCR_EL3_ref.write_to v s) (MDCR_EL3_ref.of_regval v) else + if reg_name = "MDSCR_EL1" then OPTION_MAP (\ v . MDSCR_EL1_ref.write_to v s) (MDSCR_EL1_ref.of_regval v) else + if reg_name = "OSDLR_EL1" then OPTION_MAP (\ v . OSDLR_EL1_ref.write_to v s) (OSDLR_EL1_ref.of_regval v) else + if reg_name = "OSLSR_EL1" then OPTION_MAP (\ v . OSLSR_EL1_ref.write_to v s) (OSLSR_EL1_ref.of_regval v) else + if reg_name = "PSTATE" then OPTION_MAP (\ v . PSTATE_ref.write_to v s) (PSTATE_ref.of_regval v) else + if reg_name = "RC" then OPTION_MAP (\ v . RC_ref.write_to v s) (RC_ref.of_regval v) else + if reg_name = "RVBAR_EL1" then OPTION_MAP (\ v . RVBAR_EL1_ref.write_to v s) (RVBAR_EL1_ref.of_regval v) else + if reg_name = "RVBAR_EL2" then OPTION_MAP (\ v . RVBAR_EL2_ref.write_to v s) (RVBAR_EL2_ref.of_regval v) else + if reg_name = "RVBAR_EL3" then OPTION_MAP (\ v . RVBAR_EL3_ref.write_to v s) (RVBAR_EL3_ref.of_regval v) else + if reg_name = "SCR" then OPTION_MAP (\ v . SCR_ref.write_to v s) (SCR_ref.of_regval v) else + if reg_name = "SCR_EL3" then OPTION_MAP (\ v . SCR_EL3_ref.write_to v s) (SCR_EL3_ref.of_regval v) else + if reg_name = "SCTLR" then OPTION_MAP (\ v . SCTLR_ref.write_to v s) (SCTLR_ref.of_regval v) else + if reg_name = "SCTLR_EL1" then OPTION_MAP (\ v . SCTLR_EL1_ref.write_to v s) (SCTLR_EL1_ref.of_regval v) else + if reg_name = "SCTLR_EL2" then OPTION_MAP (\ v . SCTLR_EL2_ref.write_to v s) (SCTLR_EL2_ref.of_regval v) else + if reg_name = "SCTLR_EL3" then OPTION_MAP (\ v . SCTLR_EL3_ref.write_to v s) (SCTLR_EL3_ref.of_regval v) else + if reg_name = "SDCR" then OPTION_MAP (\ v . SDCR_ref.write_to v s) (SDCR_ref.of_regval v) else + if reg_name = "SDER" then OPTION_MAP (\ v . SDER_ref.write_to v s) (SDER_ref.of_regval v) else + if reg_name = "SPIDEN" then OPTION_MAP (\ v . SPIDEN_ref.write_to v s) (SPIDEN_ref.of_regval v) else + if reg_name = "SPSR_EL1" then OPTION_MAP (\ v . SPSR_EL1_ref.write_to v s) (SPSR_EL1_ref.of_regval v) else + if reg_name = "SPSR_EL2" then OPTION_MAP (\ v . SPSR_EL2_ref.write_to v s) (SPSR_EL2_ref.of_regval v) else + if reg_name = "SPSR_EL3" then OPTION_MAP (\ v . SPSR_EL3_ref.write_to v s) (SPSR_EL3_ref.of_regval v) else + if reg_name = "SPSR_abt" then OPTION_MAP (\ v . SPSR_abt_ref.write_to v s) (SPSR_abt_ref.of_regval v) else + if reg_name = "SPSR_fiq" then OPTION_MAP (\ v . SPSR_fiq_ref.write_to v s) (SPSR_fiq_ref.of_regval v) else + if reg_name = "SPSR_hyp" then OPTION_MAP (\ v . SPSR_hyp_ref.write_to v s) (SPSR_hyp_ref.of_regval v) else + if reg_name = "SPSR_irq" then OPTION_MAP (\ v . SPSR_irq_ref.write_to v s) (SPSR_irq_ref.of_regval v) else + if reg_name = "SPSR_mon" then OPTION_MAP (\ v . SPSR_mon_ref.write_to v s) (SPSR_mon_ref.of_regval v) else + if reg_name = "SPSR_svc" then OPTION_MAP (\ v . SPSR_svc_ref.write_to v s) (SPSR_svc_ref.of_regval v) else + if reg_name = "SPSR_und" then OPTION_MAP (\ v . SPSR_und_ref.write_to v s) (SPSR_und_ref.of_regval v) else + if reg_name = "SP_EL0" then OPTION_MAP (\ v . SP_EL0_ref.write_to v s) (SP_EL0_ref.of_regval v) else + if reg_name = "SP_EL1" then OPTION_MAP (\ v . SP_EL1_ref.write_to v s) (SP_EL1_ref.of_regval v) else + if reg_name = "SP_EL2" then OPTION_MAP (\ v . SP_EL2_ref.write_to v s) (SP_EL2_ref.of_regval v) else + if reg_name = "SP_EL3" then OPTION_MAP (\ v . SP_EL3_ref.write_to v s) (SP_EL3_ref.of_regval v) else + if reg_name = "SP_mon" then OPTION_MAP (\ v . SP_mon_ref.write_to v s) (SP_mon_ref.of_regval v) else + if reg_name = "TCR_EL1" then OPTION_MAP (\ v . TCR_EL1_ref.write_to v s) (TCR_EL1_ref.of_regval v) else + if reg_name = "TCR_EL2" then OPTION_MAP (\ v . TCR_EL2_ref.write_to v s) (TCR_EL2_ref.of_regval v) else + if reg_name = "TCR_EL3" then OPTION_MAP (\ v . TCR_EL3_ref.write_to v s) (TCR_EL3_ref.of_regval v) else + if reg_name = "TTBCR" then OPTION_MAP (\ v . TTBCR_ref.write_to v s) (TTBCR_ref.of_regval v) else + if reg_name = "TTBR0_EL1" then OPTION_MAP (\ v . TTBR0_EL1_ref.write_to v s) (TTBR0_EL1_ref.of_regval v) else + if reg_name = "TTBR0_EL2" then OPTION_MAP (\ v . TTBR0_EL2_ref.write_to v s) (TTBR0_EL2_ref.of_regval v) else + if reg_name = "TTBR0_EL3" then OPTION_MAP (\ v . TTBR0_EL3_ref.write_to v s) (TTBR0_EL3_ref.of_regval v) else + if reg_name = "TTBR1_EL1" then OPTION_MAP (\ v . TTBR1_EL1_ref.write_to v s) (TTBR1_EL1_ref.of_regval v) else + if reg_name = "TTBR1_EL2" then OPTION_MAP (\ v . TTBR1_EL2_ref.write_to v s) (TTBR1_EL2_ref.of_regval v) else + if reg_name = "VBAR" then OPTION_MAP (\ v . VBAR_ref.write_to v s) (VBAR_ref.of_regval v) else + if reg_name = "VBAR_EL1" then OPTION_MAP (\ v . VBAR_EL1_ref.write_to v s) (VBAR_EL1_ref.of_regval v) else + if reg_name = "VBAR_EL2" then OPTION_MAP (\ v . VBAR_EL2_ref.write_to v s) (VBAR_EL2_ref.of_regval v) else + if reg_name = "VBAR_EL3" then OPTION_MAP (\ v . VBAR_EL3_ref.write_to v s) (VBAR_EL3_ref.of_regval v) else + if reg_name = "VDFSR" then OPTION_MAP (\ v . VDFSR_ref.write_to v s) (VDFSR_ref.of_regval v) else + if reg_name = "VSESR_EL2" then OPTION_MAP (\ v . VSESR_EL2_ref.write_to v s) (VSESR_EL2_ref.of_regval v) else + if reg_name = "VTCR_EL2" then OPTION_MAP (\ v . VTCR_EL2_ref.write_to v s) (VTCR_EL2_ref.of_regval v) else + if reg_name = "VTTBR_EL2" then OPTION_MAP (\ v . VTTBR_EL2_ref.write_to v s) (VTTBR_EL2_ref.of_regval v) else + if reg_name = "_PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else + if reg_name = "_R" then OPTION_MAP (\ v . R_ref.write_to v s) (R_ref.of_regval v) else + if reg_name = "_V" then OPTION_MAP (\ v . V_ref.write_to v s) (V_ref.of_regval v) else + if reg_name = "__BranchTaken" then OPTION_MAP (\ v . BranchTaken_ref.write_to v s) (BranchTaken_ref.of_regval v) else + if reg_name = "__ExclusiveLocal" then OPTION_MAP (\ v . ExclusiveLocal_ref.write_to v s) (ExclusiveLocal_ref.of_regval v) else + if reg_name = "__Memory" then OPTION_MAP (\ v . Memory_ref.write_to v s) (Memory_ref.of_regval v) else + if reg_name = "__PendingInterrupt" then OPTION_MAP (\ v . PendingInterrupt_ref.write_to v s) (PendingInterrupt_ref.of_regval v) else + if reg_name = "__PendingPhysicalSError" then OPTION_MAP (\ v . PendingPhysicalSError_ref.write_to v s) (PendingPhysicalSError_ref.of_regval v) else + if reg_name = "__Sleeping" then OPTION_MAP (\ v . Sleeping_ref.write_to v s) (Sleeping_ref.of_regval v) else + if reg_name = "__ThisInstr" then OPTION_MAP (\ v . ThisInstr_ref.write_to v s) (ThisInstr_ref.of_regval v) else + if reg_name = "__ThisInstrEnc" then OPTION_MAP (\ v . ThisInstrEnc_ref.write_to v s) (ThisInstrEnc_ref.of_regval v) else + if reg_name = "__currentCond" then OPTION_MAP (\ v . currentCond_ref.write_to v s) (currentCond_ref.of_regval v) else + if reg_name = "__unconditional" then OPTION_MAP (\ v . unconditional_ref.write_to v s) (unconditional_ref.of_regval v) else + NONE))`; + + +val _ = Define ` + ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`; + + + +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``); +val _ = export_theory() + diff --git a/snapshots/hol4/sail/cheri/cheriScript.sml b/snapshots/hol4/sail/cheri/cheriScript.sml index d3e724c0..5fa55723 100644 --- a/snapshots/hol4/sail/cheri/cheriScript.sml +++ b/snapshots/hol4/sail/cheri/cheriScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from cheri.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory cheri_typesTheory mips_extrasTheory; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory cheri_typesTheory mips_extrasTheory; val _ = numLib.prefer_num(); @@ -10,11 +10,12 @@ val _ = new_theory "cheri" (*Generated by Sail from cheri.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Cheri_types*) (*open import Mips_extras*) @@ -22,33 +23,49 @@ val _ = Define ` ((cap_size:int)= ((( 32 : int):ii)))`; -(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) -val _ = Define ` - ((undefined_option:'a ->(regstate)state_monad$sequential_state ->((('a option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) typ_a= (state_monad$seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`; +(*val neq_bool : bool -> bool -> bool*) +val _ = Define ` + ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; -(*val neq_bool : bool -> bool -> bool*) +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) val _ = Define ` - ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; + ((undefined_option:'a ->(regstate)sail2_state_monad$sequential_state ->((('a option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ_a= (sail2_state_monad$bindS + (undefined_unit () ) (\ (u_0 : unit) . + let (u_1 : 'a) = typ_a in + sail2_state$internal_pickS [SOME u_1;NONE])))`; + +(*val is_none : forall 'a. maybe 'a -> bool*) + +val _ = Define ` + ((is_none:'a option -> bool) opt= ((case opt of SOME (_) => F | NONE => T )))`; +(*val is_some : forall 'a. maybe 'a -> bool*) +val _ = Define ` + ((is_some:'a option -> bool) opt= ((case opt of SOME (_) => T | NONE => F )))`; -(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) +(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*) + +val _ = Define ` + ((sail_mask:'len itself -> 'v words$word -> 'len words$word) len v= + (let len = (size_itself_int len) in + if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len : 'len words$word) + else (zero_extend v len : 'len words$word)))`; -(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) @@ -56,29 +73,25 @@ val _ = Define ` val _ = Define ` ((cast_unit_vec0:bitU ->(1)words$word) b= - ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | B1 => (vec_of_bits [B1] : 1 words$word) )))`; + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | _ => (vec_of_bits [B1] : 1 words$word) )))`; -(*val DecStr : ii -> string*) - -(*val HexStr : ii -> string*) - (*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) val _ = Define ` - ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= - (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= + (write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word) addr data))`; -(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) val _ = Define ` - ((MIPS_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + ((MIPS_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] @@ -91,28 +104,23 @@ val _ = Define ` (*val undefined_exception : unit -> M exception*) val _ = Define ` - ((undefined_exception:unit ->(regstate)state_monad$sequential_state ->(((exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (state_monad$seqS - (undefined_unit () ) - (undefined_string () )) (\ (w__0 : string) . state_monad$seqS (state_monad$seqS (state_monad$seqS - (undefined_unit () ) - (undefined_unit () )) - (undefined_unit () )) - (internal_pick - [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`; + ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_string () ) (\ (u_0 : string) . sail2_state_monad$bindS + (undefined_unit () ) (\ (u_1 : unit) . + sail2_state$internal_pickS + [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]))))`; -(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) -(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) val _ = Define ` - ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + ((mips_sign_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend v m__tv : 'm words$word)))`; val _ = Define ` - ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv : 'm words$word)))`; + ((mips_zero_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend v m__tv : 'm words$word)))`; (*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) @@ -127,13 +135,13 @@ val _ = Define ` ((ones:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B1] : 1 words$word) n__tv : 'n words$word)))`; -(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) val _ = Define ` ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`; @@ -160,7 +168,7 @@ val _ = Define ` (*val bit_to_bool : bitU -> bool*) val _ = Define ` - ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | B0 => F )))`; + ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | _ => F )))`; (*val bits_to_bool : mword ty1 -> bool*) @@ -172,12 +180,12 @@ val _ = Define ` (* \function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. *) -(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) +(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*) val _ = Define ` ((to_bits:'l itself -> int -> 'l words$word) l n= (let l = (size_itself_int l) in - (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii) : 'l words$word)))`; + (get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii) : 'l words$word)))`; (*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) @@ -190,167 +198,242 @@ val _ = Define ` (*val undefined_CauseReg : unit -> M CauseReg*) val _ = Define ` - ((undefined_CauseReg:unit ->(regstate)state_monad$sequential_state ->(((CauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_CauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . - internal_pick [Mk_CauseReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS (<| CauseReg_CauseReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_CauseReg : mword ty32 -> CauseReg*) + +val _ = Define ` + ((Mk_CauseReg:(32)words$word -> CauseReg) v= + (<| CauseReg_CauseReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`; -(*val _get_CauseReg : CauseReg -> mword ty32*) +(*val _get_CauseReg_bits : CauseReg -> mword ty32*) val _ = Define ` - ((get_CauseReg:CauseReg ->(32)words$word) (Mk_CauseReg (v))= v)`; + ((get_CauseReg_bits:CauseReg ->(32)words$word) v= + ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; -(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) +(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) val _ = Define ` - ((set_CauseReg:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_CauseReg v) in - state_monad$write_regS r_ref r)))`; + ((set_CauseReg_bits:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_bits:CauseReg ->(32)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)))`; -(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) -(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) +(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*) + +(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*) + +(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) (*val _get_CauseReg_BD : CauseReg -> mword ty1*) val _ = Define ` - ((get_CauseReg_BD:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + ((get_CauseReg_BD:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; (*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) val _ = Define ` - ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_CauseReg_CE : CauseReg -> mword ty2*) val _ = Define ` - ((get_CauseReg_CE:CauseReg ->(2)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii) : 2 words$word)))`; + ((get_CauseReg_CE:CauseReg ->(2)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) : 2 words$word)))`; (*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) val _ = Define ` - ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 28 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) val _ = Define ` - ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 28 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)))`; (*val _get_CauseReg_IV : CauseReg -> mword ty1*) val _ = Define ` - ((get_CauseReg_IV:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; + ((get_CauseReg_IV:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; (*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) val _ = Define ` - ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_CauseReg_WP : CauseReg -> mword ty1*) val _ = Define ` - ((get_CauseReg_WP:CauseReg ->(1)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + ((get_CauseReg_WP:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; (*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) val _ = Define ` - ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_CauseReg_IP : CauseReg -> mword ty8*) val _ = Define ` - ((get_CauseReg_IP:CauseReg ->(8)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + ((get_CauseReg_IP:CauseReg ->(8)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; (*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) val _ = Define ` - ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) val _ = Define ` - ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)))`; (*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) val _ = Define ` - ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) (Mk_CauseReg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)))`; + ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) v= + ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)))`; (*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) val _ = Define ` - ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CauseReg) . - let r = ((get_CauseReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 2 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_CauseReg r))))`; + ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) val _ = Define ` - ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) (Mk_CauseReg (v)) x= - (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 2 : int):ii) x : 32 words$word))))`; + ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word))|>)))`; (*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) @@ -362,448 +445,673 @@ val _ = Define ` (*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) val _ = Define ` - ((undefined_TLBEntryLoReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryLoReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_TLBEntryLoReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryLoReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_TLBEntryLoReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*) + +val _ = Define ` + ((Mk_TLBEntryLoReg:(64)words$word -> TLBEntryLoReg) v= + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) +(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*) val _ = Define ` - ((get_TLBEntryLoReg:TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))= v)`; + ((get_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) +(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_TLBEntryLoReg v) in - state_monad$write_regS r_ref r)))`; + ((set_TLBEntryLoReg_bits:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) val _ = Define ` - ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; (*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) val _ = Define ` - ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; (*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) val _ = Define ` - ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))= - ((subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii) : 24 words$word)))`; + ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) : 24 words$word)))`; (*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 6 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) val _ = Define ` - ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)))`; + ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)))`; (*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) val _ = Define ` - ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; (*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) val _ = Define ` - ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) val _ = Define ` - ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryLoReg) . - let r = ((get_TLBEntryLoReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryLoReg r))))`; + ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) val _ = Define ` - ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x= - (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) val _ = Define ` - ((undefined_TLBEntryHiReg:unit ->(regstate)state_monad$sequential_state ->(((TLBEntryHiReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_TLBEntryHiReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryHiReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_TLBEntryHiReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |>))))`; -(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) +(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*) val _ = Define ` - ((get_TLBEntryHiReg:TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))= v)`; + ((Mk_TLBEntryHiReg:(64)words$word -> TLBEntryHiReg) v= + (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) +(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*) val _ = Define ` - ((set_TLBEntryHiReg:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_TLBEntryHiReg v) in - state_monad$write_regS r_ref r)))`; + ((get_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_bits:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) val _ = Define ` - ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; + ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; (*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) val _ = Define ` - ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) val _ = Define ` - ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) val _ = Define ` - ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))= - ((subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))`; + ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))`; (*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) val _ = Define ` - ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 39 : int):ii) (( 13 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) val _ = Define ` - ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) val _ = Define ` - ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; (*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) val _ = Define ` - ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntryHiReg) . - let r = ((get_TLBEntryHiReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntryHiReg r))))`; + ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) val _ = Define ` - ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x= - (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)))`; (*val undefined_ContextReg : unit -> M ContextReg*) val _ = Define ` - ((undefined_ContextReg:unit ->(regstate)state_monad$sequential_state ->(((ContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_ContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((ContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_ContextReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| ContextReg_ContextReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_ContextReg : mword ty64 -> ContextReg*) + +val _ = Define ` + ((Mk_ContextReg:(64)words$word -> ContextReg) v= + (<| ContextReg_ContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _get_ContextReg : ContextReg -> mword ty64*) +(*val _get_ContextReg_bits : ContextReg -> mword ty64*) val _ = Define ` - ((get_ContextReg:ContextReg ->(64)words$word) (Mk_ContextReg (v))= v)`; + ((get_ContextReg_bits:ContextReg ->(64)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) +(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) val _ = Define ` - ((set_ContextReg:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_ContextReg v) in - state_monad$write_regS r_ref r)))`; + ((set_ContextReg_bits:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_bits:ContextReg ->(64)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) val _ = Define ` - ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)))`; + ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)))`; (*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) val _ = Define ` - ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . - let r = ((get_ContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 23 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_ContextReg r))))`; + ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec v (( 40 : int):ii) (( 0 : int):ii) : 41 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) val _ = Define ` - ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) (Mk_ContextReg (v)) x= - (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 23 : int):ii) x : 64 words$word))))`; + ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec x (( 40 : int):ii) (( 0 : int):ii) : 41 words$word)) + : 64 words$word))|>)))`; (*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) val _ = Define ` - ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) (Mk_ContextReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii) : 19 words$word)))`; + ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) : 19 words$word)))`; (*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) val _ = Define ` - ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : ContextReg) . - let r = ((get_ContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_ContextReg r))))`; + ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 18 : int):ii) (( 0 : int):ii) : 19 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) val _ = Define ` - ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) (Mk_ContextReg (v)) x= - (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 18 : int):ii) (( 0 : int):ii) : 19 words$word)) + : 64 words$word))|>)))`; (*val undefined_XContextReg : unit -> M XContextReg*) val _ = Define ` - ((undefined_XContextReg:unit ->(regstate)state_monad$sequential_state ->(((XContextReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_XContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((XContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - internal_pick [Mk_XContextReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| XContextReg_XContextReg_chunk_0 := w__0 |>))))`; -(*val _get_XContextReg : XContextReg -> mword ty64*) +(*val Mk_XContextReg : mword ty64 -> XContextReg*) val _ = Define ` - ((get_XContextReg:XContextReg ->(64)words$word) (Mk_XContextReg (v))= v)`; + ((Mk_XContextReg:(64)words$word -> XContextReg) v= + (<| XContextReg_XContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) +(*val _get_XContextReg_bits : XContextReg -> mword ty64*) val _ = Define ` - ((set_XContextReg:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_XContextReg v) in - state_monad$write_regS r_ref r)))`; + ((get_XContextReg_bits:XContextReg ->(64)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_XContextReg_bits:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_bits:XContextReg ->(64)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) val _ = Define ` - ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) (Mk_XContextReg (v))= - ((subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)))`; + ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)))`; (*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) val _ = Define ` - ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 33 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_XContextReg r))))`; + ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec v (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) val _ = Define ` - ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):ii) (( 33 : int):ii) x : 64 words$word))))`; + ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec x (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)) + : 64 words$word))|>)))`; (*val _get_XContextReg_XR : XContextReg -> mword ty2*) val _ = Define ` - ((get_XContextReg_XR:XContextReg ->(2)words$word) (Mk_XContextReg (v))= ((subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii) : 2 words$word)))`; + ((get_XContextReg_XR:XContextReg ->(2)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) : 2 words$word)))`; (*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) val _ = Define ` - ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 31 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_XContextReg r))))`; + ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) val _ = Define ` - ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):ii) (( 31 : int):ii) x : 64 words$word))))`; + ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) val _ = Define ` - ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) (Mk_XContextReg (v))= - ((subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii) : 27 words$word)))`; + ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) : 27 words$word)))`; (*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) val _ = Define ` - ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : XContextReg) . - let r = ((get_XContextReg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_XContextReg r))))`; + ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) val _ = Define ` - ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) (Mk_XContextReg (v)) x= - (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)))`; val _ = Define ` @@ -835,439 +1143,634 @@ val _ = Define ` (*val undefined_TLBEntry : unit -> M TLBEntry*) val _ = Define ` - ((undefined_TLBEntry:unit ->(regstate)state_monad$sequential_state ->(((TLBEntry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_TLBEntry:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):ii) : ( 117 words$word) M) (\ (w__0 : 117 words$word) . - internal_pick [Mk_TLBEntry w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 : int):ii) : ( 53 words$word) M) (\ (w__0 : 53 words$word) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntry_TLBEntry_chunk_1 := w__0; + TLBEntry_TLBEntry_chunk_0 := w__1 |>)))))`; -(*val _get_TLBEntry : TLBEntry -> mword ty117*) +(*val Mk_TLBEntry : mword ty117 -> TLBEntry*) val _ = Define ` - ((get_TLBEntry:TLBEntry ->(117)words$word) (Mk_TLBEntry (v))= v)`; + ((Mk_TLBEntry:(117)words$word -> TLBEntry) v= + (<| TLBEntry_TLBEntry_chunk_1 := ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) +(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*) val _ = Define ` - ((set_TLBEntry:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_TLBEntry v) in - state_monad$write_regS r_ref r)))`; + ((get_TLBEntry_bits:TLBEntry ->(117)words$word) v= + ((concat_vec ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) : 53 words$word)) + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 117 words$word)))`; + + +(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_bits:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)) + : 53 words$word))|>)) in + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_bits:TLBEntry ->(117)words$word -> TLBEntry) v x= + (let v = + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)) + : 53 words$word))|>)) in + (v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) val _ = Define ` - ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii) : 16 words$word)))`; + ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) : 16 words$word)))`; (*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) val _ = Define ` - ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 116 : int):ii) (( 101 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) + ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):ii) (( 101 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) + ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 53 words$word))|>)))`; (*val _get_TLBEntry_r : TLBEntry -> mword ty2*) val _ = Define ` - ((get_TLBEntry_r:TLBEntry ->(2)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii) : 2 words$word)))`; + ((get_TLBEntry_r:TLBEntry ->(2)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) : 2 words$word)))`; (*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) val _ = Define ` - ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 100 : int):ii) (( 99 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):ii) (( 99 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 53 words$word))|>)))`; (*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) val _ = Define ` - ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii) : 27 words$word)))`; + ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) : 27 words$word)))`; (*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) val _ = Define ` - ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 98 : int):ii) (( 72 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):ii) (( 72 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 53 words$word))|>)))`; (*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) val _ = Define ` - ((get_TLBEntry_asid:TLBEntry ->(8)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii) : 8 words$word)))`; + ((get_TLBEntry_asid:TLBEntry ->(8)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; (*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) val _ = Define ` - ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 71 : int):ii) (( 64 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):ii) (( 64 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 53 words$word))|>)))`; (*val _get_TLBEntry_g : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_g:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_g:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_valid:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_valid:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 62 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):ii) (( 62 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 61 : int):ii) (( 61 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):ii) (( 61 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 60 : int):ii) (( 60 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):ii) (( 60 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) val _ = Define ` - ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii) : 24 words$word)))`; + ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) : 24 words$word)))`; (*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) val _ = Define ` - ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 36 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):ii) (( 36 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) val _ = Define ` - ((get_TLBEntry_c1:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii) : 3 words$word)))`; + ((get_TLBEntry_c1:TLBEntry ->(3)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) : 3 words$word)))`; (*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) val _ = Define ` - ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 33 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):ii) (( 33 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_d1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_d1:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 32 : int):ii) (( 32 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):ii) (( 32 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_v1:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_v1:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 31 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):ii) (( 31 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 30 : int):ii) (( 30 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):ii) (( 30 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 29 : int):ii) (( 29 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):ii) (( 29 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) val _ = Define ` - ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii) : 24 words$word)))`; + ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) : 24 words$word)))`; (*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) val _ = Define ` - ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 28 : int):ii) (( 5 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):ii) (( 5 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) val _ = Define ` - ((get_TLBEntry_c0:TLBEntry ->(3)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)))`; + ((get_TLBEntry_c0:TLBEntry ->(3)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)))`; (*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) val _ = Define ` - ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 2 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):ii) (( 2 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_d0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_d0:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) val _ = Define ` - ((get_TLBEntry_v0:TLBEntry ->(1)words$word) (Mk_TLBEntry (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_TLBEntry_v0:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) val _ = Define ` - ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : TLBEntry) . - let r = ((get_TLBEntry w__0 : 117 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 117 words$word)) in - state_monad$write_regS r_ref (Mk_TLBEntry r))))`; + ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) val _ = Define ` - ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) (Mk_TLBEntry (v)) x= - (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 117 words$word))))`; + ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` @@ -1288,262 +1791,376 @@ val _ = Define ` (*val undefined_StatusReg : unit -> M StatusReg*) val _ = Define ` - ((undefined_StatusReg:unit ->(regstate)state_monad$sequential_state ->(((StatusReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_StatusReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((StatusReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . - internal_pick [Mk_StatusReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS (<| StatusReg_StatusReg_chunk_0 := w__0 |>))))`; + +(*val Mk_StatusReg : mword ty32 -> StatusReg*) + +val _ = Define ` + ((Mk_StatusReg:(32)words$word -> StatusReg) v= + (<| StatusReg_StatusReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`; -(*val _get_StatusReg : StatusReg -> mword ty32*) + +(*val _get_StatusReg_bits : StatusReg -> mword ty32*) val _ = Define ` - ((get_StatusReg:StatusReg ->(32)words$word) (Mk_StatusReg (v))= v)`; + ((get_StatusReg_bits:StatusReg ->(32)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; -(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) +(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) val _ = Define ` - ((set_StatusReg:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_StatusReg v) in - state_monad$write_regS r_ref r)))`; + ((set_StatusReg_bits:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_bits:StatusReg ->(32)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_CU : StatusReg -> mword ty4*) val _ = Define ` - ((get_StatusReg_CU:StatusReg ->(4)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)))`; + ((get_StatusReg_CU:StatusReg ->(4)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)))`; (*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) val _ = Define ` - ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 31 : int):ii) (( 28 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) val _ = Define ` - ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):ii) (( 28 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_BEV : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_BEV:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + ((get_StatusReg_BEV:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_IM : StatusReg -> mword ty8*) val _ = Define ` - ((get_StatusReg_IM:StatusReg ->(8)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + ((get_StatusReg_IM:StatusReg ->(8)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; (*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) val _ = Define ` - ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) val _ = Define ` - ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_KX : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_KX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((get_StatusReg_KX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_SX : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_SX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + ((get_StatusReg_SX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_UX : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_UX:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((get_StatusReg_UX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_KSU : StatusReg -> mword ty2*) val _ = Define ` - ((get_StatusReg_KSU:StatusReg ->(2)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`; + ((get_StatusReg_KSU:StatusReg ->(2)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`; (*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) val _ = Define ` - ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 3 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) val _ = Define ` - ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):ii) (( 3 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_ERL : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_ERL:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((get_StatusReg_ERL:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_EXL : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_EXL:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_StatusReg_EXL:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val _get_StatusReg_IE : StatusReg -> mword ty1*) val _ = Define ` - ((get_StatusReg_IE:StatusReg ->(1)words$word) (Mk_StatusReg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_StatusReg_IE:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) val _ = Define ` - ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : StatusReg) . - let r = ((get_StatusReg w__0 : 32 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 32 words$word)) in - state_monad$write_regS r_ref (Mk_StatusReg r))))`; + ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) val _ = Define ` - ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) (Mk_StatusReg (v)) x= - (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 32 words$word))))`; + ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; (*val execute_branch : mword ty64 -> M unit*) val _ = Define ` - ((execute_branch:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pc= (state_monad$seqS - (state_monad$write_regS delayedPC_ref pc) (state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + ((execute_branch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc= (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPC_ref pc) (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; (*val NotWordVal : mword ty64 -> bool*) @@ -1557,27 +2174,27 @@ val _ = Define ` (*val rGPR : mword ty5 -> M (mword ty64)*) val _ = Define ` - ((rGPR:(5)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx= + ((rGPR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx= (let i = (lem$w2ui idx) in if (((i = (( 0 : int):ii)))) then - state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word) - else state_monad$bindS - (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . - state_monad$returnS ((access_list_dec w__0 i : 64 words$word)))))`; + else sail2_state_monad$bindS + (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . + sail2_state_monad$returnS ((access_list_dec w__0 i : 64 words$word)))))`; (*val wGPR : mword ty5 -> mword ty64 -> M unit*) val _ = Define ` - ((wGPR:(5)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx v= + ((wGPR:(5)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx v= (let i = (lem$w2ui idx) in - if (((i = (( 0 : int):ii)))) then state_monad$returnS () - else state_monad$bindS - (state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . - state_monad$write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list)))))`; + if (((i <> (( 0 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . + sail2_state_monad$write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list))) + else sail2_state_monad$returnS () ))`; @@ -1598,25 +2215,25 @@ val _ = Define ` val _ = Define ` ((Exception_of_num:int -> Exception) arg_= - (let l__81 = arg_ in - if (((l__81 = (( 0 : int):ii)))) then Interrupt - else if (((l__81 = (( 1 : int):ii)))) then TLBMod - else if (((l__81 = (( 2 : int):ii)))) then TLBL - else if (((l__81 = (( 3 : int):ii)))) then TLBS - else if (((l__81 = (( 4 : int):ii)))) then AdEL - else if (((l__81 = (( 5 : int):ii)))) then AdES - else if (((l__81 = (( 6 : int):ii)))) then Sys - else if (((l__81 = (( 7 : int):ii)))) then Bp - else if (((l__81 = (( 8 : int):ii)))) then ResI - else if (((l__81 = (( 9 : int):ii)))) then CpU - else if (((l__81 = (( 10 : int):ii)))) then Ov - else if (((l__81 = (( 11 : int):ii)))) then Tr - else if (((l__81 = (( 12 : int):ii)))) then C2E - else if (((l__81 = (( 13 : int):ii)))) then C2Trap - else if (((l__81 = (( 14 : int):ii)))) then XTLBRefillL - else if (((l__81 = (( 15 : int):ii)))) then XTLBRefillS - else if (((l__81 = (( 16 : int):ii)))) then XTLBInvL - else if (((l__81 = (( 17 : int):ii)))) then XTLBInvS + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Interrupt + else if (((p0_ = (( 1 : int):ii)))) then TLBMod + else if (((p0_ = (( 2 : int):ii)))) then TLBL + else if (((p0_ = (( 3 : int):ii)))) then TLBS + else if (((p0_ = (( 4 : int):ii)))) then AdEL + else if (((p0_ = (( 5 : int):ii)))) then AdES + else if (((p0_ = (( 6 : int):ii)))) then Sys + else if (((p0_ = (( 7 : int):ii)))) then Bp + else if (((p0_ = (( 8 : int):ii)))) then ResI + else if (((p0_ = (( 9 : int):ii)))) then CpU + else if (((p0_ = (( 10 : int):ii)))) then Ov + else if (((p0_ = (( 11 : int):ii)))) then Tr + else if (((p0_ = (( 12 : int):ii)))) then C2E + else if (((p0_ = (( 13 : int):ii)))) then C2Trap + else if (((p0_ = (( 14 : int):ii)))) then XTLBRefillL + else if (((p0_ = (( 15 : int):ii)))) then XTLBRefillS + else if (((p0_ = (( 16 : int):ii)))) then XTLBInvL + else if (((p0_ = (( 17 : int):ii)))) then XTLBInvS else MCheck))`; @@ -1650,8 +2267,8 @@ val _ = Define ` (*val undefined_Exception : unit -> M Exception*) val _ = Define ` - ((undefined_Exception:unit ->(regstate)state_monad$sequential_state ->(((Exception),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = - (internal_pick + ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`; @@ -1687,27 +2304,27 @@ val _ = Define ` (*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) val _ = Define ` - ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex kccBase= (state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . state_monad$bindS (state_monad$seqS - (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then state_monad$bindS - (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . - if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$seqS - (state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii) : 64 words$word))) + ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex kccBase= (sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii) : 64 words$word))) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : 1 words$word))) - else state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . state_monad$seqS - (state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) - else state_monad$returnS () ) - (state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . let vectorOffset = (if ((bits_to_bool ((get_StatusReg_EXL w__4 : 1 words$word)))) then (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . let (vectorBase : 64 bits) = (if ((bits_to_bool ((get_StatusReg_BEV w__5 : 1 words$word)))) then (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; @@ -1718,15 +2335,15 @@ val _ = Define ` (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS + : 64 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref ((sub_vec - ((add_vec vectorBase ((sign_extend1 (( 64 : int):ii) vectorOffset : 64 words$word)) : 64 words$word)) + ((add_vec vectorBase ((mips_sign_extend (( 64 : int):ii) vectorOffset : 64 words$word)) : 64 words$word)) kccBase : 64 words$word))) (set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex : 5 words$word)))) - (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (state_monad$throwS (ISAException () )))))))`; + (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (sail2_state_monad$throwS (ISAException () )))))))`; (*val SignalException : forall 'o. Exception -> M 'o*) @@ -1874,17 +2491,17 @@ val _ = Define ` val _ = Define ` - ((SignalException:Exception ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex= (state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . state_monad$bindS (state_monad$seqS - (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ pc . state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + ((SignalException:Exception ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex= (sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ pc . sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . let pcc = (capRegToCapStruct w__1) in let (success, epcc) = (setCapOffset pcc pc) in - if success then state_monad$write_regS C31_ref ((capStructToCapReg epcc : 257 words$word)) + if success then sail2_state_monad$write_regS EPCC_ref ((capStructToCapReg epcc : 257 words$word)) else - state_monad$write_regS - C31_ref + sail2_state_monad$write_regS + EPCC_ref ((capStructToCapReg ((int_to_cap ((add_vec_int @@ -1892,25 +2509,25 @@ val _ = Define ` : 64 words$word)) ((lem$w2ui pc)) : 64 words$word)))) : 257 words$word)))) - else state_monad$returnS () ) - (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__2 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS nextPCC_ref w__2) - (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__3 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS delayedPCC_ref w__3) - (state_monad$read_regS C29_ref : ( 257 words$word) M)) (\ (w__4 : 257 words$word) . + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS KCC_ref : ( 257 words$word) M)) (\ (w__2 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPCC_ref w__2) + (sail2_state_monad$read_regS KCC_ref : ( 257 words$word) M)) (\ (w__3 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPCC_ref w__3) + (sail2_state_monad$read_regS KCC_ref : ( 257 words$word) M)) (\ (w__4 : 257 words$word) . let base = (getCapBase ((capRegToCapStruct w__4))) in SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) base : 64 words$word))))))))`; val _ = Define ` - ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr= (state_monad$seqS (state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; + ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr= (sail2_state_monad$seqS (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; (*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) val _ = Define ` - ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) ex badAddr= (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0BadVAddr_ref badAddr) + ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr= (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) (set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):ii) (( 13 : int):ii) : 19 words$word)))) (set_XContextReg_XBadVPN2 TLBXContext_ref ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) @@ -1924,9 +2541,9 @@ val _ = Define ` val _ = Define ` ((MemAccessType_of_num:int -> MemAccessType) arg_= - (let l__79 = arg_ in - if (((l__79 = (( 0 : int):ii)))) then Instruction - else if (((l__79 = (( 1 : int):ii)))) then LoadData + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Instruction + else if (((p0_ = (( 1 : int):ii)))) then LoadData else StoreData))`; @@ -1940,16 +2557,16 @@ val _ = Define ` (*val undefined_MemAccessType : unit -> M MemAccessType*) val _ = Define ` - ((undefined_MemAccessType:unit ->(regstate)state_monad$sequential_state ->(((MemAccessType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [Instruction;LoadData;StoreData]))`; + ((undefined_MemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [Instruction;LoadData;StoreData]))`; (*val AccessLevel_of_num : integer -> AccessLevel*) val _ = Define ` ((AccessLevel_of_num:int -> AccessLevel) arg_= - (let l__77 = arg_ in - if (((l__77 = (( 0 : int):ii)))) then User - else if (((l__77 = (( 1 : int):ii)))) then Supervisor + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then User + else if (((p0_ = (( 1 : int):ii)))) then Supervisor else Kernel))`; @@ -1963,7 +2580,7 @@ val _ = Define ` (*val undefined_AccessLevel : unit -> M AccessLevel*) val _ = Define ` - ((undefined_AccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [User;Supervisor;Kernel]))`; + ((undefined_AccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [User;Supervisor;Kernel]))`; (*val int_of_AccessLevel : AccessLevel -> ii*) @@ -1989,18 +2606,18 @@ Returns the current effective access level determined by accessing the relevant (*val getAccessLevel : unit -> M AccessLevel*) val _ = Define ` - ((getAccessLevel:unit ->(regstate)state_monad$sequential_state ->(((AccessLevel),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state$or_boolS - ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . - state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) - ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . - state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) (\ (w__2 : bool) . - if w__2 then state_monad$returnS Kernel - else state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . - let p__133 = ((get_StatusReg_KSU w__3 : 2 words$word)) in - let b__0 = p__133 in - state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel + ((getAccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) (\ (w__2 : bool) . + if w__2 then sail2_state_monad$returnS Kernel + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . + let p__31 = ((get_StatusReg_KSU w__3 : 2 words$word)) in + let b__0 = p__31 in + sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then User else User)))))`; @@ -2009,62 +2626,62 @@ val _ = Define ` (*val checkCP0Access : unit -> M unit*) val _ = Define ` - ((checkCP0Access:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (getAccessLevel () ) (\ accessLevel . state_monad$bindS - (state$and_boolS (state_monad$returnS (((accessLevel <> Kernel)))) - ( state_monad$bindS(state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . - state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 : + ((checkCP0Access:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (getAccessLevel () ) (\ accessLevel . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((accessLevel <> Kernel)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + sail2_state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 : bool) . - if w__1 then state_monad$seqS + if w__1 then sail2_state_monad$seqS (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : 2 words$word)) (SignalException CpU) - else state_monad$returnS () ))))`; + else sail2_state_monad$returnS () ))))`; (*val incrementCP0Count : unit -> M unit*) val _ = Define ` - ((incrementCP0Count:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . state_monad$bindS - (state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__1 : 6 words$word) . state_monad$bindS - (if (((w__0 = w__1))) then state_monad$returnS TLBIndexMax - else state_monad$bindS - (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : 6 words$word) . - state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBRandom_ref w__3) - (state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__4 : 32 words$word) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii) : 32 words$word))) - (state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__5 : 32 bits) . state_monad$bindS - (state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . state_monad$bindS (state_monad$seqS - (if (((w__5 = w__6))) then state_monad$bindS - (state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . + ((incrementCP0Count:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__1 : 6 words$word) . sail2_state_monad$bindS + (if (((w__0 = w__1))) then sail2_state_monad$returnS TLBIndexMax + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : 6 words$word) . + sail2_state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBRandom_ref w__3) + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii) : 32 words$word))) + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__5 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__5 = w__6))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . set_CauseReg_IP CP0Cause_ref ((or_vec ((get_CauseReg_IP w__7 : 8 words$word)) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) : 8 words$word))) - else state_monad$returnS () ) - (state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . - let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in state_monad$bindS - (state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . - let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . - let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . - let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . + let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . + let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . + let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . + let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . let erl = ((get_StatusReg_ERL w__12 : 1 words$word)) in if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))))))))) then SignalException Interrupt - else state_monad$returnS () )))))))))))))`; + else sail2_state_monad$returnS () )))))))))))))`; (*val decode_failure_of_num : integer -> decode_failure*) val _ = Define ` ((decode_failure_of_num:int -> decode_failure) arg_= - (let l__74 = arg_ in - if (((l__74 = (( 0 : int):ii)))) then No_matching_pattern - else if (((l__74 = (( 1 : int):ii)))) then Unsupported_instruction - else if (((l__74 = (( 2 : int):ii)))) then Illegal_instruction + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then No_matching_pattern + else if (((p0_ = (( 1 : int):ii)))) then Unsupported_instruction + else if (((p0_ = (( 2 : int):ii)))) then Illegal_instruction else Internal_error))`; @@ -2078,22 +2695,22 @@ val _ = Define ` (*val undefined_decode_failure : unit -> M decode_failure*) val _ = Define ` - ((undefined_decode_failure:unit ->(regstate)state_monad$sequential_state ->(((decode_failure),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = - (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; + ((undefined_decode_failure:unit ->(regstate)sail2_state_monad$sequential_state ->(((decode_failure),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; (*val Comparison_of_num : integer -> Comparison*) val _ = Define ` ((Comparison_of_num:int -> Comparison) arg_= - (let l__67 = arg_ in - if (((l__67 = (( 0 : int):ii)))) then EQ' - else if (((l__67 = (( 1 : int):ii)))) then NE - else if (((l__67 = (( 2 : int):ii)))) then GE - else if (((l__67 = (( 3 : int):ii)))) then GEU - else if (((l__67 = (( 4 : int):ii)))) then GT' - else if (((l__67 = (( 5 : int):ii)))) then LE - else if (((l__67 = (( 6 : int):ii)))) then LT' + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then EQ' + else if (((p0_ = (( 1 : int):ii)))) then NE + else if (((p0_ = (( 2 : int):ii)))) then GE + else if (((p0_ = (( 3 : int):ii)))) then GEU + else if (((p0_ = (( 4 : int):ii)))) then GT' + else if (((p0_ = (( 5 : int):ii)))) then LE + else if (((p0_ = (( 6 : int):ii)))) then LT' else LTU))`; @@ -2116,7 +2733,7 @@ val _ = Define ` (*val undefined_Comparison : unit -> M Comparison*) val _ = Define ` - ((undefined_Comparison:unit ->(regstate)state_monad$sequential_state ->(((Comparison),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; + ((undefined_Comparison:unit ->(regstate)sail2_state_monad$sequential_state ->(((Comparison),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; (*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) @@ -2139,10 +2756,10 @@ val _ = Define ` val _ = Define ` ((WordType_of_num:int -> WordType) arg_= - (let l__64 = arg_ in - if (((l__64 = (( 0 : int):ii)))) then B - else if (((l__64 = (( 1 : int):ii)))) then H - else if (((l__64 = (( 2 : int):ii)))) then W0 + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then B + else if (((p0_ = (( 1 : int):ii)))) then H + else if (((p0_ = (( 2 : int):ii)))) then W0 else D))`; @@ -2156,7 +2773,31 @@ val _ = Define ` (*val undefined_WordType : unit -> M WordType*) val _ = Define ` - ((undefined_WordType:unit ->(regstate)state_monad$sequential_state ->(((WordType),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [B;H;W0;D]))`; + ((undefined_WordType:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [B;H;W0;D]))`; + + +(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*) + +val _ = Define ` + ((WordTypeUnaligned_of_num:int -> WordTypeUnaligned) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then WL + else if (((p0_ = (( 1 : int):ii)))) then WR + else if (((p0_ = (( 2 : int):ii)))) then DL + else DR))`; + + +(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*) + +val _ = Define ` + ((num_of_WordTypeUnaligned:WordTypeUnaligned -> int) arg_= + ((case arg_ of WL => (( 0 : int):ii) | WR => (( 1 : int):ii) | DL => (( 2 : int):ii) | DR => (( 3 : int):ii) )))`; + + +(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*) + +val _ = Define ` + ((undefined_WordTypeUnaligned:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordTypeUnaligned),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [WL;WR;DL;DR]))`; (*val wordWidthBytes : WordType -> integer*) @@ -2181,15 +2822,15 @@ val _ = Define ` (*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*) val _ = Define ` - ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1= + ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1= (if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))) then state_monad$bindS - (state_monad$read_regS UART_RVALID_ref : ( 1 words$word) M) (\ rvalid . state_monad$bindS (state_monad$seqS - (state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0] : 1 words$word)) - (state_monad$read_regS UART_RDATA_ref : ( 8 words$word) M)) (\ (w__0 : 8 bits) . - state_monad$returnS ((mask p8_times_n___tv + : 64 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS UART_RVALID_ref : ( 1 words$word) M) (\ rvalid . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0] : 1 words$word)) + (sail2_state_monad$read_regS UART_RDATA_ref : ( 8 words$word) M)) (\ (w__0 : 8 bits) . + sail2_state_monad$returnS ((mask p8_times_n___tv ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] @@ -2208,29 +2849,29 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 64 words$word)))) then - state_monad$returnS ((mask p8_times_n___tv + sail2_state_monad$returnS ((mask p8_times_n___tv (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 64 words$word) : 'p8_times_n_ words$word)) - else state_monad$bindS - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__1 . - state_monad$returnS ((reverse_endianness w__1 : 'p8_times_n_ words$word)))))`; + else sail2_state_monad$bindS + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__1 . + sail2_state_monad$returnS ((reverse_endianness w__1 : 'p8_times_n_ words$word)))))`; (*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) val _ = Define ` - ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1= (state_monad$bindS - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__0 . - state_monad$returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; + ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$bindS + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__0 . + sail2_state_monad$returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; (*val init_cp0_state : unit -> M unit*) val _ = Define ` - ((init_cp0_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; + ((init_cp0_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; (*val init_cp2_state : unit -> M unit*) @@ -2413,66 +3054,66 @@ val _ = Define ` let entryASID = ((get_TLBEntry_asid entry : 8 words$word)) in let entryG = ((get_TLBEntry_g entry : 1 words$word)) in let (vpnMask : 27 bits) = - ((not_vec ((zero_extend1 (( 27 : int):ii) entryMask : 27 words$word)) : 27 words$word)) in + ((not_vec ((mips_zero_extend (( 27 : int):ii) entryMask : 27 words$word)) : 27 words$word)) in (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask : 27 words$word)) = ((and_vec entryVPN vpnMask : 27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`; (*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) val _ = Define ` - ((tlbSearch:(64)words$word ->(regstate)state_monad$sequential_state ->(((((6)words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) VAddr= - (state_monad$catch_early_returnS + ((tlbSearch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((6)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) VAddr= + (sail2_state_monad$catch_early_returnS (let r = ((subrange_vec_dec VAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)) in - let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)) in state_monad$bindS - (state_monad$liftRS (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . - let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in state_monad$seqS - (state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () - (\ idx unit_var . state_monad$bindS - (state_monad$liftRS (state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . + let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . + let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in sail2_state_monad$seqS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () + (\ idx unit_var . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . if ((tlbEntryMatch r vpn2 asid w__1)) then - (state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) + (sail2_state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) MR) - else state_monad$returnS () ))) - (state_monad$returnS NONE)))))`; + else sail2_state_monad$returnS () ))) + (sail2_state_monad$returnS NONE)))))`; (*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) val _ = Define ` - ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS (tlbSearch vAddr : ( ( 6 words$word)option) M) (\ idx . (case idx of SOME (idx) => - let i = (lem$w2ui idx) in state_monad$bindS - (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . + let i = (lem$w2ui idx) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in - let b__0 = entryMask in state_monad$bindS + let b__0 = entryMask in sail2_state_monad$bindS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then - state_monad$returnS (( 12 : int):ii) + sail2_state_monad$returnS (( 12 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 14 : int):ii) + sail2_state_monad$returnS (( 14 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 16 : int):ii) + sail2_state_monad$returnS (( 16 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 18 : int):ii) + sail2_state_monad$returnS (( 18 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 20 : int):ii) + sail2_state_monad$returnS (( 20 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 22 : int):ii) + sail2_state_monad$returnS (( 22 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 24 : int):ii) + sail2_state_monad$returnS (( 24 : int):ii) else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 26 : int):ii) + sail2_state_monad$returnS (( 26 : int):ii) else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS (( 28 : int):ii) + sail2_state_monad$returnS (( 28 : int):ii) else undefined_range (( 12 : int):ii) (( 28 : int):ii)) (\ (evenOddBit : int) . let isOdd = (access_vec_dec vAddr evenOddBit) in let ((caps : 1 bits), (capl : 1 bits), (pfn : 24 bits), (d : 1 bits), (v : 1 bits)) = @@ -2495,7 +3136,7 @@ val _ = Define ` (SignalExceptionTLB TLBMod vAddr : (( 64 words$word # bool)) M) else let (res : 64 bits) = - ((zero_extend1 (( 64 : int):ii) + ((mips_zero_extend (( 64 : int):ii) ((subrange_subrange_concat (((((((( 23 : int):ii) - ((((evenOddBit - (( 12 : int):ii))) - (( 1 : int):ii))))) @@ -2506,7 +3147,7 @@ val _ = Define ` ((evenOddBit - (( 1 : int):ii))) (( 0 : int):ii) : 36 words$word)) : 64 words$word)) in - state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) + sail2_state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) | NONE => (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr : (( 64 words$word # bool)) M) @@ -2516,7 +3157,7 @@ val _ = Define ` (*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) val _ = Define ` - ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word#bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS (getAccessLevel () ) (\ currentAccessLevel . let compat32 = (((subrange_vec_dec vAddr (( 61 : int):ii) (( 31 : int):ii) : 31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; @@ -2539,7 +3180,7 @@ val _ = Define ` ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) : 32 words$word)) : 64 words$word))) - else + else if (((b__1 = (vec_of_bits [B0;B0] : 2 words$word)))) then (Kernel, SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -2549,7 +3190,8 @@ val _ = Define ` ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) : 32 words$word)) : 64 words$word))) - | (g__131, g__132) => (Kernel, NONE) + else (case (T, b__1) of (g__29, g__30) => (Kernel, NONE) ) + | (g__29, g__30) => (Kernel, NONE) ) else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then (Kernel, @@ -2561,9 +3203,9 @@ val _ = Define ` if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr : (( 64 words$word # bool)) M) - else state_monad$bindS + else sail2_state_monad$bindS (case addr of - SOME (a) => state_monad$returnS (a, F) + SOME (a) => sail2_state_monad$returnS (a, F) | NONE => if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):ii) (( 0 : int):ii) : 62 words$word)))) > MAX_VA))))) then (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr @@ -2573,29 +3215,29 @@ val _ = Define ` if ((((lem$w2ui pa)) > MAX_PA)) then (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr : (( 64 words$word # bool)) M) - else state_monad$returnS (pa, c)))))`; + else sail2_state_monad$returnS (pa, c)))))`; (*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) val _ = Define ` - ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr accessType= (state_monad$bindS + ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS (TLBTranslateC vAddr accessType : (( 64 words$word # bool)) M) (\ varstup . let (addr, c) = varstup in - state_monad$returnS addr)))`; + sail2_state_monad$returnS addr)))`; (*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*) val _ = Define ` ((CPtrCmpOp_of_num:int -> CPtrCmpOp) arg_= - (let l__57 = arg_ in - if (((l__57 = (( 0 : int):ii)))) then CEQ - else if (((l__57 = (( 1 : int):ii)))) then CNE - else if (((l__57 = (( 2 : int):ii)))) then CLT - else if (((l__57 = (( 3 : int):ii)))) then CLE - else if (((l__57 = (( 4 : int):ii)))) then CLTU - else if (((l__57 = (( 5 : int):ii)))) then CLEU - else if (((l__57 = (( 6 : int):ii)))) then CEXEQ + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CEQ + else if (((p0_ = (( 1 : int):ii)))) then CNE + else if (((p0_ = (( 2 : int):ii)))) then CLT + else if (((p0_ = (( 3 : int):ii)))) then CLE + else if (((p0_ = (( 4 : int):ii)))) then CLTU + else if (((p0_ = (( 5 : int):ii)))) then CLEU + else if (((p0_ = (( 6 : int):ii)))) then CEXEQ else CNEXEQ))`; @@ -2618,17 +3260,17 @@ val _ = Define ` (*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*) val _ = Define ` - ((undefined_CPtrCmpOp:unit ->(regstate)state_monad$sequential_state ->(((CPtrCmpOp),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`; + ((undefined_CPtrCmpOp:unit ->(regstate)sail2_state_monad$sequential_state ->(((CPtrCmpOp),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`; (*val ClearRegSet_of_num : integer -> ClearRegSet*) val _ = Define ` ((ClearRegSet_of_num:int -> ClearRegSet) arg_= - (let l__54 = arg_ in - if (((l__54 = (( 0 : int):ii)))) then GPLo - else if (((l__54 = (( 1 : int):ii)))) then GPHi - else if (((l__54 = (( 2 : int):ii)))) then CLo + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then GPLo + else if (((p0_ = (( 1 : int):ii)))) then GPHi + else if (((p0_ = (( 2 : int):ii)))) then CLo else CHi))`; @@ -2642,41 +3284,41 @@ val _ = Define ` (*val undefined_ClearRegSet : unit -> M ClearRegSet*) val _ = Define ` - ((undefined_ClearRegSet:unit ->(regstate)state_monad$sequential_state ->(((ClearRegSet),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (internal_pick [GPLo;GPHi;CLo;CHi]))`; + ((undefined_ClearRegSet:unit ->(regstate)sail2_state_monad$sequential_state ->(((ClearRegSet),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [GPLo;GPHi;CLo;CHi]))`; (*val undefined_CapStruct : unit -> M CapStruct*) val _ = Define ` - ((undefined_CapStruct:unit ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__0 : bool) . state_monad$bindS + ((undefined_CapStruct:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__0 : bool) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M) (\ (w__1 : 8 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M) (\ (w__1 : 8 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):ii) : ( 24 words$word) M) (\ (w__2 : 24 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 24 : int):ii) : ( 24 words$word) M) (\ (w__2 : 24 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__3 : 16 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__3 : 16 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):ii) : ( 4 words$word) M) (\ (w__4 : 4 bits) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__5 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__6 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__7 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__8 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__9 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__10 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__11 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__12 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__13 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__14 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__15 : bool) . state_monad$bindS - (state_monad$undefined_boolS () ) (\ (w__16 : bool) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 4 : int):ii) : ( 4 words$word) M) (\ (w__4 : 4 bits) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__5 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__6 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__7 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__8 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__9 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__10 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__11 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__12 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__13 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__14 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__15 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (w__16 : bool) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__17 : 64 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__17 : 64 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__18 : 64 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__18 : 64 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__19 : 64 bits) . - state_monad$returnS (<| CapStruct_tag := w__0; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__19 : 64 bits) . + sail2_state_monad$returnS (<| CapStruct_tag := w__0; CapStruct_padding := w__1; CapStruct_otype := w__2; CapStruct_uperms := w__3; @@ -2704,7 +3346,7 @@ val _ = Define ` CapStruct_padding := ((zeros0 (( 8 : int):ii) () : 8 words$word)); CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word)); CapStruct_uperms := ((ones (( 16 : int):ii) () : 16 words$word)); - CapStruct_perm_reserved11_14 := ((ones (( 4 : int):ii) () : 4 words$word)); + CapStruct_perm_reserved11_14 := ((zeros0 (( 4 : int):ii) () : 4 words$word)); CapStruct_access_system_regs := T; CapStruct_permit_unseal := T; CapStruct_permit_ccall := T; @@ -2750,8 +3392,7 @@ val _ = Define ` val _ = Define ` ((setCapPerms:CapStruct ->(31)words$word -> CapStruct) cap perms= ((cap with<| - CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):ii) (( 15 : int):ii) : 16 words$word)); CapStruct_perm_reserved11_14 := - ((subrange_vec_dec perms (( 14 : int):ii) (( 11 : int):ii) : 4 words$word)); CapStruct_access_system_regs := + CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):ii) (( 15 : int):ii) : 16 words$word)); CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec perms (( 10 : int):ii))))); CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec perms (( 9 : int):ii))))); CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec perms (( 8 : int):ii))))); CapStruct_permit_seal := @@ -2826,700 +3467,36 @@ val _ = Define ` (*val undefined_ast : unit -> M ast*) val _ = Define ` - ((undefined_ast:unit ->(regstate)state_monad$sequential_state ->(((ast),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__0 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__1 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__2 : 16 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__3 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__4 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__5 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__6 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__7 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__8 : 16 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__9 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__10 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__11 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__12 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__13 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__14 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__15 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__16 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__17 : 16 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__18 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__19 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__20 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__21 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__22 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__23 : 16 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__24 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__25 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__26 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__27 : 5 words$word) . state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (w__28 : 5 words$word) . state_monad$bindS - (undefined_bitvector - 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(w__223,w__224);ERET () ;CGetPerm (w__225,w__226);CGetType (w__227,w__228);CGetBase (w__229,w__230);CGetLen (w__231,w__232);CGetTag (w__233,w__234);CGetSealed (w__235,w__236);CGetOffset (w__237,w__238);CGetAddr (w__239,w__240);CGetPCC w__241;CGetPCCSetOffset (w__242,w__243);CGetCause w__244;CSetCause w__245;CReadHwr (w__246,w__247);CWriteHwr (w__248,w__249);CAndPerm (w__250,w__251,w__252);CToPtr (w__253,w__254,w__255);CSub (w__256,w__257,w__258);CPtrCmp (w__259,w__260,w__261,w__262);CIncOffset (w__263,w__264,w__265);CIncOffsetImmediate (w__266,w__267,w__268);CSetOffset (w__269,w__270,w__271);CSetBounds (w__272,w__273,w__274);CSetBoundsImmediate (w__275,w__276,w__277);CSetBoundsExact (w__278,w__279,w__280);CClearTag (w__281,w__282);CMOVX (w__283,w__284,w__285,w__286);ClearRegs (w__287,w__288);CFromPtr (w__289,w__290,w__291);CBuildCap (w__292,w__293,w__294);CCopyType (w__295,w__296,w__297);CCheckPerm (w__298,w__299);CCheckType (w__300,w__301);CTestSubset (w__302,w__303,w__304);CSeal (w__305,w__306,w__307);CCSeal (w__308,w__309,w__310);CUnseal (w__311,w__312,w__313);CCall (w__314,w__315,w__316);CReturn () ;CBX (w__317,w__318,w__319);CBZ (w__320,w__321,w__322);CJALR (w__323,w__324,w__325);CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332);CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339);CSC (w__340,w__341,w__342,w__343,w__344,w__345);CLC (w__346,w__347,w__348,w__349,w__350);C2Dump w__351;RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 : int):ii) : ( 26 words$word) M) (\ (u_16 : 26 bits) . + sail2_state$internal_pickS + [DADDIU (u_8,u_7,u_6);DADDU (u_9,u_8,u_7);DADDI (u_8,u_7,u_15);DADD (u_9,u_8,u_7);ADD (u_9,u_8,u_7);ADDI (u_8,u_7,u_15);ADDU (u_9,u_8,u_7);ADDIU (u_8,u_7,u_15);DSUBU (u_9,u_8,u_7);DSUB (u_9,u_8,u_7);SUB0 (u_9,u_8,u_7);SUBU (u_9,u_8,u_7);AND (u_9,u_8,u_7);ANDI (u_8,u_7,u_15);OR (u_9,u_8,u_7);ORI (u_8,u_7,u_15);NOR (u_9,u_8,u_7);XOR (u_9,u_8,u_7);XORI (u_8,u_7,u_15);LUI (u_7,u_6);DSLL (u_9,u_8,u_7);DSLL32 (u_9,u_8,u_7);DSLLV (u_9,u_8,u_7);DSRA (u_9,u_8,u_7);DSRA32 (u_9,u_8,u_7);DSRAV (u_9,u_8,u_7);DSRL (u_9,u_8,u_7);DSRL32 (u_9,u_8,u_7);DSRLV (u_9,u_8,u_7);SLL (u_9,u_8,u_7);SLLV (u_9,u_8,u_7);SRA (u_9,u_8,u_7);SRAV (u_9,u_8,u_7);SRL (u_9,u_8,u_7);SRLV (u_9,u_8,u_7);SLT (u_9,u_8,u_7);SLTI (u_8,u_7,u_15);SLTU (u_9,u_8,u_7);SLTIU (u_8,u_7,u_15);MOVN (u_9,u_8,u_7);MOVZ (u_9,u_8,u_7);MFHI u_7;MFLO u_7;MTHI u_7;MTLO u_7;MUL (u_9,u_8,u_7);MULT (u_8,u_7);MULTU (u_8,u_7);DMULT (u_8,u_7);DMULTU (u_8,u_7);MADD (u_8,u_7);MADDU (u_8,u_7);MSUB (u_8,u_7);MSUBU (u_8,u_7);DIV0 (u_8,u_7);DIVU (u_8,u_7);DDIV (u_8,u_7);DDIVU (u_8,u_7);J u_16;JAL u_16;JR u_7;JALR (u_8,u_7);BEQ (u_8,u_7,u_6,u_5,u_4);BCMPZ (u_7,u_6,u_2,u_5,u_4);SYSCALL u_11;BREAK u_11;WAIT u_11;TRAPREG (u_8,u_7,u_2);TRAPIMM (u_7,u_6,u_2);Load (u_3,u_5,u_4,u_8,u_7,u_6);Store (u_3,u_4,u_8,u_7,u_6);LWL (u_8,u_7,u_15);LWR (u_8,u_7,u_15);SWL (u_8,u_7,u_15);SWR (u_8,u_7,u_15);LDL (u_8,u_7,u_15);LDR (u_8,u_7,u_15);SDL (u_8,u_7,u_15);SDR (u_8,u_7,u_15);CACHE (u_8,u_7,u_15);SYNC u_11;MFC0 (u_8,u_7,u_12,u_4);HCF u_11;MTC0 (u_8,u_7,u_12,u_4);TLBWI u_11;TLBWR u_11;TLBR u_11;TLBP u_11;RDHWR (u_8,u_7);ERET u_11;CGetPerm (u_8,u_7);CGetType (u_8,u_7);CGetBase (u_8,u_7);CGetLen (u_8,u_7);CGetTag (u_8,u_7);CGetSealed (u_8,u_7);CGetOffset (u_8,u_7);CGetAddr (u_8,u_7);CGetPCC u_7;CGetPCCSetOffset (u_8,u_7);CGetCause u_7;CSetCause u_7;CReadHwr (u_8,u_7);CWriteHwr (u_8,u_7);CAndPerm (u_9,u_8,u_7);CToPtr (u_9,u_8,u_7);CSub (u_9,u_8,u_7);CPtrCmp (u_9,u_8,u_7,u_0);CIncOffset (u_9,u_8,u_7);CIncOffsetImmediate (u_8,u_7,u_14);CSetOffset (u_9,u_8,u_7);CSetBounds (u_9,u_8,u_7);CSetBoundsImmediate (u_8,u_7,u_14);CSetBoundsExact (u_9,u_8,u_7);CClearTag (u_8,u_7);CMOVX (u_9,u_8,u_7,u_4);ClearRegs (u_1,u_15);CFromPtr (u_9,u_8,u_7);CBuildCap (u_9,u_8,u_7);CCopyType (u_9,u_8,u_7);CCheckPerm (u_8,u_7);CCheckType (u_8,u_7);CTestSubset (u_9,u_8,u_7);CSeal (u_9,u_8,u_7);CCSeal (u_9,u_8,u_7);CUnseal (u_9,u_8,u_7);CCall (u_8,u_7,u_14);CReturn u_11;CBX (u_7,u_15,u_4);CBZ (u_7,u_15,u_4);CJALR (u_8,u_7,u_4);CLoad (u_9,u_8,u_7,u_13,u_5,u_3,u_4);CStore (u_10,u_9,u_8,u_7,u_13,u_3,u_4);CSC (u_10,u_9,u_8,u_7,u_14,u_4);CLC (u_9,u_8,u_7,u_15,u_4);C2Dump u_7;RI u_11])))))))))))))))))))`; (*val execute : ast -> M unit*) @@ -3527,38 +3504,34 @@ val _ = Define ` (*val decode : mword ty32 -> maybe ast*) val _ = Define ` -((DDC:(5)words$word)= ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))`; - - -val _ = Define ` -((IDC:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; +((IDCNO:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))`; val _ = Define ` -((KR1C:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; +((KR1CNO:(5)words$word)= ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))`; val _ = Define ` -((KR2C:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))`; +((KR2CNO:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))`; val _ = Define ` -((KCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))`; +((KCCNO:(5)words$word)= ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))`; val _ = Define ` -((KDC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))`; +((KDCNO:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))`; val _ = Define ` -((EPCC:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; +((EPCCNO:(5)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))`; val _ = Define ` ((CapRegs:(((regstate),(register_value),(CapReg))register_ref)list)= ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref; C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref;C10_ref;C09_ref;C08_ref; - C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`; + C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;DDC_ref]))`; val _ = Define ` @@ -3571,54 +3544,74 @@ val _ = Define ` (* This function reads a given capability register and returns its contents converted to a CapStruct. +If the argument is zero then the null capability is returned. *) (*val readCapReg : mword ty5 -> M CapStruct*) val _ = Define ` - ((readCapReg:(5)words$word ->(regstate)state_monad$sequential_state ->(((CapStruct),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n= - (let i = (lem$w2ui n) in state_monad$bindS - (state_monad$read_regS ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) + ((readCapReg:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n= + (if (((n = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then sail2_state_monad$returnS null_cap + else + let i = (lem$w2ui n) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) + : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__0)))))`; + + +(* +This is the same as readCapReg except that when the argument is zero the value of DDC is returned +instead of the null capability. This is used for instructions that expect an address, where using +null would always generate an exception. +*) +(*val readCapRegDDC : mword ty5 -> M CapStruct*) + +val _ = Define ` + ((readCapRegDDC:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((CapStruct),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n= + (let i = (lem$w2ui n) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) : ( 257 words$word) M) (\ (w__0 : 257 words$word) . - state_monad$returnS ((capRegToCapStruct w__0)))))`; + sail2_state_monad$returnS ((capRegToCapStruct w__0)))))`; (*val writeCapReg : mword ty5 -> CapStruct -> M unit*) val _ = Define ` - ((writeCapReg:(5)words$word -> CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) n cap= - (let i = (lem$w2ui n) in - state_monad$write_regS - ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) - ((capStructToCapReg cap : 257 words$word))))`; + ((writeCapReg:(5)words$word -> CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) n cap= + (if (((n = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then sail2_state_monad$returnS () + else + let i = (lem$w2ui n) in + sail2_state_monad$write_regS + ((access_list_dec CapRegs i : (regstate, register_value, ( 257 words$word)) register_ref)) + ((capStructToCapReg cap : 257 words$word))))`; (*val CapEx_of_num : integer -> CapEx*) val _ = Define ` ((CapEx_of_num:int -> CapEx) arg_= - (let l__32 = arg_ in - if (((l__32 = (( 0 : int):ii)))) then CapEx_None - else if (((l__32 = (( 1 : int):ii)))) then CapEx_LengthViolation - else if (((l__32 = (( 2 : int):ii)))) then CapEx_TagViolation - else if (((l__32 = (( 3 : int):ii)))) then CapEx_SealViolation - else if (((l__32 = (( 4 : int):ii)))) then CapEx_TypeViolation - else if (((l__32 = (( 5 : int):ii)))) then CapEx_CallTrap - else if (((l__32 = (( 6 : int):ii)))) then CapEx_ReturnTrap - else if (((l__32 = (( 7 : int):ii)))) then CapEx_TSSUnderFlow - else if (((l__32 = (( 8 : int):ii)))) then CapEx_UserDefViolation - else if (((l__32 = (( 9 : int):ii)))) then CapEx_TLBNoStoreCap - else if (((l__32 = (( 10 : int):ii)))) then CapEx_InexactBounds - else if (((l__32 = (( 11 : int):ii)))) then CapEx_GlobalViolation - else if (((l__32 = (( 12 : int):ii)))) then CapEx_PermitExecuteViolation - else if (((l__32 = (( 13 : int):ii)))) then CapEx_PermitLoadViolation - else if (((l__32 = (( 14 : int):ii)))) then CapEx_PermitStoreViolation - else if (((l__32 = (( 15 : int):ii)))) then CapEx_PermitLoadCapViolation - else if (((l__32 = (( 16 : int):ii)))) then CapEx_PermitStoreCapViolation - else if (((l__32 = (( 17 : int):ii)))) then CapEx_PermitStoreLocalCapViolation - else if (((l__32 = (( 18 : int):ii)))) then CapEx_PermitSealViolation - else if (((l__32 = (( 19 : int):ii)))) then CapEx_AccessSystemRegsViolation - else if (((l__32 = (( 20 : int):ii)))) then CapEx_PermitCCallViolation - else if (((l__32 = (( 21 : int):ii)))) then CapEx_AccessCCallIDCViolation + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CapEx_None + else if (((p0_ = (( 1 : int):ii)))) then CapEx_LengthViolation + else if (((p0_ = (( 2 : int):ii)))) then CapEx_TagViolation + else if (((p0_ = (( 3 : int):ii)))) then CapEx_SealViolation + else if (((p0_ = (( 4 : int):ii)))) then CapEx_TypeViolation + else if (((p0_ = (( 5 : int):ii)))) then CapEx_CallTrap + else if (((p0_ = (( 6 : int):ii)))) then CapEx_ReturnTrap + else if (((p0_ = (( 7 : int):ii)))) then CapEx_TSSUnderFlow + else if (((p0_ = (( 8 : int):ii)))) then CapEx_UserDefViolation + else if (((p0_ = (( 9 : int):ii)))) then CapEx_TLBNoStoreCap + else if (((p0_ = (( 10 : int):ii)))) then CapEx_InexactBounds + else if (((p0_ = (( 11 : int):ii)))) then CapEx_GlobalViolation + else if (((p0_ = (( 12 : int):ii)))) then CapEx_PermitExecuteViolation + else if (((p0_ = (( 13 : int):ii)))) then CapEx_PermitLoadViolation + else if (((p0_ = (( 14 : int):ii)))) then CapEx_PermitStoreViolation + else if (((p0_ = (( 15 : int):ii)))) then CapEx_PermitLoadCapViolation + else if (((p0_ = (( 16 : int):ii)))) then CapEx_PermitStoreCapViolation + else if (((p0_ = (( 17 : int):ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((p0_ = (( 18 : int):ii)))) then CapEx_PermitSealViolation + else if (((p0_ = (( 19 : int):ii)))) then CapEx_AccessSystemRegsViolation + else if (((p0_ = (( 20 : int):ii)))) then CapEx_PermitCCallViolation + else if (((p0_ = (( 21 : int):ii)))) then CapEx_AccessCCallIDCViolation else CapEx_PermitUnsealViolation))`; @@ -3656,8 +3649,8 @@ val _ = Define ` (*val undefined_CapEx : unit -> M CapEx*) val _ = Define ` - ((undefined_CapEx:unit ->(regstate)state_monad$sequential_state ->(((CapEx),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = - (internal_pick + ((undefined_CapEx:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapEx),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`; @@ -3695,87 +3688,127 @@ val _ = Define ` (*val undefined_CapCauseReg : unit -> M CapCauseReg*) val _ = Define ` - ((undefined_CapCauseReg:unit ->(regstate)state_monad$sequential_state ->(((CapCauseReg),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS + ((undefined_CapCauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CapCauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__0 : 16 words$word) . - internal_pick [Mk_CapCauseReg w__0])))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (w__0 : 16 words$word) . + sail2_state_monad$returnS (<| CapCauseReg_CapCauseReg_chunk_0 := w__0 |>))))`; + +(*val Mk_CapCauseReg : mword ty16 -> CapCauseReg*) val _ = Define ` - ((get_CapCauseReg:CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))= v)`; + ((Mk_CapCauseReg:(16)words$word -> CapCauseReg) v= + (<| CapCauseReg_CapCauseReg_chunk_0 := ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) |>))`; val _ = Define ` - ((set_CapCauseReg:((regstate),(register_value),(CapCauseReg))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_CapCauseReg v) in - state_monad$write_regS r_ref r)))`; + ((get_CapCauseReg_bits:CapCauseReg ->(16)words$word) v= + ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)))`; val _ = Define ` - ((get_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + ((set_CapCauseReg_bits:((regstate),(register_value),(CapCauseReg))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 16 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_CapCauseReg_ExcCode:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . - let r = ((get_CapCauseReg w__0 : 16 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 8 : int):ii) v : 16 words$word)) in - state_monad$write_regS r_ref (Mk_CapCauseReg r))))`; + ((update_CapCauseReg_bits:CapCauseReg ->(16)words$word -> CapCauseReg) v x= + ((v with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 16 words$word))|>)))`; val _ = Define ` - ((update_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x= - (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):ii) (( 8 : int):ii) x : 16 words$word))))`; + ((get_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word) v= + ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +val _ = Define ` + ((set_CapCauseReg_ExcCode:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 16 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_CapCauseReg_ExcCode:CapCauseReg ->(8)words$word -> CapCauseReg) v x= + ((v with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 16 words$word))|>)))`; (*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) val _ = Define ` - ((get_CapCauseReg_RegNum:CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + ((get_CapCauseReg_RegNum:CapCauseReg ->(8)words$word) v= + ((subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; (*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) val _ = Define ` - ((set_CapCauseReg_RegNum:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : CapCauseReg) . - let r = ((get_CapCauseReg w__0 : 16 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 16 words$word)) in - state_monad$write_regS r_ref (Mk_CapCauseReg r))))`; + ((set_CapCauseReg_RegNum:((regstate),(register_value),(CapCauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec r.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 16 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) val _ = Define ` - ((update_CapCauseReg_RegNum:CapCauseReg ->(8)words$word -> CapCauseReg) (Mk_CapCauseReg (v)) x= - (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 16 words$word))))`; + ((update_CapCauseReg_RegNum:CapCauseReg ->(8)words$word -> CapCauseReg) v x= + ((v with<| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec v.CapCauseReg_CapCauseReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 16 words$word))|>)))`; (*val execute_branch_pcc : CapStruct -> M unit*) val _ = Define ` - ((execute_branch_pcc:CapStruct ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) newPCC= (state_monad$seqS (state_monad$seqS - (state_monad$write_regS + ((execute_branch_pcc:CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) newPCC= (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPC_ref ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapOffset newPCC)) : 64 words$word))) - (state_monad$write_regS delayedPCC_ref ((capStructToCapReg newPCC : 257 words$word)))) - (state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + (sail2_state_monad$write_regS delayedPCC_ref ((capStructToCapReg newPCC : 257 words$word)))) + (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; (*val ERETHook : unit -> M unit*) val _ = Define ` - ((ERETHook:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS C31_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS nextPCC_ref w__0) - (state_monad$read_regS C31_ref : ( 257 words$word) M)) (\ (w__1 : CapReg) . state_monad$write_regS delayedPCC_ref w__1))))`; + ((ERETHook:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS EPCC_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPCC_ref w__0) + (sail2_state_monad$read_regS EPCC_ref : ( 257 words$word) M)) (\ (w__1 : CapReg) . sail2_state_monad$write_regS delayedPCC_ref w__1))))`; (*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) val _ = Define ` - ((raise_c2_exception8:CapEx ->(8)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum= (state_monad$seqS (state_monad$seqS + ((raise_c2_exception8:CapEx ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx regnum= (sail2_state_monad$seqS (sail2_state_monad$seqS (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx : 8 words$word))) (set_CapCauseReg_RegNum CapCause_ref regnum)) (let mipsEx = @@ -3787,9 +3820,9 @@ val _ = Define ` (*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*) val _ = Define ` - ((raise_c2_exception:CapEx ->(5)words$word ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx regnum= + ((raise_c2_exception:CapEx ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx regnum= (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) regnum : 8 words$word)) in - if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then + if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDCNO)))))) then raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 else raise_c2_exception8 capEx reg8))`; @@ -3797,17 +3830,17 @@ val _ = Define ` (*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*) val _ = Define ` - ((raise_c2_exception_noreg:CapEx ->(regstate)state_monad$sequential_state ->(('o,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) capEx= + ((raise_c2_exception_noreg:CapEx ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) capEx= (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)))`; (*val pcc_access_system_regs : unit -> M bool*) val _ = Define ` - ((pcc_access_system_regs:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + ((pcc_access_system_regs:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . let pcc = (capRegToCapStruct w__0) in - state_monad$returnS pcc.CapStruct_access_system_regs)))`; + sail2_state_monad$returnS pcc.CapStruct_access_system_regs)))`; (* @@ -3816,57 +3849,57 @@ The following function should be called before reading or writing any capability (*val register_inaccessible : mword ty5 -> M bool*) val _ = Define ` - ((register_inaccessible:(5)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r= - (state$or_boolS - (state$and_boolS (state_monad$returnS (((r = IDC)))) - ( state_monad$bindS(state_monad$read_regS inCCallDelay_ref : ( 1 words$word) M) (\ (w__0 : 1 words$word) . - state_monad$returnS ((bits_to_bool w__0))))) - (state$and_boolS - (state_monad$returnS ((((((r = KR1C))) \/ ((((((r = KR2C))) \/ ((((((r = KDC))) \/ ((((((r = KCC))) \/ (((r = EPCC)))))))))))))))) - ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__2 : bool) . state_monad$returnS ((~ w__2)))))))`; + ((register_inaccessible:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r= + (sail2_state$or_boolS + (sail2_state$and_boolS (sail2_state_monad$returnS (((r = IDCNO)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS inCCallDelay_ref : ( 1 words$word) M) (\ (w__0 : 1 words$word) . + sail2_state_monad$returnS ((bits_to_bool w__0))))) + (sail2_state$and_boolS + (sail2_state_monad$returnS ((((((r = KR1CNO))) \/ ((((((r = KR2CNO))) \/ ((((((r = KDCNO))) \/ ((((((r = KCCNO))) \/ (((r = EPCCNO)))))))))))))))) + ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))))`; (*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*) val _ = Define ` - ((MEMr_tagged:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr= (state_monad$bindS (state_monad$seqS - (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") - (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . state_monad$bindS - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . - state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; + ((MEMr_tagged:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(256)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . sail2_state_monad$bindS + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . + sail2_state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; (*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) val _ = Define ` - ((MEMr_tagged_reserve:(64)words$word ->(regstate)state_monad$sequential_state ->(((bool#(256)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr= (state_monad$bindS (state_monad$seqS - (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") - (read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . state_monad$bindS - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . - state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; + ((MEMr_tagged_reserve:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool#(256)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr= (sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr)) (\ tag . sail2_state_monad$bindS + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size : ( 256 words$word) M) (\ data . + sail2_state_monad$returnS (tag, (reverse_endianness data : 256 words$word))))))`; (*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) val _ = Define ` - ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data= (state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") - (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) - (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`; + ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr tag data= (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + (MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size)) + (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag)))`; (*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) val _ = Define ` - ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr tag data= (state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") + ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr tag data= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((((lem$w2ui addr)) % cap_size)) = (( 0 : int):ii)))) "") (MEMea_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size)) + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size)) (MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (\ success . state_monad$seqS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data : 256 words$word)))) (\ success . sail2_state_monad$seqS (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else state_monad$returnS () ) (state_monad$returnS success))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag else sail2_state_monad$returnS () ) (sail2_state_monad$returnS success))))`; val _ = Define ` @@ -3878,32 +3911,32 @@ val _ = Define ` (*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) val _ = Define ` - ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data= + ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data= (let ledata = ((reverse_endianness data : 'p8_times_n_ words$word)) in if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))) then state_monad$seqS - (state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) - (state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B1] : 1 words$word)) - else state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + : 64 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) + (sail2_state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B1] : 1 words$word)) + else sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec ((add_vec addr ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((size1 - (( 1 : int):ii))) : 64 words$word)) : 64 words$word)) cap_addr_mask : 64 words$word))))) "") - (MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) - (MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F)))`; + (MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1)) + (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F)))`; (*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) val _ = Define ` - ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr size1 data= (state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec + ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS (((((and_vec addr cap_addr_mask : 64 words$word)) = ((and_vec ((add_vec addr ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((size1 - (( 1 : int):ii))) @@ -3911,53 +3944,93 @@ val _ = Define ` : 64 words$word)) cap_addr_mask : 64 words$word))))) "") (MEMea_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1)) + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1)) (MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))) (\ success . state_monad$seqS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))) (\ success . sail2_state_monad$seqS (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F - else state_monad$returnS () ) - (state_monad$returnS success))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask : 64 words$word)) F + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS success))))`; -(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) +(*val checkDDCPerms : CapStruct -> MemAccessType -> M unit*) val _ = Define ` - ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr accessType width= - (let capno = ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)) in state_monad$bindS - (readCapReg capno) (\ cap . state_monad$seqS (state_monad$seqS - (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno - else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno - else state_monad$returnS () ) + ((checkDDCPerms:CapStruct -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ddc : CapStruct) (accessType : MemAccessType)= (sail2_state_monad$seqS + (if ((~ ddc.CapStruct_tag)) then + raise_c2_exception CapEx_TagViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + else if ddc.CapStruct_sealed then + raise_c2_exception CapEx_SealViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + else sail2_state_monad$returnS () ) (case accessType of - Instruction => - if ((~ cap.CapStruct_permit_execute)) then - raise_c2_exception CapEx_PermitExecuteViolation capno - else state_monad$returnS () + Instruction => sail2_state_monad$assert_expS F "" | LoadData => - if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno - else state_monad$returnS () + if ((~ ddc.CapStruct_permit_load)) then + raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + else sail2_state_monad$returnS () | StoreData => - if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno - else state_monad$returnS () - )) - (let cursor = (getCapCursor cap) in + if ((~ ddc.CapStruct_permit_store)) then + raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + else sail2_state_monad$returnS () + )))`; + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +val _ = Define ` + ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr accessType width= (sail2_state_monad$bindS + (sail2_state_monad$read_regS DDC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + let ddc = (capRegToCapStruct w__0) in sail2_state_monad$seqS + (checkDDCPerms ddc accessType) + (let cursor = (getCapCursor ddc) in let vAddr = (((cursor + ((lem$w2ui addr)))) % ((pow2 (( 64 : int):ii)))) in let size1 = (wordWidthBytes width) in - let base = (getCapBase cap) in - let top = (getCapTop cap) in + let base = (getCapBase ddc) in + let top = (getCapTop ddc) in if ((((vAddr + size1)) > top)) then - (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) M) - else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno : ( 64 words$word) M) - else state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word))))))`; + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + : ( 64 words$word) M) + else if ((vAddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + : ( 64 words$word) M) + else sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word))))))`; + + +(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> M (mword ty64)*) + +val _ = Define ` + ((addrWrapperUnaligned:(64)words$word -> MemAccessType -> WordTypeUnaligned ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr accessType width= (sail2_state_monad$bindS + (sail2_state_monad$read_regS DDC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . + let ddc = (capRegToCapStruct w__0) in sail2_state_monad$seqS + (checkDDCPerms ddc accessType) + (let cursor = (getCapCursor ddc) in + let vAddr = (((cursor + ((lem$w2ui addr)))) % ((pow2 (( 64 : int):ii)))) in + let woffset = (vAddr % (( 4 : int):ii)) in + let doffset = (vAddr % (( 8 : int):ii)) in + let ((waddr : ii), (size1 : ii)) = + ((case width of + WL => (vAddr, (( 4 : int):ii) - woffset) + | WR => (vAddr - woffset, woffset + (( 1 : int):ii)) + | DL => (vAddr, (( 8 : int):ii) - doffset) + | DR => (vAddr - doffset, doffset + (( 1 : int):ii)) + )) in + let base = (getCapBase ddc) in + let top = (getCapTop ddc) in + if ((((waddr + size1)) > top)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + : ( 64 words$word) M) + else if ((waddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + : ( 64 words$word) M) + else sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) vAddr : 64 words$word))))))`; (*val TranslatePC : mword ty64 -> M (mword ty64)*) val _ = Define ` - ((TranslatePC:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr= (state_monad$bindS (state_monad$seqS + ((TranslatePC:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr= (sail2_state_monad$bindS (sail2_state_monad$seqS (incrementCP0Count () ) - (state_monad$read_regS PCC_ref : ( 257 words$word) M)) (\ (w__0 : 257 words$word) . + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M)) (\ (w__0 : 257 words$word) . let pcc = (capRegToCapStruct w__0) in let base = (getCapBase pcc) in let top = (getCapTop pcc) in @@ -3986,75 +4059,79 @@ capability context for processes that use capabilities. (*val checkCP2usable : unit -> M unit*) val _ = Define ` - ((checkCP2usable:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . - if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 2 : int):ii))))))) then state_monad$seqS + ((checkCP2usable:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 2 : int):ii))))))) then sail2_state_monad$seqS (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : 2 words$word)) (SignalException CpU) - else state_monad$returnS () )))`; - - -val _ = Define ` - ((init_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = - (let defaultBits = ((capStructToCapReg default_cap : 257 words$word)) in state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS PCC_ref defaultBits) - (state_monad$write_regS nextPCC_ref defaultBits)) - (state_monad$write_regS delayedPCC_ref defaultBits)) - (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + else sail2_state_monad$returnS () )))`; + + +val _ = Define ` + ((init_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (let defaultBits = ((capStructToCapReg default_cap : 257 words$word)) in + let nullBits = ((capStructToCapReg null_cap : 257 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PCC_ref defaultBits) + (sail2_state_monad$write_regS nextPCC_ref defaultBits)) + (sail2_state_monad$write_regS delayedPCC_ref defaultBits)) + (sail2_state_monad$write_regS DDC_ref defaultBits)) + (sail2_state_monad$write_regS KCC_ref defaultBits)) + (sail2_state_monad$write_regS EPCC_ref defaultBits)) + (sail2_state_monad$write_regS KDC_ref nullBits)) + (sail2_state_monad$write_regS KR1C_ref nullBits)) + (sail2_state_monad$write_regS KR2C_ref nullBits)) + (sail2_state_monad$write_regS CTLSP_ref nullBits)) + (sail2_state_monad$write_regS CTLSU_ref nullBits)) + (sail2_state$foreachS (index_list (( 1 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () (\ i unit_var . let idx = ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) in - writeCapReg idx default_cap))))`; + writeCapReg idx null_cap))))`; val _ = Define ` - ((cp2_next_pc:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS nextPCC_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS PCC_ref w__0) - (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__1 : 1 words$word) . - if ((bits_to_bool w__1)) then state_monad$bindS - (state_monad$read_regS delayedPCC_ref : ( 257 words$word) M) (\ (w__2 : CapReg) . - state_monad$write_regS nextPCC_ref w__2) - else state_monad$write_regS inCCallDelay_ref (vec_of_bits [B0] : 1 words$word)))))`; + ((cp2_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS nextPCC_ref : ( 257 words$word) M) (\ (w__0 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PCC_ref w__0) + (sail2_state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__1 : 1 words$word) . + if ((bits_to_bool w__1)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS delayedPCC_ref : ( 257 words$word) M) (\ (w__2 : CapReg) . + sail2_state_monad$write_regS nextPCC_ref w__2) + else sail2_state_monad$write_regS inCCallDelay_ref (vec_of_bits [B0] : 1 words$word)))))`; (*val capToString : CapStruct -> M string*) val _ = Define ` - ((capToString:CapStruct ->(regstate)state_monad$sequential_state ->(((string),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cap= (state_monad$seqS + ((capToString:CapStruct ->(regstate)sail2_state_monad$sequential_state ->(((string),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cap= (sail2_state_monad$seqS (skip () ) - (state_monad$returnS ((STRCAT " t:" + (sail2_state_monad$returnS ((STRCAT " t:" ((STRCAT (if cap.CapStruct_tag then "1" else "0") ((STRCAT " s:" ((STRCAT (if cap.CapStruct_sealed then "1" else "0") ((STRCAT " perms:" ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((concat_vec (vec_of_bits [B0] : 1 words$word) ((getCapPerms cap : 31 words$word)) : 32 words$word)))) ((STRCAT " type:" - ((STRCAT ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype)) + ((STRCAT ((string_of_bits cap.CapStruct_otype)) ((STRCAT " offset:" ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapOffset cap)) : 64 words$word)))) ((STRCAT " base:" ((STRCAT - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase cap)) : 64 words$word)))) ((STRCAT " length:" - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) @@ -4064,94 +4141,118 @@ val _ = Define ` val _ = Define ` - ((dump_cp2_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . state_monad$bindS + ((dump_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__0 : 257 words$word) . sail2_state_monad$bindS (capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . - let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in - (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () - (\ i unit_var . state_monad$bindS + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP PCC" w__1))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ i unit_var . sail2_state_monad$bindS (readCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word))) (\ (w__2 : - CapStruct) . state_monad$bindS + CapStruct) . sail2_state_monad$bindS (capToString w__2) (\ (w__3 : string) . - state_monad$returnS (let _ = - (prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int + sail2_state_monad$returnS (let _ = + (print_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int instance_Show_Show_Num_integer_dict i)) w__3))))) in - () )))))))))`; + () ))))) + (sail2_state_monad$read_regS DDC_ref : ( 257 words$word) M)) (\ (w__4 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__4))) (\ (w__5 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 00" w__5))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CTLSU_ref : ( 257 words$word) M) (\ (w__6 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__6))) (\ (w__7 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 01" w__7))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CTLSP_ref : ( 257 words$word) M) (\ (w__8 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__8))) (\ (w__9 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 08" w__9))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS KR1C_ref : ( 257 words$word) M) (\ (w__10 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__10))) (\ (w__11 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 22" w__11))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS KR2C_ref : ( 257 words$word) M) (\ (w__12 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__12))) (\ (w__13 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 23" w__13))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS KCC_ref : ( 257 words$word) M) (\ (w__14 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__14))) (\ (w__15 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 29" w__15))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS KDC_ref : ( 257 words$word) M) (\ (w__16 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__16))) (\ (w__17 : string) . + let (_ : unit) = (print_endline ((STRCAT "DEBUG CAP HWREG 30" w__17))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS EPCC_ref : ( 257 words$word) M) (\ (w__18 : 257 words$word) . sail2_state_monad$bindS + (capToString ((capRegToCapStruct w__18))) (\ (w__19 : string) . + sail2_state_monad$returnS ((print_endline ((STRCAT "DEBUG CAP HWREG 31" w__19))))))))))))))))))))))))`; (*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) val _ = Define ` ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign= - (if sign then (sign_extend1 (( 64 : int):ii) memResult : 64 words$word) - else (zero_extend1 (( 64 : int):ii) memResult : 64 words$word)))`; + (if sign then (mips_sign_extend (( 64 : int):ii) memResult : 64 words$word) + else (mips_zero_extend (( 64 : int):ii) memResult : 64 words$word)))`; (*val TLBWriteEntry : mword ty6 -> M unit*) val _ = Define ` - ((TLBWriteEntry:(6)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) idx= (state_monad$bindS - (state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ pagemask . - let b__0 = pagemask in state_monad$seqS + ((TLBWriteEntry:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx= (sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ pagemask . + let b__0 = pagemask in sail2_state_monad$seqS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then - state_monad$returnS () + sail2_state_monad$returnS () else SignalException MCheck) (let i = (lem$w2ui idx) in - let entry = (access_list_dec TLBEntries i) in state_monad$bindS (state_monad$seqS + let entry = (access_list_dec TLBEntries i) in sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_pagemask entry pagemask) - (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 : 2 words$word))) - (state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 : 27 words$word))) - (state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 : 8 words$word))) - (state$and_boolS - ( state_monad$bindS(state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . - state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))))) - ( state_monad$bindS(state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . - state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word)))))))) (\ (w__5 : bool) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word)))))))) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_TLBEntry_g entry ((bool_to_bits w__5 : 1 words$word))) (set_TLBEntry_valid entry ((cast_unit_vec0 B1 : 1 words$word)))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 : 1 words$word))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 : 1 words$word))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 : 24 words$word))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 : 3 words$word))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 : 1 words$word))) - (state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 : 1 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 : 1 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 : 1 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 : 24 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 : 3 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 : 1 words$word))) - (state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 : 1 words$word))))))))))))))))))))))`; @@ -4521,10 +4622,6 @@ val _ = Define ` let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in SOME (BCMPZ (rs,imm,LE,F,T)) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; - B1;B1;B0;B0;B1;B1;B0;B0] - : 32 words$word)))) then - SOME (SYSCALL_THREAD_START () ) else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then SOME (SYSCALL () ) else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then @@ -4701,11 +4798,6 @@ val _ = Define ` let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in SOME (CACHE (base,op,imm)) - else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word)))) then - let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in - let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in - let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in - SOME (PREF (base,op,imm)) else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then SOME (SYNC () ) @@ -5299,13 +5391,19 @@ val _ = Define ` let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in let (rt : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in let (offset : 11 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) in - SOME (CLC (cd,cb,rt,offset,F)) + SOME (CLC (cd,cb,rt,(mips_sign_extend (( 16 : int):ii) offset : 16 words$word),F)) else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 11 words$word))))))) then let (cd : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in let (cb : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] - : 11 words$word),T)) + B0;B0;B0;B0;B0;B0;B0; + B0;B0] + : 16 words$word),T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1] : 6 words$word)))) then + let (cd : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (cb : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : 16 bits) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word),offset,F)) else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 16 words$word))))))) then let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in @@ -5316,16 +5414,16 @@ val _ = Define ` (*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; (*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((xor_vec w__0 w__1 : 64 words$word))))))`; @@ -5333,57 +5431,57 @@ val _ = Define ` (*val execute_WAIT : unit -> M unit*) val _ = Define ` - ((execute_WAIT:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__121= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS nextPC_ref w__0)))`; + ((execute_WAIT:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__19= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS nextPC_ref w__0)))`; (*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) val _ = Define ` - ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt cmp= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rs_val . state_monad$bindS + ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt cmp= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ rt_val . let condition = (compare cmp rs_val rt_val) in if condition then SignalException Tr - else state_monad$returnS () ))))`; + else sail2_state_monad$returnS () ))))`; (*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) val _ = Define ` - ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp= (state_monad$bindS + ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ rs_val . - let (imm_val : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in + let (imm_val : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) in let condition = (compare cmp rs_val imm_val) in if condition then SignalException Tr - else state_monad$returnS () )))`; + else sail2_state_monad$returnS () )))`; (*val execute_TLBWR : unit -> M unit*) val _ = Define ` - ((execute_TLBWR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__125= (state_monad$bindS (state_monad$seqS + ((execute_TLBWR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP0Access () ) - (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; (*val execute_TLBWI : unit -> M unit*) val _ = Define ` - ((execute_TLBWI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__124= (state_monad$bindS (state_monad$seqS + ((execute_TLBWI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP0Access () ) - (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; (*val execute_TLBR : unit -> M unit*) val _ = Define ` - ((execute_TLBR:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__126= (state_monad$bindS (state_monad$seqS + ((execute_TLBR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP0Access () ) - (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . - let i = (lem$w2ui w__0) in state_monad$bindS - (state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . + let i = (lem$w2ui w__0) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) (set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry : 2 words$word)))) (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry : 27 words$word)))) (set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry : 8 words$word)))) @@ -5406,48 +5504,43 @@ val _ = Define ` (*val execute_TLBP : unit -> M unit*) val _ = Define ` - ((execute_TLBP:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__127= (state_monad$bindS (state_monad$seqS + ((execute_TLBP:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__25= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP0Access () ) - (state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . state_monad$bindS - (tlbSearch ((get_TLBEntryHiReg w__0 : 64 words$word)) : ( ( 6 words$word)option) M) (\ result . + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . sail2_state_monad$bindS + (tlbSearch ((get_TLBEntryHiReg_bits w__0 : 64 words$word)) : ( ( 6 words$word)option) M) (\ result . (case result of - SOME (idx) => state_monad$seqS - (state_monad$write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (state_monad$write_regS TLBIndex_ref idx) - | NONE => state_monad$seqS - (state_monad$write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) + SOME (idx) => sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (sail2_state_monad$write_regS TLBIndex_ref idx) + | NONE => sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) )))))`; (*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width conditional base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width conditional base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData width - : ( 64 words$word) M) (\ (vAddr : 64 bits) . state_monad$bindS + : ( 64 words$word) M) (\ (vAddr : 64 bits) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ rt_val . if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr - else state_monad$bindS + else sail2_state_monad$bindS (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . - if conditional then state_monad$bindS - (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . state_monad$bindS + if conditional then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then (case width of - B => - MEMw_conditional_wrapper pAddr (( 1 : int):ii) - ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) - | H => - MEMw_conditional_wrapper pAddr (( 2 : int):ii) - ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) - | W0 => + W0 => MEMw_conditional_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rt_val + | _ => sail2_state_monad$throwS (Error_internal_error () ) ) - else state_monad$returnS F) (\ (success : bool) . - wGPR rt ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else sail2_state_monad$returnS F) (\ (success : bool) . + wGPR rt ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) else (case width of B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) @@ -5457,37 +5550,31 @@ val _ = Define ` )))))))`; -(*val execute_SYSCALL_THREAD_START : unit -> unit*) - -val _ = Define ` - ((execute_SYSCALL_THREAD_START:unit -> unit) g__117= () )`; - - (*val execute_SYSCALL : unit -> M unit*) val _ = Define ` - ((execute_SYSCALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__119= (SignalException Sys))`; + ((execute_SYSCALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__17= (SignalException Sys))`; (*val execute_SYNC : unit -> M unit*) val _ = Define ` - ((execute_SYNC:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__122= (MEM_sync () ))`; + ((execute_SYNC:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__20= (MEM_sync () ))`; (*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData W0 - : ( 64 words$word) M) (\ vAddr . state_monad$bindS + ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData WR + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . let wordAddr = ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) - : 64 words$word)) in state_monad$bindS + : 64 words$word)) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__12 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in if (((b__12 = (vec_of_bits [B0;B0] : 2 words$word)))) then @@ -5502,12 +5589,12 @@ val _ = Define ` (*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData W0 - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData WL + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__8 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in if (((b__8 = (vec_of_bits [B0;B0] : 2 words$word)))) then @@ -5522,15 +5609,15 @@ val _ = Define ` (*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((sub_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 32 words$word)) @@ -5540,99 +5627,101 @@ val _ = Define ` (*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else let (temp33 : 33 bits) = ((sub_vec - ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) : 33 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):ii))))) ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))`; (*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in - if ((NotWordVal temp)) then state_monad$bindS + if ((NotWordVal temp)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) else - let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; (*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ temp . - if ((NotWordVal temp)) then state_monad$bindS + if ((NotWordVal temp)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else - let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; (*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in - if ((NotWordVal temp)) then state_monad$bindS + if ((NotWordVal temp)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) else - let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; (*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ temp . - if ((NotWordVal temp)) then state_monad$bindS + if ((NotWordVal temp)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else - let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; (*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rs_val . state_monad$bindS + ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ rt_val . wGPR rd - ((zero_extend1 (( 64 : int):ii) + ((mips_zero_extend (( 64 : int):ii) (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)) : 64 words$word))))))`; @@ -5641,11 +5730,11 @@ val _ = Define ` (*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ rs_val . - let (immext : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in + let (immext : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) in wGPR rt - ((zero_extend1 (( 64 : int):ii) + ((mips_zero_extend (( 64 : int):ii) (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)) : 64 words$word)))))`; @@ -5654,12 +5743,12 @@ val _ = Define ` (*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= - (let imm_val = (integer_word$w2i imm) in state_monad$bindS + ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= + (let imm_val = (integer_word$w2i imm) in sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let rs_val = (integer_word$w2i w__0) in wGPR rt - ((zero_extend1 (( 64 : int):ii) + ((mips_zero_extend (( 64 : int):ii) (if ((rs_val < imm_val)) then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)) : 64 words$word)))))`; @@ -5668,11 +5757,11 @@ val _ = Define ` (*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd - ((zero_extend1 (( 64 : int):ii) + ((mips_zero_extend (( 64 : int):ii) (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)) : 64 words$word))))))`; @@ -5681,34 +5770,34 @@ val _ = Define ` (*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in state_monad$bindS + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__2 : 64 words$word)))))))`; + let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; (*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . - wGPR rd ((sign_extend1 (( 64 : int):ii) w__1 : 64 words$word))))))`; + let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; (*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData D - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData DR + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let wordAddr = ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) @@ -5735,12 +5824,12 @@ val _ = Define ` (*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) - StoreData D - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData DL + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__32 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in if (((b__32 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then @@ -5763,57 +5852,52 @@ val _ = Define ` (*val execute_RI : unit -> M unit*) val _ = Define ` - ((execute_RI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__130= (SignalException ResI))`; + ((execute_RI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__28= (SignalException ResI))`; (*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd= (state_monad$bindS + ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd= (sail2_state_monad$bindS (getAccessLevel () ) (\ accessLevel . - let (haveAccessLevel : bool) = (accessLevel = Kernel) in state_monad$bindS - (state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . - let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))) in - let rdi = (lem$w2ui rd) in state_monad$bindS - (state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . - let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in state_monad$seqS + let (haveAccessLevel : bool) = (accessLevel = Kernel) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + let (haveCU0 : bool) = + (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))) in + let rdi = (lem$w2ui rd) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in sail2_state_monad$seqS (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI - else state_monad$returnS () ) - (let b__146 = rd in state_monad$bindS + else sail2_state_monad$returnS () ) + (let b__146 = rd in sail2_state_monad$bindS (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then - state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) then - state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then state_monad$bindS - (state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . - state_monad$returnS ((zero_extend1 (( 64 : int):ii) w__2 : 64 words$word))) + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2 : 64 words$word))) else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) then - state_monad$returnS ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then - (state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + (sail2_state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) else (SignalException ResI : ( 64 words$word) M)) (\ (temp : 64 bits) . wGPR rt temp)))))))`; -(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) - -val _ = Define ` - ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm= () )`; - - (*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; (*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((or_vec w__0 w__1 : 64 words$word))))))`; @@ -5821,8 +5905,8 @@ val _ = Define ` (*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((not_vec ((or_vec w__0 w__1 : 64 words$word)) : 64 words$word))))))`; @@ -5830,62 +5914,66 @@ val _ = Define ` (*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (result : 64 bits) . state_monad$seqS - (state_monad$write_regS + : 64 words$word))) (\ (result : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))`; (*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (result : 64 bits) . state_monad$seqS - (state_monad$write_regS + : 64 words$word))) (\ (result : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))`; (*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ rtVal . let (result : 64 bits) = - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)) - : 64 words$word)) in state_monad$bindS + : 64 words$word)) in sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; @@ -5893,933 +5981,496 @@ val _ = Define ` (*val execute_MTLO : mword ty5 -> M unit*) val _ = Define ` - ((execute_MTLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS LO_ref w__0)))`; + ((execute_MTLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS LO_ref w__0)))`; (*val execute_MTHI : mword ty5 -> M unit*) val _ = Define ` - ((execute_MTHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$write_regS HI_ref w__0)))`; + ((execute_MTHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS HI_ref w__0)))`; (*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) val _ = Define ` - ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double= (state_monad$bindS (state_monad$seqS + ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP0Access () ) - (rGPR rt : ( 64 words$word) M)) (\ reg_val . - (case (rd, sel) of - (b__108, b__109) => - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$write_regS TLBIndex_ref - ((mask (( 6 : int): ii) reg_val : 6 words$word)) else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS () else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_TLBEntryLoReg TLBEntryLo0_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_TLBEntryLoReg TLBEntryLo1_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_ContextReg_PTEBase TLBContext_ref - ((subrange_vec_dec reg_val (( 63 : int): ii) (( 23 : int): ii) : 41 words$word)) - else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - state_monad$write_regS CP0UserLocal_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$write_regS TLBPageMask_ref - ((subrange_vec_dec reg_val (( 28 : int): ii) - (( 13 : int): ii) : 16 words$word)) else - if ((((((b__108 = - (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$seqS - (state_monad$write_regS TLBWired_ref - ((mask (( 6 : int): ii) reg_val : 6 words$word))) - (state_monad$write_regS TLBRandom_ref TLBIndexMax) else - if ((((((b__108 = - (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) - /\ - (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$write_regS CP0HWREna_ref - ((concat_vec - ((subrange_vec_dec reg_val (( 31 : int): ii) - (( 29 : int): ii) : 3 words$word)) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0] : 25 words$word) - ((subrange_vec_dec reg_val (( 3 : int): ii) - (( 0 : int): ii) : 4 words$word)) - : 29 words$word)) : 32 words$word)) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS () else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$write_regS CP0Count_ref - ((subrange_vec_dec reg_val (( 31 : int): ii) - (( 0 : int): ii) : 32 words$word)) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$seqS - (state_monad$seqS - (set_TLBEntryHiReg_R TLBEntryHi_ref - ((subrange_vec_dec reg_val - (( 63 : int): ii) (( 62 : int): ii) : 2 words$word))) - (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref - ((subrange_vec_dec reg_val - (( 39 : int): ii) (( 13 : int): ii) : 27 words$word)))) - (set_TLBEntryHiReg_ASID TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 7 : int): ii) - (( 0 : int): ii) : 8 words$word))) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$seqS - (state_monad$write_regS CP0Compare_ref - ((subrange_vec_dec reg_val - (( 31 : int): ii) (( 0 : int): ii) : 32 words$word))) - (state_monad$read_regS CP0Cause_ref)) - (\ (w__0 : CauseReg) . - set_CauseReg_IP CP0Cause_ref - ((and_vec - ((get_CauseReg_IP w__0 : 8 words$word)) - (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) - : 8 words$word))) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (state_monad$seqS - (set_StatusReg_CU - CP0Status_ref - ((subrange_vec_dec - reg_val - (( 31 : int): ii) - (( 28 : int): ii) : 4 words$word))) - (set_StatusReg_BEV - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( - 22 : int): ii))) : 1 words$word)))) - (set_StatusReg_IM - CP0Status_ref - ((subrange_vec_dec - reg_val - (( 15 : int): ii) - (( 8 : int): ii) : 8 words$word)))) - (set_StatusReg_KX - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( 7 : int): ii))) : 1 words$word)))) - (set_StatusReg_SX - CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec - reg_val - (( 6 : int): ii))) : 1 words$word)))) - (set_StatusReg_UX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 5 : int): ii))) : 1 words$word)))) - (set_StatusReg_KSU CP0Status_ref - ((subrange_vec_dec reg_val - (( 4 : int): ii) - (( 3 : int): ii) : 2 words$word)))) - (set_StatusReg_ERL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 2 : int): ii))) : 1 words$word)))) - (set_StatusReg_EXL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 1 : int): ii))) : 1 words$word)))) - (set_StatusReg_IE CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 0 : int): ii))) : 1 words$word))) - else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$seqS - (set_CauseReg_IV CP0Cause_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 23 : int): ii))) : 1 words$word))) - (state_monad$read_regS CP0Cause_ref)) - (\ (w__1 : CauseReg) . - let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in - set_CauseReg_IP CP0Cause_ref - ((concat_vec - ((subrange_vec_dec ip - (( 7 : int): ii) - (( 2 : int): ii) : 6 words$word)) - ((subrange_vec_dec reg_val - (( 9 : int): ii) - (( 8 : int): ii) : 2 words$word)) - : 8 words$word))) else - if ((((((b__108 = - (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$write_regS CP0EPC_ref reg_val - else - if ((((((b__108 = - (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS () else - if ((((((b__108 = - (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) - /\ - (((b__109 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - set_XContextReg_XPTEBase - TLBXContext_ref - ((subrange_vec_dec reg_val - (( 63 : int): ii) - (( 33 : int): ii) : 31 words$word)) - else - state_monad$write_regS CP0ErrorEPC_ref - reg_val - ))))`; + (rGPR rt : ( 64 words$word) M)) (\ reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS TLBIndex_ref ((mask (( 6 : int):ii) reg_val : 6 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS () + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0UserLocal_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 : int):ii) (( 13 : int):ii) : 16 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBWired_ref ((mask (( 6 : int):ii) reg_val : 6 words$word))) + (sail2_state_monad$write_regS TLBRandom_ref TLBIndexMax) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS + CP0HWREna_ref + ((concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 29 : int):ii) : 3 words$word)) + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0] + : 25 words$word) ((subrange_vec_dec reg_val (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 29 words$word)) + : 32 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS () + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0Count_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 62 : int):ii) : 2 words$word))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Compare_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) + (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__0 : CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec ((get_CauseReg_IP w__0 : 8 words$word)) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) + : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 28 : int):ii) : 4 words$word))) + (set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 : int):ii))) : 1 words$word)))) + (set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))) + (set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 : int):ii))) : 1 words$word)))) + (set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 : int):ii))) : 1 words$word)))) + (set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 : int):ii))) : 1 words$word)))) + (set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))) + (set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 : int):ii))) : 1 words$word)))) + (set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 : int):ii))) : 1 words$word)))) + (set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 : int):ii))) : 1 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 : int):ii))) : 1 words$word))) + (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__1 : CauseReg) . + let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec ((subrange_vec_dec ip (( 7 : int):ii) (( 2 : int):ii) : 6 words$word)) + ((subrange_vec_dec reg_val (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)) + : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0EPC_ref reg_val + else if ((((((b__108 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + else if ((((((b__108 = (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_XContextReg_XPTEBase TLBXContext_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)) + else if ((((((b__108 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0ErrorEPC_ref reg_val + else SignalException ResI + ))))`; (*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS - (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS - (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . let result = ((sub_vec ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)) mul_result - : 64 words$word)) in state_monad$seqS - (state_monad$write_regS + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; (*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS - (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS - (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . let result = ((sub_vec ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)) mul_result - : 64 words$word)) in state_monad$seqS - (state_monad$write_regS + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; (*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))) then state_monad$bindS + : 64 words$word)))) then sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else state_monad$returnS () )))`; + else sail2_state_monad$returnS () )))`; (*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS + ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))) then state_monad$bindS + : 64 words$word)))) then sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) - else state_monad$returnS () )))`; + else sail2_state_monad$returnS () )))`; (*val execute_MFLO : mword ty5 -> M unit*) val _ = Define ` - ((execute_MFLO:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS - (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + ((execute_MFLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; (*val execute_MFHI : mword ty5 -> M unit*) val _ = Define ` - ((execute_MFHI:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS - (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + ((execute_MFHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; (*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) val _ = Define ` - ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sel double= (state_monad$bindS (state_monad$seqS - (checkCP0Access () ) - (case (rd, sel) of - (b__48, b__49) => - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS TLBIndex_ref : ( 6 words$word) M) - (\ (w__0 : TLBIndexT) . - let (idx : 31 bits) = ((zero_extend1 (( 31 : int): ii) w__0 : 31 words$word)) in - state_monad$bindS - (state_monad$read_regS TLBProbe_ref : ( 1 words$word) M) - (\ (w__1 : 1 bits) . - state_monad$returnS - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word) - ((concat_vec w__1 idx : 32 words$word)) : 64 words$word)))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) - (\ (w__2 : TLBIndexT) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) w__2 : 64 words$word))) else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS (state_monad$read_regS TLBEntryLo0_ref) - (\ (w__3 : TLBEntryLoReg) . - state_monad$returnS ((get_TLBEntryLoReg w__3 : 64 words$word))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS (state_monad$read_regS TLBEntryLo1_ref) - (\ (w__4 : TLBEntryLoReg) . - state_monad$returnS ((get_TLBEntryLoReg w__4 : 64 words$word))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS (state_monad$read_regS TLBContext_ref) - (\ (w__5 : ContextReg) . - state_monad$returnS ((get_ContextReg w__5 : 64 words$word))) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) - /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then - (state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) - else - if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) - (\ (w__7 : 16 bits) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - ((concat_vec w__7 - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) - : 28 words$word)) : 64 words$word))) else - if ((((((b__48 = - (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS TLBWired_ref : ( 6 words$word) M) - (\ (w__8 : TLBIndexT) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) w__8 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) - (\ (w__9 : 32 bits) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) w__9 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - (state_monad$read_regS CP0BadVAddr_ref : ( 64 words$word) M) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS CP0Count_ref : ( 32 words$word) M) - (\ (w__11 : 32 bits) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) w__11 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS TLBEntryHi_ref) - (\ (w__12 : TLBEntryHiReg) . - state_monad$returnS - ((get_TLBEntryHiReg w__12 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) - (\ (w__13 : 32 bits) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) w__13 : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS CP0Status_ref) - (\ (w__14 : StatusReg) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - ((get_StatusReg w__14 : 32 words$word)) : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS CP0Cause_ref) - (\ (w__15 : CauseReg) . - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - ((get_CauseReg w__15 : 32 words$word)) : 64 words$word))) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - (state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) - else - if ((((((b__48 = - (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B0;B1;B1;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 (( 64 : int): ii) - (vec_of_bits [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 - (( 64 : int): ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 15 words$word) - ((concat_vec - (vec_of_bits - [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B1;B0] : 2 words$word) - ((concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B1] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - : 7 words$word)) - : 10 words$word)) - : 13 words$word)) - : 15 words$word)) - : 16 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B1] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 - (( 64 : int): ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - TLBIndexMax - ((concat_vec - (vec_of_bits - [B0;B0;B0] : 3 words$word) - ((concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0] : 3 words$word) - ( - ( - concat_vec - ( - ( - bool_to_bits - have_cp2 : 1 words$word)) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - : 1 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - : 1 words$word) - ( - vec_of_bits - [B0] - : 1 words$word) - : 2 words$word)) - : 3 words$word)) - : 4 words$word)) - : 5 words$word)) - : 6 words$word)) - : 7 words$word)) - : 10 words$word)) - : 13 words$word)) - : 16 words$word)) - : 19 words$word)) - : 22 words$word)) - : 25 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B1;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 - (( 64 : int): ii) - ((concat_vec - (vec_of_bits [B1] : 1 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0] : 3 words$word) - ((concat_vec - (vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ((concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - ( - concat_vec - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - ( - vec_of_bits - [B0;B0;B0;B0] : 4 words$word) - : 8 words$word)) - : 12 words$word)) - : 16 words$word)) - : 20 words$word)) - : 24 words$word)) - : 28 words$word)) - : 31 words$word)) - : 32 words$word)) - : 64 words$word)) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B1;B1] : 3 words$word))))))) then - state_monad$returnS - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B1;B0;B1] : 3 words$word))))))) then - state_monad$returnS - (vec_of_bits - [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word) else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B0;B1] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - (state_monad$read_regS - CP0LLAddr_ref : ( 64 words$word) M) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B1;B0] : 5 words$word)))) - /\ - (((b__49 = - (vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 - (( 64 : int): ii) - (vec_of_bits - [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - (vec_of_bits - [B1;B0;B0;B1;B1] : 5 words$word)))) - /\ - (((b__49 = - ( - vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - state_monad$returnS - ((zero_extend1 - (( 64 : int): ii) - (vec_of_bits - [B0] : 1 words$word) : 64 words$word)) - else - if ((((((b__48 = - ( - vec_of_bits - [B1;B0;B1;B0;B0] : 5 words$word)))) - /\ - ((( - b__49 = - ( - vec_of_bits - [B0;B0;B0] : 3 words$word))))))) then - state_monad$bindS - (state_monad$read_regS - TLBXContext_ref) - (\ (w__18 : XContextReg) . - state_monad$returnS - ((get_XContextReg - w__18 : 64 words$word))) - else - (state_monad$read_regS - CP0ErrorEPC_ref : ( 64 words$word) M) - )) (\ (result : 64 bits) . + ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . + let (idx : 31 bits) = ((mips_zero_extend (( 31 : int):ii) w__0 : 31 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBProbe_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . + sail2_state_monad$returnS ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) ((concat_vec w__1 idx : 32 words$word)) + : 64 words$word)))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : TLBIndexT) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . + sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__3 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . + sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__4 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBContext_ref) (\ (w__5 : ContextReg) . + sail2_state_monad$returnS ((get_ContextReg_bits w__5 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ (w__7 : 16 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 28 words$word)) + : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__8 : TLBIndexT) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__8 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__9 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__9 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0BadVAddr_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__11 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__11 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryHi_ref) (\ (w__12 : TLBEntryHiReg) . + sail2_state_monad$returnS ((get_TLBEntryHiReg_bits w__12 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__13 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__14 : StatusReg) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_StatusReg_bits w__14 : 32 words$word)) : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__15 : CauseReg) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_CauseReg_bits w__15 : 32 words$word)) : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0ConfigK0_ref : ( 3 words$word) M) (\ (w__17 : 3 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 15 words$word) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec (vec_of_bits [B1;B0] : 2 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + w__17 + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 15 words$word)) + : 16 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec TLBIndexMax + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec + ((bool_to_bits have_cp2 : 1 words$word)) + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] + : 1 words$word) + ((concat_vec + (vec_of_bits [B0] + : 1 words$word) + (vec_of_bits [B0] + : 1 words$word) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 16 words$word)) + : 19 words$word)) + : 22 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + : 8 words$word)) + : 12 words$word)) + : 16 words$word)) + : 20 words$word)) + : 24 words$word)) + : 28 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0LLAddr_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBXContext_ref) (\ (w__19 : XContextReg) . + sail2_state_monad$returnS ((get_XContextReg_bits w__19 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) + else (SignalException ResI : ( 64 words$word) M) + )) (\ (result : 64 bits) . wGPR rt (if double then result else - (sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + (mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)))))`; (*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS - (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS - (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . let result = ((add_vec mul_result ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)) - : 64 words$word)) in state_monad$seqS - (state_monad$write_regS + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; (*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) else - state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - : 64 words$word))) (\ (mul_result : 64 bits) . state_monad$bindS - (state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$bindS - (state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . let result = ((add_vec mul_result ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)) - : 64 words$word)) in state_monad$seqS - (state_monad$write_regS + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) : 64 words$word))) - (state_monad$write_regS + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS LO_ref - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; (*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) width sign linked base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - width + ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width sign linked base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + LoadData width : ( 64 words$word) M) (\ (vAddr : 64 bits) . if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr - else state_monad$bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS - (if linked then state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + else sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (case width of - B => state_monad$bindS - (MEMr_reserve_wrapper pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__1 : 8 words$word) . - state_monad$returnS ((extendLoad w__1 sign : 64 words$word))) - | H => state_monad$bindS - (MEMr_reserve_wrapper pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__2 : 16 words$word) . - state_monad$returnS ((extendLoad w__2 sign : 64 words$word))) - | W0 => state_monad$bindS - (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__3 : 32 words$word) . - state_monad$returnS ((extendLoad w__3 sign : 64 words$word))) - | D => state_monad$bindS - (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__4 : 64 words$word) . - state_monad$returnS ((extendLoad w__4 sign : 64 words$word))) + W0 => sail2_state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$returnS ((extendLoad w__1 sign : 64 words$word))) + | D => sail2_state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + sail2_state_monad$returnS ((extendLoad w__2 sign : 64 words$word))) + | _ => sail2_state_monad$throwS (Error_internal_error () ) ) else (case width of - B => state_monad$bindS - (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__6 : 8 words$word) . - state_monad$returnS ((extendLoad w__6 sign : 64 words$word))) - | H => state_monad$bindS - (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__7 : 16 words$word) . - state_monad$returnS ((extendLoad w__7 sign : 64 words$word))) - | W0 => state_monad$bindS - (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__8 : 32 words$word) . - state_monad$returnS ((extendLoad w__8 sign : 64 words$word))) - | D => state_monad$bindS - (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__9 : 64 words$word) . - state_monad$returnS ((extendLoad w__9 sign : 64 words$word))) + B => sail2_state_monad$bindS + (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__5 : 8 words$word) . + sail2_state_monad$returnS ((extendLoad w__5 sign : 64 words$word))) + | H => sail2_state_monad$bindS + (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__6 : 16 words$word) . + sail2_state_monad$returnS ((extendLoad w__6 sign : 64 words$word))) + | W0 => sail2_state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__7 : 32 words$word) . + sail2_state_monad$returnS ((extendLoad w__7 sign : 64 words$word))) + | D => sail2_state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__8 : 64 words$word) . + sail2_state_monad$returnS ((extendLoad w__8 sign : 64 words$word))) )) (\ (memResult : 64 bits) . wGPR rt memResult))))))`; @@ -6827,17 +6478,17 @@ val _ = Define ` (*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - W0 - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData WR + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (MEMr_wrapper (( 32 : int):ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) : 64 words$word)) (( 4 : int):ii) - : ( 32 words$word) M) (\ mem_val . state_monad$bindS + : ( 32 words$word) M) (\ mem_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__4 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in let (result : 32 bits) = @@ -6854,23 +6505,23 @@ val _ = Define ` ((subrange_vec_dec mem_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) : 32 words$word) else mem_val) in - wGPR rt ((sign_extend1 (( 64 : int):ii) result : 64 words$word)))))))))`; + wGPR rt ((mips_sign_extend (( 64 : int):ii) result : 64 words$word)))))))))`; (*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - W0 - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData WL + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (MEMr_wrapper (( 32 : int):ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) (vec_of_bits [B0;B0] : 2 words$word) : 64 words$word)) (( 4 : int):ii) - : ( 32 words$word) M) (\ mem_val . state_monad$bindS + : ( 32 words$word) M) (\ mem_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__0 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in let (result : 32 bits) = @@ -6887,15 +6538,15 @@ val _ = Define ` (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) : 32 words$word)) in - wGPR rt ((sign_extend1 (( 64 : int):ii) result : 64 words$word)))))))))`; + wGPR rt ((mips_sign_extend (( 64 : int):ii) result : 64 words$word)))))))))`; (*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt imm= + ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt imm= (wGPR rt - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word) : 32 words$word)) @@ -6905,17 +6556,17 @@ val _ = Define ` (*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - D - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData DR + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (MEMr_wrapper (( 64 : int):ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) (vec_of_bits [B0;B0;B0] : 3 words$word) : 64 words$word)) (( 8 : int):ii) - : ( 64 words$word) M) (\ mem_val . state_monad$bindS + : ( 64 words$word) M) (\ mem_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__24 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in wGPR rt @@ -6953,17 +6604,17 @@ val _ = Define ` (*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base rt offset= (state_monad$bindS - (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData - D - : ( 64 words$word) M) (\ vAddr . state_monad$bindS - (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData DL + : ( 64 words$word) M) (\ vAddr . sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (MEMr_wrapper (( 64 : int):ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) (vec_of_bits [B0;B0;B0] : 3 words$word) : 64 words$word)) (( 8 : int):ii) - : ( 64 words$word) M) (\ mem_val . state_monad$bindS + : ( 64 words$word) M) (\ mem_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ reg_val . let b__16 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in wGPR rt @@ -7001,38 +6652,38 @@ val _ = Define ` (*val execute_JR : mword ty5 -> M unit*) val _ = Define ` - ((execute_JR:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs= (state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; + ((execute_JR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; (*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS (state_monad$seqS + ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS (execute_branch w__0) - (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . wGPR rd ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; (*val execute_JAL : mword ty26 -> M unit*) val _ = Define ` - ((execute_JAL:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS + ((execute_JAL:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS (execute_branch ((concat_vec ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) : 64 words$word))) - (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; (*val execute_J : mword ty26 -> M unit*) val _ = Define ` - ((execute_J:(26)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) offset= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + ((execute_J:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . execute_branch ((concat_vec ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) @@ -7040,39 +6691,33 @@ val _ = Define ` : 64 words$word)))))`; -(*val execute_ImplementationDefinedStopFetching : unit -> unit*) - -val _ = Define ` - ((execute_ImplementationDefinedStopFetching:unit -> unit) g__118= () )`; - - (*val execute_HCF : unit -> unit*) val _ = Define ` - ((execute_HCF:unit -> unit) g__123= () )`; + ((execute_HCF:unit -> unit) g__21= () )`; (*val execute_ERET : unit -> M unit*) val _ = Define ` - ((execute_ERET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__128= (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS + ((execute_ERET:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__26= (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (checkCP0Access () ) (ERETHook () )) - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word))) - (state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . - if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then state_monad$bindS - (state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . state_monad$seqS - (state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) - else state_monad$bindS - (state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$seqS - (state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word))))))`; + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word))) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word))))))`; (*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((sub_vec w__0 w__1 : 64 words$word))))))`; @@ -7080,11 +6725,12 @@ val _ = Define ` (*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let (temp65 : 65 bits) = - ((sub_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1 : 65 words$word)) + ((sub_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) w__1 : 65 words$word)) : 65 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):ii))))) ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):ii))))))) then @@ -7095,67 +6741,67 @@ val _ = Define ` (*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in state_monad$bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; (*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ temp . - let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in state_monad$bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; (*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; (*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in state_monad$bindS + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in sail2_state_monad$bindS (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; (*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS + ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ temp . - let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in state_monad$bindS + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in sail2_state_monad$bindS (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; (*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ temp . state_monad$bindS + ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; (*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) : ( 64 words$word) M) (\ (w__2 : + ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) : ( 64 words$word) M) (\ (w__2 : 64 words$word) . wGPR rd w__2)))))`; @@ -7163,9 +6809,9 @@ val _ = Define ` (*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) + ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; @@ -7173,134 +6819,134 @@ val _ = Define ` (*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt rd sa= (state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; + ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; (*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let result = ((mult_vec w__0 w__1 : 128 words$word)) in state_monad$seqS - (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) - (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + let result = ((mult_vec w__0 w__1 : 128 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; (*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let result = ((mults_vec w__0 w__1 : 128 words$word)) in state_monad$seqS - (state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) - (state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + let result = ((mults_vec w__0 w__1 : 128 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; (*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))))))))) then state_monad$bindS + : 64 words$word)))))))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . - state_monad$returnS (w__0, w__1))) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (w__0, w__1))) else let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in let qi = (hardware_quot si ti) in let ri = (hardware_mod si ti) in - state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), - (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS - (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r : 64 words$word))) - (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q : 64 words$word))))))))`; + sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q : 64 words$word))))))))`; (*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ rsVal . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rtVal . state_monad$bindS + ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))))))))) then state_monad$bindS + : 64 words$word)))))))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . - state_monad$returnS (w__0, w__1))) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (w__0, w__1))) else let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in let qi = (hardware_quot si ti) in let ri = (si - ((ti * qi))) in - state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), - (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS - (state_monad$write_regS HI_ref ((sign_extend1 (( 64 : int):ii) r : 64 words$word))) - (state_monad$write_regS LO_ref ((sign_extend1 (( 64 : int):ii) q : 64 words$word))))))))`; + sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q : 64 words$word))))))))`; (*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rsVal = (lem$w2ui w__0) in state_monad$bindS + let rsVal = (lem$w2ui w__0) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let rtVal = (lem$w2ui w__1) in state_monad$bindS - (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS + let rtVal = (lem$w2ui w__1) in sail2_state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . - state_monad$returnS (w__2, w__3))) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (w__2, w__3))) else let qi = (hardware_quot rsVal rtVal) in let ri = (hardware_mod rsVal rtVal) in - state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), - (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS - (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`; + sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`; (*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt= (state_monad$bindS + ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rsVal = (integer_word$w2i w__0) in state_monad$bindS + let rsVal = (integer_word$w2i w__0) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let rtVal = (integer_word$w2i w__1) in state_monad$bindS - (if (((rtVal = (( 0 : int):ii)))) then state_monad$bindS + let rtVal = (integer_word$w2i w__1) in sail2_state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . - state_monad$returnS (w__2, w__3))) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (w__2, w__3))) else let qi = (hardware_quot rsVal rtVal) in let ri = (rsVal - ((qi * rtVal))) in - state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), - (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in state_monad$seqS - (state_monad$write_regS LO_ref q) (state_monad$write_regS HI_ref r))))))`; + sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`; (*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((add_vec w__0 w__1 : 64 words$word))))))`; @@ -7308,18 +6954,19 @@ val _ = Define ` (*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; (*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let (sum65 : 65 bits) = - ((add_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) imm : 65 words$word)) + ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) imm : 65 words$word)) : 65 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then @@ -7330,11 +6977,12 @@ val _ = Define ` (*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let (sum65 : 65 bits) = - ((add_vec ((sign_extend1 (( 65 : int):ii) w__0 : 65 words$word)) ((sign_extend1 (( 65 : int):ii) w__1 : 65 words$word)) + ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) w__1 : 65 words$word)) : 65 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then @@ -7345,20 +6993,20 @@ val _ = Define ` (*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*) val _ = Define ` - ((execute_ClearRegs:ClearRegSet ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) regset m= (state_monad$seqS (state_monad$seqS + ((execute_ClearRegs:ClearRegSet ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) regset m= (sail2_state_monad$seqS (sail2_state_monad$seqS (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () - else state_monad$returnS () ) + else sail2_state_monad$returnS () ) (if (((regset = CHi))) then - (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () (\ i unit_var . let r = - ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) : 5 words$word)) in state_monad$bindS - (state$and_boolS (state_monad$returnS ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r))) (\ (w__1 : + ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) : 5 words$word)) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r))) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r - else state_monad$returnS () ))) - else state_monad$returnS () )) - (state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () + else sail2_state_monad$returnS () ))) + else sail2_state_monad$returnS () )) + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 15 : int):ii) (( 1 : int):ii)) () (\ i unit_var . if ((bit_to_bool ((access_vec_dec m i)))) then (case regset of @@ -7370,72 +7018,80 @@ val _ = Define ` ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) : 5 words$word)) ((zeros0 (( 64 : int):ii) () : 64 words$word)) | CLo => - writeCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) null_cap + if (((i = (( 0 : int):ii)))) then sail2_state_monad$write_regS DDC_ref ((capStructToCapReg null_cap : 257 words$word)) + else + writeCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) i : 5 words$word)) + null_cap | CHi => writeCapReg ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) ((i + (( 16 : int):ii))) : 5 words$word)) null_cap ) - else state_monad$returnS () ))))`; + else sail2_state_monad$returnS () ))))`; (*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb sel= (state_monad$seqS + ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb sel= (sail2_state_monad$seqS (checkCP2usable () ) - (let l__24 = (lem$w2ui sel) in state_monad$bindS - (if (((l__24 = (( 0 : int):ii)))) then state_monad$returnS (F, F) - else if (((l__24 = (( 1 : int):ii)))) then state_monad$returnS (F, F) - else if (((l__24 = (( 8 : int):ii)))) then state_monad$returnS (F, T) - else if (((l__24 = (( 22 : int):ii)))) then state_monad$returnS (T, F) - else if (((l__24 = (( 23 : int):ii)))) then state_monad$returnS (T, F) - else if (((l__24 = (( 29 : int):ii)))) then state_monad$returnS (T, T) - else if (((l__24 = (( 30 : int):ii)))) then state_monad$returnS (T, T) - else if (((l__24 = (( 31 : int):ii)))) then state_monad$returnS (T, T) - else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS + (let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS + (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS (F, F) + else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$returnS (F, F) + else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$returnS (F, T) + else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$returnS (T, F) + else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$returnS (T, F) + else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$returnS (T, T) + else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$returnS (T, T) + else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in sail2_state_monad$bindS (register_inaccessible cb) (\ (w__8 : bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS - (state$and_boolS (state_monad$returnS needAccessSys) - ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . state_monad$returnS ((~ w__9))))) (\ (w__10 : + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS needAccessSys) + ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) (\ (w__10 : bool) . if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel - else state_monad$bindS - (state$and_boolS (state_monad$returnS needSup) - ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . - state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS needSup) + ( sail2_state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . + sail2_state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . - let l__16 = (lem$w2ui sel) in - if (((l__16 = (( 0 : int):ii)))) then writeCapReg DDC capVal - else if (((l__16 = (( 1 : int):ii)))) then - state_monad$write_regS CTLSU_ref ((capStructToCapReg capVal : 257 words$word)) - else if (((l__16 = (( 8 : int):ii)))) then - state_monad$write_regS CTLSP_ref ((capStructToCapReg capVal : 257 words$word)) - else if (((l__16 = (( 22 : int):ii)))) then writeCapReg KR1C capVal - else if (((l__16 = (( 23 : int):ii)))) then writeCapReg KR2C capVal - else if (((l__16 = (( 29 : int):ii)))) then writeCapReg KCC capVal - else if (((l__16 = (( 30 : int):ii)))) then writeCapReg KDC capVal - else if (((l__16 = (( 31 : int):ii)))) then writeCapReg EPCC capVal - else state_monad$assert_expS F "should be unreachable code"))))))))`; + let p0_ = (lem$w2ui sel) in + if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$write_regS DDC_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 1 : int):ii)))) then + sail2_state_monad$write_regS CTLSU_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 8 : int):ii)))) then + sail2_state_monad$write_regS CTLSP_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 22 : int):ii)))) then + sail2_state_monad$write_regS KR1C_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 23 : int):ii)))) then + sail2_state_monad$write_regS KR2C_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 29 : int):ii)))) then + sail2_state_monad$write_regS KCC_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 30 : int):ii)))) then + sail2_state_monad$write_regS KDC_ref ((capStructToCapReg capVal : 257 words$word)) + else if (((p0_ = (( 31 : int):ii)))) then + sail2_state_monad$write_regS EPCC_ref ((capStructToCapReg capVal : 257 words$word)) + else sail2_state_monad$assert_expS F "should be unreachable code"))))))))`; (*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . - let ct_cursor = (getCapCursor ct_val) in state_monad$bindS + let ct_cursor = (getCapCursor ct_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cs) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -7460,13 +7116,13 @@ val _ = Define ` (*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg ct)) (\ ct_val . state_monad$bindS - (readCapReg cb) (\ cb_val . state_monad$bindS + (readCapRegDDC ct)) (\ ct_val . sail2_state_monad$bindS + (readCapReg cb) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct @@ -7489,19 +7145,19 @@ val _ = Define ` (*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let ct_top = (getCapTop ct_val) in let ct_base = (getCapBase ct_val) in let ct_perms = ((getCapPerms ct_val : 31 words$word)) in let cb_top = (getCapTop cb_val) in let cb_base = (getCapBase cb_val) in - let cb_perms = ((getCapPerms cb_val : 31 words$word)) in state_monad$bindS + let cb_perms = ((getCapPerms cb_val : 31 words$word)) in sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else @@ -7513,19 +7169,19 @@ val _ = Define ` else if (((((and_vec ct_perms cb_perms : 31 words$word)) <> ct_perms))) then (vec_of_bits [B0] : 1 words$word) else (vec_of_bits [B1] : 1 words$word)) in - wGPR rd ((zero_extend1 (( 64 : int):ii) result : 64 words$word))))))))`; + wGPR rd ((mips_zero_extend (( 64 : int):ii) result : 64 words$word))))))))`; (*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct= (state_monad$bindS (state_monad$seqS + ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg ct)) (\ ct_val . state_monad$bindS - (readCapReg cb) (\ cb_val . state_monad$bindS + (readCapReg ct)) (\ ct_val . sail2_state_monad$bindS + (readCapReg cb) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else @@ -7538,9 +7194,9 @@ val _ = Define ` (*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*) val _ = Define ` - ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional= (state_monad$bindS (state_monad$seqS + ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> WordType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs cb rt rd offset width conditional= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7549,7 +7205,7 @@ val _ = Define ` raise_c2_exception CapEx_PermitStoreViolation cb else let size1 = (wordWidthBytes width) in - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset)))))) @@ -7560,11 +7216,11 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 - else state_monad$bindS - (TLBTranslate vAddr64 StoreData : ( 64 words$word) M) (\ pAddr . state_monad$bindS + else sail2_state_monad$bindS + (TLBTranslate vAddr64 StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ rs_val . - if conditional then state_monad$bindS - (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__2 : 1 bits) . state_monad$bindS + if conditional then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__2 : 1 bits) . sail2_state_monad$bindS (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):ii))))) then (case width of B => @@ -7578,8 +7234,8 @@ val _ = Define ` ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rs_val ) - else state_monad$returnS F) (\ (success : bool) . - wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else sail2_state_monad$returnS F) (\ (success : bool) . + wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) else (case width of B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rs_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) @@ -7592,13 +7248,13 @@ val _ = Define ` (*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then @@ -7618,12 +7274,12 @@ val _ = Define ` (*val execute_CSetCause : mword ty5 -> M unit*) val _ = Define ` - ((execute_CSetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rt= (state_monad$bindS (state_monad$seqS + ((execute_CSetCause:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (pcc_access_system_regs () )) (\ (w__0 : bool) . if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation - else state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$seqS + else sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . sail2_state_monad$seqS (set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):ii) (( 8 : int):ii) : 8 words$word))) (set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))))))`; @@ -7631,17 +7287,17 @@ val _ = Define ` (*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) val _ = Define ` - ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm= (state_monad$bindS (state_monad$seqS + ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb imm= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (readCapReg cb)) (\ cb_val . let immU = (lem$w2ui imm) in let cursor = (getCapCursor cb_val) in let base = (getCapBase cb_val) in let top = (getCapTop cb_val) in - let newTop = (cursor + immU) in state_monad$bindS + let newTop = (cursor + immU) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7660,18 +7316,18 @@ val _ = Define ` (*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let rt_val = (lem$w2ui w__0) in let cursor = (getCapCursor cb_val) in let base = (getCapBase cb_val) in let top = (getCapTop cb_val) in - let newTop = (cursor + rt_val) in state_monad$bindS + let newTop = (cursor + rt_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7690,18 +7346,18 @@ val _ = Define ` (*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let rt_val = (lem$w2ui w__0) in let cursor = (getCapCursor cb_val) in let base = (getCapBase cb_val) in let top = (getCapTop cb_val) in - let newTop = (cursor + rt_val) in state_monad$bindS + let newTop = (cursor + rt_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7720,19 +7376,19 @@ val _ = Define ` (*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let ct_cursor = (getCapCursor ct_val) in let ct_top = (getCapTop ct_val) in - let ct_base = (getCapBase ct_val) in state_monad$bindS + let ct_base = (getCapBase ct_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cs) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -7755,13 +7411,13 @@ val _ = Define ` (*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) val _ = Define ` - ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional= (state_monad$bindS (state_monad$seqS + ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb rt rd offset conditional= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS - (readCapReg cb) (\ cb_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS + (readCapRegDDC cb) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cs) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7773,7 +7429,7 @@ val _ = Define ` else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then raise_c2_exception CapEx_PermitStoreLocalCapViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset)))))) @@ -7784,68 +7440,80 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdES vAddr64 - else state_monad$bindS + else sail2_state_monad$bindS (TLBTranslateC vAddr64 StoreData : (( 64 words$word # bool)) M) (\ varstup . let (pAddr, noStoreCap) = varstup in if (((cs_val.CapStruct_tag /\ noStoreCap))) then raise_c2_exception CapEx_TLBNoStoreCap cs - else if conditional then state_monad$bindS - (state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__3 : 1 bits) . state_monad$bindS + else if conditional then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__3 : 1 bits) . sail2_state_monad$bindS (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):ii))))) then MEMw_tagged_conditional pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val : 256 words$word)) - else state_monad$returnS F) (\ success . - wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else sail2_state_monad$returnS F) (\ success . + wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val : 256 words$word))))))))))`; (*val execute_CReturn : unit -> M unit*) val _ = Define ` - ((execute_CReturn:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__129= (state_monad$seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`; + ((execute_CReturn:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__27= (sail2_state_monad$seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`; (*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CReadHwr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd sel= (state_monad$seqS + ((execute_CReadHwr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd sel= (sail2_state_monad$seqS (checkCP2usable () ) - (let l__8 = (lem$w2ui sel) in state_monad$bindS - (if (((l__8 = (( 0 : int):ii)))) then state_monad$returnS (F, F) - else if (((l__8 = (( 1 : int):ii)))) then state_monad$returnS (F, F) - else if (((l__8 = (( 8 : int):ii)))) then state_monad$returnS (F, T) - else if (((l__8 = (( 22 : int):ii)))) then state_monad$returnS (T, F) - else if (((l__8 = (( 23 : int):ii)))) then state_monad$returnS (T, F) - else if (((l__8 = (( 29 : int):ii)))) then state_monad$returnS (T, T) - else if (((l__8 = (( 30 : int):ii)))) then state_monad$returnS (T, T) - else if (((l__8 = (( 31 : int):ii)))) then state_monad$returnS (T, T) - else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in state_monad$bindS + (let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS + (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS (F, F) + else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$returnS (F, F) + else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$returnS (F, T) + else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$returnS (T, F) + else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$returnS (T, F) + else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$returnS (T, T) + else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$returnS (T, T) + else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$returnS (T, T) + else SignalException ResI) (\ varstup . let ((needSup : bool), (needAccessSys : bool)) = varstup in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__8 : bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS - (state$and_boolS (state_monad$returnS needAccessSys) - ( state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . state_monad$returnS ((~ w__9))))) (\ (w__10 : + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS needAccessSys) + ( sail2_state_monad$bindS(pcc_access_system_regs () ) (\ (w__9 : bool) . sail2_state_monad$returnS ((~ w__9))))) (\ (w__10 : bool) . if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel - else state_monad$bindS - (state$and_boolS (state_monad$returnS needSup) - ( state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . - state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . + else sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS needSup) + ( sail2_state_monad$bindS(getAccessLevel () ) (\ (w__11 : AccessLevel) . + sail2_state_monad$returnS ((~ ((grantsAccess w__11 Supervisor))))))) (\ (w__12 : bool) . if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel else - let l__0 = (lem$w2ui sel) in state_monad$bindS - (if (((l__0 = (( 0 : int):ii)))) then readCapReg DDC - else if (((l__0 = (( 1 : int):ii)))) then state_monad$bindS - (state_monad$read_regS CTLSU_ref : ( 257 words$word) M) (\ (w__14 : 257 words$word) . - state_monad$returnS ((capRegToCapStruct w__14))) - else if (((l__0 = (( 8 : int):ii)))) then state_monad$bindS - (state_monad$read_regS CTLSP_ref : ( 257 words$word) M) (\ (w__15 : 257 words$word) . - state_monad$returnS ((capRegToCapStruct w__15))) - else if (((l__0 = (( 22 : int):ii)))) then readCapReg KR1C - else if (((l__0 = (( 23 : int):ii)))) then readCapReg KR2C - else if (((l__0 = (( 29 : int):ii)))) then readCapReg KCC - else if (((l__0 = (( 30 : int):ii)))) then readCapReg KDC - else if (((l__0 = (( 31 : int):ii)))) then readCapReg EPCC - else state_monad$seqS (state_monad$assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal : + let p0_ = (lem$w2ui sel) in sail2_state_monad$bindS + (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS DDC_ref : ( 257 words$word) M) (\ (w__13 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__13))) + else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CTLSU_ref : ( 257 words$word) M) (\ (w__14 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__14))) + else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CTLSP_ref : ( 257 words$word) M) (\ (w__15 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__15))) + else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS KR1C_ref : ( 257 words$word) M) (\ (w__16 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__16))) + else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS KR2C_ref : ( 257 words$word) M) (\ (w__17 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__17))) + else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS KCC_ref : ( 257 words$word) M) (\ (w__18 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__18))) + else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS KDC_ref : ( 257 words$word) M) (\ (w__19 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__19))) + else if (((p0_ = (( 31 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS EPCC_ref : ( 257 words$word) M) (\ (w__20 : 257 words$word) . + sail2_state_monad$returnS ((capRegToCapStruct w__20))) + else sail2_state_monad$seqS (sail2_state_monad$assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal : CapStruct) . writeCapReg cd capVal))))))))`; @@ -7853,15 +7521,15 @@ val _ = Define ` (*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*) val _ = Define ` - ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> CPtrCmpOp ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb ct op= (state_monad$bindS (state_monad$seqS + ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> CPtrCmpOp ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb ct op= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct - else state_monad$bindS - (readCapReg cb) (\ cb_val . state_monad$bindS + else sail2_state_monad$bindS + (readCapReg cb) (\ cb_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let equal = F in let ltu = F in @@ -7895,39 +7563,39 @@ val _ = Define ` | CEXEQ => (cb_val = ct_val) | CNEXEQ => (cb_val <> ct_val) )) in - wGPR rd ((zero_extend1 (( 64 : int):ii) ((bool_to_bits cmp : 1 words$word)) : 64 words$word))))))))`; + wGPR rd ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits cmp : 1 words$word)) : 64 words$word))))))))`; (*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) val _ = Define ` - ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt ismovn= (state_monad$bindS (state_monad$seqS + ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt ismovn= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cd)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . if ((bits_to_bool ((xor_vec ((bool_to_bits (((w__2 = ((zeros0 (( 64 : int):ii) () : 64 words$word))))) : 1 words$word)) ((bool_to_bits ismovn : 1 words$word)) - : 1 words$word)))) then state_monad$bindS + : 1 words$word)))) then sail2_state_monad$bindS (readCapReg cb) (\ (w__3 : CapStruct) . writeCapReg cd w__3) - else state_monad$returnS () )))))`; + else sail2_state_monad$returnS () )))))`; (*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*) val _ = Define ` - ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> WordType -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6= + ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> WordType -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6= (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in (case merge_var of - (rd, cb, rt, offset, signext, B, linked) => state_monad$bindS (state_monad$seqS + (rd, cb, rt, offset, signext, B, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7935,7 +7603,7 @@ val _ = Define ` else if ((~ cb_val.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):ii) * ((integer_word$w2i offset)))))) @@ -7946,20 +7614,20 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 - else state_monad$bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS - (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + else sail2_state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (MEMr_reserve_wrapper pAddr (( 1 : int):ii) : ( 8 words$word) M)) (\ (w__2 : 8 words$word) . - state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) - else state_monad$bindS + sail2_state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else sail2_state_monad$bindS (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__3 : 8 words$word) . - state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + sail2_state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, D, linked) => state_monad$bindS (state_monad$seqS + | (rd, cb, rt, offset, signext, D, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7967,7 +7635,7 @@ val _ = Define ` else if ((~ cb_val.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):ii) * ((integer_word$w2i offset)))))) @@ -7978,20 +7646,20 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 - else state_monad$bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS - (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + else sail2_state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M)) (\ (w__2 : 64 words$word) . - state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) - else state_monad$bindS + sail2_state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else sail2_state_monad$bindS (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 words$word) . - state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + sail2_state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, H, linked) => state_monad$bindS (state_monad$seqS + | (rd, cb, rt, offset, signext, H, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -7999,7 +7667,7 @@ val _ = Define ` else if ((~ cb_val.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):ii) * ((integer_word$w2i offset)))))) @@ -8010,20 +7678,20 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 - else state_monad$bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS - (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + else sail2_state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (MEMr_reserve_wrapper pAddr (( 2 : int):ii) : ( 16 words$word) M)) (\ (w__2 : 16 words$word) . - state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) - else state_monad$bindS + sail2_state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else sail2_state_monad$bindS (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__3 : 16 words$word) . - state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + sail2_state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . wGPR rd memResult))))) - | (rd, cb, rt, offset, signext, W0, linked) => state_monad$bindS (state_monad$seqS + | (rd, cb, rt, offset, signext, W0, linked) => sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cb) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8031,7 +7699,7 @@ val _ = Define ` else if ((~ cb_val.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):ii) * ((integer_word$w2i offset)))))) @@ -8042,29 +7710,29 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64 - else state_monad$bindS - (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . state_monad$bindS - (if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + else sail2_state_monad$bindS + (TLBTranslate vAddr64 LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M)) (\ (w__2 : 32 words$word) . - state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) - else state_monad$bindS + sail2_state_monad$returnS ((extendLoad w__2 signext : 64 words$word))) + else sail2_state_monad$bindS (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__3 : 32 words$word) . - state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . + sail2_state_monad$returnS ((extendLoad w__3 signext : 64 words$word)))) (\ (memResult : 64 bits) . wGPR rd memResult))))) )))`; -(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty16 -> bool -> M unit*) val _ = Define ` - ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt offset linked= (state_monad$bindS (state_monad$seqS + ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt offset linked= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8072,7 +7740,7 @@ val _ = Define ` else if ((~ cb_val.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation cb else - let cursor = (getCapCursor cb_val) in state_monad$bindS + let cursor = (getCapCursor cb_val) in sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__2 : 64 words$word) . let vAddr = (((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):ii) * ((integer_word$w2i offset)))))) @@ -8083,22 +7751,22 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if (((((vAddr % cap_size)) <> (( 0 : int):ii)))) then SignalExceptionBadAddr AdEL vAddr64 - else state_monad$bindS + else sail2_state_monad$bindS (TLBTranslateC vAddr64 LoadData : (( 64 words$word # bool)) M) (\ varstup . let (pAddr, suppressTag) = varstup in let cd = (lem$w2ui cd) in - if linked then state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) - (state_monad$write_regS CP0LLAddr_ref pAddr)) + if linked then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) (MEMr_tagged_reserve pAddr : ((bool # 256 words$word)) M)) (\ varstup . let (tag, mem) = varstup in - state_monad$write_regS + sail2_state_monad$write_regS ((access_list_dec CapRegs cd : (regstate, register_value, ( 257 words$word)) register_ref)) ((memBitsToCapBits (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) mem : 257 words$word))) - else state_monad$bindS + else sail2_state_monad$bindS (MEMr_tagged pAddr : ((bool # 256 words$word)) M) (\ varstup . let (tag, mem) = varstup in - state_monad$write_regS + sail2_state_monad$write_regS ((access_list_dec CapRegs cd : (regstate, register_value, ( 257 words$word)) register_ref)) ((memBitsToCapBits (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag)))))))) @@ -8109,15 +7777,15 @@ val _ = Define ` (*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*) val _ = Define ` - ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb link= (state_monad$bindS (state_monad$seqS + ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb link= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (readCapReg cb)) (\ cb_val . let cb_ptr = (getCapCursor cb_val) in let cb_top = (getCapTop cb_val) in - let cb_base = (getCapBase cb_val) in state_monad$bindS - (state$and_boolS (state_monad$returnS link) ((register_inaccessible cd))) (\ (w__1 : bool) . + let cb_base = (getCapBase cb_val) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS link) ((register_inaccessible cd))) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8128,28 +7796,28 @@ val _ = Define ` else if ((((cb_ptr + (( 4 : int):ii))) > cb_top)) then raise_c2_exception CapEx_LengthViolation cb else if (((((cb_ptr % (( 4 : int):ii))) <> (( 0 : int):ii)))) then SignalException AdEL - else state_monad$seqS - (if link then state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__3 : 257 words$word) . - let pcc = (capRegToCapStruct w__3) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + else sail2_state_monad$seqS + (if link then sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__3 : 257 words$word) . + let pcc = (capRegToCapStruct w__3) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 : int):ii) : 64 words$word))) in if success then writeCapReg cd linkCap - else state_monad$assert_expS F "")) - else state_monad$returnS () ) + else sail2_state_monad$assert_expS F "")) + else sail2_state_monad$returnS () ) (execute_branch_pcc cb_val))))))`; (*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) val _ = Define ` - ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb imm= (state_monad$bindS (state_monad$seqS + ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb imm= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (readCapReg cb)) (\ cb_val . - let (imm64 : 64 bits) = ((sign_extend1 (( 64 : int):ii) imm : 64 words$word)) in state_monad$bindS + let (imm64 : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then @@ -8169,13 +7837,13 @@ val _ = Define ` (*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -8199,65 +7867,67 @@ val _ = Define ` (*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetType:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd - (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):ii) capVal.CapStruct_otype : 64 words$word) + (if capVal.CapStruct_sealed then + (mips_zero_extend (( 64 : int):ii) capVal.CapStruct_otype : 64 words$word) else (replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):ii) : 64 words$word))))))`; (*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetTag:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd - ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_tag : 1 words$word)) : 64 words$word))))))`; + ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_tag : 1 words$word)) : 64 words$word))))))`; (*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetSealed:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetSealed:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd - ((zero_extend1 (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_sealed : 1 words$word)) : 64 words$word))))))`; + ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits capVal.CapStruct_sealed : 1 words$word)) + : 64 words$word))))))`; (*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetPerm:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . - wGPR rd ((zero_extend1 (( 64 : int):ii) ((getCapPerms capVal : 31 words$word)) : 64 words$word))))))`; + wGPR rd ((mips_zero_extend (( 64 : int):ii) ((getCapPerms capVal : 31 words$word)) : 64 words$word))))))`; (*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd rs= (state_monad$bindS (state_monad$seqS + ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd rs= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cd)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . - let pcc = (capRegToCapStruct w__1) in state_monad$bindS + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ rs_val . let (success, newPCC) = (setCapOffset pcc rs_val) in if success then writeCapReg cd newPCC @@ -8267,26 +7937,26 @@ val _ = Define ` (*val execute_CGetPCC : mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetPCC:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd= (state_monad$bindS (state_monad$seqS + ((execute_CGetPCC:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cd)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS - (state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . - let pcc = (capRegToCapStruct w__1) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . - let (success, pcc2) = (setCapOffset pcc w__2) in state_monad$seqS - (state_monad$assert_expS success "") (writeCapReg cd pcc2))))))`; + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PCC_ref : ( 257 words$word) M) (\ (w__1 : 257 words$word) . + let pcc = (capRegToCapStruct w__1) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + let (success, pcc2) = (setCapOffset pcc w__2) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS success "") (writeCapReg cd pcc2))))))`; (*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetOffset:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetOffset:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapOffset capVal)) : 64 words$word))))))`; @@ -8295,11 +7965,11 @@ val _ = Define ` (*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetLen:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetLen:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . let len65 = (getCapLength capVal) in wGPR rd @@ -8312,23 +7982,23 @@ val _ = Define ` (*val execute_CGetCause : mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetCause:(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd= (state_monad$bindS (state_monad$seqS + ((execute_CGetCause:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (pcc_access_system_regs () )) (\ (w__0 : bool) . if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation - else state_monad$bindS - (state_monad$read_regS CapCause_ref) (\ (w__1 : CapCauseReg) . - wGPR rd ((zero_extend1 (( 64 : int):ii) ((get_CapCauseReg w__1 : 16 words$word)) : 64 words$word))))))`; + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CapCause_ref) (\ (w__1 : CapCauseReg) . + wGPR rd ((mips_zero_extend (( 64 : int):ii) ((get_CapCauseReg_bits w__1 : 16 words$word)) : 64 words$word))))))`; (*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetBase:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetBase:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapBase capVal)) : 64 words$word))))))`; @@ -8337,11 +8007,11 @@ val _ = Define ` (*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CGetAddr:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd cb= (state_monad$bindS (state_monad$seqS + ((execute_CGetAddr:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ capVal . wGPR rd ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((getCapCursor capVal)) : 64 words$word))))))`; @@ -8350,16 +8020,20 @@ val _ = Define ` (*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then writeCapReg cd null_cap + else if (((rt_val = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then + writeCapReg cd null_cap else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb else @@ -8377,19 +8051,19 @@ val _ = Define ` (*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct= (state_monad$bindS (state_monad$seqS + ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let cb_base = (getCapBase cb_val) in let cb_top = (getCapTop cb_val) in - let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in state_monad$bindS + let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8401,8 +8075,8 @@ val _ = Define ` let (success, cap) = (setCapOffset cb_val ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((ct_otype - cb_base)) - : 64 words$word))) in state_monad$seqS - (state_monad$assert_expS success "") (writeCapReg cd cap) + : 64 words$word))) in sail2_state_monad$seqS + (sail2_state_monad$assert_expS success "") (writeCapReg cd cap) else writeCapReg cd ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 : 1 words$word)) (( 64 : int):ii) : 64 words$word)))))))))))`; @@ -8411,26 +8085,26 @@ val _ = Define ` (*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CClearTag:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb= (state_monad$bindS (state_monad$seqS + ((execute_CClearTag:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cd)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS (readCapReg cb) (\ cb_val . writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`; + else sail2_state_monad$bindS (readCapReg cb) (\ cb_val . writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`; (*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CCheckType:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb= (state_monad$bindS (state_monad$seqS + ((execute_CCheckType:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS - (readCapReg cb) (\ cb_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS + (readCapReg cb) (\ cb_val . sail2_state_monad$bindS (register_inaccessible cs) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -8439,38 +8113,38 @@ val _ = Define ` else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then raise_c2_exception CapEx_TypeViolation cs - else state_monad$returnS () ))))))`; + else sail2_state_monad$returnS () ))))))`; (*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs rt= (state_monad$bindS (state_monad$seqS + ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (readCapReg cs)) (\ cs_val . let (cs_perms : 64 bits) = - ((zero_extend1 (( 64 : int):ii) ((getCapPerms cs_val : 31 words$word)) : 64 words$word)) in state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_perms . state_monad$bindS + ((mips_zero_extend (( 64 : int):ii) ((getCapPerms cs_val : 31 words$word)) : 64 words$word)) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_perms . sail2_state_monad$bindS (register_inaccessible cs) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs else if (((((and_vec cs_perms rt_perms : 64 words$word)) <> rt_perms))) then raise_c2_exception CapEx_UserDefViolation cs - else state_monad$returnS () )))))`; + else sail2_state_monad$returnS () )))))`; (*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) val _ = Define ` - ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cs cb b__151= - (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) then state_monad$bindS (state_monad$seqS + ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cs cb b__151= + (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS (readCapReg cb) (\ cb_val . - let cs_cursor = (getCapCursor cs_val) in state_monad$bindS + let cs_cursor = (getCapCursor cs_val) in sail2_state_monad$bindS (register_inaccessible cs) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -8488,14 +8162,14 @@ val _ = Define ` else if ((cs_cursor >= ((getCapTop cs_val)))) then raise_c2_exception CapEx_LengthViolation cs else raise_c2_exception CapEx_CallTrap cs)))) - else state_monad$bindS (state_monad$seqS + else sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS (readCapReg cb) (\ cb_val . - let cs_cursor = (getCapCursor cs_val) in state_monad$bindS + let cs_cursor = (getCapCursor cs_val) in sail2_state_monad$bindS (register_inaccessible cs) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__3 : bool) . if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -8516,12 +8190,12 @@ val _ = Define ` raise_c2_exception CapEx_LengthViolation cs else if ((cs_cursor >= ((getCapTop cs_val)))) then raise_c2_exception CapEx_LengthViolation cs - else state_monad$seqS (state_monad$seqS + else sail2_state_monad$seqS (sail2_state_monad$seqS (execute_branch_pcc (cs_val with<| CapStruct_sealed := F; CapStruct_otype := ((zeros0 (( 24 : int):ii) () : 24 words$word))|>)) - (state_monad$write_regS inCCallDelay_ref (vec_of_bits [B1] : 1 words$word))) - (state_monad$write_regS + (sail2_state_monad$write_regS inCCallDelay_ref (vec_of_bits [B1] : 1 words$word))) + (sail2_state_monad$write_regS C26_ref ((capStructToCapReg (cb_val with<| @@ -8532,19 +8206,19 @@ val _ = Define ` (*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cs ct= (state_monad$bindS (state_monad$seqS + ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cs ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cs)) (\ cs_val . state_monad$bindS + (readCapReg cs)) (\ cs_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let ct_cursor = (getCapCursor ct_val) in let ct_top = (getCapTop ct_val) in - let ct_base = (getCapBase ct_val) in state_monad$bindS + let ct_base = (getCapBase ct_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cs) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs @@ -8569,9 +8243,9 @@ val _ = Define ` (*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb ct= (state_monad$bindS (state_monad$seqS + ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb ct= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS + (readCapRegDDC cb)) (\ cb_val . sail2_state_monad$bindS (readCapReg ct) (\ ct_val . let cb_base = (getCapBase cb_val) in let ct_base = (getCapBase ct_val) in @@ -8579,13 +8253,13 @@ val _ = Define ` let ct_top = (getCapTop ct_val) in let cb_perms = ((getCapPerms cb_val : 31 words$word)) in let ct_perms = ((getCapPerms ct_val : 31 words$word)) in - let ct_offset = (getCapOffset ct_val) in state_monad$bindS + let ct_offset = (getCapOffset ct_val) in sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible ct) (\ (w__2 : bool) . if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8603,18 +8277,18 @@ val _ = Define ` let (representable, cd2) = (setCapOffset cd1 ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ct_offset : 64 words$word))) in - let cd3 = (setCapPerms cd2 ct_perms) in state_monad$seqS (state_monad$seqS - (state_monad$assert_expS exact "") (state_monad$assert_expS representable "")) (writeCapReg cd cd3))))))))`; + let cd3 = (setCapPerms cd2 ct_perms) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$assert_expS exact "") (sail2_state_monad$assert_expS representable "")) (writeCapReg cd cd3))))))))`; (*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*) val _ = Define ` - ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notzero= (state_monad$bindS (state_monad$seqS + ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb imm notzero= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ (w__1 : CapStruct) . if ((bits_to_bool ((xor_vec ((bool_to_bits (((w__1 = null_cap))) : 1 words$word)) @@ -8622,23 +8296,23 @@ val _ = Define ` : 1 words$word)))) then let (offset : 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) : 64 words$word)) (( 4 : int):ii) - : 64 words$word)) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . execute_branch ((add_vec w__2 offset : 64 words$word))) - else state_monad$returnS () ))))`; + else sail2_state_monad$returnS () ))))`; (*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*) val _ = Define ` - ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cb imm notset= (state_monad$bindS (state_monad$seqS + ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cb imm notset= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) (register_inaccessible cb)) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else state_monad$bindS + else sail2_state_monad$bindS (readCapReg cb) (\ (w__1 : CapStruct) . if ((bits_to_bool ((xor_vec ((bool_to_bits w__1.CapStruct_tag : 1 words$word)) @@ -8646,25 +8320,25 @@ val _ = Define ` : 1 words$word)))) then let (offset : 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) : 64 words$word)) (( 4 : int):ii) - : 64 words$word)) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . execute_branch ((add_vec w__2 offset : 64 words$word))) - else state_monad$returnS () ))))`; + else sail2_state_monad$returnS () ))))`; (*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) cd cb rt= (state_monad$bindS (state_monad$seqS + ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) cd cb rt= (sail2_state_monad$bindS (sail2_state_monad$seqS (checkCP2usable () ) - (readCapReg cb)) (\ cb_val . state_monad$bindS - (rGPR rt : ( 64 words$word) M) (\ rt_val . state_monad$bindS + (readCapReg cb)) (\ cb_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . sail2_state_monad$bindS (register_inaccessible cd) (\ (w__0 : bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd - else state_monad$bindS + else sail2_state_monad$bindS (register_inaccessible cb) (\ (w__1 : bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb @@ -8680,7 +8354,7 @@ val _ = Define ` (*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; + ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; (*val execute_C2Dump : mword ty5 -> unit*) @@ -8692,14 +8366,14 @@ val _ = Define ` (*val execute_BREAK : unit -> M unit*) val _ = Define ` - ((execute_BREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__120= (SignalException Bp))`; + ((execute_BREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__18= (SignalException Bp))`; (*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) val _ = Define ` - ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rd imm ne likely= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd imm ne likely= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rd : ( 64 words$word) M) (\ (w__1 : 64 words$word) . if ((bits_to_bool ((xor_vec ((bool_to_bits (((w__0 = w__1))) : 1 words$word)) @@ -8707,55 +8381,57 @@ val _ = Define ` : 1 words$word)))) then let (offset : 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + ((mips_sign_extend (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) : 64 words$word)) (( 4 : int):ii) - : 64 words$word)) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . execute_branch ((add_vec w__2 offset : 64 words$word))) - else if likely then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . - state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii) : 64 words$word))) - else state_monad$returnS () ))))`; + else if likely then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ))))`; (*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) val _ = Define ` - ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs imm cmp link likely= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . - let linkVal = ((add_vec_int w__0 (( 8 : int):ii) : 64 words$word)) in state_monad$bindS + ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp link likely= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let linkVal = ((add_vec_int w__0 (( 8 : int):ii) : 64 words$word)) in sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ regVal . let condition = - (compare cmp regVal ((zero_extend1 (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in state_monad$seqS + (compare cmp regVal ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in sail2_state_monad$seqS (if condition then let (offset : 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + ((mips_sign_extend (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) : 64 words$word)) (( 4 : int):ii) - : 64 words$word)) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . execute_branch ((add_vec w__1 offset : 64 words$word))) - else if likely then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . - state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii) : 64 words$word))) - else state_monad$returnS () ) + else if likely then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ) (if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) linkVal - else state_monad$returnS () )))))`; + else sail2_state_monad$returnS () )))))`; (*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; (*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd ((and_vec w__0 w__1 : 64 words$word))))))`; @@ -8763,15 +8439,15 @@ val _ = Define ` (*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ opA . state_monad$bindS + ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ opB . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 32 words$word)) @@ -8781,16 +8457,16 @@ val _ = Define ` (*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ opA . - if ((NotWordVal opA)) then state_monad$bindS + if ((NotWordVal opA)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) else wGPR rt - ((sign_extend1 (( 64 : int):ii) + ((mips_sign_extend (( 64 : int):ii) ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - ((sign_extend1 (( 32 : int):ii) imm : 32 words$word)) + ((mips_sign_extend (( 32 : int):ii) imm : 32 words$word)) : 32 words$word)) : 64 words$word)))))`; @@ -8798,50 +8474,54 @@ val _ = Define ` (*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) val _ = Define ` - ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt imm= (state_monad$bindS + ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ opA . - if ((NotWordVal opA)) then state_monad$bindS + if ((NotWordVal opA)) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) else let (sum33 : 33 bits) = ((add_vec - ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):ii) imm : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) ((mips_sign_extend (( 33 : int):ii) imm : 33 words$word)) : 33 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then SignalException Ov else wGPR rt - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)))))`; (*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) val _ = Define ` - ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs rt rd= (state_monad$bindS - (rGPR rs : ( 64 words$word) M) (\ (opA : 64 bits) . state_monad$bindS + ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (opA : 64 bits) . sail2_state_monad$bindS (rGPR rt : ( 64 words$word) M) (\ (opB : 64 bits) . - if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then state_monad$bindS + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) else let (sum33 : 33 bits) = ((add_vec - ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) - ((sign_extend1 (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) : 33 words$word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))))))`; + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))`; val _ = Define ` - ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var= + ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var= ((case merge_var of DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm | DADDU (rs,rt,rd) => execute_DADDU rs rt rd @@ -8907,12 +8587,9 @@ val _ = Define ` | JALR (rs,rd) => execute_JALR rs rd | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely - | SYSCALL_THREAD_START (g__117) => state_monad$returnS ((execute_SYSCALL_THREAD_START g__117)) - | ImplementationDefinedStopFetching (g__118) => - state_monad$returnS ((execute_ImplementationDefinedStopFetching g__118)) - | SYSCALL (g__119) => execute_SYSCALL g__119 - | BREAK (g__120) => execute_BREAK g__120 - | WAIT (g__121) => execute_WAIT g__121 + | SYSCALL (g__17) => execute_SYSCALL g__17 + | BREAK (g__18) => execute_BREAK g__18 + | WAIT (g__19) => execute_WAIT g__19 | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset @@ -8926,17 +8603,16 @@ val _ = Define ` | SDL (base,rt,offset) => execute_SDL base rt offset | SDR (base,rt,offset) => execute_SDR base rt offset | CACHE (base,op,imm) => execute_CACHE base op imm - | PREF (base,op,imm) => state_monad$returnS ((execute_PREF base op imm)) - | SYNC (g__122) => execute_SYNC g__122 + | SYNC (g__20) => execute_SYNC g__20 | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double - | HCF (g__123) => state_monad$returnS ((execute_HCF g__123)) + | HCF (g__21) => sail2_state_monad$returnS ((execute_HCF g__21)) | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double - | TLBWI (g__124) => execute_TLBWI g__124 - | TLBWR (g__125) => execute_TLBWR g__125 - | TLBR (g__126) => execute_TLBR g__126 - | TLBP (g__127) => execute_TLBP g__127 + | TLBWI (g__22) => execute_TLBWI g__22 + | TLBWR (g__23) => execute_TLBWR g__23 + | TLBR (g__24) => execute_TLBR g__24 + | TLBP (g__25) => execute_TLBP g__25 | RDHWR (rt,rd) => execute_RDHWR rt rd - | ERET (g__128) => execute_ERET g__128 + | ERET (g__26) => execute_ERET g__26 | CGetPerm (rd,cb) => execute_CGetPerm rd cb | CGetType (rd,cb) => execute_CGetType rd cb | CGetBase (rd,cb) => execute_CGetBase rd cb @@ -8974,7 +8650,7 @@ val _ = Define ` | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct | CCall (cs,cb,b__151) => execute_CCall cs cb b__151 - | CReturn (g__129) => execute_CReturn g__129 + | CReturn (g__27) => execute_CReturn g__27 | CBX (cb,imm,notset) => execute_CBX cb imm notset | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero | CJALR (cd,cb,link) => execute_CJALR cd cb link @@ -8984,8 +8660,8 @@ val _ = Define ` execute_CStore rs cb rt rd offset width conditional | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked - | C2Dump (rt) => state_monad$returnS ((execute_C2Dump rt)) - | RI (g__130) => execute_RI g__130 + | C2Dump (rt) => sail2_state_monad$returnS ((execute_C2Dump rt)) + | RI (g__28) => execute_RI g__28 )))`; @@ -8995,451 +8671,531 @@ val _ = Define ` ((supported_instructions:ast ->(ast)option) instr= (SOME instr))`; +(*val cycle_limit_reached : unit -> bool*) + +val _ = Define ` + ((cycle_limit_reached:unit -> bool) () = F)`; + + (*val fetch_and_execute : unit -> M bool*) val _ = Define ` - ((fetch_and_execute:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS PC_ref w__0) - (state_monad$read_regS branchPending_ref : ( 1 words$word) M)) (\ (w__1 : 1 bits) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS inBranchDelay_ref w__1) - (state_monad$write_regS branchPending_ref (vec_of_bits [B0] : 1 words$word))) - (state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__2 : 1 words$word) . state_monad$bindS - (if ((bits_to_bool w__2)) then (state_monad$read_regS delayedPC_ref : ( 64 words$word) M) - else state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . - state_monad$returnS ((add_vec_int w__4 (( 4 : int):ii) : 64 words$word)))) (\ (w__5 : 64 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS nextPC_ref w__5) + ((fetch_and_execute:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PC_ref w__0) + (sail2_state_monad$read_regS branchPending_ref : ( 1 words$word) M)) (\ (w__1 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS inBranchDelay_ref w__1) + (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B0] : 1 words$word))) + (sail2_state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M)) (\ (w__2 : 1 words$word) . sail2_state_monad$bindS + (if ((bits_to_bool w__2)) then (sail2_state_monad$read_regS delayedPC_ref : ( 64 words$word) M) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__4 : 64 words$word) . + sail2_state_monad$returnS ((add_vec_int w__4 (( 4 : int):ii) : 64 words$word)))) (\ (w__5 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__5) (cp2_next_pc () )) - (state_monad$read_regS instCount_ref)) (\ (w__6 : ii) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS instCount_ref ((w__6 + (( 1 : int):ii)))) - (state_monad$read_regS UART_WRITTEN_ref : ( 1 words$word) M)) (\ (w__7 : 1 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS - (if ((bits_to_bool w__7)) then state_monad$bindS - (state_monad$read_regS UART_WDATA_ref : ( 8 words$word) M) (\ (w__8 : 8 bits) . + (sail2_state_monad$read_regS instCount_ref)) (\ (w__6 : ii) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS instCount_ref ((w__6 + (( 1 : int):ii)))) + (sail2_state_monad$read_regS UART_WRITTEN_ref : ( 1 words$word) M)) (\ (w__7 : 1 words$word) . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (if ((bits_to_bool w__7)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS UART_WDATA_ref : ( 8 words$word) M) (\ (w__8 : 8 bits) . let (_ : unit) = (putchar ((lem$w2ui w__8))) in - state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B0] : 1 words$word)) - else state_monad$returnS () ) + sail2_state_monad$write_regS UART_WRITTEN_ref (vec_of_bits [B0] : 1 words$word)) + else sail2_state_monad$returnS () ) (skip () )) (skip () )) - (state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__9 : 64 bits) . - let (_ : unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict "PC: " w__9) in - state_monad$try_catchS ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . state_monad$bindS - (TranslatePC w__10 : ( 64 words$word) M) (\ pc_pa . state_monad$bindS + (let loop_again = T in sail2_state_monad$bindS + (sail2_state_monad$try_catchS ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : 64 words$word) . sail2_state_monad$bindS + (TranslatePC w__9 : ( 64 words$word) M) (\ pc_pa . sail2_state_monad$bindS (MEMr_wrapper (( 32 : int):ii) pc_pa (( 4 : int):ii) : ( 32 words$word) M) (\ instr . let instr_ast = (decode instr) in (case instr_ast of SOME ((HCF (_))) => - let (_ : unit) = (prerr_endline "simulation stopped due to halt instruction.") in - state_monad$returnS F - | SOME (ast) => state_monad$seqS (execute ast) (state_monad$returnS T) + let (_ : unit) = (print_endline "simulation stopped due to halt instruction.") in + sail2_state_monad$returnS F + | SOME (ast) => sail2_state_monad$seqS (execute ast) (sail2_state_monad$returnS loop_again) | NONE => - let (_ : unit) = (prerr_endline "Decode failed") in - state_monad$exitS () + let (_ : unit) = (print_endline "Decode failed") in + sail2_state_monad$returnS F ))))) (\x . - (case x of - ISAException (_) => - let (_ : unit) = (prerr_endline "EXCEPTION") in state_monad$returnS T - )))))))))))`; + (case x of ISAException (_) => sail2_state_monad$returnS loop_again ))) (\ (loop_again : bool) . + sail2_state_monad$returnS (((loop_again /\ ((~ ((cycle_limit_reached () )))))))))))))))))`; (*val init_registers : mword ty64 -> M unit*) val _ = Define ` - ((init_registers:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) initialPC= (state_monad$seqS (state_monad$seqS - (init_cp0_state () ) (init_cp2_state () )) (state_monad$write_regS nextPC_ref initialPC)))`; + ((init_registers:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) initialPC= (sail2_state_monad$seqS (sail2_state_monad$seqS + (init_cp0_state () ) (init_cp2_state () )) (sail2_state_monad$write_regS nextPC_ref initialPC)))`; (*val dump_mips_state : unit -> M unit*) val _ = Define ` - ((dump_mips_state:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + ((dump_mips_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . let (_ : unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict "DEBUG MIPS PC " w__0) in - (state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () - (\ idx unit_var . state_monad$bindS + instance_Sail2_values_Bitvector_Machine_word_mword_dict "DEBUG MIPS PC " w__0) in + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 31 : int):ii) (( 1 : int):ii)) () + (\ idx unit_var . sail2_state_monad$bindS (rGPR ((to_bits ((make_the_value (( 5 : int):ii) : 5 itself)) idx : 5 words$word)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - state_monad$returnS (let _ = - (prerr_endline + sail2_state_monad$returnS (let _ = + (print_endline ((STRCAT "DEBUG MIPS REG " ((STRCAT ((string_of_int - instance_Show_Show_Num_integer_dict idx)) ((STRCAT " " ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + instance_Show_Show_Num_integer_dict idx)) ((STRCAT " " ((string_of_bits w__1))))))))) in () )))))))`; (*val main : unit -> M unit*) val _ = Define ` - ((main:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$seqS + ((main:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (init_registers ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ((elf_entry () )) : 64 words$word))) - (let startTime = (get_time_ns () ) in state_monad$seqS - (state$whileS () (\ unit_var . fetch_and_execute () ) (\ unit_var . state_monad$returnS () )) + (let startTime = (get_time_ns () ) in sail2_state_monad$seqS + (sail2_state$whileS () (\ unit_var . fetch_and_execute () ) (\ unit_var . sail2_state_monad$returnS () )) (let endTime = (get_time_ns () ) in - let elapsed = (endTime - startTime) in state_monad$bindS - (state_monad$read_regS instCount_ref) (\ (w__1 : ii) . + let elapsed = (endTime - startTime) in sail2_state_monad$bindS + (sail2_state_monad$read_regS instCount_ref) (\ (w__1 : ii) . let inst_1e9 = (w__1 * (( 1000000000 : int):ii)) in - let ips = (inst_1e9 / elapsed) in state_monad$bindS (state_monad$seqS (state_monad$seqS + let ips = (inst_1e9 / elapsed) in sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (dump_mips_state () ) (dump_cp2_state () )) - (state_monad$read_regS instCount_ref)) (\ (w__2 : ii) . + (sail2_state_monad$read_regS instCount_ref)) (\ (w__2 : ii) . let (_ : unit) = (print_int "Executed instructions: " w__2) in let (_ : unit) = (print_int "Nanoseconds elapsed: " elapsed) in - state_monad$returnS ((print_int "Instructions per second: " ips))))))))`; + sail2_state_monad$returnS ((print_int "Instructions per second: " ips))))))))`; (*val initialize_registers : unit -> M unit*) val _ = Define ` - ((initialize_registers:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS PC_ref w__0) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__1 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS nextPC_ref w__1) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__2 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBProbe_ref w__2) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBIndex_ref w__3) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBRandom_ref w__4) - (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntryLo0_ref w__5) - (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntryLo1_ref w__6) - (undefined_ContextReg () )) (\ (w__7 : ContextReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBContext_ref w__7) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M)) (\ (w__8 : 16 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBPageMask_ref w__8) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBWired_ref w__9) - (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntryHi_ref w__10) - (undefined_XContextReg () )) (\ (w__11 : XContextReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBXContext_ref w__11) - (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry00_ref w__12) - (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry01_ref w__13) - (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry02_ref w__14) - (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry03_ref w__15) - (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry04_ref w__16) - (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry05_ref w__17) - (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry06_ref w__18) - (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry07_ref w__19) - (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry08_ref w__20) - (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry09_ref w__21) - (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry10_ref w__22) - (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry11_ref w__23) - (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry12_ref w__24) - (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry13_ref w__25) - (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry14_ref w__26) - (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry15_ref w__27) - (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry16_ref w__28) - (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry17_ref w__29) - (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry18_ref w__30) - (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry19_ref w__31) - (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry20_ref w__32) - (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry21_ref w__33) - (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry22_ref w__34) - (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry23_ref w__35) - (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry24_ref w__36) - (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry25_ref w__37) - (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry26_ref w__38) - (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry27_ref w__39) - (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry28_ref w__40) - (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry29_ref w__41) - (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry30_ref w__42) - (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry31_ref w__43) - (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry32_ref w__44) - (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry33_ref w__45) - (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry34_ref w__46) - (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry35_ref w__47) - (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry36_ref w__48) - (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry37_ref w__49) - (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry38_ref w__50) - (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry39_ref w__51) - (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry40_ref w__52) - (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry41_ref w__53) - (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry42_ref w__54) - (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry43_ref w__55) - (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry44_ref w__56) - (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry45_ref w__57) - (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry46_ref w__58) - (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry47_ref w__59) - (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry48_ref w__60) - (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry49_ref w__61) - (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry50_ref w__62) - (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry51_ref w__63) - (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry52_ref w__64) - (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry53_ref w__65) - (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry54_ref w__66) - (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry55_ref w__67) - (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry56_ref w__68) - (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry57_ref w__69) - (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry58_ref w__70) - (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry59_ref w__71) - (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry60_ref w__72) - (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry61_ref w__73) - (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry62_ref w__74) - (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS TLBEntry63_ref w__75) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__76 : 32 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0Compare_ref w__76) - (undefined_CauseReg () )) (\ (w__77 : CauseReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0Cause_ref w__77) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__78 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0EPC_ref w__78) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__79 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0ErrorEPC_ref w__79) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__80 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0LLBit_ref w__80) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__81 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0LLAddr_ref w__81) + ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PC_ref w__0) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__1 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__1) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__2 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref w__2) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBIndex_ref w__3) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBRandom_ref w__4) + (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryLo0_ref w__5) + (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryLo1_ref w__6) + (undefined_ContextReg () )) (\ (w__7 : ContextReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBContext_ref w__7) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M)) (\ (w__8 : 16 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBPageMask_ref w__8) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBWired_ref w__9) + (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryHi_ref w__10) + (undefined_XContextReg () )) (\ (w__11 : XContextReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBXContext_ref w__11) + (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry00_ref w__12) + (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry01_ref w__13) + (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry02_ref w__14) + (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry03_ref w__15) + (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry04_ref w__16) + (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry05_ref w__17) + (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry06_ref w__18) + (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry07_ref w__19) + (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry08_ref w__20) + (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry09_ref w__21) + (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry10_ref w__22) + (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry11_ref w__23) + (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry12_ref w__24) + (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry13_ref w__25) + (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry14_ref w__26) + (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry15_ref w__27) + (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry16_ref w__28) + (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry17_ref w__29) + (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry18_ref w__30) + (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry19_ref w__31) + (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry20_ref w__32) + (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry21_ref w__33) + (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry22_ref w__34) + (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry23_ref w__35) + (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry24_ref w__36) + (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry25_ref w__37) + (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry26_ref w__38) + (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry27_ref w__39) + (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry28_ref w__40) + (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry29_ref w__41) + (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry30_ref w__42) + (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry31_ref w__43) + (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry32_ref w__44) + (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry33_ref w__45) + (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry34_ref w__46) + (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry35_ref w__47) + (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry36_ref w__48) + (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry37_ref w__49) + (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry38_ref w__50) + (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry39_ref w__51) + (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry40_ref w__52) + (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry41_ref w__53) + (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry42_ref w__54) + (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry43_ref w__55) + (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry44_ref w__56) + (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry45_ref w__57) + (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry46_ref w__58) + (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry47_ref w__59) + (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry48_ref w__60) + (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry49_ref w__61) + (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry50_ref w__62) + (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry51_ref w__63) + (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry52_ref w__64) + (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry53_ref w__65) + (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry54_ref w__66) + (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry55_ref w__67) + (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry56_ref w__68) + (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry57_ref w__69) + (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry58_ref w__70) + (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry59_ref w__71) + (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry60_ref w__72) + (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry61_ref w__73) + (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry62_ref w__74) + (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry63_ref w__75) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__76 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Compare_ref w__76) + (undefined_CauseReg () )) (\ (w__77 : CauseReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Cause_ref w__77) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__78 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref w__78) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__79 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0ErrorEPC_ref w__79) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__80 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref w__80) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__81 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLAddr_ref w__81) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__82 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0BadVAddr_ref w__82) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__83 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Count_ref w__83) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__84 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0HWREna_ref w__84) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__85 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0UserLocal_ref w__85) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii) : ( 3 words$word) M)) (\ (w__86 : 3 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0ConfigK0_ref w__86) + (undefined_StatusReg () )) (\ (w__87 : StatusReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Status_ref w__87) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__88 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS branchPending_ref w__88) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__89 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS inBranchDelay_ref w__89) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__90 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPC_ref w__90) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__91 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref w__91) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__92 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref w__92) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__93 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 32 : int):ii) w__93 : ( ( 64 words$word)list) M) (\ (w__94 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS GPR_ref w__94) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__82 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0BadVAddr_ref w__82) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__95 : 8 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WDATA_ref w__95) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__83 : 32 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0Count_ref w__83) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__96 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WRITTEN_ref w__96) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__84 : 32 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0HWREna_ref w__84) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__97 : 8 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_RDATA_ref w__97) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__85 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0UserLocal_ref w__85) - (undefined_StatusReg () )) (\ (w__86 : StatusReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CP0Status_ref w__86) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__98 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_RVALID_ref w__98) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__87 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS branchPending_ref w__87) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__99 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PCC_ref w__99) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__88 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS inBranchDelay_ref w__88) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__100 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPCC_ref w__100) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__89 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS delayedPC_ref w__89) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__101 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPCC_ref w__101) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__90 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS HI_ref w__90) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__102 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS inCCallDelay_ref w__102) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__91 : 64 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS LO_ref w__91) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__103 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS DDC_ref w__103) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__92 : 64 words$word) . state_monad$bindS - (undefined_vector (( 32 : int):ii) w__92 : ( ( 64 words$word)list) M) (\ (w__93 : ( 64 bits) list) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS GPR_ref w__93) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__104 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C01_ref w__104) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__94 : 8 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS UART_WDATA_ref w__94) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__105 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C02_ref w__105) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__95 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS UART_WRITTEN_ref w__95) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__106 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C03_ref w__106) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__96 : 8 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS UART_RDATA_ref w__96) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__107 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C04_ref w__107) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__97 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS UART_RVALID_ref w__97) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__108 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C05_ref w__108) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__98 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS PCC_ref w__98) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__109 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C06_ref w__109) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__99 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS nextPCC_ref w__99) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__110 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C07_ref w__110) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__100 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS delayedPCC_ref w__100) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__111 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C08_ref w__111) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__101 : 1 bits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS inCCallDelay_ref w__101) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__112 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C09_ref w__112) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__102 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C00_ref w__102) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__113 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C10_ref w__113) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__103 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C01_ref w__103) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__114 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C11_ref w__114) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__104 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C02_ref w__104) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__115 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C12_ref w__115) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__105 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C03_ref w__105) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__116 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C13_ref w__116) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__106 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C04_ref w__106) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__117 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C14_ref w__117) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__107 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C05_ref w__107) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__118 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C15_ref w__118) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__108 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C06_ref w__108) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__119 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C16_ref w__119) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__109 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C07_ref w__109) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__120 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C17_ref w__120) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__110 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C08_ref w__110) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__121 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C18_ref w__121) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__111 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C09_ref w__111) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__122 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C19_ref w__122) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__112 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C10_ref w__112) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__123 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C20_ref w__123) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__113 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C11_ref w__113) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__124 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C21_ref w__124) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__114 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C12_ref w__114) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__125 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C22_ref w__125) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__115 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C13_ref w__115) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__126 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C23_ref w__126) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__116 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C14_ref w__116) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__127 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C24_ref w__127) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__117 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C15_ref w__117) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__128 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C25_ref w__128) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__118 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C16_ref w__118) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__129 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C26_ref w__129) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__119 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C17_ref w__119) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__130 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C27_ref w__130) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__120 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C18_ref w__120) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__131 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C28_ref w__131) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__121 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C19_ref w__121) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__132 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C29_ref w__132) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__122 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C20_ref w__122) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__133 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C30_ref w__133) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__123 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C21_ref w__123) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__134 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS C31_ref w__134) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__124 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C22_ref w__124) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__135 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CTLSU_ref w__135) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__125 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C23_ref w__125) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__136 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CTLSP_ref w__136) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__126 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C24_ref w__126) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__137 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS KR1C_ref w__137) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__127 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C25_ref w__127) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__138 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS KR2C_ref w__138) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__128 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C26_ref w__128) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__139 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS KCC_ref w__139) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__129 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C27_ref w__129) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__140 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS KDC_ref w__140) (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__130 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C28_ref w__130) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__131 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C29_ref w__131) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__132 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C30_ref w__132) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__133 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS C31_ref w__133) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__134 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CTLSU_ref w__134) - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__135 : CapReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CTLSP_ref w__135) - (undefined_CapCauseReg () )) (\ (w__136 : CapCauseReg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS CapCause_ref w__136) - (undefined_int () )) (\ (w__137 : ii) . state_monad$write_regS instCount_ref w__137))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 : int):ii) : ( 257 words$word) M)) (\ (w__141 : CapReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS EPCC_ref w__141) + (undefined_CapCauseReg () )) (\ (w__142 : CapCauseReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CapCause_ref w__142) + (undefined_int () )) (\ (w__143 : ii) . sail2_state_monad$write_regS instCount_ref w__143))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; val _ = Define ` ((initial_regstate:regstate)= (<| instCount := ((( 0 : int):ii)); CapCause := - (Mk_CapCauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)); + (<| CapCauseReg_CapCauseReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)) |>); + EPCC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + KDC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + KCC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + KR2C := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); + KR1C := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 257 words$word)); CTLSP := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -9836,7 +9592,7 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 257 words$word)); - C00 := + DDC := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -10036,9 +9792,11 @@ val _ = Define ` inBranchDelay := ((vec_of_bits [B0] : 1 words$word)); branchPending := ((vec_of_bits [B0] : 1 words$word)); CP0Status := - (Mk_StatusReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word)); + (<| StatusReg_StatusReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); + CP0ConfigK0 := ((vec_of_bits [B0;B0;B0] : 3 words$word)); CP0UserLocal := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -10074,557 +9832,750 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); CP0Cause := - (Mk_CauseReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 32 words$word)); + (<| CauseReg_CauseReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); CP0Compare := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0] : 32 words$word)); TLBEntry63 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry62 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry61 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry60 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry59 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry58 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry57 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry56 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry55 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry54 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry53 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry52 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry51 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry50 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry49 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry48 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry47 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry46 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry45 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry44 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry43 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry42 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry41 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry40 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry39 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry38 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry37 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry36 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry35 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry34 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry33 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry32 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry31 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry30 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry29 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry28 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry27 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry26 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry25 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry24 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry23 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry22 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry21 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry20 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry19 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry18 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry17 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry16 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry15 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry14 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry13 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry12 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry11 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry10 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry09 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry08 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry07 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry06 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry05 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry04 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry03 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry02 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry01 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntry00 := - (Mk_TLBEntry (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0] - : 117 words$word)); + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBXContext := - (Mk_XContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| XContextReg_XContextReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntryHi := - (Mk_TLBEntryHiReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] - : 64 words$word)); + (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBWired := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); TLBPageMask := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)); TLBContext := - (Mk_ContextReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| ContextReg_ContextReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntryLo1 := - (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] - : 64 words$word)); + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBEntryLo0 := - (Mk_TLBEntryLoReg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0] - : 64 words$word)); + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); TLBRandom := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); TLBIndex := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); TLBProbe := ((vec_of_bits [B0] : 1 words$word)); diff --git a/snapshots/hol4/sail/cheri/cheri_typesScript.sml b/snapshots/hol4/sail/cheri/cheri_typesScript.sml index 2bc764e0..fce47ce3 100644 --- a/snapshots/hol4/sail/cheri/cheri_typesScript.sml +++ b/snapshots/hol4/sail/cheri/cheri_typesScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from cheri_types.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory; val _ = numLib.prefer_num(); @@ -10,11 +10,12 @@ val _ = new_theory "cheri_types" (*Generated by Sail from cheri.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); @@ -31,52 +32,45 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` - CauseReg = Mk_CauseReg of ( 32 words$word)`; - + CauseReg = <| CauseReg_CauseReg_chunk_0 : 32 words$word |>`; val _ = Hol_datatype ` - CapCauseReg = Mk_CapCauseReg of ( 16 words$word)`; - + CapCauseReg = <| CapCauseReg_CapCauseReg_chunk_0 : 16 words$word |>`; val _ = Hol_datatype ` - TLBEntryLoReg = Mk_TLBEntryLoReg of ( 64 words$word)`; - + TLBEntryLoReg = <| TLBEntryLoReg_TLBEntryLoReg_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - TLBEntryHiReg = Mk_TLBEntryHiReg of ( 64 words$word)`; - + TLBEntryHiReg = <| TLBEntryHiReg_TLBEntryHiReg_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - ContextReg = Mk_ContextReg of ( 64 words$word)`; - + ContextReg = <| ContextReg_ContextReg_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - XContextReg = Mk_XContextReg of ( 64 words$word)`; - + XContextReg = <| XContextReg_XContextReg_chunk_0 : 64 words$word |>`; val _ = type_abbrev( "TLBIndexT" , ``: 6 bits``); val _ = Hol_datatype ` - TLBEntry = Mk_TLBEntry of ( 117 words$word)`; - + TLBEntry = + <| TLBEntry_TLBEntry_chunk_1 : 53 words$word; TLBEntry_TLBEntry_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - StatusReg = Mk_StatusReg of ( 32 words$word)`; - + StatusReg = <| StatusReg_StatusReg_chunk_0 : 32 words$word |>`; @@ -171,6 +165,12 @@ val _ = Hol_datatype ` +val _ = Hol_datatype ` + WordTypeUnaligned = WL | WR | DL | DR`; + + + + val _ = type_abbrev( "CapLen" , ``: int``); val _ = type_abbrev( "uint64" , ``: int``); @@ -253,8 +253,6 @@ val _ = Hol_datatype ` | JALR of ((regno # regno)) | BEQ of ((regno # regno # imm16 # bool # bool)) | BCMPZ of ((regno # imm16 # Comparison # bool # bool)) - | SYSCALL_THREAD_START of (unit) - | ImplementationDefinedStopFetching of (unit) | SYSCALL of (unit) | BREAK of (unit) | WAIT of (unit) @@ -271,7 +269,6 @@ val _ = Hol_datatype ` | SDL of ((regno # regno # 16 bits)) | SDR of ((regno # regno # 16 bits)) | CACHE of ((regno # regno # 16 bits)) - | PREF of ((regno # regno # 16 bits)) | SYNC of (unit) | MFC0 of ((regno # regno # 3 bits # bool)) | HCF of (unit) @@ -326,7 +323,7 @@ val _ = Hol_datatype ` | CLoad of ((regno # regno # regno # 8 bits # bool # WordType # bool)) | CStore of ((regno # regno # regno # regno # 8 bits # WordType # bool)) | CSC of ((regno # regno # regno # regno # 11 bits # bool)) - | CLC of ((regno # regno # regno # 11 bits # bool)) + | CLC of ((regno # regno # regno # 16 bits # bool)) | C2Dump of (regno) | RI of (unit)`; @@ -380,6 +377,7 @@ val _ = Hol_datatype ` | Regval_vector_1_dec_bit of ( 1 words$word) | Regval_vector_257_dec_bit of ( 257 words$word) | Regval_vector_32_dec_bit of ( 32 words$word) + | Regval_vector_3_dec_bit of ( 3 words$word) | Regval_vector_64_dec_bit of ( 64 words$word) | Regval_vector_6_dec_bit of ( 6 words$word) | Regval_vector_8_dec_bit of ( 8 words$word)`; @@ -391,6 +389,11 @@ val _ = Hol_datatype ` regstate = <| instCount : ii; CapCause : CapCauseReg; + EPCC : 257 words$word; + KDC : 257 words$word; + KCC : 257 words$word; + KR2C : 257 words$word; + KR1C : 257 words$word; CTLSP : 257 words$word; CTLSU : 257 words$word; C31 : 257 words$word; @@ -424,7 +427,7 @@ val _ = Hol_datatype ` C03 : 257 words$word; C02 : 257 words$word; C01 : 257 words$word; - C00 : 257 words$word; + DDC : 257 words$word; inCCallDelay : 1 words$word; delayedPCC : 257 words$word; nextPCC : 257 words$word; @@ -440,6 +443,7 @@ val _ = Hol_datatype ` inBranchDelay : 1 words$word; branchPending : 1 words$word; CP0Status : StatusReg; + CP0ConfigK0 : 3 words$word; CP0UserLocal : 64 words$word; CP0HWREna : 32 words$word; CP0Count : 32 words$word; @@ -535,7 +539,7 @@ val _ = Hol_datatype ` val _ = Define ` ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var= - ((case merge_var of Regval_CapCauseReg (v) => SOME v | g__114 => NONE )))`; + ((case merge_var of Regval_CapCauseReg (v) => SOME v | g__16 => NONE )))`; (*val regval_of_CapCauseReg : CapCauseReg -> register_value*) @@ -548,7 +552,7 @@ val _ = Define ` val _ = Define ` ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var= - ((case merge_var of Regval_CauseReg (v) => SOME v | g__113 => NONE )))`; + ((case merge_var of Regval_CauseReg (v) => SOME v | g__15 => NONE )))`; (*val regval_of_CauseReg : CauseReg -> register_value*) @@ -561,7 +565,7 @@ val _ = Define ` val _ = Define ` ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var= - ((case merge_var of Regval_ContextReg (v) => SOME v | g__112 => NONE )))`; + ((case merge_var of Regval_ContextReg (v) => SOME v | g__14 => NONE )))`; (*val regval_of_ContextReg : ContextReg -> register_value*) @@ -574,7 +578,7 @@ val _ = Define ` val _ = Define ` ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var= - ((case merge_var of Regval_StatusReg (v) => SOME v | g__111 => NONE )))`; + ((case merge_var of Regval_StatusReg (v) => SOME v | g__13 => NONE )))`; (*val regval_of_StatusReg : StatusReg -> register_value*) @@ -587,7 +591,7 @@ val _ = Define ` val _ = Define ` ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var= - ((case merge_var of Regval_TLBEntry (v) => SOME v | g__110 => NONE )))`; + ((case merge_var of Regval_TLBEntry (v) => SOME v | g__12 => NONE )))`; (*val regval_of_TLBEntry : TLBEntry -> register_value*) @@ -600,7 +604,7 @@ val _ = Define ` val _ = Define ` ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var= - ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__109 => NONE )))`; + ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__11 => NONE )))`; (*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) @@ -613,7 +617,7 @@ val _ = Define ` val _ = Define ` ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var= - ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__108 => NONE )))`; + ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__10 => NONE )))`; (*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) @@ -626,7 +630,7 @@ val _ = Define ` val _ = Define ` ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var= - ((case merge_var of Regval_XContextReg (v) => SOME v | g__107 => NONE )))`; + ((case merge_var of Regval_XContextReg (v) => SOME v | g__9 => NONE )))`; (*val regval_of_XContextReg : XContextReg -> register_value*) @@ -638,8 +642,7 @@ val _ = Define ` (*val int_of_regval : register_value -> maybe ii*) val _ = Define ` - ((int_of_regval:register_value ->(int)option) merge_var= - ((case merge_var of Regval_int (v) => SOME v | g__106 => NONE )))`; + ((int_of_regval:register_value ->(int)option) merge_var= ((case merge_var of Regval_int (v) => SOME v | g__8 => NONE )))`; (*val regval_of_int : ii -> register_value*) @@ -652,7 +655,7 @@ val _ = Define ` val _ = Define ` ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var= - ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`; + ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__7 => NONE )))`; (*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) @@ -665,7 +668,7 @@ val _ = Define ` val _ = Define ` ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= - ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`; + ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__6 => NONE )))`; (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) @@ -678,7 +681,7 @@ val _ = Define ` val _ = Define ` ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var= - ((case merge_var of Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`; + ((case merge_var of Regval_vector_257_dec_bit (v) => SOME v | g__5 => NONE )))`; (*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) @@ -691,7 +694,7 @@ val _ = Define ` val _ = Define ` ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= - ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`; + ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__4 => NONE )))`; (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) @@ -700,11 +703,24 @@ val _ = Define ` ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`; +(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*) + +val _ = Define ` + ((vector_3_dec_bit_of_regval:register_value ->((3)words$word)option) merge_var= + ((case merge_var of Regval_vector_3_dec_bit (v) => SOME v | g__3 => NONE )))`; + + +(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*) + +val _ = Define ` + ((regval_of_vector_3_dec_bit:(3)words$word -> register_value) v= (Regval_vector_3_dec_bit v))`; + + (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) val _ = Define ` ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= - ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`; + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__2 => NONE )))`; (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) @@ -717,7 +733,7 @@ val _ = Define ` val _ = Define ` ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var= - ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`; + ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__1 => NONE )))`; (*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) @@ -730,7 +746,7 @@ val _ = Define ` val _ = Define ` ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var= - ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`; + ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__0 => NONE )))`; (*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) @@ -743,44 +759,44 @@ val _ = Define ` (*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` - ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= (\x . (case x of - Regval_vector (_, _, v) => just_list (MAP of_regval v) + Regval_vector (_, _, v) => just_list (MAP of_regval1 v) | _ => NONE )))`; (*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) val _ = Define ` - ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`; (*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` - ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= (\x . (case x of - Regval_list v => just_list (MAP of_regval v) + Regval_list v => just_list (MAP of_regval1 v) | _ => NONE )))`; (*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) val _ = Define ` - ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`; (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) val _ = Define ` - ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= (\x . (case x of - Regval_option v => SOME (OPTION_BIND v of_regval) + Regval_option v => SOME (OPTION_BIND v of_regval1) | _ => NONE )))`; (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) val _ = Define ` - ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`; @@ -803,6 +819,33 @@ val _ = Define ` val _ = Define ` + ((KDC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "KDC"; + read_from := (\ s . s.KDC); + write_to := (\ v s . (( s with<| KDC := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((KR2C_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "KR2C"; + read_from := (\ s . s.KR2C); + write_to := (\ v s . (( s with<| KR2C := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` + ((KR1C_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "KR1C"; + read_from := (\ s . s.KR1C); + write_to := (\ v s . (( s with<| KR1C := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` ((CTLSP_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "CTLSP"; read_from := (\ s . s.CTLSP); @@ -821,6 +864,15 @@ val _ = Define ` val _ = Define ` + ((C31_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "C31"; + read_from := (\ s . s.C31); + write_to := (\ v s . (( s with<| C31 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` ((C30_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C30"; read_from := (\ s . s.C30); @@ -830,6 +882,15 @@ val _ = Define ` val _ = Define ` + ((C29_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "C29"; + read_from := (\ s . s.C29); + write_to := (\ v s . (( s with<| C29 := v |>))); + of_regval := (\ v . vector_257_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; + + +val _ = Define ` ((C28_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| name := "C28"; read_from := (\ s . s.C28); @@ -1082,10 +1143,10 @@ val _ = Define ` val _ = Define ` - ((C00_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| - name := "C00"; - read_from := (\ s . s.C00); - write_to := (\ v s . (( s with<| C00 := v |>))); + ((DDC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "DDC"; + read_from := (\ s . s.DDC); + write_to := (\ v s . (( s with<| DDC := v |>))); of_regval := (\ v . vector_257_dec_bit_of_regval v); regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; @@ -1127,19 +1188,19 @@ val _ = Define ` val _ = Define ` - ((C31_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| - name := "C31"; - read_from := (\ s . s.C31); - write_to := (\ v s . (( s with<| C31 := v |>))); + ((KCC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "KCC"; + read_from := (\ s . s.KCC); + write_to := (\ v s . (( s with<| KCC := v |>))); of_regval := (\ v . vector_257_dec_bit_of_regval v); regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; val _ = Define ` - ((C29_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| - name := "C29"; - read_from := (\ s . s.C29); - write_to := (\ v s . (( s with<| C29 := v |>))); + ((EPCC_ref:((regstate),(register_value),((257)words$word))register_ref)= (<| + name := "EPCC"; + read_from := (\ s . s.EPCC); + write_to := (\ v s . (( s with<| EPCC := v |>))); of_regval := (\ v . vector_257_dec_bit_of_regval v); regval_of := (\ v . regval_of_vector_257_dec_bit v) |>))`; @@ -1244,6 +1305,15 @@ val _ = Define ` val _ = Define ` + ((CP0ConfigK0_ref:((regstate),(register_value),((3)words$word))register_ref)= (<| + name := "CP0ConfigK0"; + read_from := (\ s . s.CP0ConfigK0); + write_to := (\ v s . (( s with<| CP0ConfigK0 := v |>))); + of_regval := (\ v . vector_3_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_3_dec_bit v) |>))`; + + +val _ = Define ` ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "CP0UserLocal"; read_from := (\ s . s.CP0UserLocal); @@ -2022,9 +2092,14 @@ val _ = Define ` ((get_regval:string -> regstate ->(register_value)option) reg_name s= (if reg_name = "instCount" then SOME (instCount_ref.regval_of (instCount_ref.read_from s)) else if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else + if reg_name = "KDC" then SOME (KDC_ref.regval_of (KDC_ref.read_from s)) else + if reg_name = "KR2C" then SOME (KR2C_ref.regval_of (KR2C_ref.read_from s)) else + if reg_name = "KR1C" then SOME (KR1C_ref.regval_of (KR1C_ref.read_from s)) else if reg_name = "CTLSP" then SOME (CTLSP_ref.regval_of (CTLSP_ref.read_from s)) else if reg_name = "CTLSU" then SOME (CTLSU_ref.regval_of (CTLSU_ref.read_from s)) else + if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else if reg_name = "C30" then SOME (C30_ref.regval_of (C30_ref.read_from s)) else + if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else if reg_name = "C28" then SOME (C28_ref.regval_of (C28_ref.read_from s)) else if reg_name = "C27" then SOME (C27_ref.regval_of (C27_ref.read_from s)) else if reg_name = "C26" then SOME (C26_ref.regval_of (C26_ref.read_from s)) else @@ -2053,13 +2128,13 @@ val _ = Define ` if reg_name = "C03" then SOME (C03_ref.regval_of (C03_ref.read_from s)) else if reg_name = "C02" then SOME (C02_ref.regval_of (C02_ref.read_from s)) else if reg_name = "C01" then SOME (C01_ref.regval_of (C01_ref.read_from s)) else - if reg_name = "C00" then SOME (C00_ref.regval_of (C00_ref.read_from s)) else + if reg_name = "DDC" then SOME (DDC_ref.regval_of (DDC_ref.read_from s)) else if reg_name = "inCCallDelay" then SOME (inCCallDelay_ref.regval_of (inCCallDelay_ref.read_from s)) else if reg_name = "nextPCC" then SOME (nextPCC_ref.regval_of (nextPCC_ref.read_from s)) else if reg_name = "delayedPCC" then SOME (delayedPCC_ref.regval_of (delayedPCC_ref.read_from s)) else if reg_name = "PCC" then SOME (PCC_ref.regval_of (PCC_ref.read_from s)) else - if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else - if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else + if reg_name = "KCC" then SOME (KCC_ref.regval_of (KCC_ref.read_from s)) else + if reg_name = "EPCC" then SOME (EPCC_ref.regval_of (EPCC_ref.read_from s)) else if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else @@ -2071,6 +2146,7 @@ val _ = Define ` if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else + if reg_name = "CP0ConfigK0" then SOME (CP0ConfigK0_ref.regval_of (CP0ConfigK0_ref.read_from s)) else if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else @@ -2165,9 +2241,14 @@ val _ = Define ` ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= (if reg_name = "instCount" then OPTION_MAP (\ v . instCount_ref.write_to v s) (instCount_ref.of_regval v) else if reg_name = "CapCause" then OPTION_MAP (\ v . CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else + if reg_name = "KDC" then OPTION_MAP (\ v . KDC_ref.write_to v s) (KDC_ref.of_regval v) else + if reg_name = "KR2C" then OPTION_MAP (\ v . KR2C_ref.write_to v s) (KR2C_ref.of_regval v) else + if reg_name = "KR1C" then OPTION_MAP (\ v . KR1C_ref.write_to v s) (KR1C_ref.of_regval v) else if reg_name = "CTLSP" then OPTION_MAP (\ v . CTLSP_ref.write_to v s) (CTLSP_ref.of_regval v) else if reg_name = "CTLSU" then OPTION_MAP (\ v . CTLSU_ref.write_to v s) (CTLSU_ref.of_regval v) else + if reg_name = "C31" then OPTION_MAP (\ v . C31_ref.write_to v s) (C31_ref.of_regval v) else if reg_name = "C30" then OPTION_MAP (\ v . C30_ref.write_to v s) (C30_ref.of_regval v) else + if reg_name = "C29" then OPTION_MAP (\ v . C29_ref.write_to v s) (C29_ref.of_regval v) else if reg_name = "C28" then OPTION_MAP (\ v . C28_ref.write_to v s) (C28_ref.of_regval v) else if reg_name = "C27" then OPTION_MAP (\ v . C27_ref.write_to v s) (C27_ref.of_regval v) else if reg_name = "C26" then OPTION_MAP (\ v . C26_ref.write_to v s) (C26_ref.of_regval v) else @@ -2196,13 +2277,13 @@ val _ = Define ` if reg_name = "C03" then OPTION_MAP (\ v . C03_ref.write_to v s) (C03_ref.of_regval v) else if reg_name = "C02" then OPTION_MAP (\ v . C02_ref.write_to v s) (C02_ref.of_regval v) else if reg_name = "C01" then OPTION_MAP (\ v . C01_ref.write_to v s) (C01_ref.of_regval v) else - if reg_name = "C00" then OPTION_MAP (\ v . C00_ref.write_to v s) (C00_ref.of_regval v) else + if reg_name = "DDC" then OPTION_MAP (\ v . DDC_ref.write_to v s) (DDC_ref.of_regval v) else if reg_name = "inCCallDelay" then OPTION_MAP (\ v . inCCallDelay_ref.write_to v s) (inCCallDelay_ref.of_regval v) else if reg_name = "nextPCC" then OPTION_MAP (\ v . nextPCC_ref.write_to v s) (nextPCC_ref.of_regval v) else if reg_name = "delayedPCC" then OPTION_MAP (\ v . delayedPCC_ref.write_to v s) (delayedPCC_ref.of_regval v) else if reg_name = "PCC" then OPTION_MAP (\ v . PCC_ref.write_to v s) (PCC_ref.of_regval v) else - if reg_name = "C31" then OPTION_MAP (\ v . C31_ref.write_to v s) (C31_ref.of_regval v) else - if reg_name = "C29" then OPTION_MAP (\ v . C29_ref.write_to v s) (C29_ref.of_regval v) else + if reg_name = "KCC" then OPTION_MAP (\ v . KCC_ref.write_to v s) (KCC_ref.of_regval v) else + if reg_name = "EPCC" then OPTION_MAP (\ v . EPCC_ref.write_to v s) (EPCC_ref.of_regval v) else if reg_name = "UART_RVALID" then OPTION_MAP (\ v . UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else if reg_name = "UART_RDATA" then OPTION_MAP (\ v . UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v . UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else @@ -2214,6 +2295,7 @@ val _ = Define ` if reg_name = "inBranchDelay" then OPTION_MAP (\ v . inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else if reg_name = "branchPending" then OPTION_MAP (\ v . branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else if reg_name = "CP0Status" then OPTION_MAP (\ v . CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else + if reg_name = "CP0ConfigK0" then OPTION_MAP (\ v . CP0ConfigK0_ref.write_to v s) (CP0ConfigK0_ref.of_regval v) else if reg_name = "CP0UserLocal" then OPTION_MAP (\ v . CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else if reg_name = "CP0HWREna" then OPTION_MAP (\ v . CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else if reg_name = "CP0Count" then OPTION_MAP (\ v . CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else diff --git a/snapshots/hol4/sail/cheri/mips_extrasScript.sml b/snapshots/hol4/sail/cheri/mips_extrasScript.sml index 399ecc93..aef40b53 100644 --- a/snapshots/hol4/sail/cheri/mips_extrasScript.sml +++ b/snapshots/hol4/sail/cheri/mips_extrasScript.sml @@ -1,6 +1,6 @@ -(*Generated by Lem from /usr/local/google/home/ramanakumar/cheri/sail/mips/mips_extras.lem.*) +(*Generated by Lem from mips_extras.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory prompt_monadTheory promptTheory sail_operatorsTheory; +open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_promptTheory sail2_operatorsTheory; val _ = numLib.prefer_num(); @@ -10,11 +10,11 @@ val _ = new_theory "mips_extras" (*open import Pervasives*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) (*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) @@ -22,43 +22,43 @@ val _ = new_theory "mips_extras" (*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) val _ = Define ` - ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`; + ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1))`; val _ = Define ` - ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`; + ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1))`; (*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) val _ = Define ` - ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a addr= (state_monad$bindS - (state_monad$read_tagS - dict_Sail_values_Bitvector_a addr) (\ t . - state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`; + ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a addr= (sail2_state_monad$bindS + (sail2_state_monad$read_tagS + dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`; (*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) val _ = Define ` - ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr t= (state_monad$bindS (state_monad$write_tagS - dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) - (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; + ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr t= (sail2_state_monad$bindS (sail2_state_monad$write_tagS + dict_Sail2_values_Bitvector_a addr (bitU_of_bool t)) + (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; val _ = Define ` - ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$bindS - (state_monad$read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . state_monad$bindS - (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . - state_monad$returnS (t, v)))))`; + ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$bindS + (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v . sail2_state_monad$bindS + (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$returnS (t, v)))))`; val _ = Define ` - ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1= (state_monad$bindS - (state_monad$read_memS - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v . state_monad$bindS - (read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . - state_monad$returnS (t, v)))))`; + ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$bindS + (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v . sail2_state_monad$bindS + (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$returnS (t, v)))))`; @@ -68,21 +68,21 @@ val _ = Define ` (*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) val _ = Define ` - ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS - dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS - dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS - dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; val _ = Define ` - ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a addr size1= (state_monad$write_mem_eaS - dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; @@ -92,33 +92,35 @@ val _ = Define ` (*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) val _ = Define ` - ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (state_monad$bindS (state_monad$write_mem_valS - dict_Sail_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; + ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; val _ = Define ` - ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v= (state_monad$bindS (state_monad$write_mem_valS - dict_Sail_values_Bitvector_b v) (\ b . state_monad$returnS (if b then T else F))))`; + ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\ b . sail2_state_monad$returnS (if b then T else F))))`; val _ = Define ` - ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (state_monad$bindS (state_monad$write_mem_valS - dict_Sail_values_Bitvector_b v) (\b . (case (b ) of - ( _ ) => state_monad$bindS - (write_tag_bool dict_Sail_values_Bitvector_a addr t) + ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\b . (case (b ) of + ( _ ) => sail2_state_monad$bindS + (write_tag_bool dict_Sail2_values_Bitvector_a addr t) (\u . (case (u ) of - ( _ ) => state_monad$returnS () + ( _ ) => sail2_state_monad$returnS () )) ))))`; val _ = Define ` - ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v= (state_monad$bindS (state_monad$write_mem_valS - dict_Sail_values_Bitvector_b v) (\ b . state_monad$bindS (write_tag_bool - dict_Sail_values_Bitvector_a addr t) (\u . (case (u ) of ( _ ) => state_monad$returnS (if b then T else F) )))))`; + ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\ b . sail2_state_monad$bindS (write_tag_bool + dict_Sail2_values_Bitvector_a addr t) (\u . (case (u ) of + ( _ ) => sail2_state_monad$returnS (if b then T else F) + )))))`; (*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) val _ = Define ` - ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () = (barrier Barrier_MIPS_SYNC))`; + ((MEM_sync:unit -> 'regval sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'regval sail2_state_monad$sequential_state)set) () = (barrier Barrier_MIPS_SYNC))`; (* Some wrappers copied from aarch64_extras *) @@ -134,104 +136,87 @@ val _ = Define ` (*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) val _ = Define ` - ((get_slice_int0:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= ( - dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; + ((get_slice_int0:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo= ( + dict_Sail2_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; val _ = Define ` - ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data= (state_monad$seqS - (MEMea dict_Sail_values_Bitvector_b addr size1) - (MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`; + ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd sail2_state_monad$sequential_state ->(((unit),'c)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data= (sail2_state_monad$seqS + (MEMea dict_Sail2_values_Bitvector_b addr size1) + (MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data)))`; val _ = Define ` - ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr= (MEMr - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`; + ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd sail2_state_monad$sequential_state ->(('c,'b)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr= (MEMr + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1))`; val _ = Define ` - ((string_of_bits:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs= (string_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`; - -val _ = Define ` ((string_of_int:'a Show_class -> 'a -> string)dict_Show_Show_a= (dict_Show_Show_a.show_method))`; val _ = Define ` - ((sign_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( - dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`; - -val _ = Define ` - ((zero_extend0:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len= (maybe_failwith ( - dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`; - - -val _ = Define ` - ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in - state_monad$maybe_failS "shift_bits_left" r))`; + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_left" r))`; val _ = Define ` - ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in - state_monad$maybe_failS "shift_bits_right" r))`; + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_right" r))`; val _ = Define ` - ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a state_monad$sequential_state ->(('b,'c)state_monad$result#'a state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n= + ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= (let r = (OPTION_BIND ( - dict_Sail_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in - state_monad$maybe_failS "shift_bits_right_arith" r))`; + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_right_arith" r))`; (* Use constants for undefined values for now *) val _ = Define ` - ((internal_pick:'a list -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) vs= (state_monad$returnS (HD vs)))`; - -val _ = Define ` - ((undefined_string:unit -> 'a state_monad$sequential_state ->(((string),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS ""))`; + ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS ""))`; val _ = Define ` - ((undefined_unit:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS () ))`; + ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`; val _ = Define ` - ((undefined_int:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (( 0 : int):ii)))`; + ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; (*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) val _ = Define ` - ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u= (state_monad$returnS (repeat [u] len)))`; + ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u= (sail2_state_monad$returnS (repeat [u] len)))`; (*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) val _ = Define ` - ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a len= (state_monad$returnS ( - dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`; + ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a len= (sail2_state_monad$returnS ( + dict_Sail2_values_Bitvector_a.of_bools_method (repeat [F] len))))`; (*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) val _ = Define ` - ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail_values_Bitvector_a= - (undefined_bitvector dict_Sail_values_Bitvector_a))`; + ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a= + (undefined_bitvector dict_Sail2_values_Bitvector_a))`; val _ = Define ` - ((undefined_bit:unit -> 'a state_monad$sequential_state ->(((bitU),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS B0))`; + ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS B0))`; val _ = Define ` - ((undefined_real:unit -> 'a state_monad$sequential_state ->(((real),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; + ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; val _ = Define ` - ((undefined_range:'a -> 'd -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i j= (state_monad$returnS i))`; + ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j= (sail2_state_monad$returnS i))`; val _ = Define ` - ((undefined_atom:'a -> 'b state_monad$sequential_state ->(('a,'c)state_monad$result#'b state_monad$sequential_state)set) i= (state_monad$returnS i))`; + ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i= (sail2_state_monad$returnS i))`; val _ = Define ` - ((undefined_nat:unit -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS (( 0 : int):ii)))`; + ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; val _ = Define ` - ((skip:unit -> 'a state_monad$sequential_state ->(((unit),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$returnS () ))`; + ((skip:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`; (*val elf_entry : unit -> integer*) @@ -240,13 +225,18 @@ val _ = Define ` val _ = Define ` - ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail_values_Bitvector_a msg bs= (prerr_endline ( STRCAT msg (string_of_bits - dict_Sail_values_Bitvector_a bs))))`; + ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs= (prerr_endline ( STRCAT msg (string_of_bv + dict_Sail2_values_Bitvector_a bs))))`; (*val get_time_ns : unit -> integer*) val _ = Define ` ((get_time_ns:unit -> int) () = (( 0 : int)))`; + +(*val cycle_count : unit -> unit*) +val _ = Define ` + ((cycle_count:unit -> unit) _= () )`; + val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile index 161de9d3..0e95ba5e 100644 --- a/snapshots/hol4/sail/lib/hol/Holmakefile +++ b/snapshots/hol4/sail/lib/hol/Holmakefile @@ -1,11 +1,12 @@ -LEM_SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \ - sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \ - state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml +LEM_SCRIPTS = sail2_instr_kindsScript.sml sail2_valuesScript.sml sail2_operatorsScript.sml \ + sail2_operators_mwordsScript.sml sail2_operators_bitlistsScript.sml \ + sail2_state_monadScript.sml sail2_stateScript.sml sail2_promptScript.sml sail2_prompt_monadScript.sml \ + sail2_stringScript.sml LEM_CLEANS = $(LEM_SCRIPTS) SCRIPTS = $(LEM_SCRIPTS) \ - sail_valuesAuxiliaryScript.sml stateAuxiliaryScript.sml + sail2_valuesAuxiliaryScript.sml sail2_stateAuxiliaryScript.sml THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS)) diff --git a/snapshots/hol4/sail/lib/hol/promptScript.sml b/snapshots/hol4/sail/lib/hol/promptScript.sml deleted file mode 100644 index 95d6e752..00000000 --- a/snapshots/hol4/sail/lib/hol/promptScript.sml +++ /dev/null @@ -1,15 +0,0 @@ -(*Generated by Lem from prompt.lem.*) -open HolKernel Parse boolLib bossLib; -open prompt_monadTheory state_monadTheory stateTheory; - -val _ = numLib.prefer_num(); - - - -val _ = new_theory "prompt" - -(*open import Prompt_monad*) -(*open import State_monad*) -(*open import State*) -val _ = export_theory() - diff --git a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml index 5a119d61..b8a643ef 100644 --- a/snapshots/hol4/sail/lib/hol/sail_instr_kindsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_instr_kindsScript.sml @@ -1,4 +1,4 @@ -(*Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.*) +(*Generated by Lem from ../../src/lem_interp/sail2_instr_kinds.lem.*) open HolKernel Parse boolLib bossLib; open lem_pervasives_extraTheory; @@ -6,56 +6,11 @@ val _ = numLib.prefer_num(); -val _ = new_theory "sail_instr_kinds" +val _ = new_theory "sail2_instr_kinds" (*========================================================================*) -(* Sail *) -(* *) -(* Copyright (c) 2013-2017 *) -(* Kathyrn Gray *) -(* Shaked Flur *) -(* Stephen Kell *) -(* Gabriel Kerneis *) -(* Robert Norton-Wright *) -(* Christopher Pulte *) -(* Peter Sewell *) -(* Alasdair Armstrong *) -(* Brian Campbell *) -(* Thomas Bauereiss *) -(* Anthony Fox *) -(* Jon French *) -(* Dominic Mulligan *) -(* Stephen Kell *) -(* Mark Wassell *) -(* *) -(* All rights reserved. *) -(* *) -(* This software was developed by the University of Cambridge Computer *) -(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) -(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) -(* *) -(* Redistribution and use in source and binary forms, with or without *) -(* modification, are permitted provided that the following conditions *) -(* are met: *) -(* 1. Redistributions of source code must retain the above copyright *) -(* notice, this list of conditions and the following disclaimer. *) -(* 2. Redistributions in binary form must reproduce the above copyright *) -(* notice, this list of conditions and the following disclaimer in *) -(* the documentation and/or other materials provided with the *) -(* distribution. *) -(* *) -(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) -(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) -(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) -(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) -(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) -(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) -(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) -(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) -(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) -(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) -(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) -(* SUCH DAMAGE. *) +(* Copyright (c) 2018 Sail contributors. *) +(* This material is provided for anonymous review purposes only. *) (*========================================================================*) (*open import Pervasives_extra*) @@ -70,29 +25,29 @@ val _ = Hol_datatype ` (*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*) val _ = Define ` - ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail_instr_kinds_EnumerationType_a e1 e2= + ((enumeration_typeCompare:'a EnumerationType_class -> 'a -> 'a -> ordering)dict_Sail2_instr_kinds_EnumerationType_a e1 e2= (genericCompare (<) (=) ( - dict_Sail_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail_instr_kinds_EnumerationType_a.toNat_method e2)))`; + dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e1) (dict_Sail2_instr_kinds_EnumerationType_a.toNat_method e2)))`; val _ = Define ` -((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail_instr_kinds_EnumerationType_a= (<| +((instance_Basic_classes_Ord_var_dict:'a EnumerationType_class -> 'a Ord_class)dict_Sail2_instr_kinds_EnumerationType_a= (<| compare_method := - (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a); + (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a); isLess_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LESS); + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LESS); isLessEqual_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> GREATER); + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> GREATER); isGreater_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GREATER); + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GREATER); isGreaterEqual_method := (\ r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`; + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) <> LESS)|>))`; @@ -117,7 +72,7 @@ val _ = Hol_datatype ` (* the read part of a lock'd instruction (rmw) *) val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<| +((instance_Show_Show_Sail2_instr_kinds_read_kind_dict:(read_kind)Show_class)= (<| show_method := (\x . (case x of @@ -153,7 +108,7 @@ val _ = Hol_datatype ` (* the write part of a lock'd instruction (rmw) *) val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<| +((instance_Show_Show_Sail2_instr_kinds_write_kind_dict:(write_kind)Show_class)= (<| show_method := (\x . (case x of @@ -187,6 +142,10 @@ val _ = Hol_datatype ` | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w + | Barrier_RISCV_w_rw + | Barrier_RISCV_rw_r + | Barrier_RISCV_r_w + | Barrier_RISCV_w_r | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE`; @@ -194,7 +153,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<| +((instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)Show_class)= (<| show_method := (\x . (case x of @@ -216,6 +175,10 @@ val _ = Define ` | Barrier_RISCV_r_r => "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w => "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w => "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw => "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r => "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w => "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r => "Barrier_RISCV_w_r" | Barrier_RISCV_i => "Barrier_RISCV_i" | Barrier_x86_MFENCE => "Barrier_x86_MFENCE" ))|>))`; @@ -228,7 +191,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<| +((instance_Show_Show_Sail2_instr_kinds_trans_kind_dict:(trans_kind)Show_class)= (<| show_method := (\x . (case x of @@ -244,16 +207,16 @@ val _ = Hol_datatype ` | IK_mem_read of read_kind | IK_mem_write of write_kind | IK_mem_rmw of (read_kind # write_kind) - | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + | IK_branch of unit(* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), indirect/computed-branch (single nia of kind NIA_indirect_address) and branch/jump (single nia of kind NIA_concrete_address) *) | IK_trans of trans_kind - | IK_simple`; + | IK_simple of unit`; val _ = Define ` -((instance_Show_Show_Sail_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<| +((instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict:(instruction_kind)Show_class)= (<| show_method := (\x . (case x of @@ -284,6 +247,14 @@ val _ = Define ` "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w => "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw => + "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r => + "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w => + "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r => + "Barrier_RISCV_w_r" | Barrier_RISCV_i => "Barrier_RISCV_i" | Barrier_x86_MFENCE => @@ -371,14 +342,14 @@ val _ = Define ` "Write_RISCV_conditional_strong_release" | Write_X86_locked => "Write_X86_locked" )) w)))) - | IK_branch => "IK_branch" + | IK_branch () => "IK_branch" | IK_trans trans_kind => STRCAT "IK_trans " (((\x . (case x of Transaction_start => "Transaction_start" | Transaction_commit => "Transaction_commit" | Transaction_abort => "Transaction_abort" )) trans_kind)) - | IK_simple => "IK_simple" + | IK_simple () => "IK_simple" ))|>))`; @@ -404,7 +375,7 @@ val _ = Define ` val _ = Define ` -((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<| +((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict:(read_kind)EnumerationType_class)= (<| toNat_method := (\x . (case x of @@ -424,7 +395,7 @@ val _ = Define ` val _ = Define ` -((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<| +((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict:(write_kind)EnumerationType_class)= (<| toNat_method := (\x . (case x of @@ -443,7 +414,7 @@ val _ = Define ` val _ = Define ` -((instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<| +((instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict:(barrier_kind)EnumerationType_class)= (<| toNat_method := (\x . (case x of @@ -465,8 +436,12 @@ val _ = Define ` | Barrier_RISCV_r_r =>( 15 : num) | Barrier_RISCV_rw_w =>( 16 : num) | Barrier_RISCV_w_w =>( 17 : num) - | Barrier_RISCV_i =>( 18 : num) - | Barrier_x86_MFENCE =>( 19 : num) + | Barrier_RISCV_w_rw =>( 18 : num) + | Barrier_RISCV_rw_r =>( 19 : num) + | Barrier_RISCV_r_w =>( 20 : num) + | Barrier_RISCV_w_r =>( 21 : num) + | Barrier_RISCV_i =>( 22 : num) + | Barrier_x86_MFENCE =>( 23 : num) ))|>))`; val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml index 78109827..c2c3a727 100644 --- a/snapshots/hol4/sail/lib/hol/sail_operatorsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_operatorsScript.sml @@ -1,29 +1,29 @@ -(*Generated by Lem from ../../src/gen_lib/sail_operators.lem.*) +(*Generated by Lem from ../../src/gen_lib/sail2_operators.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory; +open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory; val _ = numLib.prefer_num(); -val _ = new_theory "sail_operators" +val _ = new_theory "sail2_operators" (*open import Pervasives_extra*) (*open import Machine_word*) -(*open import Sail_values*) +(*open import Sail2_values*) (*** Bit vector operations *) (*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*) val _ = Define ` - ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r= ( - dict_Sail_values_Bitvector_a.bits_of_method l ++ dict_Sail_values_Bitvector_b.bits_of_method r))`; + ((concat_bv:'a Bitvector_class -> 'b Bitvector_class -> 'a -> 'b ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r= ( + dict_Sail2_values_Bitvector_a.bits_of_method l ++ dict_Sail2_values_Bitvector_b.bits_of_method r))`; (*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*) val _ = Define ` - ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a b v= (b :: - dict_Sail_values_Bitvector_a.bits_of_method v))`; + ((cons_bv:'a Bitvector_class -> bitU -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a b v= (b :: + dict_Sail2_values_Bitvector_a.bits_of_method v))`; (*val cast_unit_bv : bitU -> list bitU*) @@ -37,8 +37,8 @@ val _ = Define ` val _ = Define ` - ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail_values_Bitvector_a v= ((case - dict_Sail_values_Bitvector_a.bits_of_method v of + ((most_significant:'a Bitvector_class -> 'a -> bitU)dict_Sail2_values_Bitvector_a v= ((case + dict_Sail2_values_Bitvector_a.bits_of_method v of b :: _ => b | _ => B0 (* Treat empty bitvector as all zeros *) )))`; @@ -67,24 +67,24 @@ val _ = Define ` (*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) val _ = Define ` - ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail_values_Bitvector_a op sign l r= - (let r' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l r'))`; + ((arith_op_bv_int:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> int -> 'a)dict_Sail2_values_Bitvector_a op sign l r= + (let r' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r) in dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l r'))`; (*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) val _ = Define ` - ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail_values_Bitvector_a op sign l r= - (let l' = (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method r) l) in dict_Sail_values_Bitvector_a.arith_op_bv_method op sign l' r))`; + ((arith_op_int_bv:'a Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a)dict_Sail2_values_Bitvector_a op sign l r= + (let l' = (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method r) l) in dict_Sail2_values_Bitvector_a.arith_op_bv_method op sign l' r))`; val _ = Define ` - ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a op sign l r= (arith_op_bv_int - dict_Sail_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`; + ((arith_op_bv_bool:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a op sign l r= (arith_op_bv_int + dict_Sail2_values_Bitvector_a op sign l (if r then( 1 : int) else( 0 : int))))`; val _ = Define ` - ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool - dict_Sail_values_Bitvector_a op sign l) (bool_of_bitU r)))`; + ((arith_op_bv_bit:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a op sign l r= (OPTION_MAP (arith_op_bv_bool + dict_Sail2_values_Bitvector_a op sign l) (bool_of_bitU r)))`; (* TODO (or just omit and define it per spec if needed) @@ -163,8 +163,8 @@ val _ = Define ` (*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*) val _ = Define ` - ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a op v n= - (let v = (dict_Sail_values_Bitvector_a.bits_of_method v) in + ((shift_op_bv:'a Bitvector_class -> shift -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a op v n= + (let v = (dict_Sail2_values_Bitvector_a.bits_of_method v) in if n =( 0 : int) then v else let (op, n) = (if n >( 0 : int) then (op, n) else (invert_shift op, ~ n)) in (case op of @@ -174,8 +174,8 @@ val _ = Define ` repeat [B0] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int)) | RR_shift_arith => repeat [most_significant - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int)) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n ++ subrange_list T v(( 0 : int)) ((int_of_num (LENGTH v) - n) -( 1 : int)) | LL_rot => subrange_list T v n (int_of_num (LENGTH v) -( 1 : int)) ++ subrange_list T v(( 0 : int)) (n -( 1 : int)) | RR_rot => @@ -184,24 +184,24 @@ val _ = Define ` val _ = Define ` - ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv - dict_Sail_values_Bitvector_a LL_shift))`; + ((shiftl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv + dict_Sail2_values_Bitvector_a LL_shift))`; (*"<<"*) val _ = Define ` - ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv - dict_Sail_values_Bitvector_a RR_shift))`; + ((shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv + dict_Sail2_values_Bitvector_a RR_shift))`; (*">>"*) val _ = Define ` - ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv - dict_Sail_values_Bitvector_a RR_shift_arith))`; + ((arith_shiftr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv + dict_Sail2_values_Bitvector_a RR_shift_arith))`; val _ = Define ` - ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv - dict_Sail_values_Bitvector_a LL_rot))`; + ((rotl_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv + dict_Sail2_values_Bitvector_a LL_rot))`; (*"<<<"*) val _ = Define ` - ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a= (shift_op_bv - dict_Sail_values_Bitvector_a LL_rot))`; + ((rotr_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a= (shift_op_bv + dict_Sail2_values_Bitvector_a LL_rot))`; (*">>>"*) val _ = Define ` @@ -230,26 +230,26 @@ val _ = Define ` (*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*) val _ = Define ` - ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= + ((arith_op_bv_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> 'a -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r= (OPTION_BIND (int_of_bv - dict_Sail_values_Bitvector_a sign l) (\ l' . + dict_Sail2_values_Bitvector_a sign l) (\ l' . OPTION_BIND (int_of_bv - dict_Sail_values_Bitvector_a sign r) (\ r' . + dict_Sail2_values_Bitvector_a sign r) (\ r' . if r' =( 0 : int) then NONE else SOME ( - dict_Sail_values_Bitvector_b.of_int_method (dict_Sail_values_Bitvector_a.length_method l * size1) (op l' r'))))))`; + dict_Sail2_values_Bitvector_b.of_int_method (dict_Sail2_values_Bitvector_a.length_method l * size1) (op l' r'))))))`; val _ = Define ` - ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; + ((mod_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod F(( 1 : int))))`; val _ = Define ` - ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; + ((quot_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot F(( 1 : int))))`; val _ = Define ` - ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot T(( 1 : int))))`; + ((quots_bv:'a Bitvector_class -> 'b Bitvector_class -> 'b -> 'b -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot T(( 1 : int))))`; val _ = Define ` @@ -263,17 +263,17 @@ val _ = Define ` val _ = Define ` - ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l r= - (arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op sign size1 l (dict_Sail_values_Bitvector_a.of_int_method (dict_Sail_values_Bitvector_a.length_method l) r)))`; + ((arith_op_bv_int_no0:'a Bitvector_class -> 'b Bitvector_class ->(int -> int -> int) -> bool -> int -> 'a -> int -> 'b option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l r= + (arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op sign size1 l (dict_Sail2_values_Bitvector_a.of_int_method (dict_Sail2_values_Bitvector_a.length_method l) r)))`; val _ = Define ` - ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot F(( 1 : int))))`; + ((quot_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_int_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot F(( 1 : int))))`; val _ = Define ` - ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b= (arith_op_bv_int_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod F(( 1 : int))))`; + ((mod_bv_int:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> 'a option)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b= (arith_op_bv_int_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod F(( 1 : int))))`; val _ = Define ` @@ -287,41 +287,41 @@ val _ = Define ` val _ = Define ` - ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail_values_Bitvector_a v count1= (repeat ( - dict_Sail_values_Bitvector_a.bits_of_method v) count1))`; + ((replicate_bits_bv:'a Bitvector_class -> 'a -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v count1= (repeat ( + dict_Sail2_values_Bitvector_a.bits_of_method v) count1))`; val _ = Define ` - ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail_values_BitU_a bit len= (replicate_bits_bv - (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len))`; + ((duplicate_bit_bv:'a BitU_class -> 'a -> int ->(bitU)list)dict_Sail2_values_BitU_a bit len= (replicate_bits_bv + (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len))`; (*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) val _ = Define ` - ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= ( - dict_Sail_values_Bitvector_a.bits_of_method l = dict_Sail_values_Bitvector_a.bits_of_method r))`; + ((eq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r= ( + dict_Sail2_values_Bitvector_a.bits_of_method l = dict_Sail2_values_Bitvector_a.bits_of_method r))`; (*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) val _ = Define ` - ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail_values_Bitvector_a l r= (~ (eq_bv - dict_Sail_values_Bitvector_a l r)))`; + ((neq_bv:'a Bitvector_class -> 'a -> 'a -> bool)dict_Sail2_values_Bitvector_a l r= (~ (eq_bv + dict_Sail2_values_Bitvector_a l r)))`; (*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) val _ = Define ` - ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo= + ((get_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo= (let hi = ((lo + len) -( 1 : int)) in let bs = (bools_of_int (hi +( 1 : int)) n) in - dict_Sail_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`; + dict_Sail2_values_Bitvector_a.of_bools_method (subrange_list F bs hi lo)))`; (*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*) val _ = Define ` - ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail_values_Bitvector_a len n lo v= + ((set_slice_int_bv:'a Bitvector_class -> int -> int -> int -> 'a -> int)dict_Sail2_values_Bitvector_a len n lo v= (let hi = ((lo + len) -( 1 : int)) in let bs = (bits_of_int (hi +( 1 : int)) n) in maybe_failwith (signed_of_bits (update_subrange_list F bs hi lo ( - dict_Sail_values_Bitvector_a.bits_of_method v)))))`; + dict_Sail2_values_Bitvector_a.bits_of_method v)))))`; val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml new file mode 100644 index 00000000..e6b4da4f --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail2_operators_bitlistsScript.sml @@ -0,0 +1,769 @@ +(*Generated by Lem from ../../src/gen_lib/sail2_operators_bitlists.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail2_operators_bitlists" + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) + +(* Specialisation of operators to bit lists *) + +(*val uint_maybe : list bitU -> maybe integer*) +val _ = Define ` + ((uint_maybe0:(bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`; + +val _ = Define ` + ((uint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v= (sail2_state_monad$maybe_failS "uint" ( + dict_Sail2_values_Bitvector_a.unsigned_method v)))`; + +val _ = Define ` + ((uint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS + (sail2_state$bools_of_bits_nondetS v) (\ bs . + sail2_state_monad$returnS (int_of_bools F bs))))`; + +val _ = Define ` + ((uint:(bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`; + + +(*val sint_maybe : list bitU -> maybe integer*) +val _ = Define ` + ((sint_maybe0:(bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`; + +val _ = Define ` + ((sint_fail0:'a Bitvector_class -> 'a -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a v= (sail2_state_monad$maybe_failS "sint" ( + dict_Sail2_values_Bitvector_a.signed_method v)))`; + +val _ = Define ` + ((sint_nondet0:(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS + (sail2_state$bools_of_bits_nondetS v) (\ bs . + sail2_state_monad$returnS (int_of_bools T bs))))`; + +val _ = Define ` + ((sint:(bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`; + + +(*val extz_vec : integer -> list bitU -> list bitU*) +val _ = Define ` + ((extz_vec0:int ->(bitU)list ->(bitU)list)= + (extz_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val exts_vec : integer -> list bitU -> list bitU*) +val _ = Define ` + ((exts_vec0:int ->(bitU)list ->(bitU)list)= + (exts_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val zero_extend : list bitU -> integer -> list bitU*) +val _ = Define ` + ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len= (extz_bits len bits))`; + + +(*val sign_extend : list bitU -> integer -> list bitU*) +val _ = Define ` + ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len= (exts_bits len bits))`; + + +(*val zeros : integer -> list bitU*) +val _ = Define ` + ((zeros0:int ->(bitU)list) len= (repeat [B0] len))`; + + +(*val vector_truncate : list bitU -> integer -> list bitU*) +val _ = Define ` + ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len= (extz_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs))`; + + +(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) +(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_failwith : list bitU -> list bitU*) +(*val vec_of_bits : list bitU -> list bitU*) + +(*val access_vec_inc : list bitU -> integer -> bitU*) +val _ = Define ` + ((access_vec_inc0:(bitU)list -> int -> bitU)= + (access_bv_inc + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val access_vec_dec : list bitU -> integer -> bitU*) +val _ = Define ` + ((access_vec_dec0:(bitU)list -> int -> bitU)= + (access_bv_dec + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) +val _ = Define ` + ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)= + (update_bv_inc + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`; + +val _ = Define ` + ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_inc0 v i b)))`; + +val _ = Define ` + ((update_vec_inc_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_inc0 v i b)))`; + + +(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) +val _ = Define ` + ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)= + (update_bv_dec + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`; + +val _ = Define ` + ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_dec0 v i b)))`; + +val _ = Define ` + ((update_vec_dec_nondet0:(bitU)list -> int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) v i b= (sail2_state_monad$returnS (update_vec_dec0 v i b)))`; + + +(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) +val _ = Define ` + ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)= + (subrange_bv_inc + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) +val _ = Define ` + ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)= + (subrange_bv_dec + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) +val _ = Define ` + ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= + (update_subrange_bv_inc + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) +val _ = Define ` + ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= + (update_subrange_bv_dec + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val concat_vec : list bitU -> list bitU -> list bitU*) +val _ = Define ` + ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)= + (concat_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val cons_vec : bitU -> list bitU -> list bitU*) +val _ = Define ` + ((cons_vec0:bitU ->(bitU)list ->(bitU)list)= + (cons_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v= (SOME (cons_vec0 b v)))`; + +val _ = Define ` + ((cons_vec_fail0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v= (sail2_state_monad$returnS (cons_vec0 b v)))`; + +val _ = Define ` + ((cons_vec_nondet0:bitU ->(bitU)list -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b v= (sail2_state_monad$returnS (cons_vec0 b v)))`; + + +(*val cast_unit_vec : bitU -> list bitU*) +val _ = Define ` + ((cast_unit_vec0:bitU ->(bitU)list)= cast_unit_bv)`; + +val _ = Define ` + ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b= (SOME (cast_unit_vec0 b)))`; + +val _ = Define ` + ((cast_unit_vec_fail0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$returnS (cast_unit_vec0 b)))`; + +val _ = Define ` + ((cast_unit_vec_nondet0:bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$returnS (cast_unit_vec0 b)))`; + + +(*val vec_of_bit : integer -> bitU -> list bitU*) +val _ = Define ` + ((vec_of_bit0:int -> bitU ->(bitU)list)= bv_of_bit)`; + +val _ = Define ` + ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`; + +val _ = Define ` + ((vec_of_bit_fail0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$returnS (vec_of_bit0 len b)))`; + +val _ = Define ` + ((vec_of_bit_nondet0:int -> bitU -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$returnS (vec_of_bit0 len b)))`; + + +(*val msb : list bitU -> bitU*) +val _ = Define ` + ((msb0:(bitU)list -> bitU)= + (most_significant + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) +val _ = Define ` + ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)= + (int_of_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((int_of_vec_fail0:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v= (sail2_state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`; + +val _ = Define ` + ((int_of_vec_nondet:bool ->(bitU)list -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) sign v= (sail2_state_monad$bindS (sail2_state$bools_of_bits_nondetS v) (\ v . sail2_state_monad$returnS (int_of_bools sign v))))`; + +val _ = Define ` + ((int_of_vec0:bool ->(bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`; + + +(*val string_of_bits : list bitU -> string*) +val _ = Define ` + ((string_of_bits0:(bitU)list -> string)= + (string_of_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val and_vec : list bitU -> list bitU -> list bitU*) +(*val or_vec : list bitU -> list bitU -> list bitU*) +(*val xor_vec : list bitU -> list bitU -> list bitU*) +(*val not_vec : list bitU -> list bitU*) +val _ = Define ` + ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list and_bit))`; + +val _ = Define ` + ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list or_bit))`; + +val _ = Define ` + ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list xor_bit))`; + +val _ = Define ` + ((not_vec0:(bitU)list ->(bitU)list)= (MAP not_bit))`; + + +(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) +val _ = Define ` + ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a op sign l r= + (let len =(( 2 : int) * + dict_Sail2_values_Bitvector_a.length_method l) in + let l' = (if sign then exts_bv + dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in + let r' = (if sign then exts_bv + dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in + MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`; + + +(*val add_vec : list bitU -> list bitU -> list bitU*) +(*val adds_vec : list bitU -> list bitU -> list bitU*) +(*val sub_vec : list bitU -> list bitU -> list bitU*) +(*val subs_vec : list bitU -> list bitU -> list bitU*) +(*val mult_vec : list bitU -> list bitU -> list bitU*) +(*val mults_vec : list bitU -> list bitU -> list bitU*) +val _ = Define ` + ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; + +val _ = Define ` + ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F))`; + +val _ = Define ` + ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T))`; + + +(*val add_vec_int : list bitU -> integer -> list bitU*) +(*val adds_vec_int : list bitU -> integer -> list bitU*) +(*val sub_vec_int : list bitU -> integer -> list bitU*) +(*val subs_vec_int : list bitU -> integer -> list bitU*) +(*val mult_vec_int : list bitU -> integer -> list bitU*) +(*val mults_vec_int : list bitU -> integer -> list bitU*) +val _ = Define ` + ((add_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`; + +val _ = Define ` + ((adds_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`; + +val _ = Define ` + ((sub_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`; + +val _ = Define ` + ((subs_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`; + +val _ = Define ` + ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; + +val _ = Define ` + ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; + + +(*val add_int_vec : integer -> list bitU -> list bitU*) +(*val adds_int_vec : integer -> list bitU -> list bitU*) +(*val sub_int_vec : integer -> list bitU -> list bitU*) +(*val subs_int_vec : integer -> list bitU -> list bitU*) +(*val mult_int_vec : integer -> list bitU -> list bitU*) +(*val mults_int_vec : integer -> list bitU -> list bitU*) +val _ = Define ` + ((add_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) F l r))`; + +val _ = Define ` + ((adds_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (+) T l r))`; + +val _ = Define ` + ((sub_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) F l r))`; + +val _ = Define ` + ((subs_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (-) T l r))`; + +val _ = Define ` + ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; + +val _ = Define ` + ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; + + +(*val add_vec_bit : list bitU -> bitU -> list bitU*) +(*val adds_vec_bit : list bitU -> bitU -> list bitU*) +(*val sub_vec_bit : list bitU -> bitU -> list bitU*) +(*val subs_vec_bit : list bitU -> bitU -> list bitU*) + +val _ = Define ` + ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail2_values_Bitvector_a (+) F l r))`; + +val _ = Define ` + ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail2_values_Bitvector_a (+) F l r))`; + +val _ = Define ` + ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 + dict_Sail2_values_Bitvector_a l r)))`; + +val _ = Define ` + ((add_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (add_vec_bool0 + dict_Sail2_values_Bitvector_a l r))))`; + +val _ = Define ` + ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (add_vec_bit_maybe0 + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail2_values_Bitvector_a (+) T l r))`; + +val _ = Define ` + ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail2_values_Bitvector_a (+) T l r))`; + +val _ = Define ` + ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 + dict_Sail2_values_Bitvector_a l r)))`; + +val _ = Define ` + ((adds_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (adds_vec_bool0 + dict_Sail2_values_Bitvector_a l r))))`; + +val _ = Define ` + ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (adds_vec_bit_maybe0 + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail2_values_Bitvector_a (-) F l r))`; + +val _ = Define ` + ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail2_values_Bitvector_a (-) F l r))`; + +val _ = Define ` + ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 + dict_Sail2_values_Bitvector_a l r)))`; + +val _ = Define ` + ((sub_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (sub_vec_bool0 + dict_Sail2_values_Bitvector_a l r))))`; + +val _ = Define ` + ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (sub_vec_bit_maybe0 + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +val _ = Define ` + ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bool + dict_Sail2_values_Bitvector_a (-) T l r))`; + +val _ = Define ` + ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail2_values_Bitvector_a l r= (arith_op_bv_bit + dict_Sail2_values_Bitvector_a (-) T l r))`; + +val _ = Define ` + ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 + dict_Sail2_values_Bitvector_a l r)))`; + +val _ = Define ` + ((subs_vec_bit_nondet0:'a Bitvector_class -> 'a -> bitU -> 'c sail2_state_monad$sequential_state ->(('a,'d)sail2_state_monad$result#'c sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (subs_vec_bool0 + dict_Sail2_values_Bitvector_a l r))))`; + +val _ = Define ` + ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (subs_vec_bit_maybe0 + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + + +(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : list bitU -> integer -> list bitU*) +(*val shiftr : list bitU -> integer -> list bitU*) +(*val arith_shiftr : list bitU -> integer -> list bitU*) +(*val rotl : list bitU -> integer -> list bitU*) +(*val rotr : list bitU -> integer -> list bitU*) +val _ = Define ` + ((shiftl0:(bitU)list -> int ->(bitU)list)= + (shiftl_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((shiftr0:(bitU)list -> int ->(bitU)list)= + (shiftr_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((arith_shiftr0:(bitU)list -> int ->(bitU)list)= + (arith_shiftr_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((rotl0:(bitU)list -> int ->(bitU)list)= + (rotl_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((rotr0:(bitU)list -> int ->(bitU)list)= + (rotr_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val mod_vec : list bitU -> list bitU -> list bitU*) +(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +val _ = Define ` + ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (mod_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (mod_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`; + +val _ = Define ` + ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec" (mod_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`; + +val _ = Define ` + ((mod_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec0 l r)))`; + + +(*val quot_vec : list bitU -> list bitU -> list bitU*) +(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +val _ = Define ` + ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quot_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quot_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`; + +val _ = Define ` + ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec" (quot_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quot_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec0 l r)))`; + + +(*val quots_vec : list bitU -> list bitU -> list bitU*) +(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +val _ = Define ` + ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quots_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quots_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`; + +val _ = Define ` + ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quots_vec" (quots_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quots_vec_nondet0:(bitU)list ->(bitU)list -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec0 l r)))`; + + +(*val mod_vec_int : list bitU -> integer -> list bitU*) +(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +val _ = Define ` + ((mod_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (mod_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (mod_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`; + +val _ = Define ` + ((mod_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`; + +val _ = Define ` + ((mod_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int0 l r)))`; + + +(*val quot_vec_int : list bitU -> integer -> list bitU*) +(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +val _ = Define ` + ((quot_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (quot_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; + +val _ = Define ` + ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (quot_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))`; + +val _ = Define ` + ((quot_vec_int_fail0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r)))`; + +val _ = Define ` + ((quot_vec_int_nondet0:(bitU)list -> int -> 'rv sail2_state_monad$sequential_state ->((((bitU)list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state$of_bits_nondetS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int0 l r)))`; + + +(*val replicate_bits : list bitU -> integer -> list bitU*) +val _ = Define ` + ((replicate_bits0:(bitU)list -> int ->(bitU)list)= + (replicate_bits_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val duplicate : bitU -> integer -> list bitU*) +val _ = Define ` + ((duplicate0:bitU -> int ->(bitU)list)= + (duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict))`; + +val _ = Define ` + ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n= (SOME (duplicate0 b n)))`; + +val _ = Define ` + ((duplicate_fail0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$returnS (duplicate0 b n)))`; + +val _ = Define ` + ((duplicate_nondet0:bitU -> int -> 'a sail2_state_monad$sequential_state ->((((bitU)list),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS + (sail2_state$bool_of_bitU_nondetS b) (\ b . + sail2_state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`; + + +(*val reverse_endianness : list bitU -> list bitU*) +val _ = Define ` + ((reverse_endianness0:(bitU)list ->(bitU)list) v= (reverse_endianness_list v))`; + + +(*val get_slice_int : integer -> integer -> integer -> list bitU*) +val _ = Define ` + ((get_slice_int0:int -> int -> int ->(bitU)list)= + (get_slice_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) +val _ = Define ` + ((set_slice_int0:int -> int -> int ->(bitU)list -> int)= + (set_slice_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + + +(*val slice : list bitU -> integer -> integer -> list bitU*) +val _ = Define ` + ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len= + (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`; + + +(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*) +val _ = Define ` + ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v= + (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`; + + +(*val eq_vec : list bitU -> list bitU -> bool*) +(*val neq_vec : list bitU -> list bitU -> bool*) +val _ = Define ` + ((eq_vec:(bitU)list ->(bitU)list -> bool)= + (eq_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = Define ` + ((neq_vec:(bitU)list ->(bitU)list -> bool)= + (neq_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict)))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml index a35707f0..603daf57 100644 --- a/snapshots/hol4/sail/lib/hol/sail_operators_mwordsScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_operators_mwordsScript.sml @@ -1,87 +1,87 @@ -(*Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.*) +(*Generated by Lem from ../../src/gen_lib/sail2_operators_mwords.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory; +open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory sail2_operatorsTheory sail2_prompt_monadTheory sail2_promptTheory; val _ = numLib.prefer_num(); -val _ = new_theory "sail_operators_mwords" +val _ = new_theory "sail2_operators_mwords" (*open import Pervasives_extra*) (*open import Machine_word*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) val _ = Define ` ((uint_maybe:'a words$word ->(int)option) v= (SOME (lem$w2ui v)))`; val _ = Define ` - ((uint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (lem$w2ui v)))`; + ((uint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (lem$w2ui v)))`; val _ = Define ` - ((uint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (lem$w2ui v)))`; + ((uint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (lem$w2ui v)))`; val _ = Define ` ((sint_maybe:'a words$word ->(int)option) v= (SOME (integer_word$w2i v)))`; val _ = Define ` - ((sint_fail:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (integer_word$w2i v)))`; + ((sint_fail:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (integer_word$w2i v)))`; val _ = Define ` - ((sint_oracle:'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) v= (state_monad$returnS (integer_word$w2i v)))`; + ((sint_nondet:'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) v= (sail2_state_monad$returnS (integer_word$w2i v)))`; (*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*) (*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_nondet : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) (*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*) (*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*) val _ = Define ` ((vec_of_bits_maybe:(bitU)list ->('a words$word)option) bits= (OPTION_MAP bitstring$v2w (just_list (MAP bool_of_bitU bits))))`; val _ = Define ` - ((vec_of_bits_fail:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_failS - instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + ((vec_of_bits_fail:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits= (sail2_state$of_bits_failS + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` - ((vec_of_bits_oracle:(bitU)list -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) bits= (state$of_bits_oracleS - instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + ((vec_of_bits_nondet:(bitU)list -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) bits= (sail2_state$of_bits_nondetS + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` ((vec_of_bits_failwith:(bitU)list -> 'a words$word) bits= (of_bits_failwith - instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`; val _ = Define ` ((vec_of_bits:(bitU)list -> 'a words$word) bits= (of_bits_failwith - instance_Sail_values_Bitvector_Machine_word_mword_dict bits))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits))`; (*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) val _ = Define ` ((access_vec_inc:'a words$word -> int -> bitU)= - (access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + (access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; (*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) val _ = Define ` ((access_vec_dec:'a words$word -> int -> bitU)= - (access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + (access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; val _ = Define ` ((update_vec_dec_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_dec w i b))`; val _ = Define ` - ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS - (state$bool_of_bitU_fail b) (\ b . - state_monad$returnS (update_mword_bool_dec w i b))))`; + ((update_vec_dec_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS + (sail2_state$bool_of_bitU_fail b) (\ b . + sail2_state_monad$returnS (update_mword_bool_dec w i b))))`; val _ = Define ` - ((update_vec_dec_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS - (state$bool_of_bitU_oracleS b) (\ b . - state_monad$returnS (update_mword_bool_dec w i b))))`; + ((update_vec_dec_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS + (sail2_state$bool_of_bitU_nondetS b) (\ b . + sail2_state_monad$returnS (update_mword_bool_dec w i b))))`; val _ = Define ` ((update_vec_dec:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_dec_maybe w i b)))`; @@ -91,14 +91,14 @@ val _ = Define ` ((update_vec_inc_maybe:'a words$word -> int -> bitU ->('a words$word)option) w i b= (update_mword_inc w i b))`; val _ = Define ` - ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS - (state$bool_of_bitU_fail b) (\ b . - state_monad$returnS (update_mword_bool_inc w i b))))`; + ((update_vec_inc_fail:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS + (sail2_state$bool_of_bitU_fail b) (\ b . + sail2_state_monad$returnS (update_mword_bool_inc w i b))))`; val _ = Define ` - ((update_vec_inc_oracle:'a words$word -> int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) w i b= (state_monad$bindS - (state$bool_of_bitU_oracleS b) (\ b . - state_monad$returnS (update_mword_bool_inc w i b))))`; + ((update_vec_inc_nondet:'a words$word -> int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) w i b= (sail2_state_monad$bindS + (sail2_state$bool_of_bitU_nondetS b) (\ b . + sail2_state_monad$returnS (update_mword_bool_inc w i b))))`; val _ = Define ` ((update_vec_inc:'a words$word -> int -> bitU -> 'a words$word) w i b= (maybe_failwith (update_vec_inc_maybe w i b)))`; @@ -167,10 +167,10 @@ val _ = Define ` ((cons_vec_maybe:bitU -> 'c words$word ->('b words$word)option) b w= (OPTION_MAP (\ b . cons_vec_bool b w) (bool_of_bitU b)))`; val _ = Define ` - ((cons_vec_fail:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + ((cons_vec_fail:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (cons_vec_bool b w))))`; val _ = Define ` - ((cons_vec_oracle:bitU -> 'c words$word -> 'd state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'d state_monad$sequential_state)set) b w= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cons_vec_bool b w))))`; + ((cons_vec_nondet:bitU -> 'c words$word -> 'd sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set) b w= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (cons_vec_bool b w))))`; val _ = Define ` ((cons_vec:bitU -> 'a words$word -> 'b words$word) b w= (maybe_failwith (cons_vec_maybe b w)))`; @@ -184,10 +184,10 @@ val _ = Define ` ((vec_of_bit_maybe:int -> bitU ->('a words$word)option) len b= (OPTION_MAP (vec_of_bool len) (bool_of_bitU b)))`; val _ = Define ` - ((vec_of_bit_fail:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + ((vec_of_bit_fail:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (vec_of_bool len b))))`; val _ = Define ` - ((vec_of_bit_oracle:int -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) len b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (vec_of_bool len b))))`; + ((vec_of_bit_nondet:int -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) len b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (vec_of_bool len b))))`; val _ = Define ` ((vec_of_bit:int -> bitU -> 'a words$word) len b= (maybe_failwith (vec_of_bit_maybe len b)))`; @@ -201,10 +201,10 @@ val _ = Define ` ((cast_unit_vec_maybe:bitU ->('a words$word)option) b= (vec_of_bit_maybe(( 1 : int)) b))`; val _ = Define ` - ((cast_unit_vec_fail:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + ((cast_unit_vec_fail:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (cast_bool_vec b))))`; val _ = Define ` - ((cast_unit_vec_oracle:bitU -> 'a state_monad$sequential_state ->((((1)words$word),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (cast_bool_vec b))))`; + ((cast_unit_vec_nondet:bitU -> 'a sail2_state_monad$sequential_state ->((((1)words$word),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) b= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (cast_bool_vec b))))`; val _ = Define ` ((cast_unit_vec:bitU -> 'a words$word) b= (maybe_failwith (cast_unit_vec_maybe b)))`; @@ -213,7 +213,7 @@ val _ = Define ` (*val msb : forall 'a. Size 'a => mword 'a -> bitU*) val _ = Define ` ((msb:'a words$word -> bitU)= - (most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + (most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; (*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*) @@ -227,13 +227,13 @@ val _ = Define ` ((int_of_vec_maybe:bool -> 'a words$word ->(int)option) sign w= (SOME (int_of_vec sign w)))`; val _ = Define ` - ((int_of_vec_fail:bool -> 'a words$word -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set) sign w= (state_monad$returnS (int_of_vec sign w)))`; + ((int_of_vec_fail:bool -> 'a words$word -> 'b sail2_state_monad$sequential_state ->(((int),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) sign w= (sail2_state_monad$returnS (int_of_vec sign w)))`; -(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) +(*val string_of_bits : forall 'a. Size 'a => mword 'a -> string*) val _ = Define ` - ((string_of_vec:'a words$word -> string)= - (string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + ((string_of_bits:'a words$word -> string)= + (string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; (*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) @@ -286,27 +286,27 @@ val _ = Define ` (*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) val _ = Define ` ((add_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`; val _ = Define ` ((adds_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) T l r))`; val _ = Define ` ((sub_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`; val _ = Define ` ((subs_vec_int:'a words$word -> int -> 'a words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T l r))`; val _ = Define ` ((mult_vec_int:'a words$word -> int -> 'b words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) F (words$w2w l : 'b words$word) r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) F (words$w2w l : 'b words$word) r))`; val _ = Define ` ((mults_vec_int:'a words$word -> int -> 'b words$word) l r= (arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T (words$sw2sw l : 'b words$word) r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) T (words$sw2sw l : 'b words$word) r))`; (*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) @@ -317,27 +317,27 @@ val _ = Define ` (*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) val _ = Define ` ((add_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`; val _ = Define ` ((adds_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) T l r))`; val _ = Define ` ((sub_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`; val _ = Define ` ((subs_int_vec:int -> 'a words$word -> 'a words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T l r))`; val _ = Define ` ((mult_int_vec:int -> 'a words$word -> 'b words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) F l (words$w2w r : 'b words$word)))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) F l (words$w2w r : 'b words$word)))`; val _ = Define ` ((mults_int_vec:int -> 'a words$word -> 'b words$word) l r= (arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict ( * ) T l (words$sw2sw r : 'b words$word)))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict ( * ) T l (words$sw2sw r : 'b words$word)))`; (*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) @@ -347,16 +347,16 @@ val _ = Define ` val _ = Define ` ((add_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) F l r))`; val _ = Define ` ((add_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (add_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((add_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + ((add_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (add_vec_bool l r))))`; val _ = Define ` - ((add_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool l r))))`; + ((add_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (add_vec_bool l r))))`; val _ = Define ` ((add_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (add_vec_bit_maybe l r)))`; @@ -364,16 +364,16 @@ val _ = Define ` val _ = Define ` ((adds_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (+) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (+) T l r))`; val _ = Define ` ((adds_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (adds_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((adds_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + ((adds_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (adds_vec_bool l r))))`; val _ = Define ` - ((adds_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool l r))))`; + ((adds_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (adds_vec_bool l r))))`; val _ = Define ` ((adds_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (adds_vec_bit_maybe l r)))`; @@ -381,16 +381,16 @@ val _ = Define ` val _ = Define ` ((sub_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) F l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) F l r))`; val _ = Define ` ((sub_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (sub_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((sub_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + ((sub_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (sub_vec_bool l r))))`; val _ = Define ` - ((sub_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool l r))))`; + ((sub_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (sub_vec_bool l r))))`; val _ = Define ` ((sub_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (sub_vec_bit_maybe l r)))`; @@ -398,16 +398,16 @@ val _ = Define ` val _ = Define ` ((subs_vec_bool:'a words$word -> bool -> 'a words$word) l r= (arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (-) T l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict (-) T l r))`; val _ = Define ` ((subs_vec_bit_maybe:'a words$word -> bitU ->('a words$word)option) l r= (OPTION_MAP (subs_vec_bool l) (bool_of_bitU r)))`; val _ = Define ` - ((subs_vec_bit_fail:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_fail r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + ((subs_vec_bit_fail:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail r) (\ r . sail2_state_monad$returnS (subs_vec_bool l r))))`; val _ = Define ` - ((subs_vec_bit_oracle:'a words$word -> bitU -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool l r))))`; + ((subs_vec_bit_nondet:'a words$word -> bitU -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS r) (\ r . sail2_state_monad$returnS (subs_vec_bool l r))))`; val _ = Define ` ((subs_vec_bit:'a words$word -> bitU -> 'a words$word) l r= (maybe_failwith (subs_vec_bit_maybe l r)))`; @@ -464,117 +464,117 @@ val _ = Define ` (*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((mod_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (mod_mword l r))`; val _ = Define ` ((mod_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (mod_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`; val _ = Define ` - ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + ((mod_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec" (mod_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((mod_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of - SOME w => state_monad$returnS w - | NONE => state$mword_oracleS () + ((mod_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= + ((case (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => sail2_state_monad$returnS w + | NONE => sail2_state$mword_nondetS () )))`; (*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quot_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quot_mword l r))`; val _ = Define ` ((quot_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quot_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`; val _ = Define ` - ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + ((quot_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec" (quot_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quot_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of - SOME w => state_monad$returnS w - | NONE => state$mword_oracleS () + ((quot_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= + ((case (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => sail2_state_monad$returnS w + | NONE => sail2_state$mword_nondetS () )))`; (*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quots_vec:'a words$word -> 'a words$word -> 'a words$word) l r= (quots_mword l r))`; val _ = Define ` ((quots_vec_maybe:'a words$word -> 'a words$word ->('a words$word)option) l r= (quots_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`; val _ = Define ` - ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + ((quots_vec_fail:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quots_vec" (quots_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quots_vec_oracle:'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= - ((case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of - SOME w => state_monad$returnS w - | NONE => state$mword_oracleS () + ((quots_vec_nondet:'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= + ((case (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => sail2_state_monad$returnS w + | NONE => sail2_state$mword_nondetS () )))`; (*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) (*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) (*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((mod_vec_int:'a words$word -> int -> 'a words$word) l r= (mod_mword_int l r))`; val _ = Define ` ((mod_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (mod_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`; val _ = Define ` - ((mod_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + ((mod_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "mod_vec_int" (mod_bv_int + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((mod_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((mod_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= ((case (mod_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of - SOME w => state_monad$returnS w - | NONE => state$mword_oracleS () + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => sail2_state_monad$returnS w + | NONE => sail2_state$mword_nondetS () )))`; (*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) (*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) (*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) val _ = Define ` ((quot_vec_int:'a words$word -> int -> 'a words$word) l r= (quot_mword_int l r))`; val _ = Define ` ((quot_vec_int_maybe:'a words$word -> int ->('a words$word)option) l r= (quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))`; + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))`; val _ = Define ` - ((quot_vec_int_fail:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r)))`; + ((quot_vec_int_fail:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= (sail2_state_monad$maybe_failS "quot_vec_int" (quot_bv_int + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r)))`; val _ = Define ` - ((quot_vec_int_oracle:'a words$word -> int -> 'rv state_monad$sequential_state ->((('a words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= + ((quot_vec_int_nondet:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->((('a words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) l r= ((case (quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of - SOME w => state_monad$returnS w - | NONE => state$mword_oracleS () + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of + SOME w => sail2_state_monad$returnS w + | NONE => sail2_state$mword_nondetS () )))`; @@ -591,10 +591,10 @@ val _ = Define ` ((duplicate_maybe:bitU -> int ->('a words$word)option) b n= (OPTION_MAP (\ b . duplicate_bool b n) (bool_of_bitU b)))`; val _ = Define ` - ((duplicate_fail:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_fail b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + ((duplicate_fail:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_fail b) (\ b . sail2_state_monad$returnS (duplicate_bool b n))))`; val _ = Define ` - ((duplicate_oracle:bitU -> int -> 'b state_monad$sequential_state ->((('a words$word),'c)state_monad$result#'b state_monad$sequential_state)set) b n= (state_monad$bindS (state$bool_of_bitU_oracleS b) (\ b . state_monad$returnS (duplicate_bool b n))))`; + ((duplicate_nondet:bitU -> int -> 'b sail2_state_monad$sequential_state ->((('a words$word),'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) b n= (sail2_state_monad$bindS (sail2_state$bool_of_bitU_nondetS b) (\ b . sail2_state_monad$returnS (duplicate_bool b n))))`; val _ = Define ` ((duplicate:bitU -> int -> 'a words$word) b n= (maybe_failwith (duplicate_maybe b n)))`; @@ -608,13 +608,13 @@ val _ = Define ` (*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) val _ = Define ` ((get_slice_int:int -> int -> int -> 'a words$word)= - (get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + (get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; (*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) val _ = Define ` ((set_slice_int:int -> int -> int -> 'a words$word -> int)= - (set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict))`; + (set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict))`; (*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) diff --git a/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml b/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml new file mode 100644 index 00000000..629c9028 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail2_promptScript.sml @@ -0,0 +1,15 @@ +(*Generated by Lem from sail2_prompt.lem.*) +open HolKernel Parse boolLib bossLib; +open sail2_prompt_monadTheory sail2_state_monadTheory sail2_stateTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail2_prompt" + +(*open import Sail2_prompt_monad*) +(*open import Sail2_state_monad*) +(*open import Sail2_state*) +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml b/snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml index 7c18567b..c6d6bc44 100644 --- a/snapshots/hol4/sail/lib/hol/prompt_monadScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_prompt_monadScript.sml @@ -1,17 +1,17 @@ -(*Generated by Lem from prompt_monad.lem.*) +(*Generated by Lem from sail2_prompt_monad.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory state_monadTheory; +open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory sail2_state_monadTheory; val _ = numLib.prefer_num(); -val _ = new_theory "prompt_monad" +val _ = new_theory "sail2_prompt_monad" (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import State_monad*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_state_monad*) (* Fake interface of the prompt monad by redirecting to the state monad, since the former is not currently supported by HOL4 *) diff --git a/snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml index c8269750..4d70b033 100644 --- a/snapshots/hol4/sail/lib/hol/stateAuxiliaryScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_stateAuxiliaryScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from ../../src/gen_lib/state.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory stateTheory; +open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory sail2_stateTheory; val _ = numLib.prefer_num(); @@ -8,7 +8,7 @@ val _ = numLib.prefer_num(); open lemLib; (* val _ = lemLib.run_interactive := true; *) -val _ = new_theory "stateAuxiliary" +val _ = new_theory "sail2_stateAuxiliary" (****************************************************) diff --git a/snapshots/hol4/sail/lib/hol/stateScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stateScript.sml index ec3e6c26..dfe0cd7d 100644 --- a/snapshots/hol4/sail/lib/hol/stateScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_stateScript.sml @@ -1,17 +1,17 @@ -(*Generated by Lem from ../../src/gen_lib/state.lem.*) +(*Generated by Lem from ../../src/gen_lib/sail2_state.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_valuesTheory state_monadTheory; +open lem_pervasives_extraTheory sail2_valuesTheory sail2_state_monadTheory; val _ = numLib.prefer_num(); -val _ = new_theory "state" +val _ = new_theory "sail2_state" (*open import Pervasives_extra*) -(*open import Sail_values*) -(*open import State_monad*) -(*open import {isabelle} `State_monad_lemmas`*) +(*open import Sail2_values*) +(*open import Sail2_state_monad*) +(*open import {isabelle} `Sail2_state_monad_lemmas`*) (*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) val iterS_aux_defn = Hol_defn "iterS_aux" ` @@ -65,9 +65,9 @@ val _ = Define ` )))`; -(*val bool_of_bitU_oracleS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) +(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) val _ = Define ` - ((bool_of_bitU_oracleS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= + ((bool_of_bitU_nondetS:bitU -> 'rv sequential_state ->(((bool),'e)result#'rv sequential_state)set)= (\x . (case x of B0 => returnS F | B1 => returnS T @@ -75,32 +75,32 @@ val _ = Define ` )))`; -(*val bools_of_bits_oracleS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*) +(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*) val _ = Define ` - ((bools_of_bits_oracleS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits= + ((bools_of_bits_nondetS:(bitU)list -> 'rv sequential_state ->((((bool)list),'e)result#'rv sequential_state)set) bits= (foreachS bits [] (\ b bools . bindS - (bool_of_bitU_oracleS b) (\ b . + (bool_of_bitU_nondetS b) (\ b . returnS (bools ++ [b])))))`; -(*val of_bits_oracleS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) +(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) val _ = Define ` - ((of_bits_oracleS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits= (bindS - (bools_of_bits_oracleS bits) (\ bs . - returnS (dict_Sail_values_Bitvector_a.of_bools_method bs))))`; + ((of_bits_nondetS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits= (bindS + (bools_of_bits_nondetS bits) (\ bs . + returnS (dict_Sail2_values_Bitvector_a.of_bools_method bs))))`; (*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) val _ = Define ` - ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail_values_Bitvector_a bits= (maybe_failS "of_bits" ( - dict_Sail_values_Bitvector_a.of_bits_method bits)))`; + ((of_bits_failS:'a Bitvector_class ->(bitU)list ->('rv,'a,'e)monadS)dict_Sail2_values_Bitvector_a bits= (maybe_failS "of_bits" ( + dict_Sail2_values_Bitvector_a.of_bits_method bits)))`; -(*val mword_oracleS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*) +(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*) val _ = Define ` - ((mword_oracleS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () = (bindS - (bools_of_bits_oracleS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . + ((mword_nondetS:unit -> 'rv sequential_state ->((('a words$word),'e)result#'rv sequential_state)set) () = (bindS + (bools_of_bits_nondetS (repeat [BU] (int_of_num (dimindex (the_value : 'a itself))))) (\ bs . returnS (bitstring$v2w bs))))`; @@ -125,5 +125,17 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn untilS_defn; + +(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*) +val _ = Define ` + ((internal_pickS:'a list -> 'rv sequential_state ->(('a,'e)result#'rv sequential_state)set) xs= (bindS + ( + (* Use sufficiently many undefined bits and convert into an index into the list *)bools_of_bits_nondetS (repeat [BU] (int_of_num (LENGTH xs)))) (\ bs . + let idx = ((((nat_of_bools bs):num)) MOD LENGTH xs) in + (case list_index xs idx of + SOME x => returnS x + | NONE => failS "internal_pick" + ))))`; + val _ = export_theory() diff --git a/snapshots/hol4/sail/lib/hol/state_monadScript.sml b/snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml index ba687761..c3e3603d 100644 --- a/snapshots/hol4/sail/lib/hol/state_monadScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_state_monadScript.sml @@ -1,16 +1,16 @@ -(*Generated by Lem from ../../src/gen_lib/state_monad.lem.*) +(*Generated by Lem from ../../src/gen_lib/sail2_state_monad.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_valuesTheory sail_instr_kindsTheory; +open lem_pervasives_extraTheory sail2_valuesTheory sail2_instr_kindsTheory; val _ = numLib.prefer_num(); -val _ = new_theory "state_monad" +val _ = new_theory "sail2_state_monad" (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) (* 'a is result type *) @@ -24,22 +24,17 @@ val _ = Hol_datatype ` memstate : memstate; tagstate : tagstate; write_ea : (write_kind # int # int)option; - last_exclusive_operation_was_load : bool; - (* Random bool generator for use as an undefined bit oracle *) - next_bool : num -> (bool # num); - seed : num |>`; + last_exclusive_operation_was_load : bool |>`; -(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) +(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*) val _ = Define ` - ((init_state:'regs ->(num -> bool#num) -> num -> 'regs sequential_state) regs o1 s= + ((init_state:'regs -> 'regs sequential_state) regs= (<| regstate := regs; memstate := FEMPTY; tagstate := FEMPTY; write_ea := NONE; - last_exclusive_operation_was_load := F; - next_bool := o1; - seed := s |>))`; + last_exclusive_operation_was_load := F |>))`; val _ = Hol_datatype ` @@ -98,10 +93,7 @@ val _ = Define ` (*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) val _ = Define ` - ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (bindS - (readS (\ s . s.next_bool (s.seed))) (\ (b, seed) . seqS - (updateS (\ s . ( s with<| seed := seed |>))) - (returnS b))))`; + ((undefined_boolS:unit -> 'regs sequential_state ->(((bool),'e)result#'regs sequential_state)set) () = (chooseS {F; T}))`; (*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) @@ -169,18 +161,18 @@ val _ = Define ` (*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*) val _ = Define ` - ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail_values_Bitvector_a addr= (bindS + ((read_tagS:'a Bitvector_class -> 'a ->('regs,(bitU),'e)monadS)dict_Sail2_values_Bitvector_a addr= (bindS (maybe_failS "unsigned" ( - dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . readS (\ s . option_CASE (FLOOKUP s.tagstate addr) B0 I))))`; (* Read bytes from memory and return in little endian order *) (*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*) val _ = Define ` - ((read_mem_bytesS:'a Bitvector_class -> read_kind -> 'a -> num ->('regs,((memory_byte)list),'e)monadS)dict_Sail_values_Bitvector_a read_kind addr sz= (bindS + ((read_mem_bytesS:'a Bitvector_class -> read_kind -> 'a -> num ->('regs,((memory_byte)list),'e)monadS)dict_Sail2_values_Bitvector_a read_kind addr sz= (bindS (maybe_failS "unsigned" ( - dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . let sz = (int_of_num sz) in let addrs = (index_list addr ((addr+sz)-( 1 : int))(( 1 : int))) in let read_byte = (\ s addr . FLOOKUP s.memstate addr) in @@ -198,10 +190,10 @@ val _ = Define ` (*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*) val _ = Define ` - ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz= (bindS - (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . + ((read_memS:'a Bitvector_class -> 'b Bitvector_class -> read_kind -> 'a -> int ->('regs,'b,'e)monadS)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz= (bindS + (read_mem_bytesS dict_Sail2_values_Bitvector_a rk a (nat_of_int sz)) (\ bytes . maybe_failS "bits_of_mem_bytes" ( - dict_Sail_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`; + dict_Sail2_values_Bitvector_b.of_bits_method (bits_of_mem_bytes bytes)))))`; (*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) @@ -214,9 +206,9 @@ val _ = Define ` (*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*) val _ = Define ` - ((write_mem_eaS:'a Bitvector_class -> write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail_values_Bitvector_a write_kind addr sz= (bindS + ((write_mem_eaS:'a Bitvector_class -> write_kind -> 'a -> num ->('regs,(unit),'e)monadS)dict_Sail2_values_Bitvector_a write_kind addr sz= (bindS (maybe_failS "unsigned" ( - dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . + dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . let sz = (int_of_num sz) in updateS (\ s . ( s with<| write_ea := (SOME (write_kind, addr, sz)) |>)))))`; @@ -245,8 +237,8 @@ val _ = Define ` (*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) val _ = Define ` - ((write_mem_valS:'a Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a v= ((case mem_bytes_of_bits - dict_Sail_values_Bitvector_a v of + ((write_mem_valS:'a Bitvector_class -> 'a ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a v= ((case mem_bytes_of_bits + dict_Sail2_values_Bitvector_a v of SOME v => write_mem_bytesS v | NONE => failS "write_mem_val" )))`; @@ -254,9 +246,9 @@ val _ = Define ` (*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*) val _ = Define ` - ((write_tagS:'a Bitvector_class -> 'a -> bitU ->('regs,(bool),'e)monadS)dict_Sail_values_Bitvector_a addr t= (bindS + ((write_tagS:'a Bitvector_class -> 'a -> bitU ->('regs,(bool),'e)monadS)dict_Sail2_values_Bitvector_a addr t= (bindS (maybe_failS "unsigned" ( - dict_Sail_values_Bitvector_a.unsigned_method addr)) (\ addr . seqS + dict_Sail2_values_Bitvector_a.unsigned_method addr)) (\ addr . seqS (updateS (\ s . ( s with<| tagstate := (s.tagstate |+ (addr, t)) |>))) (returnS T))))`; diff --git a/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml b/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml new file mode 100644 index 00000000..dc1cba63 --- /dev/null +++ b/snapshots/hol4/sail/lib/hol/sail2_stringScript.sml @@ -0,0 +1,215 @@ +(*Generated by Lem from ../../src/gen_lib/sail2_string.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_listTheory sail2_valuesTheory sail2_operatorsTheory lem_list_extraTheory lem_stringTheory lem_string_extraTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "sail2_string" + +(*open import Pervasives*) +(*open import List*) +(*open import List_extra*) +(*open import String*) +(*open import String_extra*) + +(*open import Sail2_operators*) +(*open import Sail2_values*) + +(*val string_sub : string -> ii -> ii -> string*) +val _ = Define ` + ((string_sub:string -> int -> int -> string) str start len= + (IMPLODE (TAKE (Num (ABS (I len))) (DROP (Num (ABS (I start))) (EXPLODE str)))))`; + + +(*val string_startswith : string -> string -> bool*) +val _ = Define ` + ((string_startswith:string -> string -> bool) str1 str2= + (let prefix = (string_sub str1(( 0 : int)) (int_of_num (STRLEN str2))) in + (prefix = str2)))`; + + +(*val string_drop : string -> ii -> string*) +val _ = Define ` + ((string_drop:string -> int -> string) str n= + (IMPLODE (DROP (Num (ABS (I n))) (EXPLODE str))))`; + + +(*val string_length : string -> ii*) +val _ = Define ` + ((string_length:string -> int) s= (int_of_num (STRLEN s)))`; + + +val _ = Define ` + ((string_append:string -> string -> string)= STRCAT)`; + + +(*********************************************** + * Begin stuff that should be in Lem Num_extra * + ***********************************************) + +(*val maybeIntegerOfString : string -> maybe integer*) +val _ = Define ` + ((maybeIntegerOfString:string ->(int)option) _= NONE)`; + + +(*********************************************** + * end stuff that should be in Lem Num_extra * + ***********************************************) + + val maybe_int_of_prefix_defn = Hol_defn "maybe_int_of_prefix" ` + ((maybe_int_of_prefix:string ->(int#int)option) s= + ((case s of + "" => NONE + | str => + let len = (string_length str) in + (case maybeIntegerOfString str of + SOME n => SOME (n, len) + | NONE => maybe_int_of_prefix (string_sub str(( 0 : int)) (len -( 1 : int))) + ) + )))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn maybe_int_of_prefix_defn; + +val _ = Define ` + ((maybe_int_of_string:string ->(int)option)= maybeIntegerOfString)`; + + +(*val n_leading_spaces : string -> ii*) + val n_leading_spaces_defn = Hol_defn "n_leading_spaces" ` + ((n_leading_spaces:string -> int) s= + (let len = (string_length s) in + if len =( 0 : int) then( 0 : int) else + if len =( 1 : int) then + (case s of + " " =>( 1 : int) + | _ =>( 0 : int) + ) + else + (* match len with + * (\* | 0 -> 0 *\) + * (\* | 1 -> *\) + * | len -> *) + (* Isabelle generation for pattern matching on characters + is currently broken, so use an if-expression *) + if SUB (s, (( 0 : num))) = #" " + then( 1 : int) + (n_leading_spaces (string_sub s(( 1 : int)) (len -( 1 : int)))) + else( 0 : int)))`; + +val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn n_leading_spaces_defn; + (* end *) + +val _ = Define ` + ((opt_spc_matches_prefix:string ->(unit#int)option) s= + (SOME (() , n_leading_spaces s)))`; + + +val _ = Define ` + ((spc_matches_prefix:string ->(unit#int)option) s= + (let n = (n_leading_spaces s) in + (* match n with *) +(* | 0 -> Nothing *) + if n =( 0 : int) then NONE else + (* | n -> *) SOME (() , n)))`; + + (* end *) + +val _ = Define ` + ((hex_bits_5_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 32 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 5 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_6_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 64 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 6 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_12_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 4096 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 12 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_13_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 8192 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 13 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_16_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 65536 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 16 : int)) n, len)) + else + NONE + )))`; + + + +val _ = Define ` + ((hex_bits_20_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 1048576 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 20 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_21_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 2097152 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 21 : int)) n, len)) + else + NONE + )))`; + + +val _ = Define ` + ((hex_bits_32_matches_prefix:'a Bitvector_class -> string ->('a#int)option)dict_Sail2_values_Bitvector_a s= + ((case maybe_int_of_prefix s of + NONE => NONE + | SOME (n, len) => + if(( 0 : int) <= n) /\ (n <( 4294967296 : int)) then + SOME ((dict_Sail2_values_Bitvector_a.of_int_method(( 2147483648 : int)) n, len)) + else + NONE + )))`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml b/snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml index aa169979..b475c5ea 100644 --- a/snapshots/hol4/sail/lib/hol/sail_valuesAuxiliaryScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_valuesAuxiliaryScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from ../../src/gen_lib/sail_values.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory; +open lem_pervasives_extraTheory lem_machine_wordTheory sail2_valuesTheory; open intLib; val _ = numLib.prefer_num(); @@ -9,7 +9,7 @@ val _ = numLib.prefer_num(); open lemLib; (* val _ = lemLib.run_interactive := true; *) -val _ = new_theory "sail_valuesAuxiliary" +val _ = new_theory "sail2_valuesAuxiliary" (****************************************************) diff --git a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml b/snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml index f178a336..1d6293df 100644 --- a/snapshots/hol4/sail/lib/hol/sail_valuesScript.sml +++ b/snapshots/hol4/sail/lib/hol/sail2_valuesScript.sml @@ -1,4 +1,4 @@ -(*Generated by Lem from ../../src/gen_lib/sail_values.lem.*) +(*Generated by Lem from ../../src/gen_lib/sail2_values.lem.*) open HolKernel Parse boolLib bossLib; open lem_pervasives_extraTheory lem_machine_wordTheory; @@ -6,7 +6,7 @@ val _ = numLib.prefer_num(); -val _ = new_theory "sail_values" +val _ = new_theory "sail2_values" (*open import Pervasives_extra*) (*open import Machine_word*) @@ -54,14 +54,29 @@ let negate_real r = realNegate r let abs_real r = realAbs r let power_real b e = realPowInteger b e*) +(*val print_endline : string -> unit*) +val _ = Define ` + ((print_endline:string -> unit) _= () )`; + +(* declare ocaml target_rep function print_endline = `print_endline` *) + (*val prerr_endline : string -> unit*) val _ = Define ` ((prerr_endline:string -> unit) _= () )`; +val _ = Define ` + ((prerr:string -> unit) x= (prerr_endline x))`; + + (*val print_int : string -> integer -> unit*) val _ = Define ` - ((print_int:string -> int -> unit) msg i= (prerr_endline ( STRCAT msg (stringFromInteger i))))`; + ((print_int:string -> int -> unit) msg i= (print_endline ( STRCAT msg (stringFromInteger i))))`; + + +(*val prerr_int : string -> integer -> unit*) +val _ = Define ` + ((prerr_int:string -> int -> unit) msg i= (prerr_endline ( STRCAT msg (stringFromInteger i))))`; (*val putchar : integer -> unit*) @@ -200,7 +215,7 @@ val _ = Define ` val _ = Define ` -((instance_Show_Show_Sail_values_bitU_dict:(bitU)Show_class)= (<| +((instance_Show_Show_Sail2_values_bitU_dict:(bitU)Show_class)= (<| show_method := showBitU|>))`; @@ -219,7 +234,7 @@ val _ = Define ` val _ = Define ` -((instance_Basic_classes_Ord_Sail_values_bitU_dict:(bitU)Ord_class)= (<| +((instance_Basic_classes_Ord_Sail2_values_bitU_dict:(bitU)Ord_class)= (<| compare_method := compare_bitU; @@ -240,7 +255,7 @@ val _ = Hol_datatype ` val _ = Define ` -((instance_Sail_values_BitU_Sail_values_bitU_dict:(bitU)BitU_class)= (<| +((instance_Sail2_values_BitU_Sail2_values_bitU_dict:(bitU)BitU_class)= (<| to_bitU_method := (\ b. b); @@ -751,45 +766,45 @@ val _ = Hol_datatype ` (*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*) val _ = Define ` - ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail_values_Bitvector_a bits= (maybe_failwith ( - dict_Sail_values_Bitvector_a.of_bits_method bits)))`; + ((of_bits_failwith:'a Bitvector_class ->(bitU)list -> 'a)dict_Sail2_values_Bitvector_a bits= (maybe_failwith ( + dict_Sail2_values_Bitvector_a.of_bits_method bits)))`; val _ = Define ` - ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail_values_Bitvector_a sign= (if sign then - dict_Sail_values_Bitvector_a.signed_method else dict_Sail_values_Bitvector_a.unsigned_method))`; + ((int_of_bv:'a Bitvector_class -> bool -> 'a ->(int)option)dict_Sail2_values_Bitvector_a sign= (if sign then + dict_Sail2_values_Bitvector_a.signed_method else dict_Sail2_values_Bitvector_a.unsigned_method))`; val _ = Define ` -((instance_Sail_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail_values_BitU_a= (<| +((instance_Sail2_values_Bitvector_list_dict:'a BitU_class ->('a list)Bitvector_class)dict_Sail2_values_BitU_a= (<| bits_of_method := (\ v. MAP - dict_Sail_values_BitU_a.to_bitU_method v); + dict_Sail2_values_BitU_a.to_bitU_method v); of_bits_method := (\ v. SOME (MAP - dict_Sail_values_BitU_a.of_bitU_method v)); + dict_Sail2_values_BitU_a.of_bitU_method v)); of_bools_method := (\ v. MAP - dict_Sail_values_BitU_a.of_bitU_method (MAP bitU_of_bool v)); + dict_Sail2_values_BitU_a.of_bitU_method (MAP bitU_of_bool v)); length_method := (\ xs. int_of_num (LENGTH xs)); of_int_method := (\ len n. MAP - dict_Sail_values_BitU_a.of_bitU_method (bits_of_int len n)); + dict_Sail2_values_BitU_a.of_bitU_method (bits_of_int len n)); unsigned_method := (\ v. unsigned_of_bits (MAP - dict_Sail_values_BitU_a.to_bitU_method v)); + dict_Sail2_values_BitU_a.to_bitU_method v)); signed_method := (\ v. signed_of_bits (MAP - dict_Sail_values_BitU_a.to_bitU_method v)); + dict_Sail2_values_BitU_a.to_bitU_method v)); arith_op_bv_method := (\ op sign l r. MAP - dict_Sail_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP - dict_Sail_values_BitU_a.to_bitU_method l) (MAP dict_Sail_values_BitU_a.to_bitU_method r)))|>))`; + dict_Sail2_values_BitU_a.of_bitU_method (arith_op_bits op sign (MAP + dict_Sail2_values_BitU_a.to_bitU_method l) (MAP dict_Sail2_values_BitU_a.to_bitU_method r)))|>))`; val _ = Define ` -((instance_Sail_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<| +((instance_Sail2_values_Bitvector_Machine_word_mword_dict:('a words$word)Bitvector_class)= (<| bits_of_method := (\ v. MAP bitU_of_bool (bitstring$w2v v)); @@ -810,57 +825,57 @@ val _ = Define ` val _ = Define ` - ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n= (access_list T ( - dict_Sail_values_Bitvector_a.bits_of_method v) n))`; + ((access_bv_inc:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n= (access_list T ( + dict_Sail2_values_Bitvector_a.bits_of_method v) n))`; val _ = Define ` - ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail_values_Bitvector_a v n= (access_list F ( - dict_Sail_values_Bitvector_a.bits_of_method v) n))`; + ((access_bv_dec:'a Bitvector_class -> 'a -> int -> bitU)dict_Sail2_values_Bitvector_a v n= (access_list F ( + dict_Sail2_values_Bitvector_a.bits_of_method v) n))`; val _ = Define ` - ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b= (update_list T ( - dict_Sail_values_Bitvector_a.bits_of_method v) n b))`; + ((update_bv_inc:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b= (update_list T ( + dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`; val _ = Define ` - ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail_values_Bitvector_a v n b= (update_list F ( - dict_Sail_values_Bitvector_a.bits_of_method v) n b))`; + ((update_bv_dec:'a Bitvector_class -> 'a -> int -> bitU ->(bitU)list)dict_Sail2_values_Bitvector_a v n b= (update_list F ( + dict_Sail2_values_Bitvector_a.bits_of_method v) n b))`; val _ = Define ` - ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j= (subrange_list T ( - dict_Sail_values_Bitvector_a.bits_of_method v) i j))`; + ((subrange_bv_inc:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j= (subrange_list T ( + dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`; val _ = Define ` - ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail_values_Bitvector_a v i j= (subrange_list F ( - dict_Sail_values_Bitvector_a.bits_of_method v) i j))`; + ((subrange_bv_dec:'a Bitvector_class -> 'a -> int -> int ->(bitU)list)dict_Sail2_values_Bitvector_a v i j= (subrange_list F ( + dict_Sail2_values_Bitvector_a.bits_of_method v) i j))`; val _ = Define ` - ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'= (update_subrange_list T ( - dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`; + ((update_subrange_bv_inc:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'= (update_subrange_list T ( + dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`; val _ = Define ` - ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v'= (update_subrange_list F ( - dict_Sail_values_Bitvector_b.bits_of_method v) i j (dict_Sail_values_Bitvector_a.bits_of_method v')))`; + ((update_subrange_bv_dec:'a Bitvector_class -> 'b Bitvector_class -> 'b -> int -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v'= (update_subrange_list F ( + dict_Sail2_values_Bitvector_b.bits_of_method v) i j (dict_Sail2_values_Bitvector_a.bits_of_method v')))`; (*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) val _ = Define ` - ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (extz_bits n ( - dict_Sail_values_Bitvector_a.bits_of_method v)))`; + ((extz_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v= (extz_bits n ( + dict_Sail2_values_Bitvector_a.bits_of_method v)))`; (*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) val _ = Define ` - ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a n v= (exts_bits n ( - dict_Sail_values_Bitvector_a.bits_of_method v)))`; + ((exts_bv:'a Bitvector_class -> int -> 'a ->(bitU)list)dict_Sail2_values_Bitvector_a n v= (exts_bits n ( + dict_Sail2_values_Bitvector_a.bits_of_method v)))`; (*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*) val _ = Define ` - ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a v= (show_bitlist ( - dict_Sail_values_Bitvector_a.bits_of_method v)))`; + ((string_of_bv:'a Bitvector_class -> 'a -> string)dict_Sail2_values_Bitvector_a v= (show_bitlist ( + dict_Sail2_values_Bitvector_a.bits_of_method v)))`; (*** Bytes and addresses *) @@ -879,8 +894,8 @@ val _ = type_abbrev( "memory_byte" , ``: bitU list``); (*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*) val _ = Define ` - ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail_values_Bitvector_a bs= (byte_chunks ( - dict_Sail_values_Bitvector_a.bits_of_method bs)))`; + ((bytes_of_bits:'a Bitvector_class -> 'a ->((memory_byte)list)option)dict_Sail2_values_Bitvector_a bs= (byte_chunks ( + dict_Sail2_values_Bitvector_a.bits_of_method bs)))`; (*val bits_of_bytes : list memory_byte -> list bitU*) @@ -889,8 +904,8 @@ val _ = Define ` val _ = Define ` - ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail_values_Bitvector_a bs= (OPTION_MAP REVERSE (bytes_of_bits - dict_Sail_values_Bitvector_a bs)))`; + ((mem_bytes_of_bits:'a Bitvector_class -> 'a ->(((bitU)list)list)option)dict_Sail2_values_Bitvector_a bs= (OPTION_MAP REVERSE (bytes_of_bits + dict_Sail2_values_Bitvector_a bs)))`; val _ = Define ` ((bits_of_mem_bytes:((bitU)list)list ->(bitU)list) bs= (bits_of_bytes (REVERSE bs)))`; @@ -1150,29 +1165,29 @@ val _ = Hol_datatype ` (* eta-expanded for Isabelle output, otherwise it breaks *) val _ = Define ` -((instance_Sail_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<| +((instance_Sail2_values_ToNatural_Num_integer_dict:(int)ToNatural_class)= (<| toNatural_method := (\ n . Num (ABS n))|>))`; val _ = Define ` -((instance_Sail_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<| +((instance_Sail2_values_ToNatural_Num_int_dict:(int)ToNatural_class)= (<| toNatural_method := (\ n . ((Num (ABS n)):num))|>))`; val _ = Define ` -((instance_Sail_values_ToNatural_nat_dict:(num)ToNatural_class)= (<| +((instance_Sail2_values_ToNatural_nat_dict:(num)ToNatural_class)= (<| toNatural_method := (\ n . ( n:num))|>))`; val _ = Define ` -((instance_Sail_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<| +((instance_Sail2_values_ToNatural_Num_natural_dict:(num)ToNatural_class)= (<| toNatural_method := (\ n . n)|>))`; val _ = Define ` - ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5)= - (dict_Sail_values_ToNatural_d.toNatural_method n1, dict_Sail_values_ToNatural_c.toNatural_method n2, dict_Sail_values_ToNatural_b.toNatural_method n3, dict_Sail_values_ToNatural_a.toNatural_method n4, dict_Sail_values_ToNatural_e.toNatural_method n5))`; + ((toNaturalFiveTup:'a ToNatural_class -> 'b ToNatural_class -> 'c ToNatural_class -> 'd ToNatural_class -> 'e ToNatural_class -> 'd#'c#'b#'a#'e -> num#num#num#num#num)dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5)= + (dict_Sail2_values_ToNatural_d.toNatural_method n1, dict_Sail2_values_ToNatural_c.toNatural_method n2, dict_Sail2_values_ToNatural_b.toNatural_method n3, dict_Sail2_values_ToNatural_a.toNatural_method n4, dict_Sail2_values_ToNatural_e.toNatural_method n5))`; (* Let the following types be generated by Sail per spec, using either bitlists diff --git a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml b/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml deleted file mode 100644 index 48f4c8cb..00000000 --- a/snapshots/hol4/sail/lib/hol/sail_operators_bitlistsScript.sml +++ /dev/null @@ -1,769 +0,0 @@ -(*Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.*) -open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory lem_machine_wordTheory sail_valuesTheory sail_operatorsTheory prompt_monadTheory promptTheory; - -val _ = numLib.prefer_num(); - - - -val _ = new_theory "sail_operators_bitlists" - -(*open import Pervasives_extra*) -(*open import Machine_word*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) - -(* Specialisation of operators to bit lists *) - -(*val uint_maybe : list bitU -> maybe integer*) -val _ = Define ` - ((uint_maybe0:(bitU)list ->(int)option) v= (unsigned_of_bits (MAP (\ b. b) v)))`; - -val _ = Define ` - ((uint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "uint" ( - dict_Sail_values_Bitvector_a.unsigned_method v)))`; - -val _ = Define ` - ((uint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS - (state$bools_of_bits_oracleS v) (\ bs . - state_monad$returnS (int_of_bools F bs))))`; - -val _ = Define ` - ((uint:(bitU)list -> int) v= (maybe_failwith (uint_maybe0 v)))`; - - -(*val sint_maybe : list bitU -> maybe integer*) -val _ = Define ` - ((sint_maybe0:(bitU)list ->(int)option) v= (signed_of_bits (MAP (\ b. b) v)))`; - -val _ = Define ` - ((sint_fail0:'a Bitvector_class -> 'a -> 'b state_monad$sequential_state ->(((int),'c)state_monad$result#'b state_monad$sequential_state)set)dict_Sail_values_Bitvector_a v= (state_monad$maybe_failS "sint" ( - dict_Sail_values_Bitvector_a.signed_method v)))`; - -val _ = Define ` - ((sint_oracle0:(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) v= (state_monad$bindS - (state$bools_of_bits_oracleS v) (\ bs . - state_monad$returnS (int_of_bools T bs))))`; - -val _ = Define ` - ((sint:(bitU)list -> int) v= (maybe_failwith (sint_maybe0 v)))`; - - -(*val extz_vec : integer -> list bitU -> list bitU*) -val _ = Define ` - ((extz_vec0:int ->(bitU)list ->(bitU)list)= - (extz_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val exts_vec : integer -> list bitU -> list bitU*) -val _ = Define ` - ((exts_vec0:int ->(bitU)list ->(bitU)list)= - (exts_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val zero_extend : list bitU -> integer -> list bitU*) -val _ = Define ` - ((zero_extend0:(bitU)list -> int ->(bitU)list) bits len= (extz_bits len bits))`; - - -(*val sign_extend : list bitU -> integer -> list bitU*) -val _ = Define ` - ((sign_extend0:(bitU)list -> int ->(bitU)list) bits len= (exts_bits len bits))`; - - -(*val zeros : integer -> list bitU*) -val _ = Define ` - ((zeros0:int ->(bitU)list) len= (repeat [B0] len))`; - - -(*val vector_truncate : list bitU -> integer -> list bitU*) -val _ = Define ` - ((vector_truncate0:(bitU)list -> int ->(bitU)list) bs len= (extz_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) len bs))`; - - -(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) -(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) -(*val vec_of_bits_failwith : list bitU -> list bitU*) -(*val vec_of_bits : list bitU -> list bitU*) - -(*val access_vec_inc : list bitU -> integer -> bitU*) -val _ = Define ` - ((access_vec_inc0:(bitU)list -> int -> bitU)= - (access_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val access_vec_dec : list bitU -> integer -> bitU*) -val _ = Define ` - ((access_vec_dec0:(bitU)list -> int -> bitU)= - (access_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) -val _ = Define ` - ((update_vec_inc0:(bitU)list -> int -> bitU ->(bitU)list)= - (update_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((update_vec_inc_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_inc0 v i b)))`; - -val _ = Define ` - ((update_vec_inc_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; - -val _ = Define ` - ((update_vec_inc_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_inc0 v i b)))`; - - -(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) -val _ = Define ` - ((update_vec_dec0:(bitU)list -> int -> bitU ->(bitU)list)= - (update_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((update_vec_dec_maybe0:(bitU)list -> int -> bitU ->((bitU)list)option) v i b= (SOME (update_vec_dec0 v i b)))`; - -val _ = Define ` - ((update_vec_dec_fail0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; - -val _ = Define ` - ((update_vec_dec_oracle0:(bitU)list -> int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) v i b= (state_monad$returnS (update_vec_dec0 v i b)))`; - - -(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) -val _ = Define ` - ((subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list)= - (subrange_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) -val _ = Define ` - ((subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list)= - (subrange_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) -val _ = Define ` - ((update_subrange_vec_inc0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= - (update_subrange_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) -val _ = Define ` - ((update_subrange_vec_dec0:(bitU)list -> int -> int ->(bitU)list ->(bitU)list)= - (update_subrange_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val concat_vec : list bitU -> list bitU -> list bitU*) -val _ = Define ` - ((concat_vec0:(bitU)list ->(bitU)list ->(bitU)list)= - (concat_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val cons_vec : bitU -> list bitU -> list bitU*) -val _ = Define ` - ((cons_vec0:bitU ->(bitU)list ->(bitU)list)= - (cons_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((cons_vec_maybe0:bitU ->(bitU)list ->((bitU)list)option) b v= (SOME (cons_vec0 b v)))`; - -val _ = Define ` - ((cons_vec_fail0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; - -val _ = Define ` - ((cons_vec_oracle0:bitU ->(bitU)list -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b v= (state_monad$returnS (cons_vec0 b v)))`; - - -(*val cast_unit_vec : bitU -> list bitU*) -val _ = Define ` - ((cast_unit_vec0:bitU ->(bitU)list)= cast_unit_bv)`; - -val _ = Define ` - ((cast_unit_vec_maybe0:bitU ->((bitU)list)option) b= (SOME (cast_unit_vec0 b)))`; - -val _ = Define ` - ((cast_unit_vec_fail0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; - -val _ = Define ` - ((cast_unit_vec_oracle0:bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b= (state_monad$returnS (cast_unit_vec0 b)))`; - - -(*val vec_of_bit : integer -> bitU -> list bitU*) -val _ = Define ` - ((vec_of_bit0:int -> bitU ->(bitU)list)= bv_of_bit)`; - -val _ = Define ` - ((vec_of_bit_maybe0:int -> bitU ->((bitU)list)option) len b= (SOME (vec_of_bit0 len b)))`; - -val _ = Define ` - ((vec_of_bit_fail0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; - -val _ = Define ` - ((vec_of_bit_oracle0:int -> bitU -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) len b= (state_monad$returnS (vec_of_bit0 len b)))`; - - -(*val msb : list bitU -> bitU*) -val _ = Define ` - ((msb0:(bitU)list -> bitU)= - (most_significant - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) -val _ = Define ` - ((int_of_vec_maybe0:bool ->(bitU)list ->(int)option)= - (int_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((int_of_vec_fail0:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$maybe_failS "int_of_vec" (int_of_vec_maybe0 sign v)))`; - -val _ = Define ` - ((int_of_vec_oracle:bool ->(bitU)list -> 'a state_monad$sequential_state ->(((int),'b)state_monad$result#'a state_monad$sequential_state)set) sign v= (state_monad$bindS (state$bools_of_bits_oracleS v) (\ v . state_monad$returnS (int_of_bools sign v))))`; - -val _ = Define ` - ((int_of_vec0:bool ->(bitU)list -> int) sign v= (maybe_failwith (int_of_vec_maybe0 sign v)))`; - - -(*val string_of_vec : list bitU -> string*) -val _ = Define ` - ((string_of_vec0:(bitU)list -> string)= - (string_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val and_vec : list bitU -> list bitU -> list bitU*) -(*val or_vec : list bitU -> list bitU -> list bitU*) -(*val xor_vec : list bitU -> list bitU -> list bitU*) -(*val not_vec : list bitU -> list bitU*) -val _ = Define ` - ((and_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list and_bit))`; - -val _ = Define ` - ((or_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list or_bit))`; - -val _ = Define ` - ((xor_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (binop_list xor_bit))`; - -val _ = Define ` - ((not_vec0:(bitU)list ->(bitU)list)= (MAP not_bit))`; - - -(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => - (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) -val _ = Define ` - ((arith_op_double_bl:'a Bitvector_class ->(int -> int -> int) -> bool -> 'a -> 'a ->(bitU)list)dict_Sail_values_Bitvector_a op sign l r= - (let len =(( 2 : int) * - dict_Sail_values_Bitvector_a.length_method l) in - let l' = (if sign then exts_bv - dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in - let r' = (if sign then exts_bv - dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in - MAP (\ b. b) (arith_op_bits op sign (MAP (\ b. b) l') (MAP (\ b. b) r'))))`; - - -(*val add_vec : list bitU -> list bitU -> list bitU*) -(*val adds_vec : list bitU -> list bitU -> list bitU*) -(*val sub_vec : list bitU -> list bitU -> list bitU*) -(*val subs_vec : list bitU -> list bitU -> list bitU*) -(*val mult_vec : list bitU -> list bitU -> list bitU*) -(*val mults_vec : list bitU -> list bitU -> list bitU*) -val _ = Define ` - ((add_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; - -val _ = Define ` - ((adds_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (+) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; - -val _ = Define ` - ((sub_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) F (MAP (\ b. b) l) (MAP (\ b. b) r))))`; - -val _ = Define ` - ((subs_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (\ l r. MAP (\ b. b) (arith_op_bits (-) T (MAP (\ b. b) l) (MAP (\ b. b) r))))`; - -val _ = Define ` - ((mult_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F))`; - -val _ = Define ` - ((mults_vec0:(bitU)list ->(bitU)list ->(bitU)list)= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T))`; - - -(*val add_vec_int : list bitU -> integer -> list bitU*) -(*val adds_vec_int : list bitU -> integer -> list bitU*) -(*val sub_vec_int : list bitU -> integer -> list bitU*) -(*val subs_vec_int : list bitU -> integer -> list bitU*) -(*val mult_vec_int : list bitU -> integer -> list bitU*) -(*val mults_vec_int : list bitU -> integer -> list bitU*) -val _ = Define ` - ((add_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; - -val _ = Define ` - ((adds_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; - -val _ = Define ` - ((sub_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; - -val _ = Define ` - ((subs_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; - -val _ = Define ` - ((mult_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; - -val _ = Define ` - ((mults_vec_int0:(bitU)list -> int ->(bitU)list) l r= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T l (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH l)) r))))`; - - -(*val add_int_vec : integer -> list bitU -> list bitU*) -(*val adds_int_vec : integer -> list bitU -> list bitU*) -(*val sub_int_vec : integer -> list bitU -> list bitU*) -(*val subs_int_vec : integer -> list bitU -> list bitU*) -(*val mult_int_vec : integer -> list bitU -> list bitU*) -(*val mults_int_vec : integer -> list bitU -> list bitU*) -val _ = Define ` - ((add_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (+) F l r))`; - -val _ = Define ` - ((adds_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (+) T l r))`; - -val _ = Define ` - ((sub_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (-) F l r))`; - -val _ = Define ` - ((subs_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (-) T l r))`; - -val _ = Define ` - ((mult_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) F (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; - -val _ = Define ` - ((mults_int_vec0:int ->(bitU)list ->(bitU)list) l r= (arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ( * ) T (MAP (\ b. b) (bits_of_int (int_of_num (LENGTH r)) l)) r))`; - - -(*val add_vec_bit : list bitU -> bitU -> list bitU*) -(*val adds_vec_bit : list bitU -> bitU -> list bitU*) -(*val sub_vec_bit : list bitU -> bitU -> list bitU*) -(*val subs_vec_bit : list bitU -> bitU -> list bitU*) - -val _ = Define ` - ((add_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool - dict_Sail_values_Bitvector_a (+) F l r))`; - -val _ = Define ` - ((add_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit - dict_Sail_values_Bitvector_a (+) F l r))`; - -val _ = Define ` - ((add_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "add_vec_bit" (add_vec_bit_maybe0 - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((add_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (add_vec_bool0 - dict_Sail_values_Bitvector_a l r))))`; - -val _ = Define ` - ((add_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (add_vec_bit_maybe0 - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - - -val _ = Define ` - ((adds_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool - dict_Sail_values_Bitvector_a (+) T l r))`; - -val _ = Define ` - ((adds_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit - dict_Sail_values_Bitvector_a (+) T l r))`; - -val _ = Define ` - ((adds_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "adds_vec_bit" (adds_vec_bit_maybe0 - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((adds_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (adds_vec_bool0 - dict_Sail_values_Bitvector_a l r))))`; - -val _ = Define ` - ((adds_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (adds_vec_bit_maybe0 - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - - -val _ = Define ` - ((sub_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool - dict_Sail_values_Bitvector_a (-) F l r))`; - -val _ = Define ` - ((sub_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit - dict_Sail_values_Bitvector_a (-) F l r))`; - -val _ = Define ` - ((sub_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (sub_vec_bit_maybe0 - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((sub_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (sub_vec_bool0 - dict_Sail_values_Bitvector_a l r))))`; - -val _ = Define ` - ((sub_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (sub_vec_bit_maybe0 - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - - -val _ = Define ` - ((subs_vec_bool0:'a Bitvector_class -> 'a -> bool -> 'a)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bool - dict_Sail_values_Bitvector_a (-) T l r))`; - -val _ = Define ` - ((subs_vec_bit_maybe0:'a Bitvector_class -> 'a -> bitU -> 'a option)dict_Sail_values_Bitvector_a l r= (arith_op_bv_bit - dict_Sail_values_Bitvector_a (-) T l r))`; - -val _ = Define ` - ((subs_vec_bit_fail0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$maybe_failS "sub_vec_bit" (subs_vec_bit_maybe0 - dict_Sail_values_Bitvector_a l r)))`; - -val _ = Define ` - ((subs_vec_bit_oracle0:'a Bitvector_class -> 'a -> bitU -> 'c state_monad$sequential_state ->(('a,'d)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_a l r= (state_monad$bindS (state$bool_of_bitU_oracleS r) (\ r . state_monad$returnS (subs_vec_bool0 - dict_Sail_values_Bitvector_a l r))))`; - -val _ = Define ` - ((subs_vec_bit0:(bitU)list -> bitU ->(bitU)list) l r= (option_CASE (subs_vec_bit_maybe0 - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - - -(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) -val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) -let add_overflow_vec = add_overflow_bv -let add_overflow_vec_signed = add_overflow_bv_signed -let sub_overflow_vec = sub_overflow_bv -let sub_overflow_vec_signed = sub_overflow_bv_signed -let mult_overflow_vec = mult_overflow_bv -let mult_overflow_vec_signed = mult_overflow_bv_signed - -val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) -val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) -val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) -let add_overflow_vec_bit = add_overflow_bv_bit -let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed -let sub_overflow_vec_bit = sub_overflow_bv_bit -let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) - -(*val shiftl : list bitU -> integer -> list bitU*) -(*val shiftr : list bitU -> integer -> list bitU*) -(*val arith_shiftr : list bitU -> integer -> list bitU*) -(*val rotl : list bitU -> integer -> list bitU*) -(*val rotr : list bitU -> integer -> list bitU*) -val _ = Define ` - ((shiftl0:(bitU)list -> int ->(bitU)list)= - (shiftl_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((shiftr0:(bitU)list -> int ->(bitU)list)= - (shiftr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((arith_shiftr0:(bitU)list -> int ->(bitU)list)= - (arith_shiftr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((rotl0:(bitU)list -> int ->(bitU)list)= - (rotl_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((rotr0:(bitU)list -> int ->(bitU)list)= - (rotr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val mod_vec : list bitU -> list bitU -> list bitU*) -(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) -(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -val _ = Define ` - ((mod_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - -val _ = Define ` - ((mod_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; - -val _ = Define ` - ((mod_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec" (mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; - -val _ = Define ` - ((mod_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec0 l r)))`; - - -(*val quot_vec : list bitU -> list bitU -> list bitU*) -(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) -(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -val _ = Define ` - ((quot_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - -val _ = Define ` - ((quot_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; - -val _ = Define ` - ((quot_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec" (quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; - -val _ = Define ` - ((quot_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec0 l r)))`; - - -(*val quots_vec : list bitU -> list bitU -> list bitU*) -(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) -(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -val _ = Define ` - ((quots_vec0:(bitU)list ->(bitU)list ->(bitU)list) l r= (option_CASE (quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - -val _ = Define ` - ((quots_vec_maybe0:(bitU)list ->(bitU)list ->((bitU)list)option) l r= (quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; - -val _ = Define ` - ((quots_vec_fail0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quots_vec" (quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; - -val _ = Define ` - ((quots_vec_oracle0:(bitU)list ->(bitU)list -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec0 l r)))`; - - -(*val mod_vec_int : list bitU -> integer -> list bitU*) -(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) -(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -val _ = Define ` - ((mod_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - -val _ = Define ` - ((mod_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; - -val _ = Define ` - ((mod_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "mod_vec_int" (mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; - -val _ = Define ` - ((mod_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int0 l r)))`; - - -(*val quot_vec_int : list bitU -> integer -> list bitU*) -(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) -(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -val _ = Define ` - ((quot_vec_int0:(bitU)list -> int ->(bitU)list) l r= (option_CASE (quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r) (repeat [BU] (int_of_num (LENGTH l))) I))`; - -val _ = Define ` - ((quot_vec_int_maybe0:(bitU)list -> int ->((bitU)list)option) l r= (quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))`; - -val _ = Define ` - ((quot_vec_int_fail0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state_monad$maybe_failS "quot_vec_int" (quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r)))`; - -val _ = Define ` - ((quot_vec_int_oracle0:(bitU)list -> int -> 'rv state_monad$sequential_state ->((((bitU)list),'e)state_monad$result#'rv state_monad$sequential_state)set) l r= (state$of_bits_oracleS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int0 l r)))`; - - -(*val replicate_bits : list bitU -> integer -> list bitU*) -val _ = Define ` - ((replicate_bits0:(bitU)list -> int ->(bitU)list)= - (replicate_bits_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val duplicate : bitU -> integer -> list bitU*) -val _ = Define ` - ((duplicate0:bitU -> int ->(bitU)list)= - (duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict))`; - -val _ = Define ` - ((duplicate_maybe0:bitU -> int ->((bitU)list)option) b n= (SOME (duplicate0 b n)))`; - -val _ = Define ` - ((duplicate_fail0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$returnS (duplicate0 b n)))`; - -val _ = Define ` - ((duplicate_oracle0:bitU -> int -> 'a state_monad$sequential_state ->((((bitU)list),'b)state_monad$result#'a state_monad$sequential_state)set) b n= (state_monad$bindS - (state$bool_of_bitU_oracleS b) (\ b . - state_monad$returnS (duplicate0 (bitU_of_bool b) n))))`; - - -(*val reverse_endianness : list bitU -> list bitU*) -val _ = Define ` - ((reverse_endianness0:(bitU)list ->(bitU)list) v= (reverse_endianness_list v))`; - - -(*val get_slice_int : integer -> integer -> integer -> list bitU*) -val _ = Define ` - ((get_slice_int0:int -> int -> int ->(bitU)list)= - (get_slice_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) -val _ = Define ` - ((set_slice_int0:int -> int -> int ->(bitU)list -> int)= - (set_slice_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - - -(*val slice : list bitU -> integer -> integer -> list bitU*) -val _ = Define ` - ((slice0:(bitU)list -> int -> int ->(bitU)list) v lo len= - (subrange_vec_dec0 v ((lo + len) -( 1 : int)) lo))`; - - -(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*) -val _ = Define ` - ((set_slice0:int -> int ->(bitU)list -> int ->(bitU)list ->(bitU)list) (out_len:ii) (slice_len:ii) out (n:ii) v= - (update_subrange_vec_dec0 out ((n + slice_len) -( 1 : int)) n v))`; - - -(*val eq_vec : list bitU -> list bitU -> bool*) -(*val neq_vec : list bitU -> list bitU -> bool*) -val _ = Define ` - ((eq_vec:(bitU)list ->(bitU)list -> bool)= - (eq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = Define ` - ((neq_vec:(bitU)list ->(bitU)list -> bool)= - (neq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict)))`; - -val _ = export_theory() - diff --git a/snapshots/hol4/sail/mips/Holmakefile b/snapshots/hol4/sail/mips/Holmakefile new file mode 100644 index 00000000..a31bfd4f --- /dev/null +++ b/snapshots/hol4/sail/mips/Holmakefile @@ -0,0 +1,11 @@ +LEMDIR=../../lem/hol-lib + +INCLUDES = $(LEMDIR) ../lib/hol + +all: mipsTheory.uo +.PHONY: all + +ifdef POLY +BASE_HEAP = ../lib/hol/sail-heap + +endif diff --git a/snapshots/hol4/sail/mips/mipsScript.sml b/snapshots/hol4/sail/mips/mipsScript.sml new file mode 100644 index 00000000..928a7276 --- /dev/null +++ b/snapshots/hol4/sail/mips/mipsScript.sml @@ -0,0 +1,6871 @@ +(*Generated by Lem from mips.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory mips_typesTheory mips_extrasTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "mips" + +(*Generated by Sail from mips.*) +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) +(*open import Mips_types*) +(*open import Mips_extras*) + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +val _ = Define ` + ((neq_bool:bool -> bool -> bool) x y= (~ (((x = y)))))`; + + +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +val _ = Define ` + ((undefined_option:'a ->(regstate)sail2_state_monad$sequential_state ->((('a option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) typ_a= (sail2_state_monad$bindS + (undefined_unit () ) (\ (u_0 : unit) . + let (u_1 : 'a) = typ_a in + sail2_state$internal_pickS [SOME u_1;NONE])))`; + + +(*val is_none : forall 'a. maybe 'a -> bool*) + +val _ = Define ` + ((is_none:'a option -> bool) opt= ((case opt of SOME (_) => F | NONE => T )))`; + + +(*val is_some : forall 'a. maybe 'a -> bool*) + +val _ = Define ` + ((is_some:'a option -> bool) opt= ((case opt of SOME (_) => T | NONE => F )))`; + + +(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*) + +val _ = Define ` + ((sail_mask:'len itself -> 'v words$word -> 'len words$word) len v= + (let len = (size_itself_int len) in + if ((len <= ((int_of_num (words$word_len v))))) then (vector_truncate v len : 'len words$word) + else (zero_extend v len : 'len words$word)))`; + + + + + + +(*val cast_unit_vec : bitU -> mword ty1*) + +val _ = Define ` + ((cast_unit_vec0:bitU ->(1)words$word) b= + ((case b of B0 => (vec_of_bits [B0] : 1 words$word) | _ => (vec_of_bits [B1] : 1 words$word) )))`; + + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +val _ = Define ` + ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= + (write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr data))`; + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MIPS_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'p8_times_n_ words$word) M)))`; + + + + +(*val undefined_exception : unit -> M exception*) + +val _ = Define ` + ((undefined_exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_string () ) (\ (u_0 : string) . sail2_state_monad$bindS + (undefined_unit () ) (\ (u_1 : unit) . + sail2_state$internal_pickS + [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]))))`; + + +(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((mips_sign_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((sign_extend v m__tv : 'm words$word)))`; + + +val _ = Define ` + ((mips_zero_extend:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((zero_extend v m__tv : 'm words$word)))`; + + +(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +val _ = Define ` + ((zeros0:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B0] : 1 words$word) n__tv : 'n words$word)))`; + + +(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +val _ = Define ` + ((ones:int -> unit -> 'n words$word) (n__tv : int) () = ((replicate_bits (vec_of_bits [B1] : 1 words$word) n__tv : 'n words$word)))`; + + +(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) + +val _ = Define ` + ((zopz0zI_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) < ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zKzJ_s:'n words$word -> 'n words$word -> bool) x y= (((integer_word$w2i x)) >= ((integer_word$w2i y))))`; + + +val _ = Define ` + ((zopz0zI_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) < ((lem$w2ui y))))`; + + +val _ = Define ` + ((zopz0zKzJ_u:'n words$word -> 'n words$word -> bool) x y= (((lem$w2ui x)) >= ((lem$w2ui y))))`; + + +(*val bool_to_bits : bool -> mword ty1*) + +val _ = Define ` + ((bool_to_bits:bool ->(1)words$word) x= (if x then (vec_of_bits [B1] : 1 words$word) else (vec_of_bits [B0] : 1 words$word)))`; + + +(*val bit_to_bool : bitU -> bool*) + +val _ = Define ` + ((bit_to_bool:bitU -> bool) b= ((case b of B1 => T | _ => F )))`; + + +(*val bits_to_bool : mword ty1 -> bool*) + +val _ = Define ` + ((bits_to_bool:(1)words$word -> bool) x= (bit_to_bool ((access_vec_dec x (( 0 : int):ii)))))`; + + +(* +\function{to\_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. +*) +(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*) + +val _ = Define ` + ((to_bits:'l itself -> int -> 'l words$word) l n= + (let l = (size_itself_int l) in + (get_slice_int instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):ii) : 'l words$word)))`; + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) + +val _ = Define ` + ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs= + ((subrange_vec_dec bs ((n__tv - (( 1 : int):ii))) (( 0 : int):ii) : 'n words$word)))`; + + +(*val undefined_CauseReg : unit -> M CauseReg*) + +val _ = Define ` + ((undefined_CauseReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((CauseReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS (<| CauseReg_CauseReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_CauseReg : mword ty32 -> CauseReg*) + +val _ = Define ` + ((Mk_CauseReg:(32)words$word -> CauseReg) v= + (<| CauseReg_CauseReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`; + + +(*val _get_CauseReg_bits : CauseReg -> mword ty32*) + +val _ = Define ` + ((get_CauseReg_bits:CauseReg ->(32)words$word) v= + ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; + + +(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) + +val _ = Define ` + ((set_CauseReg_bits:((regstate),(register_value),(CauseReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_bits:CauseReg ->(32)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)))`; + + +(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*) + +(*val _get_StatusReg_bits : StatusReg -> mword ty32*) + +(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) + +(*val _get_CauseReg_BD : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_BD:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_BD:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_BD:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_CauseReg_CE : CauseReg -> mword ty2*) + +val _ = Define ` + ((get_CauseReg_CE:CauseReg ->(2)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) : 2 words$word)))`; + + +(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_CauseReg_CE:((regstate),(register_value),(CauseReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_CE:CauseReg ->(2)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 29 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_CauseReg_IV : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_IV:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_IV:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_IV:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_CauseReg_WP : CauseReg -> mword ty1*) + +val _ = Define ` + ((get_CauseReg_WP:CauseReg ->(1)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_CauseReg_WP:((regstate),(register_value),(CauseReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_WP:CauseReg ->(1)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_CauseReg_IP : CauseReg -> mword ty8*) + +val _ = Define ` + ((get_CauseReg_IP:CauseReg ->(8)words$word) v= ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_CauseReg_IP:((regstate),(register_value),(CauseReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_IP:CauseReg ->(8)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) + +val _ = Define ` + ((get_CauseReg_ExcCode:CauseReg ->(5)words$word) v= + ((subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)))`; + + +(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) + +val _ = Define ` + ((set_CauseReg_ExcCode:((regstate),(register_value),(CauseReg))register_ref ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec r.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) + +val _ = Define ` + ((update_CauseReg_ExcCode:CauseReg ->(5)words$word -> CauseReg) v x= + ((v with<| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec v.CauseReg_CauseReg_chunk_0 (( 6 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) + : 32 words$word))|>)))`; + + +(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) + +val _ = Define ` + ((undefined_TLBEntryLoReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryLoReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*) + +val _ = Define ` + ((Mk_TLBEntryLoReg:(64)words$word -> TLBEntryLoReg) v= + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*) + +val _ = Define ` + ((get_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_bits:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_bits:TLBEntryLoReg ->(64)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapS:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapS:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_CapL:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_CapL:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) + +val _ = Define ` + ((get_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_PFN:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_PFN:TLBEntryLoReg ->(24)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 29 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) + +val _ = Define ` + ((get_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_C:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_C:TLBEntryLoReg ->(3)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 5 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_D:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_D:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_V:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_V:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) + +val _ = Define ` + ((get_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntryLoReg_G:((regstate),(register_value),(TLBEntryLoReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +val _ = Define ` + ((update_TLBEntryLoReg_G:TLBEntryLoReg ->(1)words$word -> TLBEntryLoReg) v x= + ((v with<| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryLoReg_TLBEntryLoReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) + +val _ = Define ` + ((undefined_TLBEntryHiReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntryHiReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*) + +val _ = Define ` + ((Mk_TLBEntryHiReg:(64)words$word -> TLBEntryHiReg) v= + (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*) + +val _ = Define ` + ((get_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_bits:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_bits:TLBEntryHiReg ->(64)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) + +val _ = Define ` + ((get_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; + + +(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_R:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_R:TLBEntryHiReg ->(2)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) + +val _ = Define ` + ((get_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))`; + + +(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_VPN2:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_VPN2:TLBEntryHiReg ->(27)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 39 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) + +val _ = Define ` + ((get_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word) v= + ((subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_TLBEntryHiReg_ASID:((regstate),(register_value),(TLBEntryHiReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec r.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) + +val _ = Define ` + ((update_TLBEntryHiReg_ASID:TLBEntryHiReg ->(8)words$word -> TLBEntryHiReg) v x= + ((v with<| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec v.TLBEntryHiReg_TLBEntryHiReg_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)))`; + + +(*val undefined_ContextReg : unit -> M ContextReg*) + +val _ = Define ` + ((undefined_ContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((ContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| ContextReg_ContextReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_ContextReg : mword ty64 -> ContextReg*) + +val _ = Define ` + ((Mk_ContextReg:(64)words$word -> ContextReg) v= + (<| ContextReg_ContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_ContextReg_bits : ContextReg -> mword ty64*) + +val _ = Define ` + ((get_ContextReg_bits:ContextReg ->(64)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_ContextReg_bits:((regstate),(register_value),(ContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_bits:ContextReg ->(64)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) + +val _ = Define ` + ((get_ContextReg_PTEBase:ContextReg ->(41)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)))`; + + +(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) + +val _ = Define ` + ((set_ContextReg_PTEBase:((regstate),(register_value),(ContextReg))register_ref ->(41)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec v (( 40 : int):ii) (( 0 : int):ii) : 41 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_PTEBase:ContextReg ->(41)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 63 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec x (( 40 : int):ii) (( 0 : int):ii) : 41 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) + +val _ = Define ` + ((get_ContextReg_BadVPN2:ContextReg ->(19)words$word) v= + ((subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) : 19 words$word)))`; + + +(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) + +val _ = Define ` + ((set_ContextReg_BadVPN2:((regstate),(register_value),(ContextReg))register_ref ->(19)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec r.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 18 : int):ii) (( 0 : int):ii) : 19 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) + +val _ = Define ` + ((update_ContextReg_BadVPN2:ContextReg ->(19)words$word -> ContextReg) v x= + ((v with<| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec v.ContextReg_ContextReg_chunk_0 (( 22 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 18 : int):ii) (( 0 : int):ii) : 19 words$word)) + : 64 words$word))|>)))`; + + +(*val undefined_XContextReg : unit -> M XContextReg*) + +val _ = Define ` + ((undefined_XContextReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((XContextReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS (<| XContextReg_XContextReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_XContextReg : mword ty64 -> XContextReg*) + +val _ = Define ` + ((Mk_XContextReg:(64)words$word -> XContextReg) v= + (<| XContextReg_XContextReg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_XContextReg_bits : XContextReg -> mword ty64*) + +val _ = Define ` + ((get_XContextReg_bits:XContextReg ->(64)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_XContextReg_bits:((regstate),(register_value),(XContextReg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_bits:XContextReg ->(64)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) + +val _ = Define ` + ((get_XContextReg_XPTEBase:XContextReg ->(31)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)))`; + + +(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XPTEBase:((regstate),(register_value),(XContextReg))register_ref ->(31)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec v (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XPTEBase:XContextReg ->(31)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 63 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec x (( 30 : int):ii) (( 0 : int):ii) : 31 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_XContextReg_XR : XContextReg -> mword ty2*) + +val _ = Define ` + ((get_XContextReg_XR:XContextReg ->(2)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) : 2 words$word)))`; + + +(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XR:((regstate),(register_value),(XContextReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XR:XContextReg ->(2)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 32 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) + +val _ = Define ` + ((get_XContextReg_XBadVPN2:XContextReg ->(27)words$word) v= + ((subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) : 27 words$word)))`; + + +(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_XContextReg_XBadVPN2:((regstate),(register_value),(XContextReg))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec r.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) + +val _ = Define ` + ((update_XContextReg_XBadVPN2:XContextReg ->(27)words$word -> XContextReg) v x= + ((v with<| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec v.XContextReg_XContextReg_chunk_0 (( 30 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 64 words$word))|>)))`; + + +val _ = Define ` + ((TLBNumEntries:int)= ((( 64 : int):ii)))`; + + +val _ = Define ` +((TLBIndexMax:(6)words$word)= ((vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))`; + + +(*val MAX : integer -> integer*) + +val _ = Define ` + ((MAX0:int -> int) n= (((pow2 n)) - (( 1 : int):ii)))`; + + +val _ = Define ` + ((MAX_U64:int)= (MAX0 (( 64 : int):ii)))`; + + +val _ = Define ` + ((MAX_VA:int)= (MAX0 (( 40 : int):ii)))`; + + +val _ = Define ` + ((MAX_PA:int)= (MAX0 (( 36 : int):ii)))`; + + +(*val undefined_TLBEntry : unit -> M TLBEntry*) + +val _ = Define ` + ((undefined_TLBEntry:unit ->(regstate)sail2_state_monad$sequential_state ->(((TLBEntry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 : int):ii) : ( 53 words$word) M) (\ (w__0 : 53 words$word) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + sail2_state_monad$returnS (<| TLBEntry_TLBEntry_chunk_1 := w__0; + TLBEntry_TLBEntry_chunk_0 := w__1 |>)))))`; + + +(*val Mk_TLBEntry : mword ty117 -> TLBEntry*) + +val _ = Define ` + ((Mk_TLBEntry:(117)words$word -> TLBEntry) v= + (<| TLBEntry_TLBEntry_chunk_1 := ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*) + +val _ = Define ` + ((get_TLBEntry_bits:TLBEntry ->(117)words$word) v= + ((concat_vec ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) : 53 words$word)) + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 117 words$word)))`; + + +(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_bits:((regstate),(register_value),(TLBEntry))register_ref ->(117)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)) + : 53 words$word))|>)) in + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_bits:TLBEntry ->(117)words$word -> TLBEntry) v x= + (let v = + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 116 : int):ii) (( 64 : int):ii) : 53 words$word)) + : 53 words$word))|>)) in + (v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) + +val _ = Define ` + ((get_TLBEntry_pagemask:TLBEntry ->(16)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) : 16 words$word)))`; + + +(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pagemask:((regstate),(register_value),(TLBEntry))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) + ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pagemask:TLBEntry ->(16)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 52 : int):ii) (( 37 : int):ii) + ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 53 words$word))|>)))`; + + +(*val _get_TLBEntry_r : TLBEntry -> mword ty2*) + +val _ = Define ` + ((get_TLBEntry_r:TLBEntry ->(2)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) : 2 words$word)))`; + + +(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_r:((regstate),(register_value),(TLBEntry))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_r:TLBEntry ->(2)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 36 : int):ii) (( 35 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 53 words$word))|>)))`; + + +(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) + +val _ = Define ` + ((get_TLBEntry_vpn2:TLBEntry ->(27)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) : 27 words$word)))`; + + +(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_vpn2:((regstate),(register_value),(TLBEntry))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_vpn2:TLBEntry ->(27)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 34 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 53 words$word))|>)))`; + + +(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) + +val _ = Define ` + ((get_TLBEntry_asid:TLBEntry ->(8)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_asid:((regstate),(register_value),(TLBEntry))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 53 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_asid:TLBEntry ->(8)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_1 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 53 words$word))|>)))`; + + +(*val _get_TLBEntry_g : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_g:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_g:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_g:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_valid:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_valid:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_valid:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 62 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_caps1:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_caps1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 61 : int):ii) (( 61 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_capl1:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_capl1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 60 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn1:TLBEntry ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn1:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn1:TLBEntry ->(24)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 59 : int):ii) (( 36 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) + +val _ = Define ` + ((get_TLBEntry_c1:TLBEntry ->(3)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_c1:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c1:TLBEntry ->(3)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 35 : int):ii) (( 33 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_d1:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_d1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 32 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_v1:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_v1:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v1:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 31 : int):ii) (( 31 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_caps0:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_caps0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_caps0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 30 : int):ii) (( 30 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_capl0:TLBEntry ->(1)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_capl0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_capl0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 29 : int):ii) (( 29 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) + +val _ = Define ` + ((get_TLBEntry_pfn0:TLBEntry ->(24)words$word) v= + ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) : 24 words$word)))`; + + +(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_pfn0:((regstate),(register_value),(TLBEntry))register_ref ->(24)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_pfn0:TLBEntry ->(24)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 28 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) + +val _ = Define ` + ((get_TLBEntry_c0:TLBEntry ->(3)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)))`; + + +(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_c0:((regstate),(register_value),(TLBEntry))register_ref ->(3)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_c0:TLBEntry ->(3)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 4 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_d0:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_d0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_d0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) + +val _ = Define ` + ((get_TLBEntry_v0:TLBEntry ->(1)words$word) v= ((subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_TLBEntry_v0:((regstate),(register_value),(TLBEntry))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec r.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) + +val _ = Define ` + ((update_TLBEntry_v0:TLBEntry ->(1)words$word -> TLBEntry) v x= + ((v with<| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec v.TLBEntry_TLBEntry_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +val _ = Define ` +((TLBEntries:(((regstate),(register_value),(TLBEntry))register_ref)list)= + ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref; + TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref; + TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref; + TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref; + TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref; + TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref; + TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref; + TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref; + TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref; + TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;TLBEntry00_ref]))`; + + +(*val undefined_StatusReg : unit -> M StatusReg*) + +val _ = Define ` + ((undefined_StatusReg:unit ->(regstate)sail2_state_monad$sequential_state ->(((StatusReg),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 words$word) . + sail2_state_monad$returnS (<| StatusReg_StatusReg_chunk_0 := w__0 |>))))`; + + +(*val Mk_StatusReg : mword ty32 -> StatusReg*) + +val _ = Define ` + ((Mk_StatusReg:(32)words$word -> StatusReg) v= + (<| StatusReg_StatusReg_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`; + + +val _ = Define ` + ((get_StatusReg_bits:StatusReg ->(32)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; + + +val _ = Define ` + ((set_StatusReg_bits:((regstate),(register_value),(StatusReg))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_StatusReg_bits:StatusReg ->(32)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_CU : StatusReg -> mword ty4*) + +val _ = Define ` + ((get_StatusReg_CU:StatusReg ->(4)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)))`; + + +(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) + +val _ = Define ` + ((set_StatusReg_CU:((regstate),(register_value),(StatusReg))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_CU:StatusReg ->(4)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 31 : int):ii) (( 28 : int):ii) + ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_BEV : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_BEV:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_BEV:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_BEV:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_IM : StatusReg -> mword ty8*) + +val _ = Define ` + ((get_StatusReg_IM:StatusReg ->(8)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))`; + + +(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_StatusReg_IM:((regstate),(register_value),(StatusReg))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_IM:StatusReg ->(8)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 15 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_KX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_KX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_KX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_KX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_SX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_SX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_SX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_SX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_UX : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_UX:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_UX:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_UX:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_KSU : StatusReg -> mword ty2*) + +val _ = Define ` + ((get_StatusReg_KSU:StatusReg ->(2)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))`; + + +(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) + +val _ = Define ` + ((set_StatusReg_KSU:((regstate),(register_value),(StatusReg))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_KSU:StatusReg ->(2)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 4 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_ERL : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_ERL:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_ERL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_ERL:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_EXL : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_EXL:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_EXL:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_EXL:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_StatusReg_IE : StatusReg -> mword ty1*) + +val _ = Define ` + ((get_StatusReg_IE:StatusReg ->(1)words$word) v= + ((subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_StatusReg_IE:((regstate),(register_value),(StatusReg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec r.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) + +val _ = Define ` + ((update_StatusReg_IE:StatusReg ->(1)words$word -> StatusReg) v x= + ((v with<| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec v.StatusReg_StatusReg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val execute_branch : mword ty64 -> M unit*) + +val _ = Define ` + ((execute_branch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pc= (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPC_ref pc) (sail2_state_monad$write_regS branchPending_ref (vec_of_bits [B1] : 1 words$word))))`; + + +(*val NotWordVal : mword ty64 -> bool*) + +val _ = Define ` + ((NotWordVal:(64)words$word -> bool) word= + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):ii))) : 1 words$word)) (( 32 : int):ii) + : 32 words$word)) <> ((subrange_vec_dec word (( 63 : int):ii) (( 32 : int):ii) : 32 words$word))))`; + + +(*val rGPR : mword ty5 -> M (mword ty64)*) + +val _ = Define ` + ((rGPR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx= + (let i = (lem$w2ui idx) in + if (((i = (( 0 : int):ii)))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 bits) list) . + sail2_state_monad$returnS ((access_list_dec w__0 i : 64 words$word)))))`; + + +(*val wGPR : mword ty5 -> mword ty64 -> M unit*) + +val _ = Define ` + ((wGPR:(5)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx v= + (let i = (lem$w2ui idx) in + if (((i <> (( 0 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . + sail2_state_monad$write_regS GPR_ref ((update_list_dec w__0 i v : ( 64 words$word) list))) + else sail2_state_monad$returnS () ))`; + + + + + + + + + + + + + + + + +(*val Exception_of_num : integer -> Exception*) + +val _ = Define ` + ((Exception_of_num:int -> Exception) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Interrupt + else if (((p0_ = (( 1 : int):ii)))) then TLBMod + else if (((p0_ = (( 2 : int):ii)))) then TLBL + else if (((p0_ = (( 3 : int):ii)))) then TLBS + else if (((p0_ = (( 4 : int):ii)))) then AdEL + else if (((p0_ = (( 5 : int):ii)))) then AdES + else if (((p0_ = (( 6 : int):ii)))) then Sys + else if (((p0_ = (( 7 : int):ii)))) then Bp + else if (((p0_ = (( 8 : int):ii)))) then ResI + else if (((p0_ = (( 9 : int):ii)))) then CpU + else if (((p0_ = (( 10 : int):ii)))) then Ov + else if (((p0_ = (( 11 : int):ii)))) then Tr + else if (((p0_ = (( 12 : int):ii)))) then C2E + else if (((p0_ = (( 13 : int):ii)))) then C2Trap + else if (((p0_ = (( 14 : int):ii)))) then XTLBRefillL + else if (((p0_ = (( 15 : int):ii)))) then XTLBRefillS + else if (((p0_ = (( 16 : int):ii)))) then XTLBInvL + else if (((p0_ = (( 17 : int):ii)))) then XTLBInvS + else MCheck))`; + + +(*val num_of_Exception : Exception -> integer*) + +val _ = Define ` + ((num_of_Exception:Exception -> int) arg_= + ((case arg_ of + Interrupt => (( 0 : int):ii) + | TLBMod => (( 1 : int):ii) + | TLBL => (( 2 : int):ii) + | TLBS => (( 3 : int):ii) + | AdEL => (( 4 : int):ii) + | AdES => (( 5 : int):ii) + | Sys => (( 6 : int):ii) + | Bp => (( 7 : int):ii) + | ResI => (( 8 : int):ii) + | CpU => (( 9 : int):ii) + | Ov => (( 10 : int):ii) + | Tr => (( 11 : int):ii) + | C2E => (( 12 : int):ii) + | C2Trap => (( 13 : int):ii) + | XTLBRefillL => (( 14 : int):ii) + | XTLBRefillS => (( 15 : int):ii) + | XTLBInvL => (( 16 : int):ii) + | XTLBInvS => (( 17 : int):ii) + | MCheck => (( 18 : int):ii) + )))`; + + +(*val undefined_Exception : unit -> M Exception*) + +val _ = Define ` + ((undefined_Exception:unit ->(regstate)sail2_state_monad$sequential_state ->(((Exception),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`; + + +(*val ExceptionCode : Exception -> mword ty5*) + +val _ = Define ` + ((ExceptionCode:Exception ->(5)words$word) ex= + (let (x : 8 bits) = + ((case ex of + Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : 8 words$word) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : 8 words$word) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : 8 words$word) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : 8 words$word) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : 8 words$word) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : 8 words$word) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : 8 words$word) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : 8 words$word) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : 8 words$word) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : 8 words$word) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : 8 words$word) + )) in + (subrange_vec_dec x (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)))`; + + +(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) + +val _ = Define ` + ((SignalExceptionMIPS:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex kccBase= (sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS inBranchDelay_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):ii) : 64 words$word))) + (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : 1 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : 1 words$word)))) + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__4 : StatusReg) . + let vectorOffset = + (if ((bits_to_bool ((get_StatusReg_EXL w__4 : 1 words$word)))) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__5 : StatusReg) . + let (vectorBase : 64 bits) = + (if ((bits_to_bool ((get_StatusReg_BEV w__5 : 1 words$word)))) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) in sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((mips_sign_extend (( 64 : int):ii) vectorOffset : 64 words$word)) : 64 words$word)) + kccBase + : 64 words$word))) + (set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex : 5 words$word)))) + (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : 1 words$word))) (sail2_state_monad$throwS (ISAException () )))))))`; + + +(*val SignalException : forall 'o. Exception -> M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*) + +val _ = Define ` + ((SignalException:Exception ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex= + (SignalExceptionMIPS ex + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))`; + + +val _ = Define ` + ((SignalExceptionBadAddr:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr= (sail2_state_monad$seqS (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`; + + +(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) + +val _ = Define ` + ((SignalExceptionTLB:Exception ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(('o,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) ex badAddr= (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0BadVAddr_ref badAddr) + (set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):ii) (( 13 : int):ii) : 19 words$word)))) + (set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))) + (set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (SignalException ex)))`; + + +(*val MemAccessType_of_num : integer -> MemAccessType*) + +val _ = Define ` + ((MemAccessType_of_num:int -> MemAccessType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Instruction + else if (((p0_ = (( 1 : int):ii)))) then LoadData + else StoreData))`; + + +(*val num_of_MemAccessType : MemAccessType -> integer*) + +val _ = Define ` + ((num_of_MemAccessType:MemAccessType -> int) arg_= + ((case arg_ of Instruction => (( 0 : int):ii) | LoadData => (( 1 : int):ii) | StoreData => (( 2 : int):ii) )))`; + + +(*val undefined_MemAccessType : unit -> M MemAccessType*) + +val _ = Define ` + ((undefined_MemAccessType:unit ->(regstate)sail2_state_monad$sequential_state ->(((MemAccessType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [Instruction;LoadData;StoreData]))`; + + +(*val AccessLevel_of_num : integer -> AccessLevel*) + +val _ = Define ` + ((AccessLevel_of_num:int -> AccessLevel) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then User + else if (((p0_ = (( 1 : int):ii)))) then Supervisor + else Kernel))`; + + +(*val num_of_AccessLevel : AccessLevel -> integer*) + +val _ = Define ` + ((num_of_AccessLevel:AccessLevel -> int) arg_= + ((case arg_ of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`; + + +(*val undefined_AccessLevel : unit -> M AccessLevel*) + +val _ = Define ` + ((undefined_AccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [User;Supervisor;Kernel]))`; + + +(*val int_of_AccessLevel : AccessLevel -> ii*) + +val _ = Define ` + ((int_of_AccessLevel:AccessLevel -> int) level= + ((case level of User => (( 0 : int):ii) | Supervisor => (( 1 : int):ii) | Kernel => (( 2 : int):ii) )))`; + + +(* +Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + *) +(*val grantsAccess : AccessLevel -> AccessLevel -> bool*) + +val _ = Define ` + ((grantsAccess:AccessLevel -> AccessLevel -> bool) currentLevel requiredLevel= + (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`; + + +(* +Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. + *) +(*val getAccessLevel : unit -> M AccessLevel*) + +val _ = Define ` + ((getAccessLevel:unit ->(regstate)sail2_state_monad$sequential_state ->(((AccessLevel),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_EXL w__0 : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__1 : StatusReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_StatusReg_ERL w__1 : 1 words$word))))))) (\ (w__2 : bool) . + if w__2 then sail2_state_monad$returnS Kernel + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__3 : StatusReg) . + let p__27 = ((get_StatusReg_KSU w__3 : 2 words$word)) in + let b__0 = p__27 in + sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then User + else User)))))`; + + +(*val checkCP0Access : unit -> M unit*) + +val _ = Define ` + ((checkCP0Access:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (getAccessLevel () ) (\ accessLevel . sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((accessLevel <> Kernel)))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + sail2_state_monad$returnS ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))))))))) (\ (w__1 : + bool) . + if w__1 then sail2_state_monad$seqS + (set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : 2 words$word)) (SignalException CpU) + else sail2_state_monad$returnS () ))))`; + + +(*val incrementCP0Count : unit -> M unit*) + +val _ = Define ` + ((incrementCP0Count:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__1 : 6 words$word) . sail2_state_monad$bindS + (if (((w__0 = w__1))) then sail2_state_monad$returnS TLBIndexMax + else sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : 6 words$word) . + sail2_state_monad$returnS ((sub_vec_int w__2 (( 1 : int):ii) : 6 words$word)))) (\ (w__3 : 6 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBRandom_ref w__3) + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__4 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):ii) : 32 words$word))) + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M)) (\ (w__5 : 32 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__6 : 32 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (if (((w__5 = w__6))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__7 : CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 : 8 words$word)) + (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + : 8 words$word))) + else sail2_state_monad$returnS () ) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__8 : StatusReg) . + let ims = ((get_StatusReg_IM w__8 : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__9 : CauseReg) . + let ips = ((get_CauseReg_IP w__9 : 8 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__10 : StatusReg) . + let ie = ((get_StatusReg_IE w__10 : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__11 : StatusReg) . + let exl = ((get_StatusReg_EXL w__11 : 1 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__12 : StatusReg) . + let erl = ((get_StatusReg_ERL w__12 : 1 words$word)) in + if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims : 8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))))))))) then + SignalException Interrupt + else sail2_state_monad$returnS () )))))))))))))`; + + +(*val decode_failure_of_num : integer -> decode_failure*) + +val _ = Define ` + ((decode_failure_of_num:int -> decode_failure) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then No_matching_pattern + else if (((p0_ = (( 1 : int):ii)))) then Unsupported_instruction + else if (((p0_ = (( 2 : int):ii)))) then Illegal_instruction + else Internal_error))`; + + +(*val num_of_decode_failure : decode_failure -> integer*) + +val _ = Define ` + ((num_of_decode_failure:decode_failure -> int) arg_= + ((case arg_ of no_matching_pattern => (( 0 : int): ii) )))`; + + +(*val undefined_decode_failure : unit -> M decode_failure*) + +val _ = Define ` + ((undefined_decode_failure:unit ->(regstate)sail2_state_monad$sequential_state ->(((decode_failure),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$internal_pickS [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`; + + +(*val Comparison_of_num : integer -> Comparison*) + +val _ = Define ` + ((Comparison_of_num:int -> Comparison) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then EQ' + else if (((p0_ = (( 1 : int):ii)))) then NE + else if (((p0_ = (( 2 : int):ii)))) then GE + else if (((p0_ = (( 3 : int):ii)))) then GEU + else if (((p0_ = (( 4 : int):ii)))) then GT' + else if (((p0_ = (( 5 : int):ii)))) then LE + else if (((p0_ = (( 6 : int):ii)))) then LT' + else LTU))`; + + +(*val num_of_Comparison : Comparison -> integer*) + +val _ = Define ` + ((num_of_Comparison:Comparison -> int) arg_= + ((case arg_ of + EQ' => (( 0 : int):ii) + | NE => (( 1 : int):ii) + | GE => (( 2 : int):ii) + | GEU => (( 3 : int):ii) + | GT' => (( 4 : int):ii) + | LE => (( 5 : int):ii) + | LT' => (( 6 : int):ii) + | LTU => (( 7 : int):ii) + )))`; + + +(*val undefined_Comparison : unit -> M Comparison*) + +val _ = Define ` + ((undefined_Comparison:unit ->(regstate)sail2_state_monad$sequential_state ->(((Comparison),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`; + + +(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) + +val _ = Define ` + ((compare:Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB= + ((case cmp of + EQ' => (valA = valB) + | NE => (valA <> valB) + | GE => zopz0zKzJ_s valA valB + | GEU => zopz0zKzJ_u valA valB + | GT' => zopz0zI_s valB valA + | LE => zopz0zKzJ_s valB valA + | LT' => zopz0zI_s valA valB + | LTU => zopz0zI_u valA valB + )))`; + + +(*val WordType_of_num : integer -> WordType*) + +val _ = Define ` + ((WordType_of_num:int -> WordType) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then B + else if (((p0_ = (( 1 : int):ii)))) then H + else if (((p0_ = (( 2 : int):ii)))) then W0 + else D))`; + + +(*val num_of_WordType : WordType -> integer*) + +val _ = Define ` + ((num_of_WordType:WordType -> int) arg_= + ((case arg_ of B => (( 0 : int):ii) | H => (( 1 : int):ii) | W0 => (( 2 : int):ii) | D => (( 3 : int):ii) )))`; + + +(*val undefined_WordType : unit -> M WordType*) + +val _ = Define ` + ((undefined_WordType:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordType),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [B;H;W0;D]))`; + + +(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*) + +val _ = Define ` + ((WordTypeUnaligned_of_num:int -> WordTypeUnaligned) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then WL + else if (((p0_ = (( 1 : int):ii)))) then WR + else if (((p0_ = (( 2 : int):ii)))) then DL + else DR))`; + + +(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*) + +val _ = Define ` + ((num_of_WordTypeUnaligned:WordTypeUnaligned -> int) arg_= + ((case arg_ of WL => (( 0 : int):ii) | WR => (( 1 : int):ii) | DL => (( 2 : int):ii) | DR => (( 3 : int):ii) )))`; + + +(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*) + +val _ = Define ` + ((undefined_WordTypeUnaligned:unit ->(regstate)sail2_state_monad$sequential_state ->(((WordTypeUnaligned),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state$internal_pickS [WL;WR;DL;DR]))`; + + +(*val wordWidthBytes : WordType -> integer*) + +val _ = Define ` + ((wordWidthBytes:WordType -> int) w= ((case w of B => (( 1 : int):ii) | H => (( 2 : int):ii) | W0 => (( 4 : int):ii) | D => (( 8 : int):ii) )))`; + + +val _ = Define ` + ((alignment_width:int)= ((( 16 : int):ii)))`; + + +(*val isAddressAligned : mword ty64 -> WordType -> bool*) + +val _ = Define ` + ((isAddressAligned:(64)words$word -> WordType -> bool) addr wordType= + (let a = (lem$w2ui addr) in + (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):ii))) / + alignment_width)))))`; + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_wrapper:int ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (p8_times_n___tv : int) addr size1= + (if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS UART_RVALID_ref : ( 1 words$word) M) (\ rvalid . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_RVALID_ref (vec_of_bits [B0] : 1 words$word)) + (sail2_state_monad$read_regS UART_RDATA_ref : ( 8 words$word) M)) (\ (w__0 : 8 bits) . + sail2_state_monad$returnS ((mask p8_times_n___tv + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec w__0 + ((concat_vec rvalid + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 16 words$word) + : 23 words$word)) + : 24 words$word)) + : 32 words$word)) + : 64 words$word)) + : 'p8_times_n_ words$word)))) + else if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : 64 words$word)))) then + sail2_state_monad$returnS ((mask p8_times_n___tv + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; + B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : 64 words$word) + : 'p8_times_n_ words$word)) + else sail2_state_monad$bindS + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__1 . + sail2_state_monad$returnS ((reverse_endianness w__1 : 'p8_times_n_ words$word)))))`; + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +val _ = Define ` + ((MEMr_reserve_wrapper:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->((('p8_times_n_ words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$bindS + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 : ( 'p8_times_n_ words$word) M) (\ w__0 . + sail2_state_monad$returnS ((reverse_endianness w__0 : 'p8_times_n_ words$word)))))`; + + +(*val init_cp0_state : unit -> M unit*) + +val _ = Define ` + ((init_cp0_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 : 1 words$word))))`; + + +(*val init_cp2_state : unit -> M unit*) + +(*val cp2_next_pc : unit -> M unit*) + +(*val dump_cp2_state : unit -> M unit*) + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((extz_vec m__tv v : 'm words$word)))`; + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +val _ = Define ` + ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v= ((exts_vec m__tv v : 'm words$word)))`; + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +val _ = Define ` + ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l= + (let (one1 : 'n bits) = ((extzv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftl ((sub_vec ((shiftl one1 l : 'n words$word)) one1 : 'n words$word)) i : 'n words$word)))`; + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= + (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0] : 1 words$word) : 'n words$word))))`; + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j= + (let (m : 'n bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i)) : 'n words$word)) in + (((and_vec xs m : 'n words$word)) = m)))`; + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +val _ = Define ` + ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + let ys = + ((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l' : 'm words$word)) : 'm words$word)) i' + : 'm words$word)) in + (or_vec ((shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)) ((extzv r__tv ys : 'r words$word)) + : 'r words$word)))`; + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +val _ = Define ` + ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv r__tv xs : 'r words$word)) l' : 'r words$word)))`; + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +val _ = Define ` + ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j')) : 'n words$word)) : 'n words$word)) + j' + : 'n words$word)) in + (xs = ys)))`; + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +val _ = Define ` + ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j')) : 'm words$word)) : 'm words$word)) + j' + : 'm words$word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs : 's words$word)) i' : 's words$word)) + ((j' - (( 1 : int):ii))) + : 's words$word)) ((extzv s__tv ys : 's words$word)) + : 's words$word)))`; + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) j + : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (shiftl ((extzv m__tv xs : 'm words$word)) shift : 'm words$word)))`; + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + (extzv m__tv xs : 'm words$word)))`; + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +val _ = Define ` + ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l= + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) + ((((((int_of_num (words$word_len xs))) - i)) - l)) + : 'n words$word)) ((((int_of_num (words$word_len xs))) - l)) + : 'n words$word)) in + (extsv m__tv xs : 'm words$word)))`; + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_slice:'n words$word -> int -> int -> int) xs i l= + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l : 'n words$word)) : 'n words$word)) i : 'n words$word)) in + lem$w2ui xs))`; + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +val _ = Define ` + ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j= + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j)) : 'n words$word)) : 'n words$word)) i + : 'n words$word)) in + lem$w2ui xs))`; + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +val _ = Define ` + ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m= + (let (v : 'n bits) = ((extsv n__tv (vec_of_bits [B1] : 1 words$word) : 'n words$word)) in + (shiftr v ((((int_of_num (words$word_len v))) - m)) : 'n words$word)))`; + + +(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) + +val _ = Define ` + ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> TLBEntry -> bool) r vpn2 asid entry= + (let entryValid = ((get_TLBEntry_valid entry : 1 words$word)) in + let entryR = ((get_TLBEntry_r entry : 2 words$word)) in + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let entryVPN = ((get_TLBEntry_vpn2 entry : 27 words$word)) in + let entryASID = ((get_TLBEntry_asid entry : 8 words$word)) in + let entryG = ((get_TLBEntry_g entry : 1 words$word)) in + let (vpnMask : 27 bits) = + ((not_vec ((mips_zero_extend (( 27 : int):ii) entryMask : 27 words$word)) : 27 words$word)) in + (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask : 27 words$word)) = ((and_vec entryVPN vpnMask : 27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`; + + +(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) + +val _ = Define ` + ((tlbSearch:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((((6)words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) VAddr= + (sail2_state_monad$catch_early_returnS + (let r = ((subrange_vec_dec VAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)) in + let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . + let asid = ((get_TLBEntryHiReg_ASID w__0 : 8 words$word)) in sail2_state_monad$seqS + (sail2_state$foreachS (index_list (( 0 : int):ii) (( 63 : int):ii) (( 1 : int):ii)) () + (\ idx unit_var . sail2_state_monad$bindS + (sail2_state_monad$liftRS (sail2_state_monad$read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (sail2_state_monad$early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):ii) : 6 itself)) idx : 6 words$word))) : (unit, ( ( 6 words$word)option)) + MR) + else sail2_state_monad$returnS () ))) + (sail2_state_monad$returnS NONE)))))`; + + +(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +val _ = Define ` + ((TLBTranslate2:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS + (tlbSearch vAddr : ( ( 6 words$word)option) M) (\ idx . + (case idx of + SOME (idx) => + let i = (lem$w2ui idx) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . + let entryMask = ((get_TLBEntry_pagemask entry : 16 words$word)) in + let b__0 = entryMask in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + sail2_state_monad$returnS (( 12 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 14 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 16 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 18 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 20 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 22 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 24 : int):ii) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 26 : int):ii) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) + then + sail2_state_monad$returnS (( 28 : int):ii) + else undefined_range (( 12 : int):ii) (( 28 : int):ii)) (\ (evenOddBit : int) . + let isOdd = (access_vec_dec vAddr evenOddBit) in + let ((caps : 1 bits), (capl : 1 bits), (pfn : 24 bits), (d : 1 bits), (v : 1 bits)) = + (if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry : 1 words$word), + (get_TLBEntry_capl1 entry : 1 words$word), + (get_TLBEntry_pfn1 entry : 24 words$word), + (get_TLBEntry_d1 entry : 1 words$word), + (get_TLBEntry_v1 entry : 1 words$word)) + else + ((get_TLBEntry_caps0 entry : 1 words$word), + (get_TLBEntry_capl0 entry : 1 words$word), + (get_TLBEntry_pfn0 entry : 24 words$word), + (get_TLBEntry_d0 entry : 1 words$word), + (get_TLBEntry_v0 entry : 1 words$word))) in + if ((~ ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + : (( 64 words$word # bool)) M) + else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr : (( 64 words$word # bool)) M) + else + let (res : 64 bits) = + ((mips_zero_extend (( 64 : int):ii) + ((subrange_subrange_concat + (((((((( 23 : int):ii) - + ((((evenOddBit - (( 12 : int):ii))) - (( 1 : int):ii))))) + + + ((evenOddBit - (( 1 : int):ii))))) + - (((( 0 : int):ii) - (( 1 : int):ii))))) pfn + (( 23 : int):ii) ((evenOddBit - (( 12 : int):ii))) vAddr + ((evenOddBit - (( 1 : int):ii))) (( 0 : int):ii) + : 36 words$word)) + : 64 words$word)) in + sail2_state_monad$returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))) + | NONE => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + : (( 64 words$word # bool)) M) + ))))`; + + +(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +val _ = Define ` + ((TLBTranslateC:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS + (getAccessLevel () ) (\ currentAccessLevel . + let compat32 = + (((subrange_vec_dec vAddr (( 61 : int):ii) (( 31 : int):ii) : 31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1] + : 31 words$word)) in + let b__0 = ((subrange_vec_dec vAddr (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)) in + let ((requiredLevel : AccessLevel), (addr : ( 64 bits)option)) = + (if (((b__0 = (vec_of_bits [B1;B1] : 2 words$word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 : int):ii) (( 29 : int):ii) : 2 words$word)) of + (T, b__1) => + if (((b__1 = (vec_of_bits [B1;B1] : 2 words$word)))) then (Kernel, NONE) + else if (((b__1 = (vec_of_bits [B1;B0] : 2 words$word)))) then (Supervisor, NONE) + else if (((b__1 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + else if (((b__1 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((subrange_vec_dec vAddr (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word)) + : 64 words$word))) + else (case (T, b__1) of (g__25, g__26) => (Kernel, NONE) ) + | (g__25, g__26) => (Kernel, NONE) + ) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (Kernel, + SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((subrange_vec_dec vAddr (( 58 : int):ii) (( 0 : int):ii) : 59 words$word)) + : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then (Supervisor, NONE) + else (User, NONE)) in + if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else sail2_state_monad$bindS + (case addr of + SOME (a) => sail2_state_monad$returnS (a, F) + | NONE => + if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):ii) (( 0 : int):ii) : 62 words$word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else (TLBTranslate2 vAddr accessType : (( 64 words$word # bool)) M) + ) (\ varstup . let ((pa : 64 bits), (c : bool)) = varstup in + if ((((lem$w2ui pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + : (( 64 words$word # bool)) M) + else sail2_state_monad$returnS (pa, c)))))`; + + +(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) + +val _ = Define ` + ((TLBTranslate:(64)words$word -> MemAccessType ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr accessType= (sail2_state_monad$bindS + (TLBTranslateC vAddr accessType : (( 64 words$word # bool)) M) (\ varstup . let (addr, c) = varstup in + sail2_state_monad$returnS addr)))`; + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +val _ = Define ` + ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data= + (let ledata = ((reverse_endianness data : 'p8_times_n_ words$word)) in + if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) + (sail2_state_monad$write_regS UART_WRITTEN_ref ((cast_unit_vec0 B1 : 1 words$word))) + else sail2_state_monad$seqS (MEMea + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) (MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata)))`; + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) + +val _ = Define ` + ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr size1 data= (sail2_state_monad$seqS + (MEMea_conditional + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) + (MEMval_conditional + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data : 'p8_times_n_ words$word)))))`; + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> mword ty64*) + +val _ = Define ` + ((addrWrapper:(64)words$word -> MemAccessType -> WordType ->(64)words$word) addr accessType width= addr)`; + + +(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> mword ty64*) + +val _ = Define ` + ((addrWrapperUnaligned:(64)words$word -> MemAccessType -> WordTypeUnaligned ->(64)words$word) addr accessType width= addr)`; + + +(*val TranslatePC : mword ty64 -> M (mword ty64)*) + +val _ = Define ` + ((TranslatePC:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr= (sail2_state_monad$seqS + (incrementCP0Count () ) + (if (((((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) <> (vec_of_bits [B0;B0] : 2 words$word)))) + then + (SignalExceptionBadAddr AdEL vAddr : ( 64 words$word) M) + else (TLBTranslate vAddr Instruction : ( 64 words$word) M))))`; + + +val _ = Define ` + ((have_cp2:bool)= F)`; + + +(*val ERETHook : unit -> unit*) + +val _ = Define ` + ((ERETHook:unit -> unit) () = () )`; + + +val _ = Define ` + ((init_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (skip () ))`; + + +val _ = Define ` + ((cp2_next_pc:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (skip () ) (skip () )))`; + + +val _ = Define ` + ((dump_cp2_state:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (skip () ) (skip () )))`; + + +(*val undefined_ast : unit -> M ast*) + +val _ = Define ` + ((undefined_ast:unit ->(regstate)sail2_state_monad$sequential_state ->(((ast),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_Comparison () ) (\ (u_0 : Comparison) . sail2_state_monad$bindS + (undefined_WordType () ) (\ (u_1 : WordType) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (u_3 : bool) . sail2_state_monad$bindS + (sail2_state_monad$undefined_boolS () ) (\ (u_2 : bool) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (u_4 : imm16) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (u_7 : regno) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (u_6 : regno) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 5 : int):ii) : ( 5 words$word) M) (\ (u_5 : regno) . sail2_state_monad$bindS + (undefined_unit () ) (\ (u_8 : unit) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii) : ( 3 words$word) M) (\ (u_9 : 3 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M) (\ (u_10 : 16 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 : int):ii) : ( 26 words$word) M) (\ (u_11 : 26 bits) . + sail2_state$internal_pickS + [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB0 (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV0 (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8]))))))))))))))`; + + +(*val execute : ast -> M unit*) + +(*val decode : mword ty32 -> maybe ast*) + +(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) + +val _ = Define ` + ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign= + (if sign then (mips_sign_extend (( 64 : int):ii) memResult : 64 words$word) + else (mips_zero_extend (( 64 : int):ii) memResult : 64 words$word)))`; + + +(*val TLBWriteEntry : mword ty6 -> M unit*) + +val _ = Define ` + ((TLBWriteEntry:(6)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) idx= (sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ pagemask . + let b__0 = pagemask in sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) + then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : 16 words$word)))) then + sail2_state_monad$returnS () + else SignalException MCheck) + (let i = (lem$w2ui idx) in + let entry = (access_list_dec TLBEntries i) in sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_pagemask entry pagemask) + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 : 2 words$word))) + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__1 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 : 27 words$word))) + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__2 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 : 8 words$word))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__3 : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . + sail2_state_monad$returnS ((bits_to_bool ((get_TLBEntryLoReg_G w__4 : 1 words$word)))))))) (\ (w__5 : bool) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_TLBEntry_g entry ((bool_to_bits w__5 : 1 words$word))) + (set_TLBEntry_valid entry ((cast_unit_vec0 B1 : 1 words$word)))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__6 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__7 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__8 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 : 24 words$word))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__9 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 : 3 words$word))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__10 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo0_ref)) (\ (w__11 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__12 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__13 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__14 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 : 24 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__15 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 : 3 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__16 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 : 1 words$word))) + (sail2_state_monad$read_regS TLBEntryLo1_ref)) (\ (w__17 : TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 : 1 words$word))))))))))))))))))))))`; + + +val _ = Define ` + ((decode:(32)words$word ->(ast)option) v__0= + (if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (DADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (DADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DADD (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (ADD (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ADDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (ADDU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ADDIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSUB (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SUB0 (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SUBU (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (AND (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ANDI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (OR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (ORI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (NOR (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (XOR (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (XORI (rs,rt,imm)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LUI (rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSLL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRA32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : 5 bits) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (DSRL32 (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (DSRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SLL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SRA (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SRAV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sa : regno) = ((subrange_vec_dec v__0 (( 10 : int):ii) (( 6 : int):ii) : 5 words$word)) in + SOME (SRL (rt,rd,sa)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SRLV (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLT (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SLTI (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (SLTU (rs,rt,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SLTIU (rs,rt,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MOVN (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MOVZ (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MFHI rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : 11 words$word))))))) then + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MFLO rd) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : 21 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (MTHI rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 0 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : 21 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (MTLO rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 11 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (MUL (rs,rt,rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DMULT (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DMULTU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MADD (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MADDU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MSUB (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (MSUBU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DIV0 (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DIVU (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DDIV (rs,rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 16 words$word))))))) + then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (DDIVU (rs,rt)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii) : 26 words$word)) in + SOME (J offset) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (offset : 26 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 0 : int):ii) : 26 words$word)) in + SOME (JAL offset) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 11 : int):ii) : 10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0] : 6 words$word)))))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + SOME (JR rs) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1] : 6 words$word)))))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (JALR (rs,rd)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,F,T)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,F)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1] : 6 words$word)))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BEQ (rs,rt,imm,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LT',T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GE,T,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,GT',F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (BCMPZ (rs,imm,LE,F,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0] : 6 words$word))))))) then + SOME (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1] : 6 words$word))))))) then + SOME (BREAK () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0] + : 32 words$word)))) then + SOME (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,LTU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0] : 6 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + SOME (TRAPREG (rs,rt,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,EQ')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,NE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GE)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,GEU)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LT')) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1] : 6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))))) then + let (rs : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (TRAPIMM (rs,imm,LTU)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (B,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (B,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (H,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (H,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,T,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (D,F,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (W0,T,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Load (D,F,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (B,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (H,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (W0,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (D,F,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (W0,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (Store (D,T,base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SWL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SWR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (LDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SDL (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (offset : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (SDR (base,rt,offset)) + else if (((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1] : 6 words$word)))) then + let (base : regno) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 21 : int):ii) : 5 words$word)) in + let (op : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (imm : imm16) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) in + SOME (CACHE (base,op,imm)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 11 : int):ii) : 21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1] : 6 words$word))))))) then + SOME (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MFC0 (rt,rd,sel,T)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word))))))) + then + SOME (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,F)) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 3 : int):ii) : 8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + let (sel : 3 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + SOME (MTC0 (rt,rd,sel,T)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B0] + : 32 words$word)))) then + SOME (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B1;B0] + : 32 words$word)))) then + SOME (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1] + : 32 words$word)))) then + SOME (TLBR () ) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 21 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : 11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):ii) (( 0 : int):ii) : 11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : 11 words$word))))))) then + let (rt : regno) = ((subrange_vec_dec v__0 (( 20 : int):ii) (( 16 : int):ii) : 5 words$word)) in + let (rd : regno) = ((subrange_vec_dec v__0 (( 15 : int):ii) (( 11 : int):ii) : 5 words$word)) in + SOME (RDHWR (rt,rd)) + else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B1;B1;B0;B0;B0] + : 32 words$word)))) then + SOME (ERET () ) + else SOME (RI () )))`; + + +(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((xor_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_WAIT : unit -> M unit*) + +val _ = Define ` + ((execute_WAIT:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__16= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS nextPC_ref w__0)))`; + + +(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) + +val _ = Define ` + ((execute_TRAPREG:(5)words$word ->(5)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt cmp= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else sail2_state_monad$returnS () ))))`; + + +(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) + +val _ = Define ` + ((execute_TRAPIMM:(5)words$word ->(16)words$word -> Comparison ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + let (imm_val : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) in + let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else sail2_state_monad$returnS () )))`; + + +(*val execute_TLBWR : unit -> M unit*) + +val _ = Define ` + ((execute_TLBWR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__20= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBWI : unit -> M unit*) + +val _ = Define ` + ((execute_TLBWI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__19= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : 6 words$word) . TLBWriteEntry w__0)))`; + + +(*val execute_TLBR : unit -> M unit*) + +val _ = Define ` + ((execute_TLBR:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__21= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M)) (\ (w__0 : TLBIndexT) . + let i = (lem$w2ui w__0) in sail2_state_monad$bindS + (sail2_state_monad$read_regS ((access_list_dec TLBEntries i))) (\ entry . sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry : 16 words$word))) + (set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry : 2 words$word)))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry : 8 words$word)))) + (set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry : 1 words$word)))) + (set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry : 1 words$word)))) + (set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry : 24 words$word)))) + (set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry : 3 words$word)))) + (set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry : 1 words$word)))) + (set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry : 1 words$word)))) + (set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry : 1 words$word)))) + (set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry : 1 words$word)))) + (set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry : 1 words$word)))) + (set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry : 24 words$word)))) + (set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry : 3 words$word)))) + (set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry : 1 words$word)))) + (set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry : 1 words$word)))) + (set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry : 1 words$word)))))))`; + + +(*val execute_TLBP : unit -> M unit*) + +val _ = Define ` + ((execute_TLBP:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (sail2_state_monad$read_regS TLBEntryHi_ref)) (\ (w__0 : TLBEntryHiReg) . sail2_state_monad$bindS + (tlbSearch ((get_TLBEntryHiReg_bits w__0 : 64 words$word)) : ( ( 6 words$word)option) M) (\ result . + (case result of + SOME (idx) => sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B0] : 1 words$word)) (sail2_state_monad$write_regS TLBIndex_ref idx) + | NONE => sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)) + )))))`; + + +(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_Store:WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width conditional base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (vAddr : 64 bits) = + ((addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + StoreData width + : 64 words$word)) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . + if conditional then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0LLBit_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . sail2_state_monad$bindS + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):ii))))) then + (case width of + W0 => + MEMw_conditional_wrapper pAddr (( 4 : int):ii) + ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_conditional_wrapper pAddr (( 8 : int):ii) rt_val + | _ => sail2_state_monad$throwS (Error_internal_error () ) + ) + else sail2_state_monad$returnS F) (\ (success : bool) . + wGPR rt ((mips_zero_extend (( 64 : int):ii) ((bool_to_bits success : 1 words$word)) : 64 words$word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec rt_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + | H => MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec rt_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + | W0 => MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec rt_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + | D => MEMw_wrapper pAddr (( 8 : int):ii) rt_val + ))))))`; + + +(*val execute_SYSCALL : unit -> M unit*) + +val _ = Define ` + ((execute_SYSCALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__14= (SignalException Sys))`; + + +(*val execute_SYNC : unit -> M unit*) + +val _ = Define ` + ((execute_SYNC:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__17= (MEM_sync () ))`; + + +(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData + WR + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . + let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__12 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + if (((b__12 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + else if (((b__12 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + else if (((b__12 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + else MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))))))`; + + +(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData + WL + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__8 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + if (((b__8 = (vec_of_bits [B0;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if (((b__8 = (vec_of_bits [B0;B1] : 2 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + else if (((b__8 = (vec_of_bits [B1;B0] : 2 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)))))))`; + + +(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((mips_sign_extend (( 64 : int):ii) + ((sub_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (temp33 : 33 bits) = + ((sub_vec + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rd + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec temp33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + if ((NotWordVal temp)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_right + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + if ((NotWordVal temp)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_right + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + if ((NotWordVal temp)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_right_arith + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + if ((NotWordVal temp)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let rt32 = ((subrange_vec_dec temp (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_right_arith + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rt_val . + wGPR rd + ((mips_zero_extend (( 64 : int):ii) + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rs_val . + let (immext : 64 bits) = ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) in + wGPR rt + ((mips_zero_extend (( 64 : int):ii) + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= + (let imm_val = (integer_word$w2i imm) in sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rs_val = (integer_word$w2i w__0) in + wGPR rt + ((mips_zero_extend (( 64 : int):ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word)))))`; + + +(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd + ((mips_zero_extend (( 64 : int):ii) + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : 1 words$word) + else (vec_of_bits [B0] : 1 words$word)) + : 64 words$word))))))`; + + +(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__2 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__2 : 64 words$word)))))))`; + + +(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rt32 = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + wGPR rd ((mips_sign_extend (( 64 : int):ii) w__1 : 64 words$word))))))`; + + +(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData + DR + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) in + let b__40 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + if (((b__40 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + else if (((b__40 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + else if (((b__40 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + else if (((b__40 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + else if (((b__40 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper wordAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + else MEMw_wrapper wordAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + + +(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) StoreData + DL + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr StoreData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__32 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + if (((b__32 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 8 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + else if (((b__32 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 7 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 6 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + else if (((b__32 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 5 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 4 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + else if (((b__32 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + MEMw_wrapper pAddr (( 3 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + else if (((b__32 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + MEMw_wrapper pAddr (( 2 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + else MEMw_wrapper pAddr (( 1 : int):ii) ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)))))))`; + + +(*val execute_RI : unit -> M unit*) + +val _ = Define ` + ((execute_RI:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24= (SignalException ResI))`; + + +(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_RDHWR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd= (sail2_state_monad$bindS + (getAccessLevel () ) (\ accessLevel . + let (haveAccessLevel : bool) = (accessLevel = Kernel) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__0 : StatusReg) . + let (haveCU0 : bool) = + (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 : 4 words$word)) (( 0 : int):ii)))) in + let rdi = (lem$w2ui rd) in sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__1 : 32 bits) . + let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in sail2_state_monad$seqS + (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI + else sail2_state_monad$returnS () ) + (let b__146 = rd in sail2_state_monad$bindS + (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__2 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2 : 64 words$word))) + else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word)) + else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))) then + (sail2_state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + else (SignalException ResI : ( 64 words$word) M)) (\ (temp : 64 bits) . + wGPR rt temp)))))))`; + + +(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((or_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 : 64 words$word)) : 64 words$word))))))`; + + +(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))`; + + +(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (result : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))`; + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . + let (result : 64 bits) = + ((mips_sign_extend (( 64 : int):ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (w__1 : 64 words$word) . + wGPR rd w__1)))))`; + + +(*val execute_MTLO : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MTLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS LO_ref w__0)))`; + + +(*val execute_MTHI : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MTHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$write_regS HI_ref w__0)))`; + + +(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +val _ = Define ` + ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (rGPR rt : ( 64 words$word) M)) (\ reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS TLBIndex_ref ((mask (( 6 : int):ii) reg_val : 6 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS () + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 23 : int):ii) : 41 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0UserLocal_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 : int):ii) (( 13 : int):ii) : 16 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBWired_ref ((mask (( 6 : int):ii) reg_val : 6 words$word))) + (sail2_state_monad$write_regS TLBRandom_ref TLBIndexMax) + else if ((((((b__108 = (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS + CP0HWREna_ref + ((concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 29 : int):ii) : 3 words$word)) + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0] + : 25 words$word) ((subrange_vec_dec reg_val (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 29 words$word)) + : 32 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS () + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0Count_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 62 : int):ii) : 2 words$word))) + (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 : int):ii) (( 13 : int):ii) : 27 words$word)))) + (set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Compare_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) + (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__0 : CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec ((get_CauseReg_IP w__0 : 8 words$word)) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word) + : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 : int):ii) (( 28 : int):ii) : 4 words$word))) + (set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 : int):ii))) : 1 words$word)))) + (set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)))) + (set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 : int):ii))) : 1 words$word)))) + (set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 : int):ii))) : 1 words$word)))) + (set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 : int):ii))) : 1 words$word)))) + (set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)))) + (set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 : int):ii))) : 1 words$word)))) + (set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 : int):ii))) : 1 words$word)))) + (set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 : int):ii))) : 1 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 : int):ii))) : 1 words$word))) + (sail2_state_monad$read_regS CP0Cause_ref)) (\ (w__1 : CauseReg) . + let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec ((subrange_vec_dec ip (( 7 : int):ii) (( 2 : int):ii) : 6 words$word)) + ((subrange_vec_dec reg_val (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)) + : 8 words$word))) + else if ((((((b__108 = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0EPC_ref reg_val + else if ((((((b__108 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) + else if ((((((b__108 = (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + set_XContextReg_XPTEBase TLBXContext_ref + ((subrange_vec_dec reg_val (( 63 : int):ii) (( 33 : int):ii) : 31 words$word)) + else if ((((((b__108 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$write_regS CP0ErrorEPC_ref reg_val + else SignalException ResI + ))))`; + + +(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MSUBU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; + + +(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MSUB:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) mul_result + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; + + +(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else sail2_state_monad$returnS () )))`; + + +(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))) then sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1) + else sail2_state_monad$returnS () )))`; + + +(*val execute_MFLO : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MFLO:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFHI : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MFHI:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0)))`; + + +(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +val _ = Define ` + ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sel double= (sail2_state_monad$bindS (sail2_state_monad$seqS + (checkCP0Access () ) + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBIndex_ref : ( 6 words$word) M) (\ (w__0 : TLBIndexT) . + let (idx : 31 bits) = ((mips_zero_extend (( 31 : int):ii) w__0 : 31 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBProbe_ref : ( 1 words$word) M) (\ (w__1 : 1 bits) . + sail2_state_monad$returnS ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) ((concat_vec w__1 idx : 32 words$word)) + : 64 words$word)))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBRandom_ref : ( 6 words$word) M) (\ (w__2 : TLBIndexT) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__2 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryLo0_ref) (\ (w__3 : TLBEntryLoReg) . + sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__3 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryLo1_ref) (\ (w__4 : TLBEntryLoReg) . + sail2_state_monad$returnS ((get_TLBEntryLoReg_bits w__4 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBContext_ref) (\ (w__5 : ContextReg) . + sail2_state_monad$returnS ((get_ContextReg_bits w__5 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0UserLocal_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBPageMask_ref : ( 16 words$word) M) (\ (w__7 : 16 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + : 28 words$word)) + : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBWired_ref : ( 6 words$word) M) (\ (w__8 : TLBIndexT) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__8 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0HWREna_ref : ( 32 words$word) M) (\ (w__9 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__9 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0BadVAddr_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Count_ref : ( 32 words$word) M) (\ (w__11 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__11 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBEntryHi_ref) (\ (w__12 : TLBEntryHiReg) . + sail2_state_monad$returnS ((get_TLBEntryHiReg_bits w__12 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Compare_ref : ( 32 words$word) M) (\ (w__13 : 32 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) w__13 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Status_ref) (\ (w__14 : StatusReg) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_StatusReg_bits w__14 : 32 words$word)) : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0Cause_ref) (\ (w__15 : CauseReg) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) ((get_CauseReg_bits w__15 : 32 words$word)) : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0ConfigK0_ref : ( 3 words$word) M) (\ (w__17 : 3 bits) . + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 15 words$word) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec (vec_of_bits [B1;B0] : 2 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + w__17 + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 15 words$word)) + : 16 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec TLBIndexMax + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec + ((bool_to_bits have_cp2 : 1 words$word)) + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] : 1 words$word) + ((concat_vec + (vec_of_bits [B0] + : 1 words$word) + ((concat_vec + (vec_of_bits [B0] + : 1 words$word) + (vec_of_bits [B0] + : 1 words$word) + : 2 words$word)) + : 3 words$word)) + : 4 words$word)) + : 5 words$word)) + : 6 words$word)) + : 7 words$word)) + : 10 words$word)) + : 13 words$word)) + : 16 words$word)) + : 19 words$word)) + : 22 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) + ((concat_vec (vec_of_bits [B1] : 1 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + : 8 words$word)) + : 12 words$word)) + : 16 words$word)) + : 20 words$word)) + : 24 words$word)) + : 28 words$word)) + : 31 words$word)) + : 32 words$word)) + : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0LLAddr_ref : ( 64 words$word) M) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + sail2_state_monad$returnS ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)) + else if ((((((b__48 = (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS TLBXContext_ref) (\ (w__19 : XContextReg) . + sail2_state_monad$returnS ((get_XContextReg_bits w__19 : 64 words$word))) + else if ((((((b__48 = (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))) /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then + (sail2_state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) + else (SignalException ResI : ( 64 words$word) M) + )) (\ (result : 64 bits) . + wGPR rt + (if double then result + else + (mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)))))`; + + +(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MADDU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; + + +(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_MADD:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) + else + sail2_state_monad$returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))) (\ (mul_result : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS HI_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS LO_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . + let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec w__2 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)) + : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS + HI_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word))) + (sail2_state_monad$write_regS + LO_ref + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))))))`; + + +(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_Load:WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) width sign linked base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (vAddr : 64 bits) = + ((addrWrapper ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) + LoadData width + : 64 words$word)) in + if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (if linked then sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B1] : 1 words$word)) + (sail2_state_monad$write_regS CP0LLAddr_ref pAddr)) + (case width of + W0 => sail2_state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 words$word) . + sail2_state_monad$returnS ((extendLoad w__1 sign : 64 words$word))) + | D => sail2_state_monad$bindS + (MEMr_reserve_wrapper pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + sail2_state_monad$returnS ((extendLoad w__2 sign : 64 words$word))) + | _ => sail2_state_monad$throwS (Error_internal_error () ) + ) + else + (case width of + B => sail2_state_monad$bindS + (MEMr_wrapper (( 8 : int):ii) pAddr (( 1 : int):ii) : ( 8 words$word) M) (\ (w__5 : 8 words$word) . + sail2_state_monad$returnS ((extendLoad w__5 sign : 64 words$word))) + | H => sail2_state_monad$bindS + (MEMr_wrapper (( 16 : int):ii) pAddr (( 2 : int):ii) : ( 16 words$word) M) (\ (w__6 : 16 words$word) . + sail2_state_monad$returnS ((extendLoad w__6 sign : 64 words$word))) + | W0 => sail2_state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) pAddr (( 4 : int):ii) : ( 32 words$word) M) (\ (w__7 : 32 words$word) . + sail2_state_monad$returnS ((extendLoad w__7 sign : 64 words$word))) + | D => sail2_state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) pAddr (( 8 : int):ii) : ( 64 words$word) M) (\ (w__8 : 64 words$word) . + sail2_state_monad$returnS ((extendLoad w__8 sign : 64 words$word))) + )) (\ (memResult : 64 bits) . + wGPR rt memResult)))))`; + + +(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData WR + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):ii) + : ( 32 words$word) M) (\ mem_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__4 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + let (result : 32 bits) = + (if (((b__4 = (vec_of_bits [B0;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) + : 32 words$word) + else if (((b__4 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 : int):ii) (( 24 : int):ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 31 : int):ii) (( 8 : int):ii) : 24 words$word)) + : 32 words$word) + else mem_val) in + wGPR rt ((mips_sign_extend (( 64 : int):ii) result : 64 words$word))))))))`; + + +(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData WL + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (MEMr_wrapper (( 32 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)) + (vec_of_bits [B0;B0] : 2 words$word) + : 64 words$word)) (( 4 : int):ii) + : ( 32 words$word) M) (\ mem_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__0 = ((subrange_vec_dec vAddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + let (result : 32 bits) = + (if (((b__0 = (vec_of_bits [B0;B0] : 2 words$word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0;B1] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 32 words$word) + else if (((b__0 = (vec_of_bits [B1;B0] : 2 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 32 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 32 words$word)) in + wGPR rt ((mips_sign_extend (( 64 : int):ii) result : 64 words$word))))))))`; + + +(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LUI:(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt imm= + (wGPR rt + ((mips_sign_extend (( 64 : int):ii) + ((concat_vec imm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word) + : 32 words$word)) + : 64 words$word))))`; + + +(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData DR + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):ii) + : ( 64 words$word) M) (\ mem_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__24 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 32 : int):ii) : 32 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 40 : int):ii) : 24 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 24 : int):ii) : 40 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 48 : int):ii) : 16 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 16 : int):ii) : 48 words$word)) + : 64 words$word) + else if (((b__24 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)) + ((subrange_vec_dec mem_val (( 63 : int):ii) (( 8 : int):ii) : 56 words$word)) + : 64 words$word) + else mem_val)))))))`; + + +(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base rt offset= (sail2_state_monad$bindS + (rGPR base : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let vAddr = + ((addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 : int):ii) offset : 64 words$word)) w__0 : 64 words$word)) LoadData DL + : 64 words$word)) in sail2_state_monad$bindS + (TLBTranslate vAddr LoadData : ( 64 words$word) M) (\ pAddr . sail2_state_monad$bindS + (MEMr_wrapper (( 64 : int):ii) + ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):ii) (( 3 : int):ii) : 61 words$word)) + (vec_of_bits [B0;B0;B0] : 3 words$word) + : 64 words$word)) (( 8 : int):ii) + : ( 64 words$word) M) (\ mem_val . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ reg_val . + let b__16 = ((subrange_vec_dec vAddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + ((subrange_vec_dec reg_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + ((subrange_vec_dec reg_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + ((subrange_vec_dec reg_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec reg_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 : int):ii) (( 0 : int):ii) : 24 words$word)) + ((subrange_vec_dec reg_val (( 39 : int):ii) (( 0 : int):ii) : 40 words$word)) + : 64 words$word) + else if (((b__16 = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + ((subrange_vec_dec reg_val (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + : 64 words$word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + ((subrange_vec_dec reg_val (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + : 64 words$word))))))))`; + + +(*val execute_JR : mword ty5 -> M unit*) + +val _ = Define ` + ((execute_JR:(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs= (sail2_state_monad$bindS (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . execute_branch w__0)))`; + + +(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_JALR:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (execute_branch w__0) + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; + + +(*val execute_JAL : mword ty26 -> M unit*) + +val _ = Define ` + ((execute_JAL:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word))) + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . + wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) ((add_vec_int w__1 (( 8 : int):ii) : 64 words$word))))))`; + + +(*val execute_J : mword ty26 -> M unit*) + +val _ = Define ` + ((execute_J:(26)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) offset= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):ii) : 64 words$word)) (( 63 : int):ii) (( 28 : int):ii) : 36 words$word)) + ((concat_vec offset (vec_of_bits [B0;B0] : 2 words$word) : 28 words$word)) + : 64 words$word)))))`; + + +(*val execute_HCF : unit -> unit*) + +val _ = Define ` + ((execute_HCF:unit -> unit) g__18= () )`; + + +(*val execute_ERET : unit -> M unit*) + +val _ = Define ` + ((execute_ERET:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23= (sail2_state_monad$seqS + (checkCP0Access () ) + (let (_ : unit) = (ERETHook () ) in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref (vec_of_bits [B0] : 1 words$word)) + (sail2_state_monad$read_regS CP0Status_ref)) (\ (w__0 : StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 : 1 words$word)))) = ((bit_to_bool B1))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0ErrorEPC_ref : ( 64 words$word) M) (\ (w__1 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : 1 words$word))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS CP0EPC_ref : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : 1 words$word)))))))`; + + +(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((sub_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (temp65 : 65 bits) = + ((sub_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))))))`; + + +(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let sa = ((subrange_vec_dec w__0 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right_arith + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1)))))`; + + +(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . + let sa32 = ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) in sail2_state_monad$bindS + (shift_bits_right_arith + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ temp . sail2_state_monad$bindS + (shift_bits_right_arith + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0))))`; + + +(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) : ( 64 words$word) M) (\ (w__2 : + 64 words$word) . + wGPR rd w__2)))))`; + + +(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] : 1 words$word) sa : 6 words$word)) + : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd w__1))))`; + + +(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rt rd sa= (sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa : ( 64 words$word) M) (\ (w__1 : 64 words$word) . wGPR rd w__1))))`; + + +(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DMULTU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let result = ((mult_vec w__0 w__1 : 128 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + + +(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DMULT:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let result = ((mults_vec w__0 w__1 : 128 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((subrange_vec_dec result (( 127 : int):ii) (( 64 : int):ii) : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((subrange_vec_dec result (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))))`; + + +(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))))))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (w__0, w__1))) + else + let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (hardware_mod si ti) in + sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q : 64 words$word))))))))`; + + +(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ rsVal . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ rtVal . sail2_state_monad$bindS + (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))))))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__0 : 32 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M) (\ (w__1 : 32 bits) . + sail2_state_monad$returnS (w__0, w__1))) + else + let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):ii) (( 0 : int):ii) : 32 words$word))) in + let qi = (hardware_quot si ti) in + let ri = (si - ((ti * qi))) in + sail2_state_monad$returnS ((to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) qi : 32 words$word), + (to_bits ((make_the_value (( 32 : int):ii) : 32 itself)) ri : 32 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref ((mips_sign_extend (( 64 : int):ii) r : 64 words$word))) + (sail2_state_monad$write_regS LO_ref ((mips_sign_extend (( 64 : int):ii) q : 64 words$word))))))))`; + + +(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DDIVU:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rsVal = (lem$w2ui w__0) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rtVal = (lem$w2ui w__1) in sail2_state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (hardware_mod rsVal rtVal) in + sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`; + + +(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DDIV:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let rsVal = (integer_word$w2i w__0) in sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let rtVal = (integer_word$w2i w__1) in sail2_state_monad$bindS + (if (((rtVal = (( 0 : int):ii)))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__2 : 64 bits) . sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__3 : 64 bits) . + sail2_state_monad$returnS (w__2, w__3))) + else + let qi = (hardware_quot rsVal rtVal) in + let ri = (rsVal - ((qi * rtVal))) in + sail2_state_monad$returnS ((to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) qi : 64 words$word), + (to_bits ((make_the_value (( 64 : int):ii) : 64 itself)) ri : 64 words$word))) (\ varstup . let (q, r) = varstup in sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref q) (sail2_state_monad$write_regS HI_ref r))))))`; + + +(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((add_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (sum65 : 65 bits) = + ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) imm : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))))`; + + +(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (sum65 : 65 bits) = + ((add_vec ((mips_sign_extend (( 65 : int):ii) w__0 : 65 words$word)) + ((mips_sign_extend (( 65 : int):ii) w__1 : 65 words$word)) + : 65 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word))))))`; + + +(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) base op imm= (checkCP0Access () ))`; + + +(*val execute_BREAK : unit -> M unit*) + +val _ = Define ` + ((execute_BREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__15= (SignalException Bp))`; + + +(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) + +val _ = Define ` + ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rd imm ne likely= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rd : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) : 1 words$word)) + ((bool_to_bits ne : 1 words$word)) + : 1 words$word)))) then + let (offset : 64 bits) = + ((add_vec_int + ((mips_sign_extend (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + execute_branch ((add_vec w__2 offset : 64 words$word))) + else if likely then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . + sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ))))`; + + +(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) + +val _ = Define ` + ((execute_BCMPZ:(5)words$word ->(16)words$word -> Comparison -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs imm cmp link likely= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 bits) . + let linkVal = ((add_vec_int w__0 (( 8 : int):ii) : 64 words$word)) in sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ regVal . + let condition = + (compare cmp regVal ((mips_zero_extend (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) in sail2_state_monad$seqS + (if condition then + let (offset : 64 bits) = + ((add_vec_int + ((mips_sign_extend (( 64 : int):ii) + ((concat_vec imm (vec_of_bits [B0;B0] : 2 words$word) : 18 words$word)) + : 64 words$word)) (( 4 : int):ii) + : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + execute_branch ((add_vec w__1 offset : 64 words$word))) + else if likely then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):ii) : 64 words$word))) + else sail2_state_monad$returnS () ) + (if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) linkVal + else sail2_state_monad$returnS () )))))`; + + +(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)))))`; + + +(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + wGPR rd ((and_vec w__0 w__1 : 64 words$word))))))`; + + +(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ opB . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + wGPR rd + ((mips_sign_extend (( 64 : int):ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word)) + : 64 words$word))))))`; + + +(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . + if ((NotWordVal opA)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + wGPR rt + ((mips_sign_extend (( 64 : int):ii) + ((add_vec ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + ((mips_sign_extend (( 32 : int):ii) imm : 32 words$word)) + : 32 words$word)) + : 64 words$word)))))`; + + +(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +val _ = Define ` + ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt imm= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ opA . + if ((NotWordVal opA)) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rt w__0) + else + let (sum33 : 33 bits) = + ((add_vec + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) ((mips_sign_extend (( 33 : int):ii) imm : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rt + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word)))))`; + + +(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +val _ = Define ` + ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs rt rd= (sail2_state_monad$bindS + (rGPR rs : ( 64 words$word) M) (\ (opA : 64 bits) . sail2_state_monad$bindS + (rGPR rt : ( 64 words$word) M) (\ (opB : 64 bits) . + if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . wGPR rd w__0) + else + let (sum33 : 33 bits) = + ((add_vec + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opA (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + ((mips_sign_extend (( 33 : int):ii) ((subrange_vec_dec opB (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 33 words$word)) + : 33 words$word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):ii))))))) then + SignalException Ov + else + wGPR rd + ((mips_sign_extend (( 64 : int):ii) ((subrange_vec_dec sum33 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 64 words$word))))))`; + + +val _ = Define ` + ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var= + ((case merge_var of + DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm + | DADDU (rs,rt,rd) => execute_DADDU rs rt rd + | DADDI (rs,rt,imm) => execute_DADDI rs rt imm + | DADD (rs,rt,rd) => execute_DADD rs rt rd + | ADD (rs,rt,rd) => execute_ADD rs rt rd + | ADDI (rs,rt,imm) => execute_ADDI rs rt imm + | ADDU (rs,rt,rd) => execute_ADDU rs rt rd + | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm + | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd + | DSUB (rs,rt,rd) => execute_DSUB rs rt rd + | SUB0 (rs,rt,rd) => execute_SUB rs rt rd + | SUBU (rs,rt,rd) => execute_SUBU rs rt rd + | AND (rs,rt,rd) => execute_AND rs rt rd + | ANDI (rs,rt,imm) => execute_ANDI rs rt imm + | OR (rs,rt,rd) => execute_OR rs rt rd + | ORI (rs,rt,imm) => execute_ORI rs rt imm + | NOR (rs,rt,rd) => execute_NOR rs rt rd + | XOR (rs,rt,rd) => execute_XOR rs rt rd + | XORI (rs,rt,imm) => execute_XORI rs rt imm + | LUI (rt,imm) => execute_LUI rt imm + | DSLL (rt,rd,sa) => execute_DSLL rt rd sa + | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa + | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd + | DSRA (rt,rd,sa) => execute_DSRA rt rd sa + | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa + | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd + | DSRL (rt,rd,sa) => execute_DSRL rt rd sa + | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa + | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd + | SLL (rt,rd,sa) => execute_SLL rt rd sa + | SLLV (rs,rt,rd) => execute_SLLV rs rt rd + | SRA (rt,rd,sa) => execute_SRA rt rd sa + | SRAV (rs,rt,rd) => execute_SRAV rs rt rd + | SRL (rt,rd,sa) => execute_SRL rt rd sa + | SRLV (rs,rt,rd) => execute_SRLV rs rt rd + | SLT (rs,rt,rd) => execute_SLT rs rt rd + | SLTI (rs,rt,imm) => execute_SLTI rs rt imm + | SLTU (rs,rt,rd) => execute_SLTU rs rt rd + | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm + | MOVN (rs,rt,rd) => execute_MOVN rs rt rd + | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd + | MFHI (rd) => execute_MFHI rd + | MFLO (rd) => execute_MFLO rd + | MTHI (rs) => execute_MTHI rs + | MTLO (rs) => execute_MTLO rs + | MUL (rs,rt,rd) => execute_MUL rs rt rd + | MULT (rs,rt) => execute_MULT rs rt + | MULTU (rs,rt) => execute_MULTU rs rt + | DMULT (rs,rt) => execute_DMULT rs rt + | DMULTU (rs,rt) => execute_DMULTU rs rt + | MADD (rs,rt) => execute_MADD rs rt + | MADDU (rs,rt) => execute_MADDU rs rt + | MSUB (rs,rt) => execute_MSUB rs rt + | MSUBU (rs,rt) => execute_MSUBU rs rt + | DIV0 (rs,rt) => execute_DIV rs rt + | DIVU (rs,rt) => execute_DIVU rs rt + | DDIV (rs,rt) => execute_DDIV rs rt + | DDIVU (rs,rt) => execute_DDIVU rs rt + | J (offset) => execute_J offset + | JAL (offset) => execute_JAL offset + | JR (rs) => execute_JR rs + | JALR (rs,rd) => execute_JALR rs rd + | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely + | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely + | SYSCALL (g__14) => execute_SYSCALL g__14 + | BREAK (g__15) => execute_BREAK g__15 + | WAIT (g__16) => execute_WAIT g__16 + | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp + | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp + | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset + | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset + | LWL (base,rt,offset) => execute_LWL base rt offset + | LWR (base,rt,offset) => execute_LWR base rt offset + | SWL (base,rt,offset) => execute_SWL base rt offset + | SWR (base,rt,offset) => execute_SWR base rt offset + | LDL (base,rt,offset) => execute_LDL base rt offset + | LDR (base,rt,offset) => execute_LDR base rt offset + | SDL (base,rt,offset) => execute_SDL base rt offset + | SDR (base,rt,offset) => execute_SDR base rt offset + | CACHE (base,op,imm) => execute_CACHE base op imm + | SYNC (g__17) => execute_SYNC g__17 + | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double + | HCF (g__18) => sail2_state_monad$returnS ((execute_HCF g__18)) + | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double + | TLBWI (g__19) => execute_TLBWI g__19 + | TLBWR (g__20) => execute_TLBWR g__20 + | TLBR (g__21) => execute_TLBR g__21 + | TLBP (g__22) => execute_TLBP g__22 + | RDHWR (rt,rd) => execute_RDHWR rt rd + | ERET (g__23) => execute_ERET g__23 + | RI (g__24) => execute_RI g__24 + )))`; + + +(*val supported_instructions : ast -> maybe ast*) + +val _ = Define ` + ((supported_instructions:ast ->(ast)option) instr= (SOME instr))`; + + +(*val initialize_registers : unit -> M unit*) + +val _ = Define ` + ((initialize_registers:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M) (\ (w__0 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PC_ref w__0) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__1 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__1) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__2 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBProbe_ref w__2) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__3 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBIndex_ref w__3) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__4 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBRandom_ref w__4) + (undefined_TLBEntryLoReg () )) (\ (w__5 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryLo0_ref w__5) + (undefined_TLBEntryLoReg () )) (\ (w__6 : TLBEntryLoReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryLo1_ref w__6) + (undefined_ContextReg () )) (\ (w__7 : ContextReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBContext_ref w__7) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 : int):ii) : ( 16 words$word) M)) (\ (w__8 : 16 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBPageMask_ref w__8) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 : int):ii) : ( 6 words$word) M)) (\ (w__9 : TLBIndexT) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBWired_ref w__9) + (undefined_TLBEntryHiReg () )) (\ (w__10 : TLBEntryHiReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntryHi_ref w__10) + (undefined_XContextReg () )) (\ (w__11 : XContextReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBXContext_ref w__11) + (undefined_TLBEntry () )) (\ (w__12 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry00_ref w__12) + (undefined_TLBEntry () )) (\ (w__13 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry01_ref w__13) + (undefined_TLBEntry () )) (\ (w__14 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry02_ref w__14) + (undefined_TLBEntry () )) (\ (w__15 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry03_ref w__15) + (undefined_TLBEntry () )) (\ (w__16 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry04_ref w__16) + (undefined_TLBEntry () )) (\ (w__17 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry05_ref w__17) + (undefined_TLBEntry () )) (\ (w__18 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry06_ref w__18) + (undefined_TLBEntry () )) (\ (w__19 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry07_ref w__19) + (undefined_TLBEntry () )) (\ (w__20 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry08_ref w__20) + (undefined_TLBEntry () )) (\ (w__21 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry09_ref w__21) + (undefined_TLBEntry () )) (\ (w__22 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry10_ref w__22) + (undefined_TLBEntry () )) (\ (w__23 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry11_ref w__23) + (undefined_TLBEntry () )) (\ (w__24 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry12_ref w__24) + (undefined_TLBEntry () )) (\ (w__25 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry13_ref w__25) + (undefined_TLBEntry () )) (\ (w__26 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry14_ref w__26) + (undefined_TLBEntry () )) (\ (w__27 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry15_ref w__27) + (undefined_TLBEntry () )) (\ (w__28 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry16_ref w__28) + (undefined_TLBEntry () )) (\ (w__29 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry17_ref w__29) + (undefined_TLBEntry () )) (\ (w__30 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry18_ref w__30) + (undefined_TLBEntry () )) (\ (w__31 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry19_ref w__31) + (undefined_TLBEntry () )) (\ (w__32 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry20_ref w__32) + (undefined_TLBEntry () )) (\ (w__33 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry21_ref w__33) + (undefined_TLBEntry () )) (\ (w__34 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry22_ref w__34) + (undefined_TLBEntry () )) (\ (w__35 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry23_ref w__35) + (undefined_TLBEntry () )) (\ (w__36 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry24_ref w__36) + (undefined_TLBEntry () )) (\ (w__37 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry25_ref w__37) + (undefined_TLBEntry () )) (\ (w__38 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry26_ref w__38) + (undefined_TLBEntry () )) (\ (w__39 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry27_ref w__39) + (undefined_TLBEntry () )) (\ (w__40 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry28_ref w__40) + (undefined_TLBEntry () )) (\ (w__41 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry29_ref w__41) + (undefined_TLBEntry () )) (\ (w__42 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry30_ref w__42) + (undefined_TLBEntry () )) (\ (w__43 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry31_ref w__43) + (undefined_TLBEntry () )) (\ (w__44 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry32_ref w__44) + (undefined_TLBEntry () )) (\ (w__45 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry33_ref w__45) + (undefined_TLBEntry () )) (\ (w__46 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry34_ref w__46) + (undefined_TLBEntry () )) (\ (w__47 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry35_ref w__47) + (undefined_TLBEntry () )) (\ (w__48 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry36_ref w__48) + (undefined_TLBEntry () )) (\ (w__49 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry37_ref w__49) + (undefined_TLBEntry () )) (\ (w__50 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry38_ref w__50) + (undefined_TLBEntry () )) (\ (w__51 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry39_ref w__51) + (undefined_TLBEntry () )) (\ (w__52 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry40_ref w__52) + (undefined_TLBEntry () )) (\ (w__53 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry41_ref w__53) + (undefined_TLBEntry () )) (\ (w__54 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry42_ref w__54) + (undefined_TLBEntry () )) (\ (w__55 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry43_ref w__55) + (undefined_TLBEntry () )) (\ (w__56 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry44_ref w__56) + (undefined_TLBEntry () )) (\ (w__57 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry45_ref w__57) + (undefined_TLBEntry () )) (\ (w__58 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry46_ref w__58) + (undefined_TLBEntry () )) (\ (w__59 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry47_ref w__59) + (undefined_TLBEntry () )) (\ (w__60 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry48_ref w__60) + (undefined_TLBEntry () )) (\ (w__61 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry49_ref w__61) + (undefined_TLBEntry () )) (\ (w__62 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry50_ref w__62) + (undefined_TLBEntry () )) (\ (w__63 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry51_ref w__63) + (undefined_TLBEntry () )) (\ (w__64 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry52_ref w__64) + (undefined_TLBEntry () )) (\ (w__65 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry53_ref w__65) + (undefined_TLBEntry () )) (\ (w__66 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry54_ref w__66) + (undefined_TLBEntry () )) (\ (w__67 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry55_ref w__67) + (undefined_TLBEntry () )) (\ (w__68 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry56_ref w__68) + (undefined_TLBEntry () )) (\ (w__69 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry57_ref w__69) + (undefined_TLBEntry () )) (\ (w__70 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry58_ref w__70) + (undefined_TLBEntry () )) (\ (w__71 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry59_ref w__71) + (undefined_TLBEntry () )) (\ (w__72 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry60_ref w__72) + (undefined_TLBEntry () )) (\ (w__73 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry61_ref w__73) + (undefined_TLBEntry () )) (\ (w__74 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry62_ref w__74) + (undefined_TLBEntry () )) (\ (w__75 : TLBEntry) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS TLBEntry63_ref w__75) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__76 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Compare_ref w__76) + (undefined_CauseReg () )) (\ (w__77 : CauseReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Cause_ref w__77) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__78 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0EPC_ref w__78) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__79 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0ErrorEPC_ref w__79) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__80 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLBit_ref w__80) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__81 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0LLAddr_ref w__81) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__82 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0BadVAddr_ref w__82) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__83 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Count_ref w__83) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 : int):ii) : ( 32 words$word) M)) (\ (w__84 : 32 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0HWREna_ref w__84) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__85 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0UserLocal_ref w__85) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 : int):ii) : ( 3 words$word) M)) (\ (w__86 : 3 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0ConfigK0_ref w__86) + (undefined_StatusReg () )) (\ (w__87 : StatusReg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS CP0Status_ref w__87) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__88 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS branchPending_ref w__88) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__89 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS inBranchDelay_ref w__89) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__90 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS delayedPC_ref w__90) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__91 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS HI_ref w__91) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__92 : 64 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS LO_ref w__92) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 : int):ii) : ( 64 words$word) M)) (\ (w__93 : 64 words$word) . sail2_state_monad$bindS + (undefined_vector (( 32 : int):ii) w__93 : ( ( 64 words$word)list) M) (\ (w__94 : ( 64 bits) list) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS GPR_ref w__94) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__95 : 8 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WDATA_ref w__95) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__96 : 1 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_WRITTEN_ref w__96) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 : int):ii) : ( 8 words$word) M)) (\ (w__97 : 8 bits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS UART_RDATA_ref w__97) + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 : int):ii) : ( 1 words$word) M)) (\ (w__98 : 1 bits) . + sail2_state_monad$write_regS UART_RVALID_ref w__98)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`; + + +val _ = Define ` +((initial_regstate:regstate)= + (<| UART_RVALID := ((vec_of_bits [B0] : 1 words$word)); + UART_RDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)); + UART_WRITTEN := ((vec_of_bits [B0] : 1 words$word)); + UART_WDATA := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)); + GPR := + ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)]); + LO := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + HI := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + delayedPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + inBranchDelay := ((vec_of_bits [B0] : 1 words$word)); + branchPending := ((vec_of_bits [B0] : 1 words$word)); + CP0Status := + (<| StatusReg_StatusReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); + CP0ConfigK0 := ((vec_of_bits [B0;B0;B0] : 3 words$word)); + CP0UserLocal := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0HWREna := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0Count := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + CP0BadVAddr := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0LLAddr := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0LLBit := ((vec_of_bits [B0] : 1 words$word)); + CP0ErrorEPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0EPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + CP0Cause := + (<| CauseReg_CauseReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); + CP0Compare := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0] + : 32 words$word)); + TLBEntry63 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry62 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry61 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry60 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry59 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry58 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry57 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry56 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry55 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry54 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry53 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry52 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry51 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry50 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry49 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry48 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry47 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry46 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry45 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry44 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry43 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry42 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry41 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry40 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry39 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry38 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry37 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry36 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry35 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry34 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry33 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry32 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry31 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry30 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry29 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry28 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry27 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry26 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry25 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry24 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry23 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry22 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry21 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry20 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry19 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry18 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry17 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry16 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry15 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry14 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry13 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry12 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry11 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry10 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry09 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry08 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry07 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry06 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry05 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry04 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry03 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry02 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry01 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntry00 := + (<| TLBEntry_TLBEntry_chunk_1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0] + : 53 words$word)); + TLBEntry_TLBEntry_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBXContext := + (<| XContextReg_XContextReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntryHi := + (<| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBWired := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBPageMask := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)); + TLBContext := + (<| ContextReg_ContextReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntryLo1 := + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBEntryLo0 := + (<| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); + TLBRandom := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBIndex := ((vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)); + TLBProbe := ((vec_of_bits [B0] : 1 words$word)); + nextPC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + PC := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>))`; + + + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/mips/mips_extrasScript.sml b/snapshots/hol4/sail/mips/mips_extrasScript.sml new file mode 100644 index 00000000..f89e7b2f --- /dev/null +++ b/snapshots/hol4/sail/mips/mips_extrasScript.sml @@ -0,0 +1,242 @@ +(*Generated by Lem from mips_extras.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_promptTheory sail2_operatorsTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "mips_extras" + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) + +val _ = Define ` + ((MEMr:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1))`; + +val _ = Define ` + ((MEMr_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,'b,'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1))`; + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +val _ = Define ` + ((read_tag_bool:'a Bitvector_class -> 'a ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a addr= (sail2_state_monad$bindS + (sail2_state_monad$read_tagS + dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$maybe_failS "read_tag_bool" (bool_of_bitU t))))`; + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +val _ = Define ` + ((write_tag_bool:'a Bitvector_class -> 'a -> bool ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr t= (sail2_state_monad$bindS (sail2_state_monad$write_tagS + dict_Sail2_values_Bitvector_a addr (bitU_of_bool t)) + (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; + + +val _ = Define ` + ((MEMr_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$bindS + (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v . sail2_state_monad$bindS + (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$returnS (t, v)))))`; + + +val _ = Define ` + ((MEMr_tag_reserve:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1= (sail2_state_monad$bindS + (sail2_state_monad$read_memS + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1) (\ v . sail2_state_monad$bindS + (read_tag_bool dict_Sail2_values_Bitvector_a addr) (\ t . + sail2_state_monad$returnS (t, v)))))`; + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) + +val _ = Define ` + ((MEMea:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + +val _ = Define ` + ((MEMea_tag:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_tag_conditional:'a Bitvector_class -> 'a -> int ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a addr size1= (sail2_state_monad$write_mem_eaS + dict_Sail2_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`; + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) + +val _ = Define ` + ((MEMval:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; + +val _ = Define ` + ((MEMval_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\ b . sail2_state_monad$returnS (if b then T else F))))`; + +val _ = Define ` + ((MEMval_tag:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\b . (case (b ) of + ( _ ) => sail2_state_monad$bindS + (write_tag_bool dict_Sail2_values_Bitvector_a addr t) + (\u . (case (u ) of + ( _ ) => sail2_state_monad$returnS () + )) + ))))`; + +val _ = Define ` + ((MEMval_tag_conditional:'a Bitvector_class -> 'b Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)monad)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v= (sail2_state_monad$bindS (sail2_state_monad$write_mem_valS + dict_Sail2_values_Bitvector_b v) (\ b . sail2_state_monad$bindS (write_tag_bool + dict_Sail2_values_Bitvector_a addr t) (\u . (case (u ) of + ( _ ) => sail2_state_monad$returnS (if b then T else F) + )))))`; + + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +val _ = Define ` + ((MEM_sync:unit -> 'regval sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'regval sail2_state_monad$sequential_state)set) () = (barrier Barrier_MIPS_SYNC))`; + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +val _ = Define ` + ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo= + ( + (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in + let bs = (bools_of_int (hi +( 1 : int)) n) in + subrange_list F bs hi lo))`; + + +(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +val _ = Define ` + ((get_slice_int:'a Bitvector_class -> int -> int -> int -> 'a)dict_Sail2_values_Bitvector_a len n lo= ( + dict_Sail2_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`; + + +val _ = Define ` + ((write_ram:'a Bitvector_class -> 'b Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd sail2_state_monad$sequential_state ->(((unit),'c)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data= (sail2_state_monad$seqS + (MEMea dict_Sail2_values_Bitvector_b addr size1) + (MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data)))`; + + +val _ = Define ` + ((read_ram:'a Bitvector_class -> 'c Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd sail2_state_monad$sequential_state ->(('c,'b)sail2_state_monad$result#'d sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr= (MEMr + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1))`; + + +val _ = Define ` + ((string_of_int:'a Show_class -> 'a -> string)dict_Show_Show_a= + (dict_Show_Show_a.show_method))`; + + +val _ = Define ` + ((shift_bits_left:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_left" r))`; + +val _ = Define ` + ((shift_bits_right:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_right" r))`; + +val _ = Define ` + ((shift_bits_right_arith:'b Bitvector_class -> 'd Bitvector_class -> 'e Bitvector_class -> 'd -> 'e -> 'a sail2_state_monad$sequential_state ->(('b,'c)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set)dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n= + (let r = (OPTION_BIND ( + dict_Sail2_values_Bitvector_e.unsigned_method n) (\ n . dict_Sail2_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in + sail2_state_monad$maybe_failS "shift_bits_right_arith" r))`; + + +(* Use constants for undefined values for now *) +val _ = Define ` + ((undefined_string:unit -> 'a sail2_state_monad$sequential_state ->(((string),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS ""))`; + +val _ = Define ` + ((undefined_unit:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`; + +val _ = Define ` + ((undefined_int:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +val _ = Define ` + ((undefined_vector:int -> 'a -> 'rv sail2_state_monad$sequential_state ->((('a list),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) len u= (sail2_state_monad$returnS (repeat [u] len)))`; + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +val _ = Define ` + ((undefined_bitvector:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a len= (sail2_state_monad$returnS ( + dict_Sail2_values_Bitvector_a.of_bools_method (repeat [F] len))))`; + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +val _ = Define ` + ((undefined_bits:'a Bitvector_class -> int ->('rv,'a,'e)monad)dict_Sail2_values_Bitvector_a= + (undefined_bitvector dict_Sail2_values_Bitvector_a))`; + +val _ = Define ` + ((undefined_bit:unit -> 'a sail2_state_monad$sequential_state ->(((bitU),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS B0))`; + +val _ = Define ` + ((undefined_real:unit -> 'a sail2_state_monad$sequential_state ->(((real),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (realFromFrac(( 0 : int))(( 1 : int)))))`; + +val _ = Define ` + ((undefined_range:'a -> 'd -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i j= (sail2_state_monad$returnS i))`; + +val _ = Define ` + ((undefined_atom:'a -> 'b sail2_state_monad$sequential_state ->(('a,'c)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) i= (sail2_state_monad$returnS i))`; + +val _ = Define ` + ((undefined_nat:unit -> 'a sail2_state_monad$sequential_state ->(((int),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS (( 0 : int):ii)))`; + + +val _ = Define ` + ((skip:unit -> 'a sail2_state_monad$sequential_state ->(((unit),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) () = (sail2_state_monad$returnS () ))`; + + +(*val elf_entry : unit -> integer*) +val _ = Define ` + ((elf_entry:unit -> int) () = (( 0 : int)))`; + + +val _ = Define ` + ((print_bits:'a Bitvector_class -> string -> 'a -> unit)dict_Sail2_values_Bitvector_a msg bs= (prerr_endline ( STRCAT msg (string_of_bv + dict_Sail2_values_Bitvector_a bs))))`; + + +(*val get_time_ns : unit -> integer*) +val _ = Define ` + ((get_time_ns:unit -> int) () = (( 0 : int)))`; + + +(*val cycle_count : unit -> unit*) +val _ = Define ` + ((cycle_count:unit -> unit) _= () )`; + +val _ = export_theory() + diff --git a/snapshots/hol4/sail/mips/mips_typesScript.sml b/snapshots/hol4/sail/mips/mips_typesScript.sml new file mode 100644 index 00000000..fce6af4b --- /dev/null +++ b/snapshots/hol4/sail/mips/mips_typesScript.sml @@ -0,0 +1,1692 @@ +(*Generated by Lem from mips_types.lem.*) +open HolKernel Parse boolLib bossLib; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_stringTheory sail2_operators_mwordsTheory sail2_promptTheory; + +val _ = numLib.prefer_num(); + + + +val _ = new_theory "mips_types" + +(*Generated by Sail from mips.*) +(*open import Pervasives_extra*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) +val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); + + + +val _ = Hol_datatype ` + exception = + ISAException of (unit) + | Error_not_implemented of (string) + | Error_misaligned_access of (unit) + | Error_EBREAK of (unit) + | Error_internal_error of (unit)`; + + + + +val _ = Hol_datatype ` + CauseReg = <| CauseReg_CauseReg_chunk_0 : 32 words$word |>`; + + + +val _ = Hol_datatype ` + StatusReg = <| StatusReg_StatusReg_chunk_0 : 32 words$word |>`; + + + +val _ = Hol_datatype ` + TLBEntryLoReg = <| TLBEntryLoReg_TLBEntryLoReg_chunk_0 : 64 words$word |>`; + + + +val _ = Hol_datatype ` + TLBEntryHiReg = <| TLBEntryHiReg_TLBEntryHiReg_chunk_0 : 64 words$word |>`; + + + +val _ = Hol_datatype ` + ContextReg = <| ContextReg_ContextReg_chunk_0 : 64 words$word |>`; + + + +val _ = Hol_datatype ` + XContextReg = <| XContextReg_XContextReg_chunk_0 : 64 words$word |>`; + + + +val _ = type_abbrev( "TLBIndexT" , ``: 6 bits``); + +val _ = Hol_datatype ` + TLBEntry = + <| TLBEntry_TLBEntry_chunk_1 : 53 words$word; TLBEntry_TLBEntry_chunk_0 : 64 words$word |>`; + + + +val _ = Hol_datatype ` + Exception = + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck`; + + + + +val _ = Hol_datatype ` + MemAccessType = Instruction | LoadData | StoreData`; + + + + +val _ = Hol_datatype ` + AccessLevel = User | Supervisor | Kernel`; + + + + +val _ = type_abbrev( "regno" , ``: 5 bits``); + +val _ = type_abbrev( "imm16" , ``: 16 bits``); + +val _ = type_abbrev( "regregreg" , ``: (regno # regno # regno)``); + +val _ = type_abbrev( "regregimm16" , ``: (regno # regno # imm16)``); + +val _ = Hol_datatype ` + decode_failure = + No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error`; + + + + +val _ = Hol_datatype ` + Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU`; + + + + +val _ = Hol_datatype ` + WordType = B | H | W0 | D`; + + + + +val _ = Hol_datatype ` + WordTypeUnaligned = WL | WR | DL | DR`; + + + + +val _ = Hol_datatype ` + ast = + DADDIU of ((regno # regno # imm16)) + | DADDU of ((regno # regno # regno)) + | DADDI of ((regno # regno # 16 bits)) + | DADD of ((regno # regno # regno)) + | ADD of ((regno # regno # regno)) + | ADDI of ((regno # regno # 16 bits)) + | ADDU of ((regno # regno # regno)) + | ADDIU of ((regno # regno # 16 bits)) + | DSUBU of ((regno # regno # regno)) + | DSUB of ((regno # regno # regno)) + | SUB0 of ((regno # regno # regno)) + | SUBU of ((regno # regno # regno)) + | AND of ((regno # regno # regno)) + | ANDI of ((regno # regno # 16 bits)) + | OR of ((regno # regno # regno)) + | ORI of ((regno # regno # 16 bits)) + | NOR of ((regno # regno # regno)) + | XOR of ((regno # regno # regno)) + | XORI of ((regno # regno # 16 bits)) + | LUI of ((regno # imm16)) + | DSLL of ((regno # regno # regno)) + | DSLL32 of ((regno # regno # regno)) + | DSLLV of ((regno # regno # regno)) + | DSRA of ((regno # regno # regno)) + | DSRA32 of ((regno # regno # regno)) + | DSRAV of ((regno # regno # regno)) + | DSRL of ((regno # regno # regno)) + | DSRL32 of ((regno # regno # regno)) + | DSRLV of ((regno # regno # regno)) + | SLL of ((regno # regno # regno)) + | SLLV of ((regno # regno # regno)) + | SRA of ((regno # regno # regno)) + | SRAV of ((regno # regno # regno)) + | SRL of ((regno # regno # regno)) + | SRLV of ((regno # regno # regno)) + | SLT of ((regno # regno # regno)) + | SLTI of ((regno # regno # 16 bits)) + | SLTU of ((regno # regno # regno)) + | SLTIU of ((regno # regno # 16 bits)) + | MOVN of ((regno # regno # regno)) + | MOVZ of ((regno # regno # regno)) + | MFHI of (regno) + | MFLO of (regno) + | MTHI of (regno) + | MTLO of (regno) + | MUL of ((regno # regno # regno)) + | MULT of ((regno # regno)) + | MULTU of ((regno # regno)) + | DMULT of ((regno # regno)) + | DMULTU of ((regno # regno)) + | MADD of ((regno # regno)) + | MADDU of ((regno # regno)) + | MSUB of ((regno # regno)) + | MSUBU of ((regno # regno)) + | DIV0 of ((regno # regno)) + | DIVU of ((regno # regno)) + | DDIV of ((regno # regno)) + | DDIVU of ((regno # regno)) + | J of ( 26 bits) + | JAL of ( 26 bits) + | JR of (regno) + | JALR of ((regno # regno)) + | BEQ of ((regno # regno # imm16 # bool # bool)) + | BCMPZ of ((regno # imm16 # Comparison # bool # bool)) + | SYSCALL of (unit) + | BREAK of (unit) + | WAIT of (unit) + | TRAPREG of ((regno # regno # Comparison)) + | TRAPIMM of ((regno # imm16 # Comparison)) + | Load of ((WordType # bool # bool # regno # regno # imm16)) + | Store of ((WordType # bool # regno # regno # imm16)) + | LWL of ((regno # regno # 16 bits)) + | LWR of ((regno # regno # 16 bits)) + | SWL of ((regno # regno # 16 bits)) + | SWR of ((regno # regno # 16 bits)) + | LDL of ((regno # regno # 16 bits)) + | LDR of ((regno # regno # 16 bits)) + | SDL of ((regno # regno # 16 bits)) + | SDR of ((regno # regno # 16 bits)) + | CACHE of ((regno # regno # 16 bits)) + | SYNC of (unit) + | MFC0 of ((regno # regno # 3 bits # bool)) + | HCF of (unit) + | MTC0 of ((regno # regno # 3 bits # bool)) + | TLBWI of (unit) + | TLBWR of (unit) + | TLBR of (unit) + | TLBP of (unit) + | RDHWR of ((regno # regno)) + | ERET of (unit) + | RI of (unit)`; + + + + +val _ = Hol_datatype ` + register_value = + Regval_vector of ((ii # bool # register_value list)) + | Regval_list of ( register_value list) + | Regval_option of ( register_value option) + | Regval_CauseReg of (CauseReg) + | Regval_ContextReg of (ContextReg) + | Regval_StatusReg of (StatusReg) + | Regval_TLBEntry of (TLBEntry) + | Regval_TLBEntryHiReg of (TLBEntryHiReg) + | Regval_TLBEntryLoReg of (TLBEntryLoReg) + | Regval_XContextReg of (XContextReg) + | Regval_vector_16_dec_bit of ( 16 words$word) + | Regval_vector_1_dec_bit of ( 1 words$word) + | Regval_vector_32_dec_bit of ( 32 words$word) + | Regval_vector_3_dec_bit of ( 3 words$word) + | Regval_vector_64_dec_bit of ( 64 words$word) + | Regval_vector_6_dec_bit of ( 6 words$word) + | Regval_vector_8_dec_bit of ( 8 words$word)`; + + + + +val _ = Hol_datatype ` + regstate = + <| UART_RVALID : 1 words$word; + UART_RDATA : 8 words$word; + UART_WRITTEN : 1 words$word; + UART_WDATA : 8 words$word; + GPR : ( 64 words$word) list; + LO : 64 words$word; + HI : 64 words$word; + delayedPC : 64 words$word; + inBranchDelay : 1 words$word; + branchPending : 1 words$word; + CP0Status : StatusReg; + CP0ConfigK0 : 3 words$word; + CP0UserLocal : 64 words$word; + CP0HWREna : 32 words$word; + CP0Count : 32 words$word; + CP0BadVAddr : 64 words$word; + CP0LLAddr : 64 words$word; + CP0LLBit : 1 words$word; + CP0ErrorEPC : 64 words$word; + CP0EPC : 64 words$word; + CP0Cause : CauseReg; + CP0Compare : 32 words$word; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : 6 words$word; + TLBPageMask : 16 words$word; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : 6 words$word; + TLBIndex : 6 words$word; + TLBProbe : 1 words$word; + nextPC : 64 words$word; + PC : 64 words$word |>`; + + + + + +(*val CauseReg_of_regval : register_value -> maybe CauseReg*) + +val _ = Define ` + ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var= + ((case merge_var of Regval_CauseReg (v) => SOME v | g__13 => NONE )))`; + + +(*val regval_of_CauseReg : CauseReg -> register_value*) + +val _ = Define ` + ((regval_of_CauseReg:CauseReg -> register_value) v= (Regval_CauseReg v))`; + + +(*val ContextReg_of_regval : register_value -> maybe ContextReg*) + +val _ = Define ` + ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var= + ((case merge_var of Regval_ContextReg (v) => SOME v | g__12 => NONE )))`; + + +(*val regval_of_ContextReg : ContextReg -> register_value*) + +val _ = Define ` + ((regval_of_ContextReg:ContextReg -> register_value) v= (Regval_ContextReg v))`; + + +(*val StatusReg_of_regval : register_value -> maybe StatusReg*) + +val _ = Define ` + ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var= + ((case merge_var of Regval_StatusReg (v) => SOME v | g__11 => NONE )))`; + + +(*val regval_of_StatusReg : StatusReg -> register_value*) + +val _ = Define ` + ((regval_of_StatusReg:StatusReg -> register_value) v= (Regval_StatusReg v))`; + + +(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*) + +val _ = Define ` + ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var= + ((case merge_var of Regval_TLBEntry (v) => SOME v | g__10 => NONE )))`; + + +(*val regval_of_TLBEntry : TLBEntry -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntry:TLBEntry -> register_value) v= (Regval_TLBEntry v))`; + + +(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*) + +val _ = Define ` + ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var= + ((case merge_var of Regval_TLBEntryHiReg (v) => SOME v | g__9 => NONE )))`; + + +(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntryHiReg:TLBEntryHiReg -> register_value) v= (Regval_TLBEntryHiReg v))`; + + +(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*) + +val _ = Define ` + ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var= + ((case merge_var of Regval_TLBEntryLoReg (v) => SOME v | g__8 => NONE )))`; + + +(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) + +val _ = Define ` + ((regval_of_TLBEntryLoReg:TLBEntryLoReg -> register_value) v= (Regval_TLBEntryLoReg v))`; + + +(*val XContextReg_of_regval : register_value -> maybe XContextReg*) + +val _ = Define ` + ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var= + ((case merge_var of Regval_XContextReg (v) => SOME v | g__7 => NONE )))`; + + +(*val regval_of_XContextReg : XContextReg -> register_value*) + +val _ = Define ` + ((regval_of_XContextReg:XContextReg -> register_value) v= (Regval_XContextReg v))`; + + +(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*) + +val _ = Define ` + ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var= + ((case merge_var of Regval_vector_16_dec_bit (v) => SOME v | g__6 => NONE )))`; + + +(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) + +val _ = Define ` + ((regval_of_vector_16_dec_bit:(16)words$word -> register_value) v= (Regval_vector_16_dec_bit v))`; + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +val _ = Define ` + ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var= + ((case merge_var of Regval_vector_1_dec_bit (v) => SOME v | g__5 => NONE )))`; + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +val _ = Define ` + ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v= (Regval_vector_1_dec_bit v))`; + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +val _ = Define ` + ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var= + ((case merge_var of Regval_vector_32_dec_bit (v) => SOME v | g__4 => NONE )))`; + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +val _ = Define ` + ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v= (Regval_vector_32_dec_bit v))`; + + +(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*) + +val _ = Define ` + ((vector_3_dec_bit_of_regval:register_value ->((3)words$word)option) merge_var= + ((case merge_var of Regval_vector_3_dec_bit (v) => SOME v | g__3 => NONE )))`; + + +(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*) + +val _ = Define ` + ((regval_of_vector_3_dec_bit:(3)words$word -> register_value) v= (Regval_vector_3_dec_bit v))`; + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +val _ = Define ` + ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__2 => NONE )))`; + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +val _ = Define ` + ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v= (Regval_vector_64_dec_bit v))`; + + +(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*) + +val _ = Define ` + ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var= + ((case merge_var of Regval_vector_6_dec_bit (v) => SOME v | g__1 => NONE )))`; + + +(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) + +val _ = Define ` + ((regval_of_vector_6_dec_bit:(6)words$word -> register_value) v= (Regval_vector_6_dec_bit v))`; + + +(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*) + +val _ = Define ` + ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var= + ((case merge_var of Regval_vector_8_dec_bit (v) => SOME v | g__0 => NONE )))`; + + +(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) + +val _ = Define ` + ((regval_of_vector_8_dec_bit:(8)words$word -> register_value) v= (Regval_vector_8_dec_bit v))`; + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +val _ = Define ` + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= + (\x . (case x of + Regval_vector (_, _, v) => just_list (MAP of_regval1 v) + | _ => NONE + )))`; + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`; + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +val _ = Define ` + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= + (\x . (case x of + Regval_list v => just_list (MAP of_regval1 v) + | _ => NONE + )))`; + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +val _ = Define ` + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`; + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +val _ = Define ` + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= + (\x . (case x of + Regval_option v => SOME (OPTION_BIND v of_regval1) + | _ => NONE + )))`; + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +val _ = Define ` + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`; + + + +val _ = Define ` + ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "UART_RVALID"; + read_from := (\ s . s.UART_RVALID); + write_to := (\ v s . (( s with<| UART_RVALID := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))register_ref)= (<| + name := "UART_RDATA"; + read_from := (\ s . s.UART_RDATA); + write_to := (\ v s . (( s with<| UART_RDATA := v |>))); + of_regval := (\ v . vector_8_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_8_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "UART_WRITTEN"; + read_from := (\ s . s.UART_WRITTEN); + write_to := (\ v s . (( s with<| UART_WRITTEN := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))register_ref)= (<| + name := "UART_WDATA"; + read_from := (\ s . s.UART_WDATA); + write_to := (\ v s . (( s with<| UART_WDATA := v |>))); + of_regval := (\ v . vector_8_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_8_dec_bit v) |>))`; + + +val _ = Define ` + ((GPR_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| + name := "GPR"; + read_from := (\ s . s.GPR); + write_to := (\ v s . (( s with<| GPR := v |>))); + of_regval := (\ v . vector_of_regval (\ v . vector_64_dec_bit_of_regval v) v); + regval_of := (\ v . regval_of_vector (\ v . regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`; + + +val _ = Define ` + ((LO_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "LO"; + read_from := (\ s . s.LO); + write_to := (\ v s . (( s with<| LO := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((HI_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "HI"; + read_from := (\ s . s.HI); + write_to := (\ v s . (( s with<| HI := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((delayedPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "delayedPC"; + read_from := (\ s . s.delayedPC); + write_to := (\ v s . (( s with<| delayedPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "inBranchDelay"; + read_from := (\ s . s.inBranchDelay); + write_to := (\ v s . (( s with<| inBranchDelay := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((branchPending_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "branchPending"; + read_from := (\ s . s.branchPending); + write_to := (\ v s . (( s with<| branchPending := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Status_ref:((regstate),(register_value),(StatusReg))register_ref)= (<| + name := "CP0Status"; + read_from := (\ s . s.CP0Status); + write_to := (\ v s . (( s with<| CP0Status := v |>))); + of_regval := (\ v . StatusReg_of_regval v); + regval_of := (\ v . regval_of_StatusReg v) |>))`; + + +val _ = Define ` + ((CP0ConfigK0_ref:((regstate),(register_value),((3)words$word))register_ref)= (<| + name := "CP0ConfigK0"; + read_from := (\ s . s.CP0ConfigK0); + write_to := (\ v s . (( s with<| CP0ConfigK0 := v |>))); + of_regval := (\ v . vector_3_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_3_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "CP0UserLocal"; + read_from := (\ s . s.CP0UserLocal); + write_to := (\ v s . (( s with<| CP0UserLocal := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CP0HWREna"; + read_from := (\ s . s.CP0HWREna); + write_to := (\ v s . (( s with<| CP0HWREna := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Count_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CP0Count"; + read_from := (\ s . s.CP0Count); + write_to := (\ v s . (( s with<| CP0Count := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "CP0BadVAddr"; + read_from := (\ s . s.CP0BadVAddr); + write_to := (\ v s . (( s with<| CP0BadVAddr := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "CP0LLAddr"; + read_from := (\ s . s.CP0LLAddr); + write_to := (\ v s . (( s with<| CP0LLAddr := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "CP0LLBit"; + read_from := (\ s . s.CP0LLBit); + write_to := (\ v s . (( s with<| CP0LLBit := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "CP0ErrorEPC"; + read_from := (\ s . s.CP0ErrorEPC); + write_to := (\ v s . (( s with<| CP0ErrorEPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0EPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "CP0EPC"; + read_from := (\ s . s.CP0EPC); + write_to := (\ v s . (( s with<| CP0EPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((CP0Cause_ref:((regstate),(register_value),(CauseReg))register_ref)= (<| + name := "CP0Cause"; + read_from := (\ s . s.CP0Cause); + write_to := (\ v s . (( s with<| CP0Cause := v |>))); + of_regval := (\ v . CauseReg_of_regval v); + regval_of := (\ v . regval_of_CauseReg v) |>))`; + + +val _ = Define ` + ((CP0Compare_ref:((regstate),(register_value),((32)words$word))register_ref)= (<| + name := "CP0Compare"; + read_from := (\ s . s.CP0Compare); + write_to := (\ v s . (( s with<| CP0Compare := v |>))); + of_regval := (\ v . vector_32_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_32_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry63"; + read_from := (\ s . s.TLBEntry63); + write_to := (\ v s . (( s with<| TLBEntry63 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry62"; + read_from := (\ s . s.TLBEntry62); + write_to := (\ v s . (( s with<| TLBEntry62 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry61"; + read_from := (\ s . s.TLBEntry61); + write_to := (\ v s . (( s with<| TLBEntry61 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry60"; + read_from := (\ s . s.TLBEntry60); + write_to := (\ v s . (( s with<| TLBEntry60 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry59"; + read_from := (\ s . s.TLBEntry59); + write_to := (\ v s . (( s with<| TLBEntry59 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry58"; + read_from := (\ s . s.TLBEntry58); + write_to := (\ v s . (( s with<| TLBEntry58 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry57"; + read_from := (\ s . s.TLBEntry57); + write_to := (\ v s . (( s with<| TLBEntry57 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry56"; + read_from := (\ s . s.TLBEntry56); + write_to := (\ v s . (( s with<| TLBEntry56 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry55"; + read_from := (\ s . s.TLBEntry55); + write_to := (\ v s . (( s with<| TLBEntry55 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry54"; + read_from := (\ s . s.TLBEntry54); + write_to := (\ v s . (( s with<| TLBEntry54 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry53"; + read_from := (\ s . s.TLBEntry53); + write_to := (\ v s . (( s with<| TLBEntry53 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry52"; + read_from := (\ s . s.TLBEntry52); + write_to := (\ v s . (( s with<| TLBEntry52 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry51"; + read_from := (\ s . s.TLBEntry51); + write_to := (\ v s . (( s with<| TLBEntry51 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry50"; + read_from := (\ s . s.TLBEntry50); + write_to := (\ v s . (( s with<| TLBEntry50 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry49"; + read_from := (\ s . s.TLBEntry49); + write_to := (\ v s . (( s with<| TLBEntry49 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry48"; + read_from := (\ s . s.TLBEntry48); + write_to := (\ v s . (( s with<| TLBEntry48 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry47"; + read_from := (\ s . s.TLBEntry47); + write_to := (\ v s . (( s with<| TLBEntry47 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry46"; + read_from := (\ s . s.TLBEntry46); + write_to := (\ v s . (( s with<| TLBEntry46 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry45"; + read_from := (\ s . s.TLBEntry45); + write_to := (\ v s . (( s with<| TLBEntry45 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry44"; + read_from := (\ s . s.TLBEntry44); + write_to := (\ v s . (( s with<| TLBEntry44 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry43"; + read_from := (\ s . s.TLBEntry43); + write_to := (\ v s . (( s with<| TLBEntry43 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry42"; + read_from := (\ s . s.TLBEntry42); + write_to := (\ v s . (( s with<| TLBEntry42 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry41"; + read_from := (\ s . s.TLBEntry41); + write_to := (\ v s . (( s with<| TLBEntry41 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry40"; + read_from := (\ s . s.TLBEntry40); + write_to := (\ v s . (( s with<| TLBEntry40 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry39"; + read_from := (\ s . s.TLBEntry39); + write_to := (\ v s . (( s with<| TLBEntry39 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry38"; + read_from := (\ s . s.TLBEntry38); + write_to := (\ v s . (( s with<| TLBEntry38 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry37"; + read_from := (\ s . s.TLBEntry37); + write_to := (\ v s . (( s with<| TLBEntry37 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry36"; + read_from := (\ s . s.TLBEntry36); + write_to := (\ v s . (( s with<| TLBEntry36 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry35"; + read_from := (\ s . s.TLBEntry35); + write_to := (\ v s . (( s with<| TLBEntry35 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry34"; + read_from := (\ s . s.TLBEntry34); + write_to := (\ v s . (( s with<| TLBEntry34 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry33"; + read_from := (\ s . s.TLBEntry33); + write_to := (\ v s . (( s with<| TLBEntry33 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry32"; + read_from := (\ s . s.TLBEntry32); + write_to := (\ v s . (( s with<| TLBEntry32 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry31"; + read_from := (\ s . s.TLBEntry31); + write_to := (\ v s . (( s with<| TLBEntry31 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry30"; + read_from := (\ s . s.TLBEntry30); + write_to := (\ v s . (( s with<| TLBEntry30 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry29"; + read_from := (\ s . s.TLBEntry29); + write_to := (\ v s . (( s with<| TLBEntry29 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry28"; + read_from := (\ s . s.TLBEntry28); + write_to := (\ v s . (( s with<| TLBEntry28 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry27"; + read_from := (\ s . s.TLBEntry27); + write_to := (\ v s . (( s with<| TLBEntry27 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry26"; + read_from := (\ s . s.TLBEntry26); + write_to := (\ v s . (( s with<| TLBEntry26 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry25"; + read_from := (\ s . s.TLBEntry25); + write_to := (\ v s . (( s with<| TLBEntry25 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry24"; + read_from := (\ s . s.TLBEntry24); + write_to := (\ v s . (( s with<| TLBEntry24 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry23"; + read_from := (\ s . s.TLBEntry23); + write_to := (\ v s . (( s with<| TLBEntry23 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry22"; + read_from := (\ s . s.TLBEntry22); + write_to := (\ v s . (( s with<| TLBEntry22 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry21"; + read_from := (\ s . s.TLBEntry21); + write_to := (\ v s . (( s with<| TLBEntry21 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry20"; + read_from := (\ s . s.TLBEntry20); + write_to := (\ v s . (( s with<| TLBEntry20 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry19"; + read_from := (\ s . s.TLBEntry19); + write_to := (\ v s . (( s with<| TLBEntry19 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry18"; + read_from := (\ s . s.TLBEntry18); + write_to := (\ v s . (( s with<| TLBEntry18 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry17"; + read_from := (\ s . s.TLBEntry17); + write_to := (\ v s . (( s with<| TLBEntry17 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry16"; + read_from := (\ s . s.TLBEntry16); + write_to := (\ v s . (( s with<| TLBEntry16 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry15"; + read_from := (\ s . s.TLBEntry15); + write_to := (\ v s . (( s with<| TLBEntry15 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry14"; + read_from := (\ s . s.TLBEntry14); + write_to := (\ v s . (( s with<| TLBEntry14 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry13"; + read_from := (\ s . s.TLBEntry13); + write_to := (\ v s . (( s with<| TLBEntry13 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry12"; + read_from := (\ s . s.TLBEntry12); + write_to := (\ v s . (( s with<| TLBEntry12 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry11"; + read_from := (\ s . s.TLBEntry11); + write_to := (\ v s . (( s with<| TLBEntry11 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry10"; + read_from := (\ s . s.TLBEntry10); + write_to := (\ v s . (( s with<| TLBEntry10 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry09"; + read_from := (\ s . s.TLBEntry09); + write_to := (\ v s . (( s with<| TLBEntry09 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry08"; + read_from := (\ s . s.TLBEntry08); + write_to := (\ v s . (( s with<| TLBEntry08 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry07"; + read_from := (\ s . s.TLBEntry07); + write_to := (\ v s . (( s with<| TLBEntry07 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry06"; + read_from := (\ s . s.TLBEntry06); + write_to := (\ v s . (( s with<| TLBEntry06 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry05"; + read_from := (\ s . s.TLBEntry05); + write_to := (\ v s . (( s with<| TLBEntry05 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry04"; + read_from := (\ s . s.TLBEntry04); + write_to := (\ v s . (( s with<| TLBEntry04 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry03"; + read_from := (\ s . s.TLBEntry03); + write_to := (\ v s . (( s with<| TLBEntry03 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry02"; + read_from := (\ s . s.TLBEntry02); + write_to := (\ v s . (( s with<| TLBEntry02 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry01"; + read_from := (\ s . s.TLBEntry01); + write_to := (\ v s . (( s with<| TLBEntry01 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))register_ref)= (<| + name := "TLBEntry00"; + read_from := (\ s . s.TLBEntry00); + write_to := (\ v s . (( s with<| TLBEntry00 := v |>))); + of_regval := (\ v . TLBEntry_of_regval v); + regval_of := (\ v . regval_of_TLBEntry v) |>))`; + + +val _ = Define ` + ((TLBXContext_ref:((regstate),(register_value),(XContextReg))register_ref)= (<| + name := "TLBXContext"; + read_from := (\ s . s.TLBXContext); + write_to := (\ v s . (( s with<| TLBXContext := v |>))); + of_regval := (\ v . XContextReg_of_regval v); + regval_of := (\ v . regval_of_XContextReg v) |>))`; + + +val _ = Define ` + ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))register_ref)= (<| + name := "TLBEntryHi"; + read_from := (\ s . s.TLBEntryHi); + write_to := (\ v s . (( s with<| TLBEntryHi := v |>))); + of_regval := (\ v . TLBEntryHiReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryHiReg v) |>))`; + + +val _ = Define ` + ((TLBWired_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| + name := "TLBWired"; + read_from := (\ s . s.TLBWired); + write_to := (\ v s . (( s with<| TLBWired := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))register_ref)= (<| + name := "TLBPageMask"; + read_from := (\ s . s.TLBPageMask); + write_to := (\ v s . (( s with<| TLBPageMask := v |>))); + of_regval := (\ v . vector_16_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_16_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBContext_ref:((regstate),(register_value),(ContextReg))register_ref)= (<| + name := "TLBContext"; + read_from := (\ s . s.TLBContext); + write_to := (\ v s . (( s with<| TLBContext := v |>))); + of_regval := (\ v . ContextReg_of_regval v); + regval_of := (\ v . regval_of_ContextReg v) |>))`; + + +val _ = Define ` + ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)= (<| + name := "TLBEntryLo1"; + read_from := (\ s . s.TLBEntryLo1); + write_to := (\ v s . (( s with<| TLBEntryLo1 := v |>))); + of_regval := (\ v . TLBEntryLoReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryLoReg v) |>))`; + + +val _ = Define ` + ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))register_ref)= (<| + name := "TLBEntryLo0"; + read_from := (\ s . s.TLBEntryLo0); + write_to := (\ v s . (( s with<| TLBEntryLo0 := v |>))); + of_regval := (\ v . TLBEntryLoReg_of_regval v); + regval_of := (\ v . regval_of_TLBEntryLoReg v) |>))`; + + +val _ = Define ` + ((TLBRandom_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| + name := "TLBRandom"; + read_from := (\ s . s.TLBRandom); + write_to := (\ v s . (( s with<| TLBRandom := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBIndex_ref:((regstate),(register_value),((6)words$word))register_ref)= (<| + name := "TLBIndex"; + read_from := (\ s . s.TLBIndex); + write_to := (\ v s . (( s with<| TLBIndex := v |>))); + of_regval := (\ v . vector_6_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_6_dec_bit v) |>))`; + + +val _ = Define ` + ((TLBProbe_ref:((regstate),(register_value),((1)words$word))register_ref)= (<| + name := "TLBProbe"; + read_from := (\ s . s.TLBProbe); + write_to := (\ v s . (( s with<| TLBProbe := v |>))); + of_regval := (\ v . vector_1_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_1_dec_bit v) |>))`; + + +val _ = Define ` + ((nextPC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "nextPC"; + read_from := (\ s . s.nextPC); + write_to := (\ v s . (( s with<| nextPC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((PC_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "PC"; + read_from := (\ s . s.PC); + write_to := (\ v s . (( s with<| PC := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +(*val get_regval : string -> regstate -> maybe register_value*) +val _ = Define ` + ((get_regval:string -> regstate ->(register_value)option) reg_name s= + (if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else + if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else + if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else + if reg_name = "UART_WDATA" then SOME (UART_WDATA_ref.regval_of (UART_WDATA_ref.read_from s)) else + if reg_name = "GPR" then SOME (GPR_ref.regval_of (GPR_ref.read_from s)) else + if reg_name = "LO" then SOME (LO_ref.regval_of (LO_ref.read_from s)) else + if reg_name = "HI" then SOME (HI_ref.regval_of (HI_ref.read_from s)) else + if reg_name = "delayedPC" then SOME (delayedPC_ref.regval_of (delayedPC_ref.read_from s)) else + if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else + if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else + if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else + if reg_name = "CP0ConfigK0" then SOME (CP0ConfigK0_ref.regval_of (CP0ConfigK0_ref.read_from s)) else + if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else + if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else + if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else + if reg_name = "CP0BadVAddr" then SOME (CP0BadVAddr_ref.regval_of (CP0BadVAddr_ref.read_from s)) else + if reg_name = "CP0LLAddr" then SOME (CP0LLAddr_ref.regval_of (CP0LLAddr_ref.read_from s)) else + if reg_name = "CP0LLBit" then SOME (CP0LLBit_ref.regval_of (CP0LLBit_ref.read_from s)) else + if reg_name = "CP0ErrorEPC" then SOME (CP0ErrorEPC_ref.regval_of (CP0ErrorEPC_ref.read_from s)) else + if reg_name = "CP0EPC" then SOME (CP0EPC_ref.regval_of (CP0EPC_ref.read_from s)) else + if reg_name = "CP0Cause" then SOME (CP0Cause_ref.regval_of (CP0Cause_ref.read_from s)) else + if reg_name = "CP0Compare" then SOME (CP0Compare_ref.regval_of (CP0Compare_ref.read_from s)) else + if reg_name = "TLBEntry63" then SOME (TLBEntry63_ref.regval_of (TLBEntry63_ref.read_from s)) else + if reg_name = "TLBEntry62" then SOME (TLBEntry62_ref.regval_of (TLBEntry62_ref.read_from s)) else + if reg_name = "TLBEntry61" then SOME (TLBEntry61_ref.regval_of (TLBEntry61_ref.read_from s)) else + if reg_name = "TLBEntry60" then SOME (TLBEntry60_ref.regval_of (TLBEntry60_ref.read_from s)) else + if reg_name = "TLBEntry59" then SOME (TLBEntry59_ref.regval_of (TLBEntry59_ref.read_from s)) else + if reg_name = "TLBEntry58" then SOME (TLBEntry58_ref.regval_of (TLBEntry58_ref.read_from s)) else + if reg_name = "TLBEntry57" then SOME (TLBEntry57_ref.regval_of (TLBEntry57_ref.read_from s)) else + if reg_name = "TLBEntry56" then SOME (TLBEntry56_ref.regval_of (TLBEntry56_ref.read_from s)) else + if reg_name = "TLBEntry55" then SOME (TLBEntry55_ref.regval_of (TLBEntry55_ref.read_from s)) else + if reg_name = "TLBEntry54" then SOME (TLBEntry54_ref.regval_of (TLBEntry54_ref.read_from s)) else + if reg_name = "TLBEntry53" then SOME (TLBEntry53_ref.regval_of (TLBEntry53_ref.read_from s)) else + if reg_name = "TLBEntry52" then SOME (TLBEntry52_ref.regval_of (TLBEntry52_ref.read_from s)) else + if reg_name = "TLBEntry51" then SOME (TLBEntry51_ref.regval_of (TLBEntry51_ref.read_from s)) else + if reg_name = "TLBEntry50" then SOME (TLBEntry50_ref.regval_of (TLBEntry50_ref.read_from s)) else + if reg_name = "TLBEntry49" then SOME (TLBEntry49_ref.regval_of (TLBEntry49_ref.read_from s)) else + if reg_name = "TLBEntry48" then SOME (TLBEntry48_ref.regval_of (TLBEntry48_ref.read_from s)) else + if reg_name = "TLBEntry47" then SOME (TLBEntry47_ref.regval_of (TLBEntry47_ref.read_from s)) else + if reg_name = "TLBEntry46" then SOME (TLBEntry46_ref.regval_of (TLBEntry46_ref.read_from s)) else + if reg_name = "TLBEntry45" then SOME (TLBEntry45_ref.regval_of (TLBEntry45_ref.read_from s)) else + if reg_name = "TLBEntry44" then SOME (TLBEntry44_ref.regval_of (TLBEntry44_ref.read_from s)) else + if reg_name = "TLBEntry43" then SOME (TLBEntry43_ref.regval_of (TLBEntry43_ref.read_from s)) else + if reg_name = "TLBEntry42" then SOME (TLBEntry42_ref.regval_of (TLBEntry42_ref.read_from s)) else + if reg_name = "TLBEntry41" then SOME (TLBEntry41_ref.regval_of (TLBEntry41_ref.read_from s)) else + if reg_name = "TLBEntry40" then SOME (TLBEntry40_ref.regval_of (TLBEntry40_ref.read_from s)) else + if reg_name = "TLBEntry39" then SOME (TLBEntry39_ref.regval_of (TLBEntry39_ref.read_from s)) else + if reg_name = "TLBEntry38" then SOME (TLBEntry38_ref.regval_of (TLBEntry38_ref.read_from s)) else + if reg_name = "TLBEntry37" then SOME (TLBEntry37_ref.regval_of (TLBEntry37_ref.read_from s)) else + if reg_name = "TLBEntry36" then SOME (TLBEntry36_ref.regval_of (TLBEntry36_ref.read_from s)) else + if reg_name = "TLBEntry35" then SOME (TLBEntry35_ref.regval_of (TLBEntry35_ref.read_from s)) else + if reg_name = "TLBEntry34" then SOME (TLBEntry34_ref.regval_of (TLBEntry34_ref.read_from s)) else + if reg_name = "TLBEntry33" then SOME (TLBEntry33_ref.regval_of (TLBEntry33_ref.read_from s)) else + if reg_name = "TLBEntry32" then SOME (TLBEntry32_ref.regval_of (TLBEntry32_ref.read_from s)) else + if reg_name = "TLBEntry31" then SOME (TLBEntry31_ref.regval_of (TLBEntry31_ref.read_from s)) else + if reg_name = "TLBEntry30" then SOME (TLBEntry30_ref.regval_of (TLBEntry30_ref.read_from s)) else + if reg_name = "TLBEntry29" then SOME (TLBEntry29_ref.regval_of (TLBEntry29_ref.read_from s)) else + if reg_name = "TLBEntry28" then SOME (TLBEntry28_ref.regval_of (TLBEntry28_ref.read_from s)) else + if reg_name = "TLBEntry27" then SOME (TLBEntry27_ref.regval_of (TLBEntry27_ref.read_from s)) else + if reg_name = "TLBEntry26" then SOME (TLBEntry26_ref.regval_of (TLBEntry26_ref.read_from s)) else + if reg_name = "TLBEntry25" then SOME (TLBEntry25_ref.regval_of (TLBEntry25_ref.read_from s)) else + if reg_name = "TLBEntry24" then SOME (TLBEntry24_ref.regval_of (TLBEntry24_ref.read_from s)) else + if reg_name = "TLBEntry23" then SOME (TLBEntry23_ref.regval_of (TLBEntry23_ref.read_from s)) else + if reg_name = "TLBEntry22" then SOME (TLBEntry22_ref.regval_of (TLBEntry22_ref.read_from s)) else + if reg_name = "TLBEntry21" then SOME (TLBEntry21_ref.regval_of (TLBEntry21_ref.read_from s)) else + if reg_name = "TLBEntry20" then SOME (TLBEntry20_ref.regval_of (TLBEntry20_ref.read_from s)) else + if reg_name = "TLBEntry19" then SOME (TLBEntry19_ref.regval_of (TLBEntry19_ref.read_from s)) else + if reg_name = "TLBEntry18" then SOME (TLBEntry18_ref.regval_of (TLBEntry18_ref.read_from s)) else + if reg_name = "TLBEntry17" then SOME (TLBEntry17_ref.regval_of (TLBEntry17_ref.read_from s)) else + if reg_name = "TLBEntry16" then SOME (TLBEntry16_ref.regval_of (TLBEntry16_ref.read_from s)) else + if reg_name = "TLBEntry15" then SOME (TLBEntry15_ref.regval_of (TLBEntry15_ref.read_from s)) else + if reg_name = "TLBEntry14" then SOME (TLBEntry14_ref.regval_of (TLBEntry14_ref.read_from s)) else + if reg_name = "TLBEntry13" then SOME (TLBEntry13_ref.regval_of (TLBEntry13_ref.read_from s)) else + if reg_name = "TLBEntry12" then SOME (TLBEntry12_ref.regval_of (TLBEntry12_ref.read_from s)) else + if reg_name = "TLBEntry11" then SOME (TLBEntry11_ref.regval_of (TLBEntry11_ref.read_from s)) else + if reg_name = "TLBEntry10" then SOME (TLBEntry10_ref.regval_of (TLBEntry10_ref.read_from s)) else + if reg_name = "TLBEntry09" then SOME (TLBEntry09_ref.regval_of (TLBEntry09_ref.read_from s)) else + if reg_name = "TLBEntry08" then SOME (TLBEntry08_ref.regval_of (TLBEntry08_ref.read_from s)) else + if reg_name = "TLBEntry07" then SOME (TLBEntry07_ref.regval_of (TLBEntry07_ref.read_from s)) else + if reg_name = "TLBEntry06" then SOME (TLBEntry06_ref.regval_of (TLBEntry06_ref.read_from s)) else + if reg_name = "TLBEntry05" then SOME (TLBEntry05_ref.regval_of (TLBEntry05_ref.read_from s)) else + if reg_name = "TLBEntry04" then SOME (TLBEntry04_ref.regval_of (TLBEntry04_ref.read_from s)) else + if reg_name = "TLBEntry03" then SOME (TLBEntry03_ref.regval_of (TLBEntry03_ref.read_from s)) else + if reg_name = "TLBEntry02" then SOME (TLBEntry02_ref.regval_of (TLBEntry02_ref.read_from s)) else + if reg_name = "TLBEntry01" then SOME (TLBEntry01_ref.regval_of (TLBEntry01_ref.read_from s)) else + if reg_name = "TLBEntry00" then SOME (TLBEntry00_ref.regval_of (TLBEntry00_ref.read_from s)) else + if reg_name = "TLBXContext" then SOME (TLBXContext_ref.regval_of (TLBXContext_ref.read_from s)) else + if reg_name = "TLBEntryHi" then SOME (TLBEntryHi_ref.regval_of (TLBEntryHi_ref.read_from s)) else + if reg_name = "TLBWired" then SOME (TLBWired_ref.regval_of (TLBWired_ref.read_from s)) else + if reg_name = "TLBPageMask" then SOME (TLBPageMask_ref.regval_of (TLBPageMask_ref.read_from s)) else + if reg_name = "TLBContext" then SOME (TLBContext_ref.regval_of (TLBContext_ref.read_from s)) else + if reg_name = "TLBEntryLo1" then SOME (TLBEntryLo1_ref.regval_of (TLBEntryLo1_ref.read_from s)) else + if reg_name = "TLBEntryLo0" then SOME (TLBEntryLo0_ref.regval_of (TLBEntryLo0_ref.read_from s)) else + if reg_name = "TLBRandom" then SOME (TLBRandom_ref.regval_of (TLBRandom_ref.read_from s)) else + if reg_name = "TLBIndex" then SOME (TLBIndex_ref.regval_of (TLBIndex_ref.read_from s)) else + if reg_name = "TLBProbe" then SOME (TLBProbe_ref.regval_of (TLBProbe_ref.read_from s)) else + if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else + if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else + NONE))`; + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +val _ = Define ` + ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= + (if reg_name = "UART_RVALID" then OPTION_MAP (\ v . UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else + if reg_name = "UART_RDATA" then OPTION_MAP (\ v . UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else + if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v . UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else + if reg_name = "UART_WDATA" then OPTION_MAP (\ v . UART_WDATA_ref.write_to v s) (UART_WDATA_ref.of_regval v) else + if reg_name = "GPR" then OPTION_MAP (\ v . GPR_ref.write_to v s) (GPR_ref.of_regval v) else + if reg_name = "LO" then OPTION_MAP (\ v . LO_ref.write_to v s) (LO_ref.of_regval v) else + if reg_name = "HI" then OPTION_MAP (\ v . HI_ref.write_to v s) (HI_ref.of_regval v) else + if reg_name = "delayedPC" then OPTION_MAP (\ v . delayedPC_ref.write_to v s) (delayedPC_ref.of_regval v) else + if reg_name = "inBranchDelay" then OPTION_MAP (\ v . inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else + if reg_name = "branchPending" then OPTION_MAP (\ v . branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else + if reg_name = "CP0Status" then OPTION_MAP (\ v . CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else + if reg_name = "CP0ConfigK0" then OPTION_MAP (\ v . CP0ConfigK0_ref.write_to v s) (CP0ConfigK0_ref.of_regval v) else + if reg_name = "CP0UserLocal" then OPTION_MAP (\ v . CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else + if reg_name = "CP0HWREna" then OPTION_MAP (\ v . CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else + if reg_name = "CP0Count" then OPTION_MAP (\ v . CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else + if reg_name = "CP0BadVAddr" then OPTION_MAP (\ v . CP0BadVAddr_ref.write_to v s) (CP0BadVAddr_ref.of_regval v) else + if reg_name = "CP0LLAddr" then OPTION_MAP (\ v . CP0LLAddr_ref.write_to v s) (CP0LLAddr_ref.of_regval v) else + if reg_name = "CP0LLBit" then OPTION_MAP (\ v . CP0LLBit_ref.write_to v s) (CP0LLBit_ref.of_regval v) else + if reg_name = "CP0ErrorEPC" then OPTION_MAP (\ v . CP0ErrorEPC_ref.write_to v s) (CP0ErrorEPC_ref.of_regval v) else + if reg_name = "CP0EPC" then OPTION_MAP (\ v . CP0EPC_ref.write_to v s) (CP0EPC_ref.of_regval v) else + if reg_name = "CP0Cause" then OPTION_MAP (\ v . CP0Cause_ref.write_to v s) (CP0Cause_ref.of_regval v) else + if reg_name = "CP0Compare" then OPTION_MAP (\ v . CP0Compare_ref.write_to v s) (CP0Compare_ref.of_regval v) else + if reg_name = "TLBEntry63" then OPTION_MAP (\ v . TLBEntry63_ref.write_to v s) (TLBEntry63_ref.of_regval v) else + if reg_name = "TLBEntry62" then OPTION_MAP (\ v . TLBEntry62_ref.write_to v s) (TLBEntry62_ref.of_regval v) else + if reg_name = "TLBEntry61" then OPTION_MAP (\ v . TLBEntry61_ref.write_to v s) (TLBEntry61_ref.of_regval v) else + if reg_name = "TLBEntry60" then OPTION_MAP (\ v . TLBEntry60_ref.write_to v s) (TLBEntry60_ref.of_regval v) else + if reg_name = "TLBEntry59" then OPTION_MAP (\ v . TLBEntry59_ref.write_to v s) (TLBEntry59_ref.of_regval v) else + if reg_name = "TLBEntry58" then OPTION_MAP (\ v . TLBEntry58_ref.write_to v s) (TLBEntry58_ref.of_regval v) else + if reg_name = "TLBEntry57" then OPTION_MAP (\ v . TLBEntry57_ref.write_to v s) (TLBEntry57_ref.of_regval v) else + if reg_name = "TLBEntry56" then OPTION_MAP (\ v . TLBEntry56_ref.write_to v s) (TLBEntry56_ref.of_regval v) else + if reg_name = "TLBEntry55" then OPTION_MAP (\ v . TLBEntry55_ref.write_to v s) (TLBEntry55_ref.of_regval v) else + if reg_name = "TLBEntry54" then OPTION_MAP (\ v . TLBEntry54_ref.write_to v s) (TLBEntry54_ref.of_regval v) else + if reg_name = "TLBEntry53" then OPTION_MAP (\ v . TLBEntry53_ref.write_to v s) (TLBEntry53_ref.of_regval v) else + if reg_name = "TLBEntry52" then OPTION_MAP (\ v . TLBEntry52_ref.write_to v s) (TLBEntry52_ref.of_regval v) else + if reg_name = "TLBEntry51" then OPTION_MAP (\ v . TLBEntry51_ref.write_to v s) (TLBEntry51_ref.of_regval v) else + if reg_name = "TLBEntry50" then OPTION_MAP (\ v . TLBEntry50_ref.write_to v s) (TLBEntry50_ref.of_regval v) else + if reg_name = "TLBEntry49" then OPTION_MAP (\ v . TLBEntry49_ref.write_to v s) (TLBEntry49_ref.of_regval v) else + if reg_name = "TLBEntry48" then OPTION_MAP (\ v . TLBEntry48_ref.write_to v s) (TLBEntry48_ref.of_regval v) else + if reg_name = "TLBEntry47" then OPTION_MAP (\ v . TLBEntry47_ref.write_to v s) (TLBEntry47_ref.of_regval v) else + if reg_name = "TLBEntry46" then OPTION_MAP (\ v . TLBEntry46_ref.write_to v s) (TLBEntry46_ref.of_regval v) else + if reg_name = "TLBEntry45" then OPTION_MAP (\ v . TLBEntry45_ref.write_to v s) (TLBEntry45_ref.of_regval v) else + if reg_name = "TLBEntry44" then OPTION_MAP (\ v . TLBEntry44_ref.write_to v s) (TLBEntry44_ref.of_regval v) else + if reg_name = "TLBEntry43" then OPTION_MAP (\ v . TLBEntry43_ref.write_to v s) (TLBEntry43_ref.of_regval v) else + if reg_name = "TLBEntry42" then OPTION_MAP (\ v . TLBEntry42_ref.write_to v s) (TLBEntry42_ref.of_regval v) else + if reg_name = "TLBEntry41" then OPTION_MAP (\ v . TLBEntry41_ref.write_to v s) (TLBEntry41_ref.of_regval v) else + if reg_name = "TLBEntry40" then OPTION_MAP (\ v . TLBEntry40_ref.write_to v s) (TLBEntry40_ref.of_regval v) else + if reg_name = "TLBEntry39" then OPTION_MAP (\ v . TLBEntry39_ref.write_to v s) (TLBEntry39_ref.of_regval v) else + if reg_name = "TLBEntry38" then OPTION_MAP (\ v . TLBEntry38_ref.write_to v s) (TLBEntry38_ref.of_regval v) else + if reg_name = "TLBEntry37" then OPTION_MAP (\ v . TLBEntry37_ref.write_to v s) (TLBEntry37_ref.of_regval v) else + if reg_name = "TLBEntry36" then OPTION_MAP (\ v . TLBEntry36_ref.write_to v s) (TLBEntry36_ref.of_regval v) else + if reg_name = "TLBEntry35" then OPTION_MAP (\ v . TLBEntry35_ref.write_to v s) (TLBEntry35_ref.of_regval v) else + if reg_name = "TLBEntry34" then OPTION_MAP (\ v . TLBEntry34_ref.write_to v s) (TLBEntry34_ref.of_regval v) else + if reg_name = "TLBEntry33" then OPTION_MAP (\ v . TLBEntry33_ref.write_to v s) (TLBEntry33_ref.of_regval v) else + if reg_name = "TLBEntry32" then OPTION_MAP (\ v . TLBEntry32_ref.write_to v s) (TLBEntry32_ref.of_regval v) else + if reg_name = "TLBEntry31" then OPTION_MAP (\ v . TLBEntry31_ref.write_to v s) (TLBEntry31_ref.of_regval v) else + if reg_name = "TLBEntry30" then OPTION_MAP (\ v . TLBEntry30_ref.write_to v s) (TLBEntry30_ref.of_regval v) else + if reg_name = "TLBEntry29" then OPTION_MAP (\ v . TLBEntry29_ref.write_to v s) (TLBEntry29_ref.of_regval v) else + if reg_name = "TLBEntry28" then OPTION_MAP (\ v . TLBEntry28_ref.write_to v s) (TLBEntry28_ref.of_regval v) else + if reg_name = "TLBEntry27" then OPTION_MAP (\ v . TLBEntry27_ref.write_to v s) (TLBEntry27_ref.of_regval v) else + if reg_name = "TLBEntry26" then OPTION_MAP (\ v . TLBEntry26_ref.write_to v s) (TLBEntry26_ref.of_regval v) else + if reg_name = "TLBEntry25" then OPTION_MAP (\ v . TLBEntry25_ref.write_to v s) (TLBEntry25_ref.of_regval v) else + if reg_name = "TLBEntry24" then OPTION_MAP (\ v . TLBEntry24_ref.write_to v s) (TLBEntry24_ref.of_regval v) else + if reg_name = "TLBEntry23" then OPTION_MAP (\ v . TLBEntry23_ref.write_to v s) (TLBEntry23_ref.of_regval v) else + if reg_name = "TLBEntry22" then OPTION_MAP (\ v . TLBEntry22_ref.write_to v s) (TLBEntry22_ref.of_regval v) else + if reg_name = "TLBEntry21" then OPTION_MAP (\ v . TLBEntry21_ref.write_to v s) (TLBEntry21_ref.of_regval v) else + if reg_name = "TLBEntry20" then OPTION_MAP (\ v . TLBEntry20_ref.write_to v s) (TLBEntry20_ref.of_regval v) else + if reg_name = "TLBEntry19" then OPTION_MAP (\ v . TLBEntry19_ref.write_to v s) (TLBEntry19_ref.of_regval v) else + if reg_name = "TLBEntry18" then OPTION_MAP (\ v . TLBEntry18_ref.write_to v s) (TLBEntry18_ref.of_regval v) else + if reg_name = "TLBEntry17" then OPTION_MAP (\ v . TLBEntry17_ref.write_to v s) (TLBEntry17_ref.of_regval v) else + if reg_name = "TLBEntry16" then OPTION_MAP (\ v . TLBEntry16_ref.write_to v s) (TLBEntry16_ref.of_regval v) else + if reg_name = "TLBEntry15" then OPTION_MAP (\ v . TLBEntry15_ref.write_to v s) (TLBEntry15_ref.of_regval v) else + if reg_name = "TLBEntry14" then OPTION_MAP (\ v . TLBEntry14_ref.write_to v s) (TLBEntry14_ref.of_regval v) else + if reg_name = "TLBEntry13" then OPTION_MAP (\ v . TLBEntry13_ref.write_to v s) (TLBEntry13_ref.of_regval v) else + if reg_name = "TLBEntry12" then OPTION_MAP (\ v . TLBEntry12_ref.write_to v s) (TLBEntry12_ref.of_regval v) else + if reg_name = "TLBEntry11" then OPTION_MAP (\ v . TLBEntry11_ref.write_to v s) (TLBEntry11_ref.of_regval v) else + if reg_name = "TLBEntry10" then OPTION_MAP (\ v . TLBEntry10_ref.write_to v s) (TLBEntry10_ref.of_regval v) else + if reg_name = "TLBEntry09" then OPTION_MAP (\ v . TLBEntry09_ref.write_to v s) (TLBEntry09_ref.of_regval v) else + if reg_name = "TLBEntry08" then OPTION_MAP (\ v . TLBEntry08_ref.write_to v s) (TLBEntry08_ref.of_regval v) else + if reg_name = "TLBEntry07" then OPTION_MAP (\ v . TLBEntry07_ref.write_to v s) (TLBEntry07_ref.of_regval v) else + if reg_name = "TLBEntry06" then OPTION_MAP (\ v . TLBEntry06_ref.write_to v s) (TLBEntry06_ref.of_regval v) else + if reg_name = "TLBEntry05" then OPTION_MAP (\ v . TLBEntry05_ref.write_to v s) (TLBEntry05_ref.of_regval v) else + if reg_name = "TLBEntry04" then OPTION_MAP (\ v . TLBEntry04_ref.write_to v s) (TLBEntry04_ref.of_regval v) else + if reg_name = "TLBEntry03" then OPTION_MAP (\ v . TLBEntry03_ref.write_to v s) (TLBEntry03_ref.of_regval v) else + if reg_name = "TLBEntry02" then OPTION_MAP (\ v . TLBEntry02_ref.write_to v s) (TLBEntry02_ref.of_regval v) else + if reg_name = "TLBEntry01" then OPTION_MAP (\ v . TLBEntry01_ref.write_to v s) (TLBEntry01_ref.of_regval v) else + if reg_name = "TLBEntry00" then OPTION_MAP (\ v . TLBEntry00_ref.write_to v s) (TLBEntry00_ref.of_regval v) else + if reg_name = "TLBXContext" then OPTION_MAP (\ v . TLBXContext_ref.write_to v s) (TLBXContext_ref.of_regval v) else + if reg_name = "TLBEntryHi" then OPTION_MAP (\ v . TLBEntryHi_ref.write_to v s) (TLBEntryHi_ref.of_regval v) else + if reg_name = "TLBWired" then OPTION_MAP (\ v . TLBWired_ref.write_to v s) (TLBWired_ref.of_regval v) else + if reg_name = "TLBPageMask" then OPTION_MAP (\ v . TLBPageMask_ref.write_to v s) (TLBPageMask_ref.of_regval v) else + if reg_name = "TLBContext" then OPTION_MAP (\ v . TLBContext_ref.write_to v s) (TLBContext_ref.of_regval v) else + if reg_name = "TLBEntryLo1" then OPTION_MAP (\ v . TLBEntryLo1_ref.write_to v s) (TLBEntryLo1_ref.of_regval v) else + if reg_name = "TLBEntryLo0" then OPTION_MAP (\ v . TLBEntryLo0_ref.write_to v s) (TLBEntryLo0_ref.of_regval v) else + if reg_name = "TLBRandom" then OPTION_MAP (\ v . TLBRandom_ref.write_to v s) (TLBRandom_ref.of_regval v) else + if reg_name = "TLBIndex" then OPTION_MAP (\ v . TLBIndex_ref.write_to v s) (TLBIndex_ref.of_regval v) else + if reg_name = "TLBProbe" then OPTION_MAP (\ v . TLBProbe_ref.write_to v s) (TLBProbe_ref.of_regval v) else + if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else + if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else + NONE))`; + + +val _ = Define ` + ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))= (get_regval, set_regval))`; + + + +val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception)monadR``); +val _ = type_abbrev((* 'a *) "M" , ``: (regstate, 'a, exception)monad``); +val _ = export_theory() + diff --git a/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml index 160f550f..bd1d98af 100644 --- a/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml +++ b/snapshots/hol4/sail/riscv/riscvAuxiliaryScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from riscv.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory riscvTheory; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory riscvTheory; val _ = numLib.prefer_num(); diff --git a/snapshots/hol4/sail/riscv/riscvScript.sml b/snapshots/hol4/sail/riscv/riscvScript.sml index e8514af3..bd56ca74 100644 --- a/snapshots/hol4/sail/riscv/riscvScript.sml +++ b/snapshots/hol4/sail/riscv/riscvScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from riscv.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory riscv_typesTheory riscv_extrasTheory; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory riscv_typesTheory riscv_extrasTheory; val _ = numLib.prefer_num(); @@ -10,14 +10,51 @@ val _ = new_theory "riscv" (*Generated by Sail from riscv.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Riscv_types*) (*open import Riscv_extras*) +(*val spc_forwards : unit -> string*) + +val _ = Define ` + ((spc_forwards:unit -> string) () = " ")`; + + +(*val spc_backwards : string -> unit*) + +val _ = Define ` + ((spc_backwards:string -> unit) s= () )`; + + +(*val opt_spc_forwards : unit -> string*) + +val _ = Define ` + ((opt_spc_forwards:unit -> string) () = "")`; + + +(*val opt_spc_backwards : string -> unit*) + +val _ = Define ` + ((opt_spc_backwards:string -> unit) s= () )`; + + +(*val def_spc_forwards : unit -> string*) + +val _ = Define ` + ((def_spc_forwards:unit -> string) () = " ")`; + + +(*val def_spc_backwards : string -> unit*) + +val _ = Define ` + ((def_spc_backwards:string -> unit) s= () )`; + + @@ -39,7 +76,7 @@ val _ = new_theory "riscv" (*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) val _ = Define ` - ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1= ((get_slice_int0 n m o1 : 'n words$word)))`; + ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1= ((get_slice_int n m o1 : 'n words$word)))`; (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) @@ -60,28 +97,73 @@ val _ = Define ` (*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) val _ = Define ` - ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (state_monad$seqS + ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (sail2_state_monad$seqS (write_ram (( 64 : int):ii) width (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word) addr data) - (state_monad$returnS T)))`; + (sail2_state_monad$returnS T)))`; (*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) -(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (maybe (mword 'int8_times_n))*) val _ = Define ` - ((RISCV_read:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= (state_monad$bindS - (read_ram (( 64 : int):ii) width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word) addr - : ( 'int8_times_n words$word) M) (\ (w__0 : 'int8_times_n words$word) . - state_monad$returnS (SOME w__0))))`; + ((RISCV_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl res= + ((case (aq, rl, res) of + (F, F, F) => sail2_state_monad$bindS + (MEMr (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__0 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__0)) + | (T, F, F) => sail2_state_monad$bindS + (MEMr_acquire (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__1 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__1)) + | (T, T, F) => sail2_state_monad$bindS + (MEMr_strong_acquire (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__2 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__2)) + | (F, F, T) => sail2_state_monad$bindS + (MEMr_reserved (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__3 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__3)) + | (T, F, T) => sail2_state_monad$bindS + (MEMr_reserved_acquire (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__4 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__4)) + | (T, T, T) => sail2_state_monad$bindS + (MEMr_reserved_strong_acquire (( 64 : int):ii) width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word) addr + : ( 'int8_times_n words$word) M) (\ (w__5 : 'int8_times_n words$word) . + sail2_state_monad$returnS (SOME w__5)) + | (F, T, F) => sail2_state_monad$returnS NONE + | (F, T, T) => sail2_state_monad$returnS NONE + )))`; (*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) @@ -101,7 +183,7 @@ val _ = Define ` (*val coerce_int_nat : ii -> M ii*) val _ = Define ` - ((coerce_int_nat:int ->(regstate)state_monad$sequential_state ->(((int),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) x= (state_monad$seqS (state_monad$assert_expS T "") (state_monad$returnS x)))`; + ((coerce_int_nat:int ->(regstate)sail2_state_monad$sequential_state ->(((int),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) x= (sail2_state_monad$seqS (sail2_state_monad$assert_expS T "") (sail2_state_monad$returnS x)))`; (*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) @@ -161,13 +243,13 @@ val _ = Define ` (*val vector64 : ii -> mword ty64*) val _ = Define ` - ((vector64:int ->(64)words$word) n= ((get_slice_int0 (( 64 : int):ii) n (( 0 : int):ii) : 64 words$word)))`; + ((vector64:int ->(64)words$word) n= ((get_slice_int (( 64 : int):ii) n (( 0 : int):ii) : 64 words$word)))`; (*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) val _ = Define ` - ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int0 l n (( 0 : int):ii) : 'l words$word)))`; + ((to_bits:int -> int -> 'l words$word) l n= ((get_slice_int l n (( 0 : int):ii) : 'l words$word)))`; (*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) @@ -231,29 +313,89 @@ val _ = Define ` (*val rX : integer -> M (mword ty64)*) val _ = Define ` - ((rX:int ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) l__81= - (if (((l__81 = (( 0 : int):ii)))) then - state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + ((rX:int ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r= + (let p0_ = r in + if (((p0_ = (( 0 : int):ii)))) then + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word) - else state_monad$bindS - (state_monad$read_regS Xs_ref) (\ (w__0 : xlenbits list) . - state_monad$returnS ((access_list_dec w__0 l__81 : 64 words$word)))))`; + else if (((p0_ = (( 1 : int):ii)))) then (sail2_state_monad$read_regS x1_ref : ( 64 words$word) M) + else if (((p0_ = (( 2 : int):ii)))) then (sail2_state_monad$read_regS x2_ref : ( 64 words$word) M) + else if (((p0_ = (( 3 : int):ii)))) then (sail2_state_monad$read_regS x3_ref : ( 64 words$word) M) + else if (((p0_ = (( 4 : int):ii)))) then (sail2_state_monad$read_regS x4_ref : ( 64 words$word) M) + else if (((p0_ = (( 5 : int):ii)))) then (sail2_state_monad$read_regS x5_ref : ( 64 words$word) M) + else if (((p0_ = (( 6 : int):ii)))) then (sail2_state_monad$read_regS x6_ref : ( 64 words$word) M) + else if (((p0_ = (( 7 : int):ii)))) then (sail2_state_monad$read_regS x7_ref : ( 64 words$word) M) + else if (((p0_ = (( 8 : int):ii)))) then (sail2_state_monad$read_regS x8_ref : ( 64 words$word) M) + else if (((p0_ = (( 9 : int):ii)))) then (sail2_state_monad$read_regS x9_ref : ( 64 words$word) M) + else if (((p0_ = (( 10 : int):ii)))) then (sail2_state_monad$read_regS x10_ref : ( 64 words$word) M) + else if (((p0_ = (( 11 : int):ii)))) then (sail2_state_monad$read_regS x11_ref : ( 64 words$word) M) + else if (((p0_ = (( 12 : int):ii)))) then (sail2_state_monad$read_regS x12_ref : ( 64 words$word) M) + else if (((p0_ = (( 13 : int):ii)))) then (sail2_state_monad$read_regS x13_ref : ( 64 words$word) M) + else if (((p0_ = (( 14 : int):ii)))) then (sail2_state_monad$read_regS x14_ref : ( 64 words$word) M) + else if (((p0_ = (( 15 : int):ii)))) then (sail2_state_monad$read_regS x15_ref : ( 64 words$word) M) + else if (((p0_ = (( 16 : int):ii)))) then (sail2_state_monad$read_regS x16_ref : ( 64 words$word) M) + else if (((p0_ = (( 17 : int):ii)))) then (sail2_state_monad$read_regS x17_ref : ( 64 words$word) M) + else if (((p0_ = (( 18 : int):ii)))) then (sail2_state_monad$read_regS x18_ref : ( 64 words$word) M) + else if (((p0_ = (( 19 : int):ii)))) then (sail2_state_monad$read_regS x19_ref : ( 64 words$word) M) + else if (((p0_ = (( 20 : int):ii)))) then (sail2_state_monad$read_regS x20_ref : ( 64 words$word) M) + else if (((p0_ = (( 21 : int):ii)))) then (sail2_state_monad$read_regS x21_ref : ( 64 words$word) M) + else if (((p0_ = (( 22 : int):ii)))) then (sail2_state_monad$read_regS x22_ref : ( 64 words$word) M) + else if (((p0_ = (( 23 : int):ii)))) then (sail2_state_monad$read_regS x23_ref : ( 64 words$word) M) + else if (((p0_ = (( 24 : int):ii)))) then (sail2_state_monad$read_regS x24_ref : ( 64 words$word) M) + else if (((p0_ = (( 25 : int):ii)))) then (sail2_state_monad$read_regS x25_ref : ( 64 words$word) M) + else if (((p0_ = (( 26 : int):ii)))) then (sail2_state_monad$read_regS x26_ref : ( 64 words$word) M) + else if (((p0_ = (( 27 : int):ii)))) then (sail2_state_monad$read_regS x27_ref : ( 64 words$word) M) + else if (((p0_ = (( 28 : int):ii)))) then (sail2_state_monad$read_regS x28_ref : ( 64 words$word) M) + else if (((p0_ = (( 29 : int):ii)))) then (sail2_state_monad$read_regS x29_ref : ( 64 words$word) M) + else if (((p0_ = (( 30 : int):ii)))) then (sail2_state_monad$read_regS x30_ref : ( 64 words$word) M) + else (sail2_state_monad$read_regS x31_ref : ( 64 words$word) M)))`; (*val wX : integer -> mword ty64 -> M unit*) val _ = Define ` - ((wX:int ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r v= - (if (((r <> (( 0 : int):ii)))) then state_monad$bindS - (state_monad$read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) . state_monad$seqS - (state_monad$write_regS Xs_ref ((update_list_dec w__0 r v : ( 64 words$word) list))) - (state_monad$returnS ((prerr_endline - ((STRCAT "x" - ((STRCAT ((stringFromInteger r)) - ((STRCAT " <- " ((string_of_vec v)))))))))))) - else state_monad$returnS () ))`; + ((wX:int ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r v= + (let p0_ = r in sail2_state_monad$seqS + (if (((p0_ = (( 0 : int):ii)))) then sail2_state_monad$returnS () + else if (((p0_ = (( 1 : int):ii)))) then sail2_state_monad$write_regS x1_ref v + else if (((p0_ = (( 2 : int):ii)))) then sail2_state_monad$write_regS x2_ref v + else if (((p0_ = (( 3 : int):ii)))) then sail2_state_monad$write_regS x3_ref v + else if (((p0_ = (( 4 : int):ii)))) then sail2_state_monad$write_regS x4_ref v + else if (((p0_ = (( 5 : int):ii)))) then sail2_state_monad$write_regS x5_ref v + else if (((p0_ = (( 6 : int):ii)))) then sail2_state_monad$write_regS x6_ref v + else if (((p0_ = (( 7 : int):ii)))) then sail2_state_monad$write_regS x7_ref v + else if (((p0_ = (( 8 : int):ii)))) then sail2_state_monad$write_regS x8_ref v + else if (((p0_ = (( 9 : int):ii)))) then sail2_state_monad$write_regS x9_ref v + else if (((p0_ = (( 10 : int):ii)))) then sail2_state_monad$write_regS x10_ref v + else if (((p0_ = (( 11 : int):ii)))) then sail2_state_monad$write_regS x11_ref v + else if (((p0_ = (( 12 : int):ii)))) then sail2_state_monad$write_regS x12_ref v + else if (((p0_ = (( 13 : int):ii)))) then sail2_state_monad$write_regS x13_ref v + else if (((p0_ = (( 14 : int):ii)))) then sail2_state_monad$write_regS x14_ref v + else if (((p0_ = (( 15 : int):ii)))) then sail2_state_monad$write_regS x15_ref v + else if (((p0_ = (( 16 : int):ii)))) then sail2_state_monad$write_regS x16_ref v + else if (((p0_ = (( 17 : int):ii)))) then sail2_state_monad$write_regS x17_ref v + else if (((p0_ = (( 18 : int):ii)))) then sail2_state_monad$write_regS x18_ref v + else if (((p0_ = (( 19 : int):ii)))) then sail2_state_monad$write_regS x19_ref v + else if (((p0_ = (( 20 : int):ii)))) then sail2_state_monad$write_regS x20_ref v + else if (((p0_ = (( 21 : int):ii)))) then sail2_state_monad$write_regS x21_ref v + else if (((p0_ = (( 22 : int):ii)))) then sail2_state_monad$write_regS x22_ref v + else if (((p0_ = (( 23 : int):ii)))) then sail2_state_monad$write_regS x23_ref v + else if (((p0_ = (( 24 : int):ii)))) then sail2_state_monad$write_regS x24_ref v + else if (((p0_ = (( 25 : int):ii)))) then sail2_state_monad$write_regS x25_ref v + else if (((p0_ = (( 26 : int):ii)))) then sail2_state_monad$write_regS x26_ref v + else if (((p0_ = (( 27 : int):ii)))) then sail2_state_monad$write_regS x27_ref v + else if (((p0_ = (( 28 : int):ii)))) then sail2_state_monad$write_regS x28_ref v + else if (((p0_ = (( 29 : int):ii)))) then sail2_state_monad$write_regS x29_ref v + else if (((p0_ = (( 30 : int):ii)))) then sail2_state_monad$write_regS x30_ref v + else sail2_state_monad$write_regS x31_ref v) + (sail2_state_monad$returnS (if (((r <> (( 0 : int):ii)))) then + print_endline + ((STRCAT "x" + ((STRCAT ((stringFromInteger r)) + ((STRCAT " <- " ((string_of_bits v)))))))) + else () ))))`; (*val reg_name_abi : mword ty5 -> string*) @@ -330,9 +472,9 @@ val _ = Define ` val _ = Define ` ((Architecture_of_num:int -> Architecture) arg_= - (let l__79 = arg_ in - if (((l__79 = (( 0 : int):ii)))) then RV32 - else if (((l__79 = (( 1 : int):ii)))) then RV64 + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RV32 + else if (((p0_ = (( 1 : int):ii)))) then RV64 else RV128))`; @@ -369,9 +511,9 @@ val _ = Define ` val _ = Define ` ((Privilege_of_num:int -> Privilege) arg_= - (let l__77 = arg_ in - if (((l__77 = (( 0 : int):ii)))) then User - else if (((l__77 = (( 1 : int):ii)))) then Supervisor + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then User + else if (((p0_ = (( 1 : int):ii)))) then Supervisor else Machine))`; @@ -413,10 +555,10 @@ val _ = Define ` val _ = Define ` ((AccessType_of_num:int -> AccessType) arg_= - (let l__74 = arg_ in - if (((l__74 = (( 0 : int):ii)))) then Read - else if (((l__74 = (( 1 : int):ii)))) then Write - else if (((l__74 = (( 2 : int):ii)))) then ReadWrite + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Read + else if (((p0_ = (( 1 : int):ii)))) then Write + else if (((p0_ = (( 2 : int):ii)))) then ReadWrite else Execute))`; @@ -427,12 +569,19 @@ val _ = Define ` ((case arg_ of Read => (( 0 : int):ii) | Write => (( 1 : int):ii) | ReadWrite => (( 2 : int):ii) | Execute => (( 3 : int):ii) )))`; +(*val accessType_to_str : AccessType -> string*) + +val _ = Define ` + ((accessType_to_str:AccessType -> string) a= + ((case a of Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" )))`; + + (*val ReadType_of_num : integer -> ReadType*) val _ = Define ` ((ReadType_of_num:int -> ReadType) arg_= - (let l__73 = arg_ in - if (((l__73 = (( 0 : int):ii)))) then Instruction + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Instruction else Data))`; @@ -442,26 +591,32 @@ val _ = Define ` ((num_of_ReadType:ReadType -> int) arg_= ((case arg_ of Instruction => (( 0 : int):ii) | Data => (( 1 : int):ii) )))`; +(*val readType_to_str : ReadType -> string*) + +val _ = Define ` + ((readType_to_str:ReadType -> string) r= ((case r of Instruction => "I" | Data => "D" )))`; + + (*val ExceptionType_of_num : integer -> ExceptionType*) val _ = Define ` ((ExceptionType_of_num:int -> ExceptionType) arg_= - (let l__58 = arg_ in - if (((l__58 = (( 0 : int):ii)))) then E_Fetch_Addr_Align - else if (((l__58 = (( 1 : int):ii)))) then E_Fetch_Access_Fault - else if (((l__58 = (( 2 : int):ii)))) then E_Illegal_Instr - else if (((l__58 = (( 3 : int):ii)))) then E_Breakpoint - else if (((l__58 = (( 4 : int):ii)))) then E_Load_Addr_Align - else if (((l__58 = (( 5 : int):ii)))) then E_Load_Access_Fault - else if (((l__58 = (( 6 : int):ii)))) then E_SAMO_Addr_Align - else if (((l__58 = (( 7 : int):ii)))) then E_SAMO_Access_Fault - else if (((l__58 = (( 8 : int):ii)))) then E_U_EnvCall - else if (((l__58 = (( 9 : int):ii)))) then E_S_EnvCall - else if (((l__58 = (( 10 : int):ii)))) then E_Reserved_10 - else if (((l__58 = (( 11 : int):ii)))) then E_M_EnvCall - else if (((l__58 = (( 12 : int):ii)))) then E_Fetch_Page_Fault - else if (((l__58 = (( 13 : int):ii)))) then E_Load_Page_Fault - else if (((l__58 = (( 14 : int):ii)))) then E_Reserved_14 + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then E_Fetch_Addr_Align + else if (((p0_ = (( 1 : int):ii)))) then E_Fetch_Access_Fault + else if (((p0_ = (( 2 : int):ii)))) then E_Illegal_Instr + else if (((p0_ = (( 3 : int):ii)))) then E_Breakpoint + else if (((p0_ = (( 4 : int):ii)))) then E_Load_Addr_Align + else if (((p0_ = (( 5 : int):ii)))) then E_Load_Access_Fault + else if (((p0_ = (( 6 : int):ii)))) then E_SAMO_Addr_Align + else if (((p0_ = (( 7 : int):ii)))) then E_SAMO_Access_Fault + else if (((p0_ = (( 8 : int):ii)))) then E_U_EnvCall + else if (((p0_ = (( 9 : int):ii)))) then E_S_EnvCall + else if (((p0_ = (( 10 : int):ii)))) then E_Reserved_10 + else if (((p0_ = (( 11 : int):ii)))) then E_M_EnvCall + else if (((p0_ = (( 12 : int):ii)))) then E_Fetch_Page_Fault + else if (((p0_ = (( 13 : int):ii)))) then E_Load_Page_Fault + else if (((p0_ = (( 14 : int):ii)))) then E_Reserved_14 else E_SAMO_Page_Fault))`; @@ -518,7 +673,7 @@ val _ = Define ` val _ = Define ` ((exceptionType_to_str:ExceptionType -> string) e= ((case e of - E_Fetch_Addr_Align => "fisaligned-fetch" + E_Fetch_Addr_Align => "misaligned-fetch" | E_Fetch_Access_Fault => "fetch-access-fault" | E_Illegal_Instr => "illegal-instruction" | E_Breakpoint => "breakpoint" @@ -541,15 +696,15 @@ val _ = Define ` val _ = Define ` ((InterruptType_of_num:int -> InterruptType) arg_= - (let l__50 = arg_ in - if (((l__50 = (( 0 : int):ii)))) then I_U_Software - else if (((l__50 = (( 1 : int):ii)))) then I_S_Software - else if (((l__50 = (( 2 : int):ii)))) then I_M_Software - else if (((l__50 = (( 3 : int):ii)))) then I_U_Timer - else if (((l__50 = (( 4 : int):ii)))) then I_S_Timer - else if (((l__50 = (( 5 : int):ii)))) then I_M_Timer - else if (((l__50 = (( 6 : int):ii)))) then I_U_External - else if (((l__50 = (( 7 : int):ii)))) then I_S_External + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then I_U_Software + else if (((p0_ = (( 1 : int):ii)))) then I_S_Software + else if (((p0_ = (( 2 : int):ii)))) then I_M_Software + else if (((p0_ = (( 3 : int):ii)))) then I_U_Timer + else if (((p0_ = (( 4 : int):ii)))) then I_S_Timer + else if (((p0_ = (( 5 : int):ii)))) then I_M_Timer + else if (((p0_ = (( 6 : int):ii)))) then I_U_External + else if (((p0_ = (( 7 : int):ii)))) then I_S_External else I_M_External))`; @@ -591,9 +746,9 @@ val _ = Define ` val _ = Define ` ((TrapVectorMode_of_num:int -> TrapVectorMode) arg_= - (let l__48 = arg_ in - if (((l__48 = (( 0 : int):ii)))) then TV_Direct - else if (((l__48 = (( 1 : int):ii)))) then TV_Vector + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then TV_Direct + else if (((p0_ = (( 1 : int):ii)))) then TV_Vector else TV_Reserved))`; @@ -617,23 +772,23 @@ val _ = Define ` (*val not_implemented : forall 'a. string -> M 'a*) val _ = Define ` - ((not_implemented:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) message= (state_monad$throwS (Error_not_implemented message)))`; + ((not_implemented:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) message= (sail2_state_monad$throwS (Error_not_implemented message)))`; (*val internal_error : forall 'a. string -> M 'a*) val _ = Define ` - ((internal_error:string ->(regstate)state_monad$sequential_state ->(('a,(exception))state_monad$result#(regstate)state_monad$sequential_state)set) s= (state_monad$seqS (state_monad$assert_expS F s) (state_monad$throwS (Error_internal_error () ))))`; + ((internal_error:string ->(regstate)sail2_state_monad$sequential_state ->(('a,(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (sail2_state_monad$assert_expS F s) (sail2_state_monad$throwS (Error_internal_error () ))))`; (*val ExtStatus_of_num : integer -> ExtStatus*) val _ = Define ` ((ExtStatus_of_num:int -> ExtStatus) arg_= - (let l__45 = arg_ in - if (((l__45 = (( 0 : int):ii)))) then Off - else if (((l__45 = (( 1 : int):ii)))) then Initial - else if (((l__45 = (( 2 : int):ii)))) then Clean + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Off + else if (((p0_ = (( 1 : int):ii)))) then Initial + else if (((p0_ = (( 2 : int):ii)))) then Clean else Dirty))`; @@ -671,9 +826,9 @@ val _ = Define ` val _ = Define ` ((SATPMode_of_num:int -> SATPMode) arg_= - (let l__43 = arg_ in - if (((l__43 = (( 0 : int):ii)))) then Sbare - else if (((l__43 = (( 1 : int):ii)))) then Sv32 + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Sbare + else if (((p0_ = (( 1 : int):ii)))) then Sv32 else Sv39))`; @@ -687,15 +842,28 @@ val _ = Define ` val _ = Define ` ((satpMode_of_bits:Architecture ->(4)words$word ->(SATPMode)option) (a : Architecture) (m : satp_mode)= - ((case (a, m) of (g__113, b__0) => SOME Sbare )))`; + ((case (a, m) of + (g__33, b__0) => + if (((b__0 = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) then SOME Sbare + else + (case (g__33, b__0) of + (RV32, b__1) => + if (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word)))) then + SOME Sv32 else (case (RV32, b__1) of (g__34, g__35) => NONE ) + | (RV64, b__2) => + if (((b__2 = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) then + SOME Sv39 else (case (RV64, b__2) of (g__34, g__35) => NONE ) + | (g__34, g__35) => NONE + ) + )))`; (*val uop_of_num : integer -> uop*) val _ = Define ` ((uop_of_num:int -> uop) arg_= - (let l__42 = arg_ in - if (((l__42 = (( 0 : int):ii)))) then RISCV_LUI + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_LUI else RISCV_AUIPC))`; @@ -709,12 +877,12 @@ val _ = Define ` val _ = Define ` ((bop_of_num:int -> bop) arg_= - (let l__37 = arg_ in - if (((l__37 = (( 0 : int):ii)))) then RISCV_BEQ - else if (((l__37 = (( 1 : int):ii)))) then RISCV_BNE - else if (((l__37 = (( 2 : int):ii)))) then RISCV_BLT - else if (((l__37 = (( 3 : int):ii)))) then RISCV_BGE - else if (((l__37 = (( 4 : int):ii)))) then RISCV_BLTU + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_BEQ + else if (((p0_ = (( 1 : int):ii)))) then RISCV_BNE + else if (((p0_ = (( 2 : int):ii)))) then RISCV_BLT + else if (((p0_ = (( 3 : int):ii)))) then RISCV_BGE + else if (((p0_ = (( 4 : int):ii)))) then RISCV_BLTU else RISCV_BGEU))`; @@ -736,12 +904,12 @@ val _ = Define ` val _ = Define ` ((iop_of_num:int -> iop) arg_= - (let l__32 = arg_ in - if (((l__32 = (( 0 : int):ii)))) then RISCV_ADDI - else if (((l__32 = (( 1 : int):ii)))) then RISCV_SLTI - else if (((l__32 = (( 2 : int):ii)))) then RISCV_SLTIU - else if (((l__32 = (( 3 : int):ii)))) then RISCV_XORI - else if (((l__32 = (( 4 : int):ii)))) then RISCV_ORI + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDI + else if (((p0_ = (( 1 : int):ii)))) then RISCV_SLTI + else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLTIU + else if (((p0_ = (( 3 : int):ii)))) then RISCV_XORI + else if (((p0_ = (( 4 : int):ii)))) then RISCV_ORI else RISCV_ANDI))`; @@ -763,9 +931,9 @@ val _ = Define ` val _ = Define ` ((sop_of_num:int -> sop) arg_= - (let l__30 = arg_ in - if (((l__30 = (( 0 : int):ii)))) then RISCV_SLLI - else if (((l__30 = (( 1 : int):ii)))) then RISCV_SRLI + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_SLLI + else if (((p0_ = (( 1 : int):ii)))) then RISCV_SRLI else RISCV_SRAI))`; @@ -780,16 +948,16 @@ val _ = Define ` val _ = Define ` ((rop_of_num:int -> rop) arg_= - (let l__21 = arg_ in - if (((l__21 = (( 0 : int):ii)))) then RISCV_ADD - else if (((l__21 = (( 1 : int):ii)))) then RISCV_SUB - else if (((l__21 = (( 2 : int):ii)))) then RISCV_SLL - else if (((l__21 = (( 3 : int):ii)))) then RISCV_SLT - else if (((l__21 = (( 4 : int):ii)))) then RISCV_SLTU - else if (((l__21 = (( 5 : int):ii)))) then RISCV_XOR - else if (((l__21 = (( 6 : int):ii)))) then RISCV_SRL - else if (((l__21 = (( 7 : int):ii)))) then RISCV_SRA - else if (((l__21 = (( 8 : int):ii)))) then RISCV_OR + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_ADD + else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUB + else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLL + else if (((p0_ = (( 3 : int):ii)))) then RISCV_SLT + else if (((p0_ = (( 4 : int):ii)))) then RISCV_SLTU + else if (((p0_ = (( 5 : int):ii)))) then RISCV_XOR + else if (((p0_ = (( 6 : int):ii)))) then RISCV_SRL + else if (((p0_ = (( 7 : int):ii)))) then RISCV_SRA + else if (((p0_ = (( 8 : int):ii)))) then RISCV_OR else RISCV_AND))`; @@ -815,11 +983,11 @@ val _ = Define ` val _ = Define ` ((ropw_of_num:int -> ropw) arg_= - (let l__17 = arg_ in - if (((l__17 = (( 0 : int):ii)))) then RISCV_ADDW - else if (((l__17 = (( 1 : int):ii)))) then RISCV_SUBW - else if (((l__17 = (( 2 : int):ii)))) then RISCV_SLLW - else if (((l__17 = (( 3 : int):ii)))) then RISCV_SRLW + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then RISCV_ADDW + else if (((p0_ = (( 1 : int):ii)))) then RISCV_SUBW + else if (((p0_ = (( 2 : int):ii)))) then RISCV_SLLW + else if (((p0_ = (( 3 : int):ii)))) then RISCV_SRLW else RISCV_SRAW))`; @@ -840,15 +1008,15 @@ val _ = Define ` val _ = Define ` ((amoop_of_num:int -> amoop) arg_= - (let l__9 = arg_ in - if (((l__9 = (( 0 : int):ii)))) then AMOSWAP - else if (((l__9 = (( 1 : int):ii)))) then AMOADD - else if (((l__9 = (( 2 : int):ii)))) then AMOXOR - else if (((l__9 = (( 3 : int):ii)))) then AMOAND - else if (((l__9 = (( 4 : int):ii)))) then AMOOR - else if (((l__9 = (( 5 : int):ii)))) then AMOMIN - else if (((l__9 = (( 6 : int):ii)))) then AMOMAX - else if (((l__9 = (( 7 : int):ii)))) then AMOMINU + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then AMOSWAP + else if (((p0_ = (( 1 : int):ii)))) then AMOADD + else if (((p0_ = (( 2 : int):ii)))) then AMOXOR + else if (((p0_ = (( 3 : int):ii)))) then AMOAND + else if (((p0_ = (( 4 : int):ii)))) then AMOOR + else if (((p0_ = (( 5 : int):ii)))) then AMOMIN + else if (((p0_ = (( 6 : int):ii)))) then AMOMAX + else if (((p0_ = (( 7 : int):ii)))) then AMOMINU else AMOMAXU))`; @@ -873,9 +1041,9 @@ val _ = Define ` val _ = Define ` ((csrop_of_num:int -> csrop) arg_= - (let l__7 = arg_ in - if (((l__7 = (( 0 : int):ii)))) then CSRRW - else if (((l__7 = (( 1 : int):ii)))) then CSRRS + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then CSRRW + else if (((p0_ = (( 1 : int):ii)))) then CSRRS else CSRRC))`; @@ -889,10 +1057,10 @@ val _ = Define ` val _ = Define ` ((word_width_of_num:int -> word_width) arg_= - (let l__4 = arg_ in - if (((l__4 = (( 0 : int):ii)))) then BYTE - else if (((l__4 = (( 1 : int):ii)))) then HALF - else if (((l__4 = (( 2 : int):ii)))) then WORD + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then BYTE + else if (((p0_ = (( 1 : int):ii)))) then HALF + else if (((p0_ = (( 2 : int):ii)))) then WORD else DOUBLE))`; @@ -903,282 +1071,1001 @@ val _ = Define ` ((case arg_ of BYTE => (( 0 : int):ii) | HALF => (( 1 : int):ii) | WORD => (( 2 : int):ii) | DOUBLE => (( 3 : int):ii) )))`; -(*val is_aligned_addr : mword ty64 -> integer -> bool*) +(*val reg_name_forwards : mword ty5 -> string*) val _ = Define ` - ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= - (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):ii)))`; + ((reg_name_forwards:(5)words$word -> string) arg_= + (let p0_ = arg_ in + if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) + then + "zero" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then + "ra" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then + "sp" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then + "gp" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + "tp" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then + "t0" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then + "t1" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then + "t2" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + "fp" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then + "s1" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then + "a0" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then + "a1" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + "a2" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then + "a3" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then + "a4" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then + "a5" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + "a6" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then + "a7" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then + "s2" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then + "s3" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + "s4" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then + "s5" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then + "s6" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then + "s7" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + "s8" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then + "s9" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then + "s10" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then + "s11" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then + "t3" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then + "t4" + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then + "t5" + else "t6"))`; -(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val reg_name_backwards : string -> mword ty5*) val _ = Define ` - ((checked_mem_read:ReadType ->(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int)= (state_monad$bindS - (RISCV_read addr width : ( ( 'int8_times_n words$word)option) M) (\ (w__0 : - ( 'int8_times_n words$word)option) . - state_monad$returnS ((case (t, w__0) of - (Instruction, NONE) => MemException E_Fetch_Access_Fault - | (Data, NONE) => MemException E_Load_Access_Fault - | (_, SOME (v)) => MemValue v - )))))`; + ((reg_name_backwards:string ->(5)words$word) arg_= + ((case arg_ of + "zero" => (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + | "ra" => (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word) + | "sp" => (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word) + | "gp" => (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word) + | "tp" => (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word) + | "t0" => (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word) + | "t1" => (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word) + | "t2" => (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word) + | "fp" => (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word) + | "s1" => (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word) + | "a0" => (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word) + | "a1" => (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word) + | "a2" => (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word) + | "a3" => (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word) + | "a4" => (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word) + | "a5" => (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word) + | "a6" => (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word) + | "a7" => (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word) + | "s2" => (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word) + | "s3" => (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word) + | "s4" => (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word) + | "s5" => (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word) + | "s6" => (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word) + | "s7" => (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word) + | "s8" => (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word) + | "s9" => (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word) + | "s10" => (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word) + | "s11" => (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word) + | "t3" => (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word) + | "t4" => (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word) + | "t5" => (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word) + | "t6" => (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word) + )))`; -(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val reg_name_forwards_matches : mword ty5 -> bool*) -(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +val _ = Define ` + ((reg_name_forwards_matches:(5)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) + then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word)))))) then + T + else F))`; -(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) -(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val reg_name_backwards_matches : string -> bool*) + +val _ = Define ` + ((reg_name_backwards_matches:string -> bool) arg_= + ((case arg_ of + "zero" => T + | "ra" => T + | "sp" => T + | "gp" => T + | "tp" => T + | "t0" => T + | "t1" => T + | "t2" => T + | "fp" => T + | "s1" => T + | "a0" => T + | "a1" => T + | "a2" => T + | "a3" => T + | "a4" => T + | "a5" => T + | "a6" => T + | "a7" => T + | "s2" => T + | "s3" => T + | "s4" => T + | "s5" => T + | "s6" => T + | "s7" => T + | "s8" => T + | "s9" => T + | "s10" => T + | "s11" => T + | "t3" => T + | "t4" => T + | "t5" => T + | "t6" => T + | _ => F + )))`; + + +(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*) + +val _ = Define ` + ((reg_name_matches_prefix:string ->((5)words$word#int)option) arg_= + (let stringappend_1814_0 = arg_ in + if (((((string_startswith stringappend_1814_0 "zero")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "zero")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "zero")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "ra")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "ra")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "ra")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "sp")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "sp")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "sp")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "gp")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "gp")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "gp")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "tp")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "tp")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "tp")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t0")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t0")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t0")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t1")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t1")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t2")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t2")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "fp")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "fp")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "fp")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s1")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s1")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a0")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a0")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a0")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a1")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a1")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a2")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a2")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a3")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a3")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a4")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a4")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a4")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a5")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a5")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a5")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a6")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a6")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a6")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "a7")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "a7")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "a7")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B0;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s2")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s2")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B0;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s3")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s3")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B0;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s4")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s4")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s4")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s5")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s5")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s5")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s6")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s6")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s6")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s7")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s7")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s7")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s8")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s8")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s8")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s9")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s9")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s9")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s10")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s10")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s10")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "s11")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "s11")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "s11")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t3")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t3")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t4")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t4")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t4")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B0;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t5")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t5")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t5")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B0] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1814_0 "t6")) /\ ( + (case ((string_drop stringappend_1814_0 ((string_length "t6")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1814_0 ((string_length "t6")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B1] : 5 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; -(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) -(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val sep_forwards : unit -> string*) val _ = Define ` - ((MEMr:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((sep_forwards:unit -> string) arg_= + ((case arg_ of + () => + string_append ((opt_spc_forwards () )) + ((string_append "," ((string_append ((def_spc_forwards () )) "")))) + )))`; + + +(*val sep_backwards : string -> unit*) + +val _ = Define ` + ((sep_backwards:string -> unit) arg_= + (let stringappend_1807_0 = arg_ in + (case + (case ((opt_spc_matches_prefix stringappend_1807_0)) of + SOME (stringappend_1808_0,stringappend_1809_0) => (stringappend_1808_0, stringappend_1809_0) + ) of + (() , stringappend_1809_0) => + let stringappend_1810_0 = (string_drop stringappend_1807_0 + stringappend_1809_0) in + let stringappend_1811_0 = (string_drop stringappend_1810_0 + ((string_length ","))) in + (case + (case ((opt_spc_matches_prefix stringappend_1811_0)) of + SOME (stringappend_1812_0,stringappend_1813_0) => (stringappend_1812_0, stringappend_1813_0) + ) of + (() , stringappend_1813_0) => + (case ((string_drop stringappend_1811_0 stringappend_1813_0)) of + "" => () + ) + ) + )))`; + + +(*val sep_forwards_matches : unit -> bool*) + +val _ = Define ` + ((sep_forwards_matches:unit -> bool) arg_= + ((case arg_ of () => T )))`; + + +(*val sep_backwards_matches : string -> bool*) + +val _ = Define ` + ((sep_backwards_matches:string -> bool) arg_= + (let stringappend_1800_0 = arg_ in + if ((case ((opt_spc_matches_prefix stringappend_1800_0)) of + SOME (stringappend_1801_0,stringappend_1802_0) => + let stringappend_1803_0 = (string_drop stringappend_1800_0 stringappend_1802_0) in + if (((((string_startswith stringappend_1803_0 ",")) /\ (let stringappend_1804_0 = (string_drop stringappend_1803_0 ((string_length ","))) in + if ((case ((opt_spc_matches_prefix stringappend_1804_0)) of + SOME (stringappend_1805_0,stringappend_1806_0) => + (case ((string_drop stringappend_1804_0 stringappend_1806_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then (case + (case ((opt_spc_matches_prefix stringappend_1800_0)) of + SOME (stringappend_1801_0,stringappend_1802_0) => + (stringappend_1801_0, stringappend_1802_0) + ) of + (() , stringappend_1802_0) => + let stringappend_1803_0 = (string_drop stringappend_1800_0 + stringappend_1802_0) in + let stringappend_1804_0 = (string_drop stringappend_1803_0 + ((string_length ","))) in + (case + (case ((opt_spc_matches_prefix stringappend_1804_0)) of + SOME (stringappend_1805_0,stringappend_1806_0) => + (stringappend_1805_0, stringappend_1806_0) + ) of + (() , stringappend_1806_0) => + (case ((string_drop stringappend_1804_0 stringappend_1806_0)) of "" => T ) + ) + ) + else F))`; + + +(*val sep_matches_prefix : string -> maybe ((unit * ii))*) + +val _ = Define ` + ((sep_matches_prefix:string ->(unit#int)option) arg_= + (let stringappend_1793_0 = arg_ in + if ((case ((opt_spc_matches_prefix stringappend_1793_0)) of + SOME (stringappend_1794_0,stringappend_1795_0) => + let stringappend_1796_0 = (string_drop stringappend_1793_0 stringappend_1795_0) in + if (((((string_startswith stringappend_1796_0 ",")) /\ (let stringappend_1797_0 = (string_drop stringappend_1796_0 ((string_length ","))) in + if ((case ((opt_spc_matches_prefix stringappend_1797_0)) of + SOME (stringappend_1798_0,stringappend_1799_0) => + (case ((string_drop stringappend_1797_0 stringappend_1799_0)) of s_ => T ) + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then (case + (case ((opt_spc_matches_prefix stringappend_1793_0)) of + SOME (stringappend_1794_0,stringappend_1795_0) => + (stringappend_1794_0, stringappend_1795_0) + ) of + (() , stringappend_1795_0) => + let stringappend_1796_0 = (string_drop stringappend_1793_0 + stringappend_1795_0) in + let stringappend_1797_0 = (string_drop stringappend_1796_0 + ((string_length ","))) in + (case + (case ((opt_spc_matches_prefix stringappend_1797_0)) of + SOME (stringappend_1798_0,stringappend_1799_0) => + (stringappend_1798_0, stringappend_1799_0) + ) of + (() , stringappend_1799_0) => + (case ((string_drop stringappend_1797_0 stringappend_1799_0)) of + s_ => SOME (() , ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + else NONE))`; +(*val bool_bits_forwards : bool -> mword ty1*) + val _ = Define ` - ((MEMr_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((bool_bits_forwards:bool ->(1)words$word) arg_= + ((case arg_ of + T => (vec_of_bits [B1] : 1 words$word) + | F => (vec_of_bits [B0] : 1 words$word) + )))`; +(*val bool_bits_backwards : mword ty1 -> bool*) + val _ = Define ` - ((MEMr_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((bool_bits_backwards:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else F))`; +(*val bool_bits_forwards_matches : bool -> bool*) + val _ = Define ` - ((MEMr_reserved:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((bool_bits_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; +(*val bool_bits_backwards_matches : mword ty1 -> bool*) + val _ = Define ` - ((MEMr_reserved_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((bool_bits_backwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; + +(*val bool_not_bits_forwards : bool -> mword ty1*) val _ = Define ` - ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width= - ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + ((bool_not_bits_forwards:bool ->(1)words$word) arg_= + ((case arg_ of + T => (vec_of_bits [B0] : 1 words$word) + | F => (vec_of_bits [B1] : 1 words$word) + )))`; -(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val bool_not_bits_backwards : mword ty1 -> bool*) val _ = Define ` - ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl res= - (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then - state_monad$returnS (MemException E_Load_Addr_Align) - else - (case (aq, rl, res) of - (F, F, F) => (MEMr addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - | (T, F, F) => (MEMr_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - | (F, F, T) => - (MEMr_reserved addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - | (T, F, T) => - (MEMr_reserved_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - | (F, T, F) => state_monad$throwS (Error_not_implemented "load.rl") - | (T, T, F) => - (MEMr_strong_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - | (F, T, T) => state_monad$throwS (Error_not_implemented "lr.rl") - | (T, T, T) => - (MEMr_reserved_strong_acquire addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) - )))`; + ((bool_not_bits_backwards:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; -(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) +(*val bool_not_bits_forwards_matches : bool -> bool*) val _ = Define ` - ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width aq rl con= - (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then - state_monad$returnS (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (F, F, F) => state_monad$seqS (MEMea addr width) (state_monad$returnS (MemValue () )) - | (F, T, F) => state_monad$seqS (MEMea_release addr width) (state_monad$returnS (MemValue () )) - | (F, F, T) => state_monad$seqS (MEMea_conditional addr width) (state_monad$returnS (MemValue () )) - | (F, T, T) => state_monad$seqS (MEMea_conditional_release addr width) (state_monad$returnS (MemValue () )) - | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq") - | (T, T, F) => state_monad$seqS (MEMea_strong_release addr width) (state_monad$returnS (MemValue () )) - | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq") - | (T, T, T) => state_monad$seqS (MEMea_conditional_strong_release addr width) (state_monad$returnS (MemValue () )) - )))`; + ((bool_not_bits_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; -(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val bool_not_bits_backwards_matches : mword ty1 -> bool*) val _ = Define ` - ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)= (state_monad$bindS - (RISCV_write addr width data) (\ (w__0 : bool) . - state_monad$returnS (if w__0 then MemValue () - else MemException E_SAMO_Access_Fault))))`; + ((bool_not_bits_backwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else F))`; -(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val size_bits_forwards : word_width -> mword ty2*) -(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +val _ = Define ` + ((size_bits_forwards:word_width ->(2)words$word) arg_= + ((case arg_ of + BYTE => (vec_of_bits [B0;B0] : 2 words$word) + | HALF => (vec_of_bits [B0;B1] : 2 words$word) + | WORD => (vec_of_bits [B1;B0] : 2 words$word) + | DOUBLE => (vec_of_bits [B1;B1] : 2 words$word) + )))`; -(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) -(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val size_bits_backwards : mword ty2 -> word_width*) + +val _ = Define ` + ((size_bits_backwards:(2)words$word -> word_width) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0] : 2 words$word)))) then BYTE + else if (((p0_ = (vec_of_bits [B0;B1] : 2 words$word)))) then HALF + else if (((p0_ = (vec_of_bits [B1;B0] : 2 words$word)))) then WORD + else DOUBLE))`; -(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) -(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val size_bits_forwards_matches : word_width -> bool*) val _ = Define ` - ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_bits_forwards_matches:word_width -> bool) arg_= + ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`; + +(*val size_bits_backwards_matches : mword ty2 -> bool*) val _ = Define ` - ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_bits_backwards_matches:(2)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0] : 2 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B1] : 2 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0] : 2 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1] : 2 words$word)))) then T + else F))`; + +(*val size_mnemonic_forwards : word_width -> string*) val _ = Define ` - ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_mnemonic_forwards:word_width -> string) arg_= + ((case arg_ of BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" )))`; + +(*val size_mnemonic_backwards : string -> word_width*) val _ = Define ` - ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_mnemonic_backwards:string -> word_width) arg_= + ((case arg_ of "b" => BYTE | "h" => HALF | "w" => WORD | "d" => DOUBLE )))`; +(*val size_mnemonic_forwards_matches : word_width -> bool*) + val _ = Define ` - ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_mnemonic_forwards_matches:word_width -> bool) arg_= + ((case arg_ of BYTE => T | HALF => T | WORD => T | DOUBLE => T )))`; + +(*val size_mnemonic_backwards_matches : string -> bool*) val _ = Define ` - ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + ((size_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of "b" => T | "h" => T | "w" => T | "d" => T | _ => F )))`; -(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) +(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*) val _ = Define ` - ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) addr width value aq rl con= - (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then - state_monad$returnS (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (F, F, F) => MEMval addr width value - | (F, T, F) => MEMval_release addr width value - | (F, F, T) => MEMval_conditional addr width value - | (F, T, T) => MEMval_conditional_release addr width value - | (T, F, F) => state_monad$throwS (Error_not_implemented "store.aq") - | (T, T, F) => MEMval_strong_release addr width value - | (T, F, T) => state_monad$throwS (Error_not_implemented "sc.aq") - | (T, T, T) => MEMval_conditional_strong_release addr width value - )))`; + ((size_mnemonic_matches_prefix:string ->(word_width#int)option) arg_= + (let stringappend_1789_0 = arg_ in + if (((((string_startswith stringappend_1789_0 "b")) /\ ( + (case ((string_drop stringappend_1789_0 ((string_length "b")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1789_0 ((string_length "b")))) of + s_ => SOME (BYTE, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1789_0 "h")) /\ ( + (case ((string_drop stringappend_1789_0 ((string_length "h")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1789_0 ((string_length "h")))) of + s_ => SOME (HALF, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1789_0 "w")) /\ ( + (case ((string_drop stringappend_1789_0 ((string_length "w")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1789_0 ((string_length "w")))) of + s_ => SOME (WORD, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1789_0 "d")) /\ ( + (case ((string_drop stringappend_1789_0 ((string_length "d")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1789_0 ((string_length "d")))) of + s_ => SOME (DOUBLE, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; -(*val _get_Misa : Misa -> mword ty64*) +(*val Mk_Misa : mword ty64 -> Misa*) val _ = Define ` - ((get_Misa:Misa ->(64)words$word) (Mk_Misa (v))= v)`; + ((Mk_Misa:(64)words$word -> Misa) v= (<| Misa_Misa_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*) +(*val _get_Misa_bits : Misa -> mword ty64*) val _ = Define ` - ((set_Misa:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Misa v) in - state_monad$write_regS r_ref r)))`; + ((get_Misa_bits:Misa ->(64)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _get_SV39_PTE : SV39_PTE -> mword ty64*) +(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Misa_bits:((regstate),(register_value),(Misa))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; -(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) + +(*val _update_Misa_bits : Misa -> mword ty64 -> Misa*) + +val _ = Define ` + ((update_Misa_bits:Misa ->(64)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*) + +(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*) + +(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) (*val _get_Misa_MXL : Misa -> mword ty2*) val _ = Define ` - ((get_Misa_MXL:Misa ->(2)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; + ((get_Misa_MXL:Misa ->(2)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii) : 2 words$word)))`; (*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*) val _ = Define ` - ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 62 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_MXL:((regstate),(register_value),(Misa))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*) val _ = Define ` - ((update_Misa_MXL:Misa ->(2)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):ii) (( 62 : int):ii) x : 64 words$word))))`; + ((update_Misa_MXL:Misa ->(2)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 63 : int):ii) (( 62 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_Z : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_Z:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)))`; + ((get_Misa_Z:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)))`; (*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 25 : int):ii) (( 25 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_Z:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_Z : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_Z:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):ii) (( 25 : int):ii) x : 64 words$word))))`; + ((update_Misa_Z:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 25 : int):ii) (( 25 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_Y : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_Y:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii) : 1 words$word)))`; + ((get_Misa_Y:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii) : 1 words$word)))`; (*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 24 : int):ii) (( 24 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_Y:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_Y : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_Y:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):ii) (( 24 : int):ii) x : 64 words$word))))`; + ((update_Misa_Y:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 24 : int):ii) (( 24 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_X : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_X:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; + ((get_Misa_X:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii) : 1 words$word)))`; (*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 23 : int):ii) (( 23 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_X:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_X : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_X:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):ii) (( 23 : int):ii) x : 64 words$word))))`; + ((update_Misa_X:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 23 : int):ii) (( 23 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1190,24 +2077,32 @@ val _ = Define ` (*val _get_Misa_W : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_W:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + ((get_Misa_W:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; (*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_W:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_W : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_W:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 64 words$word))))`; + ((update_Misa_W:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1219,24 +2114,32 @@ val _ = Define ` (*val _get_Misa_V : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_V:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; + ((get_Misa_V:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; (*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_V:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_V : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_V:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x : 64 words$word))))`; + ((update_Misa_V:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 21 : int):ii) (( 21 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1248,24 +2151,32 @@ val _ = Define ` (*val _get_Misa_U : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_U:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; + ((get_Misa_U:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; (*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_U:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_U : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_U:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x : 64 words$word))))`; + ((update_Misa_U:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 20 : int):ii) (( 20 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1277,70 +2188,94 @@ val _ = Define ` (*val _get_Misa_T : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_T:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + ((get_Misa_T:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; (*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_T:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_T : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_T:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + ((update_Misa_T:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_S : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_S:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + ((get_Misa_S:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; (*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_S:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_S : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_S:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + ((update_Misa_S:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_R : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_R:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; + ((get_Misa_R:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; (*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_R:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_R : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_R:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x : 64 words$word))))`; + ((update_Misa_R:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 17 : int):ii) (( 17 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1352,254 +2287,342 @@ val _ = Define ` (*val _get_Misa_Q : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_Q:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii) : 1 words$word)))`; + ((get_Misa_Q:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii) : 1 words$word)))`; (*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 16 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_Q:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_Q : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_Q:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):ii) (( 16 : int):ii) x : 64 words$word))))`; + ((update_Misa_Q:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 16 : int):ii) (( 16 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_P : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_P:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; + ((get_Misa_P:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; (*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_P:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_P : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_P:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + ((update_Misa_P:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 15 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_O : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_O:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)))`; + ((get_Misa_O:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)))`; (*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 14 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_O:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_O : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_O:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):ii) (( 14 : int):ii) x : 64 words$word))))`; + ((update_Misa_O:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 14 : int):ii) (( 14 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_N : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_N:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; + ((get_Misa_N:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; (*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_N:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_N : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_N:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + ((update_Misa_N:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 13 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_M : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_M:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; + ((get_Misa_M:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; (*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_M:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_M : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_M:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x : 64 words$word))))`; + ((update_Misa_M:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 12 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_L : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_L:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; + ((get_Misa_L:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; (*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_L:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_L : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_L:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + ((update_Misa_L:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 11 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_K : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_K:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; + ((get_Misa_K:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; (*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_K:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_K : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_K:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + ((update_Misa_K:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 10 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_J : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_J:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + ((get_Misa_J:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; (*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_J:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_J : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_J:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + ((update_Misa_J:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_I : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_I:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((get_Misa_I:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; (*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_I:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_I : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_I:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((update_Misa_I:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_H : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_H:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((get_Misa_H:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; (*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_H:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_H : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_H:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + ((update_Misa_H:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_G : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_G:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + ((get_Misa_G:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; (*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_G:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_G : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_G:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + ((update_Misa_G:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1611,70 +2634,94 @@ val _ = Define ` (*val _get_Misa_F : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_F:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((get_Misa_F:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; (*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_F:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_F : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_F:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((update_Misa_F:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_E : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_E:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((get_Misa_E:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; (*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_E:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_E : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_E:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_Misa_E:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_D : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_D:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((get_Misa_D:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; (*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_D:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_D : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_D:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((update_Misa_D:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1686,70 +2733,94 @@ val _ = Define ` (*val _get_Misa_C : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_C:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((get_Misa_C:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; (*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_C:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_C : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_C:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + ((update_Misa_C:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_B : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_B:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_Misa_B:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_B:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_B : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_B:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((update_Misa_B:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Misa_A : Misa -> mword ty1*) val _ = Define ` - ((get_Misa_A:Misa ->(1)words$word) (Mk_Misa (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_Misa_A:Misa ->(1)words$word) v= ((subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*) val _ = Define ` - ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Misa) . - let r = ((get_Misa w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Misa r))))`; + ((set_Misa_A:((regstate),(register_value),(Misa))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec r.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Misa_A : Misa -> mword ty1 -> Misa*) val _ = Define ` - ((update_Misa_A:Misa ->(1)words$word -> Misa) (Mk_Misa (v)) x= - (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Misa_A:Misa ->(1)words$word -> Misa) v x= + ((v with<| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec v.Misa_Misa_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1758,48 +2829,85 @@ val _ = Define ` (*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) -(*val legalize_misa : Misa -> mword ty64 -> Misa*) +(*val legalize_misa : Misa -> mword ty64 -> M Misa*) val _ = Define ` - ((legalize_misa:Misa ->(64)words$word -> Misa) (m : Misa) (v : xlenbits)= m)`; + ((legalize_misa:Misa ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((Misa),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (m : Misa) (v : xlenbits)= + (let v = (Mk_Misa v) in sail2_state_monad$bindS + (sail2_state$and_boolS (sail2_state_monad$returnS (((((get_Misa_C v : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 1 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) (\ (w__1 : bool) . + sail2_state_monad$returnS (if w__1 then m + else update_Misa_C m ((get_Misa_C v : 1 words$word))))))`; -(*val _get_Mstatus : Mstatus -> mword ty64*) +(*val Mk_Mstatus : mword ty64 -> Mstatus*) val _ = Define ` - ((get_Mstatus:Mstatus ->(64)words$word) (Mk_Mstatus (v))= v)`; + ((Mk_Mstatus:(64)words$word -> Mstatus) v= + (<| Mstatus_Mstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) +(*val _get_Mstatus_bits : Mstatus -> mword ty64*) val _ = Define ` - ((set_Mstatus:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Mstatus v) in - state_monad$write_regS r_ref r)))`; + ((get_Mstatus_bits:Mstatus ->(64)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Mstatus_bits:((regstate),(register_value),(Mstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus*) + +val _ = Define ` + ((update_Mstatus_bits:Mstatus ->(64)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_SD : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_SD:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + ((get_Mstatus_SD:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SD:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SD:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*) @@ -1811,47 +2919,63 @@ val _ = Define ` (*val _get_Mstatus_SXL : Mstatus -> mword ty2*) val _ = Define ` - ((get_Mstatus_SXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii) : 2 words$word)))`; + ((get_Mstatus_SXL:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii) : 2 words$word)))`; (*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mstatus_SXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 35 : int):ii) (( 34 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):ii) (( 34 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SXL:Mstatus ->(2)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 35 : int):ii) (( 34 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_UXL : Mstatus -> mword ty2*) val _ = Define ` - ((get_Mstatus_UXL:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; + ((get_Mstatus_UXL:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; (*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mstatus_UXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_UXL:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*) val _ = Define ` - ((update_Mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_UXL:Mstatus ->(2)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*) @@ -1863,93 +2987,125 @@ val _ = Define ` (*val _get_Mstatus_TSR : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_TSR:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; + ((get_Mstatus_TSR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 22 : int):ii) (( 22 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_TSR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):ii) (( 22 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_TSR:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 22 : int):ii) (( 22 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_TW : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_TW:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; + ((get_Mstatus_TW:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 21 : int):ii) (( 21 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_TW:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):ii) (( 21 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_TW:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 21 : int):ii) (( 21 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_TVM : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_TVM:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; + ((get_Mstatus_TVM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 20 : int):ii) (( 20 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_TVM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):ii) (( 20 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_TVM:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 20 : int):ii) (( 20 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_MXR : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_MXR:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + ((get_Mstatus_MXR:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_MXR:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_MXR:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*) @@ -1961,24 +3117,32 @@ val _ = Define ` (*val _get_Mstatus_SUM : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_SUM:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + ((get_Mstatus_SUM:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SUM:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SUM:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*) @@ -1990,47 +3154,63 @@ val _ = Define ` (*val _get_Mstatus_MPRV : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_MPRV:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; + ((get_Mstatus_MPRV:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 17 : int):ii) (( 17 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_MPRV:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):ii) (( 17 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_MPRV:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 17 : int):ii) (( 17 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_XS : Mstatus -> mword ty2*) val _ = Define ` - ((get_Mstatus_XS:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; + ((get_Mstatus_XS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; (*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_XS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*) val _ = Define ` - ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_XS:Mstatus ->(2)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*) @@ -2042,24 +3222,32 @@ val _ = Define ` (*val _get_Mstatus_FS : Mstatus -> mword ty2*) val _ = Define ` - ((get_Mstatus_FS:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; + ((get_Mstatus_FS:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; (*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_FS:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*) val _ = Define ` - ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_FS:Mstatus ->(2)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*) @@ -2071,47 +3259,63 @@ val _ = Define ` (*val _get_Mstatus_MPP : Mstatus -> mword ty2*) val _ = Define ` - ((get_Mstatus_MPP:Mstatus ->(2)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)))`; + ((get_Mstatus_MPP:Mstatus ->(2)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)))`; (*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 11 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_MPP:((regstate),(register_value),(Mstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*) val _ = Define ` - ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_MPP:Mstatus ->(2)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 12 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_SPP : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_SPP:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((get_Mstatus_SPP:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SPP:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SPP:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*) @@ -2123,47 +3327,63 @@ val _ = Define ` (*val _get_Mstatus_MPIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_MPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((get_Mstatus_MPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_MPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_MPIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_SPIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_SPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((get_Mstatus_SPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SPIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2175,24 +3395,32 @@ val _ = Define ` (*val _get_Mstatus_UPIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_UPIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((get_Mstatus_UPIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_UPIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_UPIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2204,47 +3432,63 @@ val _ = Define ` (*val _get_Mstatus_MIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_MIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((get_Mstatus_MIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_MIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_MIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mstatus_SIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_SIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_Mstatus_SIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_SIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_SIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2256,24 +3500,32 @@ val _ = Define ` (*val _get_Mstatus_UIE : Mstatus -> mword ty1*) val _ = Define ` - ((get_Mstatus_UIE:Mstatus ->(1)words$word) (Mk_Mstatus (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_Mstatus_UIE:Mstatus ->(1)words$word) v= ((subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mstatus) . - let r = ((get_Mstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mstatus r))))`; + ((set_Mstatus_UIE:((regstate),(register_value),(Mstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec r.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*) val _ = Define ` - ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) (Mk_Mstatus (v)) x= - (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Mstatus_UIE:Mstatus ->(1)words$word -> Mstatus) v x= + ((v with<| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec v.Mstatus_Mstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2304,18 +3556,18 @@ val _ = Define ` (*val cur_Architecture : unit -> M Architecture*) val _ = Define ` - ((cur_Architecture:unit ->(regstate)state_monad$sequential_state ->(((Architecture),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS + ((cur_Architecture:unit ->(regstate)sail2_state_monad$sequential_state ->(((Architecture),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS (case w__0 of - Machine => state_monad$bindS - (state_monad$read_regS misa_ref) (\ (w__1 : Misa) . state_monad$returnS ((get_Misa_MXL w__1 : 2 words$word))) - | Supervisor => state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . state_monad$returnS ((get_Mstatus_SXL w__2 : 2 words$word))) - | User => state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . state_monad$returnS ((get_Mstatus_UXL w__3 : 2 words$word))) + Machine => sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . sail2_state_monad$returnS ((get_Misa_MXL w__1 : 2 words$word))) + | Supervisor => sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . sail2_state_monad$returnS ((get_Mstatus_SXL w__2 : 2 words$word))) + | User => sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . sail2_state_monad$returnS ((get_Mstatus_UXL w__3 : 2 words$word))) ) (\ (a : arch_xlen) . (case ((architecture a)) of - SOME (a) => state_monad$returnS a + SOME (a) => sail2_state_monad$returnS a | NONE => internal_error "Invalid current architecture" )))))`; @@ -2323,103 +3575,160 @@ val _ = Define ` (*val in32BitMode : unit -> M bool*) val _ = Define ` - ((in32BitMode:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) . state_monad$returnS (((w__0 = RV32))))))`; + ((in32BitMode:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (cur_Architecture () ) (\ (w__0 : Architecture) . sail2_state_monad$returnS (((w__0 = RV32))))))`; (*val haveAtomics : unit -> M bool*) val _ = Define ` - ((haveAtomics:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . - state_monad$returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + ((haveAtomics:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + sail2_state_monad$returnS (((((get_Misa_A w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; (*val haveRVC : unit -> M bool*) val _ = Define ` - ((haveRVC:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . - state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + ((haveRVC:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + sail2_state_monad$returnS (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; (*val haveMulDiv : unit -> M bool*) val _ = Define ` - ((haveMulDiv:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS misa_ref) (\ (w__0 : Misa) . - state_monad$returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; + ((haveMulDiv:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + sail2_state_monad$returnS (((((get_Misa_M w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))`; (*val haveFP : unit -> M bool*) val _ = Define ` - ((haveFP:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = - (state$or_boolS - ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__0 : Misa) . - state_monad$returnS (((((get_Misa_F w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) - ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__1 : Misa) . - state_monad$returnS (((((get_Misa_D w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))))`; + ((haveFP:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + sail2_state_monad$returnS (((((get_Misa_F w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__1 : Misa) . + sail2_state_monad$returnS (((((get_Misa_D w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))))`; -(*val _get_Minterrupts : Minterrupts -> mword ty64*) +(*val pc_alignment_mask : unit -> M (mword ty64)*) val _ = Define ` - ((get_Minterrupts:Minterrupts ->(64)words$word) (Mk_Minterrupts (v))= v)`; + ((pc_alignment_mask:unit ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__0 : Misa) . + sail2_state_monad$returnS ((not_vec + ((EXTZ (( 64 : int):ii) + (if (((((get_Misa_C w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + (vec_of_bits [B0;B0] : 2 words$word) + else (vec_of_bits [B1;B0] : 2 words$word)) + : 64 words$word)) + : 64 words$word)))))`; + + +(*val Mk_Minterrupts : mword ty64 -> Minterrupts*) + +val _ = Define ` + ((Mk_Minterrupts:(64)words$word -> Minterrupts) v= + (<| Minterrupts_Minterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_Minterrupts_bits : Minterrupts -> mword ty64*) + +val _ = Define ` + ((get_Minterrupts_bits:Minterrupts ->(64)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Minterrupts_bits:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; -(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) +(*val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts*) val _ = Define ` - ((set_Minterrupts:((regstate),(register_value),(Minterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Minterrupts v) in - state_monad$write_regS r_ref r)))`; + ((update_Minterrupts_bits:Minterrupts ->(64)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_MEI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 11 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_MEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):ii) (( 11 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_MEI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 11 : int):ii) (( 11 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_SEI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_SEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_SEI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2431,24 +3740,33 @@ val _ = Define ` (*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_UEI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_UEI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_UEI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2460,47 +3778,65 @@ val _ = Define ` (*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_MTI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_MTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_MTI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Minterrupts_STI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_STI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_STI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_STI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_STI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2512,24 +3848,33 @@ val _ = Define ` (*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_UTI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_UTI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_UTI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2541,47 +3886,65 @@ val _ = Define ` (*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_MSI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_MSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_MSI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_SSI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_SSI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_SSI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2593,24 +3956,33 @@ val _ = Define ` (*val _get_Minterrupts_USI : Minterrupts -> mword ty1*) val _ = Define ` - ((get_Minterrupts_USI:Minterrupts ->(1)words$word) (Mk_Minterrupts (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_Minterrupts_USI:Minterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) val _ = Define ` - ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Minterrupts) . - let r = ((get_Minterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Minterrupts r))))`; + ((set_Minterrupts_USI:((regstate),(register_value),(Minterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec r.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*) val _ = Define ` - ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) (Mk_Minterrupts (v)) x= - (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Minterrupts_USI:Minterrupts ->(1)words$word -> Minterrupts) v x= + ((v with<| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec v.Minterrupts_Minterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2652,160 +4024,234 @@ val _ = Define ` update_Minterrupts_MSI m ((bool_to_bits F : 1 words$word))))`; -(*val _get_Medeleg : Medeleg -> mword ty64*) +(*val Mk_Medeleg : mword ty64 -> Medeleg*) val _ = Define ` - ((get_Medeleg:Medeleg ->(64)words$word) (Mk_Medeleg (v))= v)`; + ((Mk_Medeleg:(64)words$word -> Medeleg) v= + (<| Medeleg_Medeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) +(*val _get_Medeleg_bits : Medeleg -> mword ty64*) val _ = Define ` - ((set_Medeleg:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Medeleg v) in - state_monad$write_regS r_ref r)))`; + ((get_Medeleg_bits:Medeleg ->(64)words$word) v= ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Medeleg_bits:((regstate),(register_value),(Medeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg*) + +val _ = Define ` + ((update_Medeleg_bits:Medeleg ->(64)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; + ((get_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 15 : int):ii) (( 15 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_SAMO_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_SAMO_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 15 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 13 : int):ii) (( 13 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Load_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Load_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 13 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 12 : int):ii) (( 12 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Fetch_Page_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):ii) (( 12 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Fetch_Page_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 12 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; + ((get_Medeleg_MEnvCall:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 10 : int):ii) (( 10 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_MEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_MEnvCall:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 10 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + ((get_Medeleg_SEnvCall:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_SEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_SEnvCall:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((get_Medeleg_UEnvCall:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_UEnvCall:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_UEnvCall:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2817,25 +4263,33 @@ val _ = Define ` (*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((get_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_SAMO_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_SAMO_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2847,24 +4301,33 @@ val _ = Define ` (*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + ((get_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_SAMO_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_SAMO_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2876,25 +4339,33 @@ val _ = Define ` (*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Load_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Load_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2906,24 +4377,33 @@ val _ = Define ` (*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Load_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Load_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2935,24 +4415,33 @@ val _ = Define ` (*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Breakpoint:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Breakpoint:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Breakpoint:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2964,24 +4453,33 @@ val _ = Define ` (*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Illegal_Instr:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Illegal_Instr:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Illegal_Instr:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2993,25 +4491,33 @@ val _ = Define ` (*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) (Mk_Medeleg (v))= - ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Fetch_Access_Fault:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Fetch_Access_Fault:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -3023,24 +4529,33 @@ val _ = Define ` (*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*) val _ = Define ` - ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) (Mk_Medeleg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((get_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word) v= + ((subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; (*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) val _ = Define ` - ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Medeleg) . - let r = ((get_Medeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Medeleg r))))`; + ((set_Medeleg_Fetch_Addr_Align:((regstate),(register_value),(Medeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec r.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) val _ = Define ` - ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) (Mk_Medeleg (v)) x= - (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Medeleg_Fetch_Addr_Align:Medeleg ->(1)words$word -> Medeleg) v x= + ((v with<| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec v.Medeleg_Medeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -3057,65 +4572,103 @@ val _ = Define ` update_Medeleg_MEnvCall m ((bool_to_bits F : 1 words$word))))`; -(*val _get_Mtvec : Mtvec -> mword ty64*) +(*val Mk_Mtvec : mword ty64 -> Mtvec*) + +val _ = Define ` + ((Mk_Mtvec:(64)words$word -> Mtvec) v= (<| Mtvec_Mtvec_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_Mtvec_bits : Mtvec -> mword ty64*) val _ = Define ` - ((get_Mtvec:Mtvec ->(64)words$word) (Mk_Mtvec (v))= v)`; + ((get_Mtvec_bits:Mtvec ->(64)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) +(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) val _ = Define ` - ((set_Mtvec:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Mtvec v) in - state_monad$write_regS r_ref r)))`; + ((set_Mtvec_bits:((regstate),(register_value),(Mtvec))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec*) + +val _ = Define ` + ((update_Mtvec_bits:Mtvec ->(64)words$word -> Mtvec) v x= + ((v with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_Mtvec_Base : Mtvec -> mword ty62*) val _ = Define ` - ((get_Mtvec_Base:Mtvec ->(62)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)))`; + ((get_Mtvec_Base:Mtvec ->(62)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii) : 62 words$word)))`; (*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*) val _ = Define ` - ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . - let r = ((get_Mtvec w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 2 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mtvec r))))`; + ((set_Mtvec_Base:((regstate),(register_value),(Mtvec))register_ref ->(62)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 61 : int):ii) (( 0 : int):ii) : 62 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*) val _ = Define ` - ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) (Mk_Mtvec (v)) x= - (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + ((update_Mtvec_Base:Mtvec ->(62)words$word -> Mtvec) v x= + ((v with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 63 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 61 : int):ii) (( 0 : int):ii) : 62 words$word)) + : 64 words$word))|>)))`; (*val _get_Mtvec_Mode : Mtvec -> mword ty2*) val _ = Define ` - ((get_Mtvec_Mode:Mtvec ->(2)words$word) (Mk_Mtvec (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)))`; + ((get_Mtvec_Mode:Mtvec ->(2)words$word) v= ((subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)))`; (*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*) val _ = Define ` - ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mtvec) . - let r = ((get_Mtvec w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mtvec r))))`; + ((set_Mtvec_Mode:((regstate),(register_value),(Mtvec))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec r.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*) val _ = Define ` - ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) (Mk_Mtvec (v)) x= - (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Mtvec_Mode:Mtvec ->(2)words$word -> Mtvec) v x= + ((v with<| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec v.Mtvec_Mtvec_chunk_0 (( 1 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*) @@ -3136,65 +4689,104 @@ val _ = Define ` )))`; -(*val _get_Mcause : Mcause -> mword ty64*) +(*val Mk_Mcause : mword ty64 -> Mcause*) + +val _ = Define ` + ((Mk_Mcause:(64)words$word -> Mcause) v= (<| Mcause_Mcause_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_Mcause_bits : Mcause -> mword ty64*) val _ = Define ` - ((get_Mcause:Mcause ->(64)words$word) (Mk_Mcause (v))= v)`; + ((get_Mcause_bits:Mcause ->(64)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) +(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) val _ = Define ` - ((set_Mcause:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Mcause v) in - state_monad$write_regS r_ref r)))`; + ((set_Mcause_bits:((regstate),(register_value),(Mcause))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause*) + +val _ = Define ` + ((update_Mcause_bits:Mcause ->(64)words$word -> Mcause) v x= + ((v with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; (*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*) val _ = Define ` - ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + ((get_Mcause_IsInterrupt:Mcause ->(1)words$word) v= + ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; (*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*) val _ = Define ` - ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . - let r = ((get_Mcause w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mcause r))))`; + ((set_Mcause_IsInterrupt:((regstate),(register_value),(Mcause))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*) val _ = Define ` - ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) (Mk_Mcause (v)) x= - (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + ((update_Mcause_IsInterrupt:Mcause ->(1)words$word -> Mcause) v x= + ((v with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val _get_Mcause_Cause : Mcause -> mword ty63*) val _ = Define ` - ((get_Mcause_Cause:Mcause ->(63)words$word) (Mk_Mcause (v))= ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)))`; + ((get_Mcause_Cause:Mcause ->(63)words$word) v= ((subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)))`; (*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*) val _ = Define ` - ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Mcause) . - let r = ((get_Mcause w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 62 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Mcause r))))`; + ((set_Mcause_Cause:((regstate),(register_value),(Mcause))register_ref ->(63)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec r.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*) val _ = Define ` - ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) (Mk_Mcause (v)) x= - (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Mcause_Cause:Mcause ->(63)words$word -> Mcause) v x= + ((v with<| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec v.Mcause_Mcause_chunk_0 (( 62 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 62 : int):ii) (( 0 : int):ii) : 63 words$word)) + : 64 words$word))|>)))`; (*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*) @@ -3223,9 +4815,9 @@ val _ = Define ` (*val legalize_xepc : mword ty64 -> M (mword ty64)*) val _ = Define ` - ((legalize_xepc:(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) v= (state_monad$bindS + ((legalize_xepc:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) v= (sail2_state_monad$bindS (haveRVC () ) (\ (w__0 : bool) . - state_monad$returnS ((and_vec v + sail2_state_monad$returnS ((and_vec v ((EXTS (( 64 : int):ii) (if w__0 then (vec_of_bits [B1;B1;B0] : 3 words$word) else (vec_of_bits [B1;B0;B0] : 3 words$word)) @@ -3233,206 +4825,514 @@ val _ = Define ` : 64 words$word)))))`; -(*val _get_Sstatus : Sstatus -> mword ty64*) +(*val Mk_Counteren : mword ty32 -> Counteren*) + +val _ = Define ` + ((Mk_Counteren:(32)words$word -> Counteren) v= + (<| Counteren_Counteren_chunk_0 := ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) |>))`; + + +(*val _get_Counteren_bits : Counteren -> mword ty32*) + +val _ = Define ` + ((get_Counteren_bits:Counteren ->(32)words$word) v= + ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)))`; + + +(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*) + +val _ = Define ` + ((set_Counteren_bits:((regstate),(register_value),(Counteren))register_ref ->(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*) + +val _ = Define ` + ((update_Counteren_bits:Counteren ->(32)words$word -> Counteren) v x= + ((v with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_Counteren_HPM : Counteren -> mword ty29*) + +val _ = Define ` + ((get_Counteren_HPM:Counteren ->(29)words$word) v= + ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii) : 29 words$word)))`; + + +(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*) + +val _ = Define ` + ((set_Counteren_HPM:((regstate),(register_value),(Counteren))register_ref ->(29)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*) + +val _ = Define ` + ((update_Counteren_HPM:Counteren ->(29)words$word -> Counteren) v x= + ((v with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 31 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 28 : int):ii) (( 0 : int):ii) : 29 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_Counteren_IR : Counteren -> mword ty1*) + +val _ = Define ` + ((get_Counteren_IR:Counteren ->(1)words$word) v= + ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + + +(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Counteren_IR:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*) + +val _ = Define ` + ((update_Counteren_IR:Counteren ->(1)words$word -> Counteren) v x= + ((v with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_Counteren_TM : Counteren -> mword ty1*) + +val _ = Define ` + ((get_Counteren_TM:Counteren ->(1)words$word) v= + ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) + +val _ = Define ` + ((set_Counteren_TM:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*) + +val _ = Define ` + ((update_Counteren_TM:Counteren ->(1)words$word -> Counteren) v x= + ((v with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; + + +(*val _get_Counteren_CY : Counteren -> mword ty1*) val _ = Define ` - ((get_Sstatus:Sstatus ->(64)words$word) (Mk_Sstatus (v))= v)`; + ((get_Counteren_CY:Counteren ->(1)words$word) v= + ((subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; -(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) +(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) val _ = Define ` - ((set_Sstatus:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Sstatus v) in - state_monad$write_regS r_ref r)))`; + ((set_Counteren_CY:((regstate),(register_value),(Counteren))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec r.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*) val _ = Define ` - ((get_Sstatus_SD:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; + ((update_Counteren_CY:Counteren ->(1)words$word -> Counteren) v x= + ((v with<| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec v.Counteren_Counteren_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 32 words$word))|>)))`; +(*val legalize_mcounteren : Counteren -> mword ty64 -> Counteren*) + val _ = Define ` - ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 63 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((legalize_mcounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)= + (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in + let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in + update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`; + +(*val legalize_scounteren : Counteren -> mword ty64 -> Counteren*) val _ = Define ` - ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):ii) (( 63 : int):ii) x : 64 words$word))))`; + ((legalize_scounteren:Counteren ->(64)words$word -> Counteren) (c : Counteren) (v : xlenbits)= + (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 : int):ii))) : 1 words$word))) in + let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 : int):ii))) : 1 words$word))) in + update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 : int):ii))) : 1 words$word))))`; + +(*val retire_instruction : unit -> M unit*) val _ = Define ` - ((get_Sstatus_UXL:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; + ((retire_instruction:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS minstret_written_ref) (\ (w__0 : bool) . + if (((((bool_to_bits w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then + sail2_state_monad$write_regS minstret_written_ref F + else sail2_state_monad$bindS + (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + sail2_state_monad$write_regS minstret_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))))))`; + + +(*val Mk_Sstatus : mword ty64 -> Sstatus*) + +val _ = Define ` + ((Mk_Sstatus:(64)words$word -> Sstatus) v= + (<| Sstatus_Sstatus_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_Sstatus_bits : Sstatus -> mword ty64*) + +val _ = Define ` + ((get_Sstatus_bits:Sstatus ->(64)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Sstatus_bits:((regstate),(register_value),(Sstatus))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus*) val _ = Define ` - ((set_Sstatus_UXL:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 33 : int):ii) (( 32 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_bits:Sstatus ->(64)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):ii) (( 32 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_SD:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_MXR:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; + ((set_Sstatus_SD:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 19 : int):ii) (( 19 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_SD:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 63 : int):ii) (( 63 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):ii) (( 19 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_UXL:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) : 2 words$word)))`; val _ = Define ` - ((get_Sstatus_SUM:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; + ((set_Sstatus_UXL:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 18 : int):ii) (( 18 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_UXL:Sstatus ->(2)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 33 : int):ii) (( 32 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):ii) (( 18 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_MXR:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_XS:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; + ((set_Sstatus_MXR:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 16 : int):ii) (( 15 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_MXR:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 19 : int):ii) (( 19 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):ii) (( 15 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_SUM:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_FS:Sstatus ->(2)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; + ((set_Sstatus_SUM:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 14 : int):ii) (( 13 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_SUM:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 18 : int):ii) (( 18 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):ii) (( 13 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_XS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) : 2 words$word)))`; val _ = Define ` - ((get_Sstatus_SPP:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((set_Sstatus_XS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_XS:Sstatus ->(2)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 16 : int):ii) (( 15 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_FS:Sstatus ->(2)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)))`; val _ = Define ` - ((get_Sstatus_SPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((set_Sstatus_FS:((regstate),(register_value),(Sstatus))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_FS:Sstatus ->(2)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 14 : int):ii) (( 13 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_SPP:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_UPIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((set_Sstatus_SPP:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_SPP:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_SPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_SIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((set_Sstatus_SPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_SPIE:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_UPIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; val _ = Define ` - ((get_Sstatus_UIE:Sstatus ->(1)words$word) (Mk_Sstatus (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((set_Sstatus_UPIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sstatus) . - let r = ((get_Sstatus w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sstatus r))))`; + ((update_Sstatus_UPIE:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) (Mk_Sstatus (v)) x= - (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((get_Sstatus_SIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_SIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_Sstatus_SIE:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; + + +val _ = Define ` + ((get_Sstatus_UIE:Sstatus ->(1)words$word) v= ((subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + + +val _ = Define ` + ((set_Sstatus_UIE:((regstate),(register_value),(Sstatus))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec r.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_Sstatus_UIE:Sstatus ->(1)words$word -> Sstatus) v x= + ((v with<| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec v.Sstatus_Sstatus_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val lower_mstatus : Mstatus -> Sstatus*) @@ -3458,7 +5358,6 @@ val _ = Define ` val _ = Define ` ((lift_sstatus:Mstatus -> Sstatus -> Mstatus) (m : Mstatus) (s : Sstatus)= (let m = (update_Mstatus_SD m ((get_Sstatus_SD s : 1 words$word))) in - let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s : 2 words$word))) in let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s : 1 words$word))) in let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s : 1 words$word))) in let m = (update_Mstatus_XS m ((get_Sstatus_XS s : 2 words$word))) in @@ -3473,178 +5372,279 @@ val _ = Define ` (*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*) val _ = Define ` - ((legalize_sstatus:Mstatus ->(64)words$word -> Mstatus) (m : Mstatus) (v : xlenbits)= (lift_sstatus m (Mk_Sstatus v)))`; + ((legalize_sstatus:Mstatus ->(64)words$word -> Mstatus) (m : Mstatus) (v : xlenbits)= (lift_sstatus m ((Mk_Sstatus v))))`; -(*val _get_Sedeleg : Sedeleg -> mword ty64*) +(*val Mk_Sedeleg : mword ty64 -> Sedeleg*) val _ = Define ` - ((get_Sedeleg:Sedeleg ->(64)words$word) (Mk_Sedeleg (v))= v)`; + ((Mk_Sedeleg:(64)words$word -> Sedeleg) v= + (<| Sedeleg_Sedeleg_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) +(*val _get_Sedeleg_bits : Sedeleg -> mword ty64*) val _ = Define ` - ((set_Sedeleg:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Sedeleg v) in - state_monad$write_regS r_ref r)))`; + ((get_Sedeleg_bits:Sedeleg ->(64)words$word) v= ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_Sedeleg_bits:((regstate),(register_value),(Sedeleg))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg*) val _ = Define ` - ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_bits:Sedeleg ->(64)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_UEnvCall:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_UEnvCall:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_UEnvCall:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_SAMO_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_SAMO_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_SAMO_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_SAMO_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Load_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_Load_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Load_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_Load_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Breakpoint:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Breakpoint:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_Breakpoint:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Illegal_Instr:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= - ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_Illegal_Instr:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Fetch_Access_Fault:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) (Mk_Sedeleg (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((update_Sedeleg_Fetch_Access_Fault:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sedeleg) . - let r = ((get_Sedeleg w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sedeleg r))))`; + ((get_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word) v= + ((subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) (Mk_Sedeleg (v)) x= - (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((set_Sedeleg_Fetch_Addr_Align:((regstate),(register_value),(Sedeleg))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec r.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_Sedeleg_Fetch_Addr_Align:Sedeleg ->(1)words$word -> Sedeleg) v x= + ((v with<| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec v.Sedeleg_Sedeleg_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*) @@ -3654,121 +5654,199 @@ val _ = Define ` (Mk_Sedeleg ((EXTZ (( 64 : int):ii) ((subrange_vec_dec v (( 8 : int):ii) (( 0 : int):ii) : 9 words$word)) : 64 words$word))))`; -(*val _get_Sinterrupts : Sinterrupts -> mword ty64*) +(*val Mk_Sinterrupts : mword ty64 -> Sinterrupts*) + +val _ = Define ` + ((Mk_Sinterrupts:(64)words$word -> Sinterrupts) v= + (<| Sinterrupts_Sinterrupts_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty64*) val _ = Define ` - ((get_Sinterrupts:Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))= v)`; + ((get_Sinterrupts_bits:Sinterrupts ->(64)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) +(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) val _ = Define ` - ((set_Sinterrupts:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Sinterrupts v) in - state_monad$write_regS r_ref r)))`; + ((set_Sinterrupts_bits:((regstate),(register_value),(Sinterrupts))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts*) val _ = Define ` - ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_bits:Sinterrupts ->(64)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 9 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_SEI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):ii) (( 9 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_SEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_SEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 9 : int):ii) (( 9 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 8 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_UEI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_UEI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_UEI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 8 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_STI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_STI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_STI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_UTI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_UTI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_UTI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_SSI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_SSI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((update_Sinterrupts_SSI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Sinterrupts) . - let r = ((get_Sinterrupts w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Sinterrupts r))))`; + ((get_Sinterrupts_USI:Sinterrupts ->(1)words$word) v= + ((subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) (Mk_Sinterrupts (v)) x= - (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((set_Sinterrupts_USI:((regstate),(register_value),(Sinterrupts))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec r.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_Sinterrupts_USI:Sinterrupts ->(1)words$word -> Sinterrupts) v x= + ((v with<| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec v.Sinterrupts_Sinterrupts_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 64 words$word))|>)))`; (*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*) @@ -3855,7 +5933,7 @@ val _ = Define ` val _ = Define ` ((legalize_sip:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)= - (lift_sip m d (Mk_Sinterrupts v)))`; + (lift_sip m d ((Mk_Sinterrupts v))))`; (*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) @@ -3892,85 +5970,131 @@ val _ = Define ` val _ = Define ` ((legalize_sie:Minterrupts -> Minterrupts ->(64)words$word -> Minterrupts) (m : Minterrupts) (d : Minterrupts) (v : xlenbits)= - (lift_sie m d (Mk_Sinterrupts v)))`; + (lift_sie m d ((Mk_Sinterrupts v))))`; + + +(*val Mk_Satp64 : mword ty64 -> Satp64*) + +val _ = Define ` + ((Mk_Satp64:(64)words$word -> Satp64) v= (<| Satp64_Satp64_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; -(*val _get_Satp64 : Satp64 -> mword ty64*) +(*val _get_Satp64_bits : Satp64 -> mword ty64*) val _ = Define ` - ((get_Satp64:Satp64 ->(64)words$word) (Mk_Satp64 (v))= v)`; + ((get_Satp64_bits:Satp64 ->(64)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; -(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) +(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) val _ = Define ` - ((set_Satp64:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_Satp64 v) in - state_monad$write_regS r_ref r)))`; + ((set_Satp64_bits:((regstate),(register_value),(Satp64))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; +(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*) + val _ = Define ` - ((get_Satp64_Mode:Satp64 ->(4)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii) : 4 words$word)))`; + ((update_Satp64_bits:Satp64 ->(64)words$word -> Satp64) v x= + ((v with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 63 : int):ii) (( 60 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Satp64 r))))`; + ((get_Satp64_Mode:Satp64 ->(4)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii) : 4 words$word)))`; val _ = Define ` - ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):ii) (( 60 : int):ii) x : 64 words$word))))`; + ((set_Satp64_Mode:((regstate),(register_value),(Satp64))register_ref ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec v (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_Satp64_Mode:Satp64 ->(4)words$word -> Satp64) v x= + ((v with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 63 : int):ii) (( 60 : int):ii) + ((subrange_vec_dec x (( 3 : int):ii) (( 0 : int):ii) : 4 words$word)) + : 64 words$word))|>)))`; (*val _get_Satp64_Asid : Satp64 -> mword ty16*) val _ = Define ` - ((get_Satp64_Asid:Satp64 ->(16)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii) : 16 words$word)))`; + ((get_Satp64_Asid:Satp64 ->(16)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii) : 16 words$word)))`; (*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*) val _ = Define ` - ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 59 : int):ii) (( 44 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Satp64 r))))`; + ((set_Satp64_Asid:((regstate),(register_value),(Satp64))register_ref ->(16)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii) + ((subrange_vec_dec v (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*) val _ = Define ` - ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):ii) (( 44 : int):ii) x : 64 words$word))))`; + ((update_Satp64_Asid:Satp64 ->(16)words$word -> Satp64) v x= + ((v with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 59 : int):ii) (( 44 : int):ii) + ((subrange_vec_dec x (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + : 64 words$word))|>)))`; (*val _get_Satp64_PPN : Satp64 -> mword ty44*) val _ = Define ` - ((get_Satp64_PPN:Satp64 ->(44)words$word) (Mk_Satp64 (v))= ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)))`; + ((get_Satp64_PPN:Satp64 ->(44)words$word) v= ((subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)))`; (*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*) val _ = Define ` - ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : Satp64) . - let r = ((get_Satp64 w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 43 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_Satp64 r))))`; + ((set_Satp64_PPN:((regstate),(register_value),(Satp64))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec r.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*) val _ = Define ` - ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) (Mk_Satp64 (v)) x= - (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_Satp64_PPN:Satp64 ->(44)words$word -> Satp64) v x= + ((v with<| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec v.Satp64_Satp64_chunk_0 (( 43 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 64 words$word))|>)))`; (*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*) @@ -3981,7 +6105,7 @@ val _ = Define ` (case ((satpMode_of_bits a ((get_Satp64_Mode s : 4 words$word)))) of NONE => o1 | SOME (Sv32) => o1 - | SOME (_) => (get_Satp64 s : 64 words$word) + | SOME (_) => (get_Satp64_bits s : 64 words$word) )))`; @@ -4070,6 +6194,10 @@ val _ = Define ` "mtval" else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then "mip" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + "pmpcfg0" + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then + "pmpaddr0" else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then "mcycle" else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then @@ -4083,6 +6211,1139 @@ val _ = Define ` else "UNKNOWN"))`; +(*val csr_name_map_forwards : mword ty12 -> string*) + +val _ = Define ` + ((csr_name_map_forwards:(12)words$word -> string) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "ustatus" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "uie" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "utvec" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "uscratch" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "uepc" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "ucause" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "utval" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "uip" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "fflags" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "frm" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "fcsr" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycle" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "time" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instret" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "cycleh" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "timeh" + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "instreth" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sstatus" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "sedeleg" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "sideleg" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sie" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "stvec" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "scounteren" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "sscratch" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "sepc" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "scause" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "stval" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "sip" + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "satp" + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + "mvendorid" + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + "marchid" + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + "mimpid" + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + "mhartid" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mstatus" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "misa" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "medeleg" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mideleg" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mie" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + "mtvec" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + "mcounteren" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mscratch" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + "mepc" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "mcause" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + "mtval" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + "mip" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + "pmpcfg0" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then + "pmpcfg1" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then + "pmpcfg2" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then + "pmpcfg3" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then + "pmpaddr0" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then + "pmpaddr1" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then + "pmpaddr2" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then + "pmpaddr3" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then + "pmpaddr4" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then + "pmpaddr5" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then + "pmpaddr6" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then + "pmpaddr7" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then + "pmpaddr8" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then + "pmpaddr9" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then + "pmpaddr10" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then + "pmpaddr11" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then + "pmpaddr12" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then + "pmpaddr13" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then + "pmpaddr14" + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then + "pmpaddr15" + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycle" + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstret" + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + "mcycleh" + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + "minstreth" + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + "tselect" + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then + "tdata1" + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then + "tdata2" + else "tdata3"))`; + + +(*val csr_name_map_backwards : string -> mword ty12*) + +val _ = Define ` + ((csr_name_map_backwards:string ->(12)words$word) arg_= + ((case arg_ of + "ustatus" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "uie" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "utvec" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word) + | "uscratch" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "uepc" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "ucause" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "utval" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "uip" => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "fflags" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "frm" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "fcsr" => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "cycle" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "time" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "instret" => (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "cycleh" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "timeh" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "instreth" => (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "sstatus" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "sedeleg" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "sideleg" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "sie" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "stvec" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word) + | "scounteren" => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word) + | "sscratch" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "sepc" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "scause" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "stval" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "sip" => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "satp" => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "mvendorid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word) + | "marchid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word) + | "mimpid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word) + | "mhartid" => (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word) + | "mstatus" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "misa" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "medeleg" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "mideleg" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "mie" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "mtvec" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word) + | "mcounteren" => (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word) + | "mscratch" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "mepc" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word) + | "mcause" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "mtval" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word) + | "mip" => (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word) + | "pmpcfg0" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word) + | "pmpcfg1" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word) + | "pmpcfg2" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word) + | "pmpcfg3" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word) + | "pmpaddr0" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word) + | "pmpaddr1" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word) + | "pmpaddr2" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word) + | "pmpaddr3" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word) + | "pmpaddr4" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word) + | "pmpaddr5" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word) + | "pmpaddr6" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word) + | "pmpaddr7" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word) + | "pmpaddr8" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word) + | "pmpaddr9" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word) + | "pmpaddr10" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word) + | "pmpaddr11" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word) + | "pmpaddr12" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word) + | "pmpaddr13" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word) + | "pmpaddr14" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word) + | "pmpaddr15" => (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word) + | "mcycle" => (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "minstret" => (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "mcycleh" => (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + | "minstreth" => (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word) + | "tselect" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word) + | "tdata1" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word) + | "tdata2" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word) + | "tdata3" => (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word) + )))`; + + +(*val csr_name_map_forwards_matches : mword ty12 -> bool*) + +val _ = Define ` + ((csr_name_map_forwards_matches:(12)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word)))) then + T + else if (((p0_ = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word)))) then + T + else F))`; + + +(*val csr_name_map_backwards_matches : string -> bool*) + +val _ = Define ` + ((csr_name_map_backwards_matches:string -> bool) arg_= + ((case arg_ of + "ustatus" => T + | "uie" => T + | "utvec" => T + | "uscratch" => T + | "uepc" => T + | "ucause" => T + | "utval" => T + | "uip" => T + | "fflags" => T + | "frm" => T + | "fcsr" => T + | "cycle" => T + | "time" => T + | "instret" => T + | "cycleh" => T + | "timeh" => T + | "instreth" => T + | "sstatus" => T + | "sedeleg" => T + | "sideleg" => T + | "sie" => T + | "stvec" => T + | "scounteren" => T + | "sscratch" => T + | "sepc" => T + | "scause" => T + | "stval" => T + | "sip" => T + | "satp" => T + | "mvendorid" => T + | "marchid" => T + | "mimpid" => T + | "mhartid" => T + | "mstatus" => T + | "misa" => T + | "medeleg" => T + | "mideleg" => T + | "mie" => T + | "mtvec" => T + | "mcounteren" => T + | "mscratch" => T + | "mepc" => T + | "mcause" => T + | "mtval" => T + | "mip" => T + | "pmpcfg0" => T + | "pmpcfg1" => T + | "pmpcfg2" => T + | "pmpcfg3" => T + | "pmpaddr0" => T + | "pmpaddr1" => T + | "pmpaddr2" => T + | "pmpaddr3" => T + | "pmpaddr4" => T + | "pmpaddr5" => T + | "pmpaddr6" => T + | "pmpaddr7" => T + | "pmpaddr8" => T + | "pmpaddr9" => T + | "pmpaddr10" => T + | "pmpaddr11" => T + | "pmpaddr12" => T + | "pmpaddr13" => T + | "pmpaddr14" => T + | "pmpaddr15" => T + | "mcycle" => T + | "minstret" => T + | "mcycleh" => T + | "minstreth" => T + | "tselect" => T + | "tdata1" => T + | "tdata2" => T + | "tdata3" => T + | _ => F + )))`; + + +(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*) + +val _ = Define ` + ((csr_name_map_matches_prefix:string ->((12)words$word#int)option) arg_= + (let stringappend_1716_0 = arg_ in + if (((((string_startswith stringappend_1716_0 "ustatus")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "ustatus")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "ustatus")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "uie")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "uie")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "uie")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "utvec")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "utvec")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "utvec")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "uscratch")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "uscratch")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "uscratch")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "uepc")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "uepc")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "uepc")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "ucause")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "ucause")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "ucause")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "utval")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "utval")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "utval")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "uip")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "uip")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "uip")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "fflags")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "fflags")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "fflags")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "frm")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "frm")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "frm")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "fcsr")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "fcsr")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "fcsr")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "cycle")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "cycle")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "cycle")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "time")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "time")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "time")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "instret")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "instret")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "instret")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "cycleh")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "cycleh")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "cycleh")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "timeh")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "timeh")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "timeh")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "instreth")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "instreth")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "instreth")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sstatus")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sstatus")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sstatus")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sedeleg")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sedeleg")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sedeleg")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sideleg")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sideleg")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sideleg")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sie")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sie")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sie")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "stvec")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "stvec")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "stvec")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "scounteren")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "scounteren")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "scounteren")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sscratch")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sscratch")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sscratch")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sepc")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sepc")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sepc")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "scause")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "scause")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "scause")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "stval")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "stval")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "stval")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "sip")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "sip")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "sip")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "satp")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "satp")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "satp")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mvendorid")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mvendorid")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mvendorid")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "marchid")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "marchid")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "marchid")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mimpid")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mimpid")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mimpid")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mhartid")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mhartid")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mhartid")))) of + s_ => + SOME ((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mstatus")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mstatus")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mstatus")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "misa")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "misa")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "misa")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "medeleg")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "medeleg")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "medeleg")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mideleg")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mideleg")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mideleg")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mie")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mie")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mie")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mtvec")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mtvec")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mtvec")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mcounteren")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mcounteren")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mcounteren")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mscratch")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mscratch")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mscratch")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mepc")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mepc")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mepc")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mcause")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mcause")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mcause")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mtval")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mtval")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mtval")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mip")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mip")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mip")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpcfg0")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg0")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg0")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpcfg1")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg1")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpcfg2")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg2")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpcfg3")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpcfg3")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr0")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr0")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr0")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr1")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr1")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr2")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr2")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr3")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr3")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr4")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr4")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr4")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr5")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr5")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr5")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr6")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr6")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr6")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr7")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr7")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr7")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr8")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr8")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr8")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr9")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr9")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr9")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr10")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr10")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr10")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr11")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr11")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr11")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr12")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr12")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr12")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr13")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr13")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr13")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr14")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr14")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr14")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "pmpaddr15")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr15")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "pmpaddr15")))) of + s_ => + SOME ((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mcycle")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mcycle")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mcycle")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "minstret")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "minstret")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "minstret")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "mcycleh")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "mcycleh")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "mcycleh")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "minstreth")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "minstreth")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "minstreth")))) of + s_ => + SOME ((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "tselect")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "tselect")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "tselect")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "tdata1")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "tdata1")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "tdata1")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "tdata2")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "tdata2")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "tdata2")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1716_0 "tdata3")) /\ ( + (case ((string_drop stringappend_1716_0 ((string_length "tdata3")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1716_0 ((string_length "tdata3")))) of + s_ => + SOME ((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : 12 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + (*val csrAccess : mword ty12 -> mword ty2*) val _ = Define ` @@ -4132,6 +7393,10 @@ val _ = Define ` (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + (((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then + F else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then ((((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) \/ (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then @@ -4171,42 +7436,94 @@ val _ = Define ` (*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*) val _ = Define ` - ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (state_monad$bindS - (state$and_boolS - (state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word))))) - (state$and_boolS - (state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) - ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . - state_monad$returnS (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ (w__2 : + ((check_TVM_SATP:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= (sail2_state_monad$bindS + (sail2_state$and_boolS + (sail2_state_monad$returnS (((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word))))) + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((privLevel_to_bits p : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + sail2_state_monad$returnS (((((get_Mstatus_TVM w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ (w__2 : bool) . - state_monad$returnS ((~ w__2)))))`; + sail2_state_monad$returnS ((~ w__2)))))`; + + +(*val check_Counteren : mword ty12 -> Privilege -> M bool*) + +val _ = Define ` + ((check_Counteren:(12)words$word -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege)= + ((case (csr, p) of + (b__0, Supervisor) => + if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcounteren_ref) (\ (w__0 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_CY w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcounteren_ref) (\ (w__1 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_TM w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcounteren_ref) (\ (w__2 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_IR w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else + sail2_state_monad$returnS ((case (b__0, Supervisor) of + (g__31, g__32) => + if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + csr)) /\ ((zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then + F + else T + )) + | (b__3, User) => + if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scounteren_ref) (\ (w__6 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_CY w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scounteren_ref) (\ (w__7 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_TM w__7 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else if (((b__3 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scounteren_ref) (\ (w__8 : Counteren) . + sail2_state_monad$returnS (((((get_Counteren_IR w__8 : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + else + sail2_state_monad$returnS ((case (b__3, User) of + (g__31, g__32) => + if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + csr)) /\ ((zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then + F + else T + )) + | (g__31, g__32) => + sail2_state_monad$returnS (if (((((zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word) + csr)) /\ ((zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : 12 words$word)))))) then + F + else T) + )))`; (*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*) val _ = Define ` - ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)= - (state$and_boolS (state_monad$returnS ((is_CSR_defined csr p))) - (state$and_boolS - (state_monad$returnS ((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p - isWrite))) ((check_TVM_SATP csr p)))))`; + ((check_CSR:(12)words$word -> Privilege -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (p : Privilege) (isWrite : bool)= + (sail2_state$and_boolS (sail2_state_monad$returnS ((is_CSR_defined csr p))) + (sail2_state$and_boolS + (sail2_state_monad$returnS ((check_CSR_access ((csrAccess csr : 2 words$word)) ((csrPriv csr : 2 words$word)) p + isWrite))) (sail2_state$and_boolS ((check_TVM_SATP csr p)) ((check_Counteren csr p))))))`; (*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*) val _ = Define ` - ((exception_delegatee:ExceptionType -> Privilege ->(regstate)state_monad$sequential_state ->(((Privilege),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)= - (let idx = (num_of_ExceptionType e) in state_monad$bindS - (state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) . - let super = (access_vec_dec ((get_Medeleg w__0 : 64 words$word)) idx) in state_monad$bindS - (state_monad$read_regS sedeleg_ref) (\ (w__1 : Sedeleg) . - let user = (access_vec_dec ((get_Sedeleg w__1 : 64 words$word)) idx) in state_monad$bindS - (state$and_boolS - ( state_monad$bindS(state_monad$read_regS misa_ref) (\ (w__2 : Misa) . - state_monad$returnS (((((get_Misa_S w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) - (state_monad$returnS ((bit_to_bool super)))) (\ (w__3 : bool) . + ((exception_delegatee:ExceptionType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((Privilege),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (e : ExceptionType) (p : Privilege)= + (let idx = (num_of_ExceptionType e) in sail2_state_monad$bindS + (sail2_state_monad$read_regS medeleg_ref) (\ (w__0 : Medeleg) . + let super = (access_vec_dec ((get_Medeleg_bits w__0 : 64 words$word)) idx) in sail2_state_monad$bindS + (sail2_state_monad$read_regS sedeleg_ref) (\ (w__1 : Sedeleg) . + let user = (access_vec_dec ((get_Sedeleg_bits w__1 : 64 words$word)) idx) in sail2_state_monad$bindS + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS misa_ref) (\ (w__2 : Misa) . + sail2_state_monad$returnS (((((get_Misa_S w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) + (sail2_state_monad$returnS ((bit_to_bool super)))) (\ (w__3 : bool) . let deleg = (if w__3 then Supervisor else Machine) in - state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg : 2 words$word)) + sail2_state_monad$returnS (if ((zopz0zI_u ((privLevel_to_bits deleg : 2 words$word)) ((privLevel_to_bits p : 2 words$word)))) then p else deleg))))))`; @@ -4246,51 +7563,98 @@ val _ = Define ` else NONE))`; -(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) +(*val curInterrupt : Privilege -> Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) val _ = Define ` - ((curInterrupt:Minterrupts -> Minterrupts -> Minterrupts ->(regstate)state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts)= + ((curInterrupt:Privilege -> Minterrupts -> Minterrupts -> Minterrupts ->(regstate)sail2_state_monad$sequential_state ->((((InterruptType#Privilege)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (priv : Privilege) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts)= (let (en_mip : xlenbits) = - ((and_vec ((get_Minterrupts pend : 64 words$word)) ((get_Minterrupts enbl : 64 words$word)) + ((and_vec ((get_Minterrupts_bits pend : 64 words$word)) + ((get_Minterrupts_bits enbl : 64 words$word)) : 64 words$word)) in if (((en_mip = ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))) then - state_monad$returnS NONE - else + sail2_state_monad$returnS NONE + else sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) <> ((privLevel_to_bits Machine : 2 words$word)))))) + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + sail2_state_monad$returnS (((((get_Mstatus_MIE w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ eff_mie . sail2_state_monad$bindS + (sail2_state$or_boolS + (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))) + (sail2_state$and_boolS + (sail2_state_monad$returnS (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word)))))) + ( sail2_state_monad$bindS(sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + sail2_state_monad$returnS (((((get_Mstatus_SIE w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) (\ eff_sie . let eff_mip = - ((and_vec en_mip ((not_vec ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) + ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg : 64 words$word)) : 64 words$word)) : 64 words$word)) in - let eff_sip = ((and_vec en_mip ((get_Minterrupts delg : 64 words$word)) : 64 words$word)) in state_monad$bindS - (state$and_boolS - ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . - state_monad$returnS (((((get_Mstatus_MIE w__0 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) - (state_monad$returnS (((eff_mip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))))))) (\ (w__1 : - bool) . - if w__1 then - state_monad$returnS ((case ((findPendingInterrupt eff_mip)) of + let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg : 64 words$word)) : 64 words$word)) in + if (((eff_mie /\ (((eff_mip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))) then + (case ((findPendingInterrupt eff_mip)) of SOME (i) => let r = (i, Machine) in - SOME r - | NONE => NONE - )) - else state_monad$bindS - (state$and_boolS - ( state_monad$bindS(state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . - state_monad$returnS (((((get_Mstatus_SIE w__2 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))) - (state$and_boolS - (state_monad$returnS (((eff_sip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))) - (state$or_boolS - ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__3 : Privilege) . - state_monad$returnS (((((privLevel_to_bits w__3 : 2 words$word)) = ((privLevel_to_bits Supervisor : 2 words$word))))))) - ( state_monad$bindS(state_monad$read_regS cur_privilege_ref) (\ (w__4 : Privilege) . - state_monad$returnS (((((privLevel_to_bits w__4 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word)))))))))) (\ (w__7 : bool) . - state_monad$returnS (if w__7 then - (case ((findPendingInterrupt eff_sip)) of - SOME (i) => - let r = (i, Supervisor) in - SOME r - | NONE => NONE - ) - else NONE)))))`; + sail2_state_monad$returnS (SOME r) + | NONE => + internal_error + ((STRCAT "non-zero eff_mip=" + ((STRCAT ((string_of_bits eff_mip)) ", but nothing pending")))) + ) + else if (((eff_sie /\ (((eff_sip <> ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))) + then + (case ((findPendingInterrupt eff_sip)) of + SOME (i) => + let r = (i, Supervisor) in + sail2_state_monad$returnS (SOME r) + | NONE => + internal_error + ((STRCAT "non-zero eff_sip=" + ((STRCAT ((string_of_bits eff_sip)) ", but nothing pending")))) + ) + else + let p = + (if (((((get_Minterrupts_MTI pend : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + "1" + else "0") in + let e = + (if (((((get_Minterrupts_MTI enbl : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + "1" + else "0") in + let d = + (if (((((get_Minterrupts_MTI delg : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + then + "1" + else "0") in + let (_ : unit) = + (print_endline + ((STRCAT " MTI: pend=" + ((STRCAT p + ((STRCAT " enbl=" ((STRCAT e ((STRCAT " delg=" d))))))))))) in + let eff_mip = + ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg : 64 words$word)) : 64 words$word)) + : 64 words$word)) in + let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg : 64 words$word)) : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__8 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__9 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__10 : Mstatus) . + let (_ : unit) = + (print_endline + ((STRCAT "mstatus=" + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__8 : 64 words$word)))) + ((STRCAT " mie,sie=" + ((STRCAT ((string_of_bits ((get_Mstatus_MIE w__9 : 1 words$word)))) + ((STRCAT "," + ((STRCAT + ((string_of_bits ((get_Mstatus_SIE w__10 : 1 words$word)))) + ((STRCAT " en_mip=" + ((STRCAT ((string_of_bits en_mip)) + ((STRCAT " eff_mip=" + ((STRCAT ((string_of_bits eff_mip)) + ((STRCAT " eff_sip=" + ((string_of_bits eff_sip))))))))))))))))))))))))) in + sail2_state_monad$returnS NONE)))))))`; (*val tval : maybe (mword ty64) -> mword ty64*) @@ -4306,57 +7670,76 @@ val _ = Define ` (*val handle_trap : Privilege -> bool -> mword ty4 -> mword ty64 -> maybe (mword ty64) -> M (mword ty64)*) val _ = Define ` - ((handle_trap:Privilege -> bool ->(4)words$word ->(64)words$word ->(xlenbits)option ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info : + ((handle_trap:Privilege -> bool ->(4)words$word ->(64)words$word ->(xlenbits)option ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (del_priv : Privilege) (intr : bool) (c : exc_code) (pc : xlenbits) (info : xlenbits option)= (let (_ : unit) = - (prerr_endline + (print_endline ((STRCAT "handling " ((STRCAT (if intr then "int#" else "exc#") - ((STRCAT ((string_of_vec c)) + ((STRCAT ((string_of_bits c)) ((STRCAT " at priv " ((STRCAT ((privLevel_to_str del_priv)) ((STRCAT " with tval " - ((string_of_vec ((tval info : 64 words$word))))))))))))))))) in + ((string_of_bits ((tval info : 64 words$word))))))))))))))))) in (case del_priv of - Machine => state_monad$bindS (state_monad$seqS (state_monad$seqS + Machine => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr : 1 words$word))) (set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word)))) - (state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__0 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 : 1 words$word))) (set_Mstatus_MIE mstatus_ref ((bool_to_bits F : 1 words$word)))) - (state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS + (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__1 : Privilege) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 : 2 words$word))) - (state_monad$write_regS mtval_ref ((tval info : 64 words$word)))) - (state_monad$write_regS mepc_ref pc)) - (state_monad$write_regS cur_privilege_ref del_priv)) - (state_monad$read_regS mtvec_ref)) (\ (w__2 : Mtvec) . state_monad$bindS - (state_monad$read_regS mcause_ref) (\ (w__3 : Mcause) . - (case ((tvec_addr w__2 w__3 : ( 64 words$word)option)) of - SOME (epc) => state_monad$returnS epc + (sail2_state_monad$write_regS mtval_ref ((tval info : 64 words$word)))) + (sail2_state_monad$write_regS mepc_ref pc)) + (sail2_state_monad$write_regS cur_privilege_ref del_priv)) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__3 : Mstatus) . + let (_ : unit) = + (print_endline + ((STRCAT "CSR mstatus <- " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__2 : 64 words$word)))) + ((STRCAT " (input: " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__3 : 64 words$word)))) ")"))))))))) in + let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mtvec_ref) (\ (w__4 : Mtvec) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mcause_ref) (\ (w__5 : Mcause) . + (case ((tvec_addr w__4 w__5 : ( 64 words$word)option)) of + SOME (epc) => sail2_state_monad$returnS epc | NONE => (internal_error "Invalid mtvec mode" : ( 64 words$word) M) - ))))) - | Supervisor => state_monad$bindS (state_monad$seqS (state_monad$seqS + ))))))) + | Supervisor => sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr : 1 words$word))) (set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):ii) c : 63 words$word)))) - (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 : 1 words$word))) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__8 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__8 : 1 words$word))) (set_Mstatus_SIE mstatus_ref ((bool_to_bits F : 1 words$word)))) - (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . state_monad$bindS - (case w__7 of - User => state_monad$returnS ((bool_to_bits F : 1 words$word)) - | Supervisor => state_monad$returnS ((bool_to_bits T : 1 words$word)) + (sail2_state_monad$read_regS cur_privilege_ref)) (\ (w__9 : Privilege) . sail2_state_monad$bindS + (case w__9 of + User => sail2_state_monad$returnS ((bool_to_bits F : 1 words$word)) + | Supervisor => sail2_state_monad$returnS ((bool_to_bits T : 1 words$word)) | Machine => (internal_error "invalid privilege for s-mode trap" : ( 1 words$word) M) - ) (\ (w__9 : 1 words$word) . state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS - (set_Mstatus_SPP mstatus_ref w__9) - (state_monad$write_regS stval_ref ((tval info : 64 words$word)))) - (state_monad$write_regS sepc_ref pc)) - (state_monad$write_regS cur_privilege_ref del_priv)) - (state_monad$read_regS stvec_ref)) (\ (w__10 : Mtvec) . state_monad$bindS - (state_monad$read_regS scause_ref) (\ (w__11 : Mcause) . - (case ((tvec_addr w__10 w__11 : ( 64 words$word)option)) of - SOME (epc) => state_monad$returnS epc + ) (\ (w__11 : 1 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_Mstatus_SPP mstatus_ref w__11) + (sail2_state_monad$write_regS stval_ref ((tval info : 64 words$word)))) + (sail2_state_monad$write_regS sepc_ref pc)) + (sail2_state_monad$write_regS cur_privilege_ref del_priv)) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__12 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__13 : Mstatus) . + let (_ : unit) = + (print_endline + ((STRCAT "CSR mstatus <- " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__12 : 64 words$word)))) + ((STRCAT " (input: " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__13 : 64 words$word)))) + ")"))))))))) in + let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS + (sail2_state_monad$read_regS stvec_ref) (\ (w__14 : Mtvec) . sail2_state_monad$bindS + (sail2_state_monad$read_regS scause_ref) (\ (w__15 : Mcause) . + (case ((tvec_addr w__14 w__15 : ( 64 words$word)option)) of + SOME (epc) => sail2_state_monad$returnS epc | NONE => (internal_error "Invalid stvec mode" : ( 64 words$word) M) - )))))) + )))))))) | User => (internal_error "the N extension is currently unsupported" : ( 64 words$word) M) )))`; @@ -4364,12 +7747,12 @@ val _ = Define ` (*val handle_exception : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*) val _ = Define ` - ((handle_exception:Privilege -> ctl_result ->(64)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)= + ((handle_exception:Privilege -> ctl_result ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (cur_priv : Privilege) (ctl : ctl_result) (pc : xlenbits)= ((case (cur_priv, ctl) of - (_, CTL_TRAP (e)) => state_monad$bindS + (_, CTL_TRAP (e)) => sail2_state_monad$bindS (exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . let (_ : unit) = - (prerr_endline + (print_endline ((STRCAT "trapping from " ((STRCAT ((privLevel_to_str cur_priv)) ((STRCAT " to " @@ -4379,269 +7762,1031 @@ val _ = Define ` (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap : 4 words$word)) pc e.sync_exception_excinfo : ( 64 words$word) M)) - | (_, CTL_MRET (_)) => state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ prev_priv . state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS + | (_, CTL_MRET (_)) => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 : 1 words$word))) (set_Mstatus_MPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) - (state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) (set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User : 2 words$word)))) - (state_monad$read_regS cur_privilege_ref)) (\ (w__3 : Privilege) . + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__3 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . + let (_ : unit) = + (print_endline + ((STRCAT "CSR mstatus <- " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__3 : 64 words$word)))) + ((STRCAT " (input: " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__4 : 64 words$word)))) ")"))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) . let (_ : unit) = - (prerr_endline + (print_endline ((STRCAT "ret-ing from " ((STRCAT ((privLevel_to_str prev_priv)) - ((STRCAT " to " ((privLevel_to_str w__3))))))))) in - (state_monad$read_regS mepc_ref : ( 64 words$word) M))))) - | (_, CTL_SRET (_)) => state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ prev_priv . state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 : 1 words$word))) + ((STRCAT " to " ((privLevel_to_str w__5))))))))) in + let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mepc_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . sail2_state_monad$bindS + (pc_alignment_mask () : ( 64 words$word) M) (\ (w__7 : 64 words$word) . + sail2_state_monad$returnS ((and_vec w__6 w__7 : 64 words$word)))))))))) + | (_, CTL_SRET (_)) => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ prev_priv . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__8 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__8 : 1 words$word))) (set_Mstatus_SPIE mstatus_ref ((bool_to_bits T : 1 words$word)))) - (state_monad$read_regS mstatus_ref)) (\ (w__6 : Mstatus) . state_monad$bindS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__9 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS cur_privilege_ref - (if (((((get_Mstatus_SPP w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) + (if (((((get_Mstatus_SPP w__9 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then Supervisor else User)) (set_Mstatus_SPP mstatus_ref ((bool_to_bits F : 1 words$word)))) - (state_monad$read_regS cur_privilege_ref)) (\ (w__7 : Privilege) . + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__10 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__11 : Mstatus) . + let (_ : unit) = + (print_endline + ((STRCAT "CSR mstatus <- " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__10 : 64 words$word)))) + ((STRCAT " (input: " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__11 : 64 words$word)))) + ")"))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__12 : Privilege) . let (_ : unit) = - (prerr_endline + (print_endline ((STRCAT "ret-ing from " ((STRCAT ((privLevel_to_str prev_priv)) - ((STRCAT " to " ((privLevel_to_str w__7))))))))) in - (state_monad$read_regS sepc_ref : ( 64 words$word) M))))) + ((STRCAT " to " ((privLevel_to_str w__12))))))))) in + let (_ : unit) = (cancel_reservation () ) in sail2_state_monad$bindS + (sail2_state_monad$read_regS sepc_ref : ( 64 words$word) M) (\ (w__13 : 64 words$word) . sail2_state_monad$bindS + (pc_alignment_mask () : ( 64 words$word) M) (\ (w__14 : 64 words$word) . + sail2_state_monad$returnS ((and_vec w__13 w__14 : 64 words$word)))))))))) )))`; (*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*) val _ = Define ` - ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)= - (let (t : sync_exception) = (<| sync_exception_trap := e; sync_exception_excinfo := (SOME addr) |>) in state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + ((handle_mem_exception:(64)words$word -> ExceptionType ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (e : ExceptionType)= + (let (t : sync_exception) = (<| sync_exception_trap := e; sync_exception_excinfo := (SOME addr) |>) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . - state_monad$write_regS nextPC_ref w__2)))))`; + sail2_state_monad$write_regS nextPC_ref w__2)))))`; (*val handle_decode_exception : mword ty64 -> M unit*) val _ = Define ` - ((handle_decode_exception:(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) instbits= + ((handle_decode_exception:(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) instbits= (let (t : sync_exception) = (<| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := (SOME instbits) |>) in state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + sync_exception_excinfo := (SOME instbits) |>) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . - state_monad$write_regS nextPC_ref w__2)))))`; + sail2_state_monad$write_regS nextPC_ref w__2)))))`; (*val handle_interrupt : InterruptType -> Privilege -> M unit*) val _ = Define ` - ((handle_interrupt:InterruptType -> Privilege ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS + ((handle_interrupt:InterruptType -> Privilege ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (i : InterruptType) (del_priv : Privilege)= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (handle_trap del_priv T ((interruptType_to_bits i : 4 words$word)) w__0 NONE : ( 64 words$word) M) (\ (w__1 : xlenbits) . - state_monad$write_regS nextPC_ref w__1))))`; + sail2_state_monad$write_regS nextPC_ref w__1))))`; (*val handle_illegal : unit -> M unit*) val _ = Define ` - ((handle_illegal:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = + ((handle_illegal:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (let (t : sync_exception) = (<| sync_exception_trap := E_Illegal_Instr; - sync_exception_excinfo := NONE |>) in state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . state_monad$bindS + sync_exception_excinfo := NONE |>) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . sail2_state_monad$bindS (handle_exception w__0 (CTL_TRAP t) w__1 : ( 64 words$word) M) (\ (w__2 : xlenbits) . - state_monad$write_regS nextPC_ref w__2)))))`; + sail2_state_monad$write_regS nextPC_ref w__2)))))`; (*val init_sys : unit -> M unit*) val _ = Define ` - ((init_sys:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS (state_monad$seqS - (state_monad$write_regS cur_privilege_ref Machine) + ((init_sys:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS cur_privilege_ref Machine) + (sail2_state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) (set_Misa_MXL misa_ref ((arch_to_bits RV64 : 2 words$word)))) + (set_Misa_A misa_ref ((bool_to_bits T : 1 words$word)))) (set_Misa_C misa_ref ((bool_to_bits T : 1 words$word)))) + (set_Misa_I misa_ref ((bool_to_bits T : 1 words$word)))) + (set_Misa_M misa_ref ((bool_to_bits T : 1 words$word)))) (set_Misa_U misa_ref ((bool_to_bits T : 1 words$word)))) (set_Misa_S misa_ref ((bool_to_bits T : 1 words$word)))) - (state_monad$read_regS misa_ref)) (\ (w__0 : Misa) . state_monad$bindS (state_monad$seqS + (sail2_state_monad$read_regS misa_ref)) (\ (w__0 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 : 2 words$word))) - (state_monad$read_regS misa_ref)) (\ (w__1 : Misa) . state_monad$seqS (state_monad$seqS + (sail2_state_monad$read_regS misa_ref)) (\ (w__1 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (sail2_state_monad$seqS (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 : 2 words$word))) (set_Mstatus_SD mstatus_ref ((bool_to_bits F : 1 words$word)))) - (state_monad$write_regS mhartid_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))))`; + (set_Minterrupts_bits mip_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Minterrupts_bits mie_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Medeleg_bits medeleg_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Mtvec_bits mtvec_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Mcause_bits mcause_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS mepc_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS mtval_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS mscratch_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS mcycle_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS mtime_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (set_Counteren_bits mcounteren_ref ((EXTZ (( 32 : int):ii) (vec_of_bits [B0] : 1 words$word) : 32 words$word)))) + (sail2_state_monad$write_regS minstret_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + (sail2_state_monad$write_regS minstret_written_ref F)) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__2 : Mstatus) . + sail2_state_monad$returnS ((print_endline + ((STRCAT "CSR mstatus <- " + ((STRCAT ((string_of_bits ((get_Mstatus_bits w__2 : 64 words$word)))) + ((STRCAT " (input: " + ((STRCAT + ((string_of_bits + ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))) + ")")))))))))))))))`; + + +(*val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))*) + +val _ = Define ` + ((phys_mem_segments:unit ->((64)words$word#(64)words$word)list) () = + (((plat_rom_base () : 64 words$word), (plat_rom_size () : 64 words$word)) :: + (((plat_ram_base () : 64 words$word), (plat_ram_size () : 64 words$word)) :: [])))`; + + +(*val within_phys_mem : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_phys_mem:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (if (((((zopz0zIzJ_u ((plat_ram_base () : 64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width : 64 words$word)) + ((add_vec ((plat_ram_base () : 64 words$word)) ((plat_ram_size () : 64 words$word)) + : 64 words$word))))))) then + T + else if (((((zopz0zIzJ_u ((plat_rom_base () : 64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width : 64 words$word)) + ((add_vec ((plat_rom_base () : 64 words$word)) ((plat_rom_size () : 64 words$word)) + : 64 words$word))))))) then + T + else F))`; + + +(*val within_clint : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_clint:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((zopz0zIzJ_u ((plat_clint_base () : 64 words$word)) addr)) /\ ((zopz0zIzJ_u ((add_vec_int addr width : 64 words$word)) + ((add_vec ((plat_clint_base () : 64 words$word)) ((plat_clint_size () : 64 words$word)) + : 64 words$word))))))`; + + +(*val within_htif_writable : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_htif_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((plat_htif_tohost () : 64 words$word)) = addr))`; + + +(*val within_htif_readable : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_htif_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((plat_htif_tohost () : 64 words$word)) = addr))`; + + +val _ = Define ` +((MSIP_BASE:(64)words$word)= + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))`; + + +val _ = Define ` +((MTIMECMP_BASE:(64)words$word)= + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)))`; + + +val _ = Define ` +((MTIME_BASE:(64)words$word)= + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B0;B0;B0] + : 64 words$word)))`; + + +(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((clint_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + (let addr = ((sub_vec addr ((plat_clint_base () : 64 words$word)) : 64 words$word)) in + if ((((((addr = MSIP_BASE))) /\ ((((((width = (( 8 : int):ii)))) \/ (((width = (( 4 : int):ii)))))))))) + then sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) . + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) + ((STRCAT "] -> " + ((string_of_bits ((get_Minterrupts_MSI w__0 : 1 words$word))))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__1 : Minterrupts) . + sail2_state_monad$returnS (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 : 1 words$word)) + (((( 8 : int):ii) * width)) + : 'int8_times_n words$word))))) + else if ((((((addr = MTIMECMP_BASE))) /\ (((width = (( 8 : int):ii))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__2 : xlenbits) . + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__2))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M) (\ (w__3 : xlenbits) . + sail2_state_monad$returnS (MemValue ((zero_extend w__3 (( 64 : int):ii) : 'int8_times_n words$word))))) + else if ((((((addr = MTIME_BASE))) /\ (((width = (( 8 : int):ii))))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__4 : xlenbits) . + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__4))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__5 : xlenbits) . + sail2_state_monad$returnS (MemValue ((zero_extend w__5 (( 64 : int):ii) : 'int8_times_n words$word))))) + else + let (_ : unit) = + (print_endline + ((STRCAT "clint[" ((STRCAT ((string_of_bits addr)) "] -> <not-mapped>"))))) in + sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`; + + +(*val clint_dispatch : unit -> M unit*) + +val _ = Define ` + ((clint_dispatch:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + let (_ : unit) = (print_endline ((STRCAT "clint::tick mtime <- " ((string_of_bits w__0))))) in sail2_state_monad$bindS (sail2_state_monad$seqS + (set_Minterrupts_MTI mip_ref ((bool_to_bits F : 1 words$word))) + (sail2_state_monad$read_regS mtimecmp_ref : ( 64 words$word) M)) (\ (w__1 : xlenbits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . + if ((zopz0zIzJ_u w__1 w__2)) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) (\ (w__3 : xlenbits) . + let (_ : unit) = + (print_endline ((STRCAT " clint timer pending at mtime " ((string_of_bits w__3))))) in + set_Minterrupts_MTI mip_ref ((bool_to_bits T : 1 words$word))) + else sail2_state_monad$returnS () )))))`; + + +(*val clint_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((clint_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= + (let addr = ((sub_vec addr ((plat_clint_base () : 64 words$word)) : 64 words$word)) in + if ((((((addr = MSIP_BASE))) /\ ((((((width = (( 8 : int):ii)))) \/ (((width = (( 4 : int):ii)))))))))) + then + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) + ((STRCAT "] <- " + ((STRCAT ((string_of_bits data)) + ((STRCAT " (mip.MSI <- " + ((STRCAT + ((string_of_bits + ((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word)))) + ")"))))))))))))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (set_Minterrupts_MSI mip_ref + ((bool_to_bits + (((((cast_unit_vec0 ((access_vec_dec data (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) + : 1 words$word))) + (clint_dispatch () )) (sail2_state_monad$returnS (MemValue () )) + else if ((((((addr = MTIMECMP_BASE))) /\ (((width = (( 8 : int):ii))))))) then + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) + ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (mtimecmp)"))))))))) in sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mtimecmp_ref ((zero_extend data (( 64 : int):ii) : 64 words$word))) + (clint_dispatch () )) (sail2_state_monad$returnS (MemValue () )) + else + let (_ : unit) = + (print_endline + ((STRCAT "clint[" + ((STRCAT ((string_of_bits addr)) + ((STRCAT "] <- " ((STRCAT ((string_of_bits data)) " (<unmapped>)"))))))))) in + sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`; (*val tick_clock : unit -> M unit*) val _ = Define ` - ((tick_clock:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii) : 64 words$word)))))`; + ((tick_clock:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):ii) : 64 words$word))) + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . sail2_state_monad$seqS + (sail2_state_monad$write_regS mtime_ref ((add_vec_int w__1 (( 1 : int):ii) : 64 words$word))) (clint_dispatch () )))))`; + + +(*val Mk_htif_cmd : mword ty64 -> htif_cmd*) + +val _ = Define ` + ((Mk_htif_cmd:(64)words$word -> htif_cmd) v= + (<| htif_cmd_htif_cmd_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; + + +(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*) + +val _ = Define ` + ((get_htif_cmd_bits:htif_cmd ->(64)words$word) v= + ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; + + +(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*) + +val _ = Define ` + ((set_htif_cmd_bits:((regstate),(register_value),(htif_cmd))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*) + +val _ = Define ` + ((update_htif_cmd_bits:htif_cmd ->(64)words$word -> htif_cmd) v x= + ((v with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_htif_cmd_device : htif_cmd -> mword ty8*) + +val _ = Define ` + ((get_htif_cmd_device:htif_cmd ->(8)words$word) v= + ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii) : 8 words$word)))`; + + +(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_htif_cmd_device:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*) + +val _ = Define ` + ((update_htif_cmd_device:htif_cmd ->(8)words$word -> htif_cmd) v x= + ((v with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 63 : int):ii) (( 56 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*) + +val _ = Define ` + ((get_htif_cmd_cmd:htif_cmd ->(8)words$word) v= + ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii) : 8 words$word)))`; + + +(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_htif_cmd_cmd:((regstate),(register_value),(htif_cmd))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*) + +val _ = Define ` + ((update_htif_cmd_cmd:htif_cmd ->(8)words$word -> htif_cmd) v x= + ((v with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 55 : int):ii) (( 48 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)))`; + + +(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*) + +val _ = Define ` + ((get_htif_cmd_payload:htif_cmd ->(48)words$word) v= + ((subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)))`; + + +(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*) + +val _ = Define ` + ((set_htif_cmd_payload:((regstate),(register_value),(htif_cmd))register_ref ->(48)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec r.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*) + +val _ = Define ` + ((update_htif_cmd_payload:htif_cmd ->(48)words$word -> htif_cmd) v x= + ((v with<| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec v.htif_cmd_htif_cmd_chunk_0 (( 47 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 47 : int):ii) (( 0 : int):ii) : 48 words$word)) + : 64 words$word))|>)))`; + + +(*val htif_load : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((htif_load:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= (sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + let (_ : unit) = + (print_endline + ((STRCAT "htif[" + ((STRCAT ((string_of_bits addr)) ((STRCAT "] -> " ((string_of_bits w__0))))))))) in + if (((width = (( 8 : int):ii)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__1 : xlenbits) . + sail2_state_monad$returnS (MemValue ((zero_extend w__1 (( 64 : int):ii) : 'int8_times_n words$word)))) + else sail2_state_monad$returnS (MemException E_Load_Access_Fault))))`; + + +(*val htif_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((htif_store:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= + (let (_ : unit) = + (print_endline + ((STRCAT "htif[" + ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))) in + let (cbits : xlenbits) = ((EXTZ (( 64 : int):ii) data : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS htif_tohost_ref cbits) + (let cmd = (Mk_htif_cmd cbits) in + let b__0 = ((get_htif_cmd_device cmd : 8 words$word)) in sail2_state_monad$seqS + (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then + let (_ : unit) = + (print_endline + ((STRCAT "htif-syscall-proxy cmd: " + ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))) in + if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 0 : int):ii))) + : 1 words$word)) = (vec_of_bits [B1] : 1 words$word)))) then sail2_state_monad$seqS + (sail2_state_monad$write_regS htif_done_ref T) + (sail2_state_monad$write_regS + htif_exit_code_ref + ((shift_bits_right + ((zero_extend ((get_htif_cmd_payload cmd : 48 words$word)) xlen : 64 words$word)) + (vec_of_bits [B0;B1] : 2 words$word) + : 64 words$word))) + else sail2_state_monad$returnS () + else + sail2_state_monad$returnS (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then + let (_ : unit) = + (print_endline + ((STRCAT "htif-term cmd: " + ((string_of_bits ((get_htif_cmd_payload cmd : 48 words$word))))))) in + let b__2 = ((get_htif_cmd_cmd cmd : 8 words$word)) in + if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then () + else if (((b__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : 8 words$word)))) then + plat_term_write + ((subrange_vec_dec ((get_htif_cmd_payload cmd : 48 words$word)) (( 7 : int):ii) (( 0 : int):ii) + : 8 words$word)) + else print_endline ((STRCAT "Unknown term cmd: " ((string_of_bits b__2)))) + else print_endline ((STRCAT "htif-???? cmd: " ((string_of_bits data)))))) + (sail2_state_monad$returnS (MemValue () )))))`; + + +(*val htif_tick : unit -> M unit*) + +val _ = Define ` + ((htif_tick:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_tohost_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + let (_ : unit) = (print_endline ((STRCAT "htif::tick " ((string_of_bits w__0))))) in + sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`; + + +(*val within_mmio_readable : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_mmio_readable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((within_clint addr width)) \/ (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= width)))))))`; + + +(*val within_mmio_writable : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((within_mmio_writable:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((within_clint addr width)) \/ (((((within_htif_writable addr width)) /\ ((width <= (( 8 : int):ii))))))))`; + + +(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((mmio_read:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int)= + (if ((within_clint addr width)) then + (clint_load addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + else if (((((within_htif_readable addr width)) /\ (((( 1 : int):ii) <= width))))) then + (htif_load addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`; + + +(*val mmio_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((mmio_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)= + (if ((within_clint addr width)) then clint_store addr width data + else if (((((within_htif_writable addr width)) /\ ((width <= (( 8 : int):ii)))))) then + htif_store addr width data + else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`; + + +(*val init_platform : unit -> M unit*) + +val _ = Define ` + ((init_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS htif_tohost_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) + (sail2_state_monad$write_regS htif_done_ref F)) + (sail2_state_monad$write_regS htif_exit_code_ref ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word)))))`; + + +(*val tick_platform : unit -> M unit*) + +val _ = Define ` + ((tick_platform:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (let (_ : unit) = (cancel_reservation () ) in + htif_tick () ))`; + + +(*val is_aligned_addr : mword ty64 -> integer -> bool*) + +val _ = Define ` + ((is_aligned_addr:(64)words$word -> int -> bool) (addr : xlenbits) (width : int)= + (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):ii)))`; + + +(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((phys_mem_read:ReadType ->(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int) (aq : bool) (rl : bool) (res : + bool)= (sail2_state_monad$bindS + (RISCV_read addr width aq rl res : ( ( 'int8_times_n words$word)option) M) (\ (w__0 : + ( 'int8_times_n words$word)option) . + sail2_state_monad$returnS ((case (t, w__0) of + (Instruction, NONE) => MemException E_Fetch_Access_Fault + | (Data, NONE) => MemException E_Load_Access_Fault + | (_, SOME (v)) => + let (_ : unit) = + (print_endline + ((STRCAT "mem[" + ((STRCAT ((readType_to_str t)) + ((STRCAT "," + ((STRCAT ((string_of_bits addr)) + ((STRCAT "] -> " ((string_of_bits v))))))))))))) in + MemValue v + )))))`; + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((checked_mem_read:ReadType ->(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (t : ReadType) (addr : xlenbits) (width : int)= + (if ((((((((readType_to_str t)) = ((readType_to_str Data))))) /\ ((within_mmio_readable addr width))))) then + (mmio_read addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + else if ((within_phys_mem addr width)) then + (phys_mem_read t addr width F F F : ( ( 'int8_times_n words$word)MemoryOpResult) M) + else sail2_state_monad$returnS (MemException E_Load_Access_Fault)))`; + + +(*val MEMr : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((MEMr0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_strong_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +val _ = Define ` + ((MEMr_reserved_strong_acquire0:(64)words$word -> int ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width= + ((checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M)))`; + + +(*val mem_read : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +val _ = Define ` + ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((('int8_times_n words$word)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl res= + (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then + sail2_state_monad$returnS (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (F, F, F) => + (checked_mem_read Data addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (T, F, F) => (MEMr_acquire0 addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, F, T) => + (MEMr_reserved0 addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (T, F, T) => + (MEMr_reserved_acquire0 addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, T, F) => sail2_state_monad$throwS (Error_not_implemented "load.rl") + | (T, T, F) => + (MEMr_strong_acquire0 addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + | (F, T, T) => sail2_state_monad$throwS (Error_not_implemented "lr.rl") + | (T, T, T) => + (MEMr_reserved_strong_acquire0 addr width : ( ( 'int8_times_n words$word)MemoryOpResult) M) + )))`; + + +(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + sail2_state_monad$returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => sail2_state_monad$seqS (MEMea addr width) (sail2_state_monad$returnS (MemValue () )) + | (F, T, F) => sail2_state_monad$seqS (MEMea_release addr width) (sail2_state_monad$returnS (MemValue () )) + | (F, F, T) => sail2_state_monad$seqS (MEMea_conditional addr width) (sail2_state_monad$returnS (MemValue () )) + | (F, T, T) => sail2_state_monad$seqS (MEMea_conditional_release addr width) (sail2_state_monad$returnS (MemValue () )) + | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq") + | (T, T, F) => sail2_state_monad$seqS (MEMea_strong_release addr width) (sail2_state_monad$returnS (MemValue () )) + | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq") + | (T, T, T) => sail2_state_monad$seqS (MEMea_conditional_strong_release addr width) (sail2_state_monad$returnS (MemValue () )) + )))`; + + +(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((phys_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)= + (let (_ : unit) = + (print_endline + ((STRCAT "mem[" + ((STRCAT ((string_of_bits addr)) ((STRCAT "] <- " ((string_of_bits data))))))))) in sail2_state_monad$bindS + (RISCV_write addr width data) (\ (w__0 : bool) . + sail2_state_monad$returnS (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault))))`; + + +(*val checked_mem_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (addr : xlenbits) (width : int) (data : 'int8_times_n bits)= + (if ((within_mmio_writable addr width)) then mmio_write addr width data + else if ((within_phys_mem addr width)) then phys_mem_write addr width data + else sail2_state_monad$returnS (MemException E_SAMO_Access_Fault)))`; + + +(*val MEMval : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +val _ = Define ` + ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width data= (checked_mem_write addr width data))`; + + +(*val mem_write_value : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +val _ = Define ` + ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->((((unit)MemoryOpResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) addr width value aq rl con= + (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then + sail2_state_monad$returnS (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (F, F, F) => checked_mem_write addr width value + | (F, T, F) => MEMval_release addr width value + | (F, F, T) => MEMval_conditional addr width value + | (F, T, T) => MEMval_conditional_release addr width value + | (T, F, F) => sail2_state_monad$throwS (Error_not_implemented "store.aq") + | (T, T, F) => MEMval_strong_release addr width value + | (T, F, T) => sail2_state_monad$throwS (Error_not_implemented "sc.aq") + | (T, T, T) => MEMval_conditional_strong_release addr width value + )))`; val _ = Define ` ((PAGESIZE_BITS:int)= ((( 12 : int):ii)))`; -(*val _get_PTE_Bits : PTE_Bits -> mword ty8*) +(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*) val _ = Define ` - ((get_PTE_Bits:PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))= v)`; + ((Mk_PTE_Bits:(8)words$word -> PTE_Bits) v= + (<| PTE_Bits_PTE_Bits_chunk_0 := ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) |>))`; -(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) +(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*) val _ = Define ` - ((set_PTE_Bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_PTE_Bits v) in - state_monad$write_regS r_ref r)))`; + ((get_PTE_Bits_bits:PTE_Bits ->(8)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + + +(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) + +val _ = Define ` + ((set_PTE_Bits_bits:((regstate),(register_value),(PTE_Bits))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + +(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*) val _ = Define ` - ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_bits:PTE_Bits ->(8)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 7 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_D:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):ii) (( 7 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_D:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_D:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 7 : int):ii) (( 7 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 6 : int):ii) (( 6 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_A:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):ii) (( 6 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_A:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_A:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 6 : int):ii) (( 6 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 5 : int):ii) (( 5 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_G:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):ii) (( 5 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_G:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_G:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 5 : int):ii) (( 5 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 4 : int):ii) (( 4 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_U:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):ii) (( 4 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_U:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_U:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 4 : int):ii) (( 4 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 3 : int):ii) (( 3 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_X:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):ii) (( 3 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_X:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_X:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 3 : int):ii) (( 3 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 2 : int):ii) (( 2 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_W:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):ii) (( 2 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_W:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_W:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 2 : int):ii) (( 2 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 1 : int):ii) (( 1 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_R:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):ii) (( 1 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_R:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))= ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; + ((update_PTE_Bits_R:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 1 : int):ii) (( 1 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; val _ = Define ` - ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : PTE_Bits) . - let r = ((get_PTE_Bits w__0 : 8 words$word)) in - let r = ((update_subrange_vec_dec r (( 0 : int):ii) (( 0 : int):ii) v : 8 words$word)) in - state_monad$write_regS r_ref (Mk_PTE_Bits r))))`; + ((get_PTE_Bits_V:PTE_Bits ->(1)words$word) v= ((subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)))`; val _ = Define ` - ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) (Mk_PTE_Bits (v)) x= - (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) x : 8 words$word))))`; + ((set_PTE_Bits_V:((regstate),(register_value),(PTE_Bits))register_ref ->(1)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec r.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_PTE_Bits_V:PTE_Bits ->(1)words$word -> PTE_Bits) v x= + ((v with<| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec v.PTE_Bits_PTE_Bits_chunk_0 (( 0 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) + : 8 words$word))|>)))`; (*val isPTEPtr : mword ty8 -> bool*) @@ -4663,25 +8808,25 @@ val _ = Define ` (*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*) val _ = Define ` - ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : + ((checkPTEPermission:AccessType -> Privilege -> bool -> bool -> PTE_Bits ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits)= ((case (ac, priv) of (Read, User) => - state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) | (Write, User) => - state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) | (ReadWrite, User) => - state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) | (Execute, User) => - state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) | (Read, Supervisor) => - state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) + sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr))))))))) | (Write, Supervisor) => - state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ (((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) | (ReadWrite, Supervisor) => - state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) + sail2_state_monad$returnS (((((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) \/ do_sum))) /\ ((((((((get_PTE_Bits_W p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ ((((((((get_PTE_Bits_R p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) /\ mxr)))))))))))) | (Execute, Supervisor) => - state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) + sail2_state_monad$returnS ((((((((get_PTE_Bits_U p : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) /\ (((((get_PTE_Bits_X p : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))))) | (_, Machine) => internal_error "m-mode mem perm check" )))`; @@ -4691,7 +8836,7 @@ val _ = Define ` val _ = Define ` ((update_PTE_Bits:PTE_Bits -> AccessType ->(PTE_Bits)option) (p : PTE_Bits) (a : AccessType)= (let update_d = - (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in + (((((((((accessType_to_str a)) = ((accessType_to_str Write))))) \/ (((((accessType_to_str a)) = ((accessType_to_str ReadWrite)))))))) /\ (((((get_PTE_Bits_D p : 1 words$word)) = ((bool_to_bits F : 1 words$word)))))) in let update_a = (((get_PTE_Bits_A p : 1 words$word)) = ((bool_to_bits F : 1 words$word))) in if (((update_d \/ update_a))) then let np = (update_PTE_Bits_A p ((bool_to_bits T : 1 words$word))) in @@ -4704,11 +8849,11 @@ val _ = Define ` val _ = Define ` ((PTW_Error_of_num:int -> PTW_Error) arg_= - (let l__0 = arg_ in - if (((l__0 = (( 0 : int):ii)))) then PTW_Access - else if (((l__0 = (( 1 : int):ii)))) then PTW_Invalid_PTE - else if (((l__0 = (( 2 : int):ii)))) then PTW_No_Permission - else if (((l__0 = (( 3 : int):ii)))) then PTW_Misaligned + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then PTW_Access + else if (((p0_ = (( 1 : int):ii)))) then PTW_Invalid_PTE + else if (((p0_ = (( 2 : int):ii)))) then PTW_No_Permission + else if (((p0_ = (( 3 : int):ii)))) then PTW_Misaligned else PTW_PTE_Update))`; @@ -4725,18 +8870,42 @@ val _ = Define ` )))`; +(*val ptw_error_to_str : PTW_Error -> string*) + +val _ = Define ` + ((ptw_error_to_str:PTW_Error -> string) e= + ((case e of + PTW_Access => "mem-access-error" + | PTW_Invalid_PTE => "invalid-pte" + | PTW_No_Permission => "no-permission" + | PTW_Misaligned => "misaligned-superpage" + | PTW_PTE_Update => "pte-update-needed" + )))`; + + (*val translationException : AccessType -> PTW_Error -> ExceptionType*) val _ = Define ` - ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)= - ((case (a, f) of - (Read, PTW_Access) => E_Load_Access_Fault + ((translationException:AccessType -> PTW_Error -> ExceptionType) (a : AccessType) (f : PTW_Error)= + (let (e : ExceptionType) = + ((case (a, f) of + (ReadWrite, PTW_Access) => E_SAMO_Access_Fault + | (ReadWrite, _) => E_SAMO_Page_Fault + | (Read, PTW_Access) => E_Load_Access_Fault | (Read, _) => E_Load_Page_Fault | (Write, PTW_Access) => E_SAMO_Access_Fault | (Write, _) => E_SAMO_Page_Fault | (Fetch, PTW_Access) => E_Fetch_Access_Fault | (Fetch, _) => E_Fetch_Page_Fault - )))`; + )) in + let (_ : unit) = + (print_endline + ((STRCAT "translationException(" + ((STRCAT ((accessType_to_str a)) + ((STRCAT ", " + ((STRCAT ((ptw_error_to_str f)) + ((STRCAT ") -> " ((exceptionType_to_str e))))))))))))) in + e))`; val _ = Define ` @@ -4755,65 +8924,107 @@ val _ = Define ` ((PTE39_SIZE:int)= ((( 8 : int):ii)))`; -(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*) +(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*) + +val _ = Define ` + ((Mk_SV39_Vaddr:(39)words$word -> SV39_Vaddr) v= + (<| SV39_Vaddr_SV39_Vaddr_chunk_0 := ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) |>))`; + + +(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*) + +val _ = Define ` + ((get_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word) v= + ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)))`; + + +(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) val _ = Define ` - ((get_SV39_Vaddr:SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))= v)`; + ((set_SV39_Vaddr_bits:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) + : 39 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; -(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) +(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*) val _ = Define ` - ((set_SV39_Vaddr:((regstate),(register_value),(SV39_Vaddr))register_ref ->(39)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_SV39_Vaddr v) in - state_monad$write_regS r_ref r)))`; + ((update_SV39_Vaddr_bits:SV39_Vaddr ->(39)words$word -> SV39_Vaddr) v x= + ((v with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 38 : int):ii) (( 0 : int):ii) : 39 words$word)) + : 39 words$word))|>)))`; (*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*) val _ = Define ` - ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`; + ((get_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word) v= + ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) : 27 words$word)))`; (*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*) val _ = Define ` - ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . - let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in - let r = ((update_subrange_vec_dec r (( 38 : int):ii) (( 12 : int):ii) v : 39 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`; + ((set_SV39_Vaddr_VPNi:((regstate),(register_value),(SV39_Vaddr))register_ref ->(27)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec v (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 39 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*) val _ = Define ` - ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= - (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):ii) (( 12 : int):ii) x : 39 words$word))))`; + ((update_SV39_Vaddr_VPNi:SV39_Vaddr ->(27)words$word -> SV39_Vaddr) v x= + ((v with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 38 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec x (( 26 : int):ii) (( 0 : int):ii) : 27 words$word)) + : 39 words$word))|>)))`; (*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*) val _ = Define ` - ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; + ((get_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word) v= + ((subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; (*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*) val _ = Define ` - ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_Vaddr) . - let r = ((get_SV39_Vaddr w__0 : 39 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v : 39 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_Vaddr r))))`; + ((set_SV39_Vaddr_PgOfs:((regstate),(register_value),(SV39_Vaddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)) + : 39 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*) val _ = Define ` - ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) (Mk_SV39_Vaddr (v)) x= - (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x : 39 words$word))))`; + ((update_SV39_Vaddr_PgOfs:SV39_Vaddr ->(12)words$word -> SV39_Vaddr) v x= + ((v with<| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Vaddr_SV39_Vaddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)) + : 39 words$word))|>)))`; (*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*) @@ -4822,42 +9033,75 @@ val _ = Define ` (*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*) -(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*) +(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*) val _ = Define ` - ((get_SV39_Paddr:SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))= v)`; + ((Mk_SV39_Paddr:(56)words$word -> SV39_Paddr) v= + (<| SV39_Paddr_SV39_Paddr_chunk_0 := ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) |>))`; -(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) +(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*) val _ = Define ` - ((set_SV39_Paddr:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_SV39_Paddr v) in - state_monad$write_regS r_ref r)))`; + ((get_SV39_Paddr_bits:SV39_Paddr ->(56)words$word) v= + ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)))`; + + +(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) + +val _ = Define ` + ((set_SV39_Paddr_bits:((regstate),(register_value),(SV39_Paddr))register_ref ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + : 56 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*) + +val _ = Define ` + ((update_SV39_Paddr_bits:SV39_Paddr ->(56)words$word -> SV39_Paddr) v x= + ((v with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 55 : int):ii) (( 0 : int):ii) : 56 words$word)) + : 56 words$word))|>)))`; (*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*) val _ = Define ` - ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`; + ((get_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word) v= + ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) : 44 words$word)))`; (*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*) val _ = Define ` - ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . - let r = ((get_SV39_Paddr w__0 : 56 words$word)) in - let r = ((update_subrange_vec_dec r (( 55 : int):ii) (( 12 : int):ii) v : 56 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`; + ((set_SV39_Paddr_PPNi:((regstate),(register_value),(SV39_Paddr))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 56 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*) val _ = Define ` - ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x= - (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):ii) (( 12 : int):ii) x : 56 words$word))))`; + ((update_SV39_Paddr_PPNi:SV39_Paddr ->(44)words$word -> SV39_Paddr) v x= + ((v with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 55 : int):ii) (( 12 : int):ii) + ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 56 words$word))|>)))`; (*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*) @@ -4867,112 +9111,168 @@ val _ = Define ` (*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*) val _ = Define ` - ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))= ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; + ((get_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word) v= + ((subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)))`; val _ = Define ` - ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_Paddr) . - let r = ((get_SV39_Paddr w__0 : 56 words$word)) in - let r = ((update_subrange_vec_dec r (( 11 : int):ii) (( 0 : int):ii) v : 56 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_Paddr r))))`; + ((set_SV39_Paddr_PgOfs:((regstate),(register_value),(SV39_Paddr))register_ref ->(12)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec r.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)) + : 56 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) (Mk_SV39_Paddr (v)) x= - (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):ii) (( 0 : int):ii) x : 56 words$word))))`; + ((update_SV39_Paddr_PgOfs:SV39_Paddr ->(12)words$word -> SV39_Paddr) v x= + ((v with<| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec v.SV39_Paddr_SV39_Paddr_chunk_0 (( 11 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 11 : int):ii) (( 0 : int):ii) : 12 words$word)) + : 56 words$word))|>)))`; + +(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*) val _ = Define ` - ((get_SV39_PTE:SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))= v)`; + ((Mk_SV39_PTE:(64)words$word -> SV39_PTE) v= + (<| SV39_PTE_SV39_PTE_chunk_0 := ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) |>))`; val _ = Define ` - ((set_SV39_PTE:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ r . - let r = (Mk_SV39_PTE v) in - state_monad$write_regS r_ref r)))`; + ((get_SV39_PTE_bits:SV39_PTE ->(64)words$word) v= + ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)))`; val _ = Define ` - ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`; + ((set_SV39_PTE_bits:((regstate),(register_value),(SV39_PTE))register_ref ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; val _ = Define ` - ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 53 : int):ii) (( 10 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + ((update_SV39_PTE_bits:SV39_PTE ->(64)words$word -> SV39_PTE) v x= + ((v with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 63 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) + : 64 words$word))|>)))`; val _ = Define ` - ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):ii) (( 10 : int):ii) x : 64 words$word))))`; + ((get_SV39_PTE_PPNi:SV39_PTE ->(44)words$word) v= + ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) : 44 words$word)))`; + + +val _ = Define ` + ((set_SV39_PTE_PPNi:((regstate),(register_value),(SV39_PTE))register_ref ->(44)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec v (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; + + +val _ = Define ` + ((update_SV39_PTE_PPNi:SV39_PTE ->(44)words$word -> SV39_PTE) v x= + ((v with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 53 : int):ii) (( 10 : int):ii) + ((subrange_vec_dec x (( 43 : int):ii) (( 0 : int):ii) : 44 words$word)) + : 64 words$word))|>)))`; (*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*) val _ = Define ` - ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`; + ((get_SV39_PTE_RSW:SV39_PTE ->(2)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) : 2 words$word)))`; (*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*) val _ = Define ` - ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 9 : int):ii) (( 8 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + ((set_SV39_PTE_RSW:((regstate),(register_value),(SV39_PTE))register_ref ->(2)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec v (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*) val _ = Define ` - ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):ii) (( 8 : int):ii) x : 64 words$word))))`; + ((update_SV39_PTE_RSW:SV39_PTE ->(2)words$word -> SV39_PTE) v x= + ((v with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 9 : int):ii) (( 8 : int):ii) + ((subrange_vec_dec x (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) + : 64 words$word))|>)))`; (*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*) val _ = Define ` - ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))= ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; + ((get_SV39_PTE_BITS:SV39_PTE ->(8)words$word) v= ((subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)))`; (*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*) val _ = Define ` - ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) r_ref v= (state_monad$bindS - (state_monad$read_regS r_ref) (\ (w__0 : SV39_PTE) . - let r = ((get_SV39_PTE w__0 : 64 words$word)) in - let r = ((update_subrange_vec_dec r (( 7 : int):ii) (( 0 : int):ii) v : 64 words$word)) in - state_monad$write_regS r_ref (Mk_SV39_PTE r))))`; + ((set_SV39_PTE_BITS:((regstate),(register_value),(SV39_PTE))register_ref ->(8)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) r_ref v= (sail2_state_monad$bindS + (sail2_state_monad$read_regS r_ref) (\ r . + let r = + ((r with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec r.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)) in + sail2_state_monad$write_regS r_ref r)))`; (*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*) val _ = Define ` - ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) (Mk_SV39_PTE (v)) x= - (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):ii) (( 0 : int):ii) x : 64 words$word))))`; + ((update_SV39_PTE_BITS:SV39_PTE ->(8)words$word -> SV39_PTE) v x= + ((v with<| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec v.SV39_PTE_SV39_PTE_chunk_0 (( 7 : int):ii) (( 0 : int):ii) + ((subrange_vec_dec x (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) + : 64 words$word))|>)))`; (*val curAsid64 : unit -> M (mword ty16)*) val _ = Define ` - ((curAsid64:unit ->(regstate)state_monad$sequential_state ->((((16)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + ((curAsid64:unit ->(regstate)sail2_state_monad$sequential_state ->((((16)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let satp64 = (Mk_Satp64 w__0) in - state_monad$returnS ((get_Satp64_Asid satp64 : 16 words$word)))))`; + sail2_state_monad$returnS ((get_Satp64_Asid satp64 : 16 words$word)))))`; (*val curPTB39 : unit -> M (mword ty56)*) val _ = Define ` - ((curPTB39:unit ->(regstate)state_monad$sequential_state ->((((56)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + ((curPTB39:unit ->(regstate)sail2_state_monad$sequential_state ->((((56)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let satp64 = (Mk_Satp64 w__0) in - state_monad$returnS ((EXTZ (( 56 : int):ii) + sail2_state_monad$returnS ((EXTZ (( 56 : int):ii) ((shiftl ((get_Satp64_PPN satp64 : 44 words$word)) PAGESIZE_BITS : 44 words$word)) : 56 words$word)))))`; @@ -4980,7 +9280,7 @@ val _ = Define ` (*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*) val walk39_defn = Hol_defn "walk39" ` - ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((PTW_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global= + ((walk39:(39)words$word -> AccessType -> Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((PTW_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vaddr ac priv mxr do_sum ptb level global= (let va = (Mk_SV39_Vaddr vaddr) in let (pt_ofs : paddr39) = ((shiftl @@ -4992,28 +9292,42 @@ val _ = Define ` : 9 words$word)) : 56 words$word)) PTE39_LOG_SIZE : 56 words$word)) in - let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in state_monad$bindS - (checked_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr : 64 words$word)) (( 8 : int):ii) + let pte_addr = ((add_vec ptb pt_ofs : 56 words$word)) in sail2_state_monad$bindS + (phys_mem_read Data ((EXTZ (( 64 : int):ii) pte_addr : 64 words$word)) (( 8 : int):ii) F F F : ( ( 64 words$word)MemoryOpResult) M) (\ (w__0 : ( 64 words$word) MemoryOpResult) . (case w__0 of - MemException (_) => state_monad$returnS (PTW_Failure PTW_Access) + MemException (_) => + let (_ : unit) = + (print_endline + ((STRCAT "walk39(vaddr=" + ((STRCAT ((string_of_bits vaddr)) + ((STRCAT " level=" + ((STRCAT ((stringFromInteger level)) + ((STRCAT " pt_base=" + ((STRCAT ((string_of_bits ptb)) + ((STRCAT " pt_ofs=" + ((STRCAT ((string_of_bits pt_ofs)) + ((STRCAT " pte_addr=" + ((STRCAT ((string_of_bits pte_addr)) + ": invalid pte address"))))))))))))))))))))) in + sail2_state_monad$returnS (PTW_Failure PTW_Access) | MemValue (v) => let pte = (Mk_SV39_PTE v) in let pbits = ((get_SV39_PTE_BITS pte : 8 words$word)) in let pattr = (Mk_PTE_Bits pbits) in let is_global = (global \/ (((((get_PTE_Bits_G pattr : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) in - if ((isInvalidPTE pbits)) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE) + if ((isInvalidPTE pbits)) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE) else if ((isPTEPtr pbits)) then - if (((level = (( 0 : int):ii)))) then state_monad$returnS (PTW_Failure PTW_Invalid_PTE) + if (((level = (( 0 : int):ii)))) then sail2_state_monad$returnS (PTW_Failure PTW_Invalid_PTE) else walk39 vaddr ac priv mxr do_sum ((EXTZ (( 56 : int):ii) ((shiftl ((get_SV39_PTE_PPNi pte : 44 words$word)) PAGESIZE_BITS : 44 words$word)) : 56 words$word)) ((level - (( 1 : int):ii))) is_global - else state_monad$bindS + else sail2_state_monad$bindS (checkPTEPermission ac priv mxr do_sum pattr) (\ (w__3 : bool) . - state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission + sail2_state_monad$returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission else if ((level > (( 0 : int):ii))) then let mask = ((sub_vec_int @@ -5048,7 +9362,7 @@ val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn (*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*) val _ = Define ` - ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> SV39_PTE -> int ->(56)words$word ->(regstate)state_monad$sequential_state ->(((TLB39_Entry),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr= + ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> SV39_PTE -> int ->(56)words$word ->(regstate)sail2_state_monad$sequential_state ->(((TLB39_Entry),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr= (let (shift : ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in let (vAddrMask : vaddr39) = ((sub_vec_int @@ -5059,9 +9373,9 @@ val _ = Define ` : 39 words$word)) shift : 39 words$word)) (( 1 : int):ii) : 39 words$word)) in - let (vMatchMask : vaddr39) = ((not_vec vAddrMask : 39 words$word)) in state_monad$bindS - (state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . - state_monad$returnS (<| TLB39_Entry_asid := asid; + let (vMatchMask : vaddr39) = ((not_vec vAddrMask : 39 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + sail2_state_monad$returnS (<| TLB39_Entry_asid := asid; TLB39_Entry_global := global; TLB39_Entry_pte := pte; TLB39_Entry_pteAddr := pteAddr; @@ -5080,9 +9394,9 @@ val _ = Define ` (*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*) val _ = Define ` - ((lookupTLB39:(16)words$word ->(39)words$word ->(regstate)state_monad$sequential_state ->((((int#TLB39_Entry)option),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vaddr= (state_monad$bindS - (state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . - state_monad$returnS ((case w__0 of + ((lookupTLB39:(16)words$word ->(39)words$word ->(regstate)sail2_state_monad$sequential_state ->((((int#TLB39_Entry)option),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vaddr= (sail2_state_monad$bindS + (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . + sail2_state_monad$returnS ((case w__0 of NONE => NONE | SOME (e) => if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr : 39 words$word)))))))) @@ -5095,22 +9409,22 @@ val _ = Define ` (*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*) val _ = Define ` - ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (state_monad$bindS + ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> SV39_PTE ->(56)words$word -> int -> bool ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global= (sail2_state_monad$bindS (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . - state_monad$write_regS tlb39_ref (SOME ent))))`; + sail2_state_monad$write_regS tlb39_ref (SOME ent))))`; (*val writeTLB39 : ii -> TLB39_Entry -> M unit*) val _ = Define ` - ((writeTLB39:int -> TLB39_Entry ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)= (state_monad$write_regS tlb39_ref (SOME ent)))`; + ((writeTLB39:int -> TLB39_Entry ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (idx : ii) (ent : TLB39_Entry)= (sail2_state_monad$write_regS tlb39_ref (SOME ent)))`; (*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*) val _ = Define ` - ((flushTLB:((16)words$word)option ->((39)words$word)option ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) asid addr= (state_monad$bindS - (state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . + ((flushTLB:((16)words$word)option ->((39)words$word)option ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) asid addr= (sail2_state_monad$bindS + (sail2_state_monad$read_regS tlb39_ref) (\ (w__0 : TLB39_Entry option) . let (ent : TLB39_Entry option) = ((case (w__0, asid, addr) of (NONE, _, _) => NONE @@ -5127,75 +9441,72 @@ val _ = Define ` NONE else SOME e )) in - state_monad$write_regS tlb39_ref ent)))`; - - -val _ = Define ` - ((enable_dirty_update:bool)= F)`; + sail2_state_monad$write_regS tlb39_ref ent)))`; (*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*) val _ = Define ` - ((translate39:(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)state_monad$sequential_state ->(((TR39_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac priv mxr do_sum level= (state_monad$bindS - (curAsid64 () : ( 16 words$word) M) (\ asid . state_monad$bindS + ((translate39:(39)words$word -> AccessType -> Privilege -> bool -> bool -> int ->(regstate)sail2_state_monad$sequential_state ->(((TR39_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac priv mxr do_sum level= (sail2_state_monad$bindS + (curAsid64 () : ( 16 words$word) M) (\ asid . sail2_state_monad$bindS (lookupTLB39 asid vAddr) (\ (w__0 : ((ii # TLB39_Entry))option) . (case w__0 of SOME (idx,ent) => - let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte : 8 words$word))) in state_monad$bindS + let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte : 8 words$word))) in sail2_state_monad$bindS (checkPTEPermission ac priv mxr do_sum pteBits) (\ (w__1 : bool) . - if ((~ w__1)) then state_monad$returnS (TR39_Failure PTW_No_Permission) + if ((~ w__1)) then sail2_state_monad$returnS (TR39_Failure PTW_No_Permission) else (case ((update_PTE_Bits pteBits ac)) of NONE => - state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + sail2_state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr ((EXTZ (( 56 : int):ii) ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) : 56 words$word)) : 56 words$word))) | SOME (pbits) => - if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update) + if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR39_Failure PTW_PTE_Update) else let (n_ent : TLB39_Entry) = ent in let n_ent = ((n_ent with<| TLB39_Entry_pte := - ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits : 8 words$word))))|>)) in state_monad$bindS (state_monad$seqS + ((update_SV39_PTE_BITS ent.TLB39_Entry_pte + ((get_PTE_Bits_bits pbits : 8 words$word))))|>)) in sail2_state_monad$bindS (sail2_state_monad$seqS (writeTLB39 idx n_ent) (checked_mem_write ((EXTZ (( 64 : int):ii) ent.TLB39_Entry_pteAddr : 64 words$word)) (( 8 : int):ii) - ((get_SV39_PTE ent.TLB39_Entry_pte : 64 words$word)))) (\ (w__2 : unit - MemoryOpResult) . state_monad$seqS + ((get_SV39_PTE_bits ent.TLB39_Entry_pte : 64 words$word)))) (\ (w__2 : unit + MemoryOpResult) . sail2_state_monad$seqS (case w__2 of - MemValue (_) => state_monad$returnS () + MemValue (_) => sail2_state_monad$returnS () | MemException (e) => internal_error "invalid physical address in TLB" ) - (state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr + (sail2_state_monad$returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr ((EXTZ (( 56 : int):ii) ((and_vec vAddr ent.TLB39_Entry_vAddrMask : 39 words$word)) : 56 words$word)) : 56 words$word))))) )) - | NONE => state_monad$bindS - (curPTB39 () : ( 56 words$word) M) (\ (w__6 : 56 words$word) . state_monad$bindS + | NONE => sail2_state_monad$bindS + (curPTB39 () : ( 56 words$word) M) (\ (w__6 : 56 words$word) . sail2_state_monad$bindS (walk39 vAddr ac priv mxr do_sum w__6 level F) (\ (w__7 : PTW_Result) . (case w__7 of - PTW_Failure (f) => state_monad$returnS (TR39_Failure f) + PTW_Failure (f) => sail2_state_monad$returnS (TR39_Failure f) | PTW_Success (pAddr,pte,pteAddr,level,global) => - (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word))) ac)) of - NONE => state_monad$seqS - (addToTLB39 asid vAddr pAddr pte pteAddr level global) (state_monad$returnS (TR39_Address pAddr)) + (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte : 8 words$word)))) ac)) of + NONE => sail2_state_monad$seqS + (addToTLB39 asid vAddr pAddr pte pteAddr level global) (sail2_state_monad$returnS (TR39_Address pAddr)) | SOME (pbits) => - if ((~ enable_dirty_update)) then state_monad$returnS (TR39_Failure PTW_PTE_Update) + if ((~ ((plat_enable_dirty_update () )))) then sail2_state_monad$returnS (TR39_Failure PTW_PTE_Update) else let (w_pte : SV39_PTE) = - (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits : 8 words$word))) in state_monad$bindS + (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits : 8 words$word))) in sail2_state_monad$bindS (checked_mem_write ((EXTZ (( 64 : int):ii) pteAddr : 64 words$word)) (( 8 : int):ii) - ((get_SV39_PTE w_pte : 64 words$word))) (\ (w__8 : unit MemoryOpResult) . + ((get_SV39_PTE_bits w_pte : 64 words$word))) (\ (w__8 : unit MemoryOpResult) . (case w__8 of - MemValue (_) => state_monad$seqS + MemValue (_) => sail2_state_monad$seqS (addToTLB39 asid vAddr pAddr w_pte pteAddr level global) - (state_monad$returnS (TR39_Address pAddr)) - | MemException (e) => state_monad$returnS (TR39_Failure PTW_Access) + (sail2_state_monad$returnS (TR39_Address pAddr)) + | MemException (e) => sail2_state_monad$returnS (TR39_Failure PTW_Access) )) ) ))) @@ -5205,19 +9516,19 @@ val _ = Define ` (*val translationMode : Privilege -> M SATPMode*) val _ = Define ` - ((translationMode:Privilege ->(regstate)state_monad$sequential_state ->(((SATPMode),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) priv= + ((translationMode:Privilege ->(regstate)sail2_state_monad$sequential_state ->(((SATPMode),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) priv= (if (((((privLevel_to_bits priv : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) then - state_monad$returnS Sbare - else state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . + sail2_state_monad$returnS Sbare + else sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . let arch = (architecture ((get_Mstatus_SXL w__0 : 2 words$word))) in (case arch of - SOME (RV64) => state_monad$bindS - (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . - let (mbits : satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) : 4 words$word)) in + SOME (RV64) => sail2_state_monad$bindS + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (mbits : satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1)) : 4 words$word)) in (case ((satpMode_of_bits RV64 mbits)) of - SOME (m) => state_monad$returnS m + SOME (m) => sail2_state_monad$returnS m | NONE => internal_error "invalid RV64 translation mode in satp" )) | _ => internal_error "unsupported address translation arch" @@ -5227,32 +9538,32 @@ val _ = Define ` (*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*) val _ = Define ` - ((translateAddr:(64)words$word -> AccessType -> ReadType ->(regstate)state_monad$sequential_state ->(((TR_Result),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) vAddr ac rt= (state_monad$bindS + ((translateAddr:(64)words$word -> AccessType -> ReadType ->(regstate)sail2_state_monad$sequential_state ->(((TR_Result),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) vAddr ac rt= (sail2_state_monad$bindS (case rt of - Instruction => state_monad$read_regS cur_privilege_ref - | Data => state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . - if (((((get_Mstatus_MPRV w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . - state_monad$returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) - else state_monad$read_regS cur_privilege_ref) - ) (\ (effPriv : Privilege) . state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . + Instruction => sail2_state_monad$read_regS cur_privilege_ref + | Data => sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + if (((((get_Mstatus_MPRV w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + sail2_state_monad$returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2 : 2 words$word))))) + else sail2_state_monad$read_regS cur_privilege_ref) + ) (\ (effPriv : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__5 : Mstatus) . let (mxr : bool) = - (((get_Mstatus_MXR w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) . + (((get_Mstatus_MXR w__5 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__6 : Mstatus) . let (do_sum : bool) = - (((get_Mstatus_SUM w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in state_monad$bindS + (((get_Mstatus_SUM w__6 : 1 words$word)) = ((bool_to_bits T : 1 words$word))) in sail2_state_monad$bindS (translationMode effPriv) (\ (mode : SATPMode) . (case mode of - Sbare => state_monad$returnS (TR_Address vAddr) - | SV39 => state_monad$bindS + Sbare => sail2_state_monad$returnS (TR_Address vAddr) + | SV39 => sail2_state_monad$bindS (translate39 ((subrange_vec_dec vAddr (( 38 : int): ii) (( 0 : int): ii) : 39 words$word)) ac effPriv mxr do_sum ((SV39_LEVELS - (( 1 : int): ii)))) (\ (w__7 : TR39_Result) . - state_monad$returnS + sail2_state_monad$returnS ((case w__7 of TR39_Address (pa) => TR_Address ((EXTZ (( 64 : int): ii) pa : 64 words$word)) @@ -5266,10 +9577,666 @@ val _ = Define ` (*val decodeCompressed : mword ty16 -> maybe ast*) -(*val execute : ast -> M unit*) +(*val execute : ast -> M bool*) (*val print_insn : ast -> string*) +(*val encdec_uop_forwards : uop -> mword ty7*) + +val _ = Define ` + ((encdec_uop_forwards:uop ->(7)words$word) arg_= + ((case arg_ of + RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word) + | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word) + )))`; + + +(*val encdec_uop_backwards : mword ty7 -> uop*) + +val _ = Define ` + ((encdec_uop_backwards:(7)words$word -> uop) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then RISCV_LUI + else RISCV_AUIPC))`; + + +(*val encdec_uop_forwards_matches : uop -> bool*) + +val _ = Define ` + ((encdec_uop_forwards_matches:uop -> bool) arg_= + ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`; + + +(*val encdec_uop_backwards_matches : mword ty7 -> bool*) + +val _ = Define ` + ((encdec_uop_backwards_matches:(7)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then T + else F))`; + + +(*val utype_mnemonic_forwards : uop -> string*) + +val _ = Define ` + ((utype_mnemonic_forwards:uop -> string) arg_= ((case arg_ of RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" )))`; + + +(*val utype_mnemonic_backwards : string -> uop*) + +val _ = Define ` + ((utype_mnemonic_backwards:string -> uop) arg_= + ((case arg_ of "lui" => RISCV_LUI | "auipc" => RISCV_AUIPC )))`; + + +(*val utype_mnemonic_forwards_matches : uop -> bool*) + +val _ = Define ` + ((utype_mnemonic_forwards_matches:uop -> bool) arg_= + ((case arg_ of RISCV_LUI => T | RISCV_AUIPC => T )))`; + + +(*val utype_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((utype_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of "lui" => T | "auipc" => T | _ => F )))`; + + +(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*) + +val _ = Define ` + ((utype_mnemonic_matches_prefix:string ->(uop#int)option) arg_= + (let stringappend_1714_0 = arg_ in + if (((((string_startswith stringappend_1714_0 "lui")) /\ ( + (case ((string_drop stringappend_1714_0 ((string_length "lui")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1714_0 ((string_length "lui")))) of + s_ => SOME (RISCV_LUI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1714_0 "auipc")) /\ ( + (case ((string_drop stringappend_1714_0 ((string_length "auipc")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1714_0 ((string_length "auipc")))) of + s_ => SOME (RISCV_AUIPC, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val encdec_bop_forwards : bop -> mword ty3*) + +val _ = Define ` + ((encdec_bop_forwards:bop ->(3)words$word) arg_= + ((case arg_ of + RISCV_BEQ => (vec_of_bits [B0;B0;B0] : 3 words$word) + | RISCV_BNE => (vec_of_bits [B0;B0;B1] : 3 words$word) + | RISCV_BLT => (vec_of_bits [B1;B0;B0] : 3 words$word) + | RISCV_BGE => (vec_of_bits [B1;B0;B1] : 3 words$word) + | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : 3 words$word) + | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : 3 words$word) + )))`; + + +(*val encdec_bop_backwards : mword ty3 -> bop*) + +val _ = Define ` + ((encdec_bop_backwards:(3)words$word -> bop) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then RISCV_BEQ + else if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then RISCV_BNE + else if (((p0_ = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then RISCV_BLT + else if (((p0_ = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then RISCV_BGE + else if (((p0_ = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then RISCV_BLTU + else RISCV_BGEU))`; + + +(*val encdec_bop_forwards_matches : bop -> bool*) + +val _ = Define ` + ((encdec_bop_forwards_matches:bop -> bool) arg_= + ((case arg_ of + RISCV_BEQ => T + | RISCV_BNE => T + | RISCV_BLT => T + | RISCV_BGE => T + | RISCV_BLTU => T + | RISCV_BGEU => T + )))`; + + +(*val encdec_bop_backwards_matches : mword ty3 -> bool*) + +val _ = Define ` + ((encdec_bop_backwards_matches:(3)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T + else F))`; + + +(*val btype_mnemonic_forwards : bop -> string*) + +val _ = Define ` + ((btype_mnemonic_forwards:bop -> string) arg_= + ((case arg_ of + RISCV_BEQ => "beq" + | RISCV_BNE => "bne" + | RISCV_BLT => "blt" + | RISCV_BGE => "bge" + | RISCV_BLTU => "bltu" + | RISCV_BGEU => "bgeu" + )))`; + + +(*val btype_mnemonic_backwards : string -> bop*) + +val _ = Define ` + ((btype_mnemonic_backwards:string -> bop) arg_= + ((case arg_ of + "beq" => RISCV_BEQ + | "bne" => RISCV_BNE + | "blt" => RISCV_BLT + | "bge" => RISCV_BGE + | "bltu" => RISCV_BLTU + | "bgeu" => RISCV_BGEU + )))`; + + +(*val btype_mnemonic_forwards_matches : bop -> bool*) + +val _ = Define ` + ((btype_mnemonic_forwards_matches:bop -> bool) arg_= + ((case arg_ of + RISCV_BEQ => T + | RISCV_BNE => T + | RISCV_BLT => T + | RISCV_BGE => T + | RISCV_BLTU => T + | RISCV_BGEU => T + )))`; + + +(*val btype_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((btype_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "beq" => T + | "bne" => T + | "blt" => T + | "bge" => T + | "bltu" => T + | "bgeu" => T + | _ => F + )))`; + + +(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*) + +val _ = Define ` + ((btype_mnemonic_matches_prefix:string ->(bop#int)option) arg_= + (let stringappend_1708_0 = arg_ in + if (((((string_startswith stringappend_1708_0 "beq")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "beq")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "beq")))) of + s_ => SOME (RISCV_BEQ, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1708_0 "bne")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "bne")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "bne")))) of + s_ => SOME (RISCV_BNE, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1708_0 "blt")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "blt")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "blt")))) of + s_ => SOME (RISCV_BLT, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1708_0 "bge")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "bge")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "bge")))) of + s_ => SOME (RISCV_BGE, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1708_0 "bltu")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "bltu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "bltu")))) of + s_ => SOME (RISCV_BLTU, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1708_0 "bgeu")) /\ ( + (case ((string_drop stringappend_1708_0 ((string_length "bgeu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1708_0 ((string_length "bgeu")))) of + s_ => SOME (RISCV_BGEU, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val encdec_iop_forwards : iop -> mword ty3*) + +val _ = Define ` + ((encdec_iop_forwards:iop ->(3)words$word) arg_= + ((case arg_ of + RISCV_ADDI => (vec_of_bits [B0;B0;B0] : 3 words$word) + | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : 3 words$word) + | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : 3 words$word) + | RISCV_XORI => (vec_of_bits [B1;B0;B0] : 3 words$word) + | RISCV_ORI => (vec_of_bits [B1;B1;B0] : 3 words$word) + | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : 3 words$word) + )))`; + + +(*val encdec_iop_backwards : mword ty3 -> iop*) + +val _ = Define ` + ((encdec_iop_backwards:(3)words$word -> iop) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then RISCV_ADDI + else if (((p0_ = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then RISCV_SLTI + else if (((p0_ = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then RISCV_SLTIU + else if (((p0_ = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then RISCV_XORI + else if (((p0_ = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then RISCV_ORI + else RISCV_ANDI))`; + + +(*val encdec_iop_forwards_matches : iop -> bool*) + +val _ = Define ` + ((encdec_iop_forwards_matches:iop -> bool) arg_= + ((case arg_ of + RISCV_ADDI => T + | RISCV_SLTI => T + | RISCV_SLTIU => T + | RISCV_XORI => T + | RISCV_ORI => T + | RISCV_ANDI => T + )))`; + + +(*val encdec_iop_backwards_matches : mword ty3 -> bool*) + +val _ = Define ` + ((encdec_iop_backwards_matches:(3)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1;B1] : 3 words$word)))) then T + else F))`; + + +(*val itype_mnemonic_forwards : iop -> string*) + +val _ = Define ` + ((itype_mnemonic_forwards:iop -> string) arg_= + ((case arg_ of + RISCV_ADDI => "addi" + | RISCV_SLTI => "slti" + | RISCV_SLTIU => "sltiu" + | RISCV_XORI => "xori" + | RISCV_ORI => "ori" + | RISCV_ANDI => "andi" + )))`; + + +(*val itype_mnemonic_backwards : string -> iop*) + +val _ = Define ` + ((itype_mnemonic_backwards:string -> iop) arg_= + ((case arg_ of + "addi" => RISCV_ADDI + | "slti" => RISCV_SLTI + | "sltiu" => RISCV_SLTIU + | "xori" => RISCV_XORI + | "ori" => RISCV_ORI + | "andi" => RISCV_ANDI + )))`; + + +(*val itype_mnemonic_forwards_matches : iop -> bool*) + +val _ = Define ` + ((itype_mnemonic_forwards_matches:iop -> bool) arg_= + ((case arg_ of + RISCV_ADDI => T + | RISCV_SLTI => T + | RISCV_SLTIU => T + | RISCV_XORI => T + | RISCV_ORI => T + | RISCV_ANDI => T + )))`; + + +(*val itype_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((itype_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "addi" => T + | "slti" => T + | "sltiu" => T + | "xori" => T + | "ori" => T + | "andi" => T + | _ => F + )))`; + + +(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*) + +val _ = Define ` + ((itype_mnemonic_matches_prefix:string ->(iop#int)option) arg_= + (let stringappend_1702_0 = arg_ in + if (((((string_startswith stringappend_1702_0 "addi")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "addi")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "addi")))) of + s_ => SOME (RISCV_ADDI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1702_0 "slti")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "slti")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "slti")))) of + s_ => SOME (RISCV_SLTI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1702_0 "sltiu")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "sltiu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "sltiu")))) of + s_ => SOME (RISCV_SLTIU, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1702_0 "xori")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "xori")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "xori")))) of + s_ => SOME (RISCV_XORI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1702_0 "ori")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "ori")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "ori")))) of + s_ => SOME (RISCV_ORI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1702_0 "andi")) /\ ( + (case ((string_drop stringappend_1702_0 ((string_length "andi")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1702_0 ((string_length "andi")))) of + s_ => SOME (RISCV_ANDI, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val encdec_sop_forwards : sop -> mword ty3*) + +val _ = Define ` + ((encdec_sop_forwards:sop ->(3)words$word) arg_= + ((case arg_ of + RISCV_SLLI => (vec_of_bits [B0;B0;B1] : 3 words$word) + | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : 3 words$word) + | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : 3 words$word) + )))`; + + +(*val encdec_sop_backwards : mword ty3 -> sop*) + +val _ = Define ` + ((encdec_sop_backwards:(3)words$word -> sop) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then RISCV_SLLI + else if (((p0_ = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then RISCV_SRLI + else RISCV_SRAI))`; + + +(*val encdec_sop_forwards_matches : sop -> bool*) + +val _ = Define ` + ((encdec_sop_forwards_matches:sop -> bool) arg_= + ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`; + + +(*val encdec_sop_backwards_matches : mword ty3 -> bool*) + +val _ = Define ` + ((encdec_sop_backwards_matches:(3)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0;B1] : 3 words$word)))) then T + else F))`; + + +(*val shiftiop_mnemonic_forwards : sop -> string*) + +val _ = Define ` + ((shiftiop_mnemonic_forwards:sop -> string) arg_= + ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`; + + +(*val shiftiop_mnemonic_backwards : string -> sop*) + +val _ = Define ` + ((shiftiop_mnemonic_backwards:string -> sop) arg_= + ((case arg_ of "slli" => RISCV_SLLI | "srli" => RISCV_SRLI | "srai" => RISCV_SRAI )))`; + + +(*val shiftiop_mnemonic_forwards_matches : sop -> bool*) + +val _ = Define ` + ((shiftiop_mnemonic_forwards_matches:sop -> bool) arg_= + ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`; + + +(*val shiftiop_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((shiftiop_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of "slli" => T | "srli" => T | "srai" => T | _ => F )))`; + + +(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*) + +val _ = Define ` + ((shiftiop_mnemonic_matches_prefix:string ->(sop#int)option) arg_= + (let stringappend_1699_0 = arg_ in + if (((((string_startswith stringappend_1699_0 "slli")) /\ ( + (case ((string_drop stringappend_1699_0 ((string_length "slli")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1699_0 ((string_length "slli")))) of + s_ => SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1699_0 "srli")) /\ ( + (case ((string_drop stringappend_1699_0 ((string_length "srli")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1699_0 ((string_length "srli")))) of + s_ => SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1699_0 "srai")) /\ ( + (case ((string_drop stringappend_1699_0 ((string_length "srai")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1699_0 ((string_length "srai")))) of + s_ => SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val rtype_mnemonic_forwards : rop -> string*) + +val _ = Define ` + ((rtype_mnemonic_forwards:rop -> string) arg_= + ((case arg_ of + RISCV_ADD => "add" + | RISCV_SUB => "sub" + | RISCV_SLL => "sll" + | RISCV_SLT => "slt" + | RISCV_SLTU => "sltu" + | RISCV_XOR => "xor" + | RISCV_SRL => "srl" + | RISCV_SRA => "sra" + | RISCV_OR => "or" + | RISCV_AND => "and" + )))`; + + +(*val rtype_mnemonic_backwards : string -> rop*) + +val _ = Define ` + ((rtype_mnemonic_backwards:string -> rop) arg_= + ((case arg_ of + "add" => RISCV_ADD + | "sub" => RISCV_SUB + | "sll" => RISCV_SLL + | "slt" => RISCV_SLT + | "sltu" => RISCV_SLTU + | "xor" => RISCV_XOR + | "srl" => RISCV_SRL + | "sra" => RISCV_SRA + | "or" => RISCV_OR + | "and" => RISCV_AND + )))`; + + +(*val rtype_mnemonic_forwards_matches : rop -> bool*) + +val _ = Define ` + ((rtype_mnemonic_forwards_matches:rop -> bool) arg_= + ((case arg_ of + RISCV_ADD => T + | RISCV_SUB => T + | RISCV_SLL => T + | RISCV_SLT => T + | RISCV_SLTU => T + | RISCV_XOR => T + | RISCV_SRL => T + | RISCV_SRA => T + | RISCV_OR => T + | RISCV_AND => T + )))`; + + +(*val rtype_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((rtype_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "add" => T + | "sub" => T + | "sll" => T + | "slt" => T + | "sltu" => T + | "xor" => T + | "srl" => T + | "sra" => T + | "or" => T + | "and" => T + | _ => F + )))`; + + +(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*) + +val _ = Define ` + ((rtype_mnemonic_matches_prefix:string ->(rop#int)option) arg_= + (let stringappend_1689_0 = arg_ in + if (((((string_startswith stringappend_1689_0 "add")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "add")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "add")))) of + s_ => SOME (RISCV_ADD, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "sub")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "sub")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "sub")))) of + s_ => SOME (RISCV_SUB, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "sll")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "sll")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "sll")))) of + s_ => SOME (RISCV_SLL, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "slt")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "slt")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "slt")))) of + s_ => SOME (RISCV_SLT, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "sltu")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "sltu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "sltu")))) of + s_ => SOME (RISCV_SLTU, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "xor")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "xor")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "xor")))) of + s_ => SOME (RISCV_XOR, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "srl")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "srl")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "srl")))) of + s_ => SOME (RISCV_SRL, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "sra")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "sra")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "sra")))) of + s_ => SOME (RISCV_SRA, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "or")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "or")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "or")))) of + s_ => SOME (RISCV_OR, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1689_0 "and")) /\ ( + (case ((string_drop stringappend_1689_0 ((string_length "and")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1689_0 ((string_length "and")))) of + s_ => SOME (RISCV_AND, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + (*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*) val _ = Define ` @@ -5282,886 +10249,1659 @@ val _ = Define ` )))`; -(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*) +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*) val _ = Define ` - ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rd addr value is_unsigned= + ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned= ((case ((extend_value is_unsigned value : ( 64 words$word) MemoryOpResult)) of - MemValue (result) => wX ((regbits_to_regno rd)) result - | MemException (e) => handle_mem_exception addr e + MemValue (result) => sail2_state_monad$seqS (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T) + | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + )))`; + + +(*val check_misaligned : mword ty64 -> word_width -> bool*) + +val _ = Define ` + ((check_misaligned:(64)words$word -> word_width -> bool) (vaddr : xlenbits) (width : word_width)= + (if ((plat_enable_misaligned_access () )) then F + else + (case width of + BYTE => F + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word))) + | WORD => + ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ (((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word)))))) + | DOUBLE => + ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ ((((((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) \/ (((((cast_unit_vec0 ((access_vec_dec vaddr (( 2 : int):ii))) : 1 words$word)) = ((bool_to_bits T : 1 words$word))))))))) + )))`; + + +(*val maybe_aq_forwards : bool -> string*) + +val _ = Define ` + ((maybe_aq_forwards:bool -> string) arg_= ((case arg_ of T => ".aq" | F => "" )))`; + + +(*val maybe_aq_backwards : string -> bool*) + +val _ = Define ` + ((maybe_aq_backwards:string -> bool) arg_= ((case arg_ of ".aq" => T | "" => F )))`; + + +(*val maybe_aq_forwards_matches : bool -> bool*) + +val _ = Define ` + ((maybe_aq_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; + + +(*val maybe_aq_backwards_matches : string -> bool*) + +val _ = Define ` + ((maybe_aq_backwards_matches:string -> bool) arg_= ((case arg_ of ".aq" => T | "" => T | _ => F )))`; + + +(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*) + +val _ = Define ` + ((maybe_aq_matches_prefix:string ->(bool#int)option) arg_= + (let stringappend_1687_0 = arg_ in + if (((((string_startswith stringappend_1687_0 ".aq")) /\ ( + (case ((string_drop stringappend_1687_0 ((string_length ".aq")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1687_0 ((string_length ".aq")))) of + s_ => SOME (T, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1687_0 "")) /\ ( + (case ((string_drop stringappend_1687_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1687_0 ((string_length "")))) of + s_ => SOME (F, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val maybe_rl_forwards : bool -> string*) + +val _ = Define ` + ((maybe_rl_forwards:bool -> string) arg_= ((case arg_ of T => ".rl" | F => "" )))`; + + +(*val maybe_rl_backwards : string -> bool*) + +val _ = Define ` + ((maybe_rl_backwards:string -> bool) arg_= ((case arg_ of ".rl" => T | "" => F )))`; + + +(*val maybe_rl_forwards_matches : bool -> bool*) + +val _ = Define ` + ((maybe_rl_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; + + +(*val maybe_rl_backwards_matches : string -> bool*) + +val _ = Define ` + ((maybe_rl_backwards_matches:string -> bool) arg_= ((case arg_ of ".rl" => T | "" => T | _ => F )))`; + + +(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*) + +val _ = Define ` + ((maybe_rl_matches_prefix:string ->(bool#int)option) arg_= + (let stringappend_1685_0 = arg_ in + if (((((string_startswith stringappend_1685_0 ".rl")) /\ ( + (case ((string_drop stringappend_1685_0 ((string_length ".rl")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1685_0 ((string_length ".rl")))) of + s_ => SOME (T, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1685_0 "")) /\ ( + (case ((string_drop stringappend_1685_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1685_0 ((string_length "")))) of + s_ => SOME (F, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val maybe_u_forwards : bool -> string*) + +val _ = Define ` + ((maybe_u_forwards:bool -> string) arg_= ((case arg_ of T => "u" | F => "" )))`; + + +(*val maybe_u_backwards : string -> bool*) + +val _ = Define ` + ((maybe_u_backwards:string -> bool) arg_= ((case arg_ of "u" => T | "" => F )))`; + + +(*val maybe_u_forwards_matches : bool -> bool*) + +val _ = Define ` + ((maybe_u_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; + + +(*val maybe_u_backwards_matches : string -> bool*) + +val _ = Define ` + ((maybe_u_backwards_matches:string -> bool) arg_= ((case arg_ of "u" => T | "" => T | _ => F )))`; + + +(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*) + +val _ = Define ` + ((maybe_u_matches_prefix:string ->(bool#int)option) arg_= + (let stringappend_1683_0 = arg_ in + if (((((string_startswith stringappend_1683_0 "u")) /\ ( + (case ((string_drop stringappend_1683_0 ((string_length "u")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1683_0 ((string_length "u")))) of + s_ => SOME (T, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1683_0 "")) /\ ( + (case ((string_drop stringappend_1683_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1683_0 ((string_length "")))) of + s_ => SOME (F, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val shiftw_mnemonic_forwards : sop -> string*) + +val _ = Define ` + ((shiftw_mnemonic_forwards:sop -> string) arg_= + ((case arg_ of RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" )))`; + + +(*val shiftw_mnemonic_backwards : string -> sop*) + +val _ = Define ` + ((shiftw_mnemonic_backwards:string -> sop) arg_= + ((case arg_ of "slli" => RISCV_SLLI | "srli" => RISCV_SRLI | "srai" => RISCV_SRAI )))`; + + +(*val shiftw_mnemonic_forwards_matches : sop -> bool*) + +val _ = Define ` + ((shiftw_mnemonic_forwards_matches:sop -> bool) arg_= + ((case arg_ of RISCV_SLLI => T | RISCV_SRLI => T | RISCV_SRAI => T )))`; + + +(*val shiftw_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((shiftw_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of "slli" => T | "srli" => T | "srai" => T | _ => F )))`; + + +(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*) + +val _ = Define ` + ((shiftw_mnemonic_matches_prefix:string ->(sop#int)option) arg_= + (let stringappend_1680_0 = arg_ in + if (((((string_startswith stringappend_1680_0 "slli")) /\ ( + (case ((string_drop stringappend_1680_0 ((string_length "slli")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1680_0 ((string_length "slli")))) of + s_ => SOME (RISCV_SLLI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1680_0 "srli")) /\ ( + (case ((string_drop stringappend_1680_0 ((string_length "srli")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1680_0 ((string_length "srli")))) of + s_ => SOME (RISCV_SRLI, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1680_0 "srai")) /\ ( + (case ((string_drop stringappend_1680_0 ((string_length "srai")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1680_0 ((string_length "srai")))) of + s_ => SOME (RISCV_SRAI, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val rtypew_mnemonic_forwards : ropw -> string*) + +val _ = Define ` + ((rtypew_mnemonic_forwards:ropw -> string) arg_= + ((case arg_ of + RISCV_ADDW => "addw" + | RISCV_SUBW => "subw" + | RISCV_SLLW => "sllw" + | RISCV_SRLW => "srlw" + | RISCV_SRAW => "sraw" + )))`; + + +(*val rtypew_mnemonic_backwards : string -> ropw*) + +val _ = Define ` + ((rtypew_mnemonic_backwards:string -> ropw) arg_= + ((case arg_ of + "addw" => RISCV_ADDW + | "subw" => RISCV_SUBW + | "sllw" => RISCV_SLLW + | "srlw" => RISCV_SRLW + | "sraw" => RISCV_SRAW + )))`; + + +(*val rtypew_mnemonic_forwards_matches : ropw -> bool*) + +val _ = Define ` + ((rtypew_mnemonic_forwards_matches:ropw -> bool) arg_= + ((case arg_ of + RISCV_ADDW => T + | RISCV_SUBW => T + | RISCV_SLLW => T + | RISCV_SRLW => T + | RISCV_SRAW => T + )))`; + + +(*val rtypew_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((rtypew_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "addw" => T + | "subw" => T + | "sllw" => T + | "srlw" => T + | "sraw" => T + | _ => F + )))`; + + +(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*) + +val _ = Define ` + ((rtypew_mnemonic_matches_prefix:string ->(ropw#int)option) arg_= + (let stringappend_1675_0 = arg_ in + if (((((string_startswith stringappend_1675_0 "addw")) /\ ( + (case ((string_drop stringappend_1675_0 ((string_length "addw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1675_0 ((string_length "addw")))) of + s_ => SOME (RISCV_ADDW, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1675_0 "subw")) /\ ( + (case ((string_drop stringappend_1675_0 ((string_length "subw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1675_0 ((string_length "subw")))) of + s_ => SOME (RISCV_SUBW, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1675_0 "sllw")) /\ ( + (case ((string_drop stringappend_1675_0 ((string_length "sllw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1675_0 ((string_length "sllw")))) of + s_ => SOME (RISCV_SLLW, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1675_0 "srlw")) /\ ( + (case ((string_drop stringappend_1675_0 ((string_length "srlw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1675_0 ((string_length "srlw")))) of + s_ => SOME (RISCV_SRLW, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1675_0 "sraw")) /\ ( + (case ((string_drop stringappend_1675_0 ((string_length "sraw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1675_0 ((string_length "sraw")))) of + s_ => SOME (RISCV_SRAW, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val encdec_mul_op_forwards : bool -> bool -> bool -> mword ty3*) + +val _ = Define ` + ((encdec_mul_op_forwards:bool -> bool -> bool ->(3)words$word) arg0 arg1 arg2= + (let arg_ = (arg0, arg1, arg2) in + (case arg_ of + (F, T, T) => (vec_of_bits [B0;B0;B0] : 3 words$word) + | (T, T, T) => (vec_of_bits [B0;B0;B1] : 3 words$word) + | (T, T, F) => (vec_of_bits [B0;B1;B0] : 3 words$word) + | (T, F, F) => (vec_of_bits [B0;B1;B1] : 3 words$word) + )))`; + + +(*val encdec_mul_op_backwards : mword ty3 -> (bool * bool * bool)*) + +val _ = Define ` + ((encdec_mul_op_backwards:(3)words$word -> bool#bool#bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then (F, T, T) + else if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then (T, T, T) + else if (((p0_ = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then (T, T, F) + else (T, F, F)))`; + + +(*val encdec_mul_op_forwards_matches : bool -> bool -> bool -> bool*) + +val _ = Define ` + ((encdec_mul_op_forwards_matches:bool -> bool -> bool -> bool) arg0 arg1 arg2= + (let arg_ = (arg0, arg1, arg2) in + (case arg_ of + (F, T, T) => T + | (T, T, T) => T + | (T, T, F) => T + | (T, F, F) => T + | _ => F + )))`; + + +(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*) + +val _ = Define ` + ((encdec_mul_op_backwards_matches:(3)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B0;B1] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B1;B0] : 3 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0;B1;B1] : 3 words$word)))) then T + else F))`; + + +(*val mul_mnemonic_forwards : bool -> bool -> bool -> string*) + +val _ = Define ` + ((mul_mnemonic_forwards:bool -> bool -> bool -> string) arg0 arg1 arg2= + (let arg_ = (arg0, arg1, arg2) in + (case arg_ of + (F, T, T) => "mul" + | (T, T, T) => "mulh" + | (T, T, F) => "mulhsu" + | (T, F, F) => "mulhu" + )))`; + + +(*val mul_mnemonic_backwards : string -> (bool * bool * bool)*) + +val _ = Define ` + ((mul_mnemonic_backwards:string -> bool#bool#bool) arg_= + ((case arg_ of + "mul" => (F, T, T) + | "mulh" => (T, T, T) + | "mulhsu" => (T, T, F) + | "mulhu" => (T, F, F) + )))`; + + +(*val mul_mnemonic_forwards_matches : bool -> bool -> bool -> bool*) + +val _ = Define ` + ((mul_mnemonic_forwards_matches:bool -> bool -> bool -> bool) arg0 arg1 arg2= + (let arg_ = (arg0, arg1, arg2) in + (case arg_ of + (F, T, T) => T + | (T, T, T) => T + | (T, T, F) => T + | (T, F, F) => T + | _ => F )))`; -(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*) +(*val mul_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((mul_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "mul" => T + | "mulh" => T + | "mulhsu" => T + | "mulhu" => T + | _ => F + )))`; + + +(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*) + +val _ = Define ` + ((mul_mnemonic_matches_prefix:string ->((bool#bool#bool)#int)option) arg_= + (let stringappend_1671_0 = arg_ in + if (((((string_startswith stringappend_1671_0 "mul")) /\ ( + (case ((string_drop stringappend_1671_0 ((string_length "mul")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1671_0 ((string_length "mul")))) of + s_ => SOME ((F, T, T), ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1671_0 "mulh")) /\ ( + (case ((string_drop stringappend_1671_0 ((string_length "mulh")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1671_0 ((string_length "mulh")))) of + s_ => SOME ((T, T, T), ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1671_0 "mulhsu")) /\ ( + (case ((string_drop stringappend_1671_0 ((string_length "mulhsu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1671_0 ((string_length "mulhsu")))) of + s_ => SOME ((T, T, F), ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1671_0 "mulhu")) /\ ( + (case ((string_drop stringappend_1671_0 ((string_length "mulhu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1671_0 ((string_length "mulhu")))) of + s_ => SOME ((T, F, F), ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val maybe_not_u_forwards : bool -> string*) + +val _ = Define ` + ((maybe_not_u_forwards:bool -> string) arg_= ((case arg_ of F => "u" | T => "" )))`; + + +(*val maybe_not_u_backwards : string -> bool*) + +val _ = Define ` + ((maybe_not_u_backwards:string -> bool) arg_= ((case arg_ of "u" => F | "" => T )))`; + + +(*val maybe_not_u_forwards_matches : bool -> bool*) + +val _ = Define ` + ((maybe_not_u_forwards_matches:bool -> bool) arg_= + ((case arg_ of F => T | T => T )))`; + + +(*val maybe_not_u_backwards_matches : string -> bool*) + +val _ = Define ` + ((maybe_not_u_backwards_matches:string -> bool) arg_= ((case arg_ of "u" => T | "" => T | _ => F )))`; + + +(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*) + +val _ = Define ` + ((maybe_not_u_matches_prefix:string ->(bool#int)option) arg_= + (let stringappend_1669_0 = arg_ in + if (((((string_startswith stringappend_1669_0 "u")) /\ ( + (case ((string_drop stringappend_1669_0 ((string_length "u")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1669_0 ((string_length "u")))) of + s_ => SOME (F, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1669_0 "")) /\ ( + (case ((string_drop stringappend_1669_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1669_0 ((string_length "")))) of + s_ => SOME (T, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val bit_maybe_r_forwards : mword ty1 -> string*) + +val _ = Define ` + ((bit_maybe_r_forwards:(1)words$word -> string) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then "r" + else ""))`; + + +(*val bit_maybe_r_backwards : string -> mword ty1*) + +val _ = Define ` + ((bit_maybe_r_backwards:string ->(1)words$word) arg_= + ((case arg_ of + "r" => (vec_of_bits [B1] : 1 words$word) + | "" => (vec_of_bits [B0] : 1 words$word) + )))`; + + +(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*) + +val _ = Define ` + ((bit_maybe_r_forwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; + + +(*val bit_maybe_r_backwards_matches : string -> bool*) + +val _ = Define ` + ((bit_maybe_r_backwards_matches:string -> bool) arg_= ((case arg_ of "r" => T | "" => T | _ => F )))`; + + +(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +val _ = Define ` + ((bit_maybe_r_matches_prefix:string ->((1)words$word#int)option) arg_= + (let stringappend_1667_0 = arg_ in + if (((((string_startswith stringappend_1667_0 "r")) /\ ( + (case ((string_drop stringappend_1667_0 ((string_length "r")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1667_0 ((string_length "r")))) of + s_ => + SOME ((vec_of_bits [B1] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1667_0 "")) /\ ( + (case ((string_drop stringappend_1667_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1667_0 ((string_length "")))) of + s_ => + SOME ((vec_of_bits [B0] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val bit_maybe_w_forwards : mword ty1 -> string*) + +val _ = Define ` + ((bit_maybe_w_forwards:(1)words$word -> string) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then "w" + else ""))`; + + +(*val bit_maybe_w_backwards : string -> mword ty1*) + +val _ = Define ` + ((bit_maybe_w_backwards:string ->(1)words$word) arg_= + ((case arg_ of + "w" => (vec_of_bits [B1] : 1 words$word) + | "" => (vec_of_bits [B0] : 1 words$word) + )))`; + + +(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*) + +val _ = Define ` + ((bit_maybe_w_forwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; + + +(*val bit_maybe_w_backwards_matches : string -> bool*) + +val _ = Define ` + ((bit_maybe_w_backwards_matches:string -> bool) arg_= ((case arg_ of "w" => T | "" => T | _ => F )))`; + + +(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +val _ = Define ` + ((bit_maybe_w_matches_prefix:string ->((1)words$word#int)option) arg_= + (let stringappend_1665_0 = arg_ in + if (((((string_startswith stringappend_1665_0 "w")) /\ ( + (case ((string_drop stringappend_1665_0 ((string_length "w")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1665_0 ((string_length "w")))) of + s_ => + SOME ((vec_of_bits [B1] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1665_0 "")) /\ ( + (case ((string_drop stringappend_1665_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1665_0 ((string_length "")))) of + s_ => + SOME ((vec_of_bits [B0] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val bit_maybe_i_forwards : mword ty1 -> string*) + +val _ = Define ` + ((bit_maybe_i_forwards:(1)words$word -> string) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then "i" + else ""))`; + + +(*val bit_maybe_i_backwards : string -> mword ty1*) + +val _ = Define ` + ((bit_maybe_i_backwards:string ->(1)words$word) arg_= + ((case arg_ of + "i" => (vec_of_bits [B1] : 1 words$word) + | "" => (vec_of_bits [B0] : 1 words$word) + )))`; + + +(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*) + +val _ = Define ` + ((bit_maybe_i_forwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; + + +(*val bit_maybe_i_backwards_matches : string -> bool*) + +val _ = Define ` + ((bit_maybe_i_backwards_matches:string -> bool) arg_= ((case arg_ of "i" => T | "" => T | _ => F )))`; + + +(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +val _ = Define ` + ((bit_maybe_i_matches_prefix:string ->((1)words$word#int)option) arg_= + (let stringappend_1663_0 = arg_ in + if (((((string_startswith stringappend_1663_0 "i")) /\ ( + (case ((string_drop stringappend_1663_0 ((string_length "i")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1663_0 ((string_length "i")))) of + s_ => + SOME ((vec_of_bits [B1] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1663_0 "")) /\ ( + (case ((string_drop stringappend_1663_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1663_0 ((string_length "")))) of + s_ => + SOME ((vec_of_bits [B0] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val bit_maybe_o_forwards : mword ty1 -> string*) + +val _ = Define ` + ((bit_maybe_o_forwards:(1)words$word -> string) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then "o" + else ""))`; + + +(*val bit_maybe_o_backwards : string -> mword ty1*) + +val _ = Define ` + ((bit_maybe_o_backwards:string ->(1)words$word) arg_= + ((case arg_ of + "o" => (vec_of_bits [B1] : 1 words$word) + | "" => (vec_of_bits [B0] : 1 words$word) + )))`; + + +(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*) + +val _ = Define ` + ((bit_maybe_o_forwards_matches:(1)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B1] : 1 words$word)))) then T + else if (((p0_ = (vec_of_bits [B0] : 1 words$word)))) then T + else F))`; + + +(*val bit_maybe_o_backwards_matches : string -> bool*) + +val _ = Define ` + ((bit_maybe_o_backwards_matches:string -> bool) arg_= ((case arg_ of "o" => T | "" => T | _ => F )))`; + + +(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +val _ = Define ` + ((bit_maybe_o_matches_prefix:string ->((1)words$word#int)option) arg_= + (let stringappend_1661_0 = arg_ in + if (((((string_startswith stringappend_1661_0 "o")) /\ ( + (case ((string_drop stringappend_1661_0 ((string_length "o")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1661_0 ((string_length "o")))) of + s_ => + SOME ((vec_of_bits [B1] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1661_0 "")) /\ ( + (case ((string_drop stringappend_1661_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1661_0 ((string_length "")))) of + s_ => + SOME ((vec_of_bits [B0] : 1 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val fence_bits_forwards : mword ty4 -> string*) + +val _ = Define ` + ((fence_bits_forwards:(4)words$word -> string) arg_= + ((case arg_ of + v__0 => + let (r : 1 bits) = ((subrange_vec_dec v__0 (( 3 : int):ii) (( 3 : int):ii) : 1 words$word)) in + let (w : 1 bits) = ((subrange_vec_dec v__0 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + let (i : 1 bits) = ((subrange_vec_dec v__0 (( 1 : int):ii) (( 1 : int):ii) : 1 words$word)) in + let (o1 : 1 bits) = ((subrange_vec_dec v__0 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in + string_append ((bit_maybe_r_forwards r)) + ((string_append ((bit_maybe_w_forwards w)) + ((string_append ((bit_maybe_i_forwards i)) + ((string_append ((bit_maybe_o_forwards o1)) "")))))) + )))`; + + +(*val fence_bits_backwards : string -> mword ty4*) + +val _ = Define ` + ((fence_bits_backwards:string ->(4)words$word) arg_= + (let stringappend_1649_0 = arg_ in + let (r, stringappend_1651_0) = + ((case ((bit_maybe_r_matches_prefix stringappend_1649_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1650_0,stringappend_1651_0) => (stringappend_1650_0, stringappend_1651_0) + )) in + let stringappend_1652_0 = (string_drop stringappend_1649_0 stringappend_1651_0) in + let (w, stringappend_1654_0) = + ((case ((bit_maybe_w_matches_prefix stringappend_1652_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1653_0,stringappend_1654_0) => (stringappend_1653_0, stringappend_1654_0) + )) in + let stringappend_1655_0 = (string_drop stringappend_1652_0 stringappend_1654_0) in + let (i, stringappend_1657_0) = + ((case ((bit_maybe_i_matches_prefix stringappend_1655_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1656_0,stringappend_1657_0) => (stringappend_1656_0, stringappend_1657_0) + )) in + let stringappend_1658_0 = (string_drop stringappend_1655_0 stringappend_1657_0) in + let (o1, stringappend_1660_0) = + ((case ((bit_maybe_o_matches_prefix stringappend_1658_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1659_0,stringappend_1660_0) => (stringappend_1659_0, stringappend_1660_0) + )) in + (case ((string_drop stringappend_1658_0 stringappend_1660_0)) of + "" => (concat_vec r ((concat_vec w ((concat_vec i o1 : 2 words$word)) : 3 words$word)) : 4 words$word) + )))`; + + +(*val fence_bits_forwards_matches : mword ty4 -> bool*) + +val _ = Define ` + ((fence_bits_forwards_matches:(4)words$word -> bool) arg_= + ((case arg_ of v__1 => T )))`; + + +(*val fence_bits_backwards_matches : string -> bool*) + +val _ = Define ` + ((fence_bits_backwards_matches:string -> bool) arg_= + (let stringappend_1637_0 = arg_ in + if ((case ((bit_maybe_r_matches_prefix stringappend_1637_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1638_0,stringappend_1639_0) => + let stringappend_1640_0 = (string_drop stringappend_1637_0 stringappend_1639_0) in + if ((case ((bit_maybe_w_matches_prefix stringappend_1640_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1641_0,stringappend_1642_0) => + let stringappend_1643_0 = (string_drop stringappend_1640_0 stringappend_1642_0) in + if ((case ((bit_maybe_i_matches_prefix stringappend_1643_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1644_0,stringappend_1645_0) => + let stringappend_1646_0 = (string_drop stringappend_1643_0 stringappend_1645_0) in + if ((case ((bit_maybe_o_matches_prefix stringappend_1646_0 + : (( 1 words$word # ii))option)) of + SOME (stringappend_1647_0,stringappend_1648_0) => + (case ((string_drop stringappend_1646_0 stringappend_1648_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (r, stringappend_1639_0) = + ((case ((bit_maybe_r_matches_prefix stringappend_1637_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1638_0,stringappend_1639_0) => + (stringappend_1638_0, stringappend_1639_0) + )) in + let stringappend_1640_0 = (string_drop stringappend_1637_0 stringappend_1639_0) in + let (w, stringappend_1642_0) = + ((case ((bit_maybe_w_matches_prefix stringappend_1640_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1641_0,stringappend_1642_0) => + (stringappend_1641_0, stringappend_1642_0) + )) in + let stringappend_1643_0 = (string_drop stringappend_1640_0 stringappend_1642_0) in + let (i, stringappend_1645_0) = + ((case ((bit_maybe_i_matches_prefix stringappend_1643_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1644_0,stringappend_1645_0) => + (stringappend_1644_0, stringappend_1645_0) + )) in + let stringappend_1646_0 = (string_drop stringappend_1643_0 stringappend_1645_0) in + let (o1, stringappend_1648_0) = + ((case ((bit_maybe_o_matches_prefix stringappend_1646_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1647_0,stringappend_1648_0) => + (stringappend_1647_0, stringappend_1648_0) + )) in + (case ((string_drop stringappend_1646_0 stringappend_1648_0)) of "" => T ) + else F))`; + + +(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*) + +val _ = Define ` + ((fence_bits_matches_prefix:string ->((4)words$word#int)option) arg_= + (let stringappend_1625_0 = arg_ in + if ((case ((bit_maybe_r_matches_prefix stringappend_1625_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1626_0,stringappend_1627_0) => + let stringappend_1628_0 = (string_drop stringappend_1625_0 stringappend_1627_0) in + if ((case ((bit_maybe_w_matches_prefix stringappend_1628_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1629_0,stringappend_1630_0) => + let stringappend_1631_0 = (string_drop stringappend_1628_0 stringappend_1630_0) in + if ((case ((bit_maybe_i_matches_prefix stringappend_1631_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1632_0,stringappend_1633_0) => + let stringappend_1634_0 = (string_drop stringappend_1631_0 stringappend_1633_0) in + if ((case ((bit_maybe_o_matches_prefix stringappend_1634_0 + : (( 1 words$word # ii))option)) of + SOME (stringappend_1635_0,stringappend_1636_0) => + (case ((string_drop stringappend_1634_0 stringappend_1636_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (r, stringappend_1627_0) = + ((case ((bit_maybe_r_matches_prefix stringappend_1625_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1626_0,stringappend_1627_0) => + (stringappend_1626_0, stringappend_1627_0) + )) in + let stringappend_1628_0 = (string_drop stringappend_1625_0 stringappend_1627_0) in + let (w, stringappend_1630_0) = + ((case ((bit_maybe_w_matches_prefix stringappend_1628_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1629_0,stringappend_1630_0) => + (stringappend_1629_0, stringappend_1630_0) + )) in + let stringappend_1631_0 = (string_drop stringappend_1628_0 stringappend_1630_0) in + let (i, stringappend_1633_0) = + ((case ((bit_maybe_i_matches_prefix stringappend_1631_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1632_0,stringappend_1633_0) => + (stringappend_1632_0, stringappend_1633_0) + )) in + let stringappend_1634_0 = (string_drop stringappend_1631_0 stringappend_1633_0) in + let (o1, stringappend_1636_0) = + ((case ((bit_maybe_o_matches_prefix stringappend_1634_0 : (( 1 words$word # ii))option)) of + SOME (stringappend_1635_0,stringappend_1636_0) => + (stringappend_1635_0, stringappend_1636_0) + )) in + (case ((string_drop stringappend_1634_0 stringappend_1636_0)) of + s_ => + SOME ((concat_vec r ((concat_vec w ((concat_vec i o1 : 2 words$word)) : 3 words$word)) + : 4 words$word), + ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val aqrl_str : bool -> bool -> string*) + +val _ = Define ` + ((aqrl_str:bool -> bool -> string) (aq : bool) (rl : bool)= + ((case (aq, rl) of + (F, F) => "" + | (F, T) => ".rl" + | (T, F) => ".aq" + | (T, T) => ".aqrl" + )))`; + + +(*val lrsc_width_str : word_width -> string*) + +val _ = Define ` + ((lrsc_width_str:word_width -> string) width= + ((case width of BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" )))`; + + +(*val process_loadres : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*) + +val _ = Define ` + ((process_loadres:(5)words$word ->(64)words$word ->('int8_times_n words$word)MemoryOpResult -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rd addr value is_unsigned= + ((case ((extend_value is_unsigned value : ( 64 words$word) MemoryOpResult)) of + MemValue (result) => + let (_ : unit) = (load_reservation addr) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T) + | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + )))`; + + +(*val encdec_amoop_forwards : amoop -> mword ty5*) + +val _ = Define ` + ((encdec_amoop_forwards:amoop ->(5)words$word) arg_= + ((case arg_ of + AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word) + | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word) + | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word) + | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word) + | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word) + | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word) + | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word) + | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word) + )))`; + + +(*val encdec_amoop_backwards : mword ty5 -> amoop*) + +val _ = Define ` + ((encdec_amoop_backwards:(5)words$word -> amoop) arg_= + (let p0_ = arg_ in + if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) + then + AMOSWAP + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then + AMOADD + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + AMOXOR + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + AMOAND + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + AMOOR + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + AMOMIN + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + AMOMAX + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + AMOMINU + else AMOMAXU))`; + + +(*val encdec_amoop_forwards_matches : amoop -> bool*) + +val _ = Define ` + ((encdec_amoop_forwards_matches:amoop -> bool) arg_= + ((case arg_ of + AMOSWAP => T + | AMOADD => T + | AMOXOR => T + | AMOAND => T + | AMOOR => T + | AMOMIN => T + | AMOMAX => T + | AMOMINU => T + | AMOMAXU => T + )))`; + + +(*val encdec_amoop_backwards_matches : mword ty5 -> bool*) + +val _ = Define ` + ((encdec_amoop_backwards_matches:(5)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) + then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) then + T + else if (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) then + T + else F))`; + + +(*val amo_mnemonic_forwards : amoop -> string*) + +val _ = Define ` + ((amo_mnemonic_forwards:amoop -> string) arg_= + ((case arg_ of + AMOSWAP => "amoswap" + | AMOADD => "amoadd" + | AMOXOR => "amoxor" + | AMOAND => "amoand" + | AMOOR => "amoor" + | AMOMIN => "amomin" + | AMOMAX => "amomax" + | AMOMINU => "amominu" + | AMOMAXU => "amomaxu" + )))`; + + +(*val amo_mnemonic_backwards : string -> amoop*) + +val _ = Define ` + ((amo_mnemonic_backwards:string -> amoop) arg_= + ((case arg_ of + "amoswap" => AMOSWAP + | "amoadd" => AMOADD + | "amoxor" => AMOXOR + | "amoand" => AMOAND + | "amoor" => AMOOR + | "amomin" => AMOMIN + | "amomax" => AMOMAX + | "amominu" => AMOMINU + | "amomaxu" => AMOMAXU + )))`; + + +(*val amo_mnemonic_forwards_matches : amoop -> bool*) + +val _ = Define ` + ((amo_mnemonic_forwards_matches:amoop -> bool) arg_= + ((case arg_ of + AMOSWAP => T + | AMOADD => T + | AMOXOR => T + | AMOAND => T + | AMOOR => T + | AMOMIN => T + | AMOMAX => T + | AMOMINU => T + | AMOMAXU => T + )))`; + + +(*val amo_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((amo_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of + "amoswap" => T + | "amoadd" => T + | "amoxor" => T + | "amoand" => T + | "amoor" => T + | "amomin" => T + | "amomax" => T + | "amominu" => T + | "amomaxu" => T + | _ => F + )))`; + + +(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*) + +val _ = Define ` + ((amo_mnemonic_matches_prefix:string ->(amoop#int)option) arg_= + (let stringappend_1616_0 = arg_ in + if (((((string_startswith stringappend_1616_0 "amoswap")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amoswap")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amoswap")))) of + s_ => SOME (AMOSWAP, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amoadd")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amoadd")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amoadd")))) of + s_ => SOME (AMOADD, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amoxor")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amoxor")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amoxor")))) of + s_ => SOME (AMOXOR, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amoand")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amoand")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amoand")))) of + s_ => SOME (AMOAND, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amoor")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amoor")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amoor")))) of + s_ => SOME (AMOOR, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amomin")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amomin")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amomin")))) of + s_ => SOME (AMOMIN, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amomax")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amomax")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amomax")))) of + s_ => SOME (AMOMAX, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amominu")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amominu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amominu")))) of + s_ => SOME (AMOMINU, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1616_0 "amomaxu")) /\ ( + (case ((string_drop stringappend_1616_0 ((string_length "amomaxu")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1616_0 ((string_length "amomaxu")))) of + s_ => SOME (AMOMAXU, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +(*val encdec_csrop_forwards : csrop -> mword ty2*) + +val _ = Define ` + ((encdec_csrop_forwards:csrop ->(2)words$word) arg_= + ((case arg_ of + CSRRW => (vec_of_bits [B0;B1] : 2 words$word) + | CSRRS => (vec_of_bits [B1;B0] : 2 words$word) + | CSRRC => (vec_of_bits [B1;B1] : 2 words$word) + )))`; + + +(*val encdec_csrop_backwards : mword ty2 -> csrop*) + +val _ = Define ` + ((encdec_csrop_backwards:(2)words$word -> csrop) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B1] : 2 words$word)))) then CSRRW + else if (((p0_ = (vec_of_bits [B1;B0] : 2 words$word)))) then CSRRS + else CSRRC))`; + + +(*val encdec_csrop_forwards_matches : csrop -> bool*) + +val _ = Define ` + ((encdec_csrop_forwards_matches:csrop -> bool) arg_= + ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`; + + +(*val encdec_csrop_backwards_matches : mword ty2 -> bool*) + +val _ = Define ` + ((encdec_csrop_backwards_matches:(2)words$word -> bool) arg_= + (let p0_ = arg_ in + if (((p0_ = (vec_of_bits [B0;B1] : 2 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B0] : 2 words$word)))) then T + else if (((p0_ = (vec_of_bits [B1;B1] : 2 words$word)))) then T + else F))`; + (*val readCSR : mword ty12 -> M (mword ty64)*) val _ = Define ` - ((readCSR:(12)words$word ->(regstate)state_monad$sequential_state ->((((64)words$word),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr= - (let b__0 = csr in - if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then - (state_monad$read_regS mvendorid_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then - (state_monad$read_regS marchid_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then - (state_monad$read_regS mimpid_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then - (state_monad$read_regS mhartid_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . state_monad$returnS ((get_Mstatus w__4 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS misa_ref) (\ (w__5 : Misa) . state_monad$returnS ((get_Misa w__5 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . state_monad$returnS ((get_Medeleg w__6 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . - state_monad$returnS ((get_Minterrupts w__7 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) . state_monad$returnS ((get_Minterrupts w__8 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mtvec_ref) (\ (w__9 : Mtvec) . state_monad$returnS ((get_Mtvec w__9 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (state_monad$read_regS mscratch_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (state_monad$read_regS mepc_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mcause_ref) (\ (w__12 : Mcause) . state_monad$returnS ((get_Mcause w__12 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (state_monad$read_regS mtval_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mip_ref) (\ (w__14 : Minterrupts) . - state_monad$returnS ((get_Minterrupts w__14 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__15 : Mstatus) . state_monad$returnS ((get_Mstatus w__15 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS sedeleg_ref) (\ (w__16 : Sedeleg) . state_monad$returnS ((get_Sedeleg w__16 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS sideleg_ref) (\ (w__17 : Sinterrupts) . - state_monad$returnS ((get_Sinterrupts w__17 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mie_ref) (\ (w__18 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__19 : Minterrupts) . - state_monad$returnS ((get_Sinterrupts ((lower_mie w__18 w__19)) : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS stvec_ref) (\ (w__20 : Mtvec) . state_monad$returnS ((get_Mtvec w__20 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (state_monad$read_regS sscratch_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (state_monad$read_regS sepc_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS scause_ref) (\ (w__23 : Mcause) . state_monad$returnS ((get_Mcause w__23 : 64 words$word))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then - (state_monad$read_regS stval_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mip_ref) (\ (w__25 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__26 : Minterrupts) . - state_monad$returnS ((get_Sinterrupts ((lower_mip w__25 w__26)) : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (state_monad$read_regS satp_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then - (state_monad$read_regS mcycle_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then - (state_monad$read_regS mtime_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then - (state_monad$read_regS minstret_ref : ( 64 words$word) M) - else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS tselect_ref : ( 64 words$word) M) (\ (w__31 : 64 words$word) . - state_monad$returnS ((not_vec w__31 : 64 words$word))) - else - let (_ : unit) = (print_bits "unhandled read to CSR " csr) in - state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)))`; + ((readCSR:(12)words$word ->(regstate)sail2_state_monad$sequential_state ->((((64)words$word),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr= + (let b__0 = csr in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : 12 words$word)))) then + (sail2_state_monad$read_regS mvendorid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS marchid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : 12 words$word)))) then + (sail2_state_monad$read_regS mimpid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS mhartid_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__4 : Mstatus) . + sail2_state_monad$returnS ((get_Mstatus_bits w__4 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__5 : Misa) . sail2_state_monad$returnS ((get_Misa_bits w__5 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS medeleg_ref) (\ (w__6 : Medeleg) . + sail2_state_monad$returnS ((get_Medeleg_bits w__6 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . + sail2_state_monad$returnS ((get_Minterrupts_bits w__7 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mie_ref) (\ (w__8 : Minterrupts) . + sail2_state_monad$returnS ((get_Minterrupts_bits w__8 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mtvec_ref) (\ (w__9 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__9 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcounteren_ref) (\ (w__10 : Counteren) . + sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__10 : 32 words$word)) : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS mscratch_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mepc_ref : ( 64 words$word) M) (\ (w__12 : 64 words$word) . sail2_state_monad$bindS + (pc_alignment_mask () : ( 64 words$word) M) (\ (w__13 : 64 words$word) . + sail2_state_monad$returnS ((and_vec w__12 w__13 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcause_ref) (\ (w__14 : Mcause) . + sail2_state_monad$returnS ((get_Mcause_bits w__14 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (sail2_state_monad$read_regS mtval_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__16 : Minterrupts) . + sail2_state_monad$returnS ((get_Minterrupts_bits w__16 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS pmpcfg0_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__19 : Mstatus) . + sail2_state_monad$returnS ((get_Sstatus_bits ((lower_mstatus w__19)) : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS sedeleg_ref) (\ (w__20 : Sedeleg) . + sail2_state_monad$returnS ((get_Sedeleg_bits w__20 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS sideleg_ref) (\ (w__21 : Sinterrupts) . + sail2_state_monad$returnS ((get_Sinterrupts_bits w__21 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mie_ref) (\ (w__22 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__23 : Minterrupts) . + sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mie w__22 w__23)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS stvec_ref) (\ (w__24 : Mtvec) . sail2_state_monad$returnS ((get_Mtvec_bits w__24 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scounteren_ref) (\ (w__25 : Counteren) . + sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__25 : 32 words$word)) : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS sscratch_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS sepc_ref : ( 64 words$word) M) (\ (w__27 : 64 words$word) . sail2_state_monad$bindS + (pc_alignment_mask () : ( 64 words$word) M) (\ (w__28 : 64 words$word) . + sail2_state_monad$returnS ((and_vec w__27 w__28 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scause_ref) (\ (w__29 : Mcause) . + sail2_state_monad$returnS ((get_Mcause_bits w__29 : 64 words$word))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then + (sail2_state_monad$read_regS stval_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__31 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__32 : Minterrupts) . + sail2_state_monad$returnS ((get_Sinterrupts_bits ((lower_mip w__31 w__32)) : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then + (sail2_state_monad$read_regS mtime_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then + (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS tselect_ref : ( 64 words$word) M) (\ (w__37 : 64 words$word) . + sail2_state_monad$returnS ((not_vec w__37 : 64 words$word))) + else + let (_ : unit) = (print_bits "unhandled read to CSR " csr) in + sail2_state_monad$returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) (\ (res : xlenbits) . + let (_ : unit) = + (print_endline + ((STRCAT "CSR " + ((STRCAT ((csr_name csr)) ((STRCAT " -> " ((string_of_bits res))))))))) in + sail2_state_monad$returnS res)))`; (*val writeCSR : mword ty12 -> mword ty64 -> M unit*) val _ = Define ` - ((writeCSR:(12)words$word ->(64)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= - (let b__0 = csr in state_monad$bindS - (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mstatus_ref ((legalize_mstatus w__0 value))) - (state_monad$read_regS mstatus_ref)) (\ (w__1 : Mstatus) . - state_monad$returnS (SOME ((get_Mstatus w__1 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS medeleg_ref) (\ (w__2 : Medeleg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS medeleg_ref ((legalize_medeleg w__2 value))) - (state_monad$read_regS medeleg_ref)) (\ (w__3 : Medeleg) . - state_monad$returnS (SOME ((get_Medeleg w__3 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__4 : Minterrupts) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mideleg_ref ((legalize_mideleg w__4 value))) - (state_monad$read_regS mideleg_ref)) (\ (w__5 : Minterrupts) . - state_monad$returnS (SOME ((get_Minterrupts w__5 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mie_ref) (\ (w__6 : Minterrupts) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mie_ref ((legalize_mie w__6 value))) - (state_monad$read_regS mie_ref)) (\ (w__7 : Minterrupts) . - state_monad$returnS (SOME ((get_Minterrupts w__7 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mtvec_ref) (\ (w__8 : Mtvec) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mtvec_ref ((legalize_tvec w__8 value))) - (state_monad$read_regS mtvec_ref)) (\ (w__9 : Mtvec) . state_monad$returnS (SOME ((get_Mtvec w__9 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (state_monad$write_regS mscratch_ref value) - (state_monad$read_regS mscratch_ref : ( 64 words$word) M)) (\ (w__10 : 64 words$word) . state_monad$returnS (SOME w__10)) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS - (legalize_xepc value : ( 64 words$word) M) (\ (w__11 : xlenbits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mepc_ref w__11) - (state_monad$read_regS mepc_ref : ( 64 words$word) M)) (\ (w__12 : 64 words$word) . state_monad$returnS (SOME w__12))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (set_Mcause mcause_ref value) - (state_monad$read_regS mcause_ref)) (\ (w__13 : Mcause) . - state_monad$returnS (SOME ((get_Mcause w__13 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (state_monad$write_regS mtval_ref value) - (state_monad$read_regS mtval_ref : ( 64 words$word) M)) (\ (w__14 : 64 words$word) . state_monad$returnS (SOME w__14)) - else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mip_ref) (\ (w__15 : Minterrupts) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mip_ref ((legalize_mip w__15 value))) - (state_monad$read_regS mip_ref)) (\ (w__16 : Minterrupts) . - state_monad$returnS (SOME ((get_Minterrupts w__16 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__17 : Mstatus) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mstatus_ref ((legalize_sstatus w__17 value))) - (state_monad$read_regS mstatus_ref)) (\ (w__18 : Mstatus) . - state_monad$returnS (SOME ((get_Mstatus w__18 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS sedeleg_ref) (\ (w__19 : Sedeleg) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__19 value))) - (state_monad$read_regS sedeleg_ref)) (\ (w__20 : Sedeleg) . - state_monad$returnS (SOME ((get_Sedeleg w__20 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (set_Sinterrupts sideleg_ref value) - (state_monad$read_regS sideleg_ref)) (\ (w__21 : Sinterrupts) . - state_monad$returnS (SOME ((get_Sinterrupts w__21 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mie_ref) (\ (w__22 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__23 : Minterrupts) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mie_ref ((legalize_sie w__22 w__23 value))) - (state_monad$read_regS mie_ref)) (\ (w__24 : Minterrupts) . - state_monad$returnS (SOME ((get_Minterrupts w__24 : 64 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS stvec_ref) (\ (w__25 : Mtvec) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS stvec_ref ((legalize_tvec w__25 value))) - (state_monad$read_regS stvec_ref)) (\ (w__26 : Mtvec) . state_monad$returnS (SOME ((get_Mtvec w__26 : 64 words$word))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (state_monad$write_regS sscratch_ref value) - (state_monad$read_regS sscratch_ref : ( 64 words$word) M)) (\ (w__27 : 64 words$word) . state_monad$returnS (SOME w__27)) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then state_monad$bindS - (legalize_xepc value : ( 64 words$word) M) (\ (w__28 : xlenbits) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS sepc_ref w__28) - (state_monad$read_regS sepc_ref : ( 64 words$word) M)) (\ (w__29 : 64 words$word) . state_monad$returnS (SOME w__29))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (set_Mcause scause_ref value) - (state_monad$read_regS scause_ref)) (\ (w__30 : Mcause) . - state_monad$returnS (SOME ((get_Mcause w__30 : 64 words$word)))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (state_monad$write_regS stval_ref value) - (state_monad$read_regS stval_ref : ( 64 words$word) M)) (\ (w__31 : 64 words$word) . state_monad$returnS (SOME w__31)) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then state_monad$bindS - (state_monad$read_regS mip_ref) (\ (w__32 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__33 : Minterrupts) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS mip_ref ((legalize_sip w__32 w__33 value))) - (state_monad$read_regS mip_ref)) (\ (w__34 : Minterrupts) . - state_monad$returnS (SOME ((get_Minterrupts w__34 : 64 words$word)))))) - else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS - (cur_Architecture () ) (\ (w__35 : Architecture) . state_monad$bindS - (state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__36 : 64 words$word) . state_monad$bindS (state_monad$seqS - (state_monad$write_regS satp_ref ((legalize_satp w__35 w__36 value : 64 words$word))) - (state_monad$read_regS satp_ref : ( 64 words$word) M)) (\ (w__37 : 64 words$word) . state_monad$returnS (SOME w__37)))) - else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then state_monad$bindS (state_monad$seqS - (state_monad$write_regS tselect_ref value) - (state_monad$read_regS tselect_ref : ( 64 words$word) M)) (\ (w__38 : 64 words$word) . state_monad$returnS (SOME w__38)) - else state_monad$returnS NONE) (\ (res : xlenbits option) . - state_monad$returnS ((case res of + ((writeCSR:(12)words$word ->(64)words$word ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) (csr : csreg) (value : xlenbits)= + (let b__0 = csr in sail2_state_monad$bindS + (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__0 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mstatus_ref ((legalize_mstatus w__0 value))) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__1 : Mstatus) . + sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__1 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS misa_ref) (\ (w__2 : Misa) . sail2_state_monad$bindS + (legalize_misa w__2 value) (\ (w__3 : Misa) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS misa_ref w__3) + (sail2_state_monad$read_regS misa_ref)) (\ (w__4 : Misa) . sail2_state_monad$returnS (SOME ((get_Misa_bits w__4 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS medeleg_ref) (\ (w__5 : Medeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS medeleg_ref ((legalize_medeleg w__5 value))) + (sail2_state_monad$read_regS medeleg_ref)) (\ (w__6 : Medeleg) . + sail2_state_monad$returnS (SOME ((get_Medeleg_bits w__6 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__7 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mideleg_ref ((legalize_mideleg w__7 value))) + (sail2_state_monad$read_regS mideleg_ref)) (\ (w__8 : Minterrupts) . + sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__8 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mie_ref) (\ (w__9 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mie_ref ((legalize_mie w__9 value))) + (sail2_state_monad$read_regS mie_ref)) (\ (w__10 : Minterrupts) . + sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__10 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mtvec_ref) (\ (w__11 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mtvec_ref ((legalize_tvec w__11 value))) + (sail2_state_monad$read_regS mtvec_ref)) (\ (w__12 : Mtvec) . + sail2_state_monad$returnS (SOME ((get_Mtvec_bits w__12 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mcounteren_ref) (\ (w__13 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mcounteren_ref ((legalize_mcounteren w__13 value))) + (sail2_state_monad$read_regS mcounteren_ref)) (\ (w__14 : Counteren) . + sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__14 : 32 words$word)) : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mscratch_ref value) + (sail2_state_monad$read_regS mscratch_ref : ( 64 words$word) M)) (\ (w__15 : 64 words$word) . sail2_state_monad$returnS (SOME w__15)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (legalize_xepc value : ( 64 words$word) M) (\ (w__16 : xlenbits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mepc_ref w__16) + (sail2_state_monad$read_regS mepc_ref : ( 64 words$word) M)) (\ (w__17 : 64 words$word) . sail2_state_monad$returnS (SOME w__17))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (set_Mcause_bits mcause_ref value) + (sail2_state_monad$read_regS mcause_ref)) (\ (w__18 : Mcause) . + sail2_state_monad$returnS (SOME ((get_Mcause_bits w__18 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mtval_ref value) + (sail2_state_monad$read_regS mtval_ref : ( 64 words$word) M)) (\ (w__19 : 64 words$word) . sail2_state_monad$returnS (SOME w__19)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__20 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mip_ref ((legalize_mip w__20 value))) + (sail2_state_monad$read_regS mip_ref)) (\ (w__21 : Minterrupts) . + sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__21 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS pmpcfg0_ref value) + (sail2_state_monad$read_regS pmpcfg0_ref : ( 64 words$word) M)) (\ (w__22 : 64 words$word) . sail2_state_monad$returnS (SOME w__22)) + else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS pmpaddr0_ref value) + (sail2_state_monad$read_regS pmpaddr0_ref : ( 64 words$word) M)) (\ (w__23 : 64 words$word) . sail2_state_monad$returnS (SOME w__23)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__24 : Mstatus) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mstatus_ref ((legalize_sstatus w__24 value))) + (sail2_state_monad$read_regS mstatus_ref)) (\ (w__25 : Mstatus) . + sail2_state_monad$returnS (SOME ((get_Mstatus_bits w__25 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS sedeleg_ref) (\ (w__26 : Sedeleg) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS sedeleg_ref ((legalize_sedeleg w__26 value))) + (sail2_state_monad$read_regS sedeleg_ref)) (\ (w__27 : Sedeleg) . + sail2_state_monad$returnS (SOME ((get_Sedeleg_bits w__27 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (set_Sinterrupts_bits sideleg_ref value) + (sail2_state_monad$read_regS sideleg_ref)) (\ (w__28 : Sinterrupts) . + sail2_state_monad$returnS (SOME ((get_Sinterrupts_bits w__28 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mie_ref) (\ (w__29 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__30 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mie_ref ((legalize_sie w__29 w__30 value))) + (sail2_state_monad$read_regS mie_ref)) (\ (w__31 : Minterrupts) . + sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__31 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS stvec_ref) (\ (w__32 : Mtvec) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS stvec_ref ((legalize_tvec w__32 value))) + (sail2_state_monad$read_regS stvec_ref)) (\ (w__33 : Mtvec) . + sail2_state_monad$returnS (SOME ((get_Mtvec_bits w__33 : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS scounteren_ref) (\ (w__34 : Counteren) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS scounteren_ref ((legalize_scounteren w__34 value))) + (sail2_state_monad$read_regS scounteren_ref)) (\ (w__35 : Counteren) . + sail2_state_monad$returnS (SOME ((EXTZ (( 64 : int):ii) ((get_Counteren_bits w__35 : 32 words$word)) : 64 words$word))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS sscratch_ref value) + (sail2_state_monad$read_regS sscratch_ref : ( 64 words$word) M)) (\ (w__36 : 64 words$word) . sail2_state_monad$returnS (SOME w__36)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : 12 words$word)))) then sail2_state_monad$bindS + (legalize_xepc value : ( 64 words$word) M) (\ (w__37 : xlenbits) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS sepc_ref w__37) + (sail2_state_monad$read_regS sepc_ref : ( 64 words$word) M)) (\ (w__38 : 64 words$word) . sail2_state_monad$returnS (SOME w__38))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (set_Mcause_bits scause_ref value) + (sail2_state_monad$read_regS scause_ref)) (\ (w__39 : Mcause) . + sail2_state_monad$returnS (SOME ((get_Mcause_bits w__39 : 64 words$word)))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS stval_ref value) + (sail2_state_monad$read_regS stval_ref : ( 64 words$word) M)) (\ (w__40 : 64 words$word) . sail2_state_monad$returnS (SOME w__40)) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__41 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__42 : Minterrupts) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mip_ref ((legalize_sip w__41 w__42 value))) + (sail2_state_monad$read_regS mip_ref)) (\ (w__43 : Minterrupts) . + sail2_state_monad$returnS (SOME ((get_Minterrupts_bits w__43 : 64 words$word)))))) + else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS + (cur_Architecture () ) (\ (w__44 : Architecture) . sail2_state_monad$bindS + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M) (\ (w__45 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS satp_ref ((legalize_satp w__44 w__45 value : 64 words$word))) + (sail2_state_monad$read_regS satp_ref : ( 64 words$word) M)) (\ (w__46 : 64 words$word) . sail2_state_monad$returnS (SOME w__46)))) + else if (((b__0 = (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS tselect_ref value) + (sail2_state_monad$read_regS tselect_ref : ( 64 words$word) M)) (\ (w__47 : 64 words$word) . sail2_state_monad$returnS (SOME w__47)) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS mcycle_ref value) + (sail2_state_monad$read_regS mcycle_ref : ( 64 words$word) M)) (\ (w__48 : 64 words$word) . sail2_state_monad$returnS (SOME w__48)) + else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : 12 words$word)))) then sail2_state_monad$bindS (sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS minstret_ref value) + (sail2_state_monad$write_regS minstret_written_ref T)) + (sail2_state_monad$read_regS minstret_ref : ( 64 words$word) M)) (\ (w__49 : 64 words$word) . sail2_state_monad$returnS (SOME w__49)) + else sail2_state_monad$returnS NONE) (\ (res : xlenbits option) . + sail2_state_monad$returnS ((case res of SOME (v) => - prerr_endline + print_endline ((STRCAT "CSR " ((STRCAT ((csr_name csr)) ((STRCAT " <- " - ((STRCAT ((string_of_vec v)) - ((STRCAT " (input: " ((STRCAT ((string_of_vec value)) ")")))))))))))) + ((STRCAT ((string_of_bits v)) + ((STRCAT " (input: " ((STRCAT ((string_of_bits value)) ")")))))))))))) | NONE => print_bits "unhandled write to CSR " csr )))))`; +(*val maybe_i_forwards : bool -> string*) + val _ = Define ` - ((decode:(32)words$word ->(ast)option) v__0= - (if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (UTYPE (imm,rd,RISCV_LUI)) - else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (UTYPE (imm,rd,RISCV_AUIPC)) - else if (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word)))) then - let (imm : 20 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) - ((concat_vec - ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm (( 18 : int):ii) (( 13 : int):ii) : 6 words$word)) - ((concat_vec - ((subrange_vec_dec imm (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 20 words$word)) - : 21 words$word),rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RISCV_JALR (imm,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BEQ)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BNE)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BLT)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BGE)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BLTU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):ii))) : 1 words$word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):ii))) : 1 words$word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):ii) (( 0 : int):ii) : 6 words$word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) - (vec_of_bits [B0] : 1 words$word) - : 5 words$word)) - : 11 words$word)) - : 12 words$word)) - : 13 words$word),rs2,rs1,RISCV_BGEU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ADDI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_SLTI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_XORI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ORI)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ITYPE (imm,rs1,rd,RISCV_ANDI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 6 bits) = ((subrange_vec_dec v__0 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_ADD)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SUB)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLL)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLT)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_XOR)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SRL)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_SRA)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_OR)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPE (rs2,rs1,rd,RISCV_AND)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOAD (imm,rs1,rd,T,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,BYTE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,HALF,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,WORD,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) then - let (imm7 : 7 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (imm5 : 5 bits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,DOUBLE,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word))))))) then - let (imm : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (ADDIW (imm,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (shamt : 5 bits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,F,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,T,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,T,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (MUL (rs2,rs1,rd,T,F,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (DIV0 (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (DIV0 (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (REM (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (REM (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (MULW (rs2,rs1,rd)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (DIVW (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (DIVW (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (REMW (rs2,rs1,rd,T)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))))))))) then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (REMW (rs2,rs1,rd,F)) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):ii) (( 0 : int):ii) : 20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] - : 20 words$word))))))) then - let (pred : 4 bits) = ((subrange_vec_dec v__0 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in - let (succ : 4 bits) = ((subrange_vec_dec v__0 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in - SOME (FENCE (pred,succ)) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0; - B0;B0;B0;B0;B1;B1;B1;B1] - : 32 words$word)))) then - SOME (FENCEI () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (ECALL () ) - else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (MRET () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (SRET () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (EBREAK () ) - else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B1;B1;B1;B0;B0;B1;B1] - : 32 words$word)))) then - SOME (WFI () ) - else if ((((((((subrange_vec_dec v__0 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):ii) (( 0 : int):ii) : 15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : 15 words$word))))))) - then - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - SOME (SFENCE_VMA (rs1,rs2)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd)) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : 5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word)))))))))) then - let aq = (access_vec_dec v__0 (( 26 : int):ii)) in - let rl = (access_vec_dec v__0 (( 25 : int):ii)) in - let (rs2 : regbits) = ((subrange_vec_dec v__0 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRW)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRS)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,F,CSRRC)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRW)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRS)) - else if ((((((((subrange_vec_dec v__0 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) then - let (csr : 12 bits) = ((subrange_vec_dec v__0 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in - let (rs1 : regbits) = ((subrange_vec_dec v__0 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__0 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - SOME (CSR (csr,rs1,rd,T,CSRRC)) + ((maybe_i_forwards:bool -> string) arg_= ((case arg_ of T => "i" | F => "" )))`; + + +(*val maybe_i_backwards : string -> bool*) + +val _ = Define ` + ((maybe_i_backwards:string -> bool) arg_= ((case arg_ of "i" => T | "" => F )))`; + + +(*val maybe_i_forwards_matches : bool -> bool*) + +val _ = Define ` + ((maybe_i_forwards_matches:bool -> bool) arg_= + ((case arg_ of T => T | F => T )))`; + + +(*val maybe_i_backwards_matches : string -> bool*) + +val _ = Define ` + ((maybe_i_backwards_matches:string -> bool) arg_= ((case arg_ of "i" => T | "" => T | _ => F )))`; + + +(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*) + +val _ = Define ` + ((maybe_i_matches_prefix:string ->(bool#int)option) arg_= + (let stringappend_1614_0 = arg_ in + if (((((string_startswith stringappend_1614_0 "i")) /\ ( + (case ((string_drop stringappend_1614_0 ((string_length "i")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1614_0 ((string_length "i")))) of + s_ => SOME (T, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1614_0 "")) /\ ( + (case ((string_drop stringappend_1614_0 ((string_length "")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1614_0 ((string_length "")))) of + s_ => SOME (F, ((string_length arg_)) - ((string_length s_))) + ) else NONE))`; +(*val csr_mnemonic_forwards : csrop -> string*) + val _ = Define ` - ((decodeCompressed:(16)words$word ->(ast)option) v__418= - (if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzi1 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (nzi0 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + ((csr_mnemonic_forwards:csrop -> string) arg_= + ((case arg_ of CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" )))`; + + +(*val csr_mnemonic_backwards : string -> csrop*) + +val _ = Define ` + ((csr_mnemonic_backwards:string -> csrop) arg_= + ((case arg_ of "csrrw" => CSRRW | "csrrs" => CSRRS | "csrrc" => CSRRC )))`; + + +(*val csr_mnemonic_forwards_matches : csrop -> bool*) + +val _ = Define ` + ((csr_mnemonic_forwards_matches:csrop -> bool) arg_= + ((case arg_ of CSRRW => T | CSRRS => T | CSRRC => T )))`; + + +(*val csr_mnemonic_backwards_matches : string -> bool*) + +val _ = Define ` + ((csr_mnemonic_backwards_matches:string -> bool) arg_= + ((case arg_ of "csrrw" => T | "csrrs" => T | "csrrc" => T | _ => F )))`; + + +(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*) + +val _ = Define ` + ((csr_mnemonic_matches_prefix:string ->(csrop#int)option) arg_= + (let stringappend_1611_0 = arg_ in + if (((((string_startswith stringappend_1611_0 "csrrw")) /\ ( + (case ((string_drop stringappend_1611_0 ((string_length "csrrw")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1611_0 ((string_length "csrrw")))) of + s_ => SOME (CSRRW, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1611_0 "csrrs")) /\ ( + (case ((string_drop stringappend_1611_0 ((string_length "csrrs")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1611_0 ((string_length "csrrs")))) of + s_ => SOME (CSRRS, ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_1611_0 "csrrc")) /\ ( + (case ((string_drop stringappend_1611_0 ((string_length "csrrc")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_1611_0 ((string_length "csrrc")))) of + s_ => SOME (CSRRC, ((string_length arg_)) - ((string_length s_))) + ) + else NONE))`; + + +val _ = Define ` + ((decodeCompressed:(16)words$word ->(ast)option) v__2= + (if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi1 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (nzi0 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in if ((((((nzi1 = (vec_of_bits [B0] : 1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) then SOME (NOP () ) else NONE - else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then - SOME (ILLEGAL () ) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (nz54 : 2 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in - let (nz96 : 4 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in - let (nz2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in - let (nz3 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in - let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (nz54 : 2 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 11 : int):ii) : 2 words$word)) in + let (nz96 : 4 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 7 : int):ii) : 4 words$word)) in + let (nz2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (nz3 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let nzimm = ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 : 2 words$word)) : 4 words$word)) : 8 words$word)) in if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word)))) then NONE else SOME (C_ADDI4SPN (rd,nzimm)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in - let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in - let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in - let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (ui6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in SOME (C_LW (uimm,rs1,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in - let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in - let (rd : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (rd : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in SOME (C_LD (uimm,rs1,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in - let (rs1 : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (ui2 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in - let (ui6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui2 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (ui6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 : 4 words$word)) : 5 words$word)) in SOME (C_SW (uimm,rs1,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then - let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in - let (rs1 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in - let (rs2 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (rs1 : 3 bits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (rs2 : 3 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let uimm = ((concat_vec ui76 ui53 : 5 words$word)) in SOME (C_SD (uimm,rs1,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (nzi40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (nzi5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (nzi40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let nzi = ((concat_vec nzi5 nzi40 : 6 words$word)) in if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then NONE else SOME (C_ADDI (nzi,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in SOME (C_ADDIW ((concat_vec imm5 imm40 : 6 words$word),rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (imm40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE else SOME (C_LI ((concat_vec imm5 imm40 : 6 words$word),rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzi9 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (nzi4 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in - let (nzi6 : 1 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in - let (nzi87 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in - let (nzi5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzi9 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (nzi4 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (nzi6 : 1 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 5 : int):ii) : 1 words$word)) in + let (nzi87 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (nzi5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in let nzimm = ((concat_vec nzi9 ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 : 2 words$word)) : 3 words$word)) @@ -6169,65 +11909,65 @@ val _ = Define ` : 6 words$word)) in if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE else SOME (C_ADDI16SP nzimm) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (imm17 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (imm1612 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (imm17 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (imm1612 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then NONE else SOME (C_LUI ((concat_vec imm17 imm1612 : 6 words$word),rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE else SOME (C_SRLI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) then NONE else SOME (C_SRAI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (i40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B0] : 3 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in SOME (C_ANDI ((concat_vec i5 i40 : 6 words$word),rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_SUB (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_XOR (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_OR (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_AND (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_SUBW (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then - let (rsd : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : cregbits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 10 : int):ii) : 6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1] : 6 words$word)))) /\ ((((((((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))))))))) then + let (rsd : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : cregbits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in SOME (C_ADDW (rsd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i11 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (i4 : 1 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in - let (i98 : 2 bits) = ((subrange_vec_dec v__418 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in - let (i10 : 1 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in - let (i6 : 1 bits) = ((subrange_vec_dec v__418 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in - let (i7 : 1 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in - let (i31 : 3 bits) = ((subrange_vec_dec v__418 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in - let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B0;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i11 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i4 : 1 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in + let (i98 : 2 bits) = ((subrange_vec_dec v__2 (( 10 : int):ii) (( 9 : int):ii) : 2 words$word)) in + let (i10 : 1 bits) = ((subrange_vec_dec v__2 (( 8 : int):ii) (( 8 : int):ii) : 1 words$word)) in + let (i6 : 1 bits) = ((subrange_vec_dec v__2 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let (i7 : 1 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 6 : int):ii) : 1 words$word)) in + let (i31 : 3 bits) = ((subrange_vec_dec v__2 (( 5 : int):ii) (( 3 : int):ii) : 3 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in SOME (C_J ((concat_vec i11 ((concat_vec i10 ((concat_vec i98 @@ -6239,231 +11979,263 @@ val _ = Define ` : 9 words$word)) : 10 words$word)) : 11 words$word))) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in - let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in - let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in - let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i43 : 2 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (rs : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (i21 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in SOME (C_BEQZ ((concat_vec i8 ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) : 7 words$word)) : 8 words$word),rs)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then - let (i8 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (i43 : 2 bits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in - let (rs : cregbits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (i76 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in - let (i21 : 2 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in - let (i5 : 1 bits) = ((subrange_vec_dec v__418 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + let (i8 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (i43 : 2 bits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 10 : int):ii) : 2 words$word)) in + let (rs : cregbits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (i76 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (i21 : 2 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 3 : int):ii) : 2 words$word)) in + let (i5 : 1 bits) = ((subrange_vec_dec v__2 (( 2 : int):ii) (( 2 : int):ii) : 1 words$word)) in SOME (C_BNEZ ((concat_vec i8 ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 : 4 words$word)) : 5 words$word)) : 7 words$word)) : 8 words$word),rs)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (nzui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (nzui40 : 5 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (nzui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (nzui40 : 5 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let (shamt : 6 bits) = ((concat_vec nzui5 nzui40 : 6 words$word)) in if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then NONE else SOME (C_SLLI (shamt,rsd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (ui42 : 3 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 4 : int):ii) : 3 words$word)) in - let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (ui42 : 3 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 4 : int):ii) : 3 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 3 : int):ii) (( 2 : int):ii) : 2 words$word)) in let (uimm : 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 : 4 words$word)) : 6 words$word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE else SOME (C_LWSP (uimm,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui5 : 1 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in - let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (ui43 : 2 bits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in - let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui5 : 1 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (ui43 : 2 bits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let (ui86 : 3 bits) = ((subrange_vec_dec v__2 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in let (uimm : 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 : 3 words$word)) : 6 words$word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE else SOME (C_LDSP (uimm,rd)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui52 : 4 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) in - let (ui76 : 2 bits) = ((subrange_vec_dec v__418 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B0] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui52 : 4 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 9 : int):ii) : 4 words$word)) in + let (ui76 : 2 bits) = ((subrange_vec_dec v__2 (( 8 : int):ii) (( 7 : int):ii) : 2 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let (uimm : 6 bits) = ((concat_vec ui76 ui52 : 6 words$word)) in SOME (C_SWSP (uimm,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (ui53 : 3 bits) = ((subrange_vec_dec v__418 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in - let (ui86 : 3 bits) = ((subrange_vec_dec v__418 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 13 : int):ii) : 3 words$word)) = (vec_of_bits [B1;B1;B1] : 3 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (ui53 : 3 bits) = ((subrange_vec_dec v__2 (( 12 : int):ii) (( 10 : int):ii) : 3 words$word)) in + let (ui86 : 3 bits) = ((subrange_vec_dec v__2 (( 9 : int):ii) (( 7 : int):ii) : 3 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in let (uimm : 6 bits) = ((concat_vec ui86 ui53 : 6 words$word)) in SOME (C_SDSP (uimm,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then - let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE else SOME (C_JR rs1) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then - let (rs1 : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : 7 words$word))))))) then + let (rs1 : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE else SOME (C_JALR rs1) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (rd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B0] : 4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then NONE else SOME (C_MV (rd,rs2)) - else if ((((((((subrange_vec_dec v__418 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then - let (rsd : regbits) = ((subrange_vec_dec v__418 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in - let (rs2 : regbits) = ((subrange_vec_dec v__418 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 : int):ii) (( 12 : int):ii) : 4 words$word)) = (vec_of_bits [B1;B0;B0;B1] : 4 words$word)))) /\ (((((subrange_vec_dec v__2 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + let (rsd : regbits) = ((subrange_vec_dec v__2 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (rs2 : regbits) = ((subrange_vec_dec v__2 (( 6 : int):ii) (( 2 : int):ii) : 5 words$word)) in if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then NONE else SOME (C_ADD (rsd,rs2)) + else if (((v__2 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 16 words$word)))) then + SOME (C_ILLEGAL () ) else NONE))`; -(*val execute_WFI : unit -> M unit*) +(*val execute_WFI : unit -> M bool*) val _ = Define ` - ((execute_WFI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__110= (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + ((execute_WFI:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__26= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . (case w__0 of - Machine => state_monad$returnS () - | Supervisor => state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . - if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then - handle_illegal () - else state_monad$returnS () ) - | User => handle_illegal () + Machine => sail2_state_monad$returnS T + | Supervisor => sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + if (((((get_Mstatus_TW w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS + (handle_illegal () ) (sail2_state_monad$returnS F) + else sail2_state_monad$returnS T) + | User => sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F) ))))`; -(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*) +(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M bool*) val _ = Define ` - ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd op= + ((execute_UTYPE:(20)words$word ->(5)words$word -> uop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd op= (let (off : xlenbits) = ((EXTS (( 64 : int):ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) : 32 words$word)) - : 64 words$word)) in state_monad$bindS + : 64 words$word)) in sail2_state_monad$bindS (case op of - RISCV_LUI => state_monad$returnS off - | RISCV_AUIPC => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - state_monad$returnS ((add_vec w__0 off : 64 words$word))) - ) (\ (ret : xlenbits) . - wX ((regbits_to_regno rd)) ret)))`; + RISCV_LUI => sail2_state_monad$returnS off + | RISCV_AUIPC => sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$returnS ((add_vec w__0 off : 64 words$word))) + ) (\ (ret : xlenbits) . sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ret) (sail2_state_monad$returnS T))))`; -(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) +(*val execute_THREAD_START : unit -> bool*) val _ = Define ` - ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (state_monad$bindS - (speculate_conditional_success () ) (\ (w__0 : bool) . - let (status : 1 bits) = - (if w__0 then (vec_of_bits [B0] : 1 words$word) - else (vec_of_bits [B1] : 1 words$word)) in state_monad$seqS - (wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):ii) status : 64 words$word))) - (if (((status = (vec_of_bits [B1] : 1 words$word)))) then state_monad$returnS () - else state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS + ((execute_THREAD_START:unit -> bool) g__29= T)`; + + +(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*) + + val _ = Define ` + ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs2 rs1 width rd= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . + let (aligned : bool) = + ((case width of + BYTE => T + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)) + | WORD => + (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)) + | DOUBLE => + (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)) + )) in + if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS + (speculate_conditional_success vaddr) (\ (w__0 : bool) . + if (((((bool_to_bits w__0 : 1 words$word)) = ((bool_to_bits F : 1 words$word))))) then sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):ii) (vec_of_bits [B1] : 1 words$word) : 64 words$word))) + (sail2_state_monad$returnS T) + else sail2_state_monad$bindS + (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . + (case w__1 of + TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F) + | TR_Address (addr) => sail2_state_monad$bindS + (case width of + WORD => mem_write_ea addr (( 4 : int):ii) aq rl T + | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (eares : unit MemoryOpResult) . + (case eares of + MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + | MemValue (_) => sail2_state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . sail2_state_monad$bindS + (case width of + WORD => + mem_write_value addr (( 4 : int):ii) + ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq rl T + | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl T + | _ => internal_error "STORECON expected word or double" + ) (\ (res : unit MemoryOpResult) . + (case res of + MemValue (_) => sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) + ((EXTZ (( 64 : int):ii) (vec_of_bits [B0] : 1 words$word) : 64 words$word))) + (let (_ : unit) = (cancel_reservation () ) in + sail2_state_monad$returnS T) + | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + ))) + )) + ))))))`; + + +(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M bool*) + + val _ = Define ` + ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 width aq rl= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in + if ((check_misaligned vaddr width)) then sail2_state_monad$seqS + (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => state_monad$bindS + TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F) + | TR_Address (addr) => sail2_state_monad$bindS (case width of - WORD => mem_write_ea addr (( 4 : int):ii) aq rl T - | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl T - | _ => internal_error "STORECON expected word or double" + BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F + | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F + | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F + | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F ) (\ (eares : unit MemoryOpResult) . (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => state_monad$bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . state_monad$bindS + MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + | MemValue (_) => sail2_state_monad$bindS + (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . sail2_state_monad$bindS (case width of - WORD => + BYTE => + mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) aq + rl F + | HALF => + mem_write_value addr (( 2 : int):ii) ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) + aq rl F + | WORD => mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) - aq rl T - | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl T - | _ => internal_error "STORECON expected word or double" + aq rl F + | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl F ) (\ (res : unit MemoryOpResult) . (case res of - MemValue (_) => state_monad$returnS () - | MemException (e) => handle_mem_exception addr e + MemValue (_) => sail2_state_monad$returnS T + | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) ))) )) - )))))))`; + )))))`; -(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*) +(*val execute_STOP_FETCHING : unit -> bool*) val _ = Define ` - ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in state_monad$bindS - (translateAddr vaddr Write Data) (\ (w__1 : TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => state_monad$bindS - (case width of - BYTE => mem_write_ea addr (( 1 : int):ii) aq rl F - | HALF => mem_write_ea addr (( 2 : int):ii) aq rl F - | WORD => mem_write_ea addr (( 4 : int):ii) aq rl F - | DOUBLE => mem_write_ea addr (( 8 : int):ii) aq rl F - ) (\ (eares : unit MemoryOpResult) . - (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => state_monad$bindS - (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . state_monad$bindS - (case width of - BYTE => - mem_write_value addr (( 1 : int):ii) ((subrange_vec_dec rs2_val (( 7 : int):ii) (( 0 : int):ii) : 8 words$word)) aq - rl F - | HALF => - mem_write_value addr (( 2 : int):ii) ((subrange_vec_dec rs2_val (( 15 : int):ii) (( 0 : int):ii) : 16 words$word)) aq - rl F - | WORD => - mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec rs2_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) aq - rl F - | DOUBLE => mem_write_value addr (( 8 : int):ii) rs2_val aq rl F - ) (\ (res : unit MemoryOpResult) . - (case res of - MemValue (_) => state_monad$returnS () - | MemException (e) => handle_mem_exception addr e - ))) - )) - )))))`; + ((execute_STOP_FETCHING:unit -> bool) g__28= T)`; -(*val execute_SRET : unit -> M unit*) +(*val execute_SRET : unit -> M bool*) val _ = Define ` - ((execute_SRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__108= (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + ((execute_SRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__24= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS (case w__0 of User => handle_illegal () - | Supervisor => state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . + | Supervisor => sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . if (((((get_Mstatus_TSR w__1 : 1 words$word)) = ((bool_to_bits T : 1 words$word))))) then handle_illegal () - else state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . state_monad$bindS + else sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__2 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__3 : 64 words$word) . sail2_state_monad$bindS (handle_exception w__2 (CTL_SRET () ) w__3 : ( 64 words$word) M) (\ (w__4 : xlenbits) . - state_monad$write_regS nextPC_ref w__4)))) - | Machine => state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . state_monad$bindS + sail2_state_monad$write_regS nextPC_ref w__4)))) + | Machine => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__5 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . sail2_state_monad$bindS (handle_exception w__5 (CTL_SRET () ) w__6 : ( 64 words$word) M) (\ (w__7 : xlenbits) . - state_monad$write_regS nextPC_ref w__7))) - ))))`; + sail2_state_monad$write_regS nextPC_ref w__7))) + ) + (sail2_state_monad$returnS F))))`; -(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*) +(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M bool*) val _ = Define ` - ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op= (state_monad$bindS + ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in let (result : 32 bits) = @@ -6471,62 +12243,66 @@ val _ = Define ` RISCV_SLLI => (shift_bits_left rs1_val shamt : 32 words$word) | RISCV_SRLI => (shift_bits_right rs1_val shamt : 32 words$word) | RISCV_SRAI => (shift_right_arith32 rs1_val shamt : 32 words$word) - )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word)))))`; + )) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))) (sail2_state_monad$returnS T))))`; -(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*) +(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M bool*) val _ = Define ` - ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) shamt rs1 rd op= (state_monad$bindS + ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> sop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) shamt rs1 rd op= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . let (result : xlenbits) = ((case op of RISCV_SLLI => (shift_bits_left rs1_val shamt : 64 words$word) | RISCV_SRLI => (shift_bits_right rs1_val shamt : 64 words$word) | RISCV_SRAI => (shift_right_arith64 rs1_val shamt : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result)))`; + )) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T))))`; -(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*) +(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M bool*) val _ = Define ` - ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs1 rs2= (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs1 rs2= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits User : 2 words$word))))) - then - handle_illegal () - else state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . state_monad$bindS - (state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . - let p__104 = + then sail2_state_monad$seqS + (handle_illegal () ) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__1 : Mstatus) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mstatus_ref) (\ (w__2 : Mstatus) . + let p__20 = (architecture ((get_Mstatus_SXL w__1 : 2 words$word)), (get_Mstatus_TVM w__2 : 1 words$word)) in - (case p__104 of + (case p__20 of (SOME (RV64), v_0) => - if (((v_0 = ((bool_to_bits T : 1 words$word))))) then handle_illegal () - else state_monad$bindS - (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then state_monad$returnS NONE - else state_monad$bindS + if (((v_0 = ((bool_to_bits T : 1 words$word))))) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F) + else if (((v_0 = ((bool_to_bits F : 1 words$word))))) then sail2_state_monad$bindS + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE + else sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__3 : 64 words$word) . - state_monad$returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))))) (\ (addr : - vaddr39 option) . state_monad$bindS - (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then state_monad$returnS NONE - else state_monad$bindS + sail2_state_monad$returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):ii) (( 0 : int):ii) : 39 words$word))))) (\ (addr : + vaddr39 option) . sail2_state_monad$bindS + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then sail2_state_monad$returnS NONE + else sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__4 : 64 words$word) . - state_monad$returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))))) (\ (asid : - asid64 option) . - flushTLB asid addr)) - | (g__102, g__103) => internal_error "unimplemented sfence architecture" + sail2_state_monad$returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):ii) (( 0 : int):ii) : 16 words$word))))) (\ (asid : + asid64 option) . sail2_state_monad$seqS + (flushTLB asid addr) (sail2_state_monad$returnS T))) + else + (case (SOME RV64, v_0) of + (g__18, g__19) => internal_error "unimplemented sfence architecture" + ) + | (g__18, g__19) => internal_error "unimplemented sfence architecture" ))))))`; -(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*) +(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M bool*) val _ = Define ` - ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (state_monad$bindS + ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> ropw ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in let (result : 32 bits) = @@ -6542,15 +12318,15 @@ val _ = Define ` | RISCV_SRAW => (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) : 32 words$word) - )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))))))`; + )) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) result : 64 words$word))) (sail2_state_monad$returnS T)))))`; -(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*) +(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M bool*) val _ = Define ` - ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd op= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> rop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd op= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . let (result : xlenbits) = ((case op of @@ -6572,74 +12348,76 @@ val _ = Define ` : 64 words$word) | RISCV_OR => (or_vec rs1_val rs2_val : 64 words$word) | RISCV_AND => (and_vec rs1_val rs2_val : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result))))`; + )) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`; -(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M bool*) val _ = Define ` - ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd= (state_monad$bindS - (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$bindS (state_monad$seqS + ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS (wX ((regbits_to_regno rd)) w__0) (rX ((regbits_to_regno rs1)) : ( 64 words$word) M)) (\ (w__1 : 64 words$word) . - let (newPC : xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in - state_monad$write_regS + let (newPC : xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref ((concat_vec ((subrange_vec_dec newPC (( 63 : int):ii) (( 1 : int):ii) : 63 words$word)) (vec_of_bits [B0] : 1 words$word) - : 64 words$word))))))`; + : 64 words$word))) + (sail2_state_monad$returnS T)))))`; -(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*) +(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M bool*) val _ = Define ` - ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rd= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (pc : xlenbits) . state_monad$bindS - (state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . state_monad$seqS + ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rd= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (pc : xlenbits) . sail2_state_monad$bindS + (sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$seqS (wX ((regbits_to_regno rd)) w__0) - (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in - state_monad$write_regS nextPC_ref ((add_vec pc offset : 64 words$word)))))))`; + (let (offset : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref ((add_vec pc offset : 64 words$word))) (sail2_state_monad$returnS T))))))`; -(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) val _ = Define ` - ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r : 32 words$word)) : 64 words$word))))))`; + let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) r : 32 words$word)) : 64 words$word))) + (sail2_state_monad$returnS T)))))`; -(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) val _ = Define ` - ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in - let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((to_bits xlen r : 64 words$word))))))`; + let (r : ii) = (if (((rs2_int = (( 0 : int):ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((to_bits xlen r : 64 words$word))) (sail2_state_monad$returnS T)))))`; -(*val execute_NOP : unit -> unit*) +(*val execute_NOP : unit -> bool*) val _ = Define ` - ((execute_NOP:unit -> unit) g__111= () )`; + ((execute_NOP:unit -> bool) g__27= T)`; -(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M bool*) val _ = Define ` - ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd= (state_monad$bindS + ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in let (rs1_int : ii) = (integer_word$w2i rs1_val) in @@ -6648,97 +12426,113 @@ val _ = Define ` ((subrange_vec_dec ((to_bits (( 64 : int):ii) ((rs1_int * rs2_int)) : 64 words$word)) (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in - let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32 : 64 words$word)) in - wX ((regbits_to_regno rd)) result))))`; + let (result : xlenbits) = ((EXTS (( 64 : int):ii) result32 : 64 words$word)) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`; -(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*) +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M bool*) val _ = Define ` - ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . let (rs1_int : ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in let (rs2_int : ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in let result128 = ((to_bits (( 128 : int):ii) ((rs1_int * rs2_int)) : 128 words$word)) in let result = (if high then (subrange_vec_dec result128 (( 127 : int):ii) (( 64 : int):ii) : 64 words$word) - else (subrange_vec_dec result128 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) in - wX ((regbits_to_regno rd)) result))))`; + else (subrange_vec_dec result128 (( 63 : int):ii) (( 0 : int):ii) : 64 words$word)) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T)))))`; -(*val execute_MRET : unit -> M unit*) +(*val execute_MRET : unit -> M bool*) val _ = Define ` - ((execute_MRET:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__107= (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . - if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) - then state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$bindS - (handle_exception w__1 (CTL_MRET () ) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . - state_monad$write_regS nextPC_ref w__3))) - else handle_illegal () )))`; + ((execute_MRET:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__23= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$seqS + (if (((((privLevel_to_bits w__0 : 2 words$word)) = ((privLevel_to_bits Machine : 2 words$word))))) + then sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS + (handle_exception w__1 (CTL_MRET () ) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . + sail2_state_monad$write_regS nextPC_ref w__3))) + else handle_illegal () ) + (sail2_state_monad$returnS F))))`; -(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*) +(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M bool*) val _ = Define ` - ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) aq rl rs1 width rd= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS - (translateAddr vaddr Read Data) (\ (w__0 : TR_Result) . - (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - WORD => state_monad$bindS - (mem_read addr (( 4 : int):ii) aq rl T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__1 : ( 32 words$word) - MemoryOpResult) . - process_load rd addr w__1 F) - | DOUBLE => state_monad$bindS - (mem_read addr (( 8 : int):ii) aq rl T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__2 : ( 64 words$word) - MemoryOpResult) . - process_load rd addr w__2 F) - | _ => internal_error "LOADRES expected WORD or DOUBLE" - ) - )))))`; + ((execute_LOADRES:bool -> bool ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) aq rl rs1 width rd= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . + let (aligned : bool) = + ((case width of + BYTE => T + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 : int):ii))) : 1 words$word)) = (vec_of_bits [B0] : 1 words$word)) + | WORD => + (((subrange_vec_dec vaddr (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)) + | DOUBLE => + (((subrange_vec_dec vaddr (( 2 : int):ii) (( 0 : int):ii) : 3 words$word)) = (vec_of_bits [B0;B0;B0] : 3 words$word)) + )) in + if ((~ aligned)) then sail2_state_monad$seqS (handle_mem_exception vaddr E_SAMO_Addr_Align) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS + (translateAddr vaddr Read Data) (\ (w__0 : TR_Result) . + (case w__0 of + TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F) + | TR_Address (addr) => + (case width of + WORD => sail2_state_monad$bindS + (mem_read addr (( 4 : int):ii) aq rl T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__1 : ( 32 words$word) + MemoryOpResult) . + process_loadres rd vaddr w__1 F) + | DOUBLE => sail2_state_monad$bindS + (mem_read addr (( 8 : int):ii) aq rl T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__3 : ( 64 words$word) + MemoryOpResult) . + process_loadres rd vaddr w__3 F) + | _ => internal_error "LOADRES expected WORD or DOUBLE" + ) + )))))`; -(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*) +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M bool*) val _ = Define ` - ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl= (state_monad$bindS + ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> word_width -> bool -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in state_monad$bindS - (translateAddr vaddr Read Data) (\ (w__1 : TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - BYTE => state_monad$bindS - (mem_read addr (( 1 : int):ii) aq rl F : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word) - MemoryOpResult) . - process_load rd vaddr w__2 is_unsigned) - | HALF => state_monad$bindS - (mem_read addr (( 2 : int):ii) aq rl F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__3 : ( 16 words$word) - MemoryOpResult) . - process_load rd vaddr w__3 is_unsigned) - | WORD => state_monad$bindS - (mem_read addr (( 4 : int):ii) aq rl F : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word) - MemoryOpResult) . - process_load rd vaddr w__4 is_unsigned) - | DOUBLE => state_monad$bindS - (mem_read addr (( 8 : int):ii) aq rl F : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word) - MemoryOpResult) . - process_load rd vaddr w__5 is_unsigned) - ) - )))))`; - - -(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + let (vaddr : xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word)) in + if ((check_misaligned vaddr width)) then sail2_state_monad$seqS + (handle_mem_exception vaddr E_Load_Addr_Align) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS + (translateAddr vaddr Read Data) (\ (w__1 : TR_Result) . + (case w__1 of + TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F) + | TR_Address (addr) => + (case width of + BYTE => sail2_state_monad$bindS + (mem_read addr (( 1 : int):ii) aq rl F : ( ( 8 words$word)MemoryOpResult) M) (\ (w__2 : ( 8 words$word) + MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => sail2_state_monad$bindS + (mem_read addr (( 2 : int):ii) aq rl F : ( ( 16 words$word)MemoryOpResult) M) (\ (w__4 : ( 16 words$word) + MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | WORD => sail2_state_monad$bindS + (mem_read addr (( 4 : int):ii) aq rl F : ( ( 32 words$word)MemoryOpResult) M) (\ (w__6 : ( 32 words$word) + MemoryOpResult) . + process_load rd vaddr w__6 is_unsigned) + | DOUBLE => sail2_state_monad$bindS + (mem_read addr (( 8 : int):ii) aq rl F : ( ( 64 words$word)MemoryOpResult) M) (\ (w__8 : ( 64 words$word) + MemoryOpResult) . + process_load rd vaddr w__8 is_unsigned) + ) + )))))`; + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M bool*) val _ = Define ` - ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd op= (state_monad$bindS + ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> iop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd op= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . let (immext : xlenbits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in let (result : xlenbits) = @@ -6751,48 +12545,61 @@ val _ = Define ` | RISCV_XORI => (xor_vec rs1_val immext : 64 words$word) | RISCV_ORI => (or_vec rs1_val immext : 64 words$word) | RISCV_ANDI => (and_vec rs1_val immext : 64 words$word) - )) in - wX ((regbits_to_regno rd)) result)))`; + )) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) result) (sail2_state_monad$returnS T))))`; -(*val execute_ILLEGAL : unit -> M unit*) +(*val execute_ILLEGAL : mword ty32 -> M bool*) val _ = Define ` - ((execute_ILLEGAL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__112= (handle_illegal () ))`; + ((execute_ILLEGAL:(32)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) s= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)))`; -(*val execute_FENCEI : unit -> M unit*) +(*val execute_FENCEI : unit -> M bool*) val _ = Define ` - ((execute_FENCEI:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__105= (MEM_fence_i () ))`; + ((execute_FENCEI:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__21= (sail2_state_monad$seqS (MEM_fence_i () ) (sail2_state_monad$returnS T)))`; -(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*) +(*val execute_FENCE : mword ty4 -> mword ty4 -> M bool*) val _ = Define ` - ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) pred succ= - ((case (pred, succ) of - (b__0, b__1) => - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then - MEM_fence_rw_rw () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then - MEM_fence_r_rw () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then - MEM_fence_r_r () else - if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\ - (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then - MEM_fence_rw_w () else MEM_fence_w_w () - )))`; + ((execute_FENCE:(4)words$word ->(4)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) pred succ= (sail2_state_monad$seqS + (case (pred, succ) of + (v__132, v__133) => + if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + MEM_fence_rw_rw () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + MEM_fence_r_rw () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + MEM_fence_r_r () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + MEM_fence_rw_w () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + MEM_fence_w_w () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + MEM_fence_w_rw () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + MEM_fence_rw_r () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + MEM_fence_r_w () + else if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + MEM_fence_w_r () + else + sail2_state_monad$returnS (if ((((((((subrange_vec_dec v__132 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__133 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + () + else + let (_ : unit) = (print_endline "FIXME: unsupported fence") in + () ) + ) + (sail2_state_monad$returnS T)))`; -(*val execute_ECALL : unit -> M unit*) +(*val execute_ECALL : unit -> M bool*) val _ = Define ` - ((execute_ECALL:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__106= (state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . + ((execute_ECALL:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__22= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . let (t : sync_exception) = (<| sync_exception_trap := ((case w__0 of @@ -6800,27 +12607,27 @@ val _ = Define ` | Supervisor => E_S_EnvCall | Machine => E_M_EnvCall )); - sync_exception_excinfo := NONE |>) in state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . state_monad$bindS - (handle_exception w__1 (CTL_TRAP t) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . - state_monad$write_regS nextPC_ref w__3))))))`; + sync_exception_excinfo := NONE |>) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__2 : 64 words$word) . sail2_state_monad$bindS + (handle_exception w__1 (CTL_TRAP t) w__2 : ( 64 words$word) M) (\ (w__3 : xlenbits) . sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref w__3) (sail2_state_monad$returnS F)))))))`; -(*val execute_EBREAK : unit -> M unit*) +(*val execute_EBREAK : unit -> M bool*) val _ = Define ` - ((execute_EBREAK:unit ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) g__109= (state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - handle_mem_exception w__0 E_Breakpoint)))`; + ((execute_EBREAK:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__25= (sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . sail2_state_monad$seqS + (handle_mem_exception w__0 E_Breakpoint) (sail2_state_monad$returnS F))))`; -(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) val _ = Define ` - ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS + ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in state_monad$bindS + let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (w__1 : 64 words$word) . let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) in let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in @@ -6829,50 +12636,57 @@ val _ = Define ` let (q' : ii) = (if (((s /\ ((q > ((((pow2 (( 31 : int):ii))) - (( 1 : int):ii)))))))) then (( 0 : int):ii) - ((ex_int ((pow0 (( 2 : int):ii) (( 31 : int):ii))))) - else q) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q' : 32 words$word)) : 64 words$word))))))`; + else q) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):ii) ((to_bits (( 32 : int):ii) q' : 32 words$word)) : 64 words$word))) + (sail2_state_monad$returnS T)))))`; -(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) val _ = Define ` - ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) rs2 rs1 rd s= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) rs2 rs1 rd s= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . let (rs1_int : ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in let (rs2_int : ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in let (q : ii) = (if (((rs2_int = (( 0 : int):ii)))) then ((( 0 : int)-( 1 : int)):ii) else hardware_quot rs1_int rs2_int) in - let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in - wX ((regbits_to_regno rd)) ((to_bits xlen q' : 64 words$word))))))`; + let (q' : ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) ((to_bits xlen q' : 64 words$word))) (sail2_state_monad$returnS T)))))`; -(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*) +(*val execute_C_ILLEGAL : unit -> M bool*) val _ = Define ` - ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rsd= - (let (imm : 32 bits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in state_monad$bindS + ((execute_C_ILLEGAL:unit ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) g__30= (sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F)))`; + + +(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M bool*) + + val _ = Define ` + ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rsd= + (let (imm : 32 bits) = ((EXTS (( 32 : int):ii) imm : 32 words$word)) in sail2_state_monad$bindS (rX ((regbits_to_regno rsd)) : ( 64 words$word) M) (\ rs_val . let (res : 32 bits) = - ((add_vec ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) imm : 32 words$word)) in - wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):ii) res : 64 words$word)))))`; + ((add_vec ((subrange_vec_dec rs_val (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) imm : 32 words$word)) in sail2_state_monad$seqS + (wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):ii) res : 64 words$word))) (sail2_state_monad$returnS T))))`; -(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*) +(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M bool*) val _ = Define ` - ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op= (state_monad$bindS - (if is_imm then state_monad$returnS ((EXTZ (( 64 : int):ii) rs1 : 64 words$word)) + ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> csrop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) csr rs1 rd is_imm op= (sail2_state_monad$bindS + (if is_imm then sail2_state_monad$returnS ((EXTZ (( 64 : int):ii) rs1 : 64 words$word)) else (rX ((regbits_to_regno rs1)) : ( 64 words$word) M)) (\ (rs1_val : xlenbits) . let (isWrite : bool) = ((case op of CSRRW => T | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii)) - )) in state_monad$bindS - (state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . state_monad$bindS + )) in sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__1 : Privilege) . sail2_state_monad$bindS (check_CSR csr w__1 isWrite) (\ (w__2 : bool) . - if ((~ w__2)) then handle_illegal () - else state_monad$bindS - (readCSR csr : ( 64 words$word) M) (\ csr_val . state_monad$seqS + if ((~ w__2)) then sail2_state_monad$seqS (handle_illegal () ) (sail2_state_monad$returnS F) + else sail2_state_monad$bindS + (readCSR csr : ( 64 words$word) M) (\ csr_val . sail2_state_monad$seqS (sail2_state_monad$seqS (if isWrite then let (new_val : xlenbits) = ((case op of @@ -6881,15 +12695,15 @@ val _ = Define ` | CSRRC => (and_vec csr_val ((not_vec rs1_val : 64 words$word)) : 64 words$word) )) in writeCSR csr new_val - else state_monad$returnS () ) - (wX ((regbits_to_regno rd)) csr_val)))))))`; + else sail2_state_monad$returnS () ) + (wX ((regbits_to_regno rd)) csr_val)) (sail2_state_monad$returnS T)))))))`; -(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*) +(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M bool*) val _ = Define ` - ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs2 rs1 op= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . state_monad$bindS + ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> bop ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs2 rs1 op= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ rs1_val . sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ rs2_val . let (taken : bool) = ((case op of @@ -6899,44 +12713,45 @@ val _ = Define ` | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val | RISCV_BLTU => zopz0zI_u rs1_val rs2_val | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val - )) in - if taken then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - state_monad$write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word))) - else state_monad$returnS () ))))`; + )) in sail2_state_monad$seqS + (if taken then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + sail2_state_monad$write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):ii) imm : 64 words$word)) : 64 words$word))) + else sail2_state_monad$returnS () ) + (sail2_state_monad$returnS T)))))`; -(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) +(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*) val _ = Define ` - ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (state_monad$bindS - (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . state_monad$bindS + ((execute_AMO:amoop -> bool -> bool ->(5)words$word ->(5)words$word -> word_width ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) op aq rl rs2 rs1 width rd= (sail2_state_monad$bindS + (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (vaddr : xlenbits) . sail2_state_monad$bindS (translateAddr vaddr ReadWrite Data) (\ (w__0 : TR_Result) . (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => state_monad$bindS + TR_Failure (e) => sail2_state_monad$seqS (handle_mem_exception vaddr e) (sail2_state_monad$returnS F) + | TR_Address (addr) => sail2_state_monad$bindS (case width of WORD => mem_write_ea addr (( 4 : int):ii) (((aq /\ rl))) rl T | DOUBLE => mem_write_ea addr (( 8 : int):ii) (((aq /\ rl))) rl T | _ => internal_error "AMO expected WORD or DOUBLE" ) (\ (eares : unit MemoryOpResult) . (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => state_monad$bindS + MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + | MemValue (_) => sail2_state_monad$bindS (case width of - WORD => state_monad$bindS + WORD => sail2_state_monad$bindS (mem_read addr (( 4 : int):ii) aq (((aq /\ rl))) T : ( ( 32 words$word)MemoryOpResult) M) (\ (w__4 : ( 32 words$word) MemoryOpResult) . - state_monad$returnS ((extend_value F w__4 : ( 64 words$word) MemoryOpResult))) - | DOUBLE => state_monad$bindS + sail2_state_monad$returnS ((extend_value F w__4 : ( 64 words$word) MemoryOpResult))) + | DOUBLE => sail2_state_monad$bindS (mem_read addr (( 8 : int):ii) aq (((aq /\ rl))) T : ( ( 64 words$word)MemoryOpResult) M) (\ (w__5 : ( 64 words$word) MemoryOpResult) . - state_monad$returnS ((extend_value F w__5 : ( 64 words$word) MemoryOpResult))) + sail2_state_monad$returnS ((extend_value F w__5 : ( 64 words$word) MemoryOpResult))) | _ => (internal_error "AMO expected WORD or DOUBLE" : ( ( 64 words$word)MemoryOpResult) M) ) (\ (rval : xlenbits MemoryOpResult) . (case rval of - MemException (e) => handle_mem_exception addr e - | MemValue (loaded) => state_monad$bindS + MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) + | MemValue (loaded) => sail2_state_monad$bindS (rX ((regbits_to_regno rs2)) : ( 64 words$word) M) (\ (rs2_val : xlenbits) . let (result : xlenbits) = ((case op of @@ -6949,7 +12764,7 @@ val _ = Define ` | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded)))) : 64 words$word) | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded)))) : 64 words$word) - )) in state_monad$bindS + )) in sail2_state_monad$bindS (case width of WORD => mem_write_value addr (( 4 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) @@ -6958,26 +12773,27 @@ val _ = Define ` | _ => internal_error "AMO expected WORD or DOUBLE" ) (\ (wval : unit MemoryOpResult) . (case wval of - MemValue (_) => wX ((regbits_to_regno rd)) loaded - | MemException (e) => handle_mem_exception addr e + MemValue (_) => sail2_state_monad$seqS (wX ((regbits_to_regno rd)) loaded) (sail2_state_monad$returnS T) + | MemException (e) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS F) ))) )) )) )))))`; -(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M bool*) val _ = Define ` - ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) imm rs1 rd= (state_monad$bindS + ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) imm rs1 rd= (sail2_state_monad$bindS (rX ((regbits_to_regno rs1)) : ( 64 words$word) M) (\ (w__0 : 64 words$word) . - let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm : 64 words$word)) w__0 : 64 words$word)) in - wX ((regbits_to_regno rd)) - ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word)))))`; + let (result : xlenbits) = ((add_vec ((EXTS (( 64 : int):ii) imm : 64 words$word)) w__0 : 64 words$word)) in sail2_state_monad$seqS + (wX ((regbits_to_regno rd)) + ((EXTS (( 64 : int):ii) ((subrange_vec_dec result (( 31 : int):ii) (( 0 : int):ii) : 32 words$word)) : 64 words$word))) + (sail2_state_monad$returnS T))))`; val execute_defn = Hol_defn "execute" ` - ((execute:ast ->(regstate)state_monad$sequential_state ->(((unit),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) merge_var= + ((execute:ast ->(regstate)sail2_state_monad$sequential_state ->(((bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) merge_var= ((case merge_var of C_ADDI4SPN (rdc,nzimm) => let (imm : 12 bits) = @@ -7123,310 +12939,9894 @@ val _ = Define ` | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s | FENCE (pred,succ) => execute_FENCE pred succ - | FENCEI (g__105) => execute_FENCEI g__105 - | ECALL (g__106) => execute_ECALL g__106 - | MRET (g__107) => execute_MRET g__107 - | SRET (g__108) => execute_SRET g__108 - | EBREAK (g__109) => execute_EBREAK g__109 - | WFI (g__110) => execute_WFI g__110 + | FENCEI (g__21) => execute_FENCEI g__21 + | ECALL (g__22) => execute_ECALL g__22 + | MRET (g__23) => execute_MRET g__23 + | SRET (g__24) => execute_SRET g__24 + | EBREAK (g__25) => execute_EBREAK g__25 + | WFI (g__26) => execute_WFI g__26 | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2 | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op - | NOP (g__111) => state_monad$returnS ((execute_NOP g__111)) - | ILLEGAL (g__112) => execute_ILLEGAL g__112 + | NOP (g__27) => sail2_state_monad$returnS ((execute_NOP g__27)) | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd + | STOP_FETCHING (g__28) => sail2_state_monad$returnS ((execute_STOP_FETCHING g__28)) + | THREAD_START (g__29) => sail2_state_monad$returnS ((execute_THREAD_START g__29)) + | ILLEGAL (s) => execute_ILLEGAL s + | C_ILLEGAL (g__30) => execute_C_ILLEGAL g__30 )))`; val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn; +(*val assembly_forwards : ast -> string*) + val _ = Define ` - ((print_insn:ast -> string) merge_var= - ((case merge_var of + ((assembly_forwards:ast -> string) arg_= + ((case arg_ of UTYPE (imm,rd,op) => - (case op of - RISCV_LUI => - STRCAT "lui " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | RISCV_AUIPC => - STRCAT "auipc " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - ) + string_append ((utype_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) "")))))))) | RISCV_JAL (imm,rd) => - STRCAT "jal " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + string_append "jal" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) "")))))))) | RISCV_JALR (imm,rs1,rd) => - STRCAT "jalr " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + string_append "jalr" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))) | BTYPE (imm,rs2,rs1,op) => - let (insn : string) = - ((case op of - RISCV_BEQ => "beq " - | RISCV_BNE => "bne " - | RISCV_BLT => "blt " - | RISCV_BGE => "bge " - | RISCV_BLTU => "bltu " - | RISCV_BGEU => "bgeu " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rs1)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm)))))))))) + string_append ((btype_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))) | ITYPE (imm,rs1,rd,op) => - let (insn : string) = - ((case op of - RISCV_ADDI => "addi " - | RISCV_SLTI => "slti " - | RISCV_SLTIU => "sltiu " - | RISCV_XORI => "xori " - | RISCV_ORI => "ori " - | RISCV_ANDI => "andi " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + string_append ((itype_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))) | SHIFTIOP (shamt,rs1,rd,op) => - let (insn : string) = - ((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + string_append ((shiftiop_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((string_of_bits shamt)) "")))))))))) | RTYPE (rs2,rs1,rd,op) => - let (insn : string) = - ((case op of - RISCV_ADD => "add " - | RISCV_SUB => "sub " - | RISCV_SLL => "sll " - | RISCV_SLT => "slt " - | RISCV_SLTU => "sltu " - | RISCV_XOR => "xor " - | RISCV_SRL => "srl " - | RISCV_SRA => "sra " - | RISCV_OR => "or " - | RISCV_AND => "and " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => - let (insn : string) = - ((case (width, is_unsigned) of - (BYTE, F) => "lb " - | (BYTE, T) => "lbu " - | (HALF, F) => "lh " - | (HALF, T) => "lhu " - | (WORD, F) => "lw " - | (WORD, T) => "lwu " - | (DOUBLE, F) => "ld " - | (DOUBLE, T) => "ldu " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) - | STORE (imm,rs2,rs1,width,aq,rl) => - let (insn : string) = - ((case width of - BYTE => "sb " - | HALF => "sh " - | WORD => "sw " - | DOUBLE => "sd " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rs2)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + string_append ((rtype_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))) + | LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl) => + string_append "l" + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((maybe_u_forwards is_unsigned)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))))))))))) + | STORE (imm,rs1,rd,size1,aq,rl) => + string_append "s" + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))))))))) | ADDIW (imm,rs1,rd) => - STRCAT "addiw " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm)))))))))) + string_append "addiw" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) "")))))))))))) | SHIFTW (shamt,rs1,rd,op) => - let (insn : string) = - ((case op of RISCV_SLLI => "slli " | RISCV_SRLI => "srli " | RISCV_SRAI => "srai " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt)))))))))) + string_append ((shiftw_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits shamt)) "")))))))))))) | RTYPEW (rs2,rs1,rd,op) => - let (insn : string) = - ((case op of - RISCV_ADDW => "addw " - | RISCV_SUBW => "subw " - | RISCV_SLLW => "sllw " - | RISCV_SRLW => "srlw " - | RISCV_SRAW => "sraw " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append ((rtypew_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))) | MUL (rs2,rs1,rd,high,signed1,signed2) => - let (insn : string) = - ((case (high, signed1, signed2) of - (F, T, T) => "mul " - | (T, T, T) => "mulh " - | (T, T, F) => "mulhsu " - | (T, F, F) => "mulhu" - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append ((mul_mnemonic_forwards high signed1 signed2)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))) | DIV0 (rs2,rs1,rd,s) => - let (insn : string) = (if s then "div " else "divu ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append "div" + ((string_append ((maybe_not_u_forwards s)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))) | REM (rs2,rs1,rd,s) => - let (insn : string) = (if s then "rem " else "remu ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append "rem" + ((string_append ((maybe_not_u_forwards s)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))) | MULW (rs2,rs1,rd) => - STRCAT "mulw " - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append "mulw" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))) | DIVW (rs2,rs1,rd,s) => - let (insn : string) = (if s then "divw " else "divuw ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append "div" + ((string_append ((maybe_not_u_forwards s)) + ((string_append "w" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))))) | REMW (rs2,rs1,rd,s) => - let (insn : string) = (if s then "remw " else "remuw ") in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) - | FENCE (pred,succ) => "fence" - | FENCEI (g__93) => "fence.i" - | ECALL (g__94) => "ecall" - | MRET (g__95) => "mret" - | SRET (g__96) => "sret" - | EBREAK (g__97) => "ebreak" - | WFI (g__98) => "wfi" + string_append "rem" + ((string_append ((maybe_not_u_forwards s)) + ((string_append "w" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))))) + | FENCE (pred,succ) => + string_append "fence" + ((string_append ((spc_forwards () )) + ((string_append ((fence_bits_forwards pred)) + ((string_append ((sep_forwards () )) + ((string_append ((fence_bits_forwards succ)) "")))))))) + | FENCEI (() ) => "fence.i" + | ECALL (() ) => "ecall" + | MRET (() ) => "mret" + | SRET (() ) => "sret" + | EBREAK (() ) => "ebreak" + | WFI (() ) => "wfi" | SFENCE_VMA (rs1,rs2) => - STRCAT "sfence.vma " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))) - | LOADRES (aq,rl,rs1,width,rd) => - let (insn : string) = - ((case width of WORD => "lr.w " | DOUBLE => "lr.d " | _ => "lr.bad " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1)))))) - | STORECON (aq,rl,rs2,rs1,width,rd) => - let (insn : string) = - ((case width of WORD => "sc.w " | DOUBLE => "sc.d " | _ => "sc.bad " )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append "sfence.vma" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) ((string_append ((reg_name_forwards rs2)) "")))))))) + | LOADRES (aq,rl,rs1,size1,rd) => + string_append "lr." + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) "")))))))))))))) + | STORECON (aq,rl,rs2,rs1,size1,rd) => + string_append "sc." + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))))))) | AMO (op,aq,rl,rs2,rs1,width,rd) => - let (insn : string) = - ((case (op, width) of - (AMOSWAP, WORD) => "amoswap.w " - | (AMOADD, WORD) => "amoadd.w " - | (AMOXOR, WORD) => "amoxor.w " - | (AMOAND, WORD) => "amoand.w " - | (AMOOR, WORD) => "amoor.w " - | (AMOMIN, WORD) => "amomin.w " - | (AMOMAX, WORD) => "amomax.w " - | (AMOMINU, WORD) => "amominu.w " - | (AMOMAXU, WORD) => "amomaxu.w " - | (AMOSWAP, DOUBLE) => "amoswap.d " - | (AMOADD, DOUBLE) => "amoadd.d " - | (AMOXOR, DOUBLE) => "amoxor.d " - | (AMOAND, DOUBLE) => "amoand.d " - | (AMOOR, DOUBLE) => "amoor.d " - | (AMOMIN, DOUBLE) => "amomin.d " - | (AMOMAX, DOUBLE) => "amomax.d " - | (AMOMINU, DOUBLE) => "amominu.d " - | (AMOMAXU, DOUBLE) => "amomaxu.d " - | (_, _) => "amo.bad " - )) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " - ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2)))))))))) + string_append ((amo_mnemonic_forwards op)) + ((string_append "." + ((string_append ((size_mnemonic_forwards width)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) "")))))))))))))))))))) + | CSR (csr,rs1,rd,T,op) => + string_append ((csr_mnemonic_forwards op)) + ((string_append "i" + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((csr_name_map_forwards csr)) "")))))))))))))) + | CSR (csr,rs1,rd,F,op) => + string_append ((csr_mnemonic_forwards op)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((csr_name_map_forwards csr)) "")))))))))))) + | ILLEGAL (s) => + string_append "illegal" + ((string_append ((spc_forwards () )) ((string_append ((string_of_bits s)) "")))) + )))`; + + +(*val assembly_backwards : string -> ast*) + +val _ = Define ` + ((assembly_backwards:string -> ast) arg_= + (let stringappend_1076_0 = arg_ in + if ((case ((utype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1077_0,stringappend_1078_0) => + let stringappend_1079_0 = (string_drop stringappend_1076_0 stringappend_1078_0) in + if ((case ((spc_matches_prefix stringappend_1079_0)) of + SOME (stringappend_1080_0,stringappend_1081_0) => + let stringappend_1082_0 = (string_drop stringappend_1079_0 stringappend_1081_0) in + if ((case ((reg_name_matches_prefix stringappend_1082_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1083_0,stringappend_1084_0) => + let stringappend_1085_0 = (string_drop stringappend_1082_0 stringappend_1084_0) in + if ((case ((sep_matches_prefix stringappend_1085_0)) of + SOME (stringappend_1086_0,stringappend_1087_0) => + let stringappend_1088_0 = (string_drop stringappend_1085_0 stringappend_1087_0) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1088_0 + : (( 20 words$word # ii))option)) of + SOME (stringappend_1089_0,stringappend_1090_0) => + (case ((string_drop stringappend_1088_0 stringappend_1090_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1078_0) = + ((case ((utype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1077_0,stringappend_1078_0) => + (stringappend_1077_0, stringappend_1078_0) + )) in + let stringappend_1079_0 = (string_drop stringappend_1076_0 stringappend_1078_0) in + (case + (case ((spc_matches_prefix stringappend_1079_0)) of + SOME (stringappend_1080_0,stringappend_1081_0) => + (stringappend_1080_0, stringappend_1081_0) + ) of + (() , stringappend_1081_0) => + let stringappend_1082_0 = (string_drop stringappend_1079_0 + stringappend_1081_0) in + let (rd, stringappend_1084_0) = + ((case ((reg_name_matches_prefix stringappend_1082_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1083_0,stringappend_1084_0) => + (stringappend_1083_0, stringappend_1084_0) + )) in + let stringappend_1085_0 = (string_drop stringappend_1082_0 + stringappend_1084_0) in + (case + (case ((sep_matches_prefix stringappend_1085_0)) of + SOME (stringappend_1086_0,stringappend_1087_0) => + (stringappend_1086_0, stringappend_1087_0) + ) of + (() , stringappend_1087_0) => + let stringappend_1088_0 = (string_drop stringappend_1085_0 + stringappend_1087_0) in + let (imm, stringappend_1090_0) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1088_0 : (( 20 words$word # ii)) option)) of + SOME (stringappend_1089_0,stringappend_1090_0) => + (stringappend_1089_0, stringappend_1090_0) + )) in + (case ((string_drop stringappend_1088_0 stringappend_1090_0)) of + "" => UTYPE (imm,rd,op) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "jal")) /\ (let stringappend_1092_0 = (string_drop stringappend_1076_0 ((string_length "jal"))) in + if ((case ((spc_matches_prefix stringappend_1092_0)) of + SOME (stringappend_1093_0,stringappend_1094_0) => + let stringappend_1095_0 = (string_drop stringappend_1092_0 stringappend_1094_0) in + if ((case ((reg_name_matches_prefix stringappend_1095_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1096_0,stringappend_1097_0) => + let stringappend_1098_0 = + (string_drop stringappend_1095_0 stringappend_1097_0) in + if ((case ((sep_matches_prefix stringappend_1098_0)) of + SOME (stringappend_1099_0,stringappend_1100_0) => + let stringappend_1101_0 = + (string_drop stringappend_1098_0 stringappend_1100_0) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1101_0 + : (( 21 words$word # ii))option)) of + SOME (stringappend_1102_0,stringappend_1103_0) => + (case ((string_drop stringappend_1101_0 stringappend_1103_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1092_0 = (string_drop stringappend_1076_0 ((string_length "jal"))) in + (case + (case ((spc_matches_prefix stringappend_1092_0)) of + SOME (stringappend_1093_0,stringappend_1094_0) => + (stringappend_1093_0, stringappend_1094_0) + ) of + (() , stringappend_1094_0) => + let stringappend_1095_0 = (string_drop stringappend_1092_0 + stringappend_1094_0) in + let (rd, stringappend_1097_0) = + ((case ((reg_name_matches_prefix stringappend_1095_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1096_0,stringappend_1097_0) => + (stringappend_1096_0, stringappend_1097_0) + )) in + let stringappend_1098_0 = (string_drop stringappend_1095_0 + stringappend_1097_0) in + (case + (case ((sep_matches_prefix stringappend_1098_0)) of + SOME (stringappend_1099_0,stringappend_1100_0) => + (stringappend_1099_0, stringappend_1100_0) + ) of + (() , stringappend_1100_0) => + let stringappend_1101_0 = (string_drop stringappend_1098_0 + stringappend_1100_0) in + let (imm, stringappend_1103_0) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1101_0 : (( 21 words$word # ii)) option)) of + SOME (stringappend_1102_0,stringappend_1103_0) => + (stringappend_1102_0, stringappend_1103_0) + )) in + (case ((string_drop stringappend_1101_0 stringappend_1103_0)) of + "" => RISCV_JAL (imm,rd) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "jalr")) /\ (let stringappend_1105_0 = (string_drop stringappend_1076_0 ((string_length "jalr"))) in + if ((case ((spc_matches_prefix stringappend_1105_0)) of + SOME (stringappend_1106_0,stringappend_1107_0) => + let stringappend_1108_0 = (string_drop stringappend_1105_0 stringappend_1107_0) in + if ((case ((reg_name_matches_prefix stringappend_1108_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1109_0,stringappend_1110_0) => + let stringappend_1111_0 = + (string_drop stringappend_1108_0 stringappend_1110_0) in + if ((case ((sep_matches_prefix stringappend_1111_0)) of + SOME (stringappend_1112_0,stringappend_1113_0) => + let stringappend_1114_0 = + (string_drop stringappend_1111_0 stringappend_1113_0) in + if ((case ((reg_name_matches_prefix stringappend_1114_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1115_0,stringappend_1116_0) => + let stringappend_1117_0 = + (string_drop stringappend_1114_0 stringappend_1116_0) in + if ((case ((sep_matches_prefix stringappend_1117_0)) of + SOME (stringappend_1118_0,stringappend_1119_0) => + let stringappend_1120_0 = + (string_drop stringappend_1117_0 stringappend_1119_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1120_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1121_0,stringappend_1122_0) => + (case ((string_drop stringappend_1120_0 + stringappend_1122_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1105_0 = (string_drop stringappend_1076_0 ((string_length "jalr"))) in + (case + (case ((spc_matches_prefix stringappend_1105_0)) of + SOME (stringappend_1106_0,stringappend_1107_0) => + (stringappend_1106_0, stringappend_1107_0) + ) of + (() , stringappend_1107_0) => + let stringappend_1108_0 = (string_drop stringappend_1105_0 + stringappend_1107_0) in + let (rd, stringappend_1110_0) = + ((case ((reg_name_matches_prefix stringappend_1108_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1109_0,stringappend_1110_0) => + (stringappend_1109_0, stringappend_1110_0) + )) in + let stringappend_1111_0 = (string_drop stringappend_1108_0 + stringappend_1110_0) in + (case + (case ((sep_matches_prefix stringappend_1111_0)) of + SOME (stringappend_1112_0,stringappend_1113_0) => + (stringappend_1112_0, stringappend_1113_0) + ) of + (() , stringappend_1113_0) => + let stringappend_1114_0 = (string_drop stringappend_1111_0 + stringappend_1113_0) in + let (rs1, stringappend_1116_0) = + ((case ((reg_name_matches_prefix stringappend_1114_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1115_0,stringappend_1116_0) => + (stringappend_1115_0, stringappend_1116_0) + )) in + let stringappend_1117_0 = (string_drop stringappend_1114_0 + stringappend_1116_0) in + (case + (case ((sep_matches_prefix stringappend_1117_0)) of + SOME (stringappend_1118_0,stringappend_1119_0) => + (stringappend_1118_0, stringappend_1119_0) + ) of + (() , stringappend_1119_0) => + let stringappend_1120_0 = (string_drop stringappend_1117_0 + stringappend_1119_0) in + let (imm, stringappend_1122_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1120_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1121_0,stringappend_1122_0) => + (stringappend_1121_0, stringappend_1122_0) + )) in + (case ((string_drop stringappend_1120_0 stringappend_1122_0)) of + "" => RISCV_JALR (imm,rs1,rd) + ) + ) + ) + ) + else if ((case ((btype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1124_0,stringappend_1125_0) => + let stringappend_1126_0 = (string_drop stringappend_1076_0 stringappend_1125_0) in + if ((case ((spc_matches_prefix stringappend_1126_0)) of + SOME (stringappend_1127_0,stringappend_1128_0) => + let stringappend_1129_0 = (string_drop stringappend_1126_0 stringappend_1128_0) in + if ((case ((reg_name_matches_prefix stringappend_1129_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1130_0,stringappend_1131_0) => + let stringappend_1132_0 = (string_drop stringappend_1129_0 stringappend_1131_0) in + if ((case ((sep_matches_prefix stringappend_1132_0)) of + SOME (stringappend_1133_0,stringappend_1134_0) => + let stringappend_1135_0 = (string_drop stringappend_1132_0 stringappend_1134_0) in + if ((case ((reg_name_matches_prefix stringappend_1135_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1136_0,stringappend_1137_0) => + let stringappend_1138_0 = + (string_drop stringappend_1135_0 stringappend_1137_0) in + if ((case ((sep_matches_prefix stringappend_1138_0)) of + SOME (stringappend_1139_0,stringappend_1140_0) => + let stringappend_1141_0 = + (string_drop stringappend_1138_0 stringappend_1140_0) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1141_0 + : (( 13 words$word # ii))option)) of + SOME (stringappend_1142_0,stringappend_1143_0) => + (case ((string_drop stringappend_1141_0 stringappend_1143_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1125_0) = + ((case ((btype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1124_0,stringappend_1125_0) => + (stringappend_1124_0, stringappend_1125_0) + )) in + let stringappend_1126_0 = (string_drop stringappend_1076_0 stringappend_1125_0) in + (case + (case ((spc_matches_prefix stringappend_1126_0)) of + SOME (stringappend_1127_0,stringappend_1128_0) => + (stringappend_1127_0, stringappend_1128_0) + ) of + (() , stringappend_1128_0) => + let stringappend_1129_0 = (string_drop stringappend_1126_0 + stringappend_1128_0) in + let (rs1, stringappend_1131_0) = + ((case ((reg_name_matches_prefix stringappend_1129_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1130_0,stringappend_1131_0) => + (stringappend_1130_0, stringappend_1131_0) + )) in + let stringappend_1132_0 = (string_drop stringappend_1129_0 + stringappend_1131_0) in + (case + (case ((sep_matches_prefix stringappend_1132_0)) of + SOME (stringappend_1133_0,stringappend_1134_0) => + (stringappend_1133_0, stringappend_1134_0) + ) of + (() , stringappend_1134_0) => + let stringappend_1135_0 = (string_drop stringappend_1132_0 + stringappend_1134_0) in + let (rs2, stringappend_1137_0) = + ((case ((reg_name_matches_prefix stringappend_1135_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1136_0,stringappend_1137_0) => + (stringappend_1136_0, stringappend_1137_0) + )) in + let stringappend_1138_0 = (string_drop stringappend_1135_0 + stringappend_1137_0) in + (case + (case ((sep_matches_prefix stringappend_1138_0)) of + SOME (stringappend_1139_0,stringappend_1140_0) => + (stringappend_1139_0, stringappend_1140_0) + ) of + (() , stringappend_1140_0) => + let stringappend_1141_0 = (string_drop stringappend_1138_0 + stringappend_1140_0) in + let (imm, stringappend_1143_0) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1141_0 : (( 13 words$word # ii)) option)) of + SOME (stringappend_1142_0,stringappend_1143_0) => + (stringappend_1142_0, stringappend_1143_0) + )) in + (case ((string_drop stringappend_1141_0 stringappend_1143_0)) of + "" => BTYPE (imm,rs2,rs1,op) + ) + ) + ) + ) + else if ((case ((itype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1145_0,stringappend_1146_0) => + let stringappend_1147_0 = (string_drop stringappend_1076_0 stringappend_1146_0) in + if ((case ((spc_matches_prefix stringappend_1147_0)) of + SOME (stringappend_1148_0,stringappend_1149_0) => + let stringappend_1150_0 = (string_drop stringappend_1147_0 stringappend_1149_0) in + if ((case ((reg_name_matches_prefix stringappend_1150_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1151_0,stringappend_1152_0) => + let stringappend_1153_0 = (string_drop stringappend_1150_0 stringappend_1152_0) in + if ((case ((sep_matches_prefix stringappend_1153_0)) of + SOME (stringappend_1154_0,stringappend_1155_0) => + let stringappend_1156_0 = (string_drop stringappend_1153_0 stringappend_1155_0) in + if ((case ((reg_name_matches_prefix stringappend_1156_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1157_0,stringappend_1158_0) => + let stringappend_1159_0 = + (string_drop stringappend_1156_0 stringappend_1158_0) in + if ((case ((sep_matches_prefix stringappend_1159_0)) of + SOME (stringappend_1160_0,stringappend_1161_0) => + let stringappend_1162_0 = + (string_drop stringappend_1159_0 stringappend_1161_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1162_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1163_0,stringappend_1164_0) => + (case ((string_drop stringappend_1162_0 stringappend_1164_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1146_0) = + ((case ((itype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1145_0,stringappend_1146_0) => + (stringappend_1145_0, stringappend_1146_0) + )) in + let stringappend_1147_0 = (string_drop stringappend_1076_0 stringappend_1146_0) in + (case + (case ((spc_matches_prefix stringappend_1147_0)) of + SOME (stringappend_1148_0,stringappend_1149_0) => + (stringappend_1148_0, stringappend_1149_0) + ) of + (() , stringappend_1149_0) => + let stringappend_1150_0 = (string_drop stringappend_1147_0 + stringappend_1149_0) in + let (rd, stringappend_1152_0) = + ((case ((reg_name_matches_prefix stringappend_1150_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1151_0,stringappend_1152_0) => + (stringappend_1151_0, stringappend_1152_0) + )) in + let stringappend_1153_0 = (string_drop stringappend_1150_0 + stringappend_1152_0) in + (case + (case ((sep_matches_prefix stringappend_1153_0)) of + SOME (stringappend_1154_0,stringappend_1155_0) => + (stringappend_1154_0, stringappend_1155_0) + ) of + (() , stringappend_1155_0) => + let stringappend_1156_0 = (string_drop stringappend_1153_0 + stringappend_1155_0) in + let (rs1, stringappend_1158_0) = + ((case ((reg_name_matches_prefix stringappend_1156_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1157_0,stringappend_1158_0) => + (stringappend_1157_0, stringappend_1158_0) + )) in + let stringappend_1159_0 = (string_drop stringappend_1156_0 + stringappend_1158_0) in + (case + (case ((sep_matches_prefix stringappend_1159_0)) of + SOME (stringappend_1160_0,stringappend_1161_0) => + (stringappend_1160_0, stringappend_1161_0) + ) of + (() , stringappend_1161_0) => + let stringappend_1162_0 = (string_drop stringappend_1159_0 + stringappend_1161_0) in + let (imm, stringappend_1164_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1162_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1163_0,stringappend_1164_0) => + (stringappend_1163_0, stringappend_1164_0) + )) in + (case ((string_drop stringappend_1162_0 stringappend_1164_0)) of + "" => ITYPE (imm,rs1,rd,op) + ) + ) + ) + ) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1166_0,stringappend_1167_0) => + let stringappend_1168_0 = (string_drop stringappend_1076_0 stringappend_1167_0) in + if ((case ((spc_matches_prefix stringappend_1168_0)) of + SOME (stringappend_1169_0,stringappend_1170_0) => + let stringappend_1171_0 = (string_drop stringappend_1168_0 stringappend_1170_0) in + if ((case ((reg_name_matches_prefix stringappend_1171_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1172_0,stringappend_1173_0) => + let stringappend_1174_0 = (string_drop stringappend_1171_0 stringappend_1173_0) in + if ((case ((sep_matches_prefix stringappend_1174_0)) of + SOME (stringappend_1175_0,stringappend_1176_0) => + let stringappend_1177_0 = (string_drop stringappend_1174_0 stringappend_1176_0) in + if ((case ((reg_name_matches_prefix stringappend_1177_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1178_0,stringappend_1179_0) => + let stringappend_1180_0 = + (string_drop stringappend_1177_0 stringappend_1179_0) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1180_0 + : (( 6 words$word # ii))option)) of + SOME (stringappend_1181_0,stringappend_1182_0) => + (case ((string_drop stringappend_1180_0 stringappend_1182_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1167_0) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1166_0,stringappend_1167_0) => + (stringappend_1166_0, stringappend_1167_0) + )) in + let stringappend_1168_0 = (string_drop stringappend_1076_0 stringappend_1167_0) in + (case + (case ((spc_matches_prefix stringappend_1168_0)) of + SOME (stringappend_1169_0,stringappend_1170_0) => + (stringappend_1169_0, stringappend_1170_0) + ) of + (() , stringappend_1170_0) => + let stringappend_1171_0 = (string_drop stringappend_1168_0 + stringappend_1170_0) in + let (rd, stringappend_1173_0) = + ((case ((reg_name_matches_prefix stringappend_1171_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1172_0,stringappend_1173_0) => + (stringappend_1172_0, stringappend_1173_0) + )) in + let stringappend_1174_0 = (string_drop stringappend_1171_0 + stringappend_1173_0) in + (case + (case ((sep_matches_prefix stringappend_1174_0)) of + SOME (stringappend_1175_0,stringappend_1176_0) => + (stringappend_1175_0, stringappend_1176_0) + ) of + (() , stringappend_1176_0) => + let stringappend_1177_0 = (string_drop stringappend_1174_0 + stringappend_1176_0) in + let (rs1, stringappend_1179_0) = + ((case ((reg_name_matches_prefix stringappend_1177_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1178_0,stringappend_1179_0) => + (stringappend_1178_0, stringappend_1179_0) + )) in + let stringappend_1180_0 = (string_drop stringappend_1177_0 + stringappend_1179_0) in + let (shamt, stringappend_1182_0) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1180_0 : (( 6 words$word # ii)) option)) of + SOME (stringappend_1181_0,stringappend_1182_0) => + (stringappend_1181_0, stringappend_1182_0) + )) in + (case ((string_drop stringappend_1180_0 stringappend_1182_0)) of + "" => SHIFTIOP (shamt,rs1,rd,op) + ) + ) + ) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1184_0,stringappend_1185_0) => + let stringappend_1186_0 = (string_drop stringappend_1076_0 stringappend_1185_0) in + if ((case ((spc_matches_prefix stringappend_1186_0)) of + SOME (stringappend_1187_0,stringappend_1188_0) => + let stringappend_1189_0 = (string_drop stringappend_1186_0 stringappend_1188_0) in + if ((case ((reg_name_matches_prefix stringappend_1189_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1190_0,stringappend_1191_0) => + let stringappend_1192_0 = (string_drop stringappend_1189_0 stringappend_1191_0) in + if ((case ((sep_matches_prefix stringappend_1192_0)) of + SOME (stringappend_1193_0,stringappend_1194_0) => + let stringappend_1195_0 = (string_drop stringappend_1192_0 stringappend_1194_0) in + if ((case ((reg_name_matches_prefix stringappend_1195_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1196_0,stringappend_1197_0) => + let stringappend_1198_0 = + (string_drop stringappend_1195_0 stringappend_1197_0) in + if ((case ((sep_matches_prefix stringappend_1198_0)) of + SOME (stringappend_1199_0,stringappend_1200_0) => + let stringappend_1201_0 = + (string_drop stringappend_1198_0 stringappend_1200_0) in + if ((case ((reg_name_matches_prefix stringappend_1201_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1202_0,stringappend_1203_0) => + (case ((string_drop stringappend_1201_0 stringappend_1203_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1185_0) = + ((case ((rtype_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1184_0,stringappend_1185_0) => + (stringappend_1184_0, stringappend_1185_0) + )) in + let stringappend_1186_0 = (string_drop stringappend_1076_0 stringappend_1185_0) in + (case + (case ((spc_matches_prefix stringappend_1186_0)) of + SOME (stringappend_1187_0,stringappend_1188_0) => + (stringappend_1187_0, stringappend_1188_0) + ) of + (() , stringappend_1188_0) => + let stringappend_1189_0 = (string_drop stringappend_1186_0 + stringappend_1188_0) in + let (rd, stringappend_1191_0) = + ((case ((reg_name_matches_prefix stringappend_1189_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1190_0,stringappend_1191_0) => + (stringappend_1190_0, stringappend_1191_0) + )) in + let stringappend_1192_0 = (string_drop stringappend_1189_0 + stringappend_1191_0) in + (case + (case ((sep_matches_prefix stringappend_1192_0)) of + SOME (stringappend_1193_0,stringappend_1194_0) => + (stringappend_1193_0, stringappend_1194_0) + ) of + (() , stringappend_1194_0) => + let stringappend_1195_0 = (string_drop stringappend_1192_0 + stringappend_1194_0) in + let (rs1, stringappend_1197_0) = + ((case ((reg_name_matches_prefix stringappend_1195_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1196_0,stringappend_1197_0) => + (stringappend_1196_0, stringappend_1197_0) + )) in + let stringappend_1198_0 = (string_drop stringappend_1195_0 + stringappend_1197_0) in + (case + (case ((sep_matches_prefix stringappend_1198_0)) of + SOME (stringappend_1199_0,stringappend_1200_0) => + (stringappend_1199_0, stringappend_1200_0) + ) of + (() , stringappend_1200_0) => + let stringappend_1201_0 = (string_drop stringappend_1198_0 + stringappend_1200_0) in + let (rs2, stringappend_1203_0) = + ((case ((reg_name_matches_prefix stringappend_1201_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1202_0,stringappend_1203_0) => + (stringappend_1202_0, stringappend_1203_0) + )) in + (case ((string_drop stringappend_1201_0 stringappend_1203_0)) of + "" => RTYPE (rs2,rs1,rd,op) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "l")) /\ (let stringappend_1205_0 = (string_drop stringappend_1076_0 ((string_length "l"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_1205_0)) of + SOME (stringappend_1206_0,stringappend_1207_0) => + let stringappend_1208_0 = (string_drop stringappend_1205_0 stringappend_1207_0) in + if ((case ((maybe_u_matches_prefix stringappend_1208_0)) of + SOME (stringappend_1209_0,stringappend_1210_0) => + let stringappend_1211_0 = + (string_drop stringappend_1208_0 stringappend_1210_0) in + if ((case ((maybe_aq_matches_prefix stringappend_1211_0)) of + SOME (stringappend_1212_0,stringappend_1213_0) => + let stringappend_1214_0 = + (string_drop stringappend_1211_0 stringappend_1213_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1214_0)) of + SOME (stringappend_1215_0,stringappend_1216_0) => + let stringappend_1217_0 = + (string_drop stringappend_1214_0 stringappend_1216_0) in + if ((case ((spc_matches_prefix stringappend_1217_0)) of + SOME (stringappend_1218_0,stringappend_1219_0) => + let stringappend_1220_0 = + (string_drop stringappend_1217_0 stringappend_1219_0) in + if ((case ((reg_name_matches_prefix stringappend_1220_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1221_0,stringappend_1222_0) => + let stringappend_1223_0 = + (string_drop stringappend_1220_0 stringappend_1222_0) in + if ((case ((sep_matches_prefix stringappend_1223_0)) of + SOME (stringappend_1224_0,stringappend_1225_0) => + let stringappend_1226_0 = + (string_drop stringappend_1223_0 + stringappend_1225_0) in + if ((case ((reg_name_matches_prefix + stringappend_1226_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1227_0,stringappend_1228_0) => + let stringappend_1229_0 = + (string_drop stringappend_1226_0 + stringappend_1228_0) in + if ((case ((sep_matches_prefix + stringappend_1229_0)) of + SOME + (stringappend_1230_0,stringappend_1231_0) => + let stringappend_1232_0 = + (string_drop stringappend_1229_0 + stringappend_1231_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1232_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_1233_0,stringappend_1234_0) => + (case ((string_drop + stringappend_1232_0 + stringappend_1234_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1205_0 = (string_drop stringappend_1076_0 ((string_length "l"))) in + let (size1, stringappend_1207_0) = + ((case ((size_mnemonic_matches_prefix stringappend_1205_0)) of + SOME (stringappend_1206_0,stringappend_1207_0) => + (stringappend_1206_0, stringappend_1207_0) + )) in + let stringappend_1208_0 = (string_drop stringappend_1205_0 stringappend_1207_0) in + let (is_unsigned, stringappend_1210_0) = + ((case ((maybe_u_matches_prefix stringappend_1208_0)) of + SOME (stringappend_1209_0,stringappend_1210_0) => + (stringappend_1209_0, stringappend_1210_0) + )) in + let stringappend_1211_0 = (string_drop stringappend_1208_0 stringappend_1210_0) in + let (aq, stringappend_1213_0) = + ((case ((maybe_aq_matches_prefix stringappend_1211_0)) of + SOME (stringappend_1212_0,stringappend_1213_0) => + (stringappend_1212_0, stringappend_1213_0) + )) in + let stringappend_1214_0 = (string_drop stringappend_1211_0 stringappend_1213_0) in + let (rl, stringappend_1216_0) = + ((case ((maybe_rl_matches_prefix stringappend_1214_0)) of + SOME (stringappend_1215_0,stringappend_1216_0) => + (stringappend_1215_0, stringappend_1216_0) + )) in + let stringappend_1217_0 = (string_drop stringappend_1214_0 stringappend_1216_0) in + (case + (case ((spc_matches_prefix stringappend_1217_0)) of + SOME (stringappend_1218_0,stringappend_1219_0) => + (stringappend_1218_0, stringappend_1219_0) + ) of + (() , stringappend_1219_0) => + let stringappend_1220_0 = (string_drop stringappend_1217_0 + stringappend_1219_0) in + let (rd, stringappend_1222_0) = + ((case ((reg_name_matches_prefix stringappend_1220_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1221_0,stringappend_1222_0) => + (stringappend_1221_0, stringappend_1222_0) + )) in + let stringappend_1223_0 = (string_drop stringappend_1220_0 + stringappend_1222_0) in + (case + (case ((sep_matches_prefix stringappend_1223_0)) of + SOME (stringappend_1224_0,stringappend_1225_0) => + (stringappend_1224_0, stringappend_1225_0) + ) of + (() , stringappend_1225_0) => + let stringappend_1226_0 = (string_drop stringappend_1223_0 + stringappend_1225_0) in + let (rs1, stringappend_1228_0) = + ((case ((reg_name_matches_prefix stringappend_1226_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1227_0,stringappend_1228_0) => + (stringappend_1227_0, stringappend_1228_0) + )) in + let stringappend_1229_0 = (string_drop stringappend_1226_0 + stringappend_1228_0) in + (case + (case ((sep_matches_prefix stringappend_1229_0)) of + SOME (stringappend_1230_0,stringappend_1231_0) => + (stringappend_1230_0, stringappend_1231_0) + ) of + (() , stringappend_1231_0) => + let stringappend_1232_0 = (string_drop stringappend_1229_0 + stringappend_1231_0) in + let (imm, stringappend_1234_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1232_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1233_0,stringappend_1234_0) => + (stringappend_1233_0, stringappend_1234_0) + )) in + (case ((string_drop stringappend_1232_0 stringappend_1234_0)) of + "" => LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "s")) /\ (let stringappend_1236_0 = (string_drop stringappend_1076_0 ((string_length "s"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_1236_0)) of + SOME (stringappend_1237_0,stringappend_1238_0) => + let stringappend_1239_0 = (string_drop stringappend_1236_0 stringappend_1238_0) in + if ((case ((maybe_aq_matches_prefix stringappend_1239_0)) of + SOME (stringappend_1240_0,stringappend_1241_0) => + let stringappend_1242_0 = + (string_drop stringappend_1239_0 stringappend_1241_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1242_0)) of + SOME (stringappend_1243_0,stringappend_1244_0) => + let stringappend_1245_0 = + (string_drop stringappend_1242_0 stringappend_1244_0) in + if ((case ((spc_matches_prefix stringappend_1245_0)) of + SOME (stringappend_1246_0,stringappend_1247_0) => + let stringappend_1248_0 = + (string_drop stringappend_1245_0 stringappend_1247_0) in + if ((case ((reg_name_matches_prefix stringappend_1248_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1249_0,stringappend_1250_0) => + let stringappend_1251_0 = + (string_drop stringappend_1248_0 stringappend_1250_0) in + if ((case ((sep_matches_prefix stringappend_1251_0)) of + SOME (stringappend_1252_0,stringappend_1253_0) => + let stringappend_1254_0 = + (string_drop stringappend_1251_0 stringappend_1253_0) in + if ((case ((reg_name_matches_prefix stringappend_1254_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1255_0,stringappend_1256_0) => + let stringappend_1257_0 = + (string_drop stringappend_1254_0 + stringappend_1256_0) in + if ((case ((sep_matches_prefix stringappend_1257_0)) of + SOME (stringappend_1258_0,stringappend_1259_0) => + let stringappend_1260_0 = + (string_drop stringappend_1257_0 + stringappend_1259_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1260_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_1261_0,stringappend_1262_0) => + (case ((string_drop stringappend_1260_0 + stringappend_1262_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1236_0 = (string_drop stringappend_1076_0 ((string_length "s"))) in + let (size1, stringappend_1238_0) = + ((case ((size_mnemonic_matches_prefix stringappend_1236_0)) of + SOME (stringappend_1237_0,stringappend_1238_0) => + (stringappend_1237_0, stringappend_1238_0) + )) in + let stringappend_1239_0 = (string_drop stringappend_1236_0 stringappend_1238_0) in + let (aq, stringappend_1241_0) = + ((case ((maybe_aq_matches_prefix stringappend_1239_0)) of + SOME (stringappend_1240_0,stringappend_1241_0) => + (stringappend_1240_0, stringappend_1241_0) + )) in + let stringappend_1242_0 = (string_drop stringappend_1239_0 stringappend_1241_0) in + let (rl, stringappend_1244_0) = + ((case ((maybe_rl_matches_prefix stringappend_1242_0)) of + SOME (stringappend_1243_0,stringappend_1244_0) => + (stringappend_1243_0, stringappend_1244_0) + )) in + let stringappend_1245_0 = (string_drop stringappend_1242_0 stringappend_1244_0) in + (case + (case ((spc_matches_prefix stringappend_1245_0)) of + SOME (stringappend_1246_0,stringappend_1247_0) => + (stringappend_1246_0, stringappend_1247_0) + ) of + (() , stringappend_1247_0) => + let stringappend_1248_0 = (string_drop stringappend_1245_0 + stringappend_1247_0) in + let (rd, stringappend_1250_0) = + ((case ((reg_name_matches_prefix stringappend_1248_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1249_0,stringappend_1250_0) => + (stringappend_1249_0, stringappend_1250_0) + )) in + let stringappend_1251_0 = (string_drop stringappend_1248_0 + stringappend_1250_0) in + (case + (case ((sep_matches_prefix stringappend_1251_0)) of + SOME (stringappend_1252_0,stringappend_1253_0) => + (stringappend_1252_0, stringappend_1253_0) + ) of + (() , stringappend_1253_0) => + let stringappend_1254_0 = (string_drop stringappend_1251_0 + stringappend_1253_0) in + let (rs1, stringappend_1256_0) = + ((case ((reg_name_matches_prefix stringappend_1254_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1255_0,stringappend_1256_0) => + (stringappend_1255_0, stringappend_1256_0) + )) in + let stringappend_1257_0 = (string_drop stringappend_1254_0 + stringappend_1256_0) in + (case + (case ((sep_matches_prefix stringappend_1257_0)) of + SOME (stringappend_1258_0,stringappend_1259_0) => + (stringappend_1258_0, stringappend_1259_0) + ) of + (() , stringappend_1259_0) => + let stringappend_1260_0 = (string_drop stringappend_1257_0 + stringappend_1259_0) in + let (imm, stringappend_1262_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1260_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1261_0,stringappend_1262_0) => + (stringappend_1261_0, stringappend_1262_0) + )) in + (case ((string_drop stringappend_1260_0 stringappend_1262_0)) of + "" => STORE (imm,rs1,rd,size1,aq,rl) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "addiw")) /\ (let stringappend_1264_0 = (string_drop stringappend_1076_0 ((string_length "addiw"))) in + if ((case ((spc_matches_prefix stringappend_1264_0)) of + SOME (stringappend_1265_0,stringappend_1266_0) => + let stringappend_1267_0 = (string_drop stringappend_1264_0 stringappend_1266_0) in + if ((case ((reg_name_matches_prefix stringappend_1267_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1268_0,stringappend_1269_0) => + let stringappend_1270_0 = + (string_drop stringappend_1267_0 stringappend_1269_0) in + if ((case ((sep_matches_prefix stringappend_1270_0)) of + SOME (stringappend_1271_0,stringappend_1272_0) => + let stringappend_1273_0 = + (string_drop stringappend_1270_0 stringappend_1272_0) in + if ((case ((reg_name_matches_prefix stringappend_1273_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1274_0,stringappend_1275_0) => + let stringappend_1276_0 = + (string_drop stringappend_1273_0 stringappend_1275_0) in + if ((case ((sep_matches_prefix stringappend_1276_0)) of + SOME (stringappend_1277_0,stringappend_1278_0) => + let stringappend_1279_0 = + (string_drop stringappend_1276_0 stringappend_1278_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1279_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1280_0,stringappend_1281_0) => + (case ((string_drop stringappend_1279_0 + stringappend_1281_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1264_0 = (string_drop stringappend_1076_0 ((string_length "addiw"))) in + (case + (case ((spc_matches_prefix stringappend_1264_0)) of + SOME (stringappend_1265_0,stringappend_1266_0) => + (stringappend_1265_0, stringappend_1266_0) + ) of + (() , stringappend_1266_0) => + let stringappend_1267_0 = (string_drop stringappend_1264_0 + stringappend_1266_0) in + let (rd, stringappend_1269_0) = + ((case ((reg_name_matches_prefix stringappend_1267_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1268_0,stringappend_1269_0) => + (stringappend_1268_0, stringappend_1269_0) + )) in + let stringappend_1270_0 = (string_drop stringappend_1267_0 + stringappend_1269_0) in + (case + (case ((sep_matches_prefix stringappend_1270_0)) of + SOME (stringappend_1271_0,stringappend_1272_0) => + (stringappend_1271_0, stringappend_1272_0) + ) of + (() , stringappend_1272_0) => + let stringappend_1273_0 = (string_drop stringappend_1270_0 + stringappend_1272_0) in + let (rs1, stringappend_1275_0) = + ((case ((reg_name_matches_prefix stringappend_1273_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1274_0,stringappend_1275_0) => + (stringappend_1274_0, stringappend_1275_0) + )) in + let stringappend_1276_0 = (string_drop stringappend_1273_0 + stringappend_1275_0) in + (case + (case ((sep_matches_prefix stringappend_1276_0)) of + SOME (stringappend_1277_0,stringappend_1278_0) => + (stringappend_1277_0, stringappend_1278_0) + ) of + (() , stringappend_1278_0) => + let stringappend_1279_0 = (string_drop stringappend_1276_0 + stringappend_1278_0) in + let (imm, stringappend_1281_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1279_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1280_0,stringappend_1281_0) => + (stringappend_1280_0, stringappend_1281_0) + )) in + (case ((string_drop stringappend_1279_0 stringappend_1281_0)) of + "" => ADDIW (imm,rs1,rd) + ) + ) + ) + ) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1283_0,stringappend_1284_0) => + let stringappend_1285_0 = (string_drop stringappend_1076_0 stringappend_1284_0) in + if ((case ((spc_matches_prefix stringappend_1285_0)) of + SOME (stringappend_1286_0,stringappend_1287_0) => + let stringappend_1288_0 = (string_drop stringappend_1285_0 stringappend_1287_0) in + if ((case ((reg_name_matches_prefix stringappend_1288_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1289_0,stringappend_1290_0) => + let stringappend_1291_0 = (string_drop stringappend_1288_0 stringappend_1290_0) in + if ((case ((sep_matches_prefix stringappend_1291_0)) of + SOME (stringappend_1292_0,stringappend_1293_0) => + let stringappend_1294_0 = (string_drop stringappend_1291_0 stringappend_1293_0) in + if ((case ((reg_name_matches_prefix stringappend_1294_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1295_0,stringappend_1296_0) => + let stringappend_1297_0 = + (string_drop stringappend_1294_0 stringappend_1296_0) in + if ((case ((sep_matches_prefix stringappend_1297_0)) of + SOME (stringappend_1298_0,stringappend_1299_0) => + let stringappend_1300_0 = + (string_drop stringappend_1297_0 stringappend_1299_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1300_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1301_0,stringappend_1302_0) => + (case ((string_drop stringappend_1300_0 stringappend_1302_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1284_0) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1283_0,stringappend_1284_0) => + (stringappend_1283_0, stringappend_1284_0) + )) in + let stringappend_1285_0 = (string_drop stringappend_1076_0 stringappend_1284_0) in + (case + (case ((spc_matches_prefix stringappend_1285_0)) of + SOME (stringappend_1286_0,stringappend_1287_0) => + (stringappend_1286_0, stringappend_1287_0) + ) of + (() , stringappend_1287_0) => + let stringappend_1288_0 = (string_drop stringappend_1285_0 + stringappend_1287_0) in + let (rd, stringappend_1290_0) = + ((case ((reg_name_matches_prefix stringappend_1288_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1289_0,stringappend_1290_0) => + (stringappend_1289_0, stringappend_1290_0) + )) in + let stringappend_1291_0 = (string_drop stringappend_1288_0 + stringappend_1290_0) in + (case + (case ((sep_matches_prefix stringappend_1291_0)) of + SOME (stringappend_1292_0,stringappend_1293_0) => + (stringappend_1292_0, stringappend_1293_0) + ) of + (() , stringappend_1293_0) => + let stringappend_1294_0 = (string_drop stringappend_1291_0 + stringappend_1293_0) in + let (rs1, stringappend_1296_0) = + ((case ((reg_name_matches_prefix stringappend_1294_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1295_0,stringappend_1296_0) => + (stringappend_1295_0, stringappend_1296_0) + )) in + let stringappend_1297_0 = (string_drop stringappend_1294_0 + stringappend_1296_0) in + (case + (case ((sep_matches_prefix stringappend_1297_0)) of + SOME (stringappend_1298_0,stringappend_1299_0) => + (stringappend_1298_0, stringappend_1299_0) + ) of + (() , stringappend_1299_0) => + let stringappend_1300_0 = (string_drop stringappend_1297_0 + stringappend_1299_0) in + let (shamt, stringappend_1302_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1300_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1301_0,stringappend_1302_0) => + (stringappend_1301_0, stringappend_1302_0) + )) in + (case ((string_drop stringappend_1300_0 stringappend_1302_0)) of + "" => SHIFTW (shamt,rs1,rd,op) + ) + ) + ) + ) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1304_0,stringappend_1305_0) => + let stringappend_1306_0 = (string_drop stringappend_1076_0 stringappend_1305_0) in + if ((case ((spc_matches_prefix stringappend_1306_0)) of + SOME (stringappend_1307_0,stringappend_1308_0) => + let stringappend_1309_0 = (string_drop stringappend_1306_0 stringappend_1308_0) in + if ((case ((reg_name_matches_prefix stringappend_1309_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1310_0,stringappend_1311_0) => + let stringappend_1312_0 = (string_drop stringappend_1309_0 stringappend_1311_0) in + if ((case ((sep_matches_prefix stringappend_1312_0)) of + SOME (stringappend_1313_0,stringappend_1314_0) => + let stringappend_1315_0 = (string_drop stringappend_1312_0 stringappend_1314_0) in + if ((case ((reg_name_matches_prefix stringappend_1315_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1316_0,stringappend_1317_0) => + let stringappend_1318_0 = + (string_drop stringappend_1315_0 stringappend_1317_0) in + if ((case ((sep_matches_prefix stringappend_1318_0)) of + SOME (stringappend_1319_0,stringappend_1320_0) => + let stringappend_1321_0 = + (string_drop stringappend_1318_0 stringappend_1320_0) in + if ((case ((reg_name_matches_prefix stringappend_1321_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1322_0,stringappend_1323_0) => + (case ((string_drop stringappend_1321_0 stringappend_1323_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1305_0) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1304_0,stringappend_1305_0) => + (stringappend_1304_0, stringappend_1305_0) + )) in + let stringappend_1306_0 = (string_drop stringappend_1076_0 stringappend_1305_0) in + (case + (case ((spc_matches_prefix stringappend_1306_0)) of + SOME (stringappend_1307_0,stringappend_1308_0) => + (stringappend_1307_0, stringappend_1308_0) + ) of + (() , stringappend_1308_0) => + let stringappend_1309_0 = (string_drop stringappend_1306_0 + stringappend_1308_0) in + let (rd, stringappend_1311_0) = + ((case ((reg_name_matches_prefix stringappend_1309_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1310_0,stringappend_1311_0) => + (stringappend_1310_0, stringappend_1311_0) + )) in + let stringappend_1312_0 = (string_drop stringappend_1309_0 + stringappend_1311_0) in + (case + (case ((sep_matches_prefix stringappend_1312_0)) of + SOME (stringappend_1313_0,stringappend_1314_0) => + (stringappend_1313_0, stringappend_1314_0) + ) of + (() , stringappend_1314_0) => + let stringappend_1315_0 = (string_drop stringappend_1312_0 + stringappend_1314_0) in + let (rs1, stringappend_1317_0) = + ((case ((reg_name_matches_prefix stringappend_1315_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1316_0,stringappend_1317_0) => + (stringappend_1316_0, stringappend_1317_0) + )) in + let stringappend_1318_0 = (string_drop stringappend_1315_0 + stringappend_1317_0) in + (case + (case ((sep_matches_prefix stringappend_1318_0)) of + SOME (stringappend_1319_0,stringappend_1320_0) => + (stringappend_1319_0, stringappend_1320_0) + ) of + (() , stringappend_1320_0) => + let stringappend_1321_0 = (string_drop stringappend_1318_0 + stringappend_1320_0) in + let (rs2, stringappend_1323_0) = + ((case ((reg_name_matches_prefix stringappend_1321_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1322_0,stringappend_1323_0) => + (stringappend_1322_0, stringappend_1323_0) + )) in + (case ((string_drop stringappend_1321_0 stringappend_1323_0)) of + "" => RTYPEW (rs2,rs1,rd,op) + ) + ) + ) + ) + else if ((case ((mul_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1325_0,stringappend_1326_0) => + let stringappend_1327_0 = (string_drop stringappend_1076_0 stringappend_1326_0) in + if ((case ((spc_matches_prefix stringappend_1327_0)) of + SOME (stringappend_1328_0,stringappend_1329_0) => + let stringappend_1330_0 = (string_drop stringappend_1327_0 stringappend_1329_0) in + if ((case ((reg_name_matches_prefix stringappend_1330_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_1331_0,stringappend_1332_0) => + let stringappend_1333_0 = (string_drop stringappend_1330_0 stringappend_1332_0) in + if ((case ((sep_matches_prefix stringappend_1333_0)) of + SOME (stringappend_1334_0,stringappend_1335_0) => + let stringappend_1336_0 = (string_drop stringappend_1333_0 stringappend_1335_0) in + if ((case ((reg_name_matches_prefix stringappend_1336_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1337_0,stringappend_1338_0) => + let stringappend_1339_0 = + (string_drop stringappend_1336_0 stringappend_1338_0) in + if ((case ((sep_matches_prefix stringappend_1339_0)) of + SOME (stringappend_1340_0,stringappend_1341_0) => + let stringappend_1342_0 = + (string_drop stringappend_1339_0 stringappend_1341_0) in + if ((case ((reg_name_matches_prefix stringappend_1342_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1343_0,stringappend_1344_0) => + (case ((string_drop stringappend_1342_0 stringappend_1344_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let ((high, signed1, signed2), stringappend_1326_0) = + ((case ((mul_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1325_0,stringappend_1326_0) => + (stringappend_1325_0, stringappend_1326_0) + )) in + let stringappend_1327_0 = (string_drop stringappend_1076_0 stringappend_1326_0) in + (case + (case ((spc_matches_prefix stringappend_1327_0)) of + SOME (stringappend_1328_0,stringappend_1329_0) => + (stringappend_1328_0, stringappend_1329_0) + ) of + (() , stringappend_1329_0) => + let stringappend_1330_0 = (string_drop stringappend_1327_0 + stringappend_1329_0) in + let (rd, stringappend_1332_0) = + ((case ((reg_name_matches_prefix stringappend_1330_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1331_0,stringappend_1332_0) => + (stringappend_1331_0, stringappend_1332_0) + )) in + let stringappend_1333_0 = (string_drop stringappend_1330_0 + stringappend_1332_0) in + (case + (case ((sep_matches_prefix stringappend_1333_0)) of + SOME (stringappend_1334_0,stringappend_1335_0) => + (stringappend_1334_0, stringappend_1335_0) + ) of + (() , stringappend_1335_0) => + let stringappend_1336_0 = (string_drop stringappend_1333_0 + stringappend_1335_0) in + let (rs1, stringappend_1338_0) = + ((case ((reg_name_matches_prefix stringappend_1336_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1337_0,stringappend_1338_0) => + (stringappend_1337_0, stringappend_1338_0) + )) in + let stringappend_1339_0 = (string_drop stringappend_1336_0 + stringappend_1338_0) in + (case + (case ((sep_matches_prefix stringappend_1339_0)) of + SOME (stringappend_1340_0,stringappend_1341_0) => + (stringappend_1340_0, stringappend_1341_0) + ) of + (() , stringappend_1341_0) => + let stringappend_1342_0 = (string_drop stringappend_1339_0 + stringappend_1341_0) in + let (rs2, stringappend_1344_0) = + ((case ((reg_name_matches_prefix stringappend_1342_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1343_0,stringappend_1344_0) => + (stringappend_1343_0, stringappend_1344_0) + )) in + (case ((string_drop stringappend_1342_0 stringappend_1344_0)) of + "" => MUL (rs2,rs1,rd,high,signed1,signed2) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "div")) /\ (let stringappend_1346_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_1346_0)) of + SOME (stringappend_1347_0,stringappend_1348_0) => + let stringappend_1349_0 = (string_drop stringappend_1346_0 stringappend_1348_0) in + if ((case ((spc_matches_prefix stringappend_1349_0)) of + SOME (stringappend_1350_0,stringappend_1351_0) => + let stringappend_1352_0 = + (string_drop stringappend_1349_0 stringappend_1351_0) in + if ((case ((reg_name_matches_prefix stringappend_1352_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1353_0,stringappend_1354_0) => + let stringappend_1355_0 = + (string_drop stringappend_1352_0 stringappend_1354_0) in + if ((case ((sep_matches_prefix stringappend_1355_0)) of + SOME (stringappend_1356_0,stringappend_1357_0) => + let stringappend_1358_0 = + (string_drop stringappend_1355_0 stringappend_1357_0) in + if ((case ((reg_name_matches_prefix stringappend_1358_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1359_0,stringappend_1360_0) => + let stringappend_1361_0 = + (string_drop stringappend_1358_0 stringappend_1360_0) in + if ((case ((sep_matches_prefix stringappend_1361_0)) of + SOME (stringappend_1362_0,stringappend_1363_0) => + let stringappend_1364_0 = + (string_drop stringappend_1361_0 stringappend_1363_0) in + if ((case ((reg_name_matches_prefix stringappend_1364_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1365_0,stringappend_1366_0) => + (case ((string_drop stringappend_1364_0 + stringappend_1366_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1346_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in + let (s, stringappend_1348_0) = + ((case ((maybe_not_u_matches_prefix stringappend_1346_0)) of + SOME (stringappend_1347_0,stringappend_1348_0) => + (stringappend_1347_0, stringappend_1348_0) + )) in + let stringappend_1349_0 = (string_drop stringappend_1346_0 stringappend_1348_0) in + (case + (case ((spc_matches_prefix stringappend_1349_0)) of + SOME (stringappend_1350_0,stringappend_1351_0) => + (stringappend_1350_0, stringappend_1351_0) + ) of + (() , stringappend_1351_0) => + let stringappend_1352_0 = (string_drop stringappend_1349_0 + stringappend_1351_0) in + let (rd, stringappend_1354_0) = + ((case ((reg_name_matches_prefix stringappend_1352_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1353_0,stringappend_1354_0) => + (stringappend_1353_0, stringappend_1354_0) + )) in + let stringappend_1355_0 = (string_drop stringappend_1352_0 + stringappend_1354_0) in + (case + (case ((sep_matches_prefix stringappend_1355_0)) of + SOME (stringappend_1356_0,stringappend_1357_0) => + (stringappend_1356_0, stringappend_1357_0) + ) of + (() , stringappend_1357_0) => + let stringappend_1358_0 = (string_drop stringappend_1355_0 + stringappend_1357_0) in + let (rs1, stringappend_1360_0) = + ((case ((reg_name_matches_prefix stringappend_1358_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1359_0,stringappend_1360_0) => + (stringappend_1359_0, stringappend_1360_0) + )) in + let stringappend_1361_0 = (string_drop stringappend_1358_0 + stringappend_1360_0) in + (case + (case ((sep_matches_prefix stringappend_1361_0)) of + SOME (stringappend_1362_0,stringappend_1363_0) => + (stringappend_1362_0, stringappend_1363_0) + ) of + (() , stringappend_1363_0) => + let stringappend_1364_0 = (string_drop stringappend_1361_0 + stringappend_1363_0) in + let (rs2, stringappend_1366_0) = + ((case ((reg_name_matches_prefix stringappend_1364_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1365_0,stringappend_1366_0) => + (stringappend_1365_0, stringappend_1366_0) + )) in + (case ((string_drop stringappend_1364_0 stringappend_1366_0)) of + "" => DIV0 (rs2,rs1,rd,s) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "rem")) /\ (let stringappend_1368_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_1368_0)) of + SOME (stringappend_1369_0,stringappend_1370_0) => + let stringappend_1371_0 = (string_drop stringappend_1368_0 stringappend_1370_0) in + if ((case ((spc_matches_prefix stringappend_1371_0)) of + SOME (stringappend_1372_0,stringappend_1373_0) => + let stringappend_1374_0 = + (string_drop stringappend_1371_0 stringappend_1373_0) in + if ((case ((reg_name_matches_prefix stringappend_1374_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1375_0,stringappend_1376_0) => + let stringappend_1377_0 = + (string_drop stringappend_1374_0 stringappend_1376_0) in + if ((case ((sep_matches_prefix stringappend_1377_0)) of + SOME (stringappend_1378_0,stringappend_1379_0) => + let stringappend_1380_0 = + (string_drop stringappend_1377_0 stringappend_1379_0) in + if ((case ((reg_name_matches_prefix stringappend_1380_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1381_0,stringappend_1382_0) => + let stringappend_1383_0 = + (string_drop stringappend_1380_0 stringappend_1382_0) in + if ((case ((sep_matches_prefix stringappend_1383_0)) of + SOME (stringappend_1384_0,stringappend_1385_0) => + let stringappend_1386_0 = + (string_drop stringappend_1383_0 stringappend_1385_0) in + if ((case ((reg_name_matches_prefix stringappend_1386_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1387_0,stringappend_1388_0) => + (case ((string_drop stringappend_1386_0 + stringappend_1388_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1368_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in + let (s, stringappend_1370_0) = + ((case ((maybe_not_u_matches_prefix stringappend_1368_0)) of + SOME (stringappend_1369_0,stringappend_1370_0) => + (stringappend_1369_0, stringappend_1370_0) + )) in + let stringappend_1371_0 = (string_drop stringappend_1368_0 stringappend_1370_0) in + (case + (case ((spc_matches_prefix stringappend_1371_0)) of + SOME (stringappend_1372_0,stringappend_1373_0) => + (stringappend_1372_0, stringappend_1373_0) + ) of + (() , stringappend_1373_0) => + let stringappend_1374_0 = (string_drop stringappend_1371_0 + stringappend_1373_0) in + let (rd, stringappend_1376_0) = + ((case ((reg_name_matches_prefix stringappend_1374_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1375_0,stringappend_1376_0) => + (stringappend_1375_0, stringappend_1376_0) + )) in + let stringappend_1377_0 = (string_drop stringappend_1374_0 + stringappend_1376_0) in + (case + (case ((sep_matches_prefix stringappend_1377_0)) of + SOME (stringappend_1378_0,stringappend_1379_0) => + (stringappend_1378_0, stringappend_1379_0) + ) of + (() , stringappend_1379_0) => + let stringappend_1380_0 = (string_drop stringappend_1377_0 + stringappend_1379_0) in + let (rs1, stringappend_1382_0) = + ((case ((reg_name_matches_prefix stringappend_1380_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1381_0,stringappend_1382_0) => + (stringappend_1381_0, stringappend_1382_0) + )) in + let stringappend_1383_0 = (string_drop stringappend_1380_0 + stringappend_1382_0) in + (case + (case ((sep_matches_prefix stringappend_1383_0)) of + SOME (stringappend_1384_0,stringappend_1385_0) => + (stringappend_1384_0, stringappend_1385_0) + ) of + (() , stringappend_1385_0) => + let stringappend_1386_0 = (string_drop stringappend_1383_0 + stringappend_1385_0) in + let (rs2, stringappend_1388_0) = + ((case ((reg_name_matches_prefix stringappend_1386_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1387_0,stringappend_1388_0) => + (stringappend_1387_0, stringappend_1388_0) + )) in + (case ((string_drop stringappend_1386_0 stringappend_1388_0)) of + "" => REM (rs2,rs1,rd,s) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "mulw")) /\ (let stringappend_1390_0 = (string_drop stringappend_1076_0 ((string_length "mulw"))) in + if ((case ((spc_matches_prefix stringappend_1390_0)) of + SOME (stringappend_1391_0,stringappend_1392_0) => + let stringappend_1393_0 = (string_drop stringappend_1390_0 stringappend_1392_0) in + if ((case ((reg_name_matches_prefix stringappend_1393_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1394_0,stringappend_1395_0) => + let stringappend_1396_0 = + (string_drop stringappend_1393_0 stringappend_1395_0) in + if ((case ((sep_matches_prefix stringappend_1396_0)) of + SOME (stringappend_1397_0,stringappend_1398_0) => + let stringappend_1399_0 = + (string_drop stringappend_1396_0 stringappend_1398_0) in + if ((case ((reg_name_matches_prefix stringappend_1399_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1400_0,stringappend_1401_0) => + let stringappend_1402_0 = + (string_drop stringappend_1399_0 stringappend_1401_0) in + if ((case ((sep_matches_prefix stringappend_1402_0)) of + SOME (stringappend_1403_0,stringappend_1404_0) => + let stringappend_1405_0 = + (string_drop stringappend_1402_0 stringappend_1404_0) in + if ((case ((reg_name_matches_prefix stringappend_1405_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1406_0,stringappend_1407_0) => + (case ((string_drop stringappend_1405_0 + stringappend_1407_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1390_0 = (string_drop stringappend_1076_0 ((string_length "mulw"))) in + (case + (case ((spc_matches_prefix stringappend_1390_0)) of + SOME (stringappend_1391_0,stringappend_1392_0) => + (stringappend_1391_0, stringappend_1392_0) + ) of + (() , stringappend_1392_0) => + let stringappend_1393_0 = (string_drop stringappend_1390_0 + stringappend_1392_0) in + let (rd, stringappend_1395_0) = + ((case ((reg_name_matches_prefix stringappend_1393_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1394_0,stringappend_1395_0) => + (stringappend_1394_0, stringappend_1395_0) + )) in + let stringappend_1396_0 = (string_drop stringappend_1393_0 + stringappend_1395_0) in + (case + (case ((sep_matches_prefix stringappend_1396_0)) of + SOME (stringappend_1397_0,stringappend_1398_0) => + (stringappend_1397_0, stringappend_1398_0) + ) of + (() , stringappend_1398_0) => + let stringappend_1399_0 = (string_drop stringappend_1396_0 + stringappend_1398_0) in + let (rs1, stringappend_1401_0) = + ((case ((reg_name_matches_prefix stringappend_1399_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1400_0,stringappend_1401_0) => + (stringappend_1400_0, stringappend_1401_0) + )) in + let stringappend_1402_0 = (string_drop stringappend_1399_0 + stringappend_1401_0) in + (case + (case ((sep_matches_prefix stringappend_1402_0)) of + SOME (stringappend_1403_0,stringappend_1404_0) => + (stringappend_1403_0, stringappend_1404_0) + ) of + (() , stringappend_1404_0) => + let stringappend_1405_0 = (string_drop stringappend_1402_0 + stringappend_1404_0) in + let (rs2, stringappend_1407_0) = + ((case ((reg_name_matches_prefix stringappend_1405_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1406_0,stringappend_1407_0) => + (stringappend_1406_0, stringappend_1407_0) + )) in + (case ((string_drop stringappend_1405_0 stringappend_1407_0)) of + "" => MULW (rs2,rs1,rd) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "div")) /\ (let stringappend_1409_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_1409_0)) of + SOME (stringappend_1410_0,stringappend_1411_0) => + let stringappend_1412_0 = (string_drop stringappend_1409_0 stringappend_1411_0) in + if (((((string_startswith stringappend_1412_0 "w")) /\ (let stringappend_1413_0 = + (string_drop stringappend_1412_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_1413_0)) of + SOME (stringappend_1414_0,stringappend_1415_0) => + let stringappend_1416_0 = + (string_drop stringappend_1413_0 stringappend_1415_0) in + if ((case ((reg_name_matches_prefix stringappend_1416_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1417_0,stringappend_1418_0) => + let stringappend_1419_0 = + (string_drop stringappend_1416_0 stringappend_1418_0) in + if ((case ((sep_matches_prefix stringappend_1419_0)) of + SOME (stringappend_1420_0,stringappend_1421_0) => + let stringappend_1422_0 = + (string_drop stringappend_1419_0 stringappend_1421_0) in + if ((case ((reg_name_matches_prefix stringappend_1422_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1423_0,stringappend_1424_0) => + let stringappend_1425_0 = + (string_drop stringappend_1422_0 stringappend_1424_0) in + if ((case ((sep_matches_prefix stringappend_1425_0)) of + SOME (stringappend_1426_0,stringappend_1427_0) => + let stringappend_1428_0 = + (string_drop stringappend_1425_0 + stringappend_1427_0) in + if ((case ((reg_name_matches_prefix + stringappend_1428_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_1429_0,stringappend_1430_0) => + (case ((string_drop stringappend_1428_0 + stringappend_1430_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1409_0 = (string_drop stringappend_1076_0 ((string_length "div"))) in + let (s, stringappend_1411_0) = + ((case ((maybe_not_u_matches_prefix stringappend_1409_0)) of + SOME (stringappend_1410_0,stringappend_1411_0) => + (stringappend_1410_0, stringappend_1411_0) + )) in + let stringappend_1412_0 = (string_drop stringappend_1409_0 stringappend_1411_0) in + let stringappend_1413_0 = (string_drop stringappend_1412_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_1413_0)) of + SOME (stringappend_1414_0,stringappend_1415_0) => + (stringappend_1414_0, stringappend_1415_0) + ) of + (() , stringappend_1415_0) => + let stringappend_1416_0 = (string_drop stringappend_1413_0 + stringappend_1415_0) in + let (rd, stringappend_1418_0) = + ((case ((reg_name_matches_prefix stringappend_1416_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1417_0,stringappend_1418_0) => + (stringappend_1417_0, stringappend_1418_0) + )) in + let stringappend_1419_0 = (string_drop stringappend_1416_0 + stringappend_1418_0) in + (case + (case ((sep_matches_prefix stringappend_1419_0)) of + SOME (stringappend_1420_0,stringappend_1421_0) => + (stringappend_1420_0, stringappend_1421_0) + ) of + (() , stringappend_1421_0) => + let stringappend_1422_0 = (string_drop stringappend_1419_0 + stringappend_1421_0) in + let (rs1, stringappend_1424_0) = + ((case ((reg_name_matches_prefix stringappend_1422_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1423_0,stringappend_1424_0) => + (stringappend_1423_0, stringappend_1424_0) + )) in + let stringappend_1425_0 = (string_drop stringappend_1422_0 + stringappend_1424_0) in + (case + (case ((sep_matches_prefix stringappend_1425_0)) of + SOME (stringappend_1426_0,stringappend_1427_0) => + (stringappend_1426_0, stringappend_1427_0) + ) of + (() , stringappend_1427_0) => + let stringappend_1428_0 = (string_drop stringappend_1425_0 + stringappend_1427_0) in + let (rs2, stringappend_1430_0) = + ((case ((reg_name_matches_prefix stringappend_1428_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1429_0,stringappend_1430_0) => + (stringappend_1429_0, stringappend_1430_0) + )) in + (case ((string_drop stringappend_1428_0 stringappend_1430_0)) of + "" => DIVW (rs2,rs1,rd,s) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "rem")) /\ (let stringappend_1432_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_1432_0)) of + SOME (stringappend_1433_0,stringappend_1434_0) => + let stringappend_1435_0 = (string_drop stringappend_1432_0 stringappend_1434_0) in + if (((((string_startswith stringappend_1435_0 "w")) /\ (let stringappend_1436_0 = + (string_drop stringappend_1435_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_1436_0)) of + SOME (stringappend_1437_0,stringappend_1438_0) => + let stringappend_1439_0 = + (string_drop stringappend_1436_0 stringappend_1438_0) in + if ((case ((reg_name_matches_prefix stringappend_1439_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1440_0,stringappend_1441_0) => + let stringappend_1442_0 = + (string_drop stringappend_1439_0 stringappend_1441_0) in + if ((case ((sep_matches_prefix stringappend_1442_0)) of + SOME (stringappend_1443_0,stringappend_1444_0) => + let stringappend_1445_0 = + (string_drop stringappend_1442_0 stringappend_1444_0) in + if ((case ((reg_name_matches_prefix stringappend_1445_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1446_0,stringappend_1447_0) => + let stringappend_1448_0 = + (string_drop stringappend_1445_0 stringappend_1447_0) in + if ((case ((sep_matches_prefix stringappend_1448_0)) of + SOME (stringappend_1449_0,stringappend_1450_0) => + let stringappend_1451_0 = + (string_drop stringappend_1448_0 + stringappend_1450_0) in + if ((case ((reg_name_matches_prefix + stringappend_1451_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_1452_0,stringappend_1453_0) => + (case ((string_drop stringappend_1451_0 + stringappend_1453_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1432_0 = (string_drop stringappend_1076_0 ((string_length "rem"))) in + let (s, stringappend_1434_0) = + ((case ((maybe_not_u_matches_prefix stringappend_1432_0)) of + SOME (stringappend_1433_0,stringappend_1434_0) => + (stringappend_1433_0, stringappend_1434_0) + )) in + let stringappend_1435_0 = (string_drop stringappend_1432_0 stringappend_1434_0) in + let stringappend_1436_0 = (string_drop stringappend_1435_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_1436_0)) of + SOME (stringappend_1437_0,stringappend_1438_0) => + (stringappend_1437_0, stringappend_1438_0) + ) of + (() , stringappend_1438_0) => + let stringappend_1439_0 = (string_drop stringappend_1436_0 + stringappend_1438_0) in + let (rd, stringappend_1441_0) = + ((case ((reg_name_matches_prefix stringappend_1439_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1440_0,stringappend_1441_0) => + (stringappend_1440_0, stringappend_1441_0) + )) in + let stringappend_1442_0 = (string_drop stringappend_1439_0 + stringappend_1441_0) in + (case + (case ((sep_matches_prefix stringappend_1442_0)) of + SOME (stringappend_1443_0,stringappend_1444_0) => + (stringappend_1443_0, stringappend_1444_0) + ) of + (() , stringappend_1444_0) => + let stringappend_1445_0 = (string_drop stringappend_1442_0 + stringappend_1444_0) in + let (rs1, stringappend_1447_0) = + ((case ((reg_name_matches_prefix stringappend_1445_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1446_0,stringappend_1447_0) => + (stringappend_1446_0, stringappend_1447_0) + )) in + let stringappend_1448_0 = (string_drop stringappend_1445_0 + stringappend_1447_0) in + (case + (case ((sep_matches_prefix stringappend_1448_0)) of + SOME (stringappend_1449_0,stringappend_1450_0) => + (stringappend_1449_0, stringappend_1450_0) + ) of + (() , stringappend_1450_0) => + let stringappend_1451_0 = (string_drop stringappend_1448_0 + stringappend_1450_0) in + let (rs2, stringappend_1453_0) = + ((case ((reg_name_matches_prefix stringappend_1451_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1452_0,stringappend_1453_0) => + (stringappend_1452_0, stringappend_1453_0) + )) in + (case ((string_drop stringappend_1451_0 stringappend_1453_0)) of + "" => REMW (rs2,rs1,rd,s) + ) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "fence")) /\ (let stringappend_1455_0 = (string_drop stringappend_1076_0 ((string_length "fence"))) in + if ((case ((spc_matches_prefix stringappend_1455_0)) of + SOME (stringappend_1456_0,stringappend_1457_0) => + let stringappend_1458_0 = (string_drop stringappend_1455_0 stringappend_1457_0) in + if ((case ((fence_bits_matches_prefix stringappend_1458_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_1459_0,stringappend_1460_0) => + let stringappend_1461_0 = + (string_drop stringappend_1458_0 stringappend_1460_0) in + if ((case ((sep_matches_prefix stringappend_1461_0)) of + SOME (stringappend_1462_0,stringappend_1463_0) => + let stringappend_1464_0 = + (string_drop stringappend_1461_0 stringappend_1463_0) in + if ((case ((fence_bits_matches_prefix stringappend_1464_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_1465_0,stringappend_1466_0) => + (case ((string_drop stringappend_1464_0 stringappend_1466_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1455_0 = (string_drop stringappend_1076_0 ((string_length "fence"))) in + (case + (case ((spc_matches_prefix stringappend_1455_0)) of + SOME (stringappend_1456_0,stringappend_1457_0) => + (stringappend_1456_0, stringappend_1457_0) + ) of + (() , stringappend_1457_0) => + let stringappend_1458_0 = (string_drop stringappend_1455_0 + stringappend_1457_0) in + let (pred, stringappend_1460_0) = + ((case ((fence_bits_matches_prefix stringappend_1458_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_1459_0,stringappend_1460_0) => + (stringappend_1459_0, stringappend_1460_0) + )) in + let stringappend_1461_0 = (string_drop stringappend_1458_0 + stringappend_1460_0) in + (case + (case ((sep_matches_prefix stringappend_1461_0)) of + SOME (stringappend_1462_0,stringappend_1463_0) => + (stringappend_1462_0, stringappend_1463_0) + ) of + (() , stringappend_1463_0) => + let stringappend_1464_0 = (string_drop stringappend_1461_0 + stringappend_1463_0) in + let (succ, stringappend_1466_0) = + ((case ((fence_bits_matches_prefix stringappend_1464_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_1465_0,stringappend_1466_0) => + (stringappend_1465_0, stringappend_1466_0) + )) in + (case ((string_drop stringappend_1464_0 stringappend_1466_0)) of + "" => FENCE (pred,succ) + ) + ) + ) + else + (case stringappend_1076_0 of + "fence.i" => FENCEI () + | "ecall" => ECALL () + | "mret" => MRET () + | "sret" => SRET () + | "ebreak" => EBREAK () + | "wfi" => WFI () + | stringappend_1076_0 => + if (((((string_startswith stringappend_1076_0 "sfence.vma")) /\ (let stringappend_1468_0 = + (string_drop stringappend_1076_0 ((string_length "sfence.vma"))) in + if ((case ((spc_matches_prefix stringappend_1468_0)) of + SOME (stringappend_1469_0,stringappend_1470_0) => + let stringappend_1471_0 = (string_drop stringappend_1468_0 stringappend_1470_0) in + if ((case ((reg_name_matches_prefix stringappend_1471_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1472_0,stringappend_1473_0) => + let stringappend_1474_0 = + (string_drop stringappend_1471_0 stringappend_1473_0) in + if ((case ((sep_matches_prefix stringappend_1474_0)) of + SOME (stringappend_1475_0,stringappend_1476_0) => + let stringappend_1477_0 = + (string_drop stringappend_1474_0 stringappend_1476_0) in + if ((case ((reg_name_matches_prefix stringappend_1477_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1478_0,stringappend_1479_0) => + (case ((string_drop stringappend_1477_0 stringappend_1479_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1468_0 = (string_drop stringappend_1076_0 ((string_length "sfence.vma"))) in + (case + (case ((spc_matches_prefix stringappend_1468_0)) of + SOME (stringappend_1469_0,stringappend_1470_0) => + (stringappend_1469_0, stringappend_1470_0) + ) of + (() , stringappend_1470_0) => + let stringappend_1471_0 = (string_drop stringappend_1468_0 + stringappend_1470_0) in + let (rs1, stringappend_1473_0) = + ((case ((reg_name_matches_prefix stringappend_1471_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1472_0,stringappend_1473_0) => + (stringappend_1472_0, stringappend_1473_0) + )) in + let stringappend_1474_0 = (string_drop stringappend_1471_0 + stringappend_1473_0) in + (case + (case ((sep_matches_prefix stringappend_1474_0)) of + SOME (stringappend_1475_0,stringappend_1476_0) => + (stringappend_1475_0, stringappend_1476_0) + ) of + (() , stringappend_1476_0) => + let stringappend_1477_0 = (string_drop stringappend_1474_0 + stringappend_1476_0) in + let (rs2, stringappend_1479_0) = + ((case ((reg_name_matches_prefix stringappend_1477_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1478_0,stringappend_1479_0) => + (stringappend_1478_0, stringappend_1479_0) + )) in + (case ((string_drop stringappend_1477_0 stringappend_1479_0)) of + "" => SFENCE_VMA (rs1,rs2) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "lr.")) /\ (let stringappend_1481_0 = + (string_drop stringappend_1076_0 ((string_length "lr."))) in + if ((case ((maybe_aq_matches_prefix stringappend_1481_0)) of + SOME (stringappend_1482_0,stringappend_1483_0) => + let stringappend_1484_0 = + (string_drop stringappend_1481_0 stringappend_1483_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1484_0)) of + SOME (stringappend_1485_0,stringappend_1486_0) => + let stringappend_1487_0 = + (string_drop stringappend_1484_0 stringappend_1486_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_1487_0)) of + SOME (stringappend_1488_0,stringappend_1489_0) => + let stringappend_1490_0 = + (string_drop stringappend_1487_0 stringappend_1489_0) in + if ((case ((spc_matches_prefix stringappend_1490_0)) of + SOME (stringappend_1491_0,stringappend_1492_0) => + let stringappend_1493_0 = + (string_drop stringappend_1490_0 stringappend_1492_0) in + if ((case ((reg_name_matches_prefix stringappend_1493_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1494_0,stringappend_1495_0) => + let stringappend_1496_0 = + (string_drop stringappend_1493_0 stringappend_1495_0) in + if ((case ((sep_matches_prefix stringappend_1496_0)) of + SOME (stringappend_1497_0,stringappend_1498_0) => + let stringappend_1499_0 = + (string_drop stringappend_1496_0 + stringappend_1498_0) in + if ((case ((reg_name_matches_prefix + stringappend_1499_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1500_0,stringappend_1501_0) => + (case ((string_drop stringappend_1499_0 + stringappend_1501_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1481_0 = (string_drop stringappend_1076_0 ((string_length "lr."))) in + let (aq, stringappend_1483_0) = + ((case ((maybe_aq_matches_prefix stringappend_1481_0)) of + SOME (stringappend_1482_0,stringappend_1483_0) => + (stringappend_1482_0, stringappend_1483_0) + )) in + let stringappend_1484_0 = (string_drop stringappend_1481_0 stringappend_1483_0) in + let (rl, stringappend_1486_0) = + ((case ((maybe_rl_matches_prefix stringappend_1484_0)) of + SOME (stringappend_1485_0,stringappend_1486_0) => + (stringappend_1485_0, stringappend_1486_0) + )) in + let stringappend_1487_0 = (string_drop stringappend_1484_0 stringappend_1486_0) in + let (size1, stringappend_1489_0) = + ((case ((size_mnemonic_matches_prefix stringappend_1487_0)) of + SOME (stringappend_1488_0,stringappend_1489_0) => + (stringappend_1488_0, stringappend_1489_0) + )) in + let stringappend_1490_0 = (string_drop stringappend_1487_0 stringappend_1489_0) in + (case + (case ((spc_matches_prefix stringappend_1490_0)) of + SOME (stringappend_1491_0,stringappend_1492_0) => + (stringappend_1491_0, stringappend_1492_0) + ) of + (() , stringappend_1492_0) => + let stringappend_1493_0 = (string_drop stringappend_1490_0 + stringappend_1492_0) in + let (rd, stringappend_1495_0) = + ((case ((reg_name_matches_prefix stringappend_1493_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1494_0,stringappend_1495_0) => + (stringappend_1494_0, stringappend_1495_0) + )) in + let stringappend_1496_0 = (string_drop stringappend_1493_0 + stringappend_1495_0) in + (case + (case ((sep_matches_prefix stringappend_1496_0)) of + SOME (stringappend_1497_0,stringappend_1498_0) => + (stringappend_1497_0, stringappend_1498_0) + ) of + (() , stringappend_1498_0) => + let stringappend_1499_0 = (string_drop stringappend_1496_0 + stringappend_1498_0) in + let (rs1, stringappend_1501_0) = + ((case ((reg_name_matches_prefix stringappend_1499_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1500_0,stringappend_1501_0) => + (stringappend_1500_0, stringappend_1501_0) + )) in + (case ((string_drop stringappend_1499_0 stringappend_1501_0)) of + "" => LOADRES (aq,rl,rs1,size1,rd) + ) + ) + ) + else if (((((string_startswith stringappend_1076_0 "sc.")) /\ (let stringappend_1503_0 = + (string_drop stringappend_1076_0 ((string_length "sc."))) in + if ((case ((maybe_aq_matches_prefix stringappend_1503_0)) of + SOME (stringappend_1504_0,stringappend_1505_0) => + let stringappend_1506_0 = + (string_drop stringappend_1503_0 stringappend_1505_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1506_0)) of + SOME (stringappend_1507_0,stringappend_1508_0) => + let stringappend_1509_0 = + (string_drop stringappend_1506_0 stringappend_1508_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_1509_0)) of + SOME (stringappend_1510_0,stringappend_1511_0) => + let stringappend_1512_0 = + (string_drop stringappend_1509_0 stringappend_1511_0) in + if ((case ((spc_matches_prefix stringappend_1512_0)) of + SOME (stringappend_1513_0,stringappend_1514_0) => + let stringappend_1515_0 = + (string_drop stringappend_1512_0 stringappend_1514_0) in + if ((case ((reg_name_matches_prefix stringappend_1515_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1516_0,stringappend_1517_0) => + let stringappend_1518_0 = + (string_drop stringappend_1515_0 stringappend_1517_0) in + if ((case ((sep_matches_prefix stringappend_1518_0)) of + SOME (stringappend_1519_0,stringappend_1520_0) => + let stringappend_1521_0 = + (string_drop stringappend_1518_0 + stringappend_1520_0) in + if ((case ((reg_name_matches_prefix + stringappend_1521_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1522_0,stringappend_1523_0) => + let stringappend_1524_0 = + (string_drop stringappend_1521_0 + stringappend_1523_0) in + if ((case ((sep_matches_prefix + stringappend_1524_0)) of + SOME + (stringappend_1525_0,stringappend_1526_0) => + let stringappend_1527_0 = + (string_drop stringappend_1524_0 + stringappend_1526_0) in + if ((case ((reg_name_matches_prefix + stringappend_1527_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_1528_0,stringappend_1529_0) => + (case ((string_drop + stringappend_1527_0 + stringappend_1529_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1503_0 = (string_drop stringappend_1076_0 ((string_length "sc."))) in + let (aq, stringappend_1505_0) = + ((case ((maybe_aq_matches_prefix stringappend_1503_0)) of + SOME (stringappend_1504_0,stringappend_1505_0) => + (stringappend_1504_0, stringappend_1505_0) + )) in + let stringappend_1506_0 = (string_drop stringappend_1503_0 stringappend_1505_0) in + let (rl, stringappend_1508_0) = + ((case ((maybe_rl_matches_prefix stringappend_1506_0)) of + SOME (stringappend_1507_0,stringappend_1508_0) => + (stringappend_1507_0, stringappend_1508_0) + )) in + let stringappend_1509_0 = (string_drop stringappend_1506_0 stringappend_1508_0) in + let (size1, stringappend_1511_0) = + ((case ((size_mnemonic_matches_prefix stringappend_1509_0)) of + SOME (stringappend_1510_0,stringappend_1511_0) => + (stringappend_1510_0, stringappend_1511_0) + )) in + let stringappend_1512_0 = (string_drop stringappend_1509_0 stringappend_1511_0) in + (case + (case ((spc_matches_prefix stringappend_1512_0)) of + SOME (stringappend_1513_0,stringappend_1514_0) => + (stringappend_1513_0, stringappend_1514_0) + ) of + (() , stringappend_1514_0) => + let stringappend_1515_0 = (string_drop stringappend_1512_0 + stringappend_1514_0) in + let (rd, stringappend_1517_0) = + ((case ((reg_name_matches_prefix stringappend_1515_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1516_0,stringappend_1517_0) => + (stringappend_1516_0, stringappend_1517_0) + )) in + let stringappend_1518_0 = (string_drop stringappend_1515_0 + stringappend_1517_0) in + (case + (case ((sep_matches_prefix stringappend_1518_0)) of + SOME (stringappend_1519_0,stringappend_1520_0) => + (stringappend_1519_0, stringappend_1520_0) + ) of + (() , stringappend_1520_0) => + let stringappend_1521_0 = (string_drop stringappend_1518_0 + stringappend_1520_0) in + let (rs1, stringappend_1523_0) = + ((case ((reg_name_matches_prefix stringappend_1521_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1522_0,stringappend_1523_0) => + (stringappend_1522_0, stringappend_1523_0) + )) in + let stringappend_1524_0 = (string_drop stringappend_1521_0 + stringappend_1523_0) in + (case + (case ((sep_matches_prefix stringappend_1524_0)) of + SOME (stringappend_1525_0,stringappend_1526_0) => + (stringappend_1525_0, stringappend_1526_0) + ) of + (() , stringappend_1526_0) => + let stringappend_1527_0 = (string_drop stringappend_1524_0 + stringappend_1526_0) in + let (rs2, stringappend_1529_0) = + ((case ((reg_name_matches_prefix stringappend_1527_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1528_0,stringappend_1529_0) => + (stringappend_1528_0, stringappend_1529_0) + )) in + (case ((string_drop stringappend_1527_0 stringappend_1529_0)) of + "" => STORECON (aq,rl,rs2,rs1,size1,rd) + ) + ) + ) + ) + else if ((case ((amo_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1531_0,stringappend_1532_0) => + let stringappend_1533_0 = (string_drop stringappend_1076_0 stringappend_1532_0) in + if (((((string_startswith stringappend_1533_0 ".")) /\ (let stringappend_1534_0 = (string_drop stringappend_1533_0 ((string_length "."))) in + if ((case ((size_mnemonic_matches_prefix stringappend_1534_0)) of + SOME (stringappend_1535_0,stringappend_1536_0) => + let stringappend_1537_0 = + (string_drop stringappend_1534_0 stringappend_1536_0) in + if ((case ((maybe_aq_matches_prefix stringappend_1537_0)) of + SOME (stringappend_1538_0,stringappend_1539_0) => + let stringappend_1540_0 = + (string_drop stringappend_1537_0 stringappend_1539_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1540_0)) of + SOME (stringappend_1541_0,stringappend_1542_0) => + let stringappend_1543_0 = + (string_drop stringappend_1540_0 stringappend_1542_0) in + if ((case ((spc_matches_prefix stringappend_1543_0)) of + SOME (stringappend_1544_0,stringappend_1545_0) => + let stringappend_1546_0 = + (string_drop stringappend_1543_0 stringappend_1545_0) in + if ((case ((reg_name_matches_prefix stringappend_1546_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1547_0,stringappend_1548_0) => + let stringappend_1549_0 = + (string_drop stringappend_1546_0 stringappend_1548_0) in + if ((case ((sep_matches_prefix stringappend_1549_0)) of + SOME (stringappend_1550_0,stringappend_1551_0) => + let stringappend_1552_0 = + (string_drop stringappend_1549_0 + stringappend_1551_0) in + if ((case ((reg_name_matches_prefix + stringappend_1552_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1553_0,stringappend_1554_0) => + let stringappend_1555_0 = + (string_drop stringappend_1552_0 + stringappend_1554_0) in + if ((case ((sep_matches_prefix + stringappend_1555_0)) of + SOME + (stringappend_1556_0,stringappend_1557_0) => + let stringappend_1558_0 = + (string_drop stringappend_1555_0 + stringappend_1557_0) in + if ((case ((reg_name_matches_prefix + stringappend_1558_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_1559_0,stringappend_1560_0) => + (case ((string_drop + stringappend_1558_0 + stringappend_1560_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_1532_0) = + ((case ((amo_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1531_0,stringappend_1532_0) => + (stringappend_1531_0, stringappend_1532_0) + )) in + let stringappend_1533_0 = (string_drop stringappend_1076_0 stringappend_1532_0) in + let stringappend_1534_0 = (string_drop stringappend_1533_0 ((string_length "."))) in + let (width, stringappend_1536_0) = + ((case ((size_mnemonic_matches_prefix stringappend_1534_0)) of + SOME (stringappend_1535_0,stringappend_1536_0) => + (stringappend_1535_0, stringappend_1536_0) + )) in + let stringappend_1537_0 = (string_drop stringappend_1534_0 stringappend_1536_0) in + let (aq, stringappend_1539_0) = + ((case ((maybe_aq_matches_prefix stringappend_1537_0)) of + SOME (stringappend_1538_0,stringappend_1539_0) => + (stringappend_1538_0, stringappend_1539_0) + )) in + let stringappend_1540_0 = (string_drop stringappend_1537_0 stringappend_1539_0) in + let (rl, stringappend_1542_0) = + ((case ((maybe_rl_matches_prefix stringappend_1540_0)) of + SOME (stringappend_1541_0,stringappend_1542_0) => + (stringappend_1541_0, stringappend_1542_0) + )) in + let stringappend_1543_0 = (string_drop stringappend_1540_0 stringappend_1542_0) in + (case + (case ((spc_matches_prefix stringappend_1543_0)) of + SOME (stringappend_1544_0,stringappend_1545_0) => + (stringappend_1544_0, stringappend_1545_0) + ) of + (() , stringappend_1545_0) => + let stringappend_1546_0 = (string_drop stringappend_1543_0 + stringappend_1545_0) in + let (rd, stringappend_1548_0) = + ((case ((reg_name_matches_prefix stringappend_1546_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1547_0,stringappend_1548_0) => + (stringappend_1547_0, stringappend_1548_0) + )) in + let stringappend_1549_0 = (string_drop stringappend_1546_0 + stringappend_1548_0) in + (case + (case ((sep_matches_prefix stringappend_1549_0)) of + SOME (stringappend_1550_0,stringappend_1551_0) => + (stringappend_1550_0, stringappend_1551_0) + ) of + (() , stringappend_1551_0) => + let stringappend_1552_0 = (string_drop stringappend_1549_0 + stringappend_1551_0) in + let (rs1, stringappend_1554_0) = + ((case ((reg_name_matches_prefix stringappend_1552_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1553_0,stringappend_1554_0) => + (stringappend_1553_0, stringappend_1554_0) + )) in + let stringappend_1555_0 = (string_drop stringappend_1552_0 + stringappend_1554_0) in + (case + (case ((sep_matches_prefix stringappend_1555_0)) of + SOME (stringappend_1556_0,stringappend_1557_0) => + (stringappend_1556_0, stringappend_1557_0) + ) of + (() , stringappend_1557_0) => + let stringappend_1558_0 = (string_drop stringappend_1555_0 + stringappend_1557_0) in + let (rs2, stringappend_1560_0) = + ((case ((reg_name_matches_prefix stringappend_1558_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1559_0,stringappend_1560_0) => + (stringappend_1559_0, stringappend_1560_0) + )) in + (case ((string_drop stringappend_1558_0 stringappend_1560_0)) of + "" => AMO (op,aq,rl,rs2,rs1,width,rd) + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1562_0,stringappend_1563_0) => + let stringappend_1564_0 = (string_drop stringappend_1076_0 stringappend_1563_0) in + if (((((string_startswith stringappend_1564_0 "i")) /\ (let stringappend_1565_0 = (string_drop stringappend_1564_0 ((string_length "i"))) in + if ((case ((spc_matches_prefix stringappend_1565_0)) of + SOME (stringappend_1566_0,stringappend_1567_0) => + let stringappend_1568_0 = + (string_drop stringappend_1565_0 stringappend_1567_0) in + if ((case ((reg_name_matches_prefix stringappend_1568_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1569_0,stringappend_1570_0) => + let stringappend_1571_0 = + (string_drop stringappend_1568_0 stringappend_1570_0) in + if ((case ((sep_matches_prefix stringappend_1571_0)) of + SOME (stringappend_1572_0,stringappend_1573_0) => + let stringappend_1574_0 = + (string_drop stringappend_1571_0 stringappend_1573_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1574_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1575_0,stringappend_1576_0) => + let stringappend_1577_0 = + (string_drop stringappend_1574_0 stringappend_1576_0) in + if ((case ((sep_matches_prefix stringappend_1577_0)) of + SOME (stringappend_1578_0,stringappend_1579_0) => + let stringappend_1580_0 = + (string_drop stringappend_1577_0 stringappend_1579_0) in + if ((case ((csr_name_map_matches_prefix + stringappend_1580_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1581_0,stringappend_1582_0) => + (case ((string_drop stringappend_1580_0 + stringappend_1582_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_1563_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1562_0,stringappend_1563_0) => + (stringappend_1562_0, stringappend_1563_0) + )) in + let stringappend_1564_0 = (string_drop stringappend_1076_0 stringappend_1563_0) in + let stringappend_1565_0 = (string_drop stringappend_1564_0 ((string_length "i"))) in + (case + (case ((spc_matches_prefix stringappend_1565_0)) of + SOME (stringappend_1566_0,stringappend_1567_0) => + (stringappend_1566_0, stringappend_1567_0) + ) of + (() , stringappend_1567_0) => + let stringappend_1568_0 = (string_drop stringappend_1565_0 + stringappend_1567_0) in + let (rd, stringappend_1570_0) = + ((case ((reg_name_matches_prefix stringappend_1568_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1569_0,stringappend_1570_0) => + (stringappend_1569_0, stringappend_1570_0) + )) in + let stringappend_1571_0 = (string_drop stringappend_1568_0 + stringappend_1570_0) in + (case + (case ((sep_matches_prefix stringappend_1571_0)) of + SOME (stringappend_1572_0,stringappend_1573_0) => + (stringappend_1572_0, stringappend_1573_0) + ) of + (() , stringappend_1573_0) => + let stringappend_1574_0 = (string_drop stringappend_1571_0 + stringappend_1573_0) in + let (rs1, stringappend_1576_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1574_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1575_0,stringappend_1576_0) => + (stringappend_1575_0, stringappend_1576_0) + )) in + let stringappend_1577_0 = (string_drop stringappend_1574_0 + stringappend_1576_0) in + (case + (case ((sep_matches_prefix stringappend_1577_0)) of + SOME (stringappend_1578_0,stringappend_1579_0) => + (stringappend_1578_0, stringappend_1579_0) + ) of + (() , stringappend_1579_0) => + let stringappend_1580_0 = (string_drop stringappend_1577_0 + stringappend_1579_0) in + let (csr, stringappend_1582_0) = + ((case ((csr_name_map_matches_prefix stringappend_1580_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1581_0,stringappend_1582_0) => + (stringappend_1581_0, stringappend_1582_0) + )) in + (case ((string_drop stringappend_1580_0 stringappend_1582_0)) of + "" => CSR (csr,rs1,rd,T,op) + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1584_0,stringappend_1585_0) => + let stringappend_1586_0 = (string_drop stringappend_1076_0 stringappend_1585_0) in + if ((case ((spc_matches_prefix stringappend_1586_0)) of + SOME (stringappend_1587_0,stringappend_1588_0) => + let stringappend_1589_0 = (string_drop stringappend_1586_0 stringappend_1588_0) in + if ((case ((reg_name_matches_prefix stringappend_1589_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1590_0,stringappend_1591_0) => + let stringappend_1592_0 = (string_drop stringappend_1589_0 stringappend_1591_0) in + if ((case ((sep_matches_prefix stringappend_1592_0)) of + SOME (stringappend_1593_0,stringappend_1594_0) => + let stringappend_1595_0 = + (string_drop stringappend_1592_0 stringappend_1594_0) in + if ((case ((reg_name_matches_prefix stringappend_1595_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1596_0,stringappend_1597_0) => + let stringappend_1598_0 = + (string_drop stringappend_1595_0 stringappend_1597_0) in + if ((case ((sep_matches_prefix stringappend_1598_0)) of + SOME (stringappend_1599_0,stringappend_1600_0) => + let stringappend_1601_0 = + (string_drop stringappend_1598_0 stringappend_1600_0) in + if ((case ((csr_name_map_matches_prefix stringappend_1601_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1602_0,stringappend_1603_0) => + (case ((string_drop stringappend_1601_0 + stringappend_1603_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1585_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_1076_0)) of + SOME (stringappend_1584_0,stringappend_1585_0) => + (stringappend_1584_0, stringappend_1585_0) + )) in + let stringappend_1586_0 = (string_drop stringappend_1076_0 stringappend_1585_0) in + (case + (case ((spc_matches_prefix stringappend_1586_0)) of + SOME (stringappend_1587_0,stringappend_1588_0) => + (stringappend_1587_0, stringappend_1588_0) + ) of + (() , stringappend_1588_0) => + let stringappend_1589_0 = (string_drop stringappend_1586_0 + stringappend_1588_0) in + let (rd, stringappend_1591_0) = + ((case ((reg_name_matches_prefix stringappend_1589_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1590_0,stringappend_1591_0) => + (stringappend_1590_0, stringappend_1591_0) + )) in + let stringappend_1592_0 = (string_drop stringappend_1589_0 + stringappend_1591_0) in + (case + (case ((sep_matches_prefix stringappend_1592_0)) of + SOME (stringappend_1593_0,stringappend_1594_0) => + (stringappend_1593_0, stringappend_1594_0) + ) of + (() , stringappend_1594_0) => + let stringappend_1595_0 = (string_drop stringappend_1592_0 + stringappend_1594_0) in + let (rs1, stringappend_1597_0) = + ((case ((reg_name_matches_prefix stringappend_1595_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1596_0,stringappend_1597_0) => + (stringappend_1596_0, stringappend_1597_0) + )) in + let stringappend_1598_0 = (string_drop stringappend_1595_0 + stringappend_1597_0) in + (case + (case ((sep_matches_prefix stringappend_1598_0)) of + SOME (stringappend_1599_0,stringappend_1600_0) => + (stringappend_1599_0, stringappend_1600_0) + ) of + (() , stringappend_1600_0) => + let stringappend_1601_0 = (string_drop stringappend_1598_0 + stringappend_1600_0) in + let (csr, stringappend_1603_0) = + ((case ((csr_name_map_matches_prefix stringappend_1601_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1602_0,stringappend_1603_0) => + (stringappend_1602_0, stringappend_1603_0) + )) in + (case ((string_drop stringappend_1601_0 stringappend_1603_0)) of + "" => CSR (csr,rs1,rd,F,op) + ) + ) + ) + ) + else + let stringappend_1605_0 = (string_drop stringappend_1076_0 ((string_length "illegal"))) in + (case + (case ((spc_matches_prefix stringappend_1605_0)) of + SOME (stringappend_1606_0,stringappend_1607_0) => + (stringappend_1606_0, stringappend_1607_0) + ) of + (() , stringappend_1607_0) => + let stringappend_1608_0 = (string_drop stringappend_1605_0 + stringappend_1607_0) in + let (s, stringappend_1610_0) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1608_0 : (( 32 words$word # ii)) option)) of + SOME (stringappend_1609_0,stringappend_1610_0) => + (stringappend_1609_0, stringappend_1610_0) + )) in + (case ((string_drop stringappend_1608_0 stringappend_1610_0)) of + "" => ILLEGAL s + ) + ) + )))`; + + +(*val assembly_forwards_matches : ast -> bool*) + +val _ = Define ` + ((assembly_forwards_matches:ast -> bool) arg_= + ((case arg_ of + UTYPE (imm,rd,op) => T + | RISCV_JAL (imm,rd) => T + | RISCV_JALR (imm,rs1,rd) => T + | BTYPE (imm,rs2,rs1,op) => T + | ITYPE (imm,rs1,rd,op) => T + | SHIFTIOP (shamt,rs1,rd,op) => T + | RTYPE (rs2,rs1,rd,op) => T + | LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl) => T + | STORE (imm,rs1,rd,size1,aq,rl) => T + | ADDIW (imm,rs1,rd) => T + | SHIFTW (shamt,rs1,rd,op) => T + | RTYPEW (rs2,rs1,rd,op) => T + | MUL (rs2,rs1,rd,high,signed1,signed2) => T + | DIV0 (rs2,rs1,rd,s) => T + | REM (rs2,rs1,rd,s) => T + | MULW (rs2,rs1,rd) => T + | DIVW (rs2,rs1,rd,s) => T + | REMW (rs2,rs1,rd,s) => T + | FENCE (pred,succ) => T + | FENCEI (() ) => T + | ECALL (() ) => T + | MRET (() ) => T + | SRET (() ) => T + | EBREAK (() ) => T + | WFI (() ) => T + | SFENCE_VMA (rs1,rs2) => T + | LOADRES (aq,rl,rs1,size1,rd) => T + | STORECON (aq,rl,rs2,rs1,size1,rd) => T + | AMO (op,aq,rl,rs2,rs1,width,rd) => T + | CSR (csr,rs1,rd,T,op) => T + | CSR (csr,rs1,rd,F,op) => T + | ILLEGAL (s) => T + | _ => F + )))`; + + +(*val assembly_backwards_matches : string -> bool*) + +val _ = Define ` + ((assembly_backwards_matches:string -> bool) arg_= + (let stringappend_541_0 = arg_ in + if ((case ((utype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_542_0,stringappend_543_0) => + let stringappend_544_0 = (string_drop stringappend_541_0 stringappend_543_0) in + if ((case ((spc_matches_prefix stringappend_544_0)) of + SOME (stringappend_545_0,stringappend_546_0) => + let stringappend_547_0 = (string_drop stringappend_544_0 stringappend_546_0) in + if ((case ((reg_name_matches_prefix stringappend_547_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_548_0,stringappend_549_0) => + let stringappend_550_0 = (string_drop stringappend_547_0 stringappend_549_0) in + if ((case ((sep_matches_prefix stringappend_550_0)) of + SOME (stringappend_551_0,stringappend_552_0) => + let stringappend_553_0 = (string_drop stringappend_550_0 stringappend_552_0) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_553_0 + : (( 20 words$word # ii))option)) of + SOME (stringappend_554_0,stringappend_555_0) => + (case ((string_drop stringappend_553_0 stringappend_555_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_543_0) = + ((case ((utype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_542_0,stringappend_543_0) => (stringappend_542_0, stringappend_543_0) + )) in + let stringappend_544_0 = (string_drop stringappend_541_0 stringappend_543_0) in + (case + (case ((spc_matches_prefix stringappend_544_0)) of + SOME (stringappend_545_0,stringappend_546_0) => (stringappend_545_0, stringappend_546_0) + ) of + (() , stringappend_546_0) => + let stringappend_547_0 = (string_drop stringappend_544_0 stringappend_546_0) in + let (rd, stringappend_549_0) = + ((case ((reg_name_matches_prefix stringappend_547_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_548_0,stringappend_549_0) => (stringappend_548_0, stringappend_549_0) + )) in + let stringappend_550_0 = (string_drop stringappend_547_0 stringappend_549_0) in + (case + (case ((sep_matches_prefix stringappend_550_0)) of + SOME (stringappend_551_0,stringappend_552_0) => (stringappend_551_0, stringappend_552_0) + ) of + (() , stringappend_552_0) => + let stringappend_553_0 = (string_drop stringappend_550_0 stringappend_552_0) in + let (imm, stringappend_555_0) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_553_0 : (( 20 words$word # ii)) option)) of + SOME (stringappend_554_0,stringappend_555_0) => (stringappend_554_0, stringappend_555_0) + )) in + (case ((string_drop stringappend_553_0 stringappend_555_0)) of "" => T ) + ) + ) + else if (((((string_startswith stringappend_541_0 "jal")) /\ (let stringappend_557_0 = (string_drop stringappend_541_0 ((string_length "jal"))) in + if ((case ((spc_matches_prefix stringappend_557_0)) of + SOME (stringappend_558_0,stringappend_559_0) => + let stringappend_560_0 = (string_drop stringappend_557_0 stringappend_559_0) in + if ((case ((reg_name_matches_prefix stringappend_560_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_561_0,stringappend_562_0) => + let stringappend_563_0 = (string_drop stringappend_560_0 stringappend_562_0) in + if ((case ((sep_matches_prefix stringappend_563_0)) of + SOME (stringappend_564_0,stringappend_565_0) => + let stringappend_566_0 = + (string_drop stringappend_563_0 stringappend_565_0) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_566_0 + : (( 21 words$word # ii))option)) of + SOME (stringappend_567_0,stringappend_568_0) => + (case ((string_drop stringappend_566_0 stringappend_568_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_557_0 = (string_drop stringappend_541_0 ((string_length "jal"))) in + (case + (case ((spc_matches_prefix stringappend_557_0)) of + SOME (stringappend_558_0,stringappend_559_0) => (stringappend_558_0, stringappend_559_0) + ) of + (() , stringappend_559_0) => + let stringappend_560_0 = (string_drop stringappend_557_0 stringappend_559_0) in + let (rd, stringappend_562_0) = + ((case ((reg_name_matches_prefix stringappend_560_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_561_0,stringappend_562_0) => (stringappend_561_0, stringappend_562_0) + )) in + let stringappend_563_0 = (string_drop stringappend_560_0 stringappend_562_0) in + (case + (case ((sep_matches_prefix stringappend_563_0)) of + SOME (stringappend_564_0,stringappend_565_0) => (stringappend_564_0, stringappend_565_0) + ) of + (() , stringappend_565_0) => + let stringappend_566_0 = (string_drop stringappend_563_0 stringappend_565_0) in + let (imm, stringappend_568_0) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_566_0 : (( 21 words$word # ii)) option)) of + SOME (stringappend_567_0,stringappend_568_0) => (stringappend_567_0, stringappend_568_0) + )) in + (case ((string_drop stringappend_566_0 stringappend_568_0)) of "" => T ) + ) + ) + else if (((((string_startswith stringappend_541_0 "jalr")) /\ (let stringappend_570_0 = (string_drop stringappend_541_0 ((string_length "jalr"))) in + if ((case ((spc_matches_prefix stringappend_570_0)) of + SOME (stringappend_571_0,stringappend_572_0) => + let stringappend_573_0 = (string_drop stringappend_570_0 stringappend_572_0) in + if ((case ((reg_name_matches_prefix stringappend_573_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_574_0,stringappend_575_0) => + let stringappend_576_0 = (string_drop stringappend_573_0 stringappend_575_0) in + if ((case ((sep_matches_prefix stringappend_576_0)) of + SOME (stringappend_577_0,stringappend_578_0) => + let stringappend_579_0 = + (string_drop stringappend_576_0 stringappend_578_0) in + if ((case ((reg_name_matches_prefix stringappend_579_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_580_0,stringappend_581_0) => + let stringappend_582_0 = + (string_drop stringappend_579_0 stringappend_581_0) in + if ((case ((sep_matches_prefix stringappend_582_0)) of + SOME (stringappend_583_0,stringappend_584_0) => + let stringappend_585_0 = + (string_drop stringappend_582_0 stringappend_584_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_585_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_586_0,stringappend_587_0) => + (case ((string_drop stringappend_585_0 + stringappend_587_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_570_0 = (string_drop stringappend_541_0 ((string_length "jalr"))) in + (case + (case ((spc_matches_prefix stringappend_570_0)) of + SOME (stringappend_571_0,stringappend_572_0) => (stringappend_571_0, stringappend_572_0) + ) of + (() , stringappend_572_0) => + let stringappend_573_0 = (string_drop stringappend_570_0 stringappend_572_0) in + let (rd, stringappend_575_0) = + ((case ((reg_name_matches_prefix stringappend_573_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_574_0,stringappend_575_0) => (stringappend_574_0, stringappend_575_0) + )) in + let stringappend_576_0 = (string_drop stringappend_573_0 stringappend_575_0) in + (case + (case ((sep_matches_prefix stringappend_576_0)) of + SOME (stringappend_577_0,stringappend_578_0) => (stringappend_577_0, stringappend_578_0) + ) of + (() , stringappend_578_0) => + let stringappend_579_0 = (string_drop stringappend_576_0 stringappend_578_0) in + let (rs1, stringappend_581_0) = + ((case ((reg_name_matches_prefix stringappend_579_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_580_0,stringappend_581_0) => (stringappend_580_0, stringappend_581_0) + )) in + let stringappend_582_0 = (string_drop stringappend_579_0 stringappend_581_0) in + (case + (case ((sep_matches_prefix stringappend_582_0)) of + SOME (stringappend_583_0,stringappend_584_0) => (stringappend_583_0, stringappend_584_0) + ) of + (() , stringappend_584_0) => + let stringappend_585_0 = (string_drop stringappend_582_0 stringappend_584_0) in + let (imm, stringappend_587_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_585_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_586_0,stringappend_587_0) => (stringappend_586_0, stringappend_587_0) + )) in + (case ((string_drop stringappend_585_0 stringappend_587_0)) of "" => T ) + ) + ) + ) + else if ((case ((btype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_589_0,stringappend_590_0) => + let stringappend_591_0 = (string_drop stringappend_541_0 stringappend_590_0) in + if ((case ((spc_matches_prefix stringappend_591_0)) of + SOME (stringappend_592_0,stringappend_593_0) => + let stringappend_594_0 = (string_drop stringappend_591_0 stringappend_593_0) in + if ((case ((reg_name_matches_prefix stringappend_594_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_595_0,stringappend_596_0) => + let stringappend_597_0 = (string_drop stringappend_594_0 stringappend_596_0) in + if ((case ((sep_matches_prefix stringappend_597_0)) of + SOME (stringappend_598_0,stringappend_599_0) => + let stringappend_600_0 = (string_drop stringappend_597_0 stringappend_599_0) in + if ((case ((reg_name_matches_prefix stringappend_600_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_601_0,stringappend_602_0) => + let stringappend_603_0 = + (string_drop stringappend_600_0 stringappend_602_0) in + if ((case ((sep_matches_prefix stringappend_603_0)) of + SOME (stringappend_604_0,stringappend_605_0) => + let stringappend_606_0 = + (string_drop stringappend_603_0 stringappend_605_0) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_606_0 + : (( 13 words$word # ii))option)) of + SOME (stringappend_607_0,stringappend_608_0) => + (case ((string_drop stringappend_606_0 stringappend_608_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_590_0) = + ((case ((btype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_589_0,stringappend_590_0) => (stringappend_589_0, stringappend_590_0) + )) in + let stringappend_591_0 = (string_drop stringappend_541_0 stringappend_590_0) in + (case + (case ((spc_matches_prefix stringappend_591_0)) of + SOME (stringappend_592_0,stringappend_593_0) => (stringappend_592_0, stringappend_593_0) + ) of + (() , stringappend_593_0) => + let stringappend_594_0 = (string_drop stringappend_591_0 stringappend_593_0) in + let (rs1, stringappend_596_0) = + ((case ((reg_name_matches_prefix stringappend_594_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_595_0,stringappend_596_0) => (stringappend_595_0, stringappend_596_0) + )) in + let stringappend_597_0 = (string_drop stringappend_594_0 stringappend_596_0) in + (case + (case ((sep_matches_prefix stringappend_597_0)) of + SOME (stringappend_598_0,stringappend_599_0) => (stringappend_598_0, stringappend_599_0) + ) of + (() , stringappend_599_0) => + let stringappend_600_0 = (string_drop stringappend_597_0 stringappend_599_0) in + let (rs2, stringappend_602_0) = + ((case ((reg_name_matches_prefix stringappend_600_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_601_0,stringappend_602_0) => (stringappend_601_0, stringappend_602_0) + )) in + let stringappend_603_0 = (string_drop stringappend_600_0 stringappend_602_0) in + (case + (case ((sep_matches_prefix stringappend_603_0)) of + SOME (stringappend_604_0,stringappend_605_0) => (stringappend_604_0, stringappend_605_0) + ) of + (() , stringappend_605_0) => + let stringappend_606_0 = (string_drop stringappend_603_0 stringappend_605_0) in + let (imm, stringappend_608_0) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_606_0 : (( 13 words$word # ii)) option)) of + SOME (stringappend_607_0,stringappend_608_0) => (stringappend_607_0, stringappend_608_0) + )) in + (case ((string_drop stringappend_606_0 stringappend_608_0)) of "" => T ) + ) + ) + ) + else if ((case ((itype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_610_0,stringappend_611_0) => + let stringappend_612_0 = (string_drop stringappend_541_0 stringappend_611_0) in + if ((case ((spc_matches_prefix stringappend_612_0)) of + SOME (stringappend_613_0,stringappend_614_0) => + let stringappend_615_0 = (string_drop stringappend_612_0 stringappend_614_0) in + if ((case ((reg_name_matches_prefix stringappend_615_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_616_0,stringappend_617_0) => + let stringappend_618_0 = (string_drop stringappend_615_0 stringappend_617_0) in + if ((case ((sep_matches_prefix stringappend_618_0)) of + SOME (stringappend_619_0,stringappend_620_0) => + let stringappend_621_0 = (string_drop stringappend_618_0 stringappend_620_0) in + if ((case ((reg_name_matches_prefix stringappend_621_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_622_0,stringappend_623_0) => + let stringappend_624_0 = + (string_drop stringappend_621_0 stringappend_623_0) in + if ((case ((sep_matches_prefix stringappend_624_0)) of + SOME (stringappend_625_0,stringappend_626_0) => + let stringappend_627_0 = + (string_drop stringappend_624_0 stringappend_626_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_627_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_628_0,stringappend_629_0) => + (case ((string_drop stringappend_627_0 stringappend_629_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_611_0) = + ((case ((itype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_610_0,stringappend_611_0) => (stringappend_610_0, stringappend_611_0) + )) in + let stringappend_612_0 = (string_drop stringappend_541_0 stringappend_611_0) in + (case + (case ((spc_matches_prefix stringappend_612_0)) of + SOME (stringappend_613_0,stringappend_614_0) => (stringappend_613_0, stringappend_614_0) + ) of + (() , stringappend_614_0) => + let stringappend_615_0 = (string_drop stringappend_612_0 stringappend_614_0) in + let (rd, stringappend_617_0) = + ((case ((reg_name_matches_prefix stringappend_615_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_616_0,stringappend_617_0) => (stringappend_616_0, stringappend_617_0) + )) in + let stringappend_618_0 = (string_drop stringappend_615_0 stringappend_617_0) in + (case + (case ((sep_matches_prefix stringappend_618_0)) of + SOME (stringappend_619_0,stringappend_620_0) => (stringappend_619_0, stringappend_620_0) + ) of + (() , stringappend_620_0) => + let stringappend_621_0 = (string_drop stringappend_618_0 stringappend_620_0) in + let (rs1, stringappend_623_0) = + ((case ((reg_name_matches_prefix stringappend_621_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_622_0,stringappend_623_0) => (stringappend_622_0, stringappend_623_0) + )) in + let stringappend_624_0 = (string_drop stringappend_621_0 stringappend_623_0) in + (case + (case ((sep_matches_prefix stringappend_624_0)) of + SOME (stringappend_625_0,stringappend_626_0) => (stringappend_625_0, stringappend_626_0) + ) of + (() , stringappend_626_0) => + let stringappend_627_0 = (string_drop stringappend_624_0 stringappend_626_0) in + let (imm, stringappend_629_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_627_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_628_0,stringappend_629_0) => (stringappend_628_0, stringappend_629_0) + )) in + (case ((string_drop stringappend_627_0 stringappend_629_0)) of "" => T ) + ) + ) + ) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_631_0,stringappend_632_0) => + let stringappend_633_0 = (string_drop stringappend_541_0 stringappend_632_0) in + if ((case ((spc_matches_prefix stringappend_633_0)) of + SOME (stringappend_634_0,stringappend_635_0) => + let stringappend_636_0 = (string_drop stringappend_633_0 stringappend_635_0) in + if ((case ((reg_name_matches_prefix stringappend_636_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_637_0,stringappend_638_0) => + let stringappend_639_0 = (string_drop stringappend_636_0 stringappend_638_0) in + if ((case ((sep_matches_prefix stringappend_639_0)) of + SOME (stringappend_640_0,stringappend_641_0) => + let stringappend_642_0 = (string_drop stringappend_639_0 stringappend_641_0) in + if ((case ((reg_name_matches_prefix stringappend_642_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_643_0,stringappend_644_0) => + let stringappend_645_0 = + (string_drop stringappend_642_0 stringappend_644_0) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_645_0 + : (( 6 words$word # ii))option)) of + SOME (stringappend_646_0,stringappend_647_0) => + (case ((string_drop stringappend_645_0 stringappend_647_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_632_0) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_631_0,stringappend_632_0) => (stringappend_631_0, stringappend_632_0) + )) in + let stringappend_633_0 = (string_drop stringappend_541_0 stringappend_632_0) in + (case + (case ((spc_matches_prefix stringappend_633_0)) of + SOME (stringappend_634_0,stringappend_635_0) => (stringappend_634_0, stringappend_635_0) + ) of + (() , stringappend_635_0) => + let stringappend_636_0 = (string_drop stringappend_633_0 stringappend_635_0) in + let (rd, stringappend_638_0) = + ((case ((reg_name_matches_prefix stringappend_636_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_637_0,stringappend_638_0) => (stringappend_637_0, stringappend_638_0) + )) in + let stringappend_639_0 = (string_drop stringappend_636_0 stringappend_638_0) in + (case + (case ((sep_matches_prefix stringappend_639_0)) of + SOME (stringappend_640_0,stringappend_641_0) => (stringappend_640_0, stringappend_641_0) + ) of + (() , stringappend_641_0) => + let stringappend_642_0 = (string_drop stringappend_639_0 stringappend_641_0) in + let (rs1, stringappend_644_0) = + ((case ((reg_name_matches_prefix stringappend_642_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_643_0,stringappend_644_0) => (stringappend_643_0, stringappend_644_0) + )) in + let stringappend_645_0 = (string_drop stringappend_642_0 stringappend_644_0) in + let (shamt, stringappend_647_0) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_645_0 : (( 6 words$word # ii)) option)) of + SOME (stringappend_646_0,stringappend_647_0) => (stringappend_646_0, stringappend_647_0) + )) in + (case ((string_drop stringappend_645_0 stringappend_647_0)) of "" => T ) + ) + ) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_649_0,stringappend_650_0) => + let stringappend_651_0 = (string_drop stringappend_541_0 stringappend_650_0) in + if ((case ((spc_matches_prefix stringappend_651_0)) of + SOME (stringappend_652_0,stringappend_653_0) => + let stringappend_654_0 = (string_drop stringappend_651_0 stringappend_653_0) in + if ((case ((reg_name_matches_prefix stringappend_654_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_655_0,stringappend_656_0) => + let stringappend_657_0 = (string_drop stringappend_654_0 stringappend_656_0) in + if ((case ((sep_matches_prefix stringappend_657_0)) of + SOME (stringappend_658_0,stringappend_659_0) => + let stringappend_660_0 = (string_drop stringappend_657_0 stringappend_659_0) in + if ((case ((reg_name_matches_prefix stringappend_660_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_661_0,stringappend_662_0) => + let stringappend_663_0 = + (string_drop stringappend_660_0 stringappend_662_0) in + if ((case ((sep_matches_prefix stringappend_663_0)) of + SOME (stringappend_664_0,stringappend_665_0) => + let stringappend_666_0 = + (string_drop stringappend_663_0 stringappend_665_0) in + if ((case ((reg_name_matches_prefix stringappend_666_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_667_0,stringappend_668_0) => + (case ((string_drop stringappend_666_0 stringappend_668_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_650_0) = + ((case ((rtype_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_649_0,stringappend_650_0) => (stringappend_649_0, stringappend_650_0) + )) in + let stringappend_651_0 = (string_drop stringappend_541_0 stringappend_650_0) in + (case + (case ((spc_matches_prefix stringappend_651_0)) of + SOME (stringappend_652_0,stringappend_653_0) => (stringappend_652_0, stringappend_653_0) + ) of + (() , stringappend_653_0) => + let stringappend_654_0 = (string_drop stringappend_651_0 stringappend_653_0) in + let (rd, stringappend_656_0) = + ((case ((reg_name_matches_prefix stringappend_654_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_655_0,stringappend_656_0) => (stringappend_655_0, stringappend_656_0) + )) in + let stringappend_657_0 = (string_drop stringappend_654_0 stringappend_656_0) in + (case + (case ((sep_matches_prefix stringappend_657_0)) of + SOME (stringappend_658_0,stringappend_659_0) => (stringappend_658_0, stringappend_659_0) + ) of + (() , stringappend_659_0) => + let stringappend_660_0 = (string_drop stringappend_657_0 stringappend_659_0) in + let (rs1, stringappend_662_0) = + ((case ((reg_name_matches_prefix stringappend_660_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_661_0,stringappend_662_0) => (stringappend_661_0, stringappend_662_0) + )) in + let stringappend_663_0 = (string_drop stringappend_660_0 stringappend_662_0) in + (case + (case ((sep_matches_prefix stringappend_663_0)) of + SOME (stringappend_664_0,stringappend_665_0) => (stringappend_664_0, stringappend_665_0) + ) of + (() , stringappend_665_0) => + let stringappend_666_0 = (string_drop stringappend_663_0 stringappend_665_0) in + let (rs2, stringappend_668_0) = + ((case ((reg_name_matches_prefix stringappend_666_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_667_0,stringappend_668_0) => (stringappend_667_0, stringappend_668_0) + )) in + (case ((string_drop stringappend_666_0 stringappend_668_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "l")) /\ (let stringappend_670_0 = (string_drop stringappend_541_0 ((string_length "l"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_670_0)) of + SOME (stringappend_671_0,stringappend_672_0) => + let stringappend_673_0 = (string_drop stringappend_670_0 stringappend_672_0) in + if ((case ((maybe_u_matches_prefix stringappend_673_0)) of + SOME (stringappend_674_0,stringappend_675_0) => + let stringappend_676_0 = (string_drop stringappend_673_0 stringappend_675_0) in + if ((case ((maybe_aq_matches_prefix stringappend_676_0)) of + SOME (stringappend_677_0,stringappend_678_0) => + let stringappend_679_0 = + (string_drop stringappend_676_0 stringappend_678_0) in + if ((case ((maybe_rl_matches_prefix stringappend_679_0)) of + SOME (stringappend_680_0,stringappend_681_0) => + let stringappend_682_0 = + (string_drop stringappend_679_0 stringappend_681_0) in + if ((case ((spc_matches_prefix stringappend_682_0)) of + SOME (stringappend_683_0,stringappend_684_0) => + let stringappend_685_0 = + (string_drop stringappend_682_0 stringappend_684_0) in + if ((case ((reg_name_matches_prefix stringappend_685_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_686_0,stringappend_687_0) => + let stringappend_688_0 = + (string_drop stringappend_685_0 stringappend_687_0) in + if ((case ((sep_matches_prefix stringappend_688_0)) of + SOME (stringappend_689_0,stringappend_690_0) => + let stringappend_691_0 = + (string_drop stringappend_688_0 + stringappend_690_0) in + if ((case ((reg_name_matches_prefix + stringappend_691_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_692_0,stringappend_693_0) => + let stringappend_694_0 = + (string_drop stringappend_691_0 + stringappend_693_0) in + if ((case ((sep_matches_prefix + stringappend_694_0)) of + SOME + (stringappend_695_0,stringappend_696_0) => + let stringappend_697_0 = + (string_drop stringappend_694_0 + stringappend_696_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_697_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_698_0,stringappend_699_0) => + (case ((string_drop + stringappend_697_0 + stringappend_699_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_670_0 = (string_drop stringappend_541_0 ((string_length "l"))) in + let (size1, stringappend_672_0) = + ((case ((size_mnemonic_matches_prefix stringappend_670_0)) of + SOME (stringappend_671_0,stringappend_672_0) => (stringappend_671_0, stringappend_672_0) + )) in + let stringappend_673_0 = (string_drop stringappend_670_0 stringappend_672_0) in + let (is_unsigned, stringappend_675_0) = + ((case ((maybe_u_matches_prefix stringappend_673_0)) of + SOME (stringappend_674_0,stringappend_675_0) => (stringappend_674_0, stringappend_675_0) + )) in + let stringappend_676_0 = (string_drop stringappend_673_0 stringappend_675_0) in + let (aq, stringappend_678_0) = + ((case ((maybe_aq_matches_prefix stringappend_676_0)) of + SOME (stringappend_677_0,stringappend_678_0) => (stringappend_677_0, stringappend_678_0) + )) in + let stringappend_679_0 = (string_drop stringappend_676_0 stringappend_678_0) in + let (rl, stringappend_681_0) = + ((case ((maybe_rl_matches_prefix stringappend_679_0)) of + SOME (stringappend_680_0,stringappend_681_0) => (stringappend_680_0, stringappend_681_0) + )) in + let stringappend_682_0 = (string_drop stringappend_679_0 stringappend_681_0) in + (case + (case ((spc_matches_prefix stringappend_682_0)) of + SOME (stringappend_683_0,stringappend_684_0) => (stringappend_683_0, stringappend_684_0) + ) of + (() , stringappend_684_0) => + let stringappend_685_0 = (string_drop stringappend_682_0 stringappend_684_0) in + let (rd, stringappend_687_0) = + ((case ((reg_name_matches_prefix stringappend_685_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_686_0,stringappend_687_0) => (stringappend_686_0, stringappend_687_0) + )) in + let stringappend_688_0 = (string_drop stringappend_685_0 stringappend_687_0) in + (case + (case ((sep_matches_prefix stringappend_688_0)) of + SOME (stringappend_689_0,stringappend_690_0) => (stringappend_689_0, stringappend_690_0) + ) of + (() , stringappend_690_0) => + let stringappend_691_0 = (string_drop stringappend_688_0 stringappend_690_0) in + let (rs1, stringappend_693_0) = + ((case ((reg_name_matches_prefix stringappend_691_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_692_0,stringappend_693_0) => (stringappend_692_0, stringappend_693_0) + )) in + let stringappend_694_0 = (string_drop stringappend_691_0 stringappend_693_0) in + (case + (case ((sep_matches_prefix stringappend_694_0)) of + SOME (stringappend_695_0,stringappend_696_0) => (stringappend_695_0, stringappend_696_0) + ) of + (() , stringappend_696_0) => + let stringappend_697_0 = (string_drop stringappend_694_0 stringappend_696_0) in + let (imm, stringappend_699_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_697_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_698_0,stringappend_699_0) => (stringappend_698_0, stringappend_699_0) + )) in + (case ((string_drop stringappend_697_0 stringappend_699_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "s")) /\ (let stringappend_701_0 = (string_drop stringappend_541_0 ((string_length "s"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_701_0)) of + SOME (stringappend_702_0,stringappend_703_0) => + let stringappend_704_0 = (string_drop stringappend_701_0 stringappend_703_0) in + if ((case ((maybe_aq_matches_prefix stringappend_704_0)) of + SOME (stringappend_705_0,stringappend_706_0) => + let stringappend_707_0 = (string_drop stringappend_704_0 stringappend_706_0) in + if ((case ((maybe_rl_matches_prefix stringappend_707_0)) of + SOME (stringappend_708_0,stringappend_709_0) => + let stringappend_710_0 = + (string_drop stringappend_707_0 stringappend_709_0) in + if ((case ((spc_matches_prefix stringappend_710_0)) of + SOME (stringappend_711_0,stringappend_712_0) => + let stringappend_713_0 = + (string_drop stringappend_710_0 stringappend_712_0) in + if ((case ((reg_name_matches_prefix stringappend_713_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_714_0,stringappend_715_0) => + let stringappend_716_0 = + (string_drop stringappend_713_0 stringappend_715_0) in + if ((case ((sep_matches_prefix stringappend_716_0)) of + SOME (stringappend_717_0,stringappend_718_0) => + let stringappend_719_0 = + (string_drop stringappend_716_0 stringappend_718_0) in + if ((case ((reg_name_matches_prefix stringappend_719_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_720_0,stringappend_721_0) => + let stringappend_722_0 = + (string_drop stringappend_719_0 + stringappend_721_0) in + if ((case ((sep_matches_prefix stringappend_722_0)) of + SOME (stringappend_723_0,stringappend_724_0) => + let stringappend_725_0 = + (string_drop stringappend_722_0 + stringappend_724_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_725_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_726_0,stringappend_727_0) => + (case ((string_drop stringappend_725_0 + stringappend_727_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_701_0 = (string_drop stringappend_541_0 ((string_length "s"))) in + let (size1, stringappend_703_0) = + ((case ((size_mnemonic_matches_prefix stringappend_701_0)) of + SOME (stringappend_702_0,stringappend_703_0) => (stringappend_702_0, stringappend_703_0) + )) in + let stringappend_704_0 = (string_drop stringappend_701_0 stringappend_703_0) in + let (aq, stringappend_706_0) = + ((case ((maybe_aq_matches_prefix stringappend_704_0)) of + SOME (stringappend_705_0,stringappend_706_0) => (stringappend_705_0, stringappend_706_0) + )) in + let stringappend_707_0 = (string_drop stringappend_704_0 stringappend_706_0) in + let (rl, stringappend_709_0) = + ((case ((maybe_rl_matches_prefix stringappend_707_0)) of + SOME (stringappend_708_0,stringappend_709_0) => (stringappend_708_0, stringappend_709_0) + )) in + let stringappend_710_0 = (string_drop stringappend_707_0 stringappend_709_0) in + (case + (case ((spc_matches_prefix stringappend_710_0)) of + SOME (stringappend_711_0,stringappend_712_0) => (stringappend_711_0, stringappend_712_0) + ) of + (() , stringappend_712_0) => + let stringappend_713_0 = (string_drop stringappend_710_0 stringappend_712_0) in + let (rd, stringappend_715_0) = + ((case ((reg_name_matches_prefix stringappend_713_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_714_0,stringappend_715_0) => (stringappend_714_0, stringappend_715_0) + )) in + let stringappend_716_0 = (string_drop stringappend_713_0 stringappend_715_0) in + (case + (case ((sep_matches_prefix stringappend_716_0)) of + SOME (stringappend_717_0,stringappend_718_0) => (stringappend_717_0, stringappend_718_0) + ) of + (() , stringappend_718_0) => + let stringappend_719_0 = (string_drop stringappend_716_0 stringappend_718_0) in + let (rs1, stringappend_721_0) = + ((case ((reg_name_matches_prefix stringappend_719_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_720_0,stringappend_721_0) => (stringappend_720_0, stringappend_721_0) + )) in + let stringappend_722_0 = (string_drop stringappend_719_0 stringappend_721_0) in + (case + (case ((sep_matches_prefix stringappend_722_0)) of + SOME (stringappend_723_0,stringappend_724_0) => (stringappend_723_0, stringappend_724_0) + ) of + (() , stringappend_724_0) => + let stringappend_725_0 = (string_drop stringappend_722_0 stringappend_724_0) in + let (imm, stringappend_727_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_725_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_726_0,stringappend_727_0) => (stringappend_726_0, stringappend_727_0) + )) in + (case ((string_drop stringappend_725_0 stringappend_727_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "addiw")) /\ (let stringappend_729_0 = (string_drop stringappend_541_0 ((string_length "addiw"))) in + if ((case ((spc_matches_prefix stringappend_729_0)) of + SOME (stringappend_730_0,stringappend_731_0) => + let stringappend_732_0 = (string_drop stringappend_729_0 stringappend_731_0) in + if ((case ((reg_name_matches_prefix stringappend_732_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_733_0,stringappend_734_0) => + let stringappend_735_0 = (string_drop stringappend_732_0 stringappend_734_0) in + if ((case ((sep_matches_prefix stringappend_735_0)) of + SOME (stringappend_736_0,stringappend_737_0) => + let stringappend_738_0 = + (string_drop stringappend_735_0 stringappend_737_0) in + if ((case ((reg_name_matches_prefix stringappend_738_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_739_0,stringappend_740_0) => + let stringappend_741_0 = + (string_drop stringappend_738_0 stringappend_740_0) in + if ((case ((sep_matches_prefix stringappend_741_0)) of + SOME (stringappend_742_0,stringappend_743_0) => + let stringappend_744_0 = + (string_drop stringappend_741_0 stringappend_743_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_744_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_745_0,stringappend_746_0) => + (case ((string_drop stringappend_744_0 + stringappend_746_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_729_0 = (string_drop stringappend_541_0 ((string_length "addiw"))) in + (case + (case ((spc_matches_prefix stringappend_729_0)) of + SOME (stringappend_730_0,stringappend_731_0) => (stringappend_730_0, stringappend_731_0) + ) of + (() , stringappend_731_0) => + let stringappend_732_0 = (string_drop stringappend_729_0 stringappend_731_0) in + let (rd, stringappend_734_0) = + ((case ((reg_name_matches_prefix stringappend_732_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_733_0,stringappend_734_0) => (stringappend_733_0, stringappend_734_0) + )) in + let stringappend_735_0 = (string_drop stringappend_732_0 stringappend_734_0) in + (case + (case ((sep_matches_prefix stringappend_735_0)) of + SOME (stringappend_736_0,stringappend_737_0) => (stringappend_736_0, stringappend_737_0) + ) of + (() , stringappend_737_0) => + let stringappend_738_0 = (string_drop stringappend_735_0 stringappend_737_0) in + let (rs1, stringappend_740_0) = + ((case ((reg_name_matches_prefix stringappend_738_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_739_0,stringappend_740_0) => (stringappend_739_0, stringappend_740_0) + )) in + let stringappend_741_0 = (string_drop stringappend_738_0 stringappend_740_0) in + (case + (case ((sep_matches_prefix stringappend_741_0)) of + SOME (stringappend_742_0,stringappend_743_0) => (stringappend_742_0, stringappend_743_0) + ) of + (() , stringappend_743_0) => + let stringappend_744_0 = (string_drop stringappend_741_0 stringappend_743_0) in + let (imm, stringappend_746_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_744_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_745_0,stringappend_746_0) => (stringappend_745_0, stringappend_746_0) + )) in + (case ((string_drop stringappend_744_0 stringappend_746_0)) of "" => T ) + ) + ) + ) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_748_0,stringappend_749_0) => + let stringappend_750_0 = (string_drop stringappend_541_0 stringappend_749_0) in + if ((case ((spc_matches_prefix stringappend_750_0)) of + SOME (stringappend_751_0,stringappend_752_0) => + let stringappend_753_0 = (string_drop stringappend_750_0 stringappend_752_0) in + if ((case ((reg_name_matches_prefix stringappend_753_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_754_0,stringappend_755_0) => + let stringappend_756_0 = (string_drop stringappend_753_0 stringappend_755_0) in + if ((case ((sep_matches_prefix stringappend_756_0)) of + SOME (stringappend_757_0,stringappend_758_0) => + let stringappend_759_0 = (string_drop stringappend_756_0 stringappend_758_0) in + if ((case ((reg_name_matches_prefix stringappend_759_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_760_0,stringappend_761_0) => + let stringappend_762_0 = + (string_drop stringappend_759_0 stringappend_761_0) in + if ((case ((sep_matches_prefix stringappend_762_0)) of + SOME (stringappend_763_0,stringappend_764_0) => + let stringappend_765_0 = + (string_drop stringappend_762_0 stringappend_764_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_765_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_766_0,stringappend_767_0) => + (case ((string_drop stringappend_765_0 stringappend_767_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_749_0) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_748_0,stringappend_749_0) => (stringappend_748_0, stringappend_749_0) + )) in + let stringappend_750_0 = (string_drop stringappend_541_0 stringappend_749_0) in + (case + (case ((spc_matches_prefix stringappend_750_0)) of + SOME (stringappend_751_0,stringappend_752_0) => (stringappend_751_0, stringappend_752_0) + ) of + (() , stringappend_752_0) => + let stringappend_753_0 = (string_drop stringappend_750_0 stringappend_752_0) in + let (rd, stringappend_755_0) = + ((case ((reg_name_matches_prefix stringappend_753_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_754_0,stringappend_755_0) => (stringappend_754_0, stringappend_755_0) + )) in + let stringappend_756_0 = (string_drop stringappend_753_0 stringappend_755_0) in + (case + (case ((sep_matches_prefix stringappend_756_0)) of + SOME (stringappend_757_0,stringappend_758_0) => (stringappend_757_0, stringappend_758_0) + ) of + (() , stringappend_758_0) => + let stringappend_759_0 = (string_drop stringappend_756_0 stringappend_758_0) in + let (rs1, stringappend_761_0) = + ((case ((reg_name_matches_prefix stringappend_759_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_760_0,stringappend_761_0) => (stringappend_760_0, stringappend_761_0) + )) in + let stringappend_762_0 = (string_drop stringappend_759_0 stringappend_761_0) in + (case + (case ((sep_matches_prefix stringappend_762_0)) of + SOME (stringappend_763_0,stringappend_764_0) => (stringappend_763_0, stringappend_764_0) + ) of + (() , stringappend_764_0) => + let stringappend_765_0 = (string_drop stringappend_762_0 stringappend_764_0) in + let (shamt, stringappend_767_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_765_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_766_0,stringappend_767_0) => (stringappend_766_0, stringappend_767_0) + )) in + (case ((string_drop stringappend_765_0 stringappend_767_0)) of "" => T ) + ) + ) + ) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_769_0,stringappend_770_0) => + let stringappend_771_0 = (string_drop stringappend_541_0 stringappend_770_0) in + if ((case ((spc_matches_prefix stringappend_771_0)) of + SOME (stringappend_772_0,stringappend_773_0) => + let stringappend_774_0 = (string_drop stringappend_771_0 stringappend_773_0) in + if ((case ((reg_name_matches_prefix stringappend_774_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_775_0,stringappend_776_0) => + let stringappend_777_0 = (string_drop stringappend_774_0 stringappend_776_0) in + if ((case ((sep_matches_prefix stringappend_777_0)) of + SOME (stringappend_778_0,stringappend_779_0) => + let stringappend_780_0 = (string_drop stringappend_777_0 stringappend_779_0) in + if ((case ((reg_name_matches_prefix stringappend_780_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_781_0,stringappend_782_0) => + let stringappend_783_0 = + (string_drop stringappend_780_0 stringappend_782_0) in + if ((case ((sep_matches_prefix stringappend_783_0)) of + SOME (stringappend_784_0,stringappend_785_0) => + let stringappend_786_0 = + (string_drop stringappend_783_0 stringappend_785_0) in + if ((case ((reg_name_matches_prefix stringappend_786_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_787_0,stringappend_788_0) => + (case ((string_drop stringappend_786_0 stringappend_788_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_770_0) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_769_0,stringappend_770_0) => (stringappend_769_0, stringappend_770_0) + )) in + let stringappend_771_0 = (string_drop stringappend_541_0 stringappend_770_0) in + (case + (case ((spc_matches_prefix stringappend_771_0)) of + SOME (stringappend_772_0,stringappend_773_0) => (stringappend_772_0, stringappend_773_0) + ) of + (() , stringappend_773_0) => + let stringappend_774_0 = (string_drop stringappend_771_0 stringappend_773_0) in + let (rd, stringappend_776_0) = + ((case ((reg_name_matches_prefix stringappend_774_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_775_0,stringappend_776_0) => (stringappend_775_0, stringappend_776_0) + )) in + let stringappend_777_0 = (string_drop stringappend_774_0 stringappend_776_0) in + (case + (case ((sep_matches_prefix stringappend_777_0)) of + SOME (stringappend_778_0,stringappend_779_0) => (stringappend_778_0, stringappend_779_0) + ) of + (() , stringappend_779_0) => + let stringappend_780_0 = (string_drop stringappend_777_0 stringappend_779_0) in + let (rs1, stringappend_782_0) = + ((case ((reg_name_matches_prefix stringappend_780_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_781_0,stringappend_782_0) => (stringappend_781_0, stringappend_782_0) + )) in + let stringappend_783_0 = (string_drop stringappend_780_0 stringappend_782_0) in + (case + (case ((sep_matches_prefix stringappend_783_0)) of + SOME (stringappend_784_0,stringappend_785_0) => (stringappend_784_0, stringappend_785_0) + ) of + (() , stringappend_785_0) => + let stringappend_786_0 = (string_drop stringappend_783_0 stringappend_785_0) in + let (rs2, stringappend_788_0) = + ((case ((reg_name_matches_prefix stringappend_786_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_787_0,stringappend_788_0) => (stringappend_787_0, stringappend_788_0) + )) in + (case ((string_drop stringappend_786_0 stringappend_788_0)) of "" => T ) + ) + ) + ) + else if ((case ((mul_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_790_0,stringappend_791_0) => + let stringappend_792_0 = (string_drop stringappend_541_0 stringappend_791_0) in + if ((case ((spc_matches_prefix stringappend_792_0)) of + SOME (stringappend_793_0,stringappend_794_0) => + let stringappend_795_0 = (string_drop stringappend_792_0 stringappend_794_0) in + if ((case ((reg_name_matches_prefix stringappend_795_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_796_0,stringappend_797_0) => + let stringappend_798_0 = (string_drop stringappend_795_0 stringappend_797_0) in + if ((case ((sep_matches_prefix stringappend_798_0)) of + SOME (stringappend_799_0,stringappend_800_0) => + let stringappend_801_0 = (string_drop stringappend_798_0 stringappend_800_0) in + if ((case ((reg_name_matches_prefix stringappend_801_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_802_0,stringappend_803_0) => + let stringappend_804_0 = + (string_drop stringappend_801_0 stringappend_803_0) in + if ((case ((sep_matches_prefix stringappend_804_0)) of + SOME (stringappend_805_0,stringappend_806_0) => + let stringappend_807_0 = + (string_drop stringappend_804_0 stringappend_806_0) in + if ((case ((reg_name_matches_prefix stringappend_807_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_808_0,stringappend_809_0) => + (case ((string_drop stringappend_807_0 stringappend_809_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let ((high, signed1, signed2), stringappend_791_0) = + ((case ((mul_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_790_0,stringappend_791_0) => (stringappend_790_0, stringappend_791_0) + )) in + let stringappend_792_0 = (string_drop stringappend_541_0 stringappend_791_0) in + (case + (case ((spc_matches_prefix stringappend_792_0)) of + SOME (stringappend_793_0,stringappend_794_0) => (stringappend_793_0, stringappend_794_0) + ) of + (() , stringappend_794_0) => + let stringappend_795_0 = (string_drop stringappend_792_0 stringappend_794_0) in + let (rd, stringappend_797_0) = + ((case ((reg_name_matches_prefix stringappend_795_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_796_0,stringappend_797_0) => (stringappend_796_0, stringappend_797_0) + )) in + let stringappend_798_0 = (string_drop stringappend_795_0 stringappend_797_0) in + (case + (case ((sep_matches_prefix stringappend_798_0)) of + SOME (stringappend_799_0,stringappend_800_0) => (stringappend_799_0, stringappend_800_0) + ) of + (() , stringappend_800_0) => + let stringappend_801_0 = (string_drop stringappend_798_0 stringappend_800_0) in + let (rs1, stringappend_803_0) = + ((case ((reg_name_matches_prefix stringappend_801_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_802_0,stringappend_803_0) => (stringappend_802_0, stringappend_803_0) + )) in + let stringappend_804_0 = (string_drop stringappend_801_0 stringappend_803_0) in + (case + (case ((sep_matches_prefix stringappend_804_0)) of + SOME (stringappend_805_0,stringappend_806_0) => (stringappend_805_0, stringappend_806_0) + ) of + (() , stringappend_806_0) => + let stringappend_807_0 = (string_drop stringappend_804_0 stringappend_806_0) in + let (rs2, stringappend_809_0) = + ((case ((reg_name_matches_prefix stringappend_807_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_808_0,stringappend_809_0) => (stringappend_808_0, stringappend_809_0) + )) in + (case ((string_drop stringappend_807_0 stringappend_809_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "div")) /\ (let stringappend_811_0 = (string_drop stringappend_541_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_811_0)) of + SOME (stringappend_812_0,stringappend_813_0) => + let stringappend_814_0 = (string_drop stringappend_811_0 stringappend_813_0) in + if ((case ((spc_matches_prefix stringappend_814_0)) of + SOME (stringappend_815_0,stringappend_816_0) => + let stringappend_817_0 = (string_drop stringappend_814_0 stringappend_816_0) in + if ((case ((reg_name_matches_prefix stringappend_817_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_818_0,stringappend_819_0) => + let stringappend_820_0 = + (string_drop stringappend_817_0 stringappend_819_0) in + if ((case ((sep_matches_prefix stringappend_820_0)) of + SOME (stringappend_821_0,stringappend_822_0) => + let stringappend_823_0 = + (string_drop stringappend_820_0 stringappend_822_0) in + if ((case ((reg_name_matches_prefix stringappend_823_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_824_0,stringappend_825_0) => + let stringappend_826_0 = + (string_drop stringappend_823_0 stringappend_825_0) in + if ((case ((sep_matches_prefix stringappend_826_0)) of + SOME (stringappend_827_0,stringappend_828_0) => + let stringappend_829_0 = + (string_drop stringappend_826_0 stringappend_828_0) in + if ((case ((reg_name_matches_prefix stringappend_829_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_830_0,stringappend_831_0) => + (case ((string_drop stringappend_829_0 + stringappend_831_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_811_0 = (string_drop stringappend_541_0 ((string_length "div"))) in + let (s, stringappend_813_0) = + ((case ((maybe_not_u_matches_prefix stringappend_811_0)) of + SOME (stringappend_812_0,stringappend_813_0) => (stringappend_812_0, stringappend_813_0) + )) in + let stringappend_814_0 = (string_drop stringappend_811_0 stringappend_813_0) in + (case + (case ((spc_matches_prefix stringappend_814_0)) of + SOME (stringappend_815_0,stringappend_816_0) => (stringappend_815_0, stringappend_816_0) + ) of + (() , stringappend_816_0) => + let stringappend_817_0 = (string_drop stringappend_814_0 stringappend_816_0) in + let (rd, stringappend_819_0) = + ((case ((reg_name_matches_prefix stringappend_817_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_818_0,stringappend_819_0) => (stringappend_818_0, stringappend_819_0) + )) in + let stringappend_820_0 = (string_drop stringappend_817_0 stringappend_819_0) in + (case + (case ((sep_matches_prefix stringappend_820_0)) of + SOME (stringappend_821_0,stringappend_822_0) => (stringappend_821_0, stringappend_822_0) + ) of + (() , stringappend_822_0) => + let stringappend_823_0 = (string_drop stringappend_820_0 stringappend_822_0) in + let (rs1, stringappend_825_0) = + ((case ((reg_name_matches_prefix stringappend_823_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_824_0,stringappend_825_0) => (stringappend_824_0, stringappend_825_0) + )) in + let stringappend_826_0 = (string_drop stringappend_823_0 stringappend_825_0) in + (case + (case ((sep_matches_prefix stringappend_826_0)) of + SOME (stringappend_827_0,stringappend_828_0) => (stringappend_827_0, stringappend_828_0) + ) of + (() , stringappend_828_0) => + let stringappend_829_0 = (string_drop stringappend_826_0 stringappend_828_0) in + let (rs2, stringappend_831_0) = + ((case ((reg_name_matches_prefix stringappend_829_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_830_0,stringappend_831_0) => (stringappend_830_0, stringappend_831_0) + )) in + (case ((string_drop stringappend_829_0 stringappend_831_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "rem")) /\ (let stringappend_833_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_833_0)) of + SOME (stringappend_834_0,stringappend_835_0) => + let stringappend_836_0 = (string_drop stringappend_833_0 stringappend_835_0) in + if ((case ((spc_matches_prefix stringappend_836_0)) of + SOME (stringappend_837_0,stringappend_838_0) => + let stringappend_839_0 = (string_drop stringappend_836_0 stringappend_838_0) in + if ((case ((reg_name_matches_prefix stringappend_839_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_840_0,stringappend_841_0) => + let stringappend_842_0 = + (string_drop stringappend_839_0 stringappend_841_0) in + if ((case ((sep_matches_prefix stringappend_842_0)) of + SOME (stringappend_843_0,stringappend_844_0) => + let stringappend_845_0 = + (string_drop stringappend_842_0 stringappend_844_0) in + if ((case ((reg_name_matches_prefix stringappend_845_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_846_0,stringappend_847_0) => + let stringappend_848_0 = + (string_drop stringappend_845_0 stringappend_847_0) in + if ((case ((sep_matches_prefix stringappend_848_0)) of + SOME (stringappend_849_0,stringappend_850_0) => + let stringappend_851_0 = + (string_drop stringappend_848_0 stringappend_850_0) in + if ((case ((reg_name_matches_prefix stringappend_851_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_852_0,stringappend_853_0) => + (case ((string_drop stringappend_851_0 + stringappend_853_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_833_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in + let (s, stringappend_835_0) = + ((case ((maybe_not_u_matches_prefix stringappend_833_0)) of + SOME (stringappend_834_0,stringappend_835_0) => (stringappend_834_0, stringappend_835_0) + )) in + let stringappend_836_0 = (string_drop stringappend_833_0 stringappend_835_0) in + (case + (case ((spc_matches_prefix stringappend_836_0)) of + SOME (stringappend_837_0,stringappend_838_0) => (stringappend_837_0, stringappend_838_0) + ) of + (() , stringappend_838_0) => + let stringappend_839_0 = (string_drop stringappend_836_0 stringappend_838_0) in + let (rd, stringappend_841_0) = + ((case ((reg_name_matches_prefix stringappend_839_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_840_0,stringappend_841_0) => (stringappend_840_0, stringappend_841_0) + )) in + let stringappend_842_0 = (string_drop stringappend_839_0 stringappend_841_0) in + (case + (case ((sep_matches_prefix stringappend_842_0)) of + SOME (stringappend_843_0,stringappend_844_0) => (stringappend_843_0, stringappend_844_0) + ) of + (() , stringappend_844_0) => + let stringappend_845_0 = (string_drop stringappend_842_0 stringappend_844_0) in + let (rs1, stringappend_847_0) = + ((case ((reg_name_matches_prefix stringappend_845_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_846_0,stringappend_847_0) => (stringappend_846_0, stringappend_847_0) + )) in + let stringappend_848_0 = (string_drop stringappend_845_0 stringappend_847_0) in + (case + (case ((sep_matches_prefix stringappend_848_0)) of + SOME (stringappend_849_0,stringappend_850_0) => (stringappend_849_0, stringappend_850_0) + ) of + (() , stringappend_850_0) => + let stringappend_851_0 = (string_drop stringappend_848_0 stringappend_850_0) in + let (rs2, stringappend_853_0) = + ((case ((reg_name_matches_prefix stringappend_851_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_852_0,stringappend_853_0) => (stringappend_852_0, stringappend_853_0) + )) in + (case ((string_drop stringappend_851_0 stringappend_853_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "mulw")) /\ (let stringappend_855_0 = (string_drop stringappend_541_0 ((string_length "mulw"))) in + if ((case ((spc_matches_prefix stringappend_855_0)) of + SOME (stringappend_856_0,stringappend_857_0) => + let stringappend_858_0 = (string_drop stringappend_855_0 stringappend_857_0) in + if ((case ((reg_name_matches_prefix stringappend_858_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_859_0,stringappend_860_0) => + let stringappend_861_0 = (string_drop stringappend_858_0 stringappend_860_0) in + if ((case ((sep_matches_prefix stringappend_861_0)) of + SOME (stringappend_862_0,stringappend_863_0) => + let stringappend_864_0 = + (string_drop stringappend_861_0 stringappend_863_0) in + if ((case ((reg_name_matches_prefix stringappend_864_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_865_0,stringappend_866_0) => + let stringappend_867_0 = + (string_drop stringappend_864_0 stringappend_866_0) in + if ((case ((sep_matches_prefix stringappend_867_0)) of + SOME (stringappend_868_0,stringappend_869_0) => + let stringappend_870_0 = + (string_drop stringappend_867_0 stringappend_869_0) in + if ((case ((reg_name_matches_prefix stringappend_870_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_871_0,stringappend_872_0) => + (case ((string_drop stringappend_870_0 + stringappend_872_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_855_0 = (string_drop stringappend_541_0 ((string_length "mulw"))) in + (case + (case ((spc_matches_prefix stringappend_855_0)) of + SOME (stringappend_856_0,stringappend_857_0) => (stringappend_856_0, stringappend_857_0) + ) of + (() , stringappend_857_0) => + let stringappend_858_0 = (string_drop stringappend_855_0 stringappend_857_0) in + let (rd, stringappend_860_0) = + ((case ((reg_name_matches_prefix stringappend_858_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_859_0,stringappend_860_0) => (stringappend_859_0, stringappend_860_0) + )) in + let stringappend_861_0 = (string_drop stringappend_858_0 stringappend_860_0) in + (case + (case ((sep_matches_prefix stringappend_861_0)) of + SOME (stringappend_862_0,stringappend_863_0) => (stringappend_862_0, stringappend_863_0) + ) of + (() , stringappend_863_0) => + let stringappend_864_0 = (string_drop stringappend_861_0 stringappend_863_0) in + let (rs1, stringappend_866_0) = + ((case ((reg_name_matches_prefix stringappend_864_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_865_0,stringappend_866_0) => (stringappend_865_0, stringappend_866_0) + )) in + let stringappend_867_0 = (string_drop stringappend_864_0 stringappend_866_0) in + (case + (case ((sep_matches_prefix stringappend_867_0)) of + SOME (stringappend_868_0,stringappend_869_0) => (stringappend_868_0, stringappend_869_0) + ) of + (() , stringappend_869_0) => + let stringappend_870_0 = (string_drop stringappend_867_0 stringappend_869_0) in + let (rs2, stringappend_872_0) = + ((case ((reg_name_matches_prefix stringappend_870_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_871_0,stringappend_872_0) => (stringappend_871_0, stringappend_872_0) + )) in + (case ((string_drop stringappend_870_0 stringappend_872_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "div")) /\ (let stringappend_874_0 = (string_drop stringappend_541_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_874_0)) of + SOME (stringappend_875_0,stringappend_876_0) => + let stringappend_877_0 = (string_drop stringappend_874_0 stringappend_876_0) in + if (((((string_startswith stringappend_877_0 "w")) /\ (let stringappend_878_0 = + (string_drop stringappend_877_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_878_0)) of + SOME (stringappend_879_0,stringappend_880_0) => + let stringappend_881_0 = + (string_drop stringappend_878_0 stringappend_880_0) in + if ((case ((reg_name_matches_prefix stringappend_881_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_882_0,stringappend_883_0) => + let stringappend_884_0 = + (string_drop stringappend_881_0 stringappend_883_0) in + if ((case ((sep_matches_prefix stringappend_884_0)) of + SOME (stringappend_885_0,stringappend_886_0) => + let stringappend_887_0 = + (string_drop stringappend_884_0 stringappend_886_0) in + if ((case ((reg_name_matches_prefix stringappend_887_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_888_0,stringappend_889_0) => + let stringappend_890_0 = + (string_drop stringappend_887_0 stringappend_889_0) in + if ((case ((sep_matches_prefix stringappend_890_0)) of + SOME (stringappend_891_0,stringappend_892_0) => + let stringappend_893_0 = + (string_drop stringappend_890_0 + stringappend_892_0) in + if ((case ((reg_name_matches_prefix + stringappend_893_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_894_0,stringappend_895_0) => + (case ((string_drop stringappend_893_0 + stringappend_895_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_874_0 = (string_drop stringappend_541_0 ((string_length "div"))) in + let (s, stringappend_876_0) = + ((case ((maybe_not_u_matches_prefix stringappend_874_0)) of + SOME (stringappend_875_0,stringappend_876_0) => (stringappend_875_0, stringappend_876_0) + )) in + let stringappend_877_0 = (string_drop stringappend_874_0 stringappend_876_0) in + let stringappend_878_0 = (string_drop stringappend_877_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_878_0)) of + SOME (stringappend_879_0,stringappend_880_0) => (stringappend_879_0, stringappend_880_0) + ) of + (() , stringappend_880_0) => + let stringappend_881_0 = (string_drop stringappend_878_0 stringappend_880_0) in + let (rd, stringappend_883_0) = + ((case ((reg_name_matches_prefix stringappend_881_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_882_0,stringappend_883_0) => (stringappend_882_0, stringappend_883_0) + )) in + let stringappend_884_0 = (string_drop stringappend_881_0 stringappend_883_0) in + (case + (case ((sep_matches_prefix stringappend_884_0)) of + SOME (stringappend_885_0,stringappend_886_0) => (stringappend_885_0, stringappend_886_0) + ) of + (() , stringappend_886_0) => + let stringappend_887_0 = (string_drop stringappend_884_0 stringappend_886_0) in + let (rs1, stringappend_889_0) = + ((case ((reg_name_matches_prefix stringappend_887_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_888_0,stringappend_889_0) => (stringappend_888_0, stringappend_889_0) + )) in + let stringappend_890_0 = (string_drop stringappend_887_0 stringappend_889_0) in + (case + (case ((sep_matches_prefix stringappend_890_0)) of + SOME (stringappend_891_0,stringappend_892_0) => (stringappend_891_0, stringappend_892_0) + ) of + (() , stringappend_892_0) => + let stringappend_893_0 = (string_drop stringappend_890_0 stringappend_892_0) in + let (rs2, stringappend_895_0) = + ((case ((reg_name_matches_prefix stringappend_893_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_894_0,stringappend_895_0) => (stringappend_894_0, stringappend_895_0) + )) in + (case ((string_drop stringappend_893_0 stringappend_895_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "rem")) /\ (let stringappend_897_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_897_0)) of + SOME (stringappend_898_0,stringappend_899_0) => + let stringappend_900_0 = (string_drop stringappend_897_0 stringappend_899_0) in + if (((((string_startswith stringappend_900_0 "w")) /\ (let stringappend_901_0 = + (string_drop stringappend_900_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_901_0)) of + SOME (stringappend_902_0,stringappend_903_0) => + let stringappend_904_0 = + (string_drop stringappend_901_0 stringappend_903_0) in + if ((case ((reg_name_matches_prefix stringappend_904_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_905_0,stringappend_906_0) => + let stringappend_907_0 = + (string_drop stringappend_904_0 stringappend_906_0) in + if ((case ((sep_matches_prefix stringappend_907_0)) of + SOME (stringappend_908_0,stringappend_909_0) => + let stringappend_910_0 = + (string_drop stringappend_907_0 stringappend_909_0) in + if ((case ((reg_name_matches_prefix stringappend_910_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_911_0,stringappend_912_0) => + let stringappend_913_0 = + (string_drop stringappend_910_0 stringappend_912_0) in + if ((case ((sep_matches_prefix stringappend_913_0)) of + SOME (stringappend_914_0,stringappend_915_0) => + let stringappend_916_0 = + (string_drop stringappend_913_0 + stringappend_915_0) in + if ((case ((reg_name_matches_prefix + stringappend_916_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_917_0,stringappend_918_0) => + (case ((string_drop stringappend_916_0 + stringappend_918_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_897_0 = (string_drop stringappend_541_0 ((string_length "rem"))) in + let (s, stringappend_899_0) = + ((case ((maybe_not_u_matches_prefix stringappend_897_0)) of + SOME (stringappend_898_0,stringappend_899_0) => (stringappend_898_0, stringappend_899_0) + )) in + let stringappend_900_0 = (string_drop stringappend_897_0 stringappend_899_0) in + let stringappend_901_0 = (string_drop stringappend_900_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_901_0)) of + SOME (stringappend_902_0,stringappend_903_0) => (stringappend_902_0, stringappend_903_0) + ) of + (() , stringappend_903_0) => + let stringappend_904_0 = (string_drop stringappend_901_0 stringappend_903_0) in + let (rd, stringappend_906_0) = + ((case ((reg_name_matches_prefix stringappend_904_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_905_0,stringappend_906_0) => (stringappend_905_0, stringappend_906_0) + )) in + let stringappend_907_0 = (string_drop stringappend_904_0 stringappend_906_0) in + (case + (case ((sep_matches_prefix stringappend_907_0)) of + SOME (stringappend_908_0,stringappend_909_0) => (stringappend_908_0, stringappend_909_0) + ) of + (() , stringappend_909_0) => + let stringappend_910_0 = (string_drop stringappend_907_0 stringappend_909_0) in + let (rs1, stringappend_912_0) = + ((case ((reg_name_matches_prefix stringappend_910_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_911_0,stringappend_912_0) => (stringappend_911_0, stringappend_912_0) + )) in + let stringappend_913_0 = (string_drop stringappend_910_0 stringappend_912_0) in + (case + (case ((sep_matches_prefix stringappend_913_0)) of + SOME (stringappend_914_0,stringappend_915_0) => (stringappend_914_0, stringappend_915_0) + ) of + (() , stringappend_915_0) => + let stringappend_916_0 = (string_drop stringappend_913_0 stringappend_915_0) in + let (rs2, stringappend_918_0) = + ((case ((reg_name_matches_prefix stringappend_916_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_917_0,stringappend_918_0) => (stringappend_917_0, stringappend_918_0) + )) in + (case ((string_drop stringappend_916_0 stringappend_918_0)) of "" => T ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "fence")) /\ (let stringappend_920_0 = (string_drop stringappend_541_0 ((string_length "fence"))) in + if ((case ((spc_matches_prefix stringappend_920_0)) of + SOME (stringappend_921_0,stringappend_922_0) => + let stringappend_923_0 = (string_drop stringappend_920_0 stringappend_922_0) in + if ((case ((fence_bits_matches_prefix stringappend_923_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_924_0,stringappend_925_0) => + let stringappend_926_0 = (string_drop stringappend_923_0 stringappend_925_0) in + if ((case ((sep_matches_prefix stringappend_926_0)) of + SOME (stringappend_927_0,stringappend_928_0) => + let stringappend_929_0 = + (string_drop stringappend_926_0 stringappend_928_0) in + if ((case ((fence_bits_matches_prefix stringappend_929_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_930_0,stringappend_931_0) => + (case ((string_drop stringappend_929_0 stringappend_931_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_920_0 = (string_drop stringappend_541_0 ((string_length "fence"))) in + (case + (case ((spc_matches_prefix stringappend_920_0)) of + SOME (stringappend_921_0,stringappend_922_0) => (stringappend_921_0, stringappend_922_0) + ) of + (() , stringappend_922_0) => + let stringappend_923_0 = (string_drop stringappend_920_0 stringappend_922_0) in + let (pred, stringappend_925_0) = + ((case ((fence_bits_matches_prefix stringappend_923_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_924_0,stringappend_925_0) => (stringappend_924_0, stringappend_925_0) + )) in + let stringappend_926_0 = (string_drop stringappend_923_0 stringappend_925_0) in + (case + (case ((sep_matches_prefix stringappend_926_0)) of + SOME (stringappend_927_0,stringappend_928_0) => (stringappend_927_0, stringappend_928_0) + ) of + (() , stringappend_928_0) => + let stringappend_929_0 = (string_drop stringappend_926_0 stringappend_928_0) in + let (succ, stringappend_931_0) = + ((case ((fence_bits_matches_prefix stringappend_929_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_930_0,stringappend_931_0) => (stringappend_930_0, stringappend_931_0) + )) in + (case ((string_drop stringappend_929_0 stringappend_931_0)) of "" => T ) + ) + ) + else + (case stringappend_541_0 of + "fence.i" => T + | "ecall" => T + | "mret" => T + | "sret" => T + | "ebreak" => T + | "wfi" => T + | stringappend_541_0 => + if (((((string_startswith stringappend_541_0 "sfence.vma")) /\ (let stringappend_933_0 = + (string_drop stringappend_541_0 ((string_length "sfence.vma"))) in + if ((case ((spc_matches_prefix stringappend_933_0)) of + SOME (stringappend_934_0,stringappend_935_0) => + let stringappend_936_0 = (string_drop stringappend_933_0 stringappend_935_0) in + if ((case ((reg_name_matches_prefix stringappend_936_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_937_0,stringappend_938_0) => + let stringappend_939_0 = (string_drop stringappend_936_0 stringappend_938_0) in + if ((case ((sep_matches_prefix stringappend_939_0)) of + SOME (stringappend_940_0,stringappend_941_0) => + let stringappend_942_0 = + (string_drop stringappend_939_0 stringappend_941_0) in + if ((case ((reg_name_matches_prefix stringappend_942_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_943_0,stringappend_944_0) => + (case ((string_drop stringappend_942_0 stringappend_944_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_933_0 = (string_drop stringappend_541_0 ((string_length "sfence.vma"))) in + (case + (case ((spc_matches_prefix stringappend_933_0)) of + SOME (stringappend_934_0,stringappend_935_0) => + (stringappend_934_0, stringappend_935_0) + ) of + (() , stringappend_935_0) => + let stringappend_936_0 = (string_drop stringappend_933_0 stringappend_935_0) in + let (rs1, stringappend_938_0) = + ((case ((reg_name_matches_prefix stringappend_936_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_937_0,stringappend_938_0) => + (stringappend_937_0, stringappend_938_0) + )) in + let stringappend_939_0 = (string_drop stringappend_936_0 stringappend_938_0) in + (case + (case ((sep_matches_prefix stringappend_939_0)) of + SOME (stringappend_940_0,stringappend_941_0) => + (stringappend_940_0, stringappend_941_0) + ) of + (() , stringappend_941_0) => + let stringappend_942_0 = (string_drop stringappend_939_0 stringappend_941_0) in + let (rs2, stringappend_944_0) = + ((case ((reg_name_matches_prefix stringappend_942_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_943_0,stringappend_944_0) => + (stringappend_943_0, stringappend_944_0) + )) in + (case ((string_drop stringappend_942_0 stringappend_944_0)) of "" => T ) + ) + ) + else if (((((string_startswith stringappend_541_0 "lr.")) /\ (let stringappend_946_0 = (string_drop stringappend_541_0 ((string_length "lr."))) in + if ((case ((maybe_aq_matches_prefix stringappend_946_0)) of + SOME (stringappend_947_0,stringappend_948_0) => + let stringappend_949_0 = (string_drop stringappend_946_0 stringappend_948_0) in + if ((case ((maybe_rl_matches_prefix stringappend_949_0)) of + SOME (stringappend_950_0,stringappend_951_0) => + let stringappend_952_0 = + (string_drop stringappend_949_0 stringappend_951_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_952_0)) of + SOME (stringappend_953_0,stringappend_954_0) => + let stringappend_955_0 = + (string_drop stringappend_952_0 stringappend_954_0) in + if ((case ((spc_matches_prefix stringappend_955_0)) of + SOME (stringappend_956_0,stringappend_957_0) => + let stringappend_958_0 = + (string_drop stringappend_955_0 stringappend_957_0) in + if ((case ((reg_name_matches_prefix stringappend_958_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_959_0,stringappend_960_0) => + let stringappend_961_0 = + (string_drop stringappend_958_0 stringappend_960_0) in + if ((case ((sep_matches_prefix stringappend_961_0)) of + SOME (stringappend_962_0,stringappend_963_0) => + let stringappend_964_0 = + (string_drop stringappend_961_0 + stringappend_963_0) in + if ((case ((reg_name_matches_prefix + stringappend_964_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_965_0,stringappend_966_0) => + (case ((string_drop stringappend_964_0 + stringappend_966_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_946_0 = (string_drop stringappend_541_0 ((string_length "lr."))) in + let (aq, stringappend_948_0) = + ((case ((maybe_aq_matches_prefix stringappend_946_0)) of + SOME (stringappend_947_0,stringappend_948_0) => + (stringappend_947_0, stringappend_948_0) + )) in + let stringappend_949_0 = (string_drop stringappend_946_0 stringappend_948_0) in + let (rl, stringappend_951_0) = + ((case ((maybe_rl_matches_prefix stringappend_949_0)) of + SOME (stringappend_950_0,stringappend_951_0) => + (stringappend_950_0, stringappend_951_0) + )) in + let stringappend_952_0 = (string_drop stringappend_949_0 stringappend_951_0) in + let (size1, stringappend_954_0) = + ((case ((size_mnemonic_matches_prefix stringappend_952_0)) of + SOME (stringappend_953_0,stringappend_954_0) => + (stringappend_953_0, stringappend_954_0) + )) in + let stringappend_955_0 = (string_drop stringappend_952_0 stringappend_954_0) in + (case + (case ((spc_matches_prefix stringappend_955_0)) of + SOME (stringappend_956_0,stringappend_957_0) => + (stringappend_956_0, stringappend_957_0) + ) of + (() , stringappend_957_0) => + let stringappend_958_0 = (string_drop stringappend_955_0 stringappend_957_0) in + let (rd, stringappend_960_0) = + ((case ((reg_name_matches_prefix stringappend_958_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_959_0,stringappend_960_0) => + (stringappend_959_0, stringappend_960_0) + )) in + let stringappend_961_0 = (string_drop stringappend_958_0 stringappend_960_0) in + (case + (case ((sep_matches_prefix stringappend_961_0)) of + SOME (stringappend_962_0,stringappend_963_0) => + (stringappend_962_0, stringappend_963_0) + ) of + (() , stringappend_963_0) => + let stringappend_964_0 = (string_drop stringappend_961_0 stringappend_963_0) in + let (rs1, stringappend_966_0) = + ((case ((reg_name_matches_prefix stringappend_964_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_965_0,stringappend_966_0) => + (stringappend_965_0, stringappend_966_0) + )) in + (case ((string_drop stringappend_964_0 stringappend_966_0)) of "" => T ) + ) + ) + else if (((((string_startswith stringappend_541_0 "sc.")) /\ (let stringappend_968_0 = (string_drop stringappend_541_0 ((string_length "sc."))) in + if ((case ((maybe_aq_matches_prefix stringappend_968_0)) of + SOME (stringappend_969_0,stringappend_970_0) => + let stringappend_971_0 = (string_drop stringappend_968_0 stringappend_970_0) in + if ((case ((maybe_rl_matches_prefix stringappend_971_0)) of + SOME (stringappend_972_0,stringappend_973_0) => + let stringappend_974_0 = + (string_drop stringappend_971_0 stringappend_973_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_974_0)) of + SOME (stringappend_975_0,stringappend_976_0) => + let stringappend_977_0 = + (string_drop stringappend_974_0 stringappend_976_0) in + if ((case ((spc_matches_prefix stringappend_977_0)) of + SOME (stringappend_978_0,stringappend_979_0) => + let stringappend_980_0 = + (string_drop stringappend_977_0 stringappend_979_0) in + if ((case ((reg_name_matches_prefix stringappend_980_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_981_0,stringappend_982_0) => + let stringappend_983_0 = + (string_drop stringappend_980_0 stringappend_982_0) in + if ((case ((sep_matches_prefix stringappend_983_0)) of + SOME (stringappend_984_0,stringappend_985_0) => + let stringappend_986_0 = + (string_drop stringappend_983_0 + stringappend_985_0) in + if ((case ((reg_name_matches_prefix + stringappend_986_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_987_0,stringappend_988_0) => + let stringappend_989_0 = + (string_drop stringappend_986_0 + stringappend_988_0) in + if ((case ((sep_matches_prefix + stringappend_989_0)) of + SOME + (stringappend_990_0,stringappend_991_0) => + let stringappend_992_0 = + (string_drop stringappend_989_0 + stringappend_991_0) in + if ((case ((reg_name_matches_prefix + stringappend_992_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_993_0,stringappend_994_0) => + (case ((string_drop + stringappend_992_0 + stringappend_994_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_968_0 = (string_drop stringappend_541_0 ((string_length "sc."))) in + let (aq, stringappend_970_0) = + ((case ((maybe_aq_matches_prefix stringappend_968_0)) of + SOME (stringappend_969_0,stringappend_970_0) => + (stringappend_969_0, stringappend_970_0) + )) in + let stringappend_971_0 = (string_drop stringappend_968_0 stringappend_970_0) in + let (rl, stringappend_973_0) = + ((case ((maybe_rl_matches_prefix stringappend_971_0)) of + SOME (stringappend_972_0,stringappend_973_0) => + (stringappend_972_0, stringappend_973_0) + )) in + let stringappend_974_0 = (string_drop stringappend_971_0 stringappend_973_0) in + let (size1, stringappend_976_0) = + ((case ((size_mnemonic_matches_prefix stringappend_974_0)) of + SOME (stringappend_975_0,stringappend_976_0) => + (stringappend_975_0, stringappend_976_0) + )) in + let stringappend_977_0 = (string_drop stringappend_974_0 stringappend_976_0) in + (case + (case ((spc_matches_prefix stringappend_977_0)) of + SOME (stringappend_978_0,stringappend_979_0) => + (stringappend_978_0, stringappend_979_0) + ) of + (() , stringappend_979_0) => + let stringappend_980_0 = (string_drop stringappend_977_0 stringappend_979_0) in + let (rd, stringappend_982_0) = + ((case ((reg_name_matches_prefix stringappend_980_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_981_0,stringappend_982_0) => + (stringappend_981_0, stringappend_982_0) + )) in + let stringappend_983_0 = (string_drop stringappend_980_0 stringappend_982_0) in + (case + (case ((sep_matches_prefix stringappend_983_0)) of + SOME (stringappend_984_0,stringappend_985_0) => + (stringappend_984_0, stringappend_985_0) + ) of + (() , stringappend_985_0) => + let stringappend_986_0 = (string_drop stringappend_983_0 stringappend_985_0) in + let (rs1, stringappend_988_0) = + ((case ((reg_name_matches_prefix stringappend_986_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_987_0,stringappend_988_0) => + (stringappend_987_0, stringappend_988_0) + )) in + let stringappend_989_0 = (string_drop stringappend_986_0 stringappend_988_0) in + (case + (case ((sep_matches_prefix stringappend_989_0)) of + SOME (stringappend_990_0,stringappend_991_0) => + (stringappend_990_0, stringappend_991_0) + ) of + (() , stringappend_991_0) => + let stringappend_992_0 = (string_drop stringappend_989_0 stringappend_991_0) in + let (rs2, stringappend_994_0) = + ((case ((reg_name_matches_prefix stringappend_992_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_993_0,stringappend_994_0) => + (stringappend_993_0, stringappend_994_0) + )) in + (case ((string_drop stringappend_992_0 stringappend_994_0)) of "" => T ) + ) + ) + ) + else if ((case ((amo_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_996_0,stringappend_997_0) => + let stringappend_998_0 = (string_drop stringappend_541_0 stringappend_997_0) in + if (((((string_startswith stringappend_998_0 ".")) /\ (let stringappend_999_0 = (string_drop stringappend_998_0 ((string_length "."))) in + if ((case ((size_mnemonic_matches_prefix stringappend_999_0)) of + SOME (stringappend_1000_0,stringappend_1001_0) => + let stringappend_1002_0 = + (string_drop stringappend_999_0 stringappend_1001_0) in + if ((case ((maybe_aq_matches_prefix stringappend_1002_0)) of + SOME (stringappend_1003_0,stringappend_1004_0) => + let stringappend_1005_0 = + (string_drop stringappend_1002_0 stringappend_1004_0) in + if ((case ((maybe_rl_matches_prefix stringappend_1005_0)) of + SOME (stringappend_1006_0,stringappend_1007_0) => + let stringappend_1008_0 = + (string_drop stringappend_1005_0 stringappend_1007_0) in + if ((case ((spc_matches_prefix stringappend_1008_0)) of + SOME (stringappend_1009_0,stringappend_1010_0) => + let stringappend_1011_0 = + (string_drop stringappend_1008_0 stringappend_1010_0) in + if ((case ((reg_name_matches_prefix stringappend_1011_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1012_0,stringappend_1013_0) => + let stringappend_1014_0 = + (string_drop stringappend_1011_0 stringappend_1013_0) in + if ((case ((sep_matches_prefix stringappend_1014_0)) of + SOME (stringappend_1015_0,stringappend_1016_0) => + let stringappend_1017_0 = + (string_drop stringappend_1014_0 + stringappend_1016_0) in + if ((case ((reg_name_matches_prefix + stringappend_1017_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1018_0,stringappend_1019_0) => + let stringappend_1020_0 = + (string_drop stringappend_1017_0 + stringappend_1019_0) in + if ((case ((sep_matches_prefix + stringappend_1020_0)) of + SOME + (stringappend_1021_0,stringappend_1022_0) => + let stringappend_1023_0 = + (string_drop stringappend_1020_0 + stringappend_1022_0) in + if ((case ((reg_name_matches_prefix + stringappend_1023_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_1024_0,stringappend_1025_0) => + (case ((string_drop + stringappend_1023_0 + stringappend_1025_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_997_0) = + ((case ((amo_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_996_0,stringappend_997_0) => + (stringappend_996_0, stringappend_997_0) + )) in + let stringappend_998_0 = (string_drop stringappend_541_0 stringappend_997_0) in + let stringappend_999_0 = (string_drop stringappend_998_0 ((string_length "."))) in + let (width, stringappend_1001_0) = + ((case ((size_mnemonic_matches_prefix stringappend_999_0)) of + SOME (stringappend_1000_0,stringappend_1001_0) => + (stringappend_1000_0, stringappend_1001_0) + )) in + let stringappend_1002_0 = (string_drop stringappend_999_0 stringappend_1001_0) in + let (aq, stringappend_1004_0) = + ((case ((maybe_aq_matches_prefix stringappend_1002_0)) of + SOME (stringappend_1003_0,stringappend_1004_0) => + (stringappend_1003_0, stringappend_1004_0) + )) in + let stringappend_1005_0 = (string_drop stringappend_1002_0 stringappend_1004_0) in + let (rl, stringappend_1007_0) = + ((case ((maybe_rl_matches_prefix stringappend_1005_0)) of + SOME (stringappend_1006_0,stringappend_1007_0) => + (stringappend_1006_0, stringappend_1007_0) + )) in + let stringappend_1008_0 = (string_drop stringappend_1005_0 stringappend_1007_0) in + (case + (case ((spc_matches_prefix stringappend_1008_0)) of + SOME (stringappend_1009_0,stringappend_1010_0) => + (stringappend_1009_0, stringappend_1010_0) + ) of + (() , stringappend_1010_0) => + let stringappend_1011_0 = (string_drop stringappend_1008_0 + stringappend_1010_0) in + let (rd, stringappend_1013_0) = + ((case ((reg_name_matches_prefix stringappend_1011_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1012_0,stringappend_1013_0) => + (stringappend_1012_0, stringappend_1013_0) + )) in + let stringappend_1014_0 = (string_drop stringappend_1011_0 + stringappend_1013_0) in + (case + (case ((sep_matches_prefix stringappend_1014_0)) of + SOME (stringappend_1015_0,stringappend_1016_0) => + (stringappend_1015_0, stringappend_1016_0) + ) of + (() , stringappend_1016_0) => + let stringappend_1017_0 = (string_drop stringappend_1014_0 + stringappend_1016_0) in + let (rs1, stringappend_1019_0) = + ((case ((reg_name_matches_prefix stringappend_1017_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1018_0,stringappend_1019_0) => + (stringappend_1018_0, stringappend_1019_0) + )) in + let stringappend_1020_0 = (string_drop stringappend_1017_0 + stringappend_1019_0) in + (case + (case ((sep_matches_prefix stringappend_1020_0)) of + SOME (stringappend_1021_0,stringappend_1022_0) => + (stringappend_1021_0, stringappend_1022_0) + ) of + (() , stringappend_1022_0) => + let stringappend_1023_0 = (string_drop stringappend_1020_0 + stringappend_1022_0) in + let (rs2, stringappend_1025_0) = + ((case ((reg_name_matches_prefix stringappend_1023_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1024_0,stringappend_1025_0) => + (stringappend_1024_0, stringappend_1025_0) + )) in + (case ((string_drop stringappend_1023_0 stringappend_1025_0)) of + "" => T + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_1027_0,stringappend_1028_0) => + let stringappend_1029_0 = (string_drop stringappend_541_0 stringappend_1028_0) in + if (((((string_startswith stringappend_1029_0 "i")) /\ (let stringappend_1030_0 = (string_drop stringappend_1029_0 ((string_length "i"))) in + if ((case ((spc_matches_prefix stringappend_1030_0)) of + SOME (stringappend_1031_0,stringappend_1032_0) => + let stringappend_1033_0 = + (string_drop stringappend_1030_0 stringappend_1032_0) in + if ((case ((reg_name_matches_prefix stringappend_1033_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1034_0,stringappend_1035_0) => + let stringappend_1036_0 = + (string_drop stringappend_1033_0 stringappend_1035_0) in + if ((case ((sep_matches_prefix stringappend_1036_0)) of + SOME (stringappend_1037_0,stringappend_1038_0) => + let stringappend_1039_0 = + (string_drop stringappend_1036_0 stringappend_1038_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1039_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1040_0,stringappend_1041_0) => + let stringappend_1042_0 = + (string_drop stringappend_1039_0 stringappend_1041_0) in + if ((case ((sep_matches_prefix stringappend_1042_0)) of + SOME (stringappend_1043_0,stringappend_1044_0) => + let stringappend_1045_0 = + (string_drop stringappend_1042_0 stringappend_1044_0) in + if ((case ((csr_name_map_matches_prefix + stringappend_1045_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1046_0,stringappend_1047_0) => + (case ((string_drop stringappend_1045_0 + stringappend_1047_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_1028_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_1027_0,stringappend_1028_0) => + (stringappend_1027_0, stringappend_1028_0) + )) in + let stringappend_1029_0 = (string_drop stringappend_541_0 stringappend_1028_0) in + let stringappend_1030_0 = (string_drop stringappend_1029_0 ((string_length "i"))) in + (case + (case ((spc_matches_prefix stringappend_1030_0)) of + SOME (stringappend_1031_0,stringappend_1032_0) => + (stringappend_1031_0, stringappend_1032_0) + ) of + (() , stringappend_1032_0) => + let stringappend_1033_0 = (string_drop stringappend_1030_0 + stringappend_1032_0) in + let (rd, stringappend_1035_0) = + ((case ((reg_name_matches_prefix stringappend_1033_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1034_0,stringappend_1035_0) => + (stringappend_1034_0, stringappend_1035_0) + )) in + let stringappend_1036_0 = (string_drop stringappend_1033_0 + stringappend_1035_0) in + (case + (case ((sep_matches_prefix stringappend_1036_0)) of + SOME (stringappend_1037_0,stringappend_1038_0) => + (stringappend_1037_0, stringappend_1038_0) + ) of + (() , stringappend_1038_0) => + let stringappend_1039_0 = (string_drop stringappend_1036_0 + stringappend_1038_0) in + let (rs1, stringappend_1041_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1039_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1040_0,stringappend_1041_0) => + (stringappend_1040_0, stringappend_1041_0) + )) in + let stringappend_1042_0 = (string_drop stringappend_1039_0 + stringappend_1041_0) in + (case + (case ((sep_matches_prefix stringappend_1042_0)) of + SOME (stringappend_1043_0,stringappend_1044_0) => + (stringappend_1043_0, stringappend_1044_0) + ) of + (() , stringappend_1044_0) => + let stringappend_1045_0 = (string_drop stringappend_1042_0 + stringappend_1044_0) in + let (csr, stringappend_1047_0) = + ((case ((csr_name_map_matches_prefix stringappend_1045_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1046_0,stringappend_1047_0) => + (stringappend_1046_0, stringappend_1047_0) + )) in + (case ((string_drop stringappend_1045_0 stringappend_1047_0)) of + "" => T + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_1049_0,stringappend_1050_0) => + let stringappend_1051_0 = (string_drop stringappend_541_0 stringappend_1050_0) in + if ((case ((spc_matches_prefix stringappend_1051_0)) of + SOME (stringappend_1052_0,stringappend_1053_0) => + let stringappend_1054_0 = (string_drop stringappend_1051_0 stringappend_1053_0) in + if ((case ((reg_name_matches_prefix stringappend_1054_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1055_0,stringappend_1056_0) => + let stringappend_1057_0 = (string_drop stringappend_1054_0 stringappend_1056_0) in + if ((case ((sep_matches_prefix stringappend_1057_0)) of + SOME (stringappend_1058_0,stringappend_1059_0) => + let stringappend_1060_0 = + (string_drop stringappend_1057_0 stringappend_1059_0) in + if ((case ((reg_name_matches_prefix stringappend_1060_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_1061_0,stringappend_1062_0) => + let stringappend_1063_0 = + (string_drop stringappend_1060_0 stringappend_1062_0) in + if ((case ((sep_matches_prefix stringappend_1063_0)) of + SOME (stringappend_1064_0,stringappend_1065_0) => + let stringappend_1066_0 = + (string_drop stringappend_1063_0 stringappend_1065_0) in + if ((case ((csr_name_map_matches_prefix stringappend_1066_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_1067_0,stringappend_1068_0) => + (case ((string_drop stringappend_1066_0 + stringappend_1068_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_1050_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_541_0)) of + SOME (stringappend_1049_0,stringappend_1050_0) => + (stringappend_1049_0, stringappend_1050_0) + )) in + let stringappend_1051_0 = (string_drop stringappend_541_0 stringappend_1050_0) in + (case + (case ((spc_matches_prefix stringappend_1051_0)) of + SOME (stringappend_1052_0,stringappend_1053_0) => + (stringappend_1052_0, stringappend_1053_0) + ) of + (() , stringappend_1053_0) => + let stringappend_1054_0 = (string_drop stringappend_1051_0 + stringappend_1053_0) in + let (rd, stringappend_1056_0) = + ((case ((reg_name_matches_prefix stringappend_1054_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1055_0,stringappend_1056_0) => + (stringappend_1055_0, stringappend_1056_0) + )) in + let stringappend_1057_0 = (string_drop stringappend_1054_0 + stringappend_1056_0) in + (case + (case ((sep_matches_prefix stringappend_1057_0)) of + SOME (stringappend_1058_0,stringappend_1059_0) => + (stringappend_1058_0, stringappend_1059_0) + ) of + (() , stringappend_1059_0) => + let stringappend_1060_0 = (string_drop stringappend_1057_0 + stringappend_1059_0) in + let (rs1, stringappend_1062_0) = + ((case ((reg_name_matches_prefix stringappend_1060_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_1061_0,stringappend_1062_0) => + (stringappend_1061_0, stringappend_1062_0) + )) in + let stringappend_1063_0 = (string_drop stringappend_1060_0 + stringappend_1062_0) in + (case + (case ((sep_matches_prefix stringappend_1063_0)) of + SOME (stringappend_1064_0,stringappend_1065_0) => + (stringappend_1064_0, stringappend_1065_0) + ) of + (() , stringappend_1065_0) => + let stringappend_1066_0 = (string_drop stringappend_1063_0 + stringappend_1065_0) in + let (csr, stringappend_1068_0) = + ((case ((csr_name_map_matches_prefix stringappend_1066_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_1067_0,stringappend_1068_0) => + (stringappend_1067_0, stringappend_1068_0) + )) in + (case ((string_drop stringappend_1066_0 stringappend_1068_0)) of + "" => T + ) + ) + ) + ) + else if (((((string_startswith stringappend_541_0 "illegal")) /\ (let stringappend_1070_0 = + (string_drop stringappend_541_0 ((string_length "illegal"))) in + if ((case ((spc_matches_prefix stringappend_1070_0)) of + SOME (stringappend_1071_0,stringappend_1072_0) => + let stringappend_1073_0 = + (string_drop stringappend_1070_0 stringappend_1072_0) in + if ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1073_0 + : (( 32 words$word # ii))option)) of + SOME (stringappend_1074_0,stringappend_1075_0) => + (case ((string_drop stringappend_1073_0 stringappend_1075_0)) of + "" => T + | _ => F + ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_1070_0 = (string_drop stringappend_541_0 ((string_length "illegal"))) in + (case + (case ((spc_matches_prefix stringappend_1070_0)) of + SOME (stringappend_1071_0,stringappend_1072_0) => + (stringappend_1071_0, stringappend_1072_0) + ) of + (() , stringappend_1072_0) => + let stringappend_1073_0 = (string_drop stringappend_1070_0 + stringappend_1072_0) in + let (s, stringappend_1075_0) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1073_0 : (( 32 words$word # ii)) option)) of + SOME (stringappend_1074_0,stringappend_1075_0) => + (stringappend_1074_0, stringappend_1075_0) + )) in + (case ((string_drop stringappend_1073_0 stringappend_1075_0)) of + "" => T + ) + ) + else F + )))`; + + +(*val assembly_matches_prefix : string -> maybe ((ast * ii))*) + +val _ = Define ` + ((assembly_matches_prefix:string ->(ast#int)option) arg_= + (let stringappend_0_0 = arg_ in + if ((case ((utype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_1_0,stringappend_2_0) => + let stringappend_3_0 = (string_drop stringappend_0_0 stringappend_2_0) in + if ((case ((spc_matches_prefix stringappend_3_0)) of + SOME (stringappend_4_0,stringappend_5_0) => + let stringappend_6_0 = (string_drop stringappend_3_0 stringappend_5_0) in + if ((case ((reg_name_matches_prefix stringappend_6_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_7_0,stringappend_8_0) => + let stringappend_9_0 = (string_drop stringappend_6_0 stringappend_8_0) in + if ((case ((sep_matches_prefix stringappend_9_0)) of + SOME (stringappend_10_0,stringappend_11_0) => + let stringappend_12_0 = (string_drop stringappend_9_0 stringappend_11_0) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_12_0 + : (( 20 words$word # ii))option)) of + SOME (stringappend_13_0,stringappend_14_0) => + (case ((string_drop stringappend_12_0 stringappend_14_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_2_0) = + ((case ((utype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_1_0,stringappend_2_0) => (stringappend_1_0, stringappend_2_0) + )) in + let stringappend_3_0 = (string_drop stringappend_0_0 stringappend_2_0) in + (case + (case ((spc_matches_prefix stringappend_3_0)) of + SOME (stringappend_4_0,stringappend_5_0) => (stringappend_4_0, stringappend_5_0) + ) of + (() , stringappend_5_0) => + let stringappend_6_0 = (string_drop stringappend_3_0 stringappend_5_0) in + let (rd, stringappend_8_0) = + ((case ((reg_name_matches_prefix stringappend_6_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_7_0,stringappend_8_0) => (stringappend_7_0, stringappend_8_0) + )) in + let stringappend_9_0 = (string_drop stringappend_6_0 stringappend_8_0) in + (case + (case ((sep_matches_prefix stringappend_9_0)) of + SOME (stringappend_10_0,stringappend_11_0) => (stringappend_10_0, stringappend_11_0) + ) of + (() , stringappend_11_0) => + let stringappend_12_0 = (string_drop stringappend_9_0 stringappend_11_0) in + let (imm, stringappend_14_0) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12_0 : (( 20 words$word # ii)) option)) of + SOME (stringappend_13_0,stringappend_14_0) => (stringappend_13_0, stringappend_14_0) + )) in + (case ((string_drop stringappend_12_0 stringappend_14_0)) of + s_ => SOME + (UTYPE (imm,rd,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "jal")) /\ (let stringappend_16_0 = (string_drop stringappend_0_0 ((string_length "jal"))) in + if ((case ((spc_matches_prefix stringappend_16_0)) of + SOME (stringappend_17_0,stringappend_18_0) => + let stringappend_19_0 = (string_drop stringappend_16_0 stringappend_18_0) in + if ((case ((reg_name_matches_prefix stringappend_19_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_20_0,stringappend_21_0) => + let stringappend_22_0 = (string_drop stringappend_19_0 stringappend_21_0) in + if ((case ((sep_matches_prefix stringappend_22_0)) of + SOME (stringappend_23_0,stringappend_24_0) => + let stringappend_25_0 = + (string_drop stringappend_22_0 stringappend_24_0) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_25_0 + : (( 21 words$word # ii))option)) of + SOME (stringappend_26_0,stringappend_27_0) => + (case ((string_drop stringappend_25_0 stringappend_27_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_16_0 = (string_drop stringappend_0_0 ((string_length "jal"))) in + (case + (case ((spc_matches_prefix stringappend_16_0)) of + SOME (stringappend_17_0,stringappend_18_0) => (stringappend_17_0, stringappend_18_0) + ) of + (() , stringappend_18_0) => + let stringappend_19_0 = (string_drop stringappend_16_0 stringappend_18_0) in + let (rd, stringappend_21_0) = + ((case ((reg_name_matches_prefix stringappend_19_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_20_0,stringappend_21_0) => (stringappend_20_0, stringappend_21_0) + )) in + let stringappend_22_0 = (string_drop stringappend_19_0 stringappend_21_0) in + (case + (case ((sep_matches_prefix stringappend_22_0)) of + SOME (stringappend_23_0,stringappend_24_0) => (stringappend_23_0, stringappend_24_0) + ) of + (() , stringappend_24_0) => + let stringappend_25_0 = (string_drop stringappend_22_0 stringappend_24_0) in + let (imm, stringappend_27_0) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_25_0 : (( 21 words$word # ii)) option)) of + SOME (stringappend_26_0,stringappend_27_0) => (stringappend_26_0, stringappend_27_0) + )) in + (case ((string_drop stringappend_25_0 stringappend_27_0)) of + s_ => SOME + (RISCV_JAL (imm,rd), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "jalr")) /\ (let stringappend_29_0 = (string_drop stringappend_0_0 ((string_length "jalr"))) in + if ((case ((spc_matches_prefix stringappend_29_0)) of + SOME (stringappend_30_0,stringappend_31_0) => + let stringappend_32_0 = (string_drop stringappend_29_0 stringappend_31_0) in + if ((case ((reg_name_matches_prefix stringappend_32_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_33_0,stringappend_34_0) => + let stringappend_35_0 = (string_drop stringappend_32_0 stringappend_34_0) in + if ((case ((sep_matches_prefix stringappend_35_0)) of + SOME (stringappend_36_0,stringappend_37_0) => + let stringappend_38_0 = + (string_drop stringappend_35_0 stringappend_37_0) in + if ((case ((reg_name_matches_prefix stringappend_38_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_39_0,stringappend_40_0) => + let stringappend_41_0 = + (string_drop stringappend_38_0 stringappend_40_0) in + if ((case ((sep_matches_prefix stringappend_41_0)) of + SOME (stringappend_42_0,stringappend_43_0) => + let stringappend_44_0 = + (string_drop stringappend_41_0 stringappend_43_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_44_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_45_0,stringappend_46_0) => + (case ((string_drop stringappend_44_0 stringappend_46_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_29_0 = (string_drop stringappend_0_0 ((string_length "jalr"))) in + (case + (case ((spc_matches_prefix stringappend_29_0)) of + SOME (stringappend_30_0,stringappend_31_0) => (stringappend_30_0, stringappend_31_0) + ) of + (() , stringappend_31_0) => + let stringappend_32_0 = (string_drop stringappend_29_0 stringappend_31_0) in + let (rd, stringappend_34_0) = + ((case ((reg_name_matches_prefix stringappend_32_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_33_0,stringappend_34_0) => (stringappend_33_0, stringappend_34_0) + )) in + let stringappend_35_0 = (string_drop stringappend_32_0 stringappend_34_0) in + (case + (case ((sep_matches_prefix stringappend_35_0)) of + SOME (stringappend_36_0,stringappend_37_0) => (stringappend_36_0, stringappend_37_0) + ) of + (() , stringappend_37_0) => + let stringappend_38_0 = (string_drop stringappend_35_0 stringappend_37_0) in + let (rs1, stringappend_40_0) = + ((case ((reg_name_matches_prefix stringappend_38_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_39_0,stringappend_40_0) => (stringappend_39_0, stringappend_40_0) + )) in + let stringappend_41_0 = (string_drop stringappend_38_0 stringappend_40_0) in + (case + (case ((sep_matches_prefix stringappend_41_0)) of + SOME (stringappend_42_0,stringappend_43_0) => (stringappend_42_0, stringappend_43_0) + ) of + (() , stringappend_43_0) => + let stringappend_44_0 = (string_drop stringappend_41_0 stringappend_43_0) in + let (imm, stringappend_46_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_44_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_45_0,stringappend_46_0) => (stringappend_45_0, stringappend_46_0) + )) in + (case ((string_drop stringappend_44_0 stringappend_46_0)) of + s_ => + SOME + (RISCV_JALR (imm,rs1,rd), ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if ((case ((btype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_48_0,stringappend_49_0) => + let stringappend_50_0 = (string_drop stringappend_0_0 stringappend_49_0) in + if ((case ((spc_matches_prefix stringappend_50_0)) of + SOME (stringappend_51_0,stringappend_52_0) => + let stringappend_53_0 = (string_drop stringappend_50_0 stringappend_52_0) in + if ((case ((reg_name_matches_prefix stringappend_53_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_54_0,stringappend_55_0) => + let stringappend_56_0 = (string_drop stringappend_53_0 stringappend_55_0) in + if ((case ((sep_matches_prefix stringappend_56_0)) of + SOME (stringappend_57_0,stringappend_58_0) => + let stringappend_59_0 = (string_drop stringappend_56_0 stringappend_58_0) in + if ((case ((reg_name_matches_prefix stringappend_59_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_60_0,stringappend_61_0) => + let stringappend_62_0 = (string_drop stringappend_59_0 stringappend_61_0) in + if ((case ((sep_matches_prefix stringappend_62_0)) of + SOME (stringappend_63_0,stringappend_64_0) => + let stringappend_65_0 = + (string_drop stringappend_62_0 stringappend_64_0) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_65_0 + : (( 13 words$word # ii))option)) of + SOME (stringappend_66_0,stringappend_67_0) => + (case ((string_drop stringappend_65_0 stringappend_67_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_49_0) = + ((case ((btype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_48_0,stringappend_49_0) => (stringappend_48_0, stringappend_49_0) + )) in + let stringappend_50_0 = (string_drop stringappend_0_0 stringappend_49_0) in + (case + (case ((spc_matches_prefix stringappend_50_0)) of + SOME (stringappend_51_0,stringappend_52_0) => (stringappend_51_0, stringappend_52_0) + ) of + (() , stringappend_52_0) => + let stringappend_53_0 = (string_drop stringappend_50_0 stringappend_52_0) in + let (rs1, stringappend_55_0) = + ((case ((reg_name_matches_prefix stringappend_53_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_54_0,stringappend_55_0) => (stringappend_54_0, stringappend_55_0) + )) in + let stringappend_56_0 = (string_drop stringappend_53_0 stringappend_55_0) in + (case + (case ((sep_matches_prefix stringappend_56_0)) of + SOME (stringappend_57_0,stringappend_58_0) => (stringappend_57_0, stringappend_58_0) + ) of + (() , stringappend_58_0) => + let stringappend_59_0 = (string_drop stringappend_56_0 stringappend_58_0) in + let (rs2, stringappend_61_0) = + ((case ((reg_name_matches_prefix stringappend_59_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_60_0,stringappend_61_0) => (stringappend_60_0, stringappend_61_0) + )) in + let stringappend_62_0 = (string_drop stringappend_59_0 stringappend_61_0) in + (case + (case ((sep_matches_prefix stringappend_62_0)) of + SOME (stringappend_63_0,stringappend_64_0) => (stringappend_63_0, stringappend_64_0) + ) of + (() , stringappend_64_0) => + let stringappend_65_0 = (string_drop stringappend_62_0 stringappend_64_0) in + let (imm, stringappend_67_0) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_65_0 : (( 13 words$word # ii)) option)) of + SOME (stringappend_66_0,stringappend_67_0) => (stringappend_66_0, stringappend_67_0) + )) in + (case ((string_drop stringappend_65_0 stringappend_67_0)) of + s_ => SOME + (BTYPE (imm,rs2,rs1,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if ((case ((itype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_69_0,stringappend_70_0) => + let stringappend_71_0 = (string_drop stringappend_0_0 stringappend_70_0) in + if ((case ((spc_matches_prefix stringappend_71_0)) of + SOME (stringappend_72_0,stringappend_73_0) => + let stringappend_74_0 = (string_drop stringappend_71_0 stringappend_73_0) in + if ((case ((reg_name_matches_prefix stringappend_74_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_75_0,stringappend_76_0) => + let stringappend_77_0 = (string_drop stringappend_74_0 stringappend_76_0) in + if ((case ((sep_matches_prefix stringappend_77_0)) of + SOME (stringappend_78_0,stringappend_79_0) => + let stringappend_80_0 = (string_drop stringappend_77_0 stringappend_79_0) in + if ((case ((reg_name_matches_prefix stringappend_80_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_81_0,stringappend_82_0) => + let stringappend_83_0 = (string_drop stringappend_80_0 stringappend_82_0) in + if ((case ((sep_matches_prefix stringappend_83_0)) of + SOME (stringappend_84_0,stringappend_85_0) => + let stringappend_86_0 = + (string_drop stringappend_83_0 stringappend_85_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_86_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_87_0,stringappend_88_0) => + (case ((string_drop stringappend_86_0 stringappend_88_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_70_0) = + ((case ((itype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_69_0,stringappend_70_0) => (stringappend_69_0, stringappend_70_0) + )) in + let stringappend_71_0 = (string_drop stringappend_0_0 stringappend_70_0) in + (case + (case ((spc_matches_prefix stringappend_71_0)) of + SOME (stringappend_72_0,stringappend_73_0) => (stringappend_72_0, stringappend_73_0) + ) of + (() , stringappend_73_0) => + let stringappend_74_0 = (string_drop stringappend_71_0 stringappend_73_0) in + let (rd, stringappend_76_0) = + ((case ((reg_name_matches_prefix stringappend_74_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_75_0,stringappend_76_0) => (stringappend_75_0, stringappend_76_0) + )) in + let stringappend_77_0 = (string_drop stringappend_74_0 stringappend_76_0) in + (case + (case ((sep_matches_prefix stringappend_77_0)) of + SOME (stringappend_78_0,stringappend_79_0) => (stringappend_78_0, stringappend_79_0) + ) of + (() , stringappend_79_0) => + let stringappend_80_0 = (string_drop stringappend_77_0 stringappend_79_0) in + let (rs1, stringappend_82_0) = + ((case ((reg_name_matches_prefix stringappend_80_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_81_0,stringappend_82_0) => (stringappend_81_0, stringappend_82_0) + )) in + let stringappend_83_0 = (string_drop stringappend_80_0 stringappend_82_0) in + (case + (case ((sep_matches_prefix stringappend_83_0)) of + SOME (stringappend_84_0,stringappend_85_0) => (stringappend_84_0, stringappend_85_0) + ) of + (() , stringappend_85_0) => + let stringappend_86_0 = (string_drop stringappend_83_0 stringappend_85_0) in + let (imm, stringappend_88_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_86_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_87_0,stringappend_88_0) => (stringappend_87_0, stringappend_88_0) + )) in + (case ((string_drop stringappend_86_0 stringappend_88_0)) of + s_ => SOME + (ITYPE (imm,rs1,rd,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_90_0,stringappend_91_0) => + let stringappend_92_0 = (string_drop stringappend_0_0 stringappend_91_0) in + if ((case ((spc_matches_prefix stringappend_92_0)) of + SOME (stringappend_93_0,stringappend_94_0) => + let stringappend_95_0 = (string_drop stringappend_92_0 stringappend_94_0) in + if ((case ((reg_name_matches_prefix stringappend_95_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_96_0,stringappend_97_0) => + let stringappend_98_0 = (string_drop stringappend_95_0 stringappend_97_0) in + if ((case ((sep_matches_prefix stringappend_98_0)) of + SOME (stringappend_99_0,stringappend_100_0) => + let stringappend_101_0 = (string_drop stringappend_98_0 stringappend_100_0) in + if ((case ((reg_name_matches_prefix stringappend_101_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_102_0,stringappend_103_0) => + let stringappend_104_0 = + (string_drop stringappend_101_0 stringappend_103_0) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_104_0 + : (( 6 words$word # ii))option)) of + SOME (stringappend_105_0,stringappend_106_0) => + (case ((string_drop stringappend_104_0 stringappend_106_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_91_0) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_90_0,stringappend_91_0) => (stringappend_90_0, stringappend_91_0) + )) in + let stringappend_92_0 = (string_drop stringappend_0_0 stringappend_91_0) in + (case + (case ((spc_matches_prefix stringappend_92_0)) of + SOME (stringappend_93_0,stringappend_94_0) => (stringappend_93_0, stringappend_94_0) + ) of + (() , stringappend_94_0) => + let stringappend_95_0 = (string_drop stringappend_92_0 stringappend_94_0) in + let (rd, stringappend_97_0) = + ((case ((reg_name_matches_prefix stringappend_95_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_96_0,stringappend_97_0) => (stringappend_96_0, stringappend_97_0) + )) in + let stringappend_98_0 = (string_drop stringappend_95_0 stringappend_97_0) in + (case + (case ((sep_matches_prefix stringappend_98_0)) of + SOME (stringappend_99_0,stringappend_100_0) => (stringappend_99_0, stringappend_100_0) + ) of + (() , stringappend_100_0) => + let stringappend_101_0 = (string_drop stringappend_98_0 stringappend_100_0) in + let (rs1, stringappend_103_0) = + ((case ((reg_name_matches_prefix stringappend_101_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_102_0,stringappend_103_0) => (stringappend_102_0, stringappend_103_0) + )) in + let stringappend_104_0 = (string_drop stringappend_101_0 stringappend_103_0) in + let (shamt, stringappend_106_0) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_104_0 : (( 6 words$word # ii)) option)) of + SOME (stringappend_105_0,stringappend_106_0) => (stringappend_105_0, stringappend_106_0) + )) in + (case ((string_drop stringappend_104_0 stringappend_106_0)) of + s_ => + SOME + (SHIFTIOP (shamt,rs1,rd,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_108_0,stringappend_109_0) => + let stringappend_110_0 = (string_drop stringappend_0_0 stringappend_109_0) in + if ((case ((spc_matches_prefix stringappend_110_0)) of + SOME (stringappend_111_0,stringappend_112_0) => + let stringappend_113_0 = (string_drop stringappend_110_0 stringappend_112_0) in + if ((case ((reg_name_matches_prefix stringappend_113_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_114_0,stringappend_115_0) => + let stringappend_116_0 = (string_drop stringappend_113_0 stringappend_115_0) in + if ((case ((sep_matches_prefix stringappend_116_0)) of + SOME (stringappend_117_0,stringappend_118_0) => + let stringappend_119_0 = (string_drop stringappend_116_0 stringappend_118_0) in + if ((case ((reg_name_matches_prefix stringappend_119_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_120_0,stringappend_121_0) => + let stringappend_122_0 = + (string_drop stringappend_119_0 stringappend_121_0) in + if ((case ((sep_matches_prefix stringappend_122_0)) of + SOME (stringappend_123_0,stringappend_124_0) => + let stringappend_125_0 = + (string_drop stringappend_122_0 stringappend_124_0) in + if ((case ((reg_name_matches_prefix stringappend_125_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_126_0,stringappend_127_0) => + (case ((string_drop stringappend_125_0 stringappend_127_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_109_0) = + ((case ((rtype_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_108_0,stringappend_109_0) => (stringappend_108_0, stringappend_109_0) + )) in + let stringappend_110_0 = (string_drop stringappend_0_0 stringappend_109_0) in + (case + (case ((spc_matches_prefix stringappend_110_0)) of + SOME (stringappend_111_0,stringappend_112_0) => (stringappend_111_0, stringappend_112_0) + ) of + (() , stringappend_112_0) => + let stringappend_113_0 = (string_drop stringappend_110_0 stringappend_112_0) in + let (rd, stringappend_115_0) = + ((case ((reg_name_matches_prefix stringappend_113_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_114_0,stringappend_115_0) => (stringappend_114_0, stringappend_115_0) + )) in + let stringappend_116_0 = (string_drop stringappend_113_0 stringappend_115_0) in + (case + (case ((sep_matches_prefix stringappend_116_0)) of + SOME (stringappend_117_0,stringappend_118_0) => (stringappend_117_0, stringappend_118_0) + ) of + (() , stringappend_118_0) => + let stringappend_119_0 = (string_drop stringappend_116_0 stringappend_118_0) in + let (rs1, stringappend_121_0) = + ((case ((reg_name_matches_prefix stringappend_119_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_120_0,stringappend_121_0) => (stringappend_120_0, stringappend_121_0) + )) in + let stringappend_122_0 = (string_drop stringappend_119_0 stringappend_121_0) in + (case + (case ((sep_matches_prefix stringappend_122_0)) of + SOME (stringappend_123_0,stringappend_124_0) => (stringappend_123_0, stringappend_124_0) + ) of + (() , stringappend_124_0) => + let stringappend_125_0 = (string_drop stringappend_122_0 stringappend_124_0) in + let (rs2, stringappend_127_0) = + ((case ((reg_name_matches_prefix stringappend_125_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_126_0,stringappend_127_0) => (stringappend_126_0, stringappend_127_0) + )) in + (case ((string_drop stringappend_125_0 stringappend_127_0)) of + s_ => SOME + (RTYPE (rs2,rs1,rd,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "l")) /\ (let stringappend_129_0 = (string_drop stringappend_0_0 ((string_length "l"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_129_0)) of + SOME (stringappend_130_0,stringappend_131_0) => + let stringappend_132_0 = (string_drop stringappend_129_0 stringappend_131_0) in + if ((case ((maybe_u_matches_prefix stringappend_132_0)) of + SOME (stringappend_133_0,stringappend_134_0) => + let stringappend_135_0 = (string_drop stringappend_132_0 stringappend_134_0) in + if ((case ((maybe_aq_matches_prefix stringappend_135_0)) of + SOME (stringappend_136_0,stringappend_137_0) => + let stringappend_138_0 = + (string_drop stringappend_135_0 stringappend_137_0) in + if ((case ((maybe_rl_matches_prefix stringappend_138_0)) of + SOME (stringappend_139_0,stringappend_140_0) => + let stringappend_141_0 = + (string_drop stringappend_138_0 stringappend_140_0) in + if ((case ((spc_matches_prefix stringappend_141_0)) of + SOME (stringappend_142_0,stringappend_143_0) => + let stringappend_144_0 = + (string_drop stringappend_141_0 stringappend_143_0) in + if ((case ((reg_name_matches_prefix stringappend_144_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_145_0,stringappend_146_0) => + let stringappend_147_0 = + (string_drop stringappend_144_0 stringappend_146_0) in + if ((case ((sep_matches_prefix stringappend_147_0)) of + SOME (stringappend_148_0,stringappend_149_0) => + let stringappend_150_0 = + (string_drop stringappend_147_0 + stringappend_149_0) in + if ((case ((reg_name_matches_prefix + stringappend_150_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_151_0,stringappend_152_0) => + let stringappend_153_0 = + (string_drop stringappend_150_0 + stringappend_152_0) in + if ((case ((sep_matches_prefix + stringappend_153_0)) of + SOME + (stringappend_154_0,stringappend_155_0) => + let stringappend_156_0 = + (string_drop stringappend_153_0 + stringappend_155_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_156_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_157_0,stringappend_158_0) => + (case ((string_drop stringappend_156_0 stringappend_158_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_129_0 = (string_drop stringappend_0_0 ((string_length "l"))) in + let (size1, stringappend_131_0) = + ((case ((size_mnemonic_matches_prefix stringappend_129_0)) of + SOME (stringappend_130_0,stringappend_131_0) => (stringappend_130_0, stringappend_131_0) + )) in + let stringappend_132_0 = (string_drop stringappend_129_0 stringappend_131_0) in + let (is_unsigned, stringappend_134_0) = + ((case ((maybe_u_matches_prefix stringappend_132_0)) of + SOME (stringappend_133_0,stringappend_134_0) => (stringappend_133_0, stringappend_134_0) + )) in + let stringappend_135_0 = (string_drop stringappend_132_0 stringappend_134_0) in + let (aq, stringappend_137_0) = + ((case ((maybe_aq_matches_prefix stringappend_135_0)) of + SOME (stringappend_136_0,stringappend_137_0) => (stringappend_136_0, stringappend_137_0) + )) in + let stringappend_138_0 = (string_drop stringappend_135_0 stringappend_137_0) in + let (rl, stringappend_140_0) = + ((case ((maybe_rl_matches_prefix stringappend_138_0)) of + SOME (stringappend_139_0,stringappend_140_0) => (stringappend_139_0, stringappend_140_0) + )) in + let stringappend_141_0 = (string_drop stringappend_138_0 stringappend_140_0) in + (case + (case ((spc_matches_prefix stringappend_141_0)) of + SOME (stringappend_142_0,stringappend_143_0) => (stringappend_142_0, stringappend_143_0) + ) of + (() , stringappend_143_0) => + let stringappend_144_0 = (string_drop stringappend_141_0 stringappend_143_0) in + let (rd, stringappend_146_0) = + ((case ((reg_name_matches_prefix stringappend_144_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_145_0,stringappend_146_0) => (stringappend_145_0, stringappend_146_0) + )) in + let stringappend_147_0 = (string_drop stringappend_144_0 stringappend_146_0) in + (case + (case ((sep_matches_prefix stringappend_147_0)) of + SOME (stringappend_148_0,stringappend_149_0) => (stringappend_148_0, stringappend_149_0) + ) of + (() , stringappend_149_0) => + let stringappend_150_0 = (string_drop stringappend_147_0 stringappend_149_0) in + let (rs1, stringappend_152_0) = + ((case ((reg_name_matches_prefix stringappend_150_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_151_0,stringappend_152_0) => (stringappend_151_0, stringappend_152_0) + )) in + let stringappend_153_0 = (string_drop stringappend_150_0 stringappend_152_0) in + (case + (case ((sep_matches_prefix stringappend_153_0)) of + SOME (stringappend_154_0,stringappend_155_0) => (stringappend_154_0, stringappend_155_0) + ) of + (() , stringappend_155_0) => + let stringappend_156_0 = (string_drop stringappend_153_0 stringappend_155_0) in + let (imm, stringappend_158_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_156_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_157_0,stringappend_158_0) => (stringappend_157_0, stringappend_158_0) + )) in + (case ((string_drop stringappend_156_0 stringappend_158_0)) of + s_ => + SOME + (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl), + ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "s")) /\ (let stringappend_160_0 = (string_drop stringappend_0_0 ((string_length "s"))) in + if ((case ((size_mnemonic_matches_prefix stringappend_160_0)) of + SOME (stringappend_161_0,stringappend_162_0) => + let stringappend_163_0 = (string_drop stringappend_160_0 stringappend_162_0) in + if ((case ((maybe_aq_matches_prefix stringappend_163_0)) of + SOME (stringappend_164_0,stringappend_165_0) => + let stringappend_166_0 = (string_drop stringappend_163_0 stringappend_165_0) in + if ((case ((maybe_rl_matches_prefix stringappend_166_0)) of + SOME (stringappend_167_0,stringappend_168_0) => + let stringappend_169_0 = + (string_drop stringappend_166_0 stringappend_168_0) in + if ((case ((spc_matches_prefix stringappend_169_0)) of + SOME (stringappend_170_0,stringappend_171_0) => + let stringappend_172_0 = + (string_drop stringappend_169_0 stringappend_171_0) in + if ((case ((reg_name_matches_prefix stringappend_172_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_173_0,stringappend_174_0) => + let stringappend_175_0 = + (string_drop stringappend_172_0 stringappend_174_0) in + if ((case ((sep_matches_prefix stringappend_175_0)) of + SOME (stringappend_176_0,stringappend_177_0) => + let stringappend_178_0 = + (string_drop stringappend_175_0 stringappend_177_0) in + if ((case ((reg_name_matches_prefix stringappend_178_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_179_0,stringappend_180_0) => + let stringappend_181_0 = + (string_drop stringappend_178_0 + stringappend_180_0) in + if ((case ((sep_matches_prefix stringappend_181_0)) of + SOME (stringappend_182_0,stringappend_183_0) => + let stringappend_184_0 = + (string_drop stringappend_181_0 + stringappend_183_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_184_0 + : (( 12 words$word # ii))option)) of + SOME + (stringappend_185_0,stringappend_186_0) => + (case ((string_drop stringappend_184_0 stringappend_186_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_160_0 = (string_drop stringappend_0_0 ((string_length "s"))) in + let (size1, stringappend_162_0) = + ((case ((size_mnemonic_matches_prefix stringappend_160_0)) of + SOME (stringappend_161_0,stringappend_162_0) => (stringappend_161_0, stringappend_162_0) + )) in + let stringappend_163_0 = (string_drop stringappend_160_0 stringappend_162_0) in + let (aq, stringappend_165_0) = + ((case ((maybe_aq_matches_prefix stringappend_163_0)) of + SOME (stringappend_164_0,stringappend_165_0) => (stringappend_164_0, stringappend_165_0) + )) in + let stringappend_166_0 = (string_drop stringappend_163_0 stringappend_165_0) in + let (rl, stringappend_168_0) = + ((case ((maybe_rl_matches_prefix stringappend_166_0)) of + SOME (stringappend_167_0,stringappend_168_0) => (stringappend_167_0, stringappend_168_0) + )) in + let stringappend_169_0 = (string_drop stringappend_166_0 stringappend_168_0) in + (case + (case ((spc_matches_prefix stringappend_169_0)) of + SOME (stringappend_170_0,stringappend_171_0) => (stringappend_170_0, stringappend_171_0) + ) of + (() , stringappend_171_0) => + let stringappend_172_0 = (string_drop stringappend_169_0 stringappend_171_0) in + let (rd, stringappend_174_0) = + ((case ((reg_name_matches_prefix stringappend_172_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_173_0,stringappend_174_0) => (stringappend_173_0, stringappend_174_0) + )) in + let stringappend_175_0 = (string_drop stringappend_172_0 stringappend_174_0) in + (case + (case ((sep_matches_prefix stringappend_175_0)) of + SOME (stringappend_176_0,stringappend_177_0) => (stringappend_176_0, stringappend_177_0) + ) of + (() , stringappend_177_0) => + let stringappend_178_0 = (string_drop stringappend_175_0 stringappend_177_0) in + let (rs1, stringappend_180_0) = + ((case ((reg_name_matches_prefix stringappend_178_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_179_0,stringappend_180_0) => (stringappend_179_0, stringappend_180_0) + )) in + let stringappend_181_0 = (string_drop stringappend_178_0 stringappend_180_0) in + (case + (case ((sep_matches_prefix stringappend_181_0)) of + SOME (stringappend_182_0,stringappend_183_0) => (stringappend_182_0, stringappend_183_0) + ) of + (() , stringappend_183_0) => + let stringappend_184_0 = (string_drop stringappend_181_0 stringappend_183_0) in + let (imm, stringappend_186_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_184_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_185_0,stringappend_186_0) => (stringappend_185_0, stringappend_186_0) + )) in + (case ((string_drop stringappend_184_0 stringappend_186_0)) of + s_ => + SOME + (STORE (imm,rs1,rd,size1,aq,rl), + ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "addiw")) /\ (let stringappend_188_0 = (string_drop stringappend_0_0 ((string_length "addiw"))) in + if ((case ((spc_matches_prefix stringappend_188_0)) of + SOME (stringappend_189_0,stringappend_190_0) => + let stringappend_191_0 = (string_drop stringappend_188_0 stringappend_190_0) in + if ((case ((reg_name_matches_prefix stringappend_191_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_192_0,stringappend_193_0) => + let stringappend_194_0 = (string_drop stringappend_191_0 stringappend_193_0) in + if ((case ((sep_matches_prefix stringappend_194_0)) of + SOME (stringappend_195_0,stringappend_196_0) => + let stringappend_197_0 = + (string_drop stringappend_194_0 stringappend_196_0) in + if ((case ((reg_name_matches_prefix stringappend_197_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_198_0,stringappend_199_0) => + let stringappend_200_0 = + (string_drop stringappend_197_0 stringappend_199_0) in + if ((case ((sep_matches_prefix stringappend_200_0)) of + SOME (stringappend_201_0,stringappend_202_0) => + let stringappend_203_0 = + (string_drop stringappend_200_0 stringappend_202_0) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_203_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_204_0,stringappend_205_0) => + (case ((string_drop stringappend_203_0 stringappend_205_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_188_0 = (string_drop stringappend_0_0 ((string_length "addiw"))) in + (case + (case ((spc_matches_prefix stringappend_188_0)) of + SOME (stringappend_189_0,stringappend_190_0) => (stringappend_189_0, stringappend_190_0) + ) of + (() , stringappend_190_0) => + let stringappend_191_0 = (string_drop stringappend_188_0 stringappend_190_0) in + let (rd, stringappend_193_0) = + ((case ((reg_name_matches_prefix stringappend_191_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_192_0,stringappend_193_0) => (stringappend_192_0, stringappend_193_0) + )) in + let stringappend_194_0 = (string_drop stringappend_191_0 stringappend_193_0) in + (case + (case ((sep_matches_prefix stringappend_194_0)) of + SOME (stringappend_195_0,stringappend_196_0) => (stringappend_195_0, stringappend_196_0) + ) of + (() , stringappend_196_0) => + let stringappend_197_0 = (string_drop stringappend_194_0 stringappend_196_0) in + let (rs1, stringappend_199_0) = + ((case ((reg_name_matches_prefix stringappend_197_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_198_0,stringappend_199_0) => (stringappend_198_0, stringappend_199_0) + )) in + let stringappend_200_0 = (string_drop stringappend_197_0 stringappend_199_0) in + (case + (case ((sep_matches_prefix stringappend_200_0)) of + SOME (stringappend_201_0,stringappend_202_0) => (stringappend_201_0, stringappend_202_0) + ) of + (() , stringappend_202_0) => + let stringappend_203_0 = (string_drop stringappend_200_0 stringappend_202_0) in + let (imm, stringappend_205_0) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_203_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_204_0,stringappend_205_0) => (stringappend_204_0, stringappend_205_0) + )) in + (case ((string_drop stringappend_203_0 stringappend_205_0)) of + s_ => SOME + (ADDIW (imm,rs1,rd), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_207_0,stringappend_208_0) => + let stringappend_209_0 = (string_drop stringappend_0_0 stringappend_208_0) in + if ((case ((spc_matches_prefix stringappend_209_0)) of + SOME (stringappend_210_0,stringappend_211_0) => + let stringappend_212_0 = (string_drop stringappend_209_0 stringappend_211_0) in + if ((case ((reg_name_matches_prefix stringappend_212_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_213_0,stringappend_214_0) => + let stringappend_215_0 = (string_drop stringappend_212_0 stringappend_214_0) in + if ((case ((sep_matches_prefix stringappend_215_0)) of + SOME (stringappend_216_0,stringappend_217_0) => + let stringappend_218_0 = (string_drop stringappend_215_0 stringappend_217_0) in + if ((case ((reg_name_matches_prefix stringappend_218_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_219_0,stringappend_220_0) => + let stringappend_221_0 = + (string_drop stringappend_218_0 stringappend_220_0) in + if ((case ((sep_matches_prefix stringappend_221_0)) of + SOME (stringappend_222_0,stringappend_223_0) => + let stringappend_224_0 = + (string_drop stringappend_221_0 stringappend_223_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_224_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_225_0,stringappend_226_0) => + (case ((string_drop stringappend_224_0 stringappend_226_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_208_0) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_207_0,stringappend_208_0) => (stringappend_207_0, stringappend_208_0) + )) in + let stringappend_209_0 = (string_drop stringappend_0_0 stringappend_208_0) in + (case + (case ((spc_matches_prefix stringappend_209_0)) of + SOME (stringappend_210_0,stringappend_211_0) => (stringappend_210_0, stringappend_211_0) + ) of + (() , stringappend_211_0) => + let stringappend_212_0 = (string_drop stringappend_209_0 stringappend_211_0) in + let (rd, stringappend_214_0) = + ((case ((reg_name_matches_prefix stringappend_212_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_213_0,stringappend_214_0) => (stringappend_213_0, stringappend_214_0) + )) in + let stringappend_215_0 = (string_drop stringappend_212_0 stringappend_214_0) in + (case + (case ((sep_matches_prefix stringappend_215_0)) of + SOME (stringappend_216_0,stringappend_217_0) => (stringappend_216_0, stringappend_217_0) + ) of + (() , stringappend_217_0) => + let stringappend_218_0 = (string_drop stringappend_215_0 stringappend_217_0) in + let (rs1, stringappend_220_0) = + ((case ((reg_name_matches_prefix stringappend_218_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_219_0,stringappend_220_0) => (stringappend_219_0, stringappend_220_0) + )) in + let stringappend_221_0 = (string_drop stringappend_218_0 stringappend_220_0) in + (case + (case ((sep_matches_prefix stringappend_221_0)) of + SOME (stringappend_222_0,stringappend_223_0) => (stringappend_222_0, stringappend_223_0) + ) of + (() , stringappend_223_0) => + let stringappend_224_0 = (string_drop stringappend_221_0 stringappend_223_0) in + let (shamt, stringappend_226_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_224_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_225_0,stringappend_226_0) => (stringappend_225_0, stringappend_226_0) + )) in + (case ((string_drop stringappend_224_0 stringappend_226_0)) of + s_ => + SOME + (SHIFTW (shamt,rs1,rd,op), ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_228_0,stringappend_229_0) => + let stringappend_230_0 = (string_drop stringappend_0_0 stringappend_229_0) in + if ((case ((spc_matches_prefix stringappend_230_0)) of + SOME (stringappend_231_0,stringappend_232_0) => + let stringappend_233_0 = (string_drop stringappend_230_0 stringappend_232_0) in + if ((case ((reg_name_matches_prefix stringappend_233_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_234_0,stringappend_235_0) => + let stringappend_236_0 = (string_drop stringappend_233_0 stringappend_235_0) in + if ((case ((sep_matches_prefix stringappend_236_0)) of + SOME (stringappend_237_0,stringappend_238_0) => + let stringappend_239_0 = (string_drop stringappend_236_0 stringappend_238_0) in + if ((case ((reg_name_matches_prefix stringappend_239_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_240_0,stringappend_241_0) => + let stringappend_242_0 = + (string_drop stringappend_239_0 stringappend_241_0) in + if ((case ((sep_matches_prefix stringappend_242_0)) of + SOME (stringappend_243_0,stringappend_244_0) => + let stringappend_245_0 = + (string_drop stringappend_242_0 stringappend_244_0) in + if ((case ((reg_name_matches_prefix stringappend_245_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_246_0,stringappend_247_0) => + (case ((string_drop stringappend_245_0 stringappend_247_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_229_0) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_228_0,stringappend_229_0) => (stringappend_228_0, stringappend_229_0) + )) in + let stringappend_230_0 = (string_drop stringappend_0_0 stringappend_229_0) in + (case + (case ((spc_matches_prefix stringappend_230_0)) of + SOME (stringappend_231_0,stringappend_232_0) => (stringappend_231_0, stringappend_232_0) + ) of + (() , stringappend_232_0) => + let stringappend_233_0 = (string_drop stringappend_230_0 stringappend_232_0) in + let (rd, stringappend_235_0) = + ((case ((reg_name_matches_prefix stringappend_233_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_234_0,stringappend_235_0) => (stringappend_234_0, stringappend_235_0) + )) in + let stringappend_236_0 = (string_drop stringappend_233_0 stringappend_235_0) in + (case + (case ((sep_matches_prefix stringappend_236_0)) of + SOME (stringappend_237_0,stringappend_238_0) => (stringappend_237_0, stringappend_238_0) + ) of + (() , stringappend_238_0) => + let stringappend_239_0 = (string_drop stringappend_236_0 stringappend_238_0) in + let (rs1, stringappend_241_0) = + ((case ((reg_name_matches_prefix stringappend_239_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_240_0,stringappend_241_0) => (stringappend_240_0, stringappend_241_0) + )) in + let stringappend_242_0 = (string_drop stringappend_239_0 stringappend_241_0) in + (case + (case ((sep_matches_prefix stringappend_242_0)) of + SOME (stringappend_243_0,stringappend_244_0) => (stringappend_243_0, stringappend_244_0) + ) of + (() , stringappend_244_0) => + let stringappend_245_0 = (string_drop stringappend_242_0 stringappend_244_0) in + let (rs2, stringappend_247_0) = + ((case ((reg_name_matches_prefix stringappend_245_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_246_0,stringappend_247_0) => (stringappend_246_0, stringappend_247_0) + )) in + (case ((string_drop stringappend_245_0 stringappend_247_0)) of + s_ => SOME + (RTYPEW (rs2,rs1,rd,op), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if ((case ((mul_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_249_0,stringappend_250_0) => + let stringappend_251_0 = (string_drop stringappend_0_0 stringappend_250_0) in + if ((case ((spc_matches_prefix stringappend_251_0)) of + SOME (stringappend_252_0,stringappend_253_0) => + let stringappend_254_0 = (string_drop stringappend_251_0 stringappend_253_0) in + if ((case ((reg_name_matches_prefix stringappend_254_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_255_0,stringappend_256_0) => + let stringappend_257_0 = (string_drop stringappend_254_0 stringappend_256_0) in + if ((case ((sep_matches_prefix stringappend_257_0)) of + SOME (stringappend_258_0,stringappend_259_0) => + let stringappend_260_0 = (string_drop stringappend_257_0 stringappend_259_0) in + if ((case ((reg_name_matches_prefix stringappend_260_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_261_0,stringappend_262_0) => + let stringappend_263_0 = + (string_drop stringappend_260_0 stringappend_262_0) in + if ((case ((sep_matches_prefix stringappend_263_0)) of + SOME (stringappend_264_0,stringappend_265_0) => + let stringappend_266_0 = + (string_drop stringappend_263_0 stringappend_265_0) in + if ((case ((reg_name_matches_prefix stringappend_266_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_267_0,stringappend_268_0) => + (case ((string_drop stringappend_266_0 stringappend_268_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let ((high, signed1, signed2), stringappend_250_0) = + ((case ((mul_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_249_0,stringappend_250_0) => (stringappend_249_0, stringappend_250_0) + )) in + let stringappend_251_0 = (string_drop stringappend_0_0 stringappend_250_0) in + (case + (case ((spc_matches_prefix stringappend_251_0)) of + SOME (stringappend_252_0,stringappend_253_0) => (stringappend_252_0, stringappend_253_0) + ) of + (() , stringappend_253_0) => + let stringappend_254_0 = (string_drop stringappend_251_0 stringappend_253_0) in + let (rd, stringappend_256_0) = + ((case ((reg_name_matches_prefix stringappend_254_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_255_0,stringappend_256_0) => (stringappend_255_0, stringappend_256_0) + )) in + let stringappend_257_0 = (string_drop stringappend_254_0 stringappend_256_0) in + (case + (case ((sep_matches_prefix stringappend_257_0)) of + SOME (stringappend_258_0,stringappend_259_0) => (stringappend_258_0, stringappend_259_0) + ) of + (() , stringappend_259_0) => + let stringappend_260_0 = (string_drop stringappend_257_0 stringappend_259_0) in + let (rs1, stringappend_262_0) = + ((case ((reg_name_matches_prefix stringappend_260_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_261_0,stringappend_262_0) => (stringappend_261_0, stringappend_262_0) + )) in + let stringappend_263_0 = (string_drop stringappend_260_0 stringappend_262_0) in + (case + (case ((sep_matches_prefix stringappend_263_0)) of + SOME (stringappend_264_0,stringappend_265_0) => (stringappend_264_0, stringappend_265_0) + ) of + (() , stringappend_265_0) => + let stringappend_266_0 = (string_drop stringappend_263_0 stringappend_265_0) in + let (rs2, stringappend_268_0) = + ((case ((reg_name_matches_prefix stringappend_266_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_267_0,stringappend_268_0) => (stringappend_267_0, stringappend_268_0) + )) in + (case ((string_drop stringappend_266_0 stringappend_268_0)) of + s_ => + SOME + (MUL (rs2,rs1,rd,high,signed1,signed2), + ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "div")) /\ (let stringappend_270_0 = (string_drop stringappend_0_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_270_0)) of + SOME (stringappend_271_0,stringappend_272_0) => + let stringappend_273_0 = (string_drop stringappend_270_0 stringappend_272_0) in + if ((case ((spc_matches_prefix stringappend_273_0)) of + SOME (stringappend_274_0,stringappend_275_0) => + let stringappend_276_0 = (string_drop stringappend_273_0 stringappend_275_0) in + if ((case ((reg_name_matches_prefix stringappend_276_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_277_0,stringappend_278_0) => + let stringappend_279_0 = + (string_drop stringappend_276_0 stringappend_278_0) in + if ((case ((sep_matches_prefix stringappend_279_0)) of + SOME (stringappend_280_0,stringappend_281_0) => + let stringappend_282_0 = + (string_drop stringappend_279_0 stringappend_281_0) in + if ((case ((reg_name_matches_prefix stringappend_282_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_283_0,stringappend_284_0) => + let stringappend_285_0 = + (string_drop stringappend_282_0 stringappend_284_0) in + if ((case ((sep_matches_prefix stringappend_285_0)) of + SOME (stringappend_286_0,stringappend_287_0) => + let stringappend_288_0 = + (string_drop stringappend_285_0 stringappend_287_0) in + if ((case ((reg_name_matches_prefix stringappend_288_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_289_0,stringappend_290_0) => + (case ((string_drop stringappend_288_0 stringappend_290_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_270_0 = (string_drop stringappend_0_0 ((string_length "div"))) in + let (s, stringappend_272_0) = + ((case ((maybe_not_u_matches_prefix stringappend_270_0)) of + SOME (stringappend_271_0,stringappend_272_0) => (stringappend_271_0, stringappend_272_0) + )) in + let stringappend_273_0 = (string_drop stringappend_270_0 stringappend_272_0) in + (case + (case ((spc_matches_prefix stringappend_273_0)) of + SOME (stringappend_274_0,stringappend_275_0) => (stringappend_274_0, stringappend_275_0) + ) of + (() , stringappend_275_0) => + let stringappend_276_0 = (string_drop stringappend_273_0 stringappend_275_0) in + let (rd, stringappend_278_0) = + ((case ((reg_name_matches_prefix stringappend_276_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_277_0,stringappend_278_0) => (stringappend_277_0, stringappend_278_0) + )) in + let stringappend_279_0 = (string_drop stringappend_276_0 stringappend_278_0) in + (case + (case ((sep_matches_prefix stringappend_279_0)) of + SOME (stringappend_280_0,stringappend_281_0) => (stringappend_280_0, stringappend_281_0) + ) of + (() , stringappend_281_0) => + let stringappend_282_0 = (string_drop stringappend_279_0 stringappend_281_0) in + let (rs1, stringappend_284_0) = + ((case ((reg_name_matches_prefix stringappend_282_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_283_0,stringappend_284_0) => (stringappend_283_0, stringappend_284_0) + )) in + let stringappend_285_0 = (string_drop stringappend_282_0 stringappend_284_0) in + (case + (case ((sep_matches_prefix stringappend_285_0)) of + SOME (stringappend_286_0,stringappend_287_0) => (stringappend_286_0, stringappend_287_0) + ) of + (() , stringappend_287_0) => + let stringappend_288_0 = (string_drop stringappend_285_0 stringappend_287_0) in + let (rs2, stringappend_290_0) = + ((case ((reg_name_matches_prefix stringappend_288_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_289_0,stringappend_290_0) => (stringappend_289_0, stringappend_290_0) + )) in + (case ((string_drop stringappend_288_0 stringappend_290_0)) of + s_ => SOME + (DIV0 (rs2,rs1,rd,s), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "rem")) /\ (let stringappend_292_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_292_0)) of + SOME (stringappend_293_0,stringappend_294_0) => + let stringappend_295_0 = (string_drop stringappend_292_0 stringappend_294_0) in + if ((case ((spc_matches_prefix stringappend_295_0)) of + SOME (stringappend_296_0,stringappend_297_0) => + let stringappend_298_0 = (string_drop stringappend_295_0 stringappend_297_0) in + if ((case ((reg_name_matches_prefix stringappend_298_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_299_0,stringappend_300_0) => + let stringappend_301_0 = + (string_drop stringappend_298_0 stringappend_300_0) in + if ((case ((sep_matches_prefix stringappend_301_0)) of + SOME (stringappend_302_0,stringappend_303_0) => + let stringappend_304_0 = + (string_drop stringappend_301_0 stringappend_303_0) in + if ((case ((reg_name_matches_prefix stringappend_304_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_305_0,stringappend_306_0) => + let stringappend_307_0 = + (string_drop stringappend_304_0 stringappend_306_0) in + if ((case ((sep_matches_prefix stringappend_307_0)) of + SOME (stringappend_308_0,stringappend_309_0) => + let stringappend_310_0 = + (string_drop stringappend_307_0 stringappend_309_0) in + if ((case ((reg_name_matches_prefix stringappend_310_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_311_0,stringappend_312_0) => + (case ((string_drop stringappend_310_0 stringappend_312_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_292_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in + let (s, stringappend_294_0) = + ((case ((maybe_not_u_matches_prefix stringappend_292_0)) of + SOME (stringappend_293_0,stringappend_294_0) => (stringappend_293_0, stringappend_294_0) + )) in + let stringappend_295_0 = (string_drop stringappend_292_0 stringappend_294_0) in + (case + (case ((spc_matches_prefix stringappend_295_0)) of + SOME (stringappend_296_0,stringappend_297_0) => (stringappend_296_0, stringappend_297_0) + ) of + (() , stringappend_297_0) => + let stringappend_298_0 = (string_drop stringappend_295_0 stringappend_297_0) in + let (rd, stringappend_300_0) = + ((case ((reg_name_matches_prefix stringappend_298_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_299_0,stringappend_300_0) => (stringappend_299_0, stringappend_300_0) + )) in + let stringappend_301_0 = (string_drop stringappend_298_0 stringappend_300_0) in + (case + (case ((sep_matches_prefix stringappend_301_0)) of + SOME (stringappend_302_0,stringappend_303_0) => (stringappend_302_0, stringappend_303_0) + ) of + (() , stringappend_303_0) => + let stringappend_304_0 = (string_drop stringappend_301_0 stringappend_303_0) in + let (rs1, stringappend_306_0) = + ((case ((reg_name_matches_prefix stringappend_304_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_305_0,stringappend_306_0) => (stringappend_305_0, stringappend_306_0) + )) in + let stringappend_307_0 = (string_drop stringappend_304_0 stringappend_306_0) in + (case + (case ((sep_matches_prefix stringappend_307_0)) of + SOME (stringappend_308_0,stringappend_309_0) => (stringappend_308_0, stringappend_309_0) + ) of + (() , stringappend_309_0) => + let stringappend_310_0 = (string_drop stringappend_307_0 stringappend_309_0) in + let (rs2, stringappend_312_0) = + ((case ((reg_name_matches_prefix stringappend_310_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_311_0,stringappend_312_0) => (stringappend_311_0, stringappend_312_0) + )) in + (case ((string_drop stringappend_310_0 stringappend_312_0)) of + s_ => SOME + (REM (rs2,rs1,rd,s), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "mulw")) /\ (let stringappend_314_0 = (string_drop stringappend_0_0 ((string_length "mulw"))) in + if ((case ((spc_matches_prefix stringappend_314_0)) of + SOME (stringappend_315_0,stringappend_316_0) => + let stringappend_317_0 = (string_drop stringappend_314_0 stringappend_316_0) in + if ((case ((reg_name_matches_prefix stringappend_317_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_318_0,stringappend_319_0) => + let stringappend_320_0 = (string_drop stringappend_317_0 stringappend_319_0) in + if ((case ((sep_matches_prefix stringappend_320_0)) of + SOME (stringappend_321_0,stringappend_322_0) => + let stringappend_323_0 = + (string_drop stringappend_320_0 stringappend_322_0) in + if ((case ((reg_name_matches_prefix stringappend_323_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_324_0,stringappend_325_0) => + let stringappend_326_0 = + (string_drop stringappend_323_0 stringappend_325_0) in + if ((case ((sep_matches_prefix stringappend_326_0)) of + SOME (stringappend_327_0,stringappend_328_0) => + let stringappend_329_0 = + (string_drop stringappend_326_0 stringappend_328_0) in + if ((case ((reg_name_matches_prefix stringappend_329_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_330_0,stringappend_331_0) => + (case ((string_drop stringappend_329_0 stringappend_331_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_314_0 = (string_drop stringappend_0_0 ((string_length "mulw"))) in + (case + (case ((spc_matches_prefix stringappend_314_0)) of + SOME (stringappend_315_0,stringappend_316_0) => (stringappend_315_0, stringappend_316_0) + ) of + (() , stringappend_316_0) => + let stringappend_317_0 = (string_drop stringappend_314_0 stringappend_316_0) in + let (rd, stringappend_319_0) = + ((case ((reg_name_matches_prefix stringappend_317_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_318_0,stringappend_319_0) => (stringappend_318_0, stringappend_319_0) + )) in + let stringappend_320_0 = (string_drop stringappend_317_0 stringappend_319_0) in + (case + (case ((sep_matches_prefix stringappend_320_0)) of + SOME (stringappend_321_0,stringappend_322_0) => (stringappend_321_0, stringappend_322_0) + ) of + (() , stringappend_322_0) => + let stringappend_323_0 = (string_drop stringappend_320_0 stringappend_322_0) in + let (rs1, stringappend_325_0) = + ((case ((reg_name_matches_prefix stringappend_323_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_324_0,stringappend_325_0) => (stringappend_324_0, stringappend_325_0) + )) in + let stringappend_326_0 = (string_drop stringappend_323_0 stringappend_325_0) in + (case + (case ((sep_matches_prefix stringappend_326_0)) of + SOME (stringappend_327_0,stringappend_328_0) => (stringappend_327_0, stringappend_328_0) + ) of + (() , stringappend_328_0) => + let stringappend_329_0 = (string_drop stringappend_326_0 stringappend_328_0) in + let (rs2, stringappend_331_0) = + ((case ((reg_name_matches_prefix stringappend_329_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_330_0,stringappend_331_0) => (stringappend_330_0, stringappend_331_0) + )) in + (case ((string_drop stringappend_329_0 stringappend_331_0)) of + s_ => SOME + (MULW (rs2,rs1,rd), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "div")) /\ (let stringappend_333_0 = (string_drop stringappend_0_0 ((string_length "div"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_333_0)) of + SOME (stringappend_334_0,stringappend_335_0) => + let stringappend_336_0 = (string_drop stringappend_333_0 stringappend_335_0) in + if (((((string_startswith stringappend_336_0 "w")) /\ (let stringappend_337_0 = + (string_drop stringappend_336_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_337_0)) of + SOME (stringappend_338_0,stringappend_339_0) => + let stringappend_340_0 = + (string_drop stringappend_337_0 stringappend_339_0) in + if ((case ((reg_name_matches_prefix stringappend_340_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_341_0,stringappend_342_0) => + let stringappend_343_0 = + (string_drop stringappend_340_0 stringappend_342_0) in + if ((case ((sep_matches_prefix stringappend_343_0)) of + SOME (stringappend_344_0,stringappend_345_0) => + let stringappend_346_0 = + (string_drop stringappend_343_0 stringappend_345_0) in + if ((case ((reg_name_matches_prefix stringappend_346_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_347_0,stringappend_348_0) => + let stringappend_349_0 = + (string_drop stringappend_346_0 stringappend_348_0) in + if ((case ((sep_matches_prefix stringappend_349_0)) of + SOME (stringappend_350_0,stringappend_351_0) => + let stringappend_352_0 = + (string_drop stringappend_349_0 + stringappend_351_0) in + if ((case ((reg_name_matches_prefix + stringappend_352_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_353_0,stringappend_354_0) => + (case ((string_drop stringappend_352_0 stringappend_354_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_333_0 = (string_drop stringappend_0_0 ((string_length "div"))) in + let (s, stringappend_335_0) = + ((case ((maybe_not_u_matches_prefix stringappend_333_0)) of + SOME (stringappend_334_0,stringappend_335_0) => (stringappend_334_0, stringappend_335_0) + )) in + let stringappend_336_0 = (string_drop stringappend_333_0 stringappend_335_0) in + let stringappend_337_0 = (string_drop stringappend_336_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_337_0)) of + SOME (stringappend_338_0,stringappend_339_0) => (stringappend_338_0, stringappend_339_0) + ) of + (() , stringappend_339_0) => + let stringappend_340_0 = (string_drop stringappend_337_0 stringappend_339_0) in + let (rd, stringappend_342_0) = + ((case ((reg_name_matches_prefix stringappend_340_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_341_0,stringappend_342_0) => (stringappend_341_0, stringappend_342_0) + )) in + let stringappend_343_0 = (string_drop stringappend_340_0 stringappend_342_0) in + (case + (case ((sep_matches_prefix stringappend_343_0)) of + SOME (stringappend_344_0,stringappend_345_0) => (stringappend_344_0, stringappend_345_0) + ) of + (() , stringappend_345_0) => + let stringappend_346_0 = (string_drop stringappend_343_0 stringappend_345_0) in + let (rs1, stringappend_348_0) = + ((case ((reg_name_matches_prefix stringappend_346_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_347_0,stringappend_348_0) => (stringappend_347_0, stringappend_348_0) + )) in + let stringappend_349_0 = (string_drop stringappend_346_0 stringappend_348_0) in + (case + (case ((sep_matches_prefix stringappend_349_0)) of + SOME (stringappend_350_0,stringappend_351_0) => (stringappend_350_0, stringappend_351_0) + ) of + (() , stringappend_351_0) => + let stringappend_352_0 = (string_drop stringappend_349_0 stringappend_351_0) in + let (rs2, stringappend_354_0) = + ((case ((reg_name_matches_prefix stringappend_352_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_353_0,stringappend_354_0) => (stringappend_353_0, stringappend_354_0) + )) in + (case ((string_drop stringappend_352_0 stringappend_354_0)) of + s_ => SOME + (DIVW (rs2,rs1,rd,s), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "rem")) /\ (let stringappend_356_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in + if ((case ((maybe_not_u_matches_prefix stringappend_356_0)) of + SOME (stringappend_357_0,stringappend_358_0) => + let stringappend_359_0 = (string_drop stringappend_356_0 stringappend_358_0) in + if (((((string_startswith stringappend_359_0 "w")) /\ (let stringappend_360_0 = + (string_drop stringappend_359_0 ((string_length "w"))) in + if ((case ((spc_matches_prefix stringappend_360_0)) of + SOME (stringappend_361_0,stringappend_362_0) => + let stringappend_363_0 = + (string_drop stringappend_360_0 stringappend_362_0) in + if ((case ((reg_name_matches_prefix stringappend_363_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_364_0,stringappend_365_0) => + let stringappend_366_0 = + (string_drop stringappend_363_0 stringappend_365_0) in + if ((case ((sep_matches_prefix stringappend_366_0)) of + SOME (stringappend_367_0,stringappend_368_0) => + let stringappend_369_0 = + (string_drop stringappend_366_0 stringappend_368_0) in + if ((case ((reg_name_matches_prefix stringappend_369_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_370_0,stringappend_371_0) => + let stringappend_372_0 = + (string_drop stringappend_369_0 stringappend_371_0) in + if ((case ((sep_matches_prefix stringappend_372_0)) of + SOME (stringappend_373_0,stringappend_374_0) => + let stringappend_375_0 = + (string_drop stringappend_372_0 + stringappend_374_0) in + if ((case ((reg_name_matches_prefix + stringappend_375_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_376_0,stringappend_377_0) => + (case ((string_drop stringappend_375_0 stringappend_377_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_356_0 = (string_drop stringappend_0_0 ((string_length "rem"))) in + let (s, stringappend_358_0) = + ((case ((maybe_not_u_matches_prefix stringappend_356_0)) of + SOME (stringappend_357_0,stringappend_358_0) => (stringappend_357_0, stringappend_358_0) + )) in + let stringappend_359_0 = (string_drop stringappend_356_0 stringappend_358_0) in + let stringappend_360_0 = (string_drop stringappend_359_0 ((string_length "w"))) in + (case + (case ((spc_matches_prefix stringappend_360_0)) of + SOME (stringappend_361_0,stringappend_362_0) => (stringappend_361_0, stringappend_362_0) + ) of + (() , stringappend_362_0) => + let stringappend_363_0 = (string_drop stringappend_360_0 stringappend_362_0) in + let (rd, stringappend_365_0) = + ((case ((reg_name_matches_prefix stringappend_363_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_364_0,stringappend_365_0) => (stringappend_364_0, stringappend_365_0) + )) in + let stringappend_366_0 = (string_drop stringappend_363_0 stringappend_365_0) in + (case + (case ((sep_matches_prefix stringappend_366_0)) of + SOME (stringappend_367_0,stringappend_368_0) => (stringappend_367_0, stringappend_368_0) + ) of + (() , stringappend_368_0) => + let stringappend_369_0 = (string_drop stringappend_366_0 stringappend_368_0) in + let (rs1, stringappend_371_0) = + ((case ((reg_name_matches_prefix stringappend_369_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_370_0,stringappend_371_0) => (stringappend_370_0, stringappend_371_0) + )) in + let stringappend_372_0 = (string_drop stringappend_369_0 stringappend_371_0) in + (case + (case ((sep_matches_prefix stringappend_372_0)) of + SOME (stringappend_373_0,stringappend_374_0) => (stringappend_373_0, stringappend_374_0) + ) of + (() , stringappend_374_0) => + let stringappend_375_0 = (string_drop stringappend_372_0 stringappend_374_0) in + let (rs2, stringappend_377_0) = + ((case ((reg_name_matches_prefix stringappend_375_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_376_0,stringappend_377_0) => (stringappend_376_0, stringappend_377_0) + )) in + (case ((string_drop stringappend_375_0 stringappend_377_0)) of + s_ => SOME + (REMW (rs2,rs1,rd,s), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "fence")) /\ (let stringappend_379_0 = (string_drop stringappend_0_0 ((string_length "fence"))) in + if ((case ((spc_matches_prefix stringappend_379_0)) of + SOME (stringappend_380_0,stringappend_381_0) => + let stringappend_382_0 = (string_drop stringappend_379_0 stringappend_381_0) in + if ((case ((fence_bits_matches_prefix stringappend_382_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_383_0,stringappend_384_0) => + let stringappend_385_0 = (string_drop stringappend_382_0 stringappend_384_0) in + if ((case ((sep_matches_prefix stringappend_385_0)) of + SOME (stringappend_386_0,stringappend_387_0) => + let stringappend_388_0 = + (string_drop stringappend_385_0 stringappend_387_0) in + if ((case ((fence_bits_matches_prefix stringappend_388_0 + : (( 4 words$word # ii))option)) of + SOME (stringappend_389_0,stringappend_390_0) => + (case ((string_drop stringappend_388_0 stringappend_390_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_379_0 = (string_drop stringappend_0_0 ((string_length "fence"))) in + (case + (case ((spc_matches_prefix stringappend_379_0)) of + SOME (stringappend_380_0,stringappend_381_0) => (stringappend_380_0, stringappend_381_0) + ) of + (() , stringappend_381_0) => + let stringappend_382_0 = (string_drop stringappend_379_0 stringappend_381_0) in + let (pred, stringappend_384_0) = + ((case ((fence_bits_matches_prefix stringappend_382_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_383_0,stringappend_384_0) => (stringappend_383_0, stringappend_384_0) + )) in + let stringappend_385_0 = (string_drop stringappend_382_0 stringappend_384_0) in + (case + (case ((sep_matches_prefix stringappend_385_0)) of + SOME (stringappend_386_0,stringappend_387_0) => (stringappend_386_0, stringappend_387_0) + ) of + (() , stringappend_387_0) => + let stringappend_388_0 = (string_drop stringappend_385_0 stringappend_387_0) in + let (succ, stringappend_390_0) = + ((case ((fence_bits_matches_prefix stringappend_388_0 : (( 4 words$word # ii)) option)) of + SOME (stringappend_389_0,stringappend_390_0) => (stringappend_389_0, stringappend_390_0) + )) in + (case ((string_drop stringappend_388_0 stringappend_390_0)) of + s_ => SOME + (FENCE (pred,succ), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "fence.i")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "fence.i")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "fence.i")))) of + s_ => SOME (FENCEI () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "ecall")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "ecall")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "ecall")))) of + s_ => SOME (ECALL () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "mret")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "mret")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "mret")))) of + s_ => SOME (MRET () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "sret")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "sret")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "sret")))) of + s_ => SOME (SRET () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "ebreak")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "ebreak")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "ebreak")))) of + s_ => SOME (EBREAK () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "wfi")) /\ ( + (case ((string_drop stringappend_0_0 ((string_length "wfi")))) of + s_ => T + ))))) then + (case ((string_drop stringappend_0_0 ((string_length "wfi")))) of + s_ => SOME (WFI () , ((string_length arg_)) - ((string_length s_))) + ) + else if (((((string_startswith stringappend_0_0 "sfence.vma")) /\ (let stringappend_398_0 = (string_drop stringappend_0_0 ((string_length "sfence.vma"))) in + if ((case ((spc_matches_prefix stringappend_398_0)) of + SOME (stringappend_399_0,stringappend_400_0) => + let stringappend_401_0 = (string_drop stringappend_398_0 stringappend_400_0) in + if ((case ((reg_name_matches_prefix stringappend_401_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_402_0,stringappend_403_0) => + let stringappend_404_0 = (string_drop stringappend_401_0 stringappend_403_0) in + if ((case ((sep_matches_prefix stringappend_404_0)) of + SOME (stringappend_405_0,stringappend_406_0) => + let stringappend_407_0 = + (string_drop stringappend_404_0 stringappend_406_0) in + if ((case ((reg_name_matches_prefix stringappend_407_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_408_0,stringappend_409_0) => + (case ((string_drop stringappend_407_0 stringappend_409_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_398_0 = (string_drop stringappend_0_0 ((string_length "sfence.vma"))) in + (case + (case ((spc_matches_prefix stringappend_398_0)) of + SOME (stringappend_399_0,stringappend_400_0) => (stringappend_399_0, stringappend_400_0) + ) of + (() , stringappend_400_0) => + let stringappend_401_0 = (string_drop stringappend_398_0 stringappend_400_0) in + let (rs1, stringappend_403_0) = + ((case ((reg_name_matches_prefix stringappend_401_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_402_0,stringappend_403_0) => (stringappend_402_0, stringappend_403_0) + )) in + let stringappend_404_0 = (string_drop stringappend_401_0 stringappend_403_0) in + (case + (case ((sep_matches_prefix stringappend_404_0)) of + SOME (stringappend_405_0,stringappend_406_0) => (stringappend_405_0, stringappend_406_0) + ) of + (() , stringappend_406_0) => + let stringappend_407_0 = (string_drop stringappend_404_0 stringappend_406_0) in + let (rs2, stringappend_409_0) = + ((case ((reg_name_matches_prefix stringappend_407_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_408_0,stringappend_409_0) => (stringappend_408_0, stringappend_409_0) + )) in + (case ((string_drop stringappend_407_0 stringappend_409_0)) of + s_ => SOME + (SFENCE_VMA (rs1,rs2), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "lr.")) /\ (let stringappend_411_0 = (string_drop stringappend_0_0 ((string_length "lr."))) in + if ((case ((maybe_aq_matches_prefix stringappend_411_0)) of + SOME (stringappend_412_0,stringappend_413_0) => + let stringappend_414_0 = (string_drop stringappend_411_0 stringappend_413_0) in + if ((case ((maybe_rl_matches_prefix stringappend_414_0)) of + SOME (stringappend_415_0,stringappend_416_0) => + let stringappend_417_0 = (string_drop stringappend_414_0 stringappend_416_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_417_0)) of + SOME (stringappend_418_0,stringappend_419_0) => + let stringappend_420_0 = + (string_drop stringappend_417_0 stringappend_419_0) in + if ((case ((spc_matches_prefix stringappend_420_0)) of + SOME (stringappend_421_0,stringappend_422_0) => + let stringappend_423_0 = + (string_drop stringappend_420_0 stringappend_422_0) in + if ((case ((reg_name_matches_prefix stringappend_423_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_424_0,stringappend_425_0) => + let stringappend_426_0 = + (string_drop stringappend_423_0 stringappend_425_0) in + if ((case ((sep_matches_prefix stringappend_426_0)) of + SOME (stringappend_427_0,stringappend_428_0) => + let stringappend_429_0 = + (string_drop stringappend_426_0 stringappend_428_0) in + if ((case ((reg_name_matches_prefix stringappend_429_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_430_0,stringappend_431_0) => + (case ((string_drop stringappend_429_0 stringappend_431_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_411_0 = (string_drop stringappend_0_0 ((string_length "lr."))) in + let (aq, stringappend_413_0) = + ((case ((maybe_aq_matches_prefix stringappend_411_0)) of + SOME (stringappend_412_0,stringappend_413_0) => (stringappend_412_0, stringappend_413_0) + )) in + let stringappend_414_0 = (string_drop stringappend_411_0 stringappend_413_0) in + let (rl, stringappend_416_0) = + ((case ((maybe_rl_matches_prefix stringappend_414_0)) of + SOME (stringappend_415_0,stringappend_416_0) => (stringappend_415_0, stringappend_416_0) + )) in + let stringappend_417_0 = (string_drop stringappend_414_0 stringappend_416_0) in + let (size1, stringappend_419_0) = + ((case ((size_mnemonic_matches_prefix stringappend_417_0)) of + SOME (stringappend_418_0,stringappend_419_0) => (stringappend_418_0, stringappend_419_0) + )) in + let stringappend_420_0 = (string_drop stringappend_417_0 stringappend_419_0) in + (case + (case ((spc_matches_prefix stringappend_420_0)) of + SOME (stringappend_421_0,stringappend_422_0) => (stringappend_421_0, stringappend_422_0) + ) of + (() , stringappend_422_0) => + let stringappend_423_0 = (string_drop stringappend_420_0 stringappend_422_0) in + let (rd, stringappend_425_0) = + ((case ((reg_name_matches_prefix stringappend_423_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_424_0,stringappend_425_0) => (stringappend_424_0, stringappend_425_0) + )) in + let stringappend_426_0 = (string_drop stringappend_423_0 stringappend_425_0) in + (case + (case ((sep_matches_prefix stringappend_426_0)) of + SOME (stringappend_427_0,stringappend_428_0) => (stringappend_427_0, stringappend_428_0) + ) of + (() , stringappend_428_0) => + let stringappend_429_0 = (string_drop stringappend_426_0 stringappend_428_0) in + let (rs1, stringappend_431_0) = + ((case ((reg_name_matches_prefix stringappend_429_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_430_0,stringappend_431_0) => (stringappend_430_0, stringappend_431_0) + )) in + (case ((string_drop stringappend_429_0 stringappend_431_0)) of + s_ => + SOME + (LOADRES (aq,rl,rs1,size1,rd), ((string_length arg_)) - + ((string_length s_))) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "sc.")) /\ (let stringappend_433_0 = (string_drop stringappend_0_0 ((string_length "sc."))) in + if ((case ((maybe_aq_matches_prefix stringappend_433_0)) of + SOME (stringappend_434_0,stringappend_435_0) => + let stringappend_436_0 = (string_drop stringappend_433_0 stringappend_435_0) in + if ((case ((maybe_rl_matches_prefix stringappend_436_0)) of + SOME (stringappend_437_0,stringappend_438_0) => + let stringappend_439_0 = (string_drop stringappend_436_0 stringappend_438_0) in + if ((case ((size_mnemonic_matches_prefix stringappend_439_0)) of + SOME (stringappend_440_0,stringappend_441_0) => + let stringappend_442_0 = + (string_drop stringappend_439_0 stringappend_441_0) in + if ((case ((spc_matches_prefix stringappend_442_0)) of + SOME (stringappend_443_0,stringappend_444_0) => + let stringappend_445_0 = + (string_drop stringappend_442_0 stringappend_444_0) in + if ((case ((reg_name_matches_prefix stringappend_445_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_446_0,stringappend_447_0) => + let stringappend_448_0 = + (string_drop stringappend_445_0 stringappend_447_0) in + if ((case ((sep_matches_prefix stringappend_448_0)) of + SOME (stringappend_449_0,stringappend_450_0) => + let stringappend_451_0 = + (string_drop stringappend_448_0 stringappend_450_0) in + if ((case ((reg_name_matches_prefix stringappend_451_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_452_0,stringappend_453_0) => + let stringappend_454_0 = + (string_drop stringappend_451_0 + stringappend_453_0) in + if ((case ((sep_matches_prefix stringappend_454_0)) of + SOME (stringappend_455_0,stringappend_456_0) => + let stringappend_457_0 = + (string_drop stringappend_454_0 + stringappend_456_0) in + if ((case ((reg_name_matches_prefix + stringappend_457_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_458_0,stringappend_459_0) => + (case ((string_drop stringappend_457_0 stringappend_459_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_433_0 = (string_drop stringappend_0_0 ((string_length "sc."))) in + let (aq, stringappend_435_0) = + ((case ((maybe_aq_matches_prefix stringappend_433_0)) of + SOME (stringappend_434_0,stringappend_435_0) => (stringappend_434_0, stringappend_435_0) + )) in + let stringappend_436_0 = (string_drop stringappend_433_0 stringappend_435_0) in + let (rl, stringappend_438_0) = + ((case ((maybe_rl_matches_prefix stringappend_436_0)) of + SOME (stringappend_437_0,stringappend_438_0) => (stringappend_437_0, stringappend_438_0) + )) in + let stringappend_439_0 = (string_drop stringappend_436_0 stringappend_438_0) in + let (size1, stringappend_441_0) = + ((case ((size_mnemonic_matches_prefix stringappend_439_0)) of + SOME (stringappend_440_0,stringappend_441_0) => (stringappend_440_0, stringappend_441_0) + )) in + let stringappend_442_0 = (string_drop stringappend_439_0 stringappend_441_0) in + (case + (case ((spc_matches_prefix stringappend_442_0)) of + SOME (stringappend_443_0,stringappend_444_0) => (stringappend_443_0, stringappend_444_0) + ) of + (() , stringappend_444_0) => + let stringappend_445_0 = (string_drop stringappend_442_0 stringappend_444_0) in + let (rd, stringappend_447_0) = + ((case ((reg_name_matches_prefix stringappend_445_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_446_0,stringappend_447_0) => (stringappend_446_0, stringappend_447_0) + )) in + let stringappend_448_0 = (string_drop stringappend_445_0 stringappend_447_0) in + (case + (case ((sep_matches_prefix stringappend_448_0)) of + SOME (stringappend_449_0,stringappend_450_0) => (stringappend_449_0, stringappend_450_0) + ) of + (() , stringappend_450_0) => + let stringappend_451_0 = (string_drop stringappend_448_0 stringappend_450_0) in + let (rs1, stringappend_453_0) = + ((case ((reg_name_matches_prefix stringappend_451_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_452_0,stringappend_453_0) => (stringappend_452_0, stringappend_453_0) + )) in + let stringappend_454_0 = (string_drop stringappend_451_0 stringappend_453_0) in + (case + (case ((sep_matches_prefix stringappend_454_0)) of + SOME (stringappend_455_0,stringappend_456_0) => (stringappend_455_0, stringappend_456_0) + ) of + (() , stringappend_456_0) => + let stringappend_457_0 = (string_drop stringappend_454_0 stringappend_456_0) in + let (rs2, stringappend_459_0) = + ((case ((reg_name_matches_prefix stringappend_457_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_458_0,stringappend_459_0) => (stringappend_458_0, stringappend_459_0) + )) in + (case ((string_drop stringappend_457_0 stringappend_459_0)) of + s_ => + SOME + (STORECON (aq,rl,rs2,rs1,size1,rd), + ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if ((case ((amo_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_461_0,stringappend_462_0) => + let stringappend_463_0 = (string_drop stringappend_0_0 stringappend_462_0) in + if (((((string_startswith stringappend_463_0 ".")) /\ (let stringappend_464_0 = (string_drop stringappend_463_0 ((string_length "."))) in + if ((case ((size_mnemonic_matches_prefix stringappend_464_0)) of + SOME (stringappend_465_0,stringappend_466_0) => + let stringappend_467_0 = (string_drop stringappend_464_0 stringappend_466_0) in + if ((case ((maybe_aq_matches_prefix stringappend_467_0)) of + SOME (stringappend_468_0,stringappend_469_0) => + let stringappend_470_0 = (string_drop stringappend_467_0 stringappend_469_0) in + if ((case ((maybe_rl_matches_prefix stringappend_470_0)) of + SOME (stringappend_471_0,stringappend_472_0) => + let stringappend_473_0 = + (string_drop stringappend_470_0 stringappend_472_0) in + if ((case ((spc_matches_prefix stringappend_473_0)) of + SOME (stringappend_474_0,stringappend_475_0) => + let stringappend_476_0 = + (string_drop stringappend_473_0 stringappend_475_0) in + if ((case ((reg_name_matches_prefix stringappend_476_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_477_0,stringappend_478_0) => + let stringappend_479_0 = + (string_drop stringappend_476_0 stringappend_478_0) in + if ((case ((sep_matches_prefix stringappend_479_0)) of + SOME (stringappend_480_0,stringappend_481_0) => + let stringappend_482_0 = + (string_drop stringappend_479_0 stringappend_481_0) in + if ((case ((reg_name_matches_prefix stringappend_482_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_483_0,stringappend_484_0) => + let stringappend_485_0 = + (string_drop stringappend_482_0 + stringappend_484_0) in + if ((case ((sep_matches_prefix stringappend_485_0)) of + SOME (stringappend_486_0,stringappend_487_0) => + let stringappend_488_0 = + (string_drop stringappend_485_0 + stringappend_487_0) in + if ((case ((reg_name_matches_prefix + stringappend_488_0 + : (( 5 words$word # ii))option)) of + SOME + (stringappend_489_0,stringappend_490_0) => + (case ((string_drop stringappend_488_0 stringappend_490_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_462_0) = + ((case ((amo_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_461_0,stringappend_462_0) => (stringappend_461_0, stringappend_462_0) + )) in + let stringappend_463_0 = (string_drop stringappend_0_0 stringappend_462_0) in + let stringappend_464_0 = (string_drop stringappend_463_0 ((string_length "."))) in + let (width, stringappend_466_0) = + ((case ((size_mnemonic_matches_prefix stringappend_464_0)) of + SOME (stringappend_465_0,stringappend_466_0) => (stringappend_465_0, stringappend_466_0) + )) in + let stringappend_467_0 = (string_drop stringappend_464_0 stringappend_466_0) in + let (aq, stringappend_469_0) = + ((case ((maybe_aq_matches_prefix stringappend_467_0)) of + SOME (stringappend_468_0,stringappend_469_0) => (stringappend_468_0, stringappend_469_0) + )) in + let stringappend_470_0 = (string_drop stringappend_467_0 stringappend_469_0) in + let (rl, stringappend_472_0) = + ((case ((maybe_rl_matches_prefix stringappend_470_0)) of + SOME (stringappend_471_0,stringappend_472_0) => (stringappend_471_0, stringappend_472_0) + )) in + let stringappend_473_0 = (string_drop stringappend_470_0 stringappend_472_0) in + (case + (case ((spc_matches_prefix stringappend_473_0)) of + SOME (stringappend_474_0,stringappend_475_0) => (stringappend_474_0, stringappend_475_0) + ) of + (() , stringappend_475_0) => + let stringappend_476_0 = (string_drop stringappend_473_0 stringappend_475_0) in + let (rd, stringappend_478_0) = + ((case ((reg_name_matches_prefix stringappend_476_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_477_0,stringappend_478_0) => (stringappend_477_0, stringappend_478_0) + )) in + let stringappend_479_0 = (string_drop stringappend_476_0 stringappend_478_0) in + (case + (case ((sep_matches_prefix stringappend_479_0)) of + SOME (stringappend_480_0,stringappend_481_0) => (stringappend_480_0, stringappend_481_0) + ) of + (() , stringappend_481_0) => + let stringappend_482_0 = (string_drop stringappend_479_0 stringappend_481_0) in + let (rs1, stringappend_484_0) = + ((case ((reg_name_matches_prefix stringappend_482_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_483_0,stringappend_484_0) => (stringappend_483_0, stringappend_484_0) + )) in + let stringappend_485_0 = (string_drop stringappend_482_0 stringappend_484_0) in + (case + (case ((sep_matches_prefix stringappend_485_0)) of + SOME (stringappend_486_0,stringappend_487_0) => (stringappend_486_0, stringappend_487_0) + ) of + (() , stringappend_487_0) => + let stringappend_488_0 = (string_drop stringappend_485_0 stringappend_487_0) in + let (rs2, stringappend_490_0) = + ((case ((reg_name_matches_prefix stringappend_488_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_489_0,stringappend_490_0) => (stringappend_489_0, stringappend_490_0) + )) in + (case ((string_drop stringappend_488_0 stringappend_490_0)) of + s_ => + SOME + (AMO (op,aq,rl,rs2,rs1,width,rd), + ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_492_0,stringappend_493_0) => + let stringappend_494_0 = (string_drop stringappend_0_0 stringappend_493_0) in + if (((((string_startswith stringappend_494_0 "i")) /\ (let stringappend_495_0 = (string_drop stringappend_494_0 ((string_length "i"))) in + if ((case ((spc_matches_prefix stringappend_495_0)) of + SOME (stringappend_496_0,stringappend_497_0) => + let stringappend_498_0 = (string_drop stringappend_495_0 stringappend_497_0) in + if ((case ((reg_name_matches_prefix stringappend_498_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_499_0,stringappend_500_0) => + let stringappend_501_0 = (string_drop stringappend_498_0 stringappend_500_0) in + if ((case ((sep_matches_prefix stringappend_501_0)) of + SOME (stringappend_502_0,stringappend_503_0) => + let stringappend_504_0 = + (string_drop stringappend_501_0 stringappend_503_0) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_504_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_505_0,stringappend_506_0) => + let stringappend_507_0 = + (string_drop stringappend_504_0 stringappend_506_0) in + if ((case ((sep_matches_prefix stringappend_507_0)) of + SOME (stringappend_508_0,stringappend_509_0) => + let stringappend_510_0 = + (string_drop stringappend_507_0 stringappend_509_0) in + if ((case ((csr_name_map_matches_prefix stringappend_510_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_511_0,stringappend_512_0) => + (case ((string_drop stringappend_510_0 stringappend_512_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + T + else F + | NONE => F + )) then + let (op, stringappend_493_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_492_0,stringappend_493_0) => (stringappend_492_0, stringappend_493_0) + )) in + let stringappend_494_0 = (string_drop stringappend_0_0 stringappend_493_0) in + let stringappend_495_0 = (string_drop stringappend_494_0 ((string_length "i"))) in + (case + (case ((spc_matches_prefix stringappend_495_0)) of + SOME (stringappend_496_0,stringappend_497_0) => (stringappend_496_0, stringappend_497_0) + ) of + (() , stringappend_497_0) => + let stringappend_498_0 = (string_drop stringappend_495_0 stringappend_497_0) in + let (rd, stringappend_500_0) = + ((case ((reg_name_matches_prefix stringappend_498_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_499_0,stringappend_500_0) => (stringappend_499_0, stringappend_500_0) + )) in + let stringappend_501_0 = (string_drop stringappend_498_0 stringappend_500_0) in + (case + (case ((sep_matches_prefix stringappend_501_0)) of + SOME (stringappend_502_0,stringappend_503_0) => (stringappend_502_0, stringappend_503_0) + ) of + (() , stringappend_503_0) => + let stringappend_504_0 = (string_drop stringappend_501_0 stringappend_503_0) in + let (rs1, stringappend_506_0) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_504_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_505_0,stringappend_506_0) => (stringappend_505_0, stringappend_506_0) + )) in + let stringappend_507_0 = (string_drop stringappend_504_0 stringappend_506_0) in + (case + (case ((sep_matches_prefix stringappend_507_0)) of + SOME (stringappend_508_0,stringappend_509_0) => (stringappend_508_0, stringappend_509_0) + ) of + (() , stringappend_509_0) => + let stringappend_510_0 = (string_drop stringappend_507_0 stringappend_509_0) in + let (csr, stringappend_512_0) = + ((case ((csr_name_map_matches_prefix stringappend_510_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_511_0,stringappend_512_0) => (stringappend_511_0, stringappend_512_0) + )) in + (case ((string_drop stringappend_510_0 stringappend_512_0)) of + s_ => + SOME (CSR (csr,rs1,rd,T,op), ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_514_0,stringappend_515_0) => + let stringappend_516_0 = (string_drop stringappend_0_0 stringappend_515_0) in + if ((case ((spc_matches_prefix stringappend_516_0)) of + SOME (stringappend_517_0,stringappend_518_0) => + let stringappend_519_0 = (string_drop stringappend_516_0 stringappend_518_0) in + if ((case ((reg_name_matches_prefix stringappend_519_0 : (( 5 words$word # ii))option)) of + SOME (stringappend_520_0,stringappend_521_0) => + let stringappend_522_0 = (string_drop stringappend_519_0 stringappend_521_0) in + if ((case ((sep_matches_prefix stringappend_522_0)) of + SOME (stringappend_523_0,stringappend_524_0) => + let stringappend_525_0 = (string_drop stringappend_522_0 stringappend_524_0) in + if ((case ((reg_name_matches_prefix stringappend_525_0 + : (( 5 words$word # ii))option)) of + SOME (stringappend_526_0,stringappend_527_0) => + let stringappend_528_0 = + (string_drop stringappend_525_0 stringappend_527_0) in + if ((case ((sep_matches_prefix stringappend_528_0)) of + SOME (stringappend_529_0,stringappend_530_0) => + let stringappend_531_0 = + (string_drop stringappend_528_0 stringappend_530_0) in + if ((case ((csr_name_map_matches_prefix stringappend_531_0 + : (( 12 words$word # ii))option)) of + SOME (stringappend_532_0,stringappend_533_0) => + (case ((string_drop stringappend_531_0 stringappend_533_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F + | NONE => F + )) then + let (op, stringappend_515_0) = + ((case ((csr_mnemonic_matches_prefix stringappend_0_0)) of + SOME (stringappend_514_0,stringappend_515_0) => (stringappend_514_0, stringappend_515_0) + )) in + let stringappend_516_0 = (string_drop stringappend_0_0 stringappend_515_0) in + (case + (case ((spc_matches_prefix stringappend_516_0)) of + SOME (stringappend_517_0,stringappend_518_0) => (stringappend_517_0, stringappend_518_0) + ) of + (() , stringappend_518_0) => + let stringappend_519_0 = (string_drop stringappend_516_0 stringappend_518_0) in + let (rd, stringappend_521_0) = + ((case ((reg_name_matches_prefix stringappend_519_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_520_0,stringappend_521_0) => (stringappend_520_0, stringappend_521_0) + )) in + let stringappend_522_0 = (string_drop stringappend_519_0 stringappend_521_0) in + (case + (case ((sep_matches_prefix stringappend_522_0)) of + SOME (stringappend_523_0,stringappend_524_0) => (stringappend_523_0, stringappend_524_0) + ) of + (() , stringappend_524_0) => + let stringappend_525_0 = (string_drop stringappend_522_0 stringappend_524_0) in + let (rs1, stringappend_527_0) = + ((case ((reg_name_matches_prefix stringappend_525_0 : (( 5 words$word # ii)) option)) of + SOME (stringappend_526_0,stringappend_527_0) => (stringappend_526_0, stringappend_527_0) + )) in + let stringappend_528_0 = (string_drop stringappend_525_0 stringappend_527_0) in + (case + (case ((sep_matches_prefix stringappend_528_0)) of + SOME (stringappend_529_0,stringappend_530_0) => (stringappend_529_0, stringappend_530_0) + ) of + (() , stringappend_530_0) => + let stringappend_531_0 = (string_drop stringappend_528_0 stringappend_530_0) in + let (csr, stringappend_533_0) = + ((case ((csr_name_map_matches_prefix stringappend_531_0 : (( 12 words$word # ii)) option)) of + SOME (stringappend_532_0,stringappend_533_0) => (stringappend_532_0, stringappend_533_0) + )) in + (case ((string_drop stringappend_531_0 stringappend_533_0)) of + s_ => + SOME (CSR (csr,rs1,rd,F,op), ((string_length arg_)) - ((string_length s_))) + ) + ) + ) + ) + else if (((((string_startswith stringappend_0_0 "illegal")) /\ (let stringappend_535_0 = (string_drop stringappend_0_0 ((string_length "illegal"))) in + if ((case ((spc_matches_prefix stringappend_535_0)) of + SOME (stringappend_536_0,stringappend_537_0) => + let stringappend_538_0 = (string_drop stringappend_535_0 stringappend_537_0) in + if ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_538_0 + : (( 32 words$word # ii))option)) of + SOME (stringappend_539_0,stringappend_540_0) => + (case ((string_drop stringappend_538_0 stringappend_540_0)) of s_ => T ) + | NONE => F + )) then + T + else F + | NONE => F + )) then + T + else F)))) then + let stringappend_535_0 = (string_drop stringappend_0_0 ((string_length "illegal"))) in + (case + (case ((spc_matches_prefix stringappend_535_0)) of + SOME (stringappend_536_0,stringappend_537_0) => (stringappend_536_0, stringappend_537_0) + ) of + (() , stringappend_537_0) => + let stringappend_538_0 = (string_drop stringappend_535_0 stringappend_537_0) in + let (s, stringappend_540_0) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_538_0 : (( 32 words$word # ii)) option)) of + SOME (stringappend_539_0,stringappend_540_0) => (stringappend_539_0, stringappend_540_0) + )) in + (case ((string_drop stringappend_538_0 stringappend_540_0)) of + s_ => SOME (ILLEGAL s, ((string_length arg_)) - ((string_length s_))) + ) + ) + else NONE))`; + + +(*val encdec_forwards : ast -> mword ty32*) + +val _ = Define ` + ((encdec_forwards:ast ->(32)words$word) arg_= + ((case arg_ of + UTYPE (imm,rd,op) => + (concat_vec imm ((concat_vec rd ((encdec_uop_forwards op : 7 words$word)) : 12 words$word)) + : 32 words$word) + | RISCV_JAL (v__172,rd) => + let (imm_19 : 1 bits) = ((subrange_vec_dec v__172 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in + let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__172 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in + let (imm_8 : 1 bits) = ((subrange_vec_dec v__172 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in + let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__172 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in + let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__172 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in + (concat_vec imm_19 + ((concat_vec imm_18_13 + ((concat_vec imm_12_9 + ((concat_vec imm_8 + ((concat_vec imm_7_0 + ((concat_vec rd (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 20 words$word)) + : 21 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word) + | RISCV_JALR (imm,rs1,rd) => + (concat_vec imm + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | BTYPE (v__173,rs2,rs1,op) => + let (imm7_6 : 1 bits) = ((subrange_vec_dec v__173 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (imm5_0 : 1 bits) = ((subrange_vec_dec v__173 (( 11 : int):ii) (( 11 : int):ii) : 1 words$word)) in + let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__173 (( 10 : int):ii) (( 5 : int):ii) : 6 words$word)) in + let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__173 (( 4 : int):ii) (( 1 : int):ii) : 4 words$word)) in + (concat_vec imm7_6 + ((concat_vec imm7_5_0 + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec ((encdec_bop_forwards op : 3 words$word)) + ((concat_vec imm5_4_1 + ((concat_vec imm5_0 (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word) + : 8 words$word)) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 31 words$word)) + : 32 words$word) + | ITYPE (imm,rs1,rd,op) => + (concat_vec imm + ((concat_vec rs1 + ((concat_vec ((encdec_iop_forwards op : 3 words$word)) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 26 words$word)) + : 32 words$word) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 26 words$word)) + : 32 words$word) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 26 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_ADD) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SUB) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SLL) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SLT) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B1;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_XOR) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SRL) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_SRA) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_OR) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B1;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPE (rs2,rs1,rd,RISCV_AND) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B1;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | LOAD (imm,rs1,rd,is_unsigned,size1,F,F) => + (concat_vec imm + ((concat_vec rs1 + ((concat_vec ((bool_bits_forwards is_unsigned : 1 words$word)) + ((concat_vec ((size_bits_forwards size1 : 2 words$word)) + ((concat_vec rd (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | STORE (v__174,rs2,rs1,size1,F,F) => + let (imm7 : 7 bits) = ((subrange_vec_dec v__174 (( 11 : int):ii) (( 5 : int):ii) : 7 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__174 (( 4 : int):ii) (( 0 : int):ii) : 5 words$word)) in + (concat_vec imm7 + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec ((size_bits_forwards size1 : 2 words$word)) + ((concat_vec imm5 (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | ADDIW (imm,rs1,rd) => + (concat_vec imm + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => + (concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0;B1] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec ((encdec_mul_op_forwards high signed1 signed2 : 3 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | DIV0 (rs2,rs1,rd,s) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0] : 2 words$word) + ((concat_vec ((bool_not_bits_forwards s : 1 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 13 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | REM (rs2,rs1,rd,s) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B1] : 2 words$word) + ((concat_vec ((bool_not_bits_forwards s : 1 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 13 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | MULW (rs2,rs1,rd) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | DIVW (rs2,rs1,rd,s) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B0] : 2 words$word) + ((concat_vec ((bool_not_bits_forwards s : 1 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 13 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | REMW (rs2,rs1,rd,s) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1;B1] : 2 words$word) + ((concat_vec ((bool_not_bits_forwards s : 1 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 13 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | FENCE (pred,succ) => + (concat_vec (vec_of_bits [B0;B0;B0;B0] : 4 words$word) + ((concat_vec pred + ((concat_vec succ + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 24 words$word)) + : 28 words$word)) + : 32 words$word) + | FENCEI (() ) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B1] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | ECALL (() ) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | MRET (() ) => + (concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | SRET (() ) => + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | EBREAK (() ) => + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | WFI (() ) => + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | SFENCE_VMA (rs1,rs2) => + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0;B0;B0] : 3 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) + : 12 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 32 words$word) + | LOADRES (aq,rl,rs1,size1,rd) => + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word) + ((concat_vec ((bool_bits_forwards aq : 1 words$word)) + ((concat_vec ((bool_bits_forwards rl : 1 words$word)) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word) + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec ((size_bits_forwards size1 : 2 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 26 words$word)) + : 27 words$word)) + : 32 words$word) + | STORECON (aq,rl,rs2,rs1,size1,rd) => + (concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word) + ((concat_vec ((bool_bits_forwards aq : 1 words$word)) + ((concat_vec ((bool_bits_forwards rl : 1 words$word)) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec ((size_bits_forwards size1 : 2 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 26 words$word)) + : 27 words$word)) + : 32 words$word) + | AMO (op,aq,rl,rs2,rs1,size1,rd) => + (concat_vec ((encdec_amoop_forwards op : 5 words$word)) + ((concat_vec ((bool_bits_forwards aq : 1 words$word)) + ((concat_vec ((bool_bits_forwards rl : 1 words$word)) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec ((size_bits_forwards size1 : 2 words$word)) + ((concat_vec rd (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word) + : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 25 words$word)) + : 26 words$word)) + : 27 words$word)) + : 32 words$word) | CSR (csr,rs1,rd,is_imm,op) => - let (insn : string) = - ((case (op, is_imm) of - (CSRRW, T) => "csrrwi " - | (CSRRW, F) => "csrrw " - | (CSRRS, T) => "csrrsi " - | (CSRRS, F) => "csrrs " - | (CSRRC, T) => "csrrci " - | (CSRRC, F) => "csrrc " - )) in - let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in - STRCAT insn - ((STRCAT ((reg_name_abi rd)) - ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr)))))))))) - | NOP (g__99) => "nop" - | ILLEGAL (g__100) => "illegal" + (concat_vec csr + ((concat_vec rs1 + ((concat_vec ((bool_bits_forwards is_imm : 1 words$word)) + ((concat_vec ((encdec_csrop_forwards op : 2 words$word)) + ((concat_vec rd (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word) : 12 words$word)) + : 14 words$word)) + : 15 words$word)) + : 20 words$word)) + : 32 words$word) + | STOP_FETCHING (() ) => + (concat_vec (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec (vec_of_bits [B0;B0] : 2 words$word) + ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word) + (vec_of_bits [B1;B1] : 2 words$word) + : 5 words$word)) + : 7 words$word)) + : 8 words$word)) + : 16 words$word)) + : 32 words$word) + | THREAD_START (() ) => + (concat_vec (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word) + ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word) + ((concat_vec (vec_of_bits [B0] : 1 words$word) + ((concat_vec (vec_of_bits [B0;B0] : 2 words$word) + ((concat_vec (vec_of_bits [B0;B1;B0] : 3 words$word) + (vec_of_bits [B1;B1] : 2 words$word) + : 5 words$word)) + : 7 words$word)) + : 8 words$word)) + : 16 words$word)) + : 32 words$word) + | ILLEGAL (s) => s + )))`; + + +(*val encdec_backwards : mword ty32 -> ast*) + +val _ = Define ` + ((encdec_backwards:(32)words$word -> ast) arg_= + (let v__175 = arg_ in + if (let mappingpatterns_23_0 = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + encdec_uop_backwards_matches mappingpatterns_23_0) then + let (imm : 20 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 12 : int):ii) : 20 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let mappingpatterns_23_0 = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + let op = (encdec_uop_backwards mappingpatterns_23_0) in + UTYPE (imm,rd,op) + else if (let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (p0_ = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word))) then + let (imm_19 : 1 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in + let (imm_18_13 : 6 bits) = ((subrange_vec_dec v__175 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in + let (imm_12_9 : 4 bits) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 21 : int):ii) : 4 words$word)) in + let (imm_8 : 1 bits) = ((subrange_vec_dec v__175 (( 20 : int):ii) (( 20 : int):ii) : 1 words$word)) in + let (imm_7_0 : 8 bits) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 12 : int):ii) : 8 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RISCV_JAL ((concat_vec imm_19 + ((concat_vec imm_7_0 + ((concat_vec imm_8 + ((concat_vec imm_18_13 + ((concat_vec imm_12_9 (vec_of_bits [B0] : 1 words$word) : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 20 words$word)) + : 21 words$word),rd) + else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((p1_ = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))))) then + let (imm : 12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RISCV_JALR (imm,rs1,rd) + else if (let mappingpatterns_24_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((encdec_bop_backwards_matches mappingpatterns_24_0)) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) then + let (imm7_6 : 1 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 31 : int):ii) : 1 words$word)) in + let (imm7_5_0 : 6 bits) = ((subrange_vec_dec v__175 (( 30 : int):ii) (( 25 : int):ii) : 6 words$word)) in + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_24_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (imm5_4_1 : 4 bits) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 8 : int):ii) : 4 words$word)) in + let (imm5_0 : 1 bits) = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let op = (encdec_bop_backwards mappingpatterns_24_0) in + BTYPE ((concat_vec imm7_6 + ((concat_vec imm5_0 + ((concat_vec imm7_5_0 + ((concat_vec imm5_4_1 (vec_of_bits [B0] : 1 words$word) : 5 words$word)) + : 11 words$word)) + : 12 words$word)) + : 13 words$word),rs2,rs1,op) + else if (let mappingpatterns_25_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((encdec_iop_backwards_matches mappingpatterns_25_0)) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) then + let (imm : 12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_25_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let op = (encdec_iop_backwards mappingpatterns_25_0) in + ITYPE (imm,rs1,rd,op) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))) then + let (shamt : 6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))) then + let (shamt : 6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))))) then + let (shamt : 6 words$word) = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 20 : int):ii) : 6 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_ADD) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SUB) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SLL) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SLT) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SLTU) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_XOR) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SRL) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_SRA) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_OR) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPE (rs2,rs1,rd,RISCV_AND) + else if (let mappingpatterns_26_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_27_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((size_bits_backwards_matches mappingpatterns_27_0)) /\ ((bool_bits_backwards_matches mappingpatterns_26_0))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) then + let (imm : 12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_26_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_27_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_27_0) in + let is_unsigned = (bool_bits_backwards mappingpatterns_26_0) in + LOAD (imm,rs1,rd,is_unsigned,size1,F,F) + else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_28_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((size_bits_backwards_matches mappingpatterns_28_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0] : 1 words$word)))))) then + let (imm7 : 7 bits) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_28_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (imm5 : 5 bits) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_28_0) in + STORE ((concat_vec imm7 imm5 : 12 words$word),rs2,rs1,size1,F,F) + else if (let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((p1_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))))) then + let (imm : 12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + ADDIW (imm,rs1,rd) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (shamt : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTW (shamt,rs1,rd,RISCV_SLLI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (shamt : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTW (shamt,rs1,rd,RISCV_SRLI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (shamt : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + SHIFTW (shamt,rs1,rd,RISCV_SRAI) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPEW (rs2,rs1,rd,RISCV_ADDW) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPEW (rs2,rs1,rd,RISCV_SUBW) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPEW (rs2,rs1,rd,RISCV_SLLW) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPEW (rs2,rs1,rd,RISCV_SRLW) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + RTYPEW (rs2,rs1,rd,RISCV_SRAW) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (mappingpatterns_29_0 : 3 bits) = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((encdec_mul_op_backwards_matches mappingpatterns_29_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (mappingpatterns_29_0 : 3 bits) = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_29_0) in + MUL (rs2,rs1,rd,high,signed1,signed2) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_30_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_30_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_30_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_30_0) in + DIV0 (rs2,rs1,rd,s) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_31_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_31_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_31_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_31_0) in + REM (rs2,rs1,rd,s) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + MULW (rs2,rs1,rd) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_32_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_32_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_32_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_32_0) in + DIVW (rs2,rs1,rd,s) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_33_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_33_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_33_0 = ((subrange_vec_dec v__175 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_33_0) in + REMW (rs2,rs1,rd,s) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))))) then + let (pred : 4 words$word) = ((subrange_vec_dec v__175 (( 27 : int):ii) (( 24 : int):ii) : 4 words$word)) in + let (succ : 4 words$word) = ((subrange_vec_dec v__175 (( 23 : int):ii) (( 20 : int):ii) : 4 words$word)) in + FENCE (pred,succ) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))) then + FENCEI () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))) then + ECALL () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p5_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)))))) then + MRET () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p5_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))))) then + SRET () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))))) then + EBREAK () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))))) then + WFI () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((p3_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))))) then + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + SFENCE_VMA (rs1,rs2) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_34_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_35_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_36_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((((size_bits_backwards_matches mappingpatterns_36_0)) /\ ((bool_bits_backwards_matches mappingpatterns_35_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_34_0))))) /\ (((p3_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))))) then + let mappingpatterns_34_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_35_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_36_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_36_0) in + let rl = (bool_bits_backwards mappingpatterns_35_0) in + let aq = (bool_bits_backwards mappingpatterns_34_0) in + LOADRES (aq,rl,rs1,size1,rd) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_37_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_38_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_39_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_39_0)) /\ ((bool_bits_backwards_matches mappingpatterns_38_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_37_0))))) /\ (((p2_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))))) then + let mappingpatterns_37_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_38_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_39_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_39_0) in + let rl = (bool_bits_backwards mappingpatterns_38_0) in + let aq = (bool_bits_backwards mappingpatterns_37_0) in + STORECON (aq,rl,rs2,rs1,size1,rd) + else if (let mappingpatterns_40_0 = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_41_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_42_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p0_ = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_43_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_43_0)) /\ ((bool_bits_backwards_matches mappingpatterns_42_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_41_0))))) /\ ((encdec_amoop_backwards_matches mappingpatterns_40_0))))) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0] : 1 words$word)))))) then + let mappingpatterns_40_0 = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_41_0 = ((subrange_vec_dec v__175 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_42_0 = ((subrange_vec_dec v__175 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let (rs2 : 5 words$word) = ((subrange_vec_dec v__175 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_43_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_43_0) in + let rl = (bool_bits_backwards mappingpatterns_42_0) in + let aq = (bool_bits_backwards mappingpatterns_41_0) in + let op = (encdec_amoop_backwards mappingpatterns_40_0) in + AMO (op,aq,rl,rs2,rs1,size1,rd) + else if (let mappingpatterns_44_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_45_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p0_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((encdec_csrop_backwards_matches mappingpatterns_45_0)) /\ ((bool_bits_backwards_matches mappingpatterns_44_0))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) then + let (csr : 12 words$word) = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let (rs1 : 5 words$word) = ((subrange_vec_dec v__175 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let mappingpatterns_44_0 = ((subrange_vec_dec v__175 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_45_0 = ((subrange_vec_dec v__175 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let (rd : 5 words$word) = ((subrange_vec_dec v__175 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let op = (encdec_csrop_backwards mappingpatterns_45_0) in + let is_imm = (bool_bits_backwards mappingpatterns_44_0) in + CSR (csr,rs1,rd,is_imm,op) + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let p5_ = ((subrange_vec_dec v__175 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0] : 2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word)))))) + then + STOP_FETCHING () + else if (let p0_ = ((subrange_vec_dec v__175 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) in + let p1_ = ((subrange_vec_dec v__175 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)) in + let p2_ = ((subrange_vec_dec v__175 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let p3_ = ((subrange_vec_dec v__175 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let p4_ = ((subrange_vec_dec v__175 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let p5_ = ((subrange_vec_dec v__175 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0] : 2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word)))))) + then + THREAD_START () + else ILLEGAL v__175))`; + + +(*val encdec_forwards_matches : ast -> bool*) + +val _ = Define ` + ((encdec_forwards_matches:ast -> bool) arg_= + ((case arg_ of + UTYPE (imm,rd,op) => T + | RISCV_JAL (v__224,rd) => + if (let p0_ = ((subrange_vec_dec v__224 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in + (p0_ = (vec_of_bits [B0] : 1 words$word))) then + T + else + let g__17 = (RISCV_JAL (v__224,rd)) in + F + | RISCV_JALR (imm,rs1,rd) => T + | BTYPE (v__225,rs2,rs1,op) => + if (let p0_ = ((subrange_vec_dec v__225 (( 0 : int):ii) (( 0 : int):ii) : 1 words$word)) in + (p0_ = (vec_of_bits [B0] : 1 words$word))) then + T + else + let g__17 = (BTYPE (v__225,rs2,rs1,op)) in + F + | ITYPE (imm,rs1,rd,op) => T + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => T + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => T + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => T + | RTYPE (rs2,rs1,rd,RISCV_ADD) => T + | RTYPE (rs2,rs1,rd,RISCV_SUB) => T + | RTYPE (rs2,rs1,rd,RISCV_SLL) => T + | RTYPE (rs2,rs1,rd,RISCV_SLT) => T + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => T + | RTYPE (rs2,rs1,rd,RISCV_XOR) => T + | RTYPE (rs2,rs1,rd,RISCV_SRL) => T + | RTYPE (rs2,rs1,rd,RISCV_SRA) => T + | RTYPE (rs2,rs1,rd,RISCV_OR) => T + | RTYPE (rs2,rs1,rd,RISCV_AND) => T + | LOAD (imm,rs1,rd,is_unsigned,size1,F,F) => T + | STORE (v__226,rs2,rs1,size1,F,F) => T + | ADDIW (imm,rs1,rd) => T + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => T + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => T + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => T + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => T + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => T + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => T + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => T + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => T + | MUL (rs2,rs1,rd,high,signed1,signed2) => T + | DIV0 (rs2,rs1,rd,s) => T + | REM (rs2,rs1,rd,s) => T + | MULW (rs2,rs1,rd) => T + | DIVW (rs2,rs1,rd,s) => T + | REMW (rs2,rs1,rd,s) => T + | FENCE (pred,succ) => T + | FENCEI (() ) => T + | ECALL (() ) => T + | MRET (() ) => T + | SRET (() ) => T + | EBREAK (() ) => T + | WFI (() ) => T + | SFENCE_VMA (rs1,rs2) => T + | LOADRES (aq,rl,rs1,size1,rd) => T + | STORECON (aq,rl,rs2,rs1,size1,rd) => T + | AMO (op,aq,rl,rs2,rs1,size1,rd) => T + | CSR (csr,rs1,rd,is_imm,op) => T + | STOP_FETCHING (() ) => T + | THREAD_START (() ) => T + | ILLEGAL (s) => T + | g__17 => F + )))`; + + +(*val encdec_backwards_matches : mword ty32 -> bool*) + +val _ = Define ` + ((encdec_backwards_matches:(32)words$word -> bool) arg_= + (let v__227 = arg_ in + if (let mappingpatterns_0_0 = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + encdec_uop_backwards_matches mappingpatterns_0_0) then + let mappingpatterns_0_0 = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + let op = (encdec_uop_backwards mappingpatterns_0_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (p0_ = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : 7 words$word))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((p1_ = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : 7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))))) then + T + else if (let mappingpatterns_1_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((encdec_bop_backwards_matches mappingpatterns_1_0)) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : 7 words$word)))))) then + let mappingpatterns_1_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let op = (encdec_bop_backwards mappingpatterns_1_0) in + T + else if (let mappingpatterns_2_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((encdec_iop_backwards_matches mappingpatterns_2_0)) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))))) then + let mappingpatterns_2_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let op = (encdec_iop_backwards mappingpatterns_2_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0] : 6 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 26 : int):ii) : 6 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0] : 6 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B1;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B1;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let mappingpatterns_3_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_4_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((size_bits_backwards_matches mappingpatterns_4_0)) /\ ((bool_bits_backwards_matches mappingpatterns_3_0))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : 7 words$word)))))) then + let mappingpatterns_3_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_4_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_4_0) in + let is_unsigned = (bool_bits_backwards mappingpatterns_3_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_5_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((size_bits_backwards_matches mappingpatterns_5_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0] : 1 words$word)))))) then + let mappingpatterns_5_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_5_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((p1_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p0_ = (vec_of_bits [B0;B0;B0] : 3 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B1;B0;B1] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let (mappingpatterns_6_0 : 3 bits) = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((encdec_mul_op_backwards_matches mappingpatterns_6_0)) /\ (((p1_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let (mappingpatterns_6_0 : 3 bits) = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_6_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_7_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_7_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let mappingpatterns_7_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_7_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_8_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_8_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let mappingpatterns_8_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_8_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word)))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_9_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_9_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B0] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let mappingpatterns_9_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_9_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 13 : int):ii) : 2 words$word)) in + let mappingpatterns_10_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_10_0)) /\ (((p2_ = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B1;B1] : 2 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : 7 words$word)))))) then + let mappingpatterns_10_0 = ((subrange_vec_dec v__227 (( 12 : int):ii) (( 12 : int):ii) : 1 words$word)) in + let s = (bool_not_bits_backwards mappingpatterns_10_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 28 : int):ii) : 4 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0] : 4 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B1] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p5_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p5_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p4_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p3_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : 12 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 20 : int):ii) : 12 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 19 : int):ii) (( 15 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((p4_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p3_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p2_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : 12 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 25 : int):ii) : 7 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 12 : int):ii) : 3 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 11 : int):ii) (( 7 : int):ii) : 5 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((p3_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))) /\ (((((regbits_to_regno p2_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) /\ (((p0_ = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : 7 words$word)))))) then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_11_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_12_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 24 : int):ii) (( 20 : int):ii) : 5 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_13_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((((((((((((((size_bits_backwards_matches mappingpatterns_13_0)) /\ ((bool_bits_backwards_matches mappingpatterns_12_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_11_0))))) /\ (((p3_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((((regbits_to_regno p1_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word))))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))))))) then + let mappingpatterns_11_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_12_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let mappingpatterns_13_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_13_0) in + let rl = (bool_bits_backwards mappingpatterns_12_0) in + let aq = (bool_bits_backwards mappingpatterns_11_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_14_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_15_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_16_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_16_0)) /\ ((bool_bits_backwards_matches mappingpatterns_15_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_14_0))))) /\ (((p2_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p1_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((((regbits_to_regno p0_)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))))))) then + let mappingpatterns_14_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_15_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let mappingpatterns_16_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_16_0) in + let rl = (bool_bits_backwards mappingpatterns_15_0) in + let aq = (bool_bits_backwards mappingpatterns_14_0) in + T + else if (let mappingpatterns_17_0 = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_18_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_19_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let p0_ = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_20_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_20_0)) /\ ((bool_bits_backwards_matches mappingpatterns_19_0))))) /\ ((bool_bits_backwards_matches mappingpatterns_18_0))))) /\ ((encdec_amoop_backwards_matches mappingpatterns_17_0))))) /\ (((p1_ = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : 7 words$word))))))) /\ (((p0_ = (vec_of_bits [B0] : 1 words$word)))))) then + let mappingpatterns_17_0 = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 27 : int):ii) : 5 words$word)) in + let mappingpatterns_18_0 = ((subrange_vec_dec v__227 (( 26 : int):ii) (( 26 : int):ii) : 1 words$word)) in + let mappingpatterns_19_0 = ((subrange_vec_dec v__227 (( 25 : int):ii) (( 25 : int):ii) : 1 words$word)) in + let mappingpatterns_20_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let size1 = (size_bits_backwards mappingpatterns_20_0) in + let rl = (bool_bits_backwards mappingpatterns_19_0) in + let aq = (bool_bits_backwards mappingpatterns_18_0) in + let op = (encdec_amoop_backwards mappingpatterns_17_0) in + T + else if (let mappingpatterns_21_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_22_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let p0_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 0 : int):ii) : 7 words$word)) in + ((((((encdec_csrop_backwards_matches mappingpatterns_22_0)) /\ ((bool_bits_backwards_matches mappingpatterns_21_0))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : 7 words$word)))))) then + let mappingpatterns_21_0 = ((subrange_vec_dec v__227 (( 14 : int):ii) (( 14 : int):ii) : 1 words$word)) in + let mappingpatterns_22_0 = ((subrange_vec_dec v__227 (( 13 : int):ii) (( 12 : int):ii) : 2 words$word)) in + let op = (encdec_csrop_backwards mappingpatterns_22_0) in + let is_imm = (bool_bits_backwards mappingpatterns_21_0) in + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let p5_ = ((subrange_vec_dec v__227 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0] : 2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word)))))) + then + T + else if (let p0_ = ((subrange_vec_dec v__227 (( 31 : int):ii) (( 16 : int):ii) : 16 words$word)) in + let p1_ = ((subrange_vec_dec v__227 (( 15 : int):ii) (( 8 : int):ii) : 8 words$word)) in + let p2_ = ((subrange_vec_dec v__227 (( 7 : int):ii) (( 7 : int):ii) : 1 words$word)) in + let p3_ = ((subrange_vec_dec v__227 (( 6 : int):ii) (( 5 : int):ii) : 2 words$word)) in + let p4_ = ((subrange_vec_dec v__227 (( 4 : int):ii) (( 2 : int):ii) : 3 words$word)) in + let p5_ = ((subrange_vec_dec v__227 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) in + ((((((((((((((((p5_ = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((p4_ = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) /\ (((p3_ = (vec_of_bits [B0;B0] : 2 words$word))))))) /\ (((p2_ = (vec_of_bits [B0] : 1 words$word))))))) /\ (((p1_ = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : 8 words$word))))))) /\ (((p0_ = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : 16 words$word)))))) + then + T + else T))`; + + +val _ = Define ` + ((print_insn:ast -> string) merge_var= + ((case merge_var of + NOP (g__13) => "nop" | C_ADDI4SPN (rdc,nzimm) => STRCAT "c.addi4spn " ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec nzimm)))))) + ((STRCAT ", " ((string_of_bits nzimm)))))) | C_LW (uimm,rsc,rdc) => STRCAT "c.lw " ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) ((STRCAT ", " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) + ((STRCAT ", " ((string_of_bits uimm)))))))))) | C_LD (uimm,rsc,rdc) => STRCAT "c.ld " ((STRCAT ((reg_name_abi ((creg2reg_bits rdc : 5 words$word)))) ((STRCAT ", " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) + ((STRCAT ", " ((string_of_bits uimm)))))))))) | C_SW (uimm,rsc1,rsc2) => STRCAT "c.sw " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) ((STRCAT ", " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) + ((STRCAT ", " ((string_of_bits uimm)))))))))) | C_SD (uimm,rsc1,rsc2) => STRCAT "c.sd " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1 : 5 words$word)))) ((STRCAT ", " ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2 : 5 words$word)))) - ((STRCAT ", " ((string_of_vec uimm)))))))))) + ((STRCAT ", " ((string_of_bits uimm)))))))))) | C_ADDI (nzi,rsd) => STRCAT "c.addi " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi)))))) - | C_JAL (imm) => STRCAT "c.jal " ((string_of_vec imm)) + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits nzi)))))) + | C_JAL (imm) => STRCAT "c.jal " ((string_of_bits imm)) | C_ADDIW (imm,rsd) => STRCAT "c.addiw " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm)))))) + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits imm)))))) | C_LI (imm,rd) => STRCAT "c.li " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) - | C_ADDI16SP (imm) => STRCAT "c.addi16sp " ((string_of_vec imm)) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits imm)))))) + | C_ADDI16SP (imm) => STRCAT "c.addi16sp " ((string_of_bits imm)) | C_LUI (imm,rd) => STRCAT "c.lui " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm)))))) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits imm)))))) | C_SRLI (shamt,rsd) => STRCAT "c.srli " ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec shamt)))))) + ((STRCAT ", " ((string_of_bits shamt)))))) | C_SRAI (shamt,rsd) => STRCAT "c.srai " ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec shamt)))))) + ((STRCAT ", " ((string_of_bits shamt)))))) | C_ANDI (imm,rsd) => STRCAT "c.andi " ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) + ((STRCAT ", " ((string_of_bits imm)))))) | C_SUB (rsd,rs2) => STRCAT "c.sub " ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) @@ -7451,30 +22851,30 @@ val _ = Define ` STRCAT "c.addw " ((STRCAT ((reg_name_abi ((creg2reg_bits rsd : 5 words$word)))) ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2 : 5 words$word)))))))) - | C_J (imm) => STRCAT "c.j " ((string_of_vec imm)) + | C_J (imm) => STRCAT "c.j " ((string_of_bits imm)) | C_BEQZ (imm,rs) => STRCAT "c.beqz " ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) + ((STRCAT ", " ((string_of_bits imm)))))) | C_BNEZ (imm,rs) => STRCAT "c.bnez " ((STRCAT ((reg_name_abi ((creg2reg_bits rs : 5 words$word)))) - ((STRCAT ", " ((string_of_vec imm)))))) + ((STRCAT ", " ((string_of_bits imm)))))) | C_SLLI (shamt,rsd) => STRCAT "c.slli " - ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt)))))) + ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_bits shamt)))))) | C_LWSP (uimm,rd) => STRCAT "c.lwsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm)))))) | C_LDSP (uimm,rd) => STRCAT "c.ldsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm)))))) | C_SWSP (uimm,rd) => STRCAT "c.swsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm)))))) | C_SDSP (uimm,rd) => STRCAT "c.sdsp " - ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm)))))) + ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_bits uimm)))))) | C_JR (rs1) => STRCAT "c.jr " ((reg_name_abi rs1)) | C_JALR (rs1) => STRCAT "c.jalr " ((reg_name_abi rs1)) | C_MV (rd,rs2) => @@ -7483,9 +22883,18 @@ val _ = Define ` | C_ADD (rsd,rs2) => STRCAT "c.add " ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2)))))) + | STOP_FETCHING (g__14) => "stop_fetching" + | THREAD_START (g__15) => "thread_start" + | ILLEGAL (s) => STRCAT "illegal " ((string_of_bits s)) + | C_ILLEGAL (g__16) => "c.illegal" + | insn => assembly_forwards insn )))`; +val _ = Define ` + ((decode:(32)words$word ->(ast)option) bv= (SOME ((encdec_backwards bv))))`; + + (*val isRVC : mword ty16 -> bool*) val _ = Define ` @@ -7496,42 +22905,42 @@ val _ = Define ` (*val fetch : unit -> M FetchResult*) val _ = Define ` - ((fetch:unit ->(regstate)state_monad$sequential_state ->(((FetchResult),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state$or_boolS - ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . - state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) - (state$and_boolS - ( state_monad$bindS(state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : xlenbits) . - state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) - ( state_monad$bindS(haveRVC () ) (\ (w__2 : bool) . state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . - if w__4 then state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . - state_monad$returnS (F_Error (E_Fetch_Addr_Align,w__5))) - else state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . state_monad$bindS + ((fetch:unit ->(regstate)sail2_state_monad$sequential_state ->(((FetchResult),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = (sail2_state_monad$bindS + (sail2_state$or_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : xlenbits) . + sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) + (sail2_state$and_boolS + ( sail2_state_monad$bindS(sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : xlenbits) . + sail2_state_monad$returnS (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):ii))) : 1 words$word)) <> (vec_of_bits [B0] : 1 words$word)))))) + ( sail2_state_monad$bindS(haveRVC () ) (\ (w__2 : bool) . sail2_state_monad$returnS ((~ w__2)))))) (\ (w__4 : bool) . + if w__4 then sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : 64 words$word) . + sail2_state_monad$returnS (F_Error (E_Fetch_Addr_Align,w__5))) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : 64 words$word) . sail2_state_monad$bindS (translateAddr w__6 Execute Instruction) (\ (w__7 : TR_Result) . (case w__7 of - TR_Failure (e) => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) . state_monad$returnS (F_Error (e,w__8))) - | TR_Address (ppclo) => state_monad$bindS + TR_Failure (e) => sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__8 : 64 words$word) . sail2_state_monad$returnS (F_Error (e,w__8))) + | TR_Address (ppclo) => sail2_state_monad$bindS (checked_mem_read Instruction ppclo (( 2 : int):ii) : ( ( 16 words$word)MemoryOpResult) M) (\ (w__9 : ( 16 words$word) MemoryOpResult) . (case w__9 of - MemException (e) => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . - state_monad$returnS (F_Error (E_Fetch_Access_Fault,w__10))) + MemException (e) => sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . + sail2_state_monad$returnS (F_Error (E_Fetch_Access_Fault,w__10))) | MemValue (ilo) => - if ((isRVC ilo)) then state_monad$returnS (F_RVC ilo) - else state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) . - let (PChi : xlenbits) = ((add_vec_int w__11 (( 2 : int):ii) : 64 words$word)) in state_monad$bindS + if ((isRVC ilo)) then sail2_state_monad$returnS (F_RVC ilo) + else sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) . + let (PChi : xlenbits) = ((add_vec_int w__11 (( 2 : int):ii) : 64 words$word)) in sail2_state_monad$bindS (translateAddr PChi Execute Instruction) (\ (w__12 : TR_Result) . (case w__12 of - TR_Failure (e) => state_monad$returnS (F_Error (e,PChi)) - | TR_Address (ppchi) => state_monad$bindS + TR_Failure (e) => sail2_state_monad$returnS (F_Error (e,PChi)) + | TR_Address (ppchi) => sail2_state_monad$bindS (checked_mem_read Instruction ppchi (( 2 : int):ii) : ( ( 16 words$word)MemoryOpResult) M) (\ (w__13 : ( 16 words$word) MemoryOpResult) . - state_monad$returnS ((case w__13 of + sail2_state_monad$returnS ((case w__13 of MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) | MemValue (ihi) => F_Base ((concat_vec ihi ilo : 32 words$word)) ))) @@ -7540,77 +22949,566 @@ val _ = Define ` ))))))`; -(*val step : unit -> M bool*) +(*val step : ii -> M (bool * bool)*) val _ = Define ` - ((step:unit ->(regstate)state_monad$sequential_state ->(((bool),(exception))state_monad$result#(regstate)state_monad$sequential_state)set) () = (state_monad$bindS - (state_monad$read_regS mip_ref) (\ (w__0 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mie_ref) (\ (w__1 : Minterrupts) . state_monad$bindS - (state_monad$read_regS mideleg_ref) (\ (w__2 : Minterrupts) . state_monad$bindS - (curInterrupt w__0 w__1 w__2) (\ (w__3 : ((InterruptType # Privilege))option) . - (case w__3 of + ((step:int ->(regstate)sail2_state_monad$sequential_state ->(((bool#bool),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) step_no= (sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__0 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mip_ref) (\ (w__1 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mie_ref) (\ (w__2 : Minterrupts) . sail2_state_monad$bindS + (sail2_state_monad$read_regS mideleg_ref) (\ (w__3 : Minterrupts) . sail2_state_monad$bindS + (curInterrupt w__0 w__1 w__2 w__3) (\ (w__4 : ((InterruptType # Privilege))option) . + (case w__4 of SOME (intr,priv) => - let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr : 4 words$word))) in state_monad$seqS - (handle_interrupt intr priv) (state_monad$returnS F) - | NONE => state_monad$bindS - (fetch () ) (\ (w__4 : FetchResult) . - (case w__4 of - F_Error (e,addr) => state_monad$seqS (handle_mem_exception addr e) (state_monad$returnS F) + let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr : 4 words$word))) in sail2_state_monad$seqS + (handle_interrupt intr priv) (sail2_state_monad$returnS (F, F)) + | NONE => sail2_state_monad$bindS + (fetch () ) (\ (w__5 : FetchResult) . + (case w__5 of + F_Error (e,addr) => sail2_state_monad$seqS (handle_mem_exception addr e) (sail2_state_monad$returnS (F, F)) | F_RVC (h) => (case ((decodeCompressed h)) of - NONE => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__5 : xlenbits) . + NONE => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__6 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__7 : xlenbits) . let (_ : unit) = - (prerr_endline - ((STRCAT "PC: " - ((STRCAT ((string_of_vec w__5)) - ((STRCAT " instr: " - ((STRCAT ((string_of_vec h)) " : <no-decode>"))))))))) in state_monad$seqS - (handle_decode_exception ((EXTZ (( 64 : int):ii) h : 64 words$word))) (state_monad$returnS F)) - | SOME (ast) => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__6 : xlenbits) . + (print_endline + ((STRCAT "[" + ((STRCAT ((stringFromInteger step_no)) + ((STRCAT "] [" + ((STRCAT ((privLevel_to_str w__6)) + ((STRCAT "]: " + ((STRCAT ((string_of_bits w__7)) + ((STRCAT " (" + ((STRCAT ((string_of_bits h)) ") <no-decode>"))))))))))))))))) in sail2_state_monad$seqS + (handle_decode_exception ((EXTZ (( 64 : int):ii) h : 64 words$word))) (sail2_state_monad$returnS (F, T)))) + | SOME (ast) => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__8 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : xlenbits) . let (_ : unit) = - (prerr_endline - ((STRCAT "PC: " - ((STRCAT ((string_of_vec w__6)) - ((STRCAT " instr: " - ((STRCAT ((string_of_vec h)) - ((STRCAT " : " ((print_insn ast))))))))))))) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__7 : 64 words$word) . state_monad$seqS (state_monad$seqS - (state_monad$write_regS nextPC_ref ((add_vec_int w__7 (( 2 : int):ii) : 64 words$word))) - (execute ast)) (state_monad$returnS T))) + (print_endline + ((STRCAT "[" + ((STRCAT ((stringFromInteger step_no)) + ((STRCAT "] [" + ((STRCAT ((privLevel_to_str w__8)) + ((STRCAT "]: " + ((STRCAT ((string_of_bits w__9)) + ((STRCAT " (" + ((STRCAT ((string_of_bits h)) + ((STRCAT ") " ((print_insn ast))))))))))))))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__10 (( 2 : int):ii) : 64 words$word))) + (execute ast)) (\ (w__11 : bool) . sail2_state_monad$returnS (w__11, T))))) ) | F_Base (w) => (case ((decode w)) of - NONE => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__9 : xlenbits) . + NONE => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__13 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__14 : xlenbits) . let (_ : unit) = - (prerr_endline - ((STRCAT "PC: " - ((STRCAT ((string_of_vec w__9)) - ((STRCAT " instr: " - ((STRCAT ((string_of_vec w)) " : <no-decode>"))))))))) in state_monad$seqS - (handle_decode_exception ((EXTZ (( 64 : int):ii) w : 64 words$word))) (state_monad$returnS F)) - | SOME (ast) => state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__10 : xlenbits) . + (print_endline + ((STRCAT "[" + ((STRCAT ((stringFromInteger step_no)) + ((STRCAT "] [" + ((STRCAT ((privLevel_to_str w__13)) + ((STRCAT "]: " + ((STRCAT ((string_of_bits w__14)) + ((STRCAT " (" + ((STRCAT ((string_of_bits w)) ") <no-decode>"))))))))))))))))) in sail2_state_monad$seqS + (handle_decode_exception ((EXTZ (( 64 : int):ii) w : 64 words$word))) (sail2_state_monad$returnS (F, T)))) + | SOME (ast) => sail2_state_monad$bindS + (sail2_state_monad$read_regS cur_privilege_ref) (\ (w__15 : Privilege) . sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__16 : xlenbits) . let (_ : unit) = - (prerr_endline - ((STRCAT "PC: " - ((STRCAT ((string_of_vec w__10)) - ((STRCAT " instr: " - ((STRCAT ((string_of_vec w)) - ((STRCAT " : " ((print_insn ast))))))))))))) in state_monad$bindS - (state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__11 : 64 words$word) . state_monad$seqS (state_monad$seqS - (state_monad$write_regS nextPC_ref ((add_vec_int w__11 (( 4 : int):ii) : 64 words$word))) - (execute ast)) (state_monad$returnS T))) + (print_endline + ((STRCAT "[" + ((STRCAT ((stringFromInteger step_no)) + ((STRCAT "] [" + ((STRCAT ((privLevel_to_str w__15)) + ((STRCAT "]: " + ((STRCAT ((string_of_bits w__16)) + ((STRCAT " (" + ((STRCAT ((string_of_bits w)) + ((STRCAT ") " ((print_insn ast))))))))))))))))))))) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__17 : 64 words$word) . sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS nextPC_ref ((add_vec_int w__17 (( 4 : int):ii) : 64 words$word))) + (execute ast)) (\ (w__18 : bool) . sail2_state_monad$returnS (w__18, T))))) ) )) - )))))))`; + ))))))))`; + + +(*val loop : unit -> M unit*) + +val _ = Define ` + ((loop:unit ->(regstate)sail2_state_monad$sequential_state ->(((unit),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) () = + (let insns_per_tick = (plat_insns_per_tick () ) in + let (i : ii) = ((( 0 : int):ii)) in + let (step_no : ii) = ((( 0 : int):ii)) in sail2_state_monad$bindS + (sail2_state$whileS (i, step_no) + (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_done_ref) (\ (w__0 : bool) . sail2_state_monad$returnS ((~ w__0)))) + (\ varstup . let (i, step_no) = varstup in sail2_state_monad$bindS (sail2_state_monad$seqS + (sail2_state_monad$write_regS minstret_written_ref F) + (step step_no)) (\ varstup . let (retired, stepped) = varstup in sail2_state_monad$bindS + (sail2_state_monad$read_regS nextPC_ref : ( 64 words$word) M) (\ (w__1 : xlenbits) . sail2_state_monad$seqS (sail2_state_monad$seqS + (sail2_state_monad$write_regS PC_ref w__1) + (if retired then retire_instruction () + else sail2_state_monad$returnS () )) + (let (step_no : ii) = (if stepped then ((ex_int step_no)) + (( 1 : int):ii) else step_no) in sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_done_ref) (\ (w__2 : bool) . sail2_state_monad$bindS + (if w__2 then sail2_state_monad$bindS + (sail2_state_monad$read_regS htif_exit_code_ref : ( 64 words$word) M) (\ (w__3 : xlenbits) . + let exit_val = (lem$w2ui w__3) in + sail2_state_monad$returnS (let _ = + (if (((exit_val = (( 0 : int):ii)))) then print_endline "SUCCESS" + else print_int "FAILURE: " exit_val) in + i)) + else + let i = (((ex_int i)) + (( 1 : int):ii)) in + if (((((ex_int i)) = insns_per_tick))) then sail2_state_monad$seqS (sail2_state_monad$seqS + (tick_clock () ) (tick_platform () )) (sail2_state_monad$returnS (( 0 : int):ii)) + else sail2_state_monad$returnS i) (\ (i : ii) . + sail2_state_monad$returnS (i, step_no)))))))) (\ varstup . let ((i : ii), (step_no : ii)) = varstup in + sail2_state_monad$returnS () )))`; + + +(*val read_kind_of_num : integer -> read_kind*) + +val _ = Define ` + ((read_kind_of_num:int -> read_kind) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Read_plain + else if (((p0_ = (( 1 : int):ii)))) then Read_reserve + else if (((p0_ = (( 2 : int):ii)))) then Read_acquire + else if (((p0_ = (( 3 : int):ii)))) then Read_exclusive + else if (((p0_ = (( 4 : int):ii)))) then Read_exclusive_acquire + else if (((p0_ = (( 5 : int):ii)))) then Read_stream + else if (((p0_ = (( 6 : int):ii)))) then Read_RISCV_acquire + else if (((p0_ = (( 7 : int):ii)))) then Read_RISCV_strong_acquire + else if (((p0_ = (( 8 : int):ii)))) then Read_RISCV_reserved + else if (((p0_ = (( 9 : int):ii)))) then Read_RISCV_reserved_acquire + else if (((p0_ = (( 10 : int):ii)))) then Read_RISCV_reserved_strong_acquire + else Read_X86_locked))`; + + +(*val num_of_read_kind : read_kind -> integer*) + +val _ = Define ` + ((num_of_read_kind:read_kind -> int) arg_= + ((case arg_ of + Read_plain => (( 0 : int):ii) + | Read_reserve => (( 1 : int):ii) + | Read_acquire => (( 2 : int):ii) + | Read_exclusive => (( 3 : int):ii) + | Read_exclusive_acquire => (( 4 : int):ii) + | Read_stream => (( 5 : int):ii) + | Read_RISCV_acquire => (( 6 : int):ii) + | Read_RISCV_strong_acquire => (( 7 : int):ii) + | Read_RISCV_reserved => (( 8 : int):ii) + | Read_RISCV_reserved_acquire => (( 9 : int):ii) + | Read_RISCV_reserved_strong_acquire => (( 10 : int):ii) + | Read_X86_locked => (( 11 : int):ii) + )))`; + + +(*val write_kind_of_num : integer -> write_kind*) + +val _ = Define ` + ((write_kind_of_num:int -> write_kind) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Write_plain + else if (((p0_ = (( 1 : int):ii)))) then Write_conditional + else if (((p0_ = (( 2 : int):ii)))) then Write_release + else if (((p0_ = (( 3 : int):ii)))) then Write_exclusive + else if (((p0_ = (( 4 : int):ii)))) then Write_exclusive_release + else if (((p0_ = (( 5 : int):ii)))) then Write_RISCV_release + else if (((p0_ = (( 6 : int):ii)))) then Write_RISCV_strong_release + else if (((p0_ = (( 7 : int):ii)))) then Write_RISCV_conditional + else if (((p0_ = (( 8 : int):ii)))) then Write_RISCV_conditional_release + else if (((p0_ = (( 9 : int):ii)))) then Write_RISCV_conditional_strong_release + else Write_X86_locked))`; + + +(*val num_of_write_kind : write_kind -> integer*) + +val _ = Define ` + ((num_of_write_kind:write_kind -> int) arg_= + ((case arg_ of + Write_plain => (( 0 : int):ii) + | Write_conditional => (( 1 : int):ii) + | Write_release => (( 2 : int):ii) + | Write_exclusive => (( 3 : int):ii) + | Write_exclusive_release => (( 4 : int):ii) + | Write_RISCV_release => (( 5 : int):ii) + | Write_RISCV_strong_release => (( 6 : int):ii) + | Write_RISCV_conditional => (( 7 : int):ii) + | Write_RISCV_conditional_release => (( 8 : int):ii) + | Write_RISCV_conditional_strong_release => (( 9 : int):ii) + | Write_X86_locked => (( 10 : int):ii) + )))`; + + +(*val barrier_kind_of_num : integer -> barrier_kind*) + +val _ = Define ` + ((barrier_kind_of_num:int -> barrier_kind) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Barrier_Sync + else if (((p0_ = (( 1 : int):ii)))) then Barrier_LwSync + else if (((p0_ = (( 2 : int):ii)))) then Barrier_Eieio + else if (((p0_ = (( 3 : int):ii)))) then Barrier_Isync + else if (((p0_ = (( 4 : int):ii)))) then Barrier_DMB + else if (((p0_ = (( 5 : int):ii)))) then Barrier_DMB_ST + else if (((p0_ = (( 6 : int):ii)))) then Barrier_DMB_LD + else if (((p0_ = (( 7 : int):ii)))) then Barrier_DSB + else if (((p0_ = (( 8 : int):ii)))) then Barrier_DSB_ST + else if (((p0_ = (( 9 : int):ii)))) then Barrier_DSB_LD + else if (((p0_ = (( 10 : int):ii)))) then Barrier_ISB + else if (((p0_ = (( 11 : int):ii)))) then Barrier_MIPS_SYNC + else if (((p0_ = (( 12 : int):ii)))) then Barrier_RISCV_rw_rw + else if (((p0_ = (( 13 : int):ii)))) then Barrier_RISCV_r_rw + else if (((p0_ = (( 14 : int):ii)))) then Barrier_RISCV_r_r + else if (((p0_ = (( 15 : int):ii)))) then Barrier_RISCV_rw_w + else if (((p0_ = (( 16 : int):ii)))) then Barrier_RISCV_w_w + else if (((p0_ = (( 17 : int):ii)))) then Barrier_RISCV_w_rw + else if (((p0_ = (( 18 : int):ii)))) then Barrier_RISCV_rw_r + else if (((p0_ = (( 19 : int):ii)))) then Barrier_RISCV_r_w + else if (((p0_ = (( 20 : int):ii)))) then Barrier_RISCV_w_r + else if (((p0_ = (( 21 : int):ii)))) then Barrier_RISCV_i + else Barrier_x86_MFENCE))`; + + +(*val num_of_barrier_kind : barrier_kind -> integer*) + +val _ = Define ` + ((num_of_barrier_kind:barrier_kind -> int) arg_= + ((case arg_ of + Barrier_Sync => (( 0 : int):ii) + | Barrier_LwSync => (( 1 : int):ii) + | Barrier_Eieio => (( 2 : int):ii) + | Barrier_Isync => (( 3 : int):ii) + | Barrier_DMB => (( 4 : int):ii) + | Barrier_DMB_ST => (( 5 : int):ii) + | Barrier_DMB_LD => (( 6 : int):ii) + | Barrier_DSB => (( 7 : int):ii) + | Barrier_DSB_ST => (( 8 : int):ii) + | Barrier_DSB_LD => (( 9 : int):ii) + | Barrier_ISB => (( 10 : int):ii) + | Barrier_MIPS_SYNC => (( 11 : int):ii) + | Barrier_RISCV_rw_rw => (( 12 : int):ii) + | Barrier_RISCV_r_rw => (( 13 : int):ii) + | Barrier_RISCV_r_r => (( 14 : int):ii) + | Barrier_RISCV_rw_w => (( 15 : int):ii) + | Barrier_RISCV_w_w => (( 16 : int):ii) + | Barrier_RISCV_w_rw => (( 17 : int):ii) + | Barrier_RISCV_rw_r => (( 18 : int):ii) + | Barrier_RISCV_r_w => (( 19 : int):ii) + | Barrier_RISCV_w_r => (( 20 : int):ii) + | Barrier_RISCV_i => (( 21 : int):ii) + | Barrier_x86_MFENCE => (( 22 : int):ii) + )))`; + + +(*val trans_kind_of_num : integer -> trans_kind*) + +val _ = Define ` + ((trans_kind_of_num:int -> trans_kind) arg_= + (let p0_ = arg_ in + if (((p0_ = (( 0 : int):ii)))) then Transaction_start + else if (((p0_ = (( 1 : int):ii)))) then Transaction_commit + else Transaction_abort))`; + + +(*val num_of_trans_kind : trans_kind -> integer*) + +val _ = Define ` + ((num_of_trans_kind:trans_kind -> int) arg_= + ((case arg_ of + Transaction_start => (( 0 : int):ii) + | Transaction_commit => (( 1 : int):ii) + | Transaction_abort => (( 2 : int):ii) + )))`; + + +val _ = Define ` +((GPRstr:(string)list)= + (["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16"; + "x15";"x14";"x13";"x12";"x21";"x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]))`; + + +val _ = Define ` + ((CIA_fp:regfp)= (RFull "CIA"))`; + + +val _ = Define ` + ((NIA_fp:regfp)= (RFull "NIA"))`; + + +(*val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)*) + +val _ = Define ` + ((initial_analysis:ast ->(regstate)sail2_state_monad$sequential_state ->((((regfp)list#(regfp)list#(regfp)list#(niafp)list#diafp#instruction_kind),(exception))sail2_state_monad$result#(regstate)sail2_state_monad$sequential_state)set) instr= + (let iR = ([]) in + let oR = ([]) in + let aR = ([]) in + let ik = (IK_simple () ) in + let Nias = ([NIAFP_successor () ]) in + let Dia = (DIAFP_none () ) in sail2_state_monad$bindS + (case instr of + EBREAK (_) => sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | UTYPE (imm,rd,op) => + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | RISCV_JAL (imm,rd) => + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__0 : 64 words$word) . + let (Nias : niafps) = ([NIAFP_concrete_address ((add_vec w__0 offset : 64 words$word))]) in + let (ik : instruction_kind) = (IK_branch () ) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | RISCV_JALR (imm,rs,rd) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in + let (Nias : niafps) = ([NIAFP_indirect_address () ]) in + let (ik : instruction_kind) = (IK_branch () ) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | BTYPE (imm,rs2,rs1,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let ik = (IK_branch () ) in + let (offset : 64 bits) = ((EXTS (( 64 : int):ii) imm : 64 words$word)) in sail2_state_monad$bindS + (sail2_state_monad$read_regS PC_ref : ( 64 words$word) M) (\ (w__1 : 64 words$word) . + let (Nias : niafps) = + ([NIAFP_concrete_address ((add_vec w__1 offset : 64 words$word));NIAFP_successor () ]) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | ITYPE (imm,rs,rd,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | SHIFTIOP (imm,rs,rd,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | RTYPE (rs2,rs1,rd,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | CSR (csr,rs1,rd,is_imm,op) => + let (isWrite : bool) = + ((case op of + CSRRW => T + | _ => if is_imm then (((lem$w2ui rs1)) <> (( 0 : int):ii)) else (((lem$w2ui rs1)) <> (( 0 : int):ii)) + )) in + let (iR : regfps) = ((RFull ((csr_name csr))) :: iR) in + let (iR : regfps) = + (if ((~ is_imm)) then (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR + else iR) in + let (oR : regfps) = (if isWrite then (RFull ((csr_name csr))) :: oR else oR) in + let (oR : regfps) = ((RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | LOAD (imm,rs,rd,unsign,width,aq,rl) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + let aR = iR in sail2_state_monad$bindS + (case (aq, rl) of + (F, F) => sail2_state_monad$returnS (IK_mem_read Read_plain) + | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_acquire) + | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_strong_acquire) + | _ => internal_error "LOAD type not implemented in initial_analysis" + ) (\ (w__3 : instruction_kind) . + let (ik : instruction_kind) = w__3 in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | STORE (imm,rs2,rs1,width,aq,rl) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (aR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in sail2_state_monad$bindS + (case (aq, rl) of + (F, F) => sail2_state_monad$returnS (IK_mem_write Write_plain) + | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_release) + | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_strong_release) + | _ => internal_error "STORE type not implemented in initial_analysis" + ) (\ (w__5 : instruction_kind) . + let (ik : instruction_kind) = w__5 in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | ADDIW (imm,rs,rd) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | SHIFTW (imm,rs,rd,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | RTYPEW (rs2,rs1,rd,op) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | FENCE (pred,succ) => sail2_state_monad$bindS + (case (pred, succ) of + (v__276, v__277) => + if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_r) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_w) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_w) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_rw_r) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_r_w) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B1] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B1;B0] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_barrier Barrier_RISCV_w_r) + else if ((((((((subrange_vec_dec v__276 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word)))) /\ (((((subrange_vec_dec v__277 (( 1 : int):ii) (( 0 : int):ii) : 2 words$word)) = (vec_of_bits [B0;B0] : 2 words$word))))))) then + sail2_state_monad$returnS (IK_simple () ) + else internal_error "barrier type not implemented in initial_analysis" + ) (\ (w__17 : instruction_kind) . + let (ik : instruction_kind) = w__17 in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | FENCEI (_) => + let (ik : instruction_kind) = (IK_barrier Barrier_RISCV_i) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | LOADRES (aq,rl,rs1,width,rd) => + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + let aR = iR in sail2_state_monad$bindS + (case (aq, rl) of + (F, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved) + | (T, F) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_acquire) + | (T, T) => sail2_state_monad$returnS (IK_mem_read Read_RISCV_reserved_strong_acquire) + | (F, T) => internal_error "LOADRES type not implemented in initial_analysis" + ) (\ (w__19 : instruction_kind) . + let (ik : instruction_kind) = w__19 in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | STORECON (aq,rl,rs2,rs1,width,rd) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (aR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in sail2_state_monad$bindS + (case (aq, rl) of + (F, F) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional) + | (F, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_release) + | (T, T) => sail2_state_monad$returnS (IK_mem_write Write_RISCV_conditional_strong_release) + | (T, F) => internal_error "STORECON type not implemented in initial_analysis" + ) (\ (w__21 : instruction_kind) . + let (ik : instruction_kind) = w__21 in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR)) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + let (iR : regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) :: iR) in + let (iR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: iR) in + let (aR : regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 : int):ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) :: aR) in + let (oR : regfps) = + (if (((((regbits_to_regno rd)) = (( 0 : int):ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) :: oR) in + let (ik : instruction_kind) = + ((case (aq, rl) of + (F, F) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional) + | (F, T) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional_release) + | (T, F) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional) + | (T, T) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional_release) + )) in + sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + | _ => sail2_state_monad$returnS (Nias, aR, iR, ik, oR) + ) (\ varstup . let ((Nias : niafps), (aR : regfps), (iR : regfps), (ik : instruction_kind), (oR : + regfps)) = varstup in + sail2_state_monad$returnS (iR, oR, aR, Nias, Dia, ik))))`; val _ = Define ` ((initial_regstate:regstate)= (<| tlb39 := NONE; + htif_exit_code := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + htif_done := F; + htif_tohost := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + mtimecmp := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); tselect := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -7622,10 +23520,11 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); scause := - (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Mcause_Mcause_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); sepc := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -7637,26 +23536,28 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); stvec := - (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Mtvec_Mtvec_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); satp := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); sideleg := - (Mk_Sinterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| Sinterrupts_Sinterrupts_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); sedeleg := - (Mk_Sedeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Sedeleg_Sedeleg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); pmpcfg0 := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -7687,6 +23588,7 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); + minstret_written := F; minstret := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -7702,6 +23604,16 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); + scounteren := + (<| Counteren_Counteren_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); + mcounteren := + (<| Counteren_Counteren_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0] + : 32 words$word)) |>); mscratch := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -7718,54 +23630,214 @@ val _ = Define ` B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); mcause := - (Mk_Mcause (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Mcause_Mcause_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); mtvec := - (Mk_Mtvec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Mtvec_Mtvec_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); medeleg := - (Mk_Medeleg (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Medeleg_Medeleg_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); mideleg := - (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| Minterrupts_Minterrupts_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); mie := - (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| Minterrupts_Minterrupts_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); mip := - (Mk_Minterrupts (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : 64 words$word)); + (<| Minterrupts_Minterrupts_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); mstatus := - (Mk_Mstatus (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Mstatus_Mstatus_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); misa := - (Mk_Misa (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : 64 words$word)); + (<| Misa_Misa_chunk_0 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)) |>); cur_inst := ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 64 words$word)); cur_privilege := User; + x31 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x30 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x29 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x28 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x27 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x26 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x25 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x24 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x23 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x22 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x21 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x20 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x19 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x18 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x17 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x16 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x15 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x14 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x13 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x12 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x11 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x10 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x9 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x8 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x7 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x6 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x5 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x4 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x3 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x2 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); + x1 := + ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : 64 words$word)); Xs := ([(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; diff --git a/snapshots/hol4/sail/riscv/riscv_extrasScript.sml b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml index 41ae5deb..32ef1ebd 100644 --- a/snapshots/hol4/sail/riscv/riscv_extrasScript.sml +++ b/snapshots/hol4/sail/riscv/riscv_extrasScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from riscv_extras.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; +open lem_pervasivesTheory lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory; val _ = numLib.prefer_num(); @@ -10,31 +10,43 @@ val _ = new_theory "riscv_extras" (*open import Pervasives*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) val _ = type_abbrev((* 'a *) "bitvector" , ``: 'a words$word``); val _ = Define ` - ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_rw))`; + ((MEM_fence_rw_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_rw))`; val _ = Define ` - ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_rw))`; + ((MEM_fence_r_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_rw))`; val _ = Define ` - ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_r))`; + ((MEM_fence_r_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_r))`; val _ = Define ` - ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_w))`; + ((MEM_fence_rw_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_w))`; val _ = Define ` - ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_w))`; + ((MEM_fence_w_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_w))`; val _ = Define ` - ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () = (barrier Barrier_RISCV_i))`; + ((MEM_fence_w_rw:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_rw))`; + +val _ = Define ` + ((MEM_fence_rw_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_rw_r))`; + +val _ = Define ` + ((MEM_fence_r_w:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_r_w))`; + +val _ = Define ` + ((MEM_fence_w_r:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_w_r))`; + +val _ = Define ` + ((MEM_fence_i:unit -> 'b sail2_state_monad$sequential_state ->(((unit),'a)sail2_state_monad$result#'b sail2_state_monad$sequential_state)set) () = (barrier Barrier_RISCV_i))`; (*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) @@ -45,60 +57,150 @@ val _ = Define ` (*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) val _ = Define ` - ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`; + ((MEMea:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`; + +val _ = Define ` + ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addr size1= + (sail2_state_monad$write_mem_eaS + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`; + + +(*val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) + +val _ = Define ` + ((MEMr:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addr size1))`; val _ = Define ` - ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`; + ((MEMr_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addr size1))`; val _ = Define ` - ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`; + ((MEMr_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addr size1))`; val _ = Define ` - ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`; + ((MEMr_reserved:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addr size1))`; val _ = Define ` - ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`; + ((MEMr_reserved_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addr size1))`; val _ = Define ` - ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1= - (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`; + ((MEMr_reserved_strong_acquire:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM addr= (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addr size1))`; (*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*) val _ = Define ` - ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value= (state_monad$bindS (state_monad$seqS - (state_monad$write_mem_eaS - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1)) - (state_monad$write_mem_valS - instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b . (case (b ) of ( _ ) => state_monad$returnS () ))))`; + ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv sail2_state_monad$sequential_state ->(((unit),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address value= (sail2_state_monad$bindS + (sail2_state_monad$write_mem_valS + instance_Sail2_values_Bitvector_Machine_word_mword_dict value) (\b . (case (b ) of ( _ ) => sail2_state_monad$returnS () ))))`; (*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) val _ = Define ` - ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address= - (state_monad$read_memS - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; + ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv sail2_state_monad$sequential_state ->((('b words$word),'e)sail2_state_monad$result#'rv sail2_state_monad$sequential_state)set) addrsize size1 hexRAM address= + (sail2_state_monad$read_memS + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`; + + +(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*) +val _ = Define ` + ((load_reservation:'a words$word -> unit) addr= () )`; + + +val _ = Define ` + ((speculate_conditional_success:'c -> 'a sail2_state_monad$sequential_state ->(((bool),'b)sail2_state_monad$result#'a sail2_state_monad$sequential_state)set) _= (sail2_state_monad$excl_resultS () ))`; + + +val _ = Define ` + ((cancel_reservation:unit -> unit) () = () )`; + + +(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_ram_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; +(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*) val _ = Define ` - ((speculate_conditional_success:unit -> 'a state_monad$sequential_state ->(((bool),'b)state_monad$result#'a state_monad$sequential_state)set) () = (state_monad$excl_resultS () ))`; + ((plat_ram_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; -(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*) +(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*) val _ = Define ` - ((get_slice_int0:int -> int -> int -> 'a words$word) len n lo= - ( - (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in - let bits = (bits_of_int (hi +( 1 : int)) n) in - of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list F bits hi lo)))`; + ((plat_rom_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; + + +(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_rom_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; + + +(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_clint_base:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; + + +(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_clint_size:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; + + +(*val plat_enable_dirty_update : unit -> bool*) +val _ = Define ` + ((plat_enable_dirty_update:unit -> bool) () = F)`; + + +(*val plat_enable_misaligned_access : unit -> bool*) +val _ = Define ` + ((plat_enable_misaligned_access:unit -> bool) () = F)`; + + +(*val plat_insns_per_tick : unit -> integer*) +val _ = Define ` + ((plat_insns_per_tick:unit -> int) () = (( 1 : int)))`; + + +(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_htif_tohost:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; + + +(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*) +val _ = Define ` + ((plat_term_write:'a words$word -> unit) _= () )`; + + +(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*) +val _ = Define ` + ((plat_term_read:unit -> 'a words$word) () = (integer_word$i2w(( 0 : int))))`; (*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) @@ -112,12 +214,22 @@ val _ = Define ` (*val print_string : string -> string -> unit*) val _ = Define ` - ((print_string:string -> string -> unit) msg s= (prerr_endline ( STRCAT msg s)))`; + ((print_string:string -> string -> unit) msg s= () )`; + (* print_endline (msg ^ s) *) +(*val prerr_string : string -> string -> unit*) +val _ = Define ` + ((prerr_string:string -> string -> unit) msg s= (prerr_endline ( STRCAT msg s)))`; -(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) + +(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) val _ = Define ` - ((print_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`; + ((prerr_bits:string -> 'a words$word -> unit) msg bs= (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`; + +(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) +val _ = Define ` + ((print_bits:string -> 'a words$word -> unit) msg bs= () )`; + (* print_endline (msg ^ (show_bitlist (bits_of bs))) *) val _ = export_theory() diff --git a/snapshots/hol4/sail/riscv/riscv_typesScript.sml b/snapshots/hol4/sail/riscv/riscv_typesScript.sml index 4637d1df..d478b614 100644 --- a/snapshots/hol4/sail/riscv/riscv_typesScript.sml +++ b/snapshots/hol4/sail/riscv/riscv_typesScript.sml @@ -1,6 +1,6 @@ (*Generated by Lem from riscv_types.lem.*) open HolKernel Parse boolLib bossLib; -open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory prompt_monadTheory promptTheory; +open lem_pervasives_extraTheory sail2_instr_kindsTheory sail2_valuesTheory sail2_prompt_monadTheory sail2_operators_mwordsTheory sail2_promptTheory sail2_stringTheory; val _ = numLib.prefer_num(); @@ -10,11 +10,12 @@ val _ = new_theory "riscv_types" (*Generated by Sail from riscv.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) val _ = type_abbrev((* 'n *) "bits" , ``: 'n words$word``); @@ -205,80 +206,67 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` - MemoryOpResult = MemValue of ('a) | MemException of (ExceptionType)`; - + Misa = <| Misa_Misa_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Misa = Mk_Misa of ( 64 words$word)`; - + SV39_PTE = <| SV39_PTE_SV39_PTE_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - SV39_PTE = Mk_SV39_PTE of ( 64 words$word)`; - + PTE_Bits = <| PTE_Bits_PTE_Bits_chunk_0 : 8 words$word |>`; val _ = Hol_datatype ` - PTE_Bits = Mk_PTE_Bits of ( 8 words$word)`; - + Mstatus = <| Mstatus_Mstatus_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Mstatus = Mk_Mstatus of ( 64 words$word)`; - + Sstatus = <| Sstatus_Sstatus_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Sstatus = Mk_Sstatus of ( 64 words$word)`; - + Minterrupts = <| Minterrupts_Minterrupts_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Minterrupts = Mk_Minterrupts of ( 64 words$word)`; - + Sinterrupts = <| Sinterrupts_Sinterrupts_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Sinterrupts = Mk_Sinterrupts of ( 64 words$word)`; - + Medeleg = <| Medeleg_Medeleg_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Medeleg = Mk_Medeleg of ( 64 words$word)`; - + Sedeleg = <| Sedeleg_Sedeleg_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Sedeleg = Mk_Sedeleg of ( 64 words$word)`; - + Mtvec = <| Mtvec_Mtvec_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Mtvec = Mk_Mtvec of ( 64 words$word)`; - + Satp64 = <| Satp64_Satp64_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Satp64 = Mk_Satp64 of ( 64 words$word)`; - + Mcause = <| Mcause_Mcause_chunk_0 : 64 words$word |>`; val _ = Hol_datatype ` - Mcause = Mk_Mcause of ( 64 words$word)`; - + Counteren = <| Counteren_Counteren_chunk_0 : 32 words$word |>`; @@ -294,6 +282,17 @@ val _ = Hol_datatype ` +val _ = Hol_datatype ` + MemoryOpResult = MemValue of ('a) | MemException of (ExceptionType)`; + + + + +val _ = Hol_datatype ` + htif_cmd = <| htif_cmd_htif_cmd_chunk_0 : 64 words$word |>`; + + + val _ = type_abbrev( "pteAttribs" , ``: 8 bits``); val _ = Hol_datatype ` @@ -309,14 +308,12 @@ val _ = type_abbrev( "paddr39" , ``: 56 bits``); val _ = type_abbrev( "pte39" , ``: xlenbits``); val _ = Hol_datatype ` - SV39_Vaddr = Mk_SV39_Vaddr of ( 39 words$word)`; - + SV39_Vaddr = <| SV39_Vaddr_SV39_Vaddr_chunk_0 : 39 words$word |>`; val _ = Hol_datatype ` - SV39_Paddr = Mk_SV39_Paddr of ( 56 words$word)`; - + SV39_Paddr = <| SV39_Paddr_SV39_Paddr_chunk_0 : 56 words$word |>`; @@ -388,7 +385,6 @@ val _ = Hol_datatype ` | AMO of ((amoop # bool # bool # regbits # regbits # word_width # regbits)) | CSR of (( 12 bits # regbits # regbits # bool # csrop)) | NOP of (unit) - | ILLEGAL of (unit) | C_ADDI4SPN of ((cregbits # 8 bits)) | C_LW of (( 5 bits # cregbits # cregbits)) | C_LD of (( 5 bits # cregbits # cregbits)) @@ -420,7 +416,11 @@ val _ = Hol_datatype ` | C_JR of (regbits) | C_JALR of (regbits) | C_MV of ((regbits # regbits)) - | C_ADD of ((regbits # regbits))`; + | C_ADD of ((regbits # regbits)) + | STOP_FETCHING of (unit) + | THREAD_START of (unit) + | ILLEGAL of (word) + | C_ILLEGAL of (unit)`; @@ -432,10 +432,50 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` + regfp = + RFull of (string) + | RSlice of ((string # ii # ii)) + | RSliceBit of ((string # ii)) + | RField of ((string # string))`; + + + + +val _ = type_abbrev( "regfps" , ``: regfp list``); + +val _ = Hol_datatype ` + niafp = + NIAFP_successor of (unit) + | NIAFP_concrete_address of ( 64 bits) + | NIAFP_indirect_address of (unit)`; + + + + +val _ = type_abbrev( "niafps" , ``: niafp list``); + +val _ = Hol_datatype ` + diafp = DIAFP_none of (unit) | DIAFP_concrete of ( 64 bits) | DIAFP_reg of (regfp)`; + + + + + + + + + + + + + + +val _ = Hol_datatype ` register_value = Regval_vector of ((ii # bool # register_value list)) | Regval_list of ( register_value list) | Regval_option of ( register_value option) + | Regval_Counteren of (Counteren) | Regval_Mcause of (Mcause) | Regval_Medeleg of (Medeleg) | Regval_Minterrupts of (Minterrupts) @@ -446,6 +486,7 @@ val _ = Hol_datatype ` | Regval_Sedeleg of (Sedeleg) | Regval_Sinterrupts of (Sinterrupts) | Regval_TLB39_Entry of (TLB39_Entry) + | Regval_bool of (bool) | Regval_vector_64_dec_bit of ( 64 words$word)`; @@ -454,6 +495,10 @@ val _ = Hol_datatype ` val _ = Hol_datatype ` regstate = <| tlb39 : TLB39_Entry option; + htif_exit_code : 64 words$word; + htif_done : bool; + htif_tohost : 64 words$word; + mtimecmp : 64 words$word; tselect : 64 words$word; stval : 64 words$word; scause : Mcause; @@ -469,9 +514,12 @@ val _ = Hol_datatype ` marchid : 64 words$word; mimpid : 64 words$word; mvendorid : 64 words$word; + minstret_written : bool; minstret : 64 words$word; mtime : 64 words$word; mcycle : 64 words$word; + scounteren : Counteren; + mcounteren : Counteren; mscratch : 64 words$word; mtval : 64 words$word; mepc : 64 words$word; @@ -485,6 +533,37 @@ val _ = Hol_datatype ` misa : Misa; cur_inst : 64 words$word; cur_privilege : Privilege; + x31 : 64 words$word; + x30 : 64 words$word; + x29 : 64 words$word; + x28 : 64 words$word; + x27 : 64 words$word; + x26 : 64 words$word; + x25 : 64 words$word; + x24 : 64 words$word; + x23 : 64 words$word; + x22 : 64 words$word; + x21 : 64 words$word; + x20 : 64 words$word; + x19 : 64 words$word; + x18 : 64 words$word; + x17 : 64 words$word; + x16 : 64 words$word; + x15 : 64 words$word; + x14 : 64 words$word; + x13 : 64 words$word; + x12 : 64 words$word; + x11 : 64 words$word; + x10 : 64 words$word; + x9 : 64 words$word; + x8 : 64 words$word; + x7 : 64 words$word; + x6 : 64 words$word; + x5 : 64 words$word; + x4 : 64 words$word; + x3 : 64 words$word; + x2 : 64 words$word; + x1 : 64 words$word; Xs : ( 64 words$word) list; nextPC : 64 words$word; PC : 64 words$word |>`; @@ -493,11 +572,24 @@ val _ = Hol_datatype ` +(*val Counteren_of_regval : register_value -> maybe Counteren*) + +val _ = Define ` + ((Counteren_of_regval:register_value ->(Counteren)option) merge_var= + ((case merge_var of Regval_Counteren (v) => SOME v | g__12 => NONE )))`; + + +(*val regval_of_Counteren : Counteren -> register_value*) + +val _ = Define ` + ((regval_of_Counteren:Counteren -> register_value) v= (Regval_Counteren v))`; + + (*val Mcause_of_regval : register_value -> maybe Mcause*) val _ = Define ` ((Mcause_of_regval:register_value ->(Mcause)option) merge_var= - ((case merge_var of Regval_Mcause (v) => SOME v | g__92 => NONE )))`; + ((case merge_var of Regval_Mcause (v) => SOME v | g__11 => NONE )))`; (*val regval_of_Mcause : Mcause -> register_value*) @@ -510,7 +602,7 @@ val _ = Define ` val _ = Define ` ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var= - ((case merge_var of Regval_Medeleg (v) => SOME v | g__91 => NONE )))`; + ((case merge_var of Regval_Medeleg (v) => SOME v | g__10 => NONE )))`; (*val regval_of_Medeleg : Medeleg -> register_value*) @@ -523,7 +615,7 @@ val _ = Define ` val _ = Define ` ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var= - ((case merge_var of Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`; + ((case merge_var of Regval_Minterrupts (v) => SOME v | g__9 => NONE )))`; (*val regval_of_Minterrupts : Minterrupts -> register_value*) @@ -536,7 +628,7 @@ val _ = Define ` val _ = Define ` ((Misa_of_regval:register_value ->(Misa)option) merge_var= - ((case merge_var of Regval_Misa (v) => SOME v | g__89 => NONE )))`; + ((case merge_var of Regval_Misa (v) => SOME v | g__8 => NONE )))`; (*val regval_of_Misa : Misa -> register_value*) @@ -549,7 +641,7 @@ val _ = Define ` val _ = Define ` ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var= - ((case merge_var of Regval_Mstatus (v) => SOME v | g__88 => NONE )))`; + ((case merge_var of Regval_Mstatus (v) => SOME v | g__7 => NONE )))`; (*val regval_of_Mstatus : Mstatus -> register_value*) @@ -562,7 +654,7 @@ val _ = Define ` val _ = Define ` ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var= - ((case merge_var of Regval_Mtvec (v) => SOME v | g__87 => NONE )))`; + ((case merge_var of Regval_Mtvec (v) => SOME v | g__6 => NONE )))`; (*val regval_of_Mtvec : Mtvec -> register_value*) @@ -575,7 +667,7 @@ val _ = Define ` val _ = Define ` ((Privilege_of_regval:register_value ->(Privilege)option) merge_var= - ((case merge_var of Regval_Privilege (v) => SOME v | g__86 => NONE )))`; + ((case merge_var of Regval_Privilege (v) => SOME v | g__5 => NONE )))`; (*val regval_of_Privilege : Privilege -> register_value*) @@ -588,7 +680,7 @@ val _ = Define ` val _ = Define ` ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var= - ((case merge_var of Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`; + ((case merge_var of Regval_Sedeleg (v) => SOME v | g__4 => NONE )))`; (*val regval_of_Sedeleg : Sedeleg -> register_value*) @@ -601,7 +693,7 @@ val _ = Define ` val _ = Define ` ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var= - ((case merge_var of Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`; + ((case merge_var of Regval_Sinterrupts (v) => SOME v | g__3 => NONE )))`; (*val regval_of_Sinterrupts : Sinterrupts -> register_value*) @@ -614,7 +706,7 @@ val _ = Define ` val _ = Define ` ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var= - ((case merge_var of Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`; + ((case merge_var of Regval_TLB39_Entry (v) => SOME v | g__2 => NONE )))`; (*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) @@ -623,11 +715,24 @@ val _ = Define ` ((regval_of_TLB39_Entry:TLB39_Entry -> register_value) v= (Regval_TLB39_Entry v))`; +(*val bool_of_regval : register_value -> maybe bool*) + +val _ = Define ` + ((bool_of_regval:register_value ->(bool)option) merge_var= + ((case merge_var of Regval_bool (v) => SOME v | g__1 => NONE )))`; + + +(*val regval_of_bool : bool -> register_value*) + +val _ = Define ` + ((regval_of_bool:bool -> register_value) v= (Regval_bool v))`; + + (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) val _ = Define ` ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var= - ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`; + ((case merge_var of Regval_vector_64_dec_bit (v) => SOME v | g__0 => NONE )))`; (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) @@ -640,44 +745,44 @@ val _ = Define ` (*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` - ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= (\x . (case x of - Regval_vector (_, _, v) => just_list (MAP of_regval v) + Regval_vector (_, _, v) => just_list (MAP of_regval1 v) | _ => NONE )))`; (*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) val _ = Define ` - ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of xs)))`; + ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of1 size1 is_inc xs= (Regval_vector (size1, is_inc, MAP regval_of1 xs)))`; (*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) val _ = Define ` - ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= + ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval1= (\x . (case x of - Regval_list v => just_list (MAP of_regval v) + Regval_list v => just_list (MAP of_regval1 v) | _ => NONE )))`; (*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) val _ = Define ` - ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs= (Regval_list (MAP regval_of xs)))`; + ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of1 xs= (Regval_list (MAP regval_of1 xs)))`; (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) val _ = Define ` - ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= + ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval1= (\x . (case x of - Regval_option v => SOME (OPTION_BIND v of_regval) + Regval_option v => SOME (OPTION_BIND v of_regval1) | _ => NONE )))`; (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) val _ = Define ` - ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v= (Regval_option (OPTION_MAP regval_of v)))`; + ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of1 v= (Regval_option (OPTION_MAP regval_of1 v)))`; @@ -691,6 +796,42 @@ val _ = Define ` val _ = Define ` + ((htif_exit_code_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "htif_exit_code"; + read_from := (\ s . s.htif_exit_code); + write_to := (\ v s . (( s with<| htif_exit_code := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((htif_done_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "htif_done"; + read_from := (\ s . s.htif_done); + write_to := (\ v s . (( s with<| htif_done := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` + ((htif_tohost_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "htif_tohost"; + read_from := (\ s . s.htif_tohost); + write_to := (\ v s . (( s with<| htif_tohost := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((mtimecmp_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "mtimecmp"; + read_from := (\ s . s.mtimecmp); + write_to := (\ v s . (( s with<| mtimecmp := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` ((tselect_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "tselect"; read_from := (\ s . s.tselect); @@ -826,6 +967,15 @@ val _ = Define ` val _ = Define ` + ((minstret_written_ref:((regstate),(register_value),(bool))register_ref)= (<| + name := "minstret_written"; + read_from := (\ s . s.minstret_written); + write_to := (\ v s . (( s with<| minstret_written := v |>))); + of_regval := (\ v . bool_of_regval v); + regval_of := (\ v . regval_of_bool v) |>))`; + + +val _ = Define ` ((minstret_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "minstret"; read_from := (\ s . s.minstret); @@ -853,6 +1003,24 @@ val _ = Define ` val _ = Define ` + ((scounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<| + name := "scounteren"; + read_from := (\ s . s.scounteren); + write_to := (\ v s . (( s with<| scounteren := v |>))); + of_regval := (\ v . Counteren_of_regval v); + regval_of := (\ v . regval_of_Counteren v) |>))`; + + +val _ = Define ` + ((mcounteren_ref:((regstate),(register_value),(Counteren))register_ref)= (<| + name := "mcounteren"; + read_from := (\ s . s.mcounteren); + write_to := (\ v s . (( s with<| mcounteren := v |>))); + of_regval := (\ v . Counteren_of_regval v); + regval_of := (\ v . regval_of_Counteren v) |>))`; + + +val _ = Define ` ((mscratch_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| name := "mscratch"; read_from := (\ s . s.mscratch); @@ -970,6 +1138,285 @@ val _ = Define ` val _ = Define ` + ((x31_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x31"; + read_from := (\ s . s.x31); + write_to := (\ v s . (( s with<| x31 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x30_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x30"; + read_from := (\ s . s.x30); + write_to := (\ v s . (( s with<| x30 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x29_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x29"; + read_from := (\ s . s.x29); + write_to := (\ v s . (( s with<| x29 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x28_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x28"; + read_from := (\ s . s.x28); + write_to := (\ v s . (( s with<| x28 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x27_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x27"; + read_from := (\ s . s.x27); + write_to := (\ v s . (( s with<| x27 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x26_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x26"; + read_from := (\ s . s.x26); + write_to := (\ v s . (( s with<| x26 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x25_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x25"; + read_from := (\ s . s.x25); + write_to := (\ v s . (( s with<| x25 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x24_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x24"; + read_from := (\ s . s.x24); + write_to := (\ v s . (( s with<| x24 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x23_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x23"; + read_from := (\ s . s.x23); + write_to := (\ v s . (( s with<| x23 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x22_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x22"; + read_from := (\ s . s.x22); + write_to := (\ v s . (( s with<| x22 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x21_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x21"; + read_from := (\ s . s.x21); + write_to := (\ v s . (( s with<| x21 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x20_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x20"; + read_from := (\ s . s.x20); + write_to := (\ v s . (( s with<| x20 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x19_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x19"; + read_from := (\ s . s.x19); + write_to := (\ v s . (( s with<| x19 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x18_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x18"; + read_from := (\ s . s.x18); + write_to := (\ v s . (( s with<| x18 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x17_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x17"; + read_from := (\ s . s.x17); + write_to := (\ v s . (( s with<| x17 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x16_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x16"; + read_from := (\ s . s.x16); + write_to := (\ v s . (( s with<| x16 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x15_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x15"; + read_from := (\ s . s.x15); + write_to := (\ v s . (( s with<| x15 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x14_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x14"; + read_from := (\ s . s.x14); + write_to := (\ v s . (( s with<| x14 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x13_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x13"; + read_from := (\ s . s.x13); + write_to := (\ v s . (( s with<| x13 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x12_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x12"; + read_from := (\ s . s.x12); + write_to := (\ v s . (( s with<| x12 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x11_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x11"; + read_from := (\ s . s.x11); + write_to := (\ v s . (( s with<| x11 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x10_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x10"; + read_from := (\ s . s.x10); + write_to := (\ v s . (( s with<| x10 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x9_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x9"; + read_from := (\ s . s.x9); + write_to := (\ v s . (( s with<| x9 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x8_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x8"; + read_from := (\ s . s.x8); + write_to := (\ v s . (( s with<| x8 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x7_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x7"; + read_from := (\ s . s.x7); + write_to := (\ v s . (( s with<| x7 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x6_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x6"; + read_from := (\ s . s.x6); + write_to := (\ v s . (( s with<| x6 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x5_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x5"; + read_from := (\ s . s.x5); + write_to := (\ v s . (( s with<| x5 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x4_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x4"; + read_from := (\ s . s.x4); + write_to := (\ v s . (( s with<| x4 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x3_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x3"; + read_from := (\ s . s.x3); + write_to := (\ v s . (( s with<| x3 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x2_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x2"; + read_from := (\ s . s.x2); + write_to := (\ v s . (( s with<| x2 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` + ((x1_ref:((regstate),(register_value),((64)words$word))register_ref)= (<| + name := "x1"; + read_from := (\ s . s.x1); + write_to := (\ v s . (( s with<| x1 := v |>))); + of_regval := (\ v . vector_64_dec_bit_of_regval v); + regval_of := (\ v . regval_of_vector_64_dec_bit v) |>))`; + + +val _ = Define ` ((Xs_ref:((regstate),(register_value),(((64)words$word)list))register_ref)= (<| name := "Xs"; read_from := (\ s . s.Xs); @@ -1000,6 +1447,10 @@ val _ = Define ` val _ = Define ` ((get_regval:string -> regstate ->(register_value)option) reg_name s= (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else + if reg_name = "htif_exit_code" then SOME (htif_exit_code_ref.regval_of (htif_exit_code_ref.read_from s)) else + if reg_name = "htif_done" then SOME (htif_done_ref.regval_of (htif_done_ref.read_from s)) else + if reg_name = "htif_tohost" then SOME (htif_tohost_ref.regval_of (htif_tohost_ref.read_from s)) else + if reg_name = "mtimecmp" then SOME (mtimecmp_ref.regval_of (mtimecmp_ref.read_from s)) else if reg_name = "tselect" then SOME (tselect_ref.regval_of (tselect_ref.read_from s)) else if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else @@ -1015,9 +1466,12 @@ val _ = Define ` if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else + if reg_name = "minstret_written" then SOME (minstret_written_ref.regval_of (minstret_written_ref.read_from s)) else if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else + if reg_name = "scounteren" then SOME (scounteren_ref.regval_of (scounteren_ref.read_from s)) else + if reg_name = "mcounteren" then SOME (mcounteren_ref.regval_of (mcounteren_ref.read_from s)) else if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else @@ -1031,6 +1485,37 @@ val _ = Define ` if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else + if reg_name = "x31" then SOME (x31_ref.regval_of (x31_ref.read_from s)) else + if reg_name = "x30" then SOME (x30_ref.regval_of (x30_ref.read_from s)) else + if reg_name = "x29" then SOME (x29_ref.regval_of (x29_ref.read_from s)) else + if reg_name = "x28" then SOME (x28_ref.regval_of (x28_ref.read_from s)) else + if reg_name = "x27" then SOME (x27_ref.regval_of (x27_ref.read_from s)) else + if reg_name = "x26" then SOME (x26_ref.regval_of (x26_ref.read_from s)) else + if reg_name = "x25" then SOME (x25_ref.regval_of (x25_ref.read_from s)) else + if reg_name = "x24" then SOME (x24_ref.regval_of (x24_ref.read_from s)) else + if reg_name = "x23" then SOME (x23_ref.regval_of (x23_ref.read_from s)) else + if reg_name = "x22" then SOME (x22_ref.regval_of (x22_ref.read_from s)) else + if reg_name = "x21" then SOME (x21_ref.regval_of (x21_ref.read_from s)) else + if reg_name = "x20" then SOME (x20_ref.regval_of (x20_ref.read_from s)) else + if reg_name = "x19" then SOME (x19_ref.regval_of (x19_ref.read_from s)) else + if reg_name = "x18" then SOME (x18_ref.regval_of (x18_ref.read_from s)) else + if reg_name = "x17" then SOME (x17_ref.regval_of (x17_ref.read_from s)) else + if reg_name = "x16" then SOME (x16_ref.regval_of (x16_ref.read_from s)) else + if reg_name = "x15" then SOME (x15_ref.regval_of (x15_ref.read_from s)) else + if reg_name = "x14" then SOME (x14_ref.regval_of (x14_ref.read_from s)) else + if reg_name = "x13" then SOME (x13_ref.regval_of (x13_ref.read_from s)) else + if reg_name = "x12" then SOME (x12_ref.regval_of (x12_ref.read_from s)) else + if reg_name = "x11" then SOME (x11_ref.regval_of (x11_ref.read_from s)) else + if reg_name = "x10" then SOME (x10_ref.regval_of (x10_ref.read_from s)) else + if reg_name = "x9" then SOME (x9_ref.regval_of (x9_ref.read_from s)) else + if reg_name = "x8" then SOME (x8_ref.regval_of (x8_ref.read_from s)) else + if reg_name = "x7" then SOME (x7_ref.regval_of (x7_ref.read_from s)) else + if reg_name = "x6" then SOME (x6_ref.regval_of (x6_ref.read_from s)) else + if reg_name = "x5" then SOME (x5_ref.regval_of (x5_ref.read_from s)) else + if reg_name = "x4" then SOME (x4_ref.regval_of (x4_ref.read_from s)) else + if reg_name = "x3" then SOME (x3_ref.regval_of (x3_ref.read_from s)) else + if reg_name = "x2" then SOME (x2_ref.regval_of (x2_ref.read_from s)) else + if reg_name = "x1" then SOME (x1_ref.regval_of (x1_ref.read_from s)) else if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else @@ -1041,6 +1526,10 @@ val _ = Define ` val _ = Define ` ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s= (if reg_name = "tlb39" then OPTION_MAP (\ v . tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else + if reg_name = "htif_exit_code" then OPTION_MAP (\ v . htif_exit_code_ref.write_to v s) (htif_exit_code_ref.of_regval v) else + if reg_name = "htif_done" then OPTION_MAP (\ v . htif_done_ref.write_to v s) (htif_done_ref.of_regval v) else + if reg_name = "htif_tohost" then OPTION_MAP (\ v . htif_tohost_ref.write_to v s) (htif_tohost_ref.of_regval v) else + if reg_name = "mtimecmp" then OPTION_MAP (\ v . mtimecmp_ref.write_to v s) (mtimecmp_ref.of_regval v) else if reg_name = "tselect" then OPTION_MAP (\ v . tselect_ref.write_to v s) (tselect_ref.of_regval v) else if reg_name = "stval" then OPTION_MAP (\ v . stval_ref.write_to v s) (stval_ref.of_regval v) else if reg_name = "scause" then OPTION_MAP (\ v . scause_ref.write_to v s) (scause_ref.of_regval v) else @@ -1056,9 +1545,12 @@ val _ = Define ` if reg_name = "marchid" then OPTION_MAP (\ v . marchid_ref.write_to v s) (marchid_ref.of_regval v) else if reg_name = "mimpid" then OPTION_MAP (\ v . mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else if reg_name = "mvendorid" then OPTION_MAP (\ v . mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else + if reg_name = "minstret_written" then OPTION_MAP (\ v . minstret_written_ref.write_to v s) (minstret_written_ref.of_regval v) else if reg_name = "minstret" then OPTION_MAP (\ v . minstret_ref.write_to v s) (minstret_ref.of_regval v) else if reg_name = "mtime" then OPTION_MAP (\ v . mtime_ref.write_to v s) (mtime_ref.of_regval v) else if reg_name = "mcycle" then OPTION_MAP (\ v . mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else + if reg_name = "scounteren" then OPTION_MAP (\ v . scounteren_ref.write_to v s) (scounteren_ref.of_regval v) else + if reg_name = "mcounteren" then OPTION_MAP (\ v . mcounteren_ref.write_to v s) (mcounteren_ref.of_regval v) else if reg_name = "mscratch" then OPTION_MAP (\ v . mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else if reg_name = "mtval" then OPTION_MAP (\ v . mtval_ref.write_to v s) (mtval_ref.of_regval v) else if reg_name = "mepc" then OPTION_MAP (\ v . mepc_ref.write_to v s) (mepc_ref.of_regval v) else @@ -1072,6 +1564,37 @@ val _ = Define ` if reg_name = "misa" then OPTION_MAP (\ v . misa_ref.write_to v s) (misa_ref.of_regval v) else if reg_name = "cur_inst" then OPTION_MAP (\ v . cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else if reg_name = "cur_privilege" then OPTION_MAP (\ v . cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else + if reg_name = "x31" then OPTION_MAP (\ v . x31_ref.write_to v s) (x31_ref.of_regval v) else + if reg_name = "x30" then OPTION_MAP (\ v . x30_ref.write_to v s) (x30_ref.of_regval v) else + if reg_name = "x29" then OPTION_MAP (\ v . x29_ref.write_to v s) (x29_ref.of_regval v) else + if reg_name = "x28" then OPTION_MAP (\ v . x28_ref.write_to v s) (x28_ref.of_regval v) else + if reg_name = "x27" then OPTION_MAP (\ v . x27_ref.write_to v s) (x27_ref.of_regval v) else + if reg_name = "x26" then OPTION_MAP (\ v . x26_ref.write_to v s) (x26_ref.of_regval v) else + if reg_name = "x25" then OPTION_MAP (\ v . x25_ref.write_to v s) (x25_ref.of_regval v) else + if reg_name = "x24" then OPTION_MAP (\ v . x24_ref.write_to v s) (x24_ref.of_regval v) else + if reg_name = "x23" then OPTION_MAP (\ v . x23_ref.write_to v s) (x23_ref.of_regval v) else + if reg_name = "x22" then OPTION_MAP (\ v . x22_ref.write_to v s) (x22_ref.of_regval v) else + if reg_name = "x21" then OPTION_MAP (\ v . x21_ref.write_to v s) (x21_ref.of_regval v) else + if reg_name = "x20" then OPTION_MAP (\ v . x20_ref.write_to v s) (x20_ref.of_regval v) else + if reg_name = "x19" then OPTION_MAP (\ v . x19_ref.write_to v s) (x19_ref.of_regval v) else + if reg_name = "x18" then OPTION_MAP (\ v . x18_ref.write_to v s) (x18_ref.of_regval v) else + if reg_name = "x17" then OPTION_MAP (\ v . x17_ref.write_to v s) (x17_ref.of_regval v) else + if reg_name = "x16" then OPTION_MAP (\ v . x16_ref.write_to v s) (x16_ref.of_regval v) else + if reg_name = "x15" then OPTION_MAP (\ v . x15_ref.write_to v s) (x15_ref.of_regval v) else + if reg_name = "x14" then OPTION_MAP (\ v . x14_ref.write_to v s) (x14_ref.of_regval v) else + if reg_name = "x13" then OPTION_MAP (\ v . x13_ref.write_to v s) (x13_ref.of_regval v) else + if reg_name = "x12" then OPTION_MAP (\ v . x12_ref.write_to v s) (x12_ref.of_regval v) else + if reg_name = "x11" then OPTION_MAP (\ v . x11_ref.write_to v s) (x11_ref.of_regval v) else + if reg_name = "x10" then OPTION_MAP (\ v . x10_ref.write_to v s) (x10_ref.of_regval v) else + if reg_name = "x9" then OPTION_MAP (\ v . x9_ref.write_to v s) (x9_ref.of_regval v) else + if reg_name = "x8" then OPTION_MAP (\ v . x8_ref.write_to v s) (x8_ref.of_regval v) else + if reg_name = "x7" then OPTION_MAP (\ v . x7_ref.write_to v s) (x7_ref.of_regval v) else + if reg_name = "x6" then OPTION_MAP (\ v . x6_ref.write_to v s) (x6_ref.of_regval v) else + if reg_name = "x5" then OPTION_MAP (\ v . x5_ref.write_to v s) (x5_ref.of_regval v) else + if reg_name = "x4" then OPTION_MAP (\ v . x4_ref.write_to v s) (x4_ref.of_regval v) else + if reg_name = "x3" then OPTION_MAP (\ v . x3_ref.write_to v s) (x3_ref.of_regval v) else + if reg_name = "x2" then OPTION_MAP (\ v . x2_ref.write_to v s) (x2_ref.of_regval v) else + if reg_name = "x1" then OPTION_MAP (\ v . x1_ref.write_to v s) (x1_ref.of_regval v) else if reg_name = "Xs" then OPTION_MAP (\ v . Xs_ref.write_to v s) (Xs_ref.of_regval v) else if reg_name = "nextPC" then OPTION_MAP (\ v . nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else if reg_name = "PC" then OPTION_MAP (\ v . PC_ref.write_to v s) (PC_ref.of_regval v) else |