diff options
Diffstat (limited to 'snapshots/isabelle/cheri')
| -rw-r--r-- | snapshots/isabelle/cheri/Cheri.thy | 10570 | ||||
| -rw-r--r-- | snapshots/isabelle/cheri/Cheri_lemmas.thy | 1205 | ||||
| -rw-r--r-- | snapshots/isabelle/cheri/Cheri_types.thy | 2432 | ||||
| -rw-r--r-- | snapshots/isabelle/cheri/Mips_extras.thy | 251 | ||||
| -rw-r--r-- | snapshots/isabelle/cheri/ROOT | 4 |
5 files changed, 14462 insertions, 0 deletions
diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy new file mode 100644 index 00000000..eed49a23 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri.thy @@ -0,0 +1,10570 @@ +chapter \<open>Generated by Lem from cheri.lem.\<close> + +theory "Cheri" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Cheri_types" + "Mips_extras" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Cheri_types*) +(*open import Mips_extras*) + +definition cap_size :: " int " where + " cap_size = ( (( 32 :: int)::ii))" + + +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where + " undefined_option typ_a = ( undefined_unit () \<then> internal_pick [None,Some typ_a])" + + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where + " neq_bool x y = ( \<not> (((x = y))))" + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MIPS_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MIPS_write addr width data = ( + write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data )" + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MIPS_read addr width = ( + (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'p8_times_n_::len)Word.word) M))" + + + + +(*val undefined_exception : unit -> M exception*) + +definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where + " undefined_exception _ = ( + (undefined_unit () \<then> + undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . + ((undefined_unit () \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + internal_pick + [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))" + + +(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition sign_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " sign_extend1 (m__tv :: int) v = ( (sign_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +definition zero_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " zero_extend1 (m__tv :: int) v = ( (zero_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition zeros0 :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where + " zeros0 (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition ones :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where + " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \<Rightarrow> bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val bits_to_bool : mword ty1 -> bool*) + +definition bits_to_bool :: "(1)Word.word \<Rightarrow> bool " where + " bits_to_bool x = ( bit_to_bool ((access_vec_dec x (( 0 :: int)::ii))))" + + +(* +function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. +*) +(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) + +definition to_bits :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where + " to_bits l n = ( + (let l = (size_itself_int l) in + (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) + +definition mask0 :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len)Word.word " where + " mask0 (n__tv :: int) bs = ( + (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))" + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) + j' + :: ( 'm::len)Word.word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) + ((j' - (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + +(*val undefined_CauseReg : unit -> M CauseReg*) + +definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where + " undefined_CauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + internal_pick [Mk_CauseReg w__0]))" + + +(*val _get_CauseReg : CauseReg -> mword ty32*) + +fun get_CauseReg :: " CauseReg \<Rightarrow>(32)Word.word " where + " get_CauseReg (Mk_CauseReg (v)) = ( v )" + + +(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) + +definition set_CauseReg :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_CauseReg v) in + write_reg r_ref r)))" + + +(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) + +(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) + +(*val _get_CauseReg_BD : CauseReg -> mword ty1*) + +fun get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_BD r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_BD (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_CE : CauseReg -> mword ty2*) + +fun get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where + " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" + + +(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) + +definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_CE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) + +fun update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_CE (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IV : CauseReg -> mword ty1*) + +fun get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_IV r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IV (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_WP : CauseReg -> mword ty1*) + +fun get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_WP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_WP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IP : CauseReg -> mword ty8*) + +fun get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where + " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) + +definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_IP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) + +fun update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) + +fun get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where + " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" + + +(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) + +definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_ExcCode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) + +fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) + +(*val _get_CapCauseReg_ExcCode : CapCauseReg -> mword ty8*) + +(*val _set_CapCauseReg_ExcCode : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) + +definition undefined_TLBEntryLoReg :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad " where + " undefined_TLBEntryLoReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryLoReg w__0]))" + + +(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) + +fun get_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )" + + +(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) + +definition set_TLBEntryLoReg :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntryLoReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) + +fun get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where + " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) + +definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_PFN r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) + +fun get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where + " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) + +definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_C r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_D r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_V r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_G r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) + +definition undefined_TLBEntryHiReg :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad " where + " undefined_TLBEntryHiReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryHiReg w__0]))" + + +(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) + +fun get_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )" + + +(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +definition set_TLBEntryHiReg :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntryHiReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) + +fun get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where + " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) + +definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_R r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) + +fun get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where + " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = ( + (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) + +definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_VPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) + +fun get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where + " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) + +definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_ASID r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_ContextReg : unit -> M ContextReg*) + +definition undefined_ContextReg :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad " where + " undefined_ContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_ContextReg w__0]))" + + +(*val _get_ContextReg : ContextReg -> mword ty64*) + +fun get_ContextReg :: " ContextReg \<Rightarrow>(64)Word.word " where + " get_ContextReg (Mk_ContextReg (v)) = ( v )" + + +(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +definition set_ContextReg :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_ContextReg v) in + write_reg r_ref r)))" + + +(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) + +fun get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where + " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" + + +(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) + +definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_PTEBase r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) + +fun update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) + +fun get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where + " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" + + +(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) + +definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_BadVPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) + +fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_XContextReg : unit -> M XContextReg*) + +definition undefined_XContextReg :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad " where + " undefined_XContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_XContextReg w__0]))" + + +(*val _get_XContextReg : XContextReg -> mword ty64*) + +fun get_XContextReg :: " XContextReg \<Rightarrow>(64)Word.word " where + " get_XContextReg (Mk_XContextReg (v)) = ( v )" + + +(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +definition set_XContextReg :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_XContextReg v) in + write_reg r_ref r)))" + + +(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) + +fun get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where + " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" + + +(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) + +definition set_XContextReg_XPTEBase :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XPTEBase r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) + +fun update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XR : XContextReg -> mword ty2*) + +fun get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where + " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" + + +(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) + +definition set_XContextReg_XR :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) + +fun update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XR (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) + +fun get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where + " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" + + +(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) + +definition set_XContextReg_XBadVPN2 :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XBadVPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) + +fun update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +definition TLBNumEntries :: " int " where + " TLBNumEntries = ( (( 64 :: int)::ii))" + + +definition TLBIndexMax :: "(6)Word.word " where + " TLBIndexMax = ( (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))" + + +(*val MAX : integer -> integer*) + +definition MAX :: " int \<Rightarrow> int " where + " MAX n = ( ((pow2 n)) - (( 1 :: int)::ii))" + + +definition MAX_U64 :: " int " where + " MAX_U64 = ( MAX (( 64 :: int)::ii))" + + +definition MAX_VA :: " int " where + " MAX_VA = ( MAX (( 40 :: int)::ii))" + + +definition MAX_PA :: " int " where + " MAX_PA = ( MAX (( 36 :: int)::ii))" + + +(*val undefined_TLBEntry : unit -> M TLBEntry*) + +definition undefined_TLBEntry :: " unit \<Rightarrow>((register_value),(TLBEntry),(exception))monad " where + " undefined_TLBEntry _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii) :: ( 117 Word.word) M) \<bind> (\<lambda> (w__0 :: 117 Word.word) . + internal_pick [Mk_TLBEntry w__0]))" + + +(*val _get_TLBEntry : TLBEntry -> mword ty117*) + +fun get_TLBEntry :: " TLBEntry \<Rightarrow>(117)Word.word " where + " get_TLBEntry (Mk_TLBEntry (v)) = ( v )" + + +(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +definition set_TLBEntry :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntry v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) + +fun get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where + " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) :: 16 Word.word))" + + +(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) + +definition set_TLBEntry_pagemask :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pagemask r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) + +fun update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_r : TLBEntry -> mword ty2*) + +fun get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where + " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) + +definition set_TLBEntry_r :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_r r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) + +fun update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_r (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) + +fun get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where + " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) + +definition set_TLBEntry_vpn2 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_vpn2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) + +fun update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) + +fun get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where + " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) + +definition set_TLBEntry_asid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_asid r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) + +fun update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_asid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_g : TLBEntry -> mword ty1*) + +fun get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_g :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_g r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_g (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) + +fun get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_valid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_valid r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_valid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_c1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_d1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_v1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_c0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_d0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_v0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 117 Word.word)))" + + +definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref)list " where + " TLBEntries = ( + [TLBEntry63_ref,TLBEntry62_ref,TLBEntry61_ref,TLBEntry60_ref,TLBEntry59_ref,TLBEntry58_ref, + TLBEntry57_ref,TLBEntry56_ref,TLBEntry55_ref,TLBEntry54_ref,TLBEntry53_ref,TLBEntry52_ref, + TLBEntry51_ref,TLBEntry50_ref,TLBEntry49_ref,TLBEntry48_ref,TLBEntry47_ref,TLBEntry46_ref, + TLBEntry45_ref,TLBEntry44_ref,TLBEntry43_ref,TLBEntry42_ref,TLBEntry41_ref,TLBEntry40_ref, + TLBEntry39_ref,TLBEntry38_ref,TLBEntry37_ref,TLBEntry36_ref,TLBEntry35_ref,TLBEntry34_ref, + TLBEntry33_ref,TLBEntry32_ref,TLBEntry31_ref,TLBEntry30_ref,TLBEntry29_ref,TLBEntry28_ref, + TLBEntry27_ref,TLBEntry26_ref,TLBEntry25_ref,TLBEntry24_ref,TLBEntry23_ref,TLBEntry22_ref, + TLBEntry21_ref,TLBEntry20_ref,TLBEntry19_ref,TLBEntry18_ref,TLBEntry17_ref,TLBEntry16_ref, + TLBEntry15_ref,TLBEntry14_ref,TLBEntry13_ref,TLBEntry12_ref,TLBEntry11_ref,TLBEntry10_ref, + TLBEntry09_ref,TLBEntry08_ref,TLBEntry07_ref,TLBEntry06_ref,TLBEntry05_ref,TLBEntry04_ref, + TLBEntry03_ref,TLBEntry02_ref,TLBEntry01_ref,TLBEntry00_ref])" + + +(*val undefined_StatusReg : unit -> M StatusReg*) + +definition undefined_StatusReg :: " unit \<Rightarrow>((register_value),(StatusReg),(exception))monad " where + " undefined_StatusReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + internal_pick [Mk_StatusReg w__0]))" + + +(*val _get_StatusReg : StatusReg -> mword ty32*) + +fun get_StatusReg :: " StatusReg \<Rightarrow>(32)Word.word " where + " get_StatusReg (Mk_StatusReg (v)) = ( v )" + + +(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) + +definition set_StatusReg :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_StatusReg v) in + write_reg r_ref r)))" + + +(*val _get_StatusReg_CU : StatusReg -> mword ty4*) + +fun get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where + " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" + + +(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) + +definition set_StatusReg_CU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_CU r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) + +fun update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_CU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_BEV : StatusReg -> mword ty1*) + +fun get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_BEV :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_BEV r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_BEV (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IM : StatusReg -> mword ty8*) + +fun get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where + " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) + +definition set_StatusReg_IM :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_IM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) + +fun update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IM (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KX : StatusReg -> mword ty1*) + +fun get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_KX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_KX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_SX : StatusReg -> mword ty1*) + +fun get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_SX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_SX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_SX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_UX : StatusReg -> mword ty1*) + +fun get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_UX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_UX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_UX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KSU : StatusReg -> mword ty2*) + +fun get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where + " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" + + +(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) + +definition set_StatusReg_KSU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_KSU r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) + +fun update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KSU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_ERL : StatusReg -> mword ty1*) + +fun get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_ERL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_ERL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_ERL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_EXL : StatusReg -> mword ty1*) + +fun get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_EXL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_EXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_EXL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IE : StatusReg -> mword ty1*) + +fun get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_IE :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_IE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IE (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 32 Word.word)))" + + +(*val execute_branch : mword ty64 -> M unit*) + +definition execute_branch :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_branch pc = ( + write_reg delayedPC_ref pc \<then> write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val NotWordVal : mword ty64 -> bool*) + +definition NotWordVal :: "(64)Word.word \<Rightarrow> bool " where + " NotWordVal word1 = ( + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word1 (( 31 :: int)::ii))) :: 1 Word.word)) (( 32 :: int)::ii) + :: 32 Word.word)) \<noteq> ((subrange_vec_dec word1 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))))" + + +(*val rGPR : mword ty5 -> M (mword ty64)*) + +definition rGPR :: "(5)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " rGPR idx = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . + return ((access_list_dec w__0 i :: 64 Word.word)))))" + + +(*val wGPR : mword ty5 -> mword ty64 -> M unit*) + +definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " wGPR idx v = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then return () + else + read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list)))))" + + + + + + + + + + + + + + + + +(*val Exception_of_num : integer -> Exception*) + +definition Exception_of_num :: " int \<Rightarrow> Exception " where + " Exception_of_num arg0 = ( + (let l__81 = arg0 in + if (((l__81 = (( 0 :: int)::ii)))) then Interrupt + else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod + else if (((l__81 = (( 2 :: int)::ii)))) then TLBL + else if (((l__81 = (( 3 :: int)::ii)))) then TLBS + else if (((l__81 = (( 4 :: int)::ii)))) then AdEL + else if (((l__81 = (( 5 :: int)::ii)))) then AdES + else if (((l__81 = (( 6 :: int)::ii)))) then Sys + else if (((l__81 = (( 7 :: int)::ii)))) then Bp + else if (((l__81 = (( 8 :: int)::ii)))) then ResI + else if (((l__81 = (( 9 :: int)::ii)))) then CpU + else if (((l__81 = (( 10 :: int)::ii)))) then Ov + else if (((l__81 = (( 11 :: int)::ii)))) then Tr + else if (((l__81 = (( 12 :: int)::ii)))) then C2E + else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap + else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL + else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS + else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL + else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS + else MCheck))" + + +(*val num_of_Exception : Exception -> integer*) + +fun num_of_Exception :: " Exception \<Rightarrow> int " where + " num_of_Exception Interrupt = ( (( 0 :: int)::ii))" +|" num_of_Exception TLBMod = ( (( 1 :: int)::ii))" +|" num_of_Exception TLBL = ( (( 2 :: int)::ii))" +|" num_of_Exception TLBS = ( (( 3 :: int)::ii))" +|" num_of_Exception AdEL = ( (( 4 :: int)::ii))" +|" num_of_Exception AdES = ( (( 5 :: int)::ii))" +|" num_of_Exception Sys = ( (( 6 :: int)::ii))" +|" num_of_Exception Bp = ( (( 7 :: int)::ii))" +|" num_of_Exception ResI = ( (( 8 :: int)::ii))" +|" num_of_Exception CpU = ( (( 9 :: int)::ii))" +|" num_of_Exception Ov = ( (( 10 :: int)::ii))" +|" num_of_Exception Tr = ( (( 11 :: int)::ii))" +|" num_of_Exception C2E = ( (( 12 :: int)::ii))" +|" num_of_Exception C2Trap = ( (( 13 :: int)::ii))" +|" num_of_Exception XTLBRefillL = ( (( 14 :: int)::ii))" +|" num_of_Exception XTLBRefillS = ( (( 15 :: int)::ii))" +|" num_of_Exception XTLBInvL = ( (( 16 :: int)::ii))" +|" num_of_Exception XTLBInvS = ( (( 17 :: int)::ii))" +|" num_of_Exception MCheck = ( (( 18 :: int)::ii))" + + +(*val undefined_Exception : unit -> M Exception*) + +definition undefined_Exception :: " unit \<Rightarrow>((register_value),(Exception),(exception))monad " where + " undefined_Exception _ = ( + internal_pick + [Interrupt,TLBMod,TLBL,TLBS,AdEL,AdES,Sys,Bp,ResI,CpU,Ov,Tr,C2E,C2Trap,XTLBRefillL,XTLBRefillS,XTLBInvL,XTLBInvS,MCheck])" + + +(*val ExceptionCode : Exception -> mword ty5*) + +definition ExceptionCode :: " Exception \<Rightarrow>(5)Word.word " where + " ExceptionCode ex = ( + (let (x :: 8 bits) = + ((case ex of + Interrupt => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + | TLBMod => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word) + | TLBL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | TLBS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | AdEL => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word) + | AdES => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word) + | Sys => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word) + | Bp => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word) + | ResI => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word) + | CpU => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word) + | Ov => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B0] :: 8 Word.word) + | Tr => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B1] :: 8 Word.word) + | C2E => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | C2Trap => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | XTLBInvL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBInvS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | MCheck => (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word) + )) in + (subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)))" + + +(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionMIPS :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionMIPS ex kccBase = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + ((if ((\<not> ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg inBranchDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + write_reg CP0EPC_ref ((sub_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)) \<then> + set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] :: 1 Word.word)) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + write_reg CP0EPC_ref w__3 \<then> set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] :: 1 Word.word))) + else return () ) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__4 :: StatusReg) . + (let vectorOffset = + (if ((bits_to_bool ((get_StatusReg_EXL w__4 :: 1 Word.word)))) then + (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if ((((((ex = XTLBRefillL))) \<or> (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if (((ex = C2Trap))) then (vec_of_bits [B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__5 :: StatusReg) . + (let (vectorBase :: 64 bits) = + (if ((bits_to_bool ((get_StatusReg_BEV w__5 :: 1 Word.word)))) then + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) in + ((write_reg + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) + kccBase + :: 64 Word.word)) \<then> + set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex :: 5 Word.word))) \<then> + set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] :: 1 Word.word)) \<then> throw (ISAException () )))))))" + + +(*val SignalException : forall 'o. Exception -> M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*) + +(*val capRegToCapStruct : mword ty257 -> CapStruct*) + +definition capRegToCapStruct :: "(257)Word.word \<Rightarrow> CapStruct " where + " capRegToCapStruct capReg = ( + (| CapStruct_tag = ((bit_to_bool ((access_vec_dec capReg (( 256 :: int)::ii))))), + CapStruct_padding = ((subrange_vec_dec capReg (( 255 :: int)::ii) (( 248 :: int)::ii) :: 8 Word.word)), + CapStruct_otype = ((subrange_vec_dec capReg (( 247 :: int)::ii) (( 224 :: int)::ii) :: 24 Word.word)), + CapStruct_uperms = ((subrange_vec_dec capReg (( 223 :: int)::ii) (( 208 :: int)::ii) :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((subrange_vec_dec capReg (( 207 :: int)::ii) (( 204 :: int)::ii) :: 4 Word.word)), + CapStruct_access_system_regs = ((bit_to_bool ((access_vec_dec capReg (( 203 :: int)::ii))))), + CapStruct_permit_unseal = ((bit_to_bool ((access_vec_dec capReg (( 202 :: int)::ii))))), + CapStruct_permit_ccall = ((bit_to_bool ((access_vec_dec capReg (( 201 :: int)::ii))))), + CapStruct_permit_seal = ((bit_to_bool ((access_vec_dec capReg (( 200 :: int)::ii))))), + CapStruct_permit_store_local_cap = ((bit_to_bool ((access_vec_dec capReg (( 199 :: int)::ii))))), + CapStruct_permit_store_cap = ((bit_to_bool ((access_vec_dec capReg (( 198 :: int)::ii))))), + CapStruct_permit_load_cap = ((bit_to_bool ((access_vec_dec capReg (( 197 :: int)::ii))))), + CapStruct_permit_store = ((bit_to_bool ((access_vec_dec capReg (( 196 :: int)::ii))))), + CapStruct_permit_load = ((bit_to_bool ((access_vec_dec capReg (( 195 :: int)::ii))))), + CapStruct_permit_execute = ((bit_to_bool ((access_vec_dec capReg (( 194 :: int)::ii))))), + CapStruct_global = ((bit_to_bool ((access_vec_dec capReg (( 193 :: int)::ii))))), + CapStruct_sealed = ((bit_to_bool ((access_vec_dec capReg (( 192 :: int)::ii))))), + CapStruct_address = ((subrange_vec_dec capReg (( 191 :: int)::ii) (( 128 :: int)::ii) :: 64 Word.word)), + CapStruct_base = ((subrange_vec_dec capReg (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)), + CapStruct_length = ((subrange_vec_dec capReg (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + + +(*val getCapPerms : CapStruct -> mword ty31*) + +definition getCapPerms :: " CapStruct \<Rightarrow>(31)Word.word " where + " getCapPerms cap = ( + (concat_vec(CapStruct_uperms cap) + ((concat_vec(CapStruct_perm_reserved11_14 cap) + ((concat_vec ((bool_to_bits(CapStruct_access_system_regs cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_unseal cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_ccall cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_seal cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_local_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_execute cap) + :: 1 Word.word)) + ((bool_to_bits(CapStruct_global cap) :: 1 Word.word)) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 8 Word.word)) + :: 9 Word.word)) + :: 10 Word.word)) + :: 11 Word.word)) + :: 15 Word.word)) + :: 31 Word.word))" + + +(*val capStructToMemBits256 : CapStruct -> mword ty256*) + +definition capStructToMemBits256 :: " CapStruct \<Rightarrow>(256)Word.word " where + " capStructToMemBits256 cap = ( + (concat_vec(CapStruct_padding cap) + ((concat_vec(CapStruct_otype cap) + ((concat_vec ((getCapPerms cap :: 31 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_sealed cap) :: 1 Word.word)) + ((concat_vec(CapStruct_address cap) + ((concat_vec(CapStruct_base cap)(CapStruct_length cap) :: 128 Word.word)) + :: 192 Word.word)) + :: 193 Word.word)) + :: 224 Word.word)) + :: 248 Word.word)) + :: 256 Word.word))" + + +(*val capStructToCapReg : CapStruct -> mword ty257*) + +definition capStructToCapReg :: " CapStruct \<Rightarrow>(257)Word.word " where + " capStructToCapReg cap = ( + (concat_vec ((bool_to_bits(CapStruct_tag cap) :: 1 Word.word)) + ((capStructToMemBits256 cap :: 256 Word.word)) + :: 257 Word.word))" + + +(*val getCapBase : CapStruct -> integer*) + +definition getCapBase :: " CapStruct \<Rightarrow> int " where + " getCapBase c = ( Word.uint(CapStruct_base c))" + + +definition null_cap :: " CapStruct " where + " null_cap = ( + (| CapStruct_tag = False, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((zeros0 (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = False, + CapStruct_permit_unseal = False, + CapStruct_permit_ccall = False, + CapStruct_permit_seal = False, + CapStruct_permit_store_local_cap = False, + CapStruct_permit_store_cap = False, + CapStruct_permit_load_cap = False, + CapStruct_permit_store = False, + CapStruct_permit_load = False, + CapStruct_permit_execute = False, + CapStruct_global = False, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +(*val int_to_cap : mword ty64 -> CapStruct*) + +definition int_to_cap :: "(64)Word.word \<Rightarrow> CapStruct " where + " int_to_cap address = ( (null_cap (| CapStruct_address := address |)))" + + +(* +Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). + *) +(*val setCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition setCapOffset :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct " where + " setCapOffset c offset = ( + (True, (c (| CapStruct_address := ((add_vec(CapStruct_base c) offset :: 64 Word.word))|))))" + + +definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalException ex = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + ((if ((\<not> ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> pc . + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (let (success, epcc) = (setCapOffset pcc pc) in + if success then write_reg C31_ref ((capStructToCapReg epcc :: 257 Word.word)) + else + write_reg + C31_ref + ((capStructToCapReg + ((int_to_cap + ((add_vec_int + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase pcc)) + :: 64 Word.word)) ((Word.uint pc)) + :: 64 Word.word)))) + :: 257 Word.word)))))) + else return () ) \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . + (write_reg nextPCC_ref w__2 \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . + (write_reg delayedPCC_ref w__3 \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + (let base = (getCapBase ((capRegToCapStruct w__4))) in + SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) base :: 64 Word.word))))))))" + + +definition SignalExceptionBadAddr :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionBadAddr ex badAddr = ( write_reg CP0BadVAddr_ref badAddr \<then> SignalException ex )" + + +(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionTLB :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionTLB ex badAddr = ( + (((((write_reg CP0BadVAddr_ref badAddr \<then> + set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 :: int)::ii) (( 13 :: int)::ii) :: 19 Word.word))) \<then> + set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \<then> + set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + SignalException ex )" + + +(*val MemAccessType_of_num : integer -> MemAccessType*) + +definition MemAccessType_of_num :: " int \<Rightarrow> MemAccessType " where + " MemAccessType_of_num arg0 = ( + (let l__79 = arg0 in + if (((l__79 = (( 0 :: int)::ii)))) then Instruction + else if (((l__79 = (( 1 :: int)::ii)))) then LoadData + else StoreData))" + + +(*val num_of_MemAccessType : MemAccessType -> integer*) + +fun num_of_MemAccessType :: " MemAccessType \<Rightarrow> int " where + " num_of_MemAccessType Instruction = ( (( 0 :: int)::ii))" +|" num_of_MemAccessType LoadData = ( (( 1 :: int)::ii))" +|" num_of_MemAccessType StoreData = ( (( 2 :: int)::ii))" + + +(*val undefined_MemAccessType : unit -> M MemAccessType*) + +definition undefined_MemAccessType :: " unit \<Rightarrow>((register_value),(MemAccessType),(exception))monad " where + " undefined_MemAccessType _ = ( internal_pick [Instruction,LoadData,StoreData])" + + +(*val AccessLevel_of_num : integer -> AccessLevel*) + +definition AccessLevel_of_num :: " int \<Rightarrow> AccessLevel " where + " AccessLevel_of_num arg0 = ( + (let l__77 = arg0 in + if (((l__77 = (( 0 :: int)::ii)))) then User + else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + else Kernel))" + + +(*val num_of_AccessLevel : AccessLevel -> integer*) + +fun num_of_AccessLevel :: " AccessLevel \<Rightarrow> int " where + " num_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" num_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" num_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(*val undefined_AccessLevel : unit -> M AccessLevel*) + +definition undefined_AccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel),(exception))monad " where + " undefined_AccessLevel _ = ( internal_pick [User,Supervisor,Kernel])" + + +(*val int_of_AccessLevel : AccessLevel -> ii*) + +fun int_of_AccessLevel :: " AccessLevel \<Rightarrow> int " where + " int_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" int_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" int_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(* +Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + *) +(*val grantsAccess : AccessLevel -> AccessLevel -> bool*) + +definition grantsAccess :: " AccessLevel \<Rightarrow> AccessLevel \<Rightarrow> bool " where + " grantsAccess currentLevel requiredLevel = ( + ((int_of_AccessLevel currentLevel)) \<ge> ((int_of_AccessLevel requiredLevel)))" + + +(* +Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. + *) +(*val getAccessLevel : unit -> M AccessLevel*) + +definition getAccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel),(exception))monad " where + " getAccessLevel _ = ( + or_boolM + (read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) + (read_reg CP0Status_ref \<bind> (\<lambda> (w__1 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_ERL w__1 :: 1 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then return Kernel + else + read_reg CP0Status_ref \<bind> (\<lambda> (w__3 :: StatusReg) . + (let p__133 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in + (let b__0 = p__133 in + return (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then User + else User))))))" + + +(*val checkCP0Access : unit -> M unit*) + +definition checkCP0Access :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkCP0Access _ = ( + getAccessLevel () \<bind> (\<lambda> accessLevel . + and_boolM (return (((accessLevel \<noteq> Kernel)))) + (read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + return ((\<not> ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii))))))))) \<bind> (\<lambda> (w__1 :: + bool) . + if w__1 then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0,B0] :: 2 Word.word) \<then> SignalException CpU + else return () )))" + + +(*val incrementCP0Count : unit -> M unit*) + +definition incrementCP0Count :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " incrementCP0Count _ = ( + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__1 :: 6 Word.word) . + (if (((w__0 = w__1))) then return TLBIndexMax + else + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__2 :: 6 Word.word) . + return ((sub_vec_int w__2 (( 1 :: int)::ii) :: 6 Word.word)))) \<bind> (\<lambda> (w__3 :: 6 Word.word) . + (write_reg TLBRandom_ref w__3 \<then> + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (write_reg CP0Count_ref ((add_vec_int w__4 (( 1 :: int)::ii) :: 32 Word.word)) \<then> + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 bits) . + (read_reg CP0Compare_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + ((if (((w__5 = w__6))) then + read_reg CP0Cause_ref \<bind> (\<lambda> (w__7 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 :: 8 Word.word)) + (vec_of_bits [B1,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + :: 8 Word.word))) + else return () ) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__8 :: StatusReg) . + (let ims = ((get_StatusReg_IM w__8 :: 8 Word.word)) in + read_reg CP0Cause_ref \<bind> (\<lambda> (w__9 :: CauseReg) . + (let ips = ((get_CauseReg_IP w__9 :: 8 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__10 :: StatusReg) . + (let ie = ((get_StatusReg_IE w__10 :: 1 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__11 :: StatusReg) . + (let exl = ((get_StatusReg_EXL w__11 :: 1 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__12 :: StatusReg) . + (let erl = ((get_StatusReg_ERL w__12 :: 1 Word.word)) in + if (((((\<not> ((bits_to_bool exl)))) \<and> (((((\<not> ((bits_to_bool erl)))) \<and> (((((bits_to_bool ie)) \<and> (((((and_vec ips ims :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))))))))) then + SignalException Interrupt + else return () )))))))))))))))))" + + +(*val decode_failure_of_num : integer -> decode_failure*) + +definition decode_failure_of_num :: " int \<Rightarrow> decode_failure " where + " decode_failure_of_num arg0 = ( + (let l__74 = arg0 in + if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern + else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction + else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction + else Internal_error))" + + +(*val num_of_decode_failure : decode_failure -> integer*) + +definition num_of_decode_failure :: " decode_failure \<Rightarrow> int " where + " num_of_decode_failure no_matching_pattern = ( (( 0 :: int)::ii))" + + +(*val undefined_decode_failure : unit -> M decode_failure*) + +definition undefined_decode_failure :: " unit \<Rightarrow>((register_value),(decode_failure),(exception))monad " where + " undefined_decode_failure _ = ( + internal_pick [No_matching_pattern,Unsupported_instruction,Illegal_instruction,Internal_error])" + + +(*val Comparison_of_num : integer -> Comparison*) + +definition Comparison_of_num :: " int \<Rightarrow> Comparison " where + " Comparison_of_num arg0 = ( + (let l__67 = arg0 in + if (((l__67 = (( 0 :: int)::ii)))) then EQ' + else if (((l__67 = (( 1 :: int)::ii)))) then NE + else if (((l__67 = (( 2 :: int)::ii)))) then GE + else if (((l__67 = (( 3 :: int)::ii)))) then GEU + else if (((l__67 = (( 4 :: int)::ii)))) then GT' + else if (((l__67 = (( 5 :: int)::ii)))) then LE + else if (((l__67 = (( 6 :: int)::ii)))) then LT' + else LTU))" + + +(*val num_of_Comparison : Comparison -> integer*) + +fun num_of_Comparison :: " Comparison \<Rightarrow> int " where + " num_of_Comparison EQ' = ( (( 0 :: int)::ii))" +|" num_of_Comparison NE = ( (( 1 :: int)::ii))" +|" num_of_Comparison GE = ( (( 2 :: int)::ii))" +|" num_of_Comparison GEU = ( (( 3 :: int)::ii))" +|" num_of_Comparison GT' = ( (( 4 :: int)::ii))" +|" num_of_Comparison LE = ( (( 5 :: int)::ii))" +|" num_of_Comparison LT' = ( (( 6 :: int)::ii))" +|" num_of_Comparison LTU = ( (( 7 :: int)::ii))" + + +(*val undefined_Comparison : unit -> M Comparison*) + +definition undefined_Comparison :: " unit \<Rightarrow>((register_value),(Comparison),(exception))monad " where + " undefined_Comparison _ = ( internal_pick [EQ',NE,GE,GEU,GT',LE,LT',LTU])" + + +(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) + +fun compare :: " Comparison \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> bool " where + " compare EQ' valA valB = ( (valA = valB))" +|" compare NE valA valB = ( (valA \<noteq> valB))" +|" compare GE valA valB = ( zopz0zKzJ_s valA valB )" +|" compare GEU valA valB = ( zopz0zKzJ_u valA valB )" +|" compare GT' valA valB = ( zopz0zI_s valB valA )" +|" compare LE valA valB = ( zopz0zKzJ_s valB valA )" +|" compare LT' valA valB = ( zopz0zI_s valA valB )" +|" compare LTU valA valB = ( zopz0zI_u valA valB )" + + +(*val WordType_of_num : integer -> WordType*) + +definition WordType_of_num :: " int \<Rightarrow> WordType " where + " WordType_of_num arg0 = ( + (let l__64 = arg0 in + if (((l__64 = (( 0 :: int)::ii)))) then B + else if (((l__64 = (( 1 :: int)::ii)))) then H + else if (((l__64 = (( 2 :: int)::ii)))) then W + else D))" + + +(*val num_of_WordType : WordType -> integer*) + +fun num_of_WordType :: " WordType \<Rightarrow> int " where + " num_of_WordType B = ( (( 0 :: int)::ii))" +|" num_of_WordType H = ( (( 1 :: int)::ii))" +|" num_of_WordType W = ( (( 2 :: int)::ii))" +|" num_of_WordType D = ( (( 3 :: int)::ii))" + + +(*val undefined_WordType : unit -> M WordType*) + +definition undefined_WordType :: " unit \<Rightarrow>((register_value),(WordType),(exception))monad " where + " undefined_WordType _ = ( internal_pick [B,H,W,D])" + + +(*val wordWidthBytes : WordType -> integer*) + +fun wordWidthBytes :: " WordType \<Rightarrow> int " where + " wordWidthBytes B = ( (( 1 :: int)::ii))" +|" wordWidthBytes H = ( (( 2 :: int)::ii))" +|" wordWidthBytes W = ( (( 4 :: int)::ii))" +|" wordWidthBytes D = ( (( 8 :: int)::ii))" + + +definition alignment_width :: " int " where + " alignment_width = ( (( 16 :: int)::ii))" + + +(*val isAddressAligned : mword ty64 -> WordType -> bool*) + +definition isAddressAligned :: "(64)Word.word \<Rightarrow> WordType \<Rightarrow> bool " where + " isAddressAligned addr wordType = ( + (let a = (Word.uint addr) in + (((a div alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 :: int)::ii))) div + alignment_width)))))" + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_wrapper addr size1 = ( + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_reserve_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_reserve_wrapper addr size1 = ( + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val init_cp0_state : unit -> M unit*) + +definition init_cp0_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_cp0_state _ = ( set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 :: 1 Word.word)))" + + +(*val init_cp2_state : unit -> M unit*) + +(*val cp2_next_pc : unit -> M unit*) + +(*val dump_cp2_state : unit -> M unit*) + +(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) + +definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry \<Rightarrow> bool " where + " tlbEntryMatch r vpn2 asid entry = ( + (let entryValid = ((get_TLBEntry_valid entry :: 1 Word.word)) in + (let entryR = ((get_TLBEntry_r entry :: 2 Word.word)) in + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let entryVPN = ((get_TLBEntry_vpn2 entry :: 27 Word.word)) in + (let entryASID = ((get_TLBEntry_asid entry :: 8 Word.word)) in + (let entryG = ((get_TLBEntry_g entry :: 1 Word.word)) in + (let (vpnMask :: 27 bits) = + ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in + (((bits_to_bool entryValid)) \<and> ((((((r = entryR))) \<and> ((((((((and_vec vpn2 vpnMask :: 27 Word.word)) = ((and_vec entryVPN vpnMask :: 27 Word.word))))) \<and> ((((((asid = entryASID))) \<or> ((bits_to_bool entryG))))))))))))))))))))" + + +(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) + +definition tlbSearch :: "(64)Word.word \<Rightarrow>((register_value),(((6)Word.word)option),(exception))monad " where + " tlbSearch VAddr = ( + catch_early_return + ((let r = ((subrange_vec_dec VAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let vpn2 = ((subrange_vec_dec VAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word)) in + liftR (read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let asid = ((get_TLBEntryHiReg_ASID w__0 :: 8 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) (( 63 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> idx unit_var . + liftR (reg_deref ((access_list_dec TLBEntries idx))) \<bind> (\<lambda> (w__1 :: TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return (Some ((to_bits ((make_the_value (( 6 :: int)::ii) :: 6 itself)) idx :: 6 Word.word))) :: (unit, ( ( 6 Word.word)option)) + MR) + else return () ))) \<then> + return None))))))" + + +(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslate2 :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslate2 vAddr accessType = ( + (tlbSearch vAddr :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> idx . + (case idx of + Some (idx) => + (let i = (Word.uint idx) in + reg_deref ((access_list_dec TLBEntries i)) \<bind> (\<lambda> entry . + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let b__0 = entryMask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + return (( 12 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) + then + return (( 14 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 16 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 18 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 20 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 22 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 24 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 26 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 28 :: int)::ii) + else undefined_range (( 12 :: int)::ii) (( 28 :: int)::ii)) \<bind> (\<lambda> (evenOddBit :: int) . + (let isOdd = (access_vec_dec vAddr evenOddBit) in + (let ((caps :: 1 bits), (capl :: 1 bits), (pfn :: 24 bits), (d :: 1 bits), (v :: 1 bits)) = + (if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry :: 1 Word.word), + (get_TLBEntry_capl1 entry :: 1 Word.word), + (get_TLBEntry_pfn1 entry :: 24 Word.word), + (get_TLBEntry_d1 entry :: 1 Word.word), + (get_TLBEntry_v1 entry :: 1 Word.word)) + else + ((get_TLBEntry_caps0 entry :: 1 Word.word), + (get_TLBEntry_capl0 entry :: 1 Word.word), + (get_TLBEntry_pfn0 entry :: 24 Word.word), + (get_TLBEntry_d0 entry :: 1 Word.word), + (get_TLBEntry_v0 entry :: 1 Word.word))) in + if ((\<not> ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + :: (( 64 Word.word * bool)) M) + else if ((((((accessType = StoreData))) \<and> ((\<not> ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr :: (( 64 Word.word * bool)) M) + else + (let (res :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) + ((subrange_subrange_concat + (((((((( 23 :: int)::ii) - + ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii))))) + + + ((evenOddBit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) pfn + (( 23 :: int)::ii) ((evenOddBit - (( 12 :: int)::ii))) vAddr + ((evenOddBit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 36 Word.word)) + :: 64 Word.word)) in + return (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))))))))) + | None => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + :: (( 64 Word.word * bool)) M) + )))" + + +(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslateC vAddr accessType = ( + getAccessLevel () \<bind> (\<lambda> currentAccessLevel . + (let compat32 = + (((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 31 :: int)::ii) :: 31 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1] + :: 31 Word.word)) in + (let b__0 = ((subrange_vec_dec vAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let ((requiredLevel :: AccessLevel), (addr :: ( 64 bits)option)) = + (if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) of + (True, b__1) => + if (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then (Kernel, None) + else if (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then (Supervisor, None) + else if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + else + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + | (g__131, g__132) => (Kernel, None) + ) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((subrange_vec_dec vAddr (( 58 :: int)::ii) (( 0 :: int)::ii) :: 59 Word.word)) + :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then (Supervisor, None) + else (User, None)) in + if ((\<not> ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else + (case addr of + Some (a) => return (a, False) + | None => + if (((((\<not> compat32)) \<and> ((((Word.uint ((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else (TLBTranslate2 vAddr accessType :: (( 64 Word.word * bool)) M) + ) \<bind> (\<lambda> varstup . (let ((pa :: 64 bits), (c :: bool)) = varstup in + if ((((Word.uint pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else return (pa, c))))))))" + + +(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) + +definition TLBTranslate :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " TLBTranslate vAddr accessType = ( + (TLBTranslateC vAddr accessType :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (addr, c) = varstup in + return addr)))" + + +(*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*) + +definition CPtrCmpOp_of_num :: " int \<Rightarrow> CPtrCmpOp " where + " CPtrCmpOp_of_num arg0 = ( + (let l__57 = arg0 in + if (((l__57 = (( 0 :: int)::ii)))) then CEQ + else if (((l__57 = (( 1 :: int)::ii)))) then CNE + else if (((l__57 = (( 2 :: int)::ii)))) then CLT + else if (((l__57 = (( 3 :: int)::ii)))) then CLE + else if (((l__57 = (( 4 :: int)::ii)))) then CLTU + else if (((l__57 = (( 5 :: int)::ii)))) then CLEU + else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ + else CNEXEQ))" + + +(*val num_of_CPtrCmpOp : CPtrCmpOp -> integer*) + +fun num_of_CPtrCmpOp :: " CPtrCmpOp \<Rightarrow> int " where + " num_of_CPtrCmpOp CEQ = ( (( 0 :: int)::ii))" +|" num_of_CPtrCmpOp CNE = ( (( 1 :: int)::ii))" +|" num_of_CPtrCmpOp CLT = ( (( 2 :: int)::ii))" +|" num_of_CPtrCmpOp CLE = ( (( 3 :: int)::ii))" +|" num_of_CPtrCmpOp CLTU = ( (( 4 :: int)::ii))" +|" num_of_CPtrCmpOp CLEU = ( (( 5 :: int)::ii))" +|" num_of_CPtrCmpOp CEXEQ = ( (( 6 :: int)::ii))" +|" num_of_CPtrCmpOp CNEXEQ = ( (( 7 :: int)::ii))" + + +(*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*) + +definition undefined_CPtrCmpOp :: " unit \<Rightarrow>((register_value),(CPtrCmpOp),(exception))monad " where + " undefined_CPtrCmpOp _ = ( internal_pick [CEQ,CNE,CLT,CLE,CLTU,CLEU,CEXEQ,CNEXEQ])" + + +(*val ClearRegSet_of_num : integer -> ClearRegSet*) + +definition ClearRegSet_of_num :: " int \<Rightarrow> ClearRegSet " where + " ClearRegSet_of_num arg0 = ( + (let l__54 = arg0 in + if (((l__54 = (( 0 :: int)::ii)))) then GPLo + else if (((l__54 = (( 1 :: int)::ii)))) then GPHi + else if (((l__54 = (( 2 :: int)::ii)))) then CLo + else CHi))" + + +(*val num_of_ClearRegSet : ClearRegSet -> integer*) + +fun num_of_ClearRegSet :: " ClearRegSet \<Rightarrow> int " where + " num_of_ClearRegSet GPLo = ( (( 0 :: int)::ii))" +|" num_of_ClearRegSet GPHi = ( (( 1 :: int)::ii))" +|" num_of_ClearRegSet CLo = ( (( 2 :: int)::ii))" +|" num_of_ClearRegSet CHi = ( (( 3 :: int)::ii))" + + +(*val undefined_ClearRegSet : unit -> M ClearRegSet*) + +definition undefined_ClearRegSet :: " unit \<Rightarrow>((register_value),(ClearRegSet),(exception))monad " where + " undefined_ClearRegSet _ = ( internal_pick [GPLo,GPHi,CLo,CHi])" + + +(*val undefined_CapStruct : unit -> M CapStruct*) + +definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " undefined_CapStruct _ = ( + undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . + undefined_bool () \<bind> (\<lambda> (w__5 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__6 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__7 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__8 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__9 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__10 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__11 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__12 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__13 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__14 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__15 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__16 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + return ((| CapStruct_tag = w__0, + CapStruct_padding = w__1, + CapStruct_otype = w__2, + CapStruct_uperms = w__3, + CapStruct_perm_reserved11_14 = w__4, + CapStruct_access_system_regs = w__5, + CapStruct_permit_unseal = w__6, + CapStruct_permit_ccall = w__7, + CapStruct_permit_seal = w__8, + CapStruct_permit_store_local_cap = w__9, + CapStruct_permit_store_cap = w__10, + CapStruct_permit_load_cap = w__11, + CapStruct_permit_store = w__12, + CapStruct_permit_load = w__13, + CapStruct_permit_execute = w__14, + CapStruct_global = w__15, + CapStruct_sealed = w__16, + CapStruct_address = w__17, + CapStruct_base = w__18, + CapStruct_length = w__19 |)))))))))))))))))))))))" + + +definition default_cap :: " CapStruct " where + " default_cap = ( + (| CapStruct_tag = True, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((ones (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = True, + CapStruct_permit_unseal = True, + CapStruct_permit_ccall = True, + CapStruct_permit_seal = True, + CapStruct_permit_store_local_cap = True, + CapStruct_permit_store_cap = True, + CapStruct_permit_load_cap = True, + CapStruct_permit_store = True, + CapStruct_permit_load = True, + CapStruct_permit_execute = True, + CapStruct_global = True, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +definition null_cap_bits :: "(256)Word.word " where + " null_cap_bits = ( (capStructToMemBits256 null_cap :: 256 Word.word))" + + +(*val capStructToMemBits : CapStruct -> mword ty256*) + +definition capStructToMemBits :: " CapStruct \<Rightarrow>(256)Word.word " where + " capStructToMemBits cap = ( + (xor_vec ((capStructToMemBits256 cap :: 256 Word.word)) null_cap_bits :: 256 Word.word))" + + +(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*) + +definition memBitsToCapBits :: " bool \<Rightarrow>(256)Word.word \<Rightarrow>(257)Word.word " where + " memBitsToCapBits tag b = ( + (concat_vec ((bool_to_bits tag :: 1 Word.word)) ((xor_vec b null_cap_bits :: 256 Word.word)) + :: 257 Word.word))" + + +(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*) + +definition setCapPerms :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct " where + " setCapPerms cap perms = ( + (cap (| + CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_perm_reserved11_14 := + ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii) :: 4 Word.word)), CapStruct_access_system_regs := + ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal := + ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall := + ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal := + ((bit_to_bool ((access_vec_dec perms (( 7 :: int)::ii))))), CapStruct_permit_store_local_cap := + ((bit_to_bool ((access_vec_dec perms (( 6 :: int)::ii))))), CapStruct_permit_store_cap := + ((bit_to_bool ((access_vec_dec perms (( 5 :: int)::ii))))), CapStruct_permit_load_cap := + ((bit_to_bool ((access_vec_dec perms (( 4 :: int)::ii))))), CapStruct_permit_store := + ((bit_to_bool ((access_vec_dec perms (( 3 :: int)::ii))))), CapStruct_permit_load := + ((bit_to_bool ((access_vec_dec perms (( 2 :: int)::ii))))), CapStruct_permit_execute := + ((bit_to_bool ((access_vec_dec perms (( 1 :: int)::ii))))), CapStruct_global := + ((bit_to_bool ((access_vec_dec perms (( 0 :: int)::ii)))))|)))" + + +(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*) + +definition sealCap :: " CapStruct \<Rightarrow>(24)Word.word \<Rightarrow> bool*CapStruct " where + " sealCap cap otype = ( (True, (cap (| CapStruct_sealed := True, CapStruct_otype := otype |))))" + + +(*val getCapTop : CapStruct -> integer*) + +definition getCapTop :: " CapStruct \<Rightarrow> int " where + " getCapTop c = ( ((Word.uint(CapStruct_base c))) + ((Word.uint(CapStruct_length c))))" + + +(*val getCapOffset : CapStruct -> integer*) + +definition getCapOffset :: " CapStruct \<Rightarrow> int " where + " getCapOffset c = ( + hardware_mod ((((Word.uint(CapStruct_address c))) - ((Word.uint(CapStruct_base c))))) + ((pow2 (( 64 :: int)::ii))))" + + +(*val getCapLength : CapStruct -> integer*) + +definition getCapLength :: " CapStruct \<Rightarrow> int " where + " getCapLength c = ( Word.uint(CapStruct_length c))" + + +(*val getCapCursor : CapStruct -> integer*) + +definition getCapCursor :: " CapStruct \<Rightarrow> int " where + " getCapCursor c = ( Word.uint(CapStruct_address c))" + + +(* +function{incCapOffset} is the same as function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). + *) +(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition incCapOffset :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct " where + " incCapOffset c delta = ( + (let (newAddr :: 64 bits) = ((add_vec(CapStruct_address c) delta :: 64 Word.word)) in + (True, (c (| CapStruct_address := newAddr |)))))" + + +(* +Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. + *) +(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*) + +definition setCapBounds :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow>(65)Word.word \<Rightarrow> bool*CapStruct " where + " setCapBounds cap base top1 = ( + (let (length1 :: 65 bits) = + ((sub_vec top1 ((concat_vec (vec_of_bits [B0] :: 1 Word.word) base :: 65 Word.word)) :: 65 Word.word)) in + (True, + (cap (| + CapStruct_base := base, CapStruct_length := + ((subrange_vec_dec length1 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)), CapStruct_address := base |)))))" + + +(*val undefined_ast : unit -> M ast*) + +definition undefined_ast :: " unit \<Rightarrow>((register_value),(ast),(exception))monad " where + " undefined_ast _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__0 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__1 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__3 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__5 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__6 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__7 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__8 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__9 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__10 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__11 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__12 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__13 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__14 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__15 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__16 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__17 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__18 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__19 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__20 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__21 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__22 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__23 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__24 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__25 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__26 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__27 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__28 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__29 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__30 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__31 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__32 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__33 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__34 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__35 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__36 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__37 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__38 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__39 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__40 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__41 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__42 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__43 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__44 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__45 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__46 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__47 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__48 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__49 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__50 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__51 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__52 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__53 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__54 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__55 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__56 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__57 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__58 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__59 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__60 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__61 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__62 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__63 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__64 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__65 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__66 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__67 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__68 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__69 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__70 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__71 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__72 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__73 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__74 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__75 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__76 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__77 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__78 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__79 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__80 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__81 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__82 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__83 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__84 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__85 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__86 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__87 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__88 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__89 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__90 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__91 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__92 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__93 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__94 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__95 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__96 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__97 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__98 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__99 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__100 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__101 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__102 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__103 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__104 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__105 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__106 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__107 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__108 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__109 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__110 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__111 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__112 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__113 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__114 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__115 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__116 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__117 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__118 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__119 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__120 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__121 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__122 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__123 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__124 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__125 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__126 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__127 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__128 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__129 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__130 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__131 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__132 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__133 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__134 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__135 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__136 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__137 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__138 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__139 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__140 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__141 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__142 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__143 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__144 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__145 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__146 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__147 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__148 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__149 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__150 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__151 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__152 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \<bind> (\<lambda> (w__153 :: 26 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \<bind> (\<lambda> (w__154 :: 26 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__155 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__156 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__157 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__158 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__159 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__160 :: 16 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__161 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__162 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__163 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__164 :: 16 Word.word) . + undefined_Comparison () \<bind> (\<lambda> (w__165 :: Comparison) . + undefined_bool () \<bind> (\<lambda> (w__166 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__167 :: bool) . + (((((undefined_unit () \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__168 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__169 :: 5 Word.word) . + undefined_Comparison () \<bind> (\<lambda> (w__170 :: Comparison) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__171 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__172 :: 16 Word.word) . + undefined_Comparison () \<bind> (\<lambda> (w__173 :: Comparison) . + undefined_WordType () \<bind> (\<lambda> (w__174 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__175 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__176 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__177 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__178 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__179 :: 16 Word.word) . + undefined_WordType () \<bind> (\<lambda> (w__180 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__181 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__182 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__183 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__184 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__185 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__186 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__187 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__188 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__189 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__190 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__191 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__192 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__193 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__194 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__195 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__196 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__197 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__198 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__199 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__200 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__201 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__202 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__203 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__204 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__205 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__206 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__207 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__208 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__209 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__210 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__211 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__212 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__213 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__214 :: 16 Word.word) . + (undefined_unit () \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__215 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__216 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__217 :: 3 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__218 :: bool) . + (undefined_unit () \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__219 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__220 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__221 :: 3 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__222 :: bool) . + ((((undefined_unit () \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__223 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__224 :: 5 Word.word) . + (undefined_unit () \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__225 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__226 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__227 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__228 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__229 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__230 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__231 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__232 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__233 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__234 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__235 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__236 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__237 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__238 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__239 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__240 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__241 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__242 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__243 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__244 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__245 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__246 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__247 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__248 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__249 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__250 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__251 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__252 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__253 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__254 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__255 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__256 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__257 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__258 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__259 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__260 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__261 :: 5 Word.word) . + undefined_CPtrCmpOp () \<bind> (\<lambda> (w__262 :: CPtrCmpOp) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__263 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__264 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__265 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__266 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__267 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__268 :: 11 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__269 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__270 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__271 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__272 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__273 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__274 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__275 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__276 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__277 :: 11 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__278 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__279 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__280 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__281 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__282 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__283 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__284 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__285 :: 5 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__286 :: bool) . + undefined_ClearRegSet () \<bind> (\<lambda> (w__287 :: ClearRegSet) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__288 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__289 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__290 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__291 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__292 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__293 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__294 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__295 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__296 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__297 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__298 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__299 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__300 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__301 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__302 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__303 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__304 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__305 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__306 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__307 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__308 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__309 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__310 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__311 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__312 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__313 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__314 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__315 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__316 :: 11 Word.word) . + (undefined_unit () \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__317 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__318 :: 16 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__319 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__320 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__321 :: 16 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__322 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__323 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__324 :: 5 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__325 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__326 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__327 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__328 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__329 :: 8 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__330 :: bool) . + undefined_WordType () \<bind> (\<lambda> (w__331 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__332 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__333 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__334 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__335 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__336 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__337 :: 8 Word.word) . + undefined_WordType () \<bind> (\<lambda> (w__338 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__339 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__340 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__341 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__342 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__343 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__344 :: 11 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__345 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__346 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__347 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__348 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__349 :: 11 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__350 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__351 :: 5 Word.word) . + undefined_unit () \<then> + internal_pick + [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL (w__86,w__87,w__88),SLLV (w__89,w__90,w__91),SRA (w__92,w__93,w__94),SRAV (w__95,w__96,w__97),SRL (w__98,w__99,w__100),SRLV (w__101,w__102,w__103),SLT (w__104,w__105,w__106),SLTI (w__107,w__108,w__109),SLTU (w__110,w__111,w__112),SLTIU (w__113,w__114,w__115),MOVN (w__116,w__117,w__118),MOVZ (w__119,w__120,w__121),MFHI w__122,MFLO w__123,MTHI w__124,MTLO w__125,MUL (w__126,w__127,w__128),MULT (w__129,w__130),MULTU (w__131,w__132),DMULT (w__133,w__134),DMULTU (w__135,w__136),MADD (w__137,w__138),MADDU (w__139,w__140),MSUB (w__141,w__142),MSUBU (w__143,w__144),DIV (w__145,w__146),DIVU (w__147,w__148),DDIV (w__149,w__150),DDIVU (w__151,w__152),J w__153,JAL w__154,JR w__155,JALR (w__156,w__157),BEQ (w__158,w__159,w__160,w__161,w__162),BCMPZ (w__163,w__164,w__165,w__166,w__167),SYSCALL_THREAD_START () ,ImplementationDefinedStopFetching () ,SYSCALL () ,BREAK () ,WAIT () ,TRAPREG (w__168,w__169,w__170),TRAPIMM (w__171,w__172,w__173),Load (w__174,w__175,w__176,w__177,w__178,w__179),Store (w__180,w__181,w__182,w__183,w__184),LWL (w__185,w__186,w__187),LWR (w__188,w__189,w__190),SWL (w__191,w__192,w__193),SWR (w__194,w__195,w__196),LDL (w__197,w__198,w__199),LDR (w__200,w__201,w__202),SDL (w__203,w__204,w__205),SDR (w__206,w__207,w__208),CACHE (w__209,w__210,w__211),PREF (w__212,w__213,w__214),SYNC () ,MFC0 (w__215,w__216,w__217,w__218),HCF () ,MTC0 (w__219,w__220,w__221,w__222),TLBWI () ,TLBWR () ,TLBR () ,TLBP () ,RDHWR (w__223,w__224),ERET () ,CGetPerm (w__225,w__226),CGetType (w__227,w__228),CGetBase (w__229,w__230),CGetLen (w__231,w__232),CGetTag (w__233,w__234),CGetSealed (w__235,w__236),CGetOffset (w__237,w__238),CGetAddr (w__239,w__240),CGetPCC w__241,CGetPCCSetOffset (w__242,w__243),CGetCause w__244,CSetCause w__245,CReadHwr (w__246,w__247),CWriteHwr (w__248,w__249),CAndPerm (w__250,w__251,w__252),CToPtr (w__253,w__254,w__255),CSub (w__256,w__257,w__258),CPtrCmp (w__259,w__260,w__261,w__262),CIncOffset (w__263,w__264,w__265),CIncOffsetImmediate (w__266,w__267,w__268),CSetOffset (w__269,w__270,w__271),CSetBounds (w__272,w__273,w__274),CSetBoundsImmediate (w__275,w__276,w__277),CSetBoundsExact (w__278,w__279,w__280),CClearTag (w__281,w__282),CMOVX (w__283,w__284,w__285,w__286),ClearRegs (w__287,w__288),CFromPtr (w__289,w__290,w__291),CBuildCap (w__292,w__293,w__294),CCopyType (w__295,w__296,w__297),CCheckPerm (w__298,w__299),CCheckType (w__300,w__301),CTestSubset (w__302,w__303,w__304),CSeal (w__305,w__306,w__307),CCSeal (w__308,w__309,w__310),CUnseal (w__311,w__312,w__313),CCall (w__314,w__315,w__316),CReturn () ,CBX (w__317,w__318,w__319),CBZ (w__320,w__321,w__322),CJALR (w__323,w__324,w__325),CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332),CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339),CSC (w__340,w__341,w__342,w__343,w__344,w__345),CLC (w__346,w__347,w__348,w__349,w__350),C2Dump w__351,RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val execute : ast -> M unit*) + +(*val decode : mword ty32 -> maybe ast*) + +definition DDC :: "(5)Word.word " where + " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" + + +definition IDC :: "(5)Word.word " where + " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" + + +definition KR1C :: "(5)Word.word " where + " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" + + +definition KR2C :: "(5)Word.word " where + " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" + + +definition KCC :: "(5)Word.word " where + " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" + + +definition KDC :: "(5)Word.word " where + " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" + + +definition EPCC :: "(5)Word.word " where + " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" + + +definition CapRegs :: "(((regstate),(register_value),((257)Word.word))register_ref)list " where + " CapRegs = ( + [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref, + C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref, + C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])" + + +definition max_otype :: " int " where + " max_otype = ( MAX (( 24 :: int)::ii))" + + +definition have_cp2 :: " bool " where + " have_cp2 = ( True )" + + +(* +This function reads a given capability register and returns its contents converted to a CapStruct. +*) +(*val readCapReg : mword ty5 -> M CapStruct*) + +definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " readCapReg n = ( + (let i = (Word.uint n) in + (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + return ((capRegToCapStruct w__0)))))" + + +(*val writeCapReg : mword ty5 -> CapStruct -> M unit*) + +definition writeCapReg :: "(5)Word.word \<Rightarrow> CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where + " writeCapReg n cap = ( + (let i = (Word.uint n) in + write_reg + ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((capStructToCapReg cap :: 257 Word.word))))" + + +(*val CapEx_of_num : integer -> CapEx*) + +definition CapEx_of_num :: " int \<Rightarrow> CapEx " where + " CapEx_of_num arg0 = ( + (let l__32 = arg0 in + if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None + else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation + else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation + else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation + else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation + else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap + else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap + else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow + else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation + else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap + else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds + else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation + else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation + else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation + else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation + else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation + else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation + else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation + else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation + else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation + else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation + else CapEx_PermitUnsealViolation))" + + +(*val num_of_CapEx : CapEx -> integer*) + +fun num_of_CapEx :: " CapEx \<Rightarrow> int " where + " num_of_CapEx CapEx_None = ( (( 0 :: int)::ii))" +|" num_of_CapEx CapEx_LengthViolation = ( (( 1 :: int)::ii))" +|" num_of_CapEx CapEx_TagViolation = ( (( 2 :: int)::ii))" +|" num_of_CapEx CapEx_SealViolation = ( (( 3 :: int)::ii))" +|" num_of_CapEx CapEx_TypeViolation = ( (( 4 :: int)::ii))" +|" num_of_CapEx CapEx_CallTrap = ( (( 5 :: int)::ii))" +|" num_of_CapEx CapEx_ReturnTrap = ( (( 6 :: int)::ii))" +|" num_of_CapEx CapEx_TSSUnderFlow = ( (( 7 :: int)::ii))" +|" num_of_CapEx CapEx_UserDefViolation = ( (( 8 :: int)::ii))" +|" num_of_CapEx CapEx_TLBNoStoreCap = ( (( 9 :: int)::ii))" +|" num_of_CapEx CapEx_InexactBounds = ( (( 10 :: int)::ii))" +|" num_of_CapEx CapEx_GlobalViolation = ( (( 11 :: int)::ii))" +|" num_of_CapEx CapEx_PermitExecuteViolation = ( (( 12 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadViolation = ( (( 13 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreViolation = ( (( 14 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadCapViolation = ( (( 15 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreCapViolation = ( (( 16 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreLocalCapViolation = ( (( 17 :: int)::ii))" +|" num_of_CapEx CapEx_PermitSealViolation = ( (( 18 :: int)::ii))" +|" num_of_CapEx CapEx_AccessSystemRegsViolation = ( (( 19 :: int)::ii))" +|" num_of_CapEx CapEx_PermitCCallViolation = ( (( 20 :: int)::ii))" +|" num_of_CapEx CapEx_AccessCCallIDCViolation = ( (( 21 :: int)::ii))" +|" num_of_CapEx CapEx_PermitUnsealViolation = ( (( 22 :: int)::ii))" + + +(*val undefined_CapEx : unit -> M CapEx*) + +definition undefined_CapEx :: " unit \<Rightarrow>((register_value),(CapEx),(exception))monad " where + " undefined_CapEx _ = ( + internal_pick + [CapEx_None,CapEx_LengthViolation,CapEx_TagViolation,CapEx_SealViolation,CapEx_TypeViolation,CapEx_CallTrap,CapEx_ReturnTrap,CapEx_TSSUnderFlow,CapEx_UserDefViolation,CapEx_TLBNoStoreCap,CapEx_InexactBounds,CapEx_GlobalViolation,CapEx_PermitExecuteViolation,CapEx_PermitLoadViolation,CapEx_PermitStoreViolation,CapEx_PermitLoadCapViolation,CapEx_PermitStoreCapViolation,CapEx_PermitStoreLocalCapViolation,CapEx_PermitSealViolation,CapEx_AccessSystemRegsViolation,CapEx_PermitCCallViolation,CapEx_AccessCCallIDCViolation,CapEx_PermitUnsealViolation])" + + +(*val CapExCode : CapEx -> mword ty8*) + +fun CapExCode :: " CapEx \<Rightarrow>(8)Word.word " where + " CapExCode CapEx_None = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_LengthViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_TagViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_SealViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_TypeViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_CallTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_ReturnTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_TSSUnderFlow = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_UserDefViolation = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_TLBNoStoreCap = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_InexactBounds = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_GlobalViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitExecuteViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreLocalCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitSealViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessSystemRegsViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitCCallViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessCCallIDCViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitUnsealViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B1] :: 8 Word.word))" + + +(*val undefined_CapCauseReg : unit -> M CapCauseReg*) + +definition undefined_CapCauseReg :: " unit \<Rightarrow>((register_value),(CapCauseReg),(exception))monad " where + " undefined_CapCauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . + internal_pick [Mk_CapCauseReg w__0]))" + + +fun get_CapCauseReg :: " CapCauseReg \<Rightarrow>(16)Word.word " where + " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )" + + +definition set_CapCauseReg :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_CapCauseReg v) in + write_reg r_ref r)))" + + +fun get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +definition set_CapCauseReg_ExcCode :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_ExcCode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +fun update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 16 Word.word)))" + + +(*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) + +fun get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +definition set_CapCauseReg_RegNum :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_RegNum r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +(*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) + +fun update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 16 Word.word)))" + + +(*val execute_branch_pcc : CapStruct -> M unit*) + +definition execute_branch_pcc :: " CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_branch_pcc newPCC = ( + (write_reg + delayedPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset newPCC)) :: 64 Word.word)) \<then> + write_reg delayedPCC_ref ((capStructToCapReg newPCC :: 257 Word.word))) \<then> + write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val ERETHook : unit -> M unit*) + +definition ERETHook :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " ERETHook _ = ( + (read_reg C31_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (write_reg nextPCC_ref w__0 \<then> + (read_reg C31_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" + + +(*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) + +definition raise_c2_exception8 :: " CapEx \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception8 capEx regnum = ( + (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx :: 8 Word.word)) \<then> + set_CapCauseReg_RegNum CapCause_ref regnum) \<then> + ((let mipsEx = + (if ((((((capEx = CapEx_CallTrap))) \<or> (((capEx = CapEx_ReturnTrap)))))) then C2Trap + else C2E) in + SignalException mipsEx)))" + + +(*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*) + +definition raise_c2_exception :: " CapEx \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception capEx regnum = ( + (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) regnum :: 8 Word.word)) in + if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDC)))))) then + raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 + else raise_c2_exception8 capEx reg8))" + + +(*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*) + +definition raise_c2_exception_noreg :: " CapEx \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception_noreg capEx = ( + raise_c2_exception8 capEx (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word))" + + +(*val pcc_access_system_regs : unit -> M bool*) + +definition pcc_access_system_regs :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " pcc_access_system_regs _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + return(CapStruct_access_system_regs pcc))))" + + +(* +The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. + *) +(*val register_inaccessible : mword ty5 -> M bool*) + +definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " register_inaccessible r = ( + or_boolM + (and_boolM (return (((r = IDC)))) + ((read_reg inCCallDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 Word.word) . + return ((bits_to_bool w__0))))) + (and_boolM + (return ((((((r = KR1C))) \<or> ((((((r = KR2C))) \<or> ((((((r = KDC))) \<or> ((((((r = KCC))) \<or> (((r = EPCC)))))))))))))))) + (pcc_access_system_regs () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))))" + + +(*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged_reserve :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged_reserve addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) + +definition MEMw_tagged :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MEMw_tagged addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )" + + +(*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) + +definition MEMw_tagged_conditional :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " MEMw_tagged_conditional addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" + + +definition cap_addr_mask :: "(64)Word.word " where + " cap_addr_mask = ( + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((((pow2 (( 64 :: int)::ii))) - cap_size)) + :: 64 Word.word))" + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MEMw_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MEMw_wrapper addr size1 data = ( + (let ledata = ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word)) in + if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + write_reg UART_WDATA_ref ((subrange_vec_dec ledata (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) \<then> + write_reg UART_WRITTEN_ref (vec_of_bits [B1] :: 1 Word.word) + else + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \<then> + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) + +definition MEMw_conditional_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " MEMw_conditional_wrapper addr size1 data = ( + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \<then> + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False + else return () ) \<then> + return success))" + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapper addr accessType width = ( + (let capno = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) in + readCapReg capno \<bind> (\<lambda> cap . + ((if ((\<not>(CapStruct_tag cap))) then raise_c2_exception CapEx_TagViolation capno + else if(CapStruct_sealed cap) then raise_c2_exception CapEx_SealViolation capno + else return () ) \<then> + (case accessType of + Instruction => + if ((\<not>(CapStruct_permit_execute cap))) then + raise_c2_exception CapEx_PermitExecuteViolation capno + else return () + | LoadData => + if ((\<not>(CapStruct_permit_load cap))) then raise_c2_exception CapEx_PermitLoadViolation capno + else return () + | StoreData => + if ((\<not>(CapStruct_permit_store cap))) then raise_c2_exception CapEx_PermitStoreViolation capno + else return () + )) \<then> + ((let cursor = (getCapCursor cap) in + (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in + (let size1 = (wordWidthBytes width) in + (let base = (getCapBase cap) in + (let top1 = (getCapTop cap) in + if ((((vAddr + size1)) > top1)) then + (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))" + + +(*val TranslatePC : mword ty64 -> M (mword ty64)*) + +definition TranslatePC :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " TranslatePC vAddr = ( + (incrementCP0Count () \<then> + (read_reg PCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + (let base = (getCapBase pcc) in + (let top1 = (getCapTop pcc) in + (let absPC = (base + ((Word.uint vAddr))) in + if (((((absPC mod (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then + (SignalExceptionBadAddr AdEL + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + :: ( 64 Word.word) M) + else if ((\<not>(CapStruct_tag pcc))) then + (raise_c2_exception_noreg CapEx_TagViolation :: ( 64 Word.word) M) + else if ((((absPC + (( 4 :: int)::ii))) > top1)) then + (raise_c2_exception_noreg CapEx_LengthViolation :: ( 64 Word.word) M) + else + (TLBTranslate ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + Instruction + :: ( 64 Word.word) M)))))))" + + +(* +All capability instrucitons must first check that the capability +co-processor is enabled using the following function that raises a +co-processor unusable exception if a CP0Status.CU2 is not set. This +allows the operating system to only save and restore the full +capability context for processes that use capabilities. +*) +(*val checkCP2usable : unit -> M unit*) + +definition checkCP2usable :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkCP2usable _ = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + if ((\<not> ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 2 :: int)::ii))))))) then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1,B0] :: 2 Word.word) \<then> SignalException CpU + else return () ))" + + +definition init_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_cp2_state _ = ( + (let defaultBits = ((capStructToCapReg default_cap :: 257 Word.word)) in + ((write_reg PCC_ref defaultBits \<then> + write_reg nextPCC_ref defaultBits) \<then> + write_reg delayedPCC_ref defaultBits) \<then> + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) in + writeCapReg idx default_cap)))))" + + +definition cp2_next_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " cp2_next_pc _ = ( + (read_reg nextPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (write_reg PCC_ref w__0 \<then> + (read_reg inBranchDelay_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__1 :: 1 Word.word) . + if ((bits_to_bool w__1)) then + (read_reg delayedPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__2 :: CapReg) . + write_reg nextPCC_ref w__2) + else write_reg inCCallDelay_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val capToString : CapStruct -> M string*) + +definition capToString :: " CapStruct \<Rightarrow>((register_value),(string),(exception))monad " where + " capToString cap = ( + skip () \<then> + return (((op@) ('' t:'') + (((op@) (if(CapStruct_tag cap) then (''1'') else (''0'')) + (((op@) ('' s:'') + (((op@) (if(CapStruct_sealed cap) then (''1'') else (''0'')) + (((op@) ('' perms:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((getCapPerms cap :: 31 Word.word)) + :: 32 Word.word)))) + (((op@) ('' type:'') + (((op@) ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype cap))) + (((op@) ('' offset:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((getCapOffset cap)) + :: 64 Word.word)))) + (((op@) ('' base:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((getCapBase cap)) + :: 64 Word.word)))) + (((op@) ('' length:'') + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((min ((getCapLength cap)) + ((MAX (( 64 :: int)::ii))))) + :: 64 Word.word)))))))))))))))))))))))))))))))" + + +definition dump_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " dump_cp2_state _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + capToString ((capRegToCapStruct w__0)) \<bind> (\<lambda> (w__1 :: string) . + (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) \<bind> (\<lambda> (w__2 :: + CapStruct) . + capToString w__2 \<bind> (\<lambda> (w__3 :: string) . + return ((let _ = + (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict i)) w__3))))) in + () ))))))))))" + + +(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) + +definition extendLoad :: "('sz::len)Word.word \<Rightarrow> bool \<Rightarrow>(64)Word.word " where + " extendLoad memResult sign = ( + if sign then (sign_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word) + else (zero_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word))" + + +(*val TLBWriteEntry : mword ty6 -> M unit*) + +definition TLBWriteEntry :: "(6)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " TLBWriteEntry idx = ( + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> (\<lambda> pagemask . + (let b__0 = pagemask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) + then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else SignalException MCheck) \<then> + ((let i = (Word.uint idx) in + (let entry = (access_list_dec TLBEntries i) in + (set_TLBEntry_pagemask entry pagemask \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 :: 2 Word.word)) \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__1 :: TLBEntryHiReg) . + (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 :: 27 Word.word)) \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__2 :: TLBEntryHiReg) . + (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 :: 8 Word.word)) \<then> + and_boolM + (read_reg TLBEntryLo0_ref \<bind> (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__3 :: 1 Word.word)))))) + (read_reg TLBEntryLo1_ref \<bind> (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__4 :: 1 Word.word))))))) \<bind> (\<lambda> (w__5 :: bool) . + ((set_TLBEntry_g entry ((bool_to_bits w__5 :: 1 Word.word)) \<then> + set_TLBEntry_valid entry ((cast_unit_vec0 B1 :: 1 Word.word))) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__6 :: TLBEntryLoReg) . + (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__7 :: TLBEntryLoReg) . + (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__8 :: TLBEntryLoReg) . + (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 :: 24 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__9 :: TLBEntryLoReg) . + (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 :: 3 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__10 :: TLBEntryLoReg) . + (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__11 :: TLBEntryLoReg) . + (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__12 :: TLBEntryLoReg) . + (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__13 :: TLBEntryLoReg) . + (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__14 :: TLBEntryLoReg) . + (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 :: 24 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__15 :: TLBEntryLoReg) . + (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 :: 3 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__16 :: TLBEntryLoReg) . + (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__17 :: TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 :: 1 Word.word))))))))))))))))))))))))" + + +definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where + " decode v__0 = ( + if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADD (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADD (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (AND0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ANDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (OR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ORI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (NOR (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (XOR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (XORI (rs,rt,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LUI (rt,imm)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLT (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLTU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVN (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVZ (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFHI rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFLO rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTHI rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTLO rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADD (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADDU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUB (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUBU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIVU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIVU (rs,rt)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (J offset)) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (JAL offset)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 11 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 10 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (JR rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (JALR (rs,rd)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,True)))) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B0,B0,B1,B1,B0,B0] + :: 32 Word.word)))) then + Some (SYSCALL_THREAD_START () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + Some (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + Some (BREAK () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LTU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LTU)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (B,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (H,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CACHE (base,op1,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (PREF (base,op1,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + Some (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,True))))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B1,B0] + :: 32 Word.word)))) then + Some (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B1,B1,B0] + :: 32 Word.word)))) then + Some (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B1] + :: 32 Word.word)))) then + Some (TLBR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (RDHWR (rt,rd)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B1,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (ERET () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (CReturn () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCC cd1)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCCSetOffset (cd1,rs)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CReadHwr (cd1,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CWriteHwr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetAddr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBoundsExact (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CBuildCap (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCopyType (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSub (rt,cb,cs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CTestSubset (rd,cb,ct))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,True)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,True)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1] + :: 32 Word.word)))) then + Some (CReturn () ) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (selector :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CCall (cs,cb,selector))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CIncOffsetImmediate (cd1,cb,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B1,B0,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSetBoundsImmediate (cd1,cb,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,D,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),B,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),H,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),W,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),D,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSC (cs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSC (cs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 11 Word.word),True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CLC (cd1,cb,rt,offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 11 Word.word),True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (C2Dump rt)) + else Some (RI () ))" + + +(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_XORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_XORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_XOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_XOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((xor_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_WAIT : unit -> M unit*) + +definition execute_WAIT :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_WAIT g__121 = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg nextPC_ref w__0))" + + +(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) + +definition execute_TRAPREG :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TRAPREG rs rt cmp = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + (let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) + +definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TRAPIMM rs imm cmp = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TLBWR : unit -> M unit*) + +definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBWR g__125 = ( + (checkCP0Access () \<then> + (read_reg TLBRandom_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBWI : unit -> M unit*) + +definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBWI g__124 = ( + (checkCP0Access () \<then> + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBR : unit -> M unit*) + +definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBR g__126 = ( + (checkCP0Access () \<then> + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (let i = (Word.uint w__0) in + reg_deref ((access_list_dec TLBEntries i)) \<bind> (\<lambda> entry . + ((((((((((((((((write_reg TLBPageMask_ref ((get_TLBEntry_pagemask entry :: 16 Word.word)) \<then> + set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry :: 2 Word.word))) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry :: 27 Word.word))) \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry :: 8 Word.word))) \<then> + set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry :: 24 Word.word))) \<then> + set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry :: 3 Word.word))) \<then> + set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry :: 24 Word.word))) \<then> + set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry :: 3 Word.word))) \<then> + set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry :: 1 Word.word))))))" + + +(*val execute_TLBP : unit -> M unit*) + +definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBP g__127 = ( + (checkCP0Access () \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (tlbSearch ((get_TLBEntryHiReg w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . + (case result of + Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] :: 1 Word.word) \<then> write_reg TLBIndex_ref idx + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg TLBIndex_ref (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word) + ))))" + + +(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_Store width conditional base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData width + :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val + ) + else return False) \<bind> (\<lambda> (success :: bool) . + wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rt_val + ))))))" + + +(*val execute_SYSCALL_THREAD_START : unit -> unit*) + +definition execute_SYSCALL_THREAD_START :: " unit \<Rightarrow> unit " where + " execute_SYSCALL_THREAD_START g__117 = ( () )" + + +(*val execute_SYSCALL : unit -> M unit*) + +definition execute_SYSCALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SYSCALL g__119 = ( SignalException Sys )" + + +(*val execute_SYNC : unit -> M unit*) + +definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SYNC g__122 = ( MEM_sync () )" + + +(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__12 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__12 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__12 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__12 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))))))))" + + +(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__8 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__8 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__8 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + else if (((b__8 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (temp33 :: 33 bits) = + ((sub_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTI rs rt imm = ( + (let imm_val = (Word.sint imm) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs_val = (Word.sint w__0) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLT rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLLV rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) in + (let b__40 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__40 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + else MEMw_wrapper wordAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))))))" + + +(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__32 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__32 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_RI : unit -> M unit*) + +definition execute_RI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RI g__130 = ( SignalException ResI )" + + +(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RDHWR rt rd = ( + getAccessLevel () \<bind> (\<lambda> accessLevel . + (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in + (let rdi = (Word.uint rd) in + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in + (if ((\<not> (((haveAccessLevel \<or> (((haveCU0 \<or> haveHWREna)))))))) then SignalException ResI + else return () ) \<then> + ((let b__146 = rd in + (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . + return ((zero_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) + else (SignalException ResI :: ( 64 Word.word) M)) \<bind> (\<lambda> (temp :: 64 bits) . + wGPR rt temp)))))))))))" + + +(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) + +definition execute_PREF :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> unit " where + " execute_PREF base op1 imm = ( () )" + + +(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_OR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_OR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((or_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_NOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_NOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 :: 64 Word.word)) :: 64 Word.word)))))" + + +(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MUL rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (let (result :: 64 bits) = + ((sign_extend1 (( 64 :: int)::ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd w__1)))))" + + +(*val execute_MTLO : mword ty5 -> M unit*) + +definition execute_MTLO :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTLO rs = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg LO_ref w__0))" + + +(*val execute_MTHI : mword ty5 -> M unit*) + +definition execute_MTHI :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTHI rs = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg HI_ref w__0))" + + +(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MTC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTC0 rt rd sel double = ( + (checkCP0Access () \<then> + (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBIndex_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo0_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo1_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 23 :: int):: ii) :: 41 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + write_reg CP0UserLocal_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBPageMask_ref + ((subrange_vec_dec reg_val (( 28 :: int):: ii) + (( 13 :: int):: ii) :: 16 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBWired_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) + \<then> write_reg TLBRandom_ref TLBIndexMax else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0HWREna_ref + ((concat_vec + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 29 :: int):: ii) :: 3 Word.word)) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0] :: 25 Word.word) + ((subrange_vec_dec reg_val (( 3 :: int):: ii) + (( 0 :: int):: ii) :: 4 Word.word)) + :: 29 Word.word)) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0Count_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 62 :: int):: ii) :: 2 Word.word)) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 :: int):: ii) + (( 13 :: int):: ii) :: 27 Word.word))) + \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 :: int):: ii) + (( 0 :: int):: ii) :: 8 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (write_reg CP0Compare_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) + \<then> read_reg CP0Cause_ref) \<bind> + (\<lambda> (w__0 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec + ((get_CauseReg_IP w__0 :: 8 Word.word)) + (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) + :: 8 Word.word))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + ((((((((set_StatusReg_CU CP0Status_ref + ((subrange_vec_dec reg_val + (( 31 :: int):: ii) + (( 28 :: int):: ii) :: 4 Word.word)) + \<then> + set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 22 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_IM CP0Status_ref + ((subrange_vec_dec reg_val + (( 15 :: int):: ii) + (( 8 :: int):: ii) :: 8 Word.word))) + \<then> + set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 7 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 6 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 5 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_KSU CP0Status_ref + ((subrange_vec_dec reg_val + (( 4 :: int):: ii) + (( 3 :: int):: ii) :: 2 Word.word))) + \<then> + set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 2 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 1 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 0 :: int):: ii))) :: 1 Word.word)) + else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 23 :: int):: ii))) :: 1 Word.word)) + \<then> read_reg CP0Cause_ref) \<bind> + (\<lambda> (w__1 :: CauseReg) . + (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec + ((subrange_vec_dec ip + (( 7 :: int):: ii) + (( 2 :: int):: ii) :: 6 Word.word)) + ((subrange_vec_dec reg_val + (( 9 :: int):: ii) + (( 8 :: int):: ii) :: 2 Word.word)) + :: 8 Word.word)))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0EPC_ref reg_val else + if ((((((b__108 = + (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_XContextReg_XPTEBase + TLBXContext_ref + ((subrange_vec_dec reg_val + (( 63 :: int):: ii) + (( 33 :: int):: ii) :: 31 Word.word)) + else write_reg CP0ErrorEPC_ref reg_val + )))" + + +(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MSUBU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MSUB rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVZ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MOVZ rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + if (((w__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVN :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MOVN rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + if (((w__0 \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MFLO : mword ty5 -> M unit*) + +definition execute_MFLO :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFLO rd = ( + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFHI : mword ty5 -> M unit*) + +definition execute_MFHI :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFHI rd = ( + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MFC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFC0 rt rd sel double = ( + (checkCP0Access () \<then> + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__0 :: TLBIndexT) . + (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in + (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> + (\<lambda> (w__1 :: 1 bits) . + return + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word) + ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word))))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__2 :: TLBIndexT) . + return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo0_ref \<bind> + (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo1_ref \<bind> + (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBContext_ref \<bind> + (\<lambda> (w__5 :: ContextReg) . + return ((get_ContextReg w__5 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> + (\<lambda> (w__7 :: 16 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((concat_vec w__7 + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 28 Word.word)) :: 64 Word.word))) else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__8 :: TLBIndexT) . + return + ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> + (\<lambda> (w__9 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) + \<bind> + (\<lambda> (w__11 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryHi_ref \<bind> + (\<lambda> (w__12 :: TLBEntryHiReg) . + return + ((get_TLBEntryHiReg w__12 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Compare_ref :: ( 32 Word.word) M) + \<bind> + (\<lambda> (w__13 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Status_ref \<bind> + (\<lambda> (w__14 :: StatusReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Cause_ref \<bind> + (\<lambda> (w__15 :: CauseReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0EPC_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) + ((concat_vec + (vec_of_bits + [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B1,B0] :: 2 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B1] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 16 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + TLBIndexMax + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + ( + bool_to_bits + have_cp2 :: 1 Word.word)) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + vec_of_bits + [B0] + :: 1 Word.word) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 16 Word.word)) + :: 19 Word.word)) + :: 22 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 16 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B1,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B1,B0,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + ( + vec_of_bits + [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + ((( + b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + read_reg + TLBXContext_ref + \<bind> + (\<lambda> (w__18 :: XContextReg) . + return + ((get_XContextReg + w__18 :: 64 Word.word))) + else + (read_reg + CP0ErrorEPC_ref :: ( 64 Word.word) M) + )) \<bind> (\<lambda> (result :: 64 bits) . + wGPR rt + (if double then result + else + (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))" + + +(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MADDU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MADD rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_Load width sign linked base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + width + :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . + if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + (write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (case width of + B => + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . + return ((extendLoad w__1 sign :: 64 Word.word))) + | H => + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + return ((extendLoad w__2 sign :: 64 Word.word))) + | W => + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + return ((extendLoad w__3 sign :: 64 Word.word))) + | D => + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((extendLoad w__4 sign :: 64 Word.word))) + ) + else + (case width of + B => + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__6 :: 8 Word.word) . + return ((extendLoad w__6 sign :: 64 Word.word))) + | H => + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . + return ((extendLoad w__7 sign :: 64 Word.word))) + | W => + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . + return ((extendLoad w__8 sign :: 64 Word.word))) + | D => + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . + return ((extendLoad w__9 sign :: 64 Word.word))) + )) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rt memResult)))))" + + +(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__4 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word) + else mem_val) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__0 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word)) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) + +definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LUI rt imm = ( + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) + :: 32 Word.word)) + :: 64 Word.word)))" + + +(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__24 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word) + else mem_val))))))))" + + +(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__16 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word)))))))))" + + +(*val execute_JR : mword ty5 -> M unit*) + +definition execute_JR :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JR rs = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . execute_branch w__0))" + + +(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_JALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JALR rs rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (execute_branch w__0 \<then> + (read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_JAL : mword ty26 -> M unit*) + +definition execute_JAL :: "(26)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JAL offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word)) \<then> + (read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_J : mword ty26 -> M unit*) + +definition execute_J :: "(26)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_J offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ImplementationDefinedStopFetching : unit -> unit*) + +definition execute_ImplementationDefinedStopFetching :: " unit \<Rightarrow> unit " where + " execute_ImplementationDefinedStopFetching g__118 = ( () )" + + +(*val execute_HCF : unit -> unit*) + +definition execute_HCF :: " unit \<Rightarrow> unit " where + " execute_HCF g__123 = ( () )" + + +(*val execute_ERET : unit -> M unit*) + +definition execute_ERET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ERET g__128 = ( + (((checkCP0Access () \<then> + ERETHook () ) \<then> + write_reg CP0LLBit_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__0 :: StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 :: 1 Word.word)))) = ((bit_to_bool B1))))) then + (read_reg CP0ErrorEPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + write_reg nextPC_ref w__1 \<then> set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word)) + else + (read_reg CP0EPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + write_reg nextPC_ref w__2 \<then> set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((sub_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (temp65 :: 65 bits) = + ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRA32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: + 64 Word.word) . + wGPR rd w__2))))" + + +(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd w__1)))" + + +(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" + + +(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DMULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let result = ((mult_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DMULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let result = ((mults_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> (((((NotWordVal rtVal)) \<or> (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.uint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (hardware_mod si ti) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> (((((NotWordVal rtVal)) \<or> (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.sint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (si - ((ti * qi))) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DDIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rsVal = (Word.uint w__0) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rtVal = (Word.uint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (hardware_mod rsVal rtVal) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg LO_ref q \<then> write_reg HI_ref r)))))))" + + +(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DDIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rsVal = (Word.sint w__0) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rtVal = (Word.sint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (rsVal - ((qi * rtVal))) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg LO_ref q \<then> write_reg HI_ref r)))))))" + + +(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((add_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*) + +definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ClearRegs regset m = ( + ((if ((((((regset = CLo))) \<or> (((regset = CHi)))))) then checkCP2usable () + else return () ) \<then> + (if (((regset = CHi))) then + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + (let r = + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) :: 5 Word.word)) in + and_boolM (return ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r)) \<bind> (\<lambda> (w__1 :: + bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r + else return () )))) + else return () )) \<then> + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + if ((bit_to_bool ((access_vec_dec m i)))) then + (case regset of + GPLo => + wGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) + ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | GPHi => + wGPR + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | CLo => + writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) null_cap + | CHi => + writeCapReg + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) null_cap + ) + else return () )))" + + +(*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CWriteHwr cb sel = ( + checkCP2usable () \<then> + ((let l__24 = (Word.uint sel) in + (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cb \<bind> (\<lambda> (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9)))) \<bind> (\<lambda> (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \<bind> (\<lambda> (w__11 :: AccessLevel) . + return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + readCapReg cb \<bind> (\<lambda> capVal . + (let l__16 = (Word.uint sel) in + if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal + else if (((l__16 = (( 1 :: int)::ii)))) then + write_reg CTLSU_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 8 :: int)::ii)))) then + write_reg CTLSP_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal + else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal + else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal + else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal + else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal + else assert_exp False (''should be unreachable code'')))))))))))" + + +(*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CUnseal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CUnseal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if (((ct_cursor \<noteq> ((Word.uint(CapStruct_otype cs_val)))))) then + raise_c2_exception CapEx_TypeViolation ct + else if ((\<not>(CapStruct_permit_unseal ct_val))) then + raise_c2_exception CapEx_PermitUnsealViolation ct + else if ((ct_cursor < ((getCapBase ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ((getCapTop ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else + writeCapReg cd1 + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), CapStruct_global := + ((((CapStruct_global cs_val) \<and>(CapStruct_global ct_val))))|)))))))))" + + +(*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CToPtr rd cb ct = ( + (checkCP2usable () \<then> + readCapReg ct) \<bind> (\<lambda> ct_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let cbBase = (getCapBase cb_val) in + (let cbTop = (getCapTop cb_val) in + (let ctBase = (getCapBase ct_val) in + (let ctTop = (getCapTop ct_val) in + wGPR rd + (if (((((\<not>(CapStruct_tag cb_val))) \<or> (((((cbBase < ctBase)) \<or> ((cbTop > ctTop)))))))) then + (zeros0 (( 64 :: int)::ii) () :: 64 Word.word) + else + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ctBase)) + :: 64 Word.word)))))))))))" + + +(*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CTestSubset rd cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + (let (result :: 1 bits) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_base < cb_base)) then (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_top > cb_top)) then (vec_of_bits [B0] :: 1 Word.word) + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then + (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" + + +(*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSub :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSub rd cb ct = ( + (checkCP2usable () \<then> + readCapReg ct) \<bind> (\<lambda> ct_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) + :: 64 Word.word)))))))" + + +(*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*) + +definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CStore rs cb rt rd offset width conditional = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else + (let size1 = (wordWidthBytes width) in + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + size1)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslate vAddr64 StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__2 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val + ) + else return False) \<bind> (\<lambda> (success :: bool) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rs_val + )))))))))))" + + +(*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetOffset cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CSetCause : mword ty5 -> M unit*) + +definition execute_CSetCause :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetCause rt = ( + (checkCP2usable () \<then> + pcc_access_system_regs () ) \<bind> (\<lambda> (w__0 :: bool) . + if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) \<then> + set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))))" + + +(*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CSetBoundsImmediate :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBoundsImmediate cd1 cb imm = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let immU = (Word.uint imm) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + immU) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBoundsExact :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBoundsExact cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (exact, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + if ((\<not> exact)) then raise_c2_exception CapEx_InexactBounds cb + else writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBounds :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBounds cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSeal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\<not>(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\<not> success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSC cs cb rt rd offset conditional = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else if ((\<not>(CapStruct_permit_store_cap cb_val))) then + raise_c2_exception CapEx_PermitStoreCapViolation cb + else if (((((\<not>(CapStruct_permit_store_local_cap cb_val))) \<and> ((((CapStruct_tag cs_val) \<and> ((\<not>(CapStruct_global cs_val))))))))) then + raise_c2_exception CapEx_PermitStoreLocalCapViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslateC vAddr64 StoreData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, noStoreCap) = varstup in + if ((((CapStruct_tag cs_val) \<and> noStoreCap))) then + raise_c2_exception CapEx_TLBNoStoreCap cs + else if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__3 (( 0 :: int)::ii))))) then + MEMw_tagged_conditional pAddr(CapStruct_tag cs_val) + ((capStructToMemBits cs_val :: 256 Word.word)) + else return False) \<bind> (\<lambda> success . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else MEMw_tagged pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)))))))))))))" + + +(*val execute_CReturn : unit -> M unit*) + +definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CReturn g__129 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" + + +(*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CReadHwr cd1 sel = ( + checkCP2usable () \<then> + ((let l__8 = (Word.uint sel) in + (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cd1 \<bind> (\<lambda> (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9)))) \<bind> (\<lambda> (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \<bind> (\<lambda> (w__11 :: AccessLevel) . + return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + (let l__0 = (Word.uint sel) in + (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC + else if (((l__0 = (( 1 :: int)::ii)))) then + (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . + return ((capRegToCapStruct w__14))) + else if (((l__0 = (( 8 :: int)::ii)))) then + (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__15 :: 257 Word.word) . + return ((capRegToCapStruct w__15))) + else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C + else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C + else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC + else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC + else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC + else assert_exp False (''should be unreachable code'') \<then> undefined_CapStruct () ) \<bind> (\<lambda> (capVal :: + CapStruct) . + writeCapReg cd1 capVal))))))))))" + + +(*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*) + +definition execute_CPtrCmp :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> CPtrCmpOp \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CPtrCmp rd cb ct op1 = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + readCapReg cb \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let equal = False in + (let ltu = False in + (let lts = False in + (let ((equal :: bool), (lts :: bool), (ltu :: bool)) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (let ((lts :: bool), (ltu :: bool)) = + (if ((\<not>(CapStruct_tag cb_val))) then + (let (ltu :: bool) = True in + (let (lts :: bool) = True in + (lts, ltu))) + else (lts, ltu)) in + (equal, lts, ltu)) + else + (let cursor1 = (getCapCursor cb_val) in + (let cursor2 = (getCapCursor ct_val) in + (let (equal :: bool) = (cursor1 = cursor2) in + (let (ltu :: bool) = (cursor1 < cursor2) in + (let (lts :: bool) = + (zopz0zI_s ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor1 :: 64 Word.word)) + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor2 :: 64 Word.word))) in + (equal, lts, ltu))))))) in + (let (cmp :: bool) = + ((case op1 of + CEQ => equal + | CNE => \<not> equal + | CLT => lts + | CLE => (lts \<or> equal) + | CLTU => ltu + | CLEU => (ltu \<or> equal) + | CEXEQ => (cb_val = ct_val) + | CNEXEQ => (cb_val \<noteq> ct_val) + )) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" + + +(*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CMOVX :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CMOVX cd1 cb rt ismovn = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec + ((bool_to_bits (((w__2 = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word))))) :: 1 Word.word)) + ((bool_to_bits ismovn :: 1 Word.word)) + :: 1 Word.word)))) then + readCapReg cb \<bind> (\<lambda> (w__3 :: CapStruct) . writeCapReg cd1 w__3) + else return () ))))" + + +(*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*) + +definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> bool \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CLoad arg0 arg1 arg2 arg3 arg4 arg5 arg6 = ( + (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in + (case merge_var of + (rd, cb, rt, offset, signext, B, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__2 :: 8 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, D, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, H, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, W, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 W)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + )))" + + +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CLC cd1 cb rt offset linked = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslateC vAddr64 LoadData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, suppressTag) = varstup in + (let cd1 = (Word.uint cd1) in + if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_tagged_reserve pAddr :: ((bool * 256 Word.word)) M)) \<bind> (\<lambda> varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \<and> ((((CapStruct_permit_load_cap cb_val) \<and> ((\<not> suppressTag)))))))) + mem + :: 257 Word.word)))) + else + (MEMr_tagged pAddr :: ((bool * 256 Word.word)) M) \<bind> (\<lambda> varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \<and> ((((CapStruct_permit_load_cap cb_val) \<and> ((\<not> suppressTag)))))))) + mem + :: 257 Word.word)))))))))))))))" + + +(*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CJALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CJALR cd1 cb link = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let cb_ptr = (getCapCursor cb_val) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + and_boolM (return link) ((register_inaccessible cd1)) \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_execute cb_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then + raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL + else + (if link then + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__3 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__3) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + (let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 :: int)::ii) :: 64 Word.word))) in + if success then writeCapReg cd1 linkCap + else assert_exp False (''''))))) + else return () ) \<then> + execute_branch_pcc cb_val)))))))" + + +(*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CIncOffsetImmediate :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CIncOffsetImmediate cd1 cb imm = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val imm64) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) imm64 + :: 64 Word.word))))))))))" + + +(*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CIncOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CIncOffset cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and> ((((CapStruct_sealed cb_val) \<and> (((rt_val \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetType rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + (if(CapStruct_sealed capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) + else (replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetTag rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetSealed :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetSealed rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPerm rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPCCSetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPCCSetOffset cd1 rs = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (success, newPCC) = (setCapOffset pcc rs_val) in + if success then writeCapReg cd1 newPCC + else writeCapReg cd1 ((int_to_cap rs_val))))))))" + + +(*val execute_CGetPCC : mword ty5 -> M unit*) + +definition execute_CGetPCC :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPCC cd1 = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let (success, pcc2) = (setCapOffset pcc w__2) in + assert_exp success ('''') \<then> writeCapReg cd1 pcc2))))))" + + +(*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetOffset rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetLen :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetLen rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + (let len65 = (getCapLength capVal) in + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + (if ((len65 > MAX_U64)) then MAX_U64 + else len65) + :: 64 Word.word))))))" + + +(*val execute_CGetCause : mword ty5 -> M unit*) + +definition execute_CGetCause :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetCause rd = ( + (checkCP2usable () \<then> + pcc_access_system_regs () ) \<bind> (\<lambda> (w__0 :: bool) . + if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + read_reg CapCause_ref \<bind> (\<lambda> (w__1 :: CapCauseReg) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1 :: 16 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetBase :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetBase rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetAddr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetAddr rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapCursor capVal)) :: 64 Word.word)))))" + + +(*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CFromPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CFromPtr cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then writeCapReg cd1 null_cap + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCopyType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCopyType cd1 cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let cb_base = (getCapBase cb_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_otype = (Word.uint(CapStruct_otype ct_val)) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if(CapStruct_sealed ct_val) then + if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_otype \<ge> cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (success, cap) = + (setCapOffset cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((ct_otype - cb_base)) + :: 64 Word.word))) in + assert_exp success ('''') \<then> writeCapReg cd1 cap) + else + writeCapReg cd1 + ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))))))" + + +(*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CClearTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CClearTag cd1 cb = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else readCapReg cb \<bind> (\<lambda> cb_val . writeCapReg cd1 (cb_val (| CapStruct_tag := False |))))))" + + +(*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCheckType cs cb = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else return () )))))" + + +(*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCheckPerm cs rt = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + (let (cs_perms :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_perms . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((and_vec cs_perms rt_perms :: 64 Word.word)) \<noteq> rt_perms))) then + raise_c2_exception CapEx_UserDefViolation cs + else return () )))))" + + +(*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CCall :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCall cs cb b__151 = ( + if (((b__151 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\<not>(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \<ge> ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else raise_c2_exception CapEx_CallTrap cs))))) + else + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__3 :: bool) . + if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\<not>(CapStruct_permit_ccall cs_val))) then + raise_c2_exception CapEx_PermitCCallViolation cs + else if ((\<not>(CapStruct_permit_ccall cb_val))) then + raise_c2_exception CapEx_PermitCCallViolation cb + else if ((\<not>(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \<ge> ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else + (execute_branch_pcc + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) \<then> + write_reg inCCallDelay_ref (vec_of_bits [B1] :: 1 Word.word)) \<then> + write_reg + C26_ref + ((capStructToCapReg + (cb_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) + :: 257 Word.word))))))))" + + +(*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCSeal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((\<not>(CapStruct_tag ct_val))) \<or> (((((getCapCursor ct_val)) = ((Word.uint ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))) + then + writeCapReg cd1 cs_val + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\<not>(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\<not> success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CBuildCap :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBuildCap cd1 cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let cb_base = (getCapBase cb_val) in + (let ct_base = (getCapBase ct_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_top = (getCapTop ct_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let ct_offset = (getCapOffset ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then + raise_c2_exception CapEx_UserDefViolation cb + else + (let (exact, cd11) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_base :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) ct_top :: 65 Word.word))) in + (let (representable, cd2) = + (setCapOffset cd11 + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_offset :: 64 Word.word))) in + (let cd3 = (setCapPerms cd2 ct_perms) in + (assert_exp exact ('''') \<then> assert_exp representable ('''')) \<then> writeCapReg cd1 cd3))))))))))))))))" + + +(*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBZ cb imm notzero = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__1 = null_cap))) :: 1 Word.word)) + ((bool_to_bits notzero :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBX :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBX cb imm notset = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits(CapStruct_tag w__1) :: 1 Word.word)) + ((bool_to_bits notset :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CAndPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CAndPerm cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let newCap = + (setCapPerms cb_val + ((and_vec perms ((subrange_vec_dec rt_val (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) :: 31 Word.word))) in + writeCapReg cd1 newCap)))))))" + + +(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_CACHE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CACHE base op1 imm = ( checkCP0Access () )" + + +(*val execute_C2Dump : mword ty5 -> unit*) + +definition execute_C2Dump :: "(5)Word.word \<Rightarrow> unit " where + " execute_C2Dump rt = ( () )" + + +(*val execute_BREAK : unit -> M unit*) + +definition execute_BREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BREAK g__120 = ( SignalException Bp )" + + +(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) + +definition execute_BEQ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BEQ rs rd imm ne likely = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rd :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) :: 1 Word.word)) + ((bool_to_bits ne :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__3 (( 8 :: int)::ii) :: 64 Word.word))) + else return () )))" + + +(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) + +definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BCMPZ rs imm cmp link likely = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii) :: 64 Word.word)) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> regVal . + (let condition = + (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (if condition then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + execute_branch ((add_vec w__1 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__2 (( 8 :: int)::ii) :: 64 Word.word))) + else return () ) \<then> + (if link then wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) linkVal + else return () ))))))" + + +(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ANDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ANDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_AND :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_AND rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((and_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((sign_extend1 (( 32 :: int)::ii) imm :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) imm :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + + +(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (opA :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (opB :: 64 bits) . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute (DADDIU (rs,rt,imm)) = ( execute_DADDIU rs rt imm )" +|" execute (DADDU (rs,rt,rd)) = ( execute_DADDU rs rt rd )" +|" execute (DADDI (rs,rt,imm)) = ( execute_DADDI rs rt imm )" +|" execute (DADD (rs,rt,rd)) = ( execute_DADD rs rt rd )" +|" execute (ADD (rs,rt,rd)) = ( execute_ADD rs rt rd )" +|" execute (ADDI (rs,rt,imm)) = ( execute_ADDI rs rt imm )" +|" execute (ADDU (rs,rt,rd)) = ( execute_ADDU rs rt rd )" +|" execute (ADDIU (rs,rt,imm)) = ( execute_ADDIU rs rt imm )" +|" execute (DSUBU (rs,rt,rd)) = ( execute_DSUBU rs rt rd )" +|" execute (DSUB (rs,rt,rd)) = ( execute_DSUB rs rt rd )" +|" execute (SUB (rs,rt,rd)) = ( execute_SUB rs rt rd )" +|" execute (SUBU (rs,rt,rd)) = ( execute_SUBU rs rt rd )" +|" execute (AND0 (rs,rt,rd)) = ( execute_AND rs rt rd )" +|" execute (ANDI (rs,rt,imm)) = ( execute_ANDI rs rt imm )" +|" execute (OR0 (rs,rt,rd)) = ( execute_OR rs rt rd )" +|" execute (ORI (rs,rt,imm)) = ( execute_ORI rs rt imm )" +|" execute (NOR (rs,rt,rd)) = ( execute_NOR rs rt rd )" +|" execute (XOR0 (rs,rt,rd)) = ( execute_XOR rs rt rd )" +|" execute (XORI (rs,rt,imm)) = ( execute_XORI rs rt imm )" +|" execute (LUI (rt,imm)) = ( execute_LUI rt imm )" +|" execute (DSLL (rt,rd,sa)) = ( execute_DSLL rt rd sa )" +|" execute (DSLL32 (rt,rd,sa)) = ( execute_DSLL32 rt rd sa )" +|" execute (DSLLV (rs,rt,rd)) = ( execute_DSLLV rs rt rd )" +|" execute (DSRA (rt,rd,sa)) = ( execute_DSRA rt rd sa )" +|" execute (DSRA32 (rt,rd,sa)) = ( execute_DSRA32 rt rd sa )" +|" execute (DSRAV (rs,rt,rd)) = ( execute_DSRAV rs rt rd )" +|" execute (DSRL (rt,rd,sa)) = ( execute_DSRL rt rd sa )" +|" execute (DSRL32 (rt,rd,sa)) = ( execute_DSRL32 rt rd sa )" +|" execute (DSRLV (rs,rt,rd)) = ( execute_DSRLV rs rt rd )" +|" execute (SLL (rt,rd,sa)) = ( execute_SLL rt rd sa )" +|" execute (SLLV (rs,rt,rd)) = ( execute_SLLV rs rt rd )" +|" execute (SRA (rt,rd,sa)) = ( execute_SRA rt rd sa )" +|" execute (SRAV (rs,rt,rd)) = ( execute_SRAV rs rt rd )" +|" execute (SRL (rt,rd,sa)) = ( execute_SRL rt rd sa )" +|" execute (SRLV (rs,rt,rd)) = ( execute_SRLV rs rt rd )" +|" execute (SLT (rs,rt,rd)) = ( execute_SLT rs rt rd )" +|" execute (SLTI (rs,rt,imm)) = ( execute_SLTI rs rt imm )" +|" execute (SLTU (rs,rt,rd)) = ( execute_SLTU rs rt rd )" +|" execute (SLTIU (rs,rt,imm)) = ( execute_SLTIU rs rt imm )" +|" execute (MOVN (rs,rt,rd)) = ( execute_MOVN rs rt rd )" +|" execute (MOVZ (rs,rt,rd)) = ( execute_MOVZ rs rt rd )" +|" execute (MFHI (rd)) = ( execute_MFHI rd )" +|" execute (MFLO (rd)) = ( execute_MFLO rd )" +|" execute (MTHI (rs)) = ( execute_MTHI rs )" +|" execute (MTLO (rs)) = ( execute_MTLO rs )" +|" execute (MUL (rs,rt,rd)) = ( execute_MUL rs rt rd )" +|" execute (MULT (rs,rt)) = ( execute_MULT rs rt )" +|" execute (MULTU (rs,rt)) = ( execute_MULTU rs rt )" +|" execute (DMULT (rs,rt)) = ( execute_DMULT rs rt )" +|" execute (DMULTU (rs,rt)) = ( execute_DMULTU rs rt )" +|" execute (MADD (rs,rt)) = ( execute_MADD rs rt )" +|" execute (MADDU (rs,rt)) = ( execute_MADDU rs rt )" +|" execute (MSUB (rs,rt)) = ( execute_MSUB rs rt )" +|" execute (MSUBU (rs,rt)) = ( execute_MSUBU rs rt )" +|" execute (DIV (rs,rt)) = ( execute_DIV rs rt )" +|" execute (DIVU (rs,rt)) = ( execute_DIVU rs rt )" +|" execute (DDIV (rs,rt)) = ( execute_DDIV rs rt )" +|" execute (DDIVU (rs,rt)) = ( execute_DDIVU rs rt )" +|" execute (J (offset)) = ( execute_J offset )" +|" execute (JAL (offset)) = ( execute_JAL offset )" +|" execute (JR (rs)) = ( execute_JR rs )" +|" execute (JALR (rs,rd)) = ( execute_JALR rs rd )" +|" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )" +|" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )" +|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))" +|" execute (ImplementationDefinedStopFetching (g__118)) = ( + return ((execute_ImplementationDefinedStopFetching g__118)))" +|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )" +|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )" +|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )" +|" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )" +|" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )" +|" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )" +|" execute (Store (width,conditional,base,rt,offset)) = ( execute_Store width conditional base rt offset )" +|" execute (LWL (base,rt,offset)) = ( execute_LWL base rt offset )" +|" execute (LWR (base,rt,offset)) = ( execute_LWR base rt offset )" +|" execute (SWL (base,rt,offset)) = ( execute_SWL base rt offset )" +|" execute (SWR (base,rt,offset)) = ( execute_SWR base rt offset )" +|" execute (LDL (base,rt,offset)) = ( execute_LDL base rt offset )" +|" execute (LDR (base,rt,offset)) = ( execute_LDR base rt offset )" +|" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )" +|" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )" +|" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )" +|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))" +|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )" +|" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )" +|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))" +|" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )" +|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )" +|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )" +|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )" +|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )" +|" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )" +|" execute (ERET (g__128)) = ( execute_ERET g__128 )" +|" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )" +|" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )" +|" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )" +|" execute (CGetOffset (rd,cb)) = ( execute_CGetOffset rd cb )" +|" execute (CGetLen (rd,cb)) = ( execute_CGetLen rd cb )" +|" execute (CGetTag (rd,cb)) = ( execute_CGetTag rd cb )" +|" execute (CGetSealed (rd,cb)) = ( execute_CGetSealed rd cb )" +|" execute (CGetAddr (rd,cb)) = ( execute_CGetAddr rd cb )" +|" execute (CGetPCC (cd1)) = ( execute_CGetPCC cd1 )" +|" execute (CGetPCCSetOffset (cd1,rs)) = ( execute_CGetPCCSetOffset cd1 rs )" +|" execute (CGetCause (rd)) = ( execute_CGetCause rd )" +|" execute (CSetCause (rt)) = ( execute_CSetCause rt )" +|" execute (CReadHwr (cd1,sel)) = ( execute_CReadHwr cd1 sel )" +|" execute (CWriteHwr (cb,sel)) = ( execute_CWriteHwr cb sel )" +|" execute (CAndPerm (cd1,cb,rt)) = ( execute_CAndPerm cd1 cb rt )" +|" execute (CToPtr (rd,cb,ct)) = ( execute_CToPtr rd cb ct )" +|" execute (CSub (rd,cb,ct)) = ( execute_CSub rd cb ct )" +|" execute (CPtrCmp (rd,cb,ct,op1)) = ( execute_CPtrCmp rd cb ct op1 )" +|" execute (CIncOffset (cd1,cb,rt)) = ( execute_CIncOffset cd1 cb rt )" +|" execute (CIncOffsetImmediate (cd1,cb,imm)) = ( execute_CIncOffsetImmediate cd1 cb imm )" +|" execute (CSetOffset (cd1,cb,rt)) = ( execute_CSetOffset cd1 cb rt )" +|" execute (CSetBounds (cd1,cb,rt)) = ( execute_CSetBounds cd1 cb rt )" +|" execute (CSetBoundsImmediate (cd1,cb,imm)) = ( execute_CSetBoundsImmediate cd1 cb imm )" +|" execute (CSetBoundsExact (cd1,cb,rt)) = ( execute_CSetBoundsExact cd1 cb rt )" +|" execute (CClearTag (cd1,cb)) = ( execute_CClearTag cd1 cb )" +|" execute (CMOVX (cd1,cb,rt,ismovn)) = ( execute_CMOVX cd1 cb rt ismovn )" +|" execute (ClearRegs (regset,m)) = ( execute_ClearRegs regset m )" +|" execute (CFromPtr (cd1,cb,rt)) = ( execute_CFromPtr cd1 cb rt )" +|" execute (CBuildCap (cd1,cb,ct)) = ( execute_CBuildCap cd1 cb ct )" +|" execute (CCopyType (cd1,cb,ct)) = ( execute_CCopyType cd1 cb ct )" +|" execute (CCheckPerm (cs,rt)) = ( execute_CCheckPerm cs rt )" +|" execute (CCheckType (cs,cb)) = ( execute_CCheckType cs cb )" +|" execute (CTestSubset (rd,cb,ct)) = ( execute_CTestSubset rd cb ct )" +|" execute (CSeal (cd1,cs,ct)) = ( execute_CSeal cd1 cs ct )" +|" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )" +|" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )" +|" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )" +|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )" +|" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )" +|" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )" +|" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )" +|" execute (CLoad (rd,cb,rt,offset,signext,arg5,linked)) = ( + execute_CLoad rd cb rt offset signext arg5 linked )" +|" execute (CStore (rs,cb,rt,rd,offset,width,conditional)) = ( + execute_CStore rs cb rt rd offset width conditional )" +|" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )" +|" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )" +|" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))" +|" execute (RI (g__130)) = ( execute_RI g__130 )" + + +(*val supported_instructions : ast -> maybe ast*) + +definition supported_instructions :: " ast \<Rightarrow>(ast)option " where + " supported_instructions instr = ( Some instr )" + + +(*val fetch_and_execute : unit -> M unit*) + +definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " fetch_and_execute _ = ( + catch_early_return + (((whileM () + (\<lambda> unit_var . return True) + (\<lambda> unit_var . + liftR ((read_reg nextPC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . + (liftR (write_reg PC_ref w__0) \<then> + liftR ((read_reg branchPending_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__1 :: 1 bits) . + ((liftR (write_reg inBranchDelay_ref w__1) \<then> + liftR (write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word))) \<then> + liftR ((read_reg inBranchDelay_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref :: ( 64 Word.word) M)) + else + liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . + ((liftR (write_reg nextPC_ref w__5) \<then> + liftR (cp2_next_pc () )) \<then> + liftR (read_reg instCount_ref)) \<bind> (\<lambda> (w__6 :: ii) . + (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \<then> + liftR ((read_reg PC_ref :: ( 64 Word.word) M))) \<bind> (\<lambda> (w__7 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in + try_catchR (liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 Word.word) . + liftR ((TranslatePC w__8 :: ( 64 Word.word) M)) \<bind> (\<lambda> pc_pa . + liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> instr . + (let instr_ast = (decode instr) in + (case instr_ast of + Some ((HCF (_))) => + (let (_ :: unit) = + (prerr_endline (''simulation stopped due to halt instruction.'')) in + (early_return () :: (unit, unit) MR)) + | Some (ast) => liftR (execute ast) + | None => + (let (_ :: unit) = (prerr_endline (''Decode failed'')) in + liftR (exit0 () )) + )))))) (\<lambda>x . + (case x of ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \<then> + liftR (skip () )) \<then> liftR (skip () )))" + + +(*val main : unit -> M unit*) + +(*val dump_mips_state : unit -> M unit*) + +definition dump_mips_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " dump_mips_state _ = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> idx unit_var . + (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) idx :: 5 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: + 64 Word.word) . + return ((let _ = + (prerr_endline + (((op@) (''DEBUG MIPS REG '') + (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + () ))))))))" + + +definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " main _ = ( + ((init_cp0_state () \<then> + init_cp2_state () ) \<then> + write_reg + nextPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word))) \<then> + ((let startTime = (get_time_ns () ) in + fetch_and_execute () \<then> + ((let endTime = (get_time_ns () ) in + (let elapsed = (endTime - startTime) in + read_reg instCount_ref \<bind> (\<lambda> (w__0 :: ii) . + (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in + (let ips = (inst_1e9 div elapsed) in + ((dump_mips_state () \<then> + dump_cp2_state () ) \<then> + read_reg instCount_ref) \<bind> (\<lambda> (w__1 :: ii) . + (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in + (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in + return ((print_int (''Instructions per second: '') ips))))))))))))))" + + +(*val initialize_registers : unit -> M unit*) + +definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " initialize_registers _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (write_reg PC_ref w__0 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . + (write_reg nextPC_ref w__1 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . + (write_reg TLBProbe_ref w__2 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . + (write_reg TLBIndex_ref w__3 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . + (write_reg TLBRandom_ref w__4 \<then> + undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__5 :: TLBEntryLoReg) . + (write_reg TLBEntryLo0_ref w__5 \<then> + undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__6 :: TLBEntryLoReg) . + (write_reg TLBEntryLo1_ref w__6 \<then> + undefined_ContextReg () ) \<bind> (\<lambda> (w__7 :: ContextReg) . + (write_reg TLBContext_ref w__7 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . + (write_reg TLBPageMask_ref w__8 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . + (write_reg TLBWired_ref w__9 \<then> + undefined_TLBEntryHiReg () ) \<bind> (\<lambda> (w__10 :: TLBEntryHiReg) . + (write_reg TLBEntryHi_ref w__10 \<then> + undefined_XContextReg () ) \<bind> (\<lambda> (w__11 :: XContextReg) . + (write_reg TLBXContext_ref w__11 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__12 :: TLBEntry) . + (write_reg TLBEntry00_ref w__12 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__13 :: TLBEntry) . + (write_reg TLBEntry01_ref w__13 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__14 :: TLBEntry) . + (write_reg TLBEntry02_ref w__14 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__15 :: TLBEntry) . + (write_reg TLBEntry03_ref w__15 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__16 :: TLBEntry) . + (write_reg TLBEntry04_ref w__16 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__17 :: TLBEntry) . + (write_reg TLBEntry05_ref w__17 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__18 :: TLBEntry) . + (write_reg TLBEntry06_ref w__18 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__19 :: TLBEntry) . + (write_reg TLBEntry07_ref w__19 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__20 :: TLBEntry) . + (write_reg TLBEntry08_ref w__20 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__21 :: TLBEntry) . + (write_reg TLBEntry09_ref w__21 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__22 :: TLBEntry) . + (write_reg TLBEntry10_ref w__22 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__23 :: TLBEntry) . + (write_reg TLBEntry11_ref w__23 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__24 :: TLBEntry) . + (write_reg TLBEntry12_ref w__24 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__25 :: TLBEntry) . + (write_reg TLBEntry13_ref w__25 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__26 :: TLBEntry) . + (write_reg TLBEntry14_ref w__26 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__27 :: TLBEntry) . + (write_reg TLBEntry15_ref w__27 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__28 :: TLBEntry) . + (write_reg TLBEntry16_ref w__28 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__29 :: TLBEntry) . + (write_reg TLBEntry17_ref w__29 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__30 :: TLBEntry) . + (write_reg TLBEntry18_ref w__30 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__31 :: TLBEntry) . + (write_reg TLBEntry19_ref w__31 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__32 :: TLBEntry) . + (write_reg TLBEntry20_ref w__32 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__33 :: TLBEntry) . + (write_reg TLBEntry21_ref w__33 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__34 :: TLBEntry) . + (write_reg TLBEntry22_ref w__34 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__35 :: TLBEntry) . + (write_reg TLBEntry23_ref w__35 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__36 :: TLBEntry) . + (write_reg TLBEntry24_ref w__36 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__37 :: TLBEntry) . + (write_reg TLBEntry25_ref w__37 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__38 :: TLBEntry) . + (write_reg TLBEntry26_ref w__38 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__39 :: TLBEntry) . + (write_reg TLBEntry27_ref w__39 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__40 :: TLBEntry) . + (write_reg TLBEntry28_ref w__40 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__41 :: TLBEntry) . + (write_reg TLBEntry29_ref w__41 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__42 :: TLBEntry) . + (write_reg TLBEntry30_ref w__42 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__43 :: TLBEntry) . + (write_reg TLBEntry31_ref w__43 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__44 :: TLBEntry) . + (write_reg TLBEntry32_ref w__44 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__45 :: TLBEntry) . + (write_reg TLBEntry33_ref w__45 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__46 :: TLBEntry) . + (write_reg TLBEntry34_ref w__46 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__47 :: TLBEntry) . + (write_reg TLBEntry35_ref w__47 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__48 :: TLBEntry) . + (write_reg TLBEntry36_ref w__48 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__49 :: TLBEntry) . + (write_reg TLBEntry37_ref w__49 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__50 :: TLBEntry) . + (write_reg TLBEntry38_ref w__50 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__51 :: TLBEntry) . + (write_reg TLBEntry39_ref w__51 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__52 :: TLBEntry) . + (write_reg TLBEntry40_ref w__52 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__53 :: TLBEntry) . + (write_reg TLBEntry41_ref w__53 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__54 :: TLBEntry) . + (write_reg TLBEntry42_ref w__54 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__55 :: TLBEntry) . + (write_reg TLBEntry43_ref w__55 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__56 :: TLBEntry) . + (write_reg TLBEntry44_ref w__56 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__57 :: TLBEntry) . + (write_reg TLBEntry45_ref w__57 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__58 :: TLBEntry) . + (write_reg TLBEntry46_ref w__58 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__59 :: TLBEntry) . + (write_reg TLBEntry47_ref w__59 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__60 :: TLBEntry) . + (write_reg TLBEntry48_ref w__60 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__61 :: TLBEntry) . + (write_reg TLBEntry49_ref w__61 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__62 :: TLBEntry) . + (write_reg TLBEntry50_ref w__62 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__63 :: TLBEntry) . + (write_reg TLBEntry51_ref w__63 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__64 :: TLBEntry) . + (write_reg TLBEntry52_ref w__64 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__65 :: TLBEntry) . + (write_reg TLBEntry53_ref w__65 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__66 :: TLBEntry) . + (write_reg TLBEntry54_ref w__66 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__67 :: TLBEntry) . + (write_reg TLBEntry55_ref w__67 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__68 :: TLBEntry) . + (write_reg TLBEntry56_ref w__68 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__69 :: TLBEntry) . + (write_reg TLBEntry57_ref w__69 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__70 :: TLBEntry) . + (write_reg TLBEntry58_ref w__70 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__71 :: TLBEntry) . + (write_reg TLBEntry59_ref w__71 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__72 :: TLBEntry) . + (write_reg TLBEntry60_ref w__72 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__73 :: TLBEntry) . + (write_reg TLBEntry61_ref w__73 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__74 :: TLBEntry) . + (write_reg TLBEntry62_ref w__74 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__75 :: TLBEntry) . + (write_reg TLBEntry63_ref w__75 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . + (write_reg CP0Compare_ref w__76 \<then> + undefined_CauseReg () ) \<bind> (\<lambda> (w__77 :: CauseReg) . + (write_reg CP0Cause_ref w__77 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . + (write_reg CP0EPC_ref w__78 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . + (write_reg CP0ErrorEPC_ref w__79 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . + (write_reg CP0LLBit_ref w__80 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . + (write_reg CP0LLAddr_ref w__81 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . + (write_reg CP0BadVAddr_ref w__82 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . + (write_reg CP0Count_ref w__83 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . + (write_reg CP0HWREna_ref w__84 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . + (write_reg CP0UserLocal_ref w__85 \<then> + undefined_StatusReg () ) \<bind> (\<lambda> (w__86 :: StatusReg) . + (write_reg CP0Status_ref w__86 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__87 :: 1 bits) . + (write_reg branchPending_ref w__87 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . + (write_reg inBranchDelay_ref w__88 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . + (write_reg delayedPC_ref w__89 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . + (write_reg HI_ref w__90 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . + (write_reg LO_ref w__91 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__92 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__93 :: ( 64 bits) list) . + (write_reg GPR_ref w__93 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__94 :: 8 bits) . + (write_reg UART_WDATA_ref w__94 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__95 :: 1 bits) . + (write_reg UART_WRITTEN_ref w__95 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__96 :: 8 bits) . + (write_reg UART_RDATA_ref w__96 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__97 :: 1 bits) . + (write_reg UART_RVALID_ref w__97 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__98 :: CapReg) . + (write_reg PCC_ref w__98 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . + (write_reg nextPCC_ref w__99 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . + (write_reg delayedPCC_ref w__100 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__101 :: 1 bits) . + (write_reg inCCallDelay_ref w__101 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__102 :: CapReg) . + (write_reg C00_ref w__102 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . + (write_reg C01_ref w__103 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . + (write_reg C02_ref w__104 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . + (write_reg C03_ref w__105 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . + (write_reg C04_ref w__106 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . + (write_reg C05_ref w__107 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . + (write_reg C06_ref w__108 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . + (write_reg C07_ref w__109 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . + (write_reg C08_ref w__110 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . + (write_reg C09_ref w__111 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . + (write_reg C10_ref w__112 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . + (write_reg C11_ref w__113 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . + (write_reg C12_ref w__114 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . + (write_reg C13_ref w__115 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . + (write_reg C14_ref w__116 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . + (write_reg C15_ref w__117 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . + (write_reg C16_ref w__118 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . + (write_reg C17_ref w__119 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . + (write_reg C18_ref w__120 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . + (write_reg C19_ref w__121 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . + (write_reg C20_ref w__122 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . + (write_reg C21_ref w__123 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . + (write_reg C22_ref w__124 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . + (write_reg C23_ref w__125 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . + (write_reg C24_ref w__126 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . + (write_reg C25_ref w__127 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . + (write_reg C26_ref w__128 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . + (write_reg C27_ref w__129 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . + (write_reg C28_ref w__130 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . + (write_reg C29_ref w__131 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . + (write_reg C30_ref w__132 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . + (write_reg C31_ref w__133 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . + (write_reg CTLSU_ref w__134 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . + (write_reg CTLSP_ref w__135 \<then> + undefined_CapCauseReg () ) \<bind> (\<lambda> (w__136 :: CapCauseReg) . + (write_reg CapCause_ref w__136 \<then> + undefined_int () ) \<bind> (\<lambda> (w__137 :: ii) . write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| instCount = ((( 0 :: int)::ii)), + CapCause = + (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + CTLSP = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + CTLSU = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C31 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C30 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C29 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C28 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C27 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C26 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C25 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C24 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C23 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C22 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C21 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C20 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C19 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C18 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C17 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C16 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C15 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C14 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C13 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C12 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C11 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C10 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C09 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C08 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C07 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C06 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C05 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C04 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C03 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C02 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C01 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C00 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + inCCallDelay = ((vec_of_bits [B0] :: 1 Word.word)), + delayedPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + nextPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + PCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + UART_RVALID = ((vec_of_bits [B0] :: 1 Word.word)), + UART_RDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + UART_WRITTEN = ((vec_of_bits [B0] :: 1 Word.word)), + UART_WDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + GPR = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + LO = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + HI = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + delayedPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + inBranchDelay = ((vec_of_bits [B0] :: 1 Word.word)), + branchPending = ((vec_of_bits [B0] :: 1 Word.word)), + CP0Status = + (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0UserLocal = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0HWREna = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Count = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0BadVAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLBit = ((vec_of_bits [B0] :: 1 Word.word)), + CP0ErrorEPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0EPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0Cause = + (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Compare = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TLBEntry63 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry62 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry61 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry60 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry59 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry58 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry57 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry56 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry55 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry54 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry53 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry52 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry51 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry50 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry49 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry48 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry47 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry46 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry45 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry44 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry43 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry42 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry41 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry40 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry39 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry38 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry37 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry36 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry35 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry34 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry33 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry32 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry31 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry30 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry29 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry28 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry27 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry26 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry25 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry24 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry23 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry22 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry21 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry20 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry19 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry18 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry17 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry16 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry15 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry14 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry13 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry12 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry11 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry10 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry09 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry08 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry07 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry06 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry05 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry04 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry03 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry02 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry01 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry00 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBXContext = + (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryHi = + (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + TLBContext = + (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryLo1 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBEntryLo0 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBProbe = ((vec_of_bits [B0] :: 1 Word.word)), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/cheri/Cheri_lemmas.thy b/snapshots/isabelle/cheri/Cheri_lemmas.thy new file mode 100644 index 00000000..6dbee433 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_lemmas.thy @@ -0,0 +1,1205 @@ +theory Cheri_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Cheri +begin + +abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def + CTLSP_ref_def CTLSU_ref_def C30_ref_def C28_ref_def C27_ref_def C26_ref_def C25_ref_def + C24_ref_def C23_ref_def C22_ref_def C21_ref_def C20_ref_def C19_ref_def C18_ref_def C17_ref_def + C16_ref_def C15_ref_def C14_ref_def C13_ref_def C12_ref_def C11_ref_def C10_ref_def C09_ref_def + C08_ref_def C07_ref_def C06_ref_def C05_ref_def C04_ref_def C03_ref_def C02_ref_def C01_ref_def + C00_ref_def inCCallDelay_ref_def nextPCC_ref_def delayedPCC_ref_def PCC_ref_def C31_ref_def + C29_ref_def UART_RVALID_ref_def UART_RDATA_ref_def UART_WRITTEN_ref_def UART_WDATA_ref_def + GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def inBranchDelay_ref_def branchPending_ref_def + CP0Status_ref_def CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def + CP0LLAddr_ref_def CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def + CP0Compare_ref_def TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def + TLBEntry59_ref_def TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def + TLBEntry54_ref_def TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def + TLBEntry49_ref_def TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def + TLBEntry44_ref_def TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def + TLBEntry39_ref_def TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def + TLBEntry34_ref_def TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def + TLBEntry29_ref_def TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def + TLBEntry24_ref_def TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def + TLBEntry19_ref_def TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def + TLBEntry14_ref_def TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def + TLBEntry09_ref_def TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def + TLBEntry04_ref_def TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def + TLBXContext_ref_def TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def + TLBEntryLo1_ref_def TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def + nextPC_ref_def PC_ref_def + +lemma regval_CapCauseReg[simp]: + "CapCauseReg_of_regval (regval_of_CapCauseReg v) = Some v" + by (auto simp: regval_of_CapCauseReg_def) + +lemma regval_CauseReg[simp]: + "CauseReg_of_regval (regval_of_CauseReg v) = Some v" + by (auto simp: regval_of_CauseReg_def) + +lemma regval_ContextReg[simp]: + "ContextReg_of_regval (regval_of_ContextReg v) = Some v" + by (auto simp: regval_of_ContextReg_def) + +lemma regval_StatusReg[simp]: + "StatusReg_of_regval (regval_of_StatusReg v) = Some v" + by (auto simp: regval_of_StatusReg_def) + +lemma regval_TLBEntry[simp]: + "TLBEntry_of_regval (regval_of_TLBEntry v) = Some v" + by (auto simp: regval_of_TLBEntry_def) + +lemma regval_TLBEntryHiReg[simp]: + "TLBEntryHiReg_of_regval (regval_of_TLBEntryHiReg v) = Some v" + by (auto simp: regval_of_TLBEntryHiReg_def) + +lemma regval_TLBEntryLoReg[simp]: + "TLBEntryLoReg_of_regval (regval_of_TLBEntryLoReg v) = Some v" + by (auto simp: regval_of_TLBEntryLoReg_def) + +lemma regval_XContextReg[simp]: + "XContextReg_of_regval (regval_of_XContextReg v) = Some v" + by (auto simp: regval_of_XContextReg_def) + +lemma regval_int[simp]: + "int_of_regval (regval_of_int v) = Some v" + by (auto simp: regval_of_int_def) + +lemma regval_vector_16_dec_bit[simp]: + "vector_16_dec_bit_of_regval (regval_of_vector_16_dec_bit v) = Some v" + by (auto simp: regval_of_vector_16_dec_bit_def) + +lemma regval_vector_1_dec_bit[simp]: + "vector_1_dec_bit_of_regval (regval_of_vector_1_dec_bit v) = Some v" + by (auto simp: regval_of_vector_1_dec_bit_def) + +lemma regval_vector_257_dec_bit[simp]: + "vector_257_dec_bit_of_regval (regval_of_vector_257_dec_bit v) = Some v" + by (auto simp: regval_of_vector_257_dec_bit_def) + +lemma regval_vector_32_dec_bit[simp]: + "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v" + by (auto simp: regval_of_vector_32_dec_bit_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma regval_vector_6_dec_bit[simp]: + "vector_6_dec_bit_of_regval (regval_of_vector_6_dec_bit v) = Some v" + by (auto simp: regval_of_vector_6_dec_bit_def) + +lemma regval_vector_8_dec_bit[simp]: + "vector_8_dec_bit_of_regval (regval_of_vector_8_dec_bit v) = Some v" + by (auto simp: regval_of_vector_8_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_instCount[simp]: + "liftS (read_reg instCount_ref) = readS (instCount \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_instCount[simp]: + "liftS (write_reg instCount_ref v) = updateS (regstate_update (instCount_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CapCause[simp]: + "liftS (read_reg CapCause_ref) = readS (CapCause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CapCause[simp]: + "liftS (write_reg CapCause_ref v) = updateS (regstate_update (CapCause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSP[simp]: + "liftS (read_reg CTLSP_ref) = readS (CTLSP \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSP[simp]: + "liftS (write_reg CTLSP_ref v) = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSU[simp]: + "liftS (read_reg CTLSU_ref) = readS (CTLSU \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSU[simp]: + "liftS (write_reg CTLSU_ref v) = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C30[simp]: + "liftS (read_reg C30_ref) = readS (C30 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C30[simp]: + "liftS (write_reg C30_ref v) = updateS (regstate_update (C30_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C28[simp]: + "liftS (read_reg C28_ref) = readS (C28 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C28[simp]: + "liftS (write_reg C28_ref v) = updateS (regstate_update (C28_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C27[simp]: + "liftS (read_reg C27_ref) = readS (C27 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C27[simp]: + "liftS (write_reg C27_ref v) = updateS (regstate_update (C27_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C26[simp]: + "liftS (read_reg C26_ref) = readS (C26 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C26[simp]: + "liftS (write_reg C26_ref v) = updateS (regstate_update (C26_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C25[simp]: + "liftS (read_reg C25_ref) = readS (C25 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C25[simp]: + "liftS (write_reg C25_ref v) = updateS (regstate_update (C25_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C24[simp]: + "liftS (read_reg C24_ref) = readS (C24 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C24[simp]: + "liftS (write_reg C24_ref v) = updateS (regstate_update (C24_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C23[simp]: + "liftS (read_reg C23_ref) = readS (C23 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C23[simp]: + "liftS (write_reg C23_ref v) = updateS (regstate_update (C23_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C22[simp]: + "liftS (read_reg C22_ref) = readS (C22 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C22[simp]: + "liftS (write_reg C22_ref v) = updateS (regstate_update (C22_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C21[simp]: + "liftS (read_reg C21_ref) = readS (C21 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C21[simp]: + "liftS (write_reg C21_ref v) = updateS (regstate_update (C21_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C20[simp]: + "liftS (read_reg C20_ref) = readS (C20 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C20[simp]: + "liftS (write_reg C20_ref v) = updateS (regstate_update (C20_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C19[simp]: + "liftS (read_reg C19_ref) = readS (C19 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C19[simp]: + "liftS (write_reg C19_ref v) = updateS (regstate_update (C19_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C18[simp]: + "liftS (read_reg C18_ref) = readS (C18 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C18[simp]: + "liftS (write_reg C18_ref v) = updateS (regstate_update (C18_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C17[simp]: + "liftS (read_reg C17_ref) = readS (C17 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C17[simp]: + "liftS (write_reg C17_ref v) = updateS (regstate_update (C17_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C16[simp]: + "liftS (read_reg C16_ref) = readS (C16 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C16[simp]: + "liftS (write_reg C16_ref v) = updateS (regstate_update (C16_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C15[simp]: + "liftS (read_reg C15_ref) = readS (C15 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C15[simp]: + "liftS (write_reg C15_ref v) = updateS (regstate_update (C15_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C14[simp]: + "liftS (read_reg C14_ref) = readS (C14 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C14[simp]: + "liftS (write_reg C14_ref v) = updateS (regstate_update (C14_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C13[simp]: + "liftS (read_reg C13_ref) = readS (C13 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C13[simp]: + "liftS (write_reg C13_ref v) = updateS (regstate_update (C13_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C12[simp]: + "liftS (read_reg C12_ref) = readS (C12 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C12[simp]: + "liftS (write_reg C12_ref v) = updateS (regstate_update (C12_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C11[simp]: + "liftS (read_reg C11_ref) = readS (C11 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C11[simp]: + "liftS (write_reg C11_ref v) = updateS (regstate_update (C11_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C10[simp]: + "liftS (read_reg C10_ref) = readS (C10 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C10[simp]: + "liftS (write_reg C10_ref v) = updateS (regstate_update (C10_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C09[simp]: + "liftS (read_reg C09_ref) = readS (C09 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C09[simp]: + "liftS (write_reg C09_ref v) = updateS (regstate_update (C09_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C08[simp]: + "liftS (read_reg C08_ref) = readS (C08 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C08[simp]: + "liftS (write_reg C08_ref v) = updateS (regstate_update (C08_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C07[simp]: + "liftS (read_reg C07_ref) = readS (C07 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C07[simp]: + "liftS (write_reg C07_ref v) = updateS (regstate_update (C07_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C06[simp]: + "liftS (read_reg C06_ref) = readS (C06 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C06[simp]: + "liftS (write_reg C06_ref v) = updateS (regstate_update (C06_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C05[simp]: + "liftS (read_reg C05_ref) = readS (C05 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C05[simp]: + "liftS (write_reg C05_ref v) = updateS (regstate_update (C05_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C04[simp]: + "liftS (read_reg C04_ref) = readS (C04 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C04[simp]: + "liftS (write_reg C04_ref v) = updateS (regstate_update (C04_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C03[simp]: + "liftS (read_reg C03_ref) = readS (C03 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C03[simp]: + "liftS (write_reg C03_ref v) = updateS (regstate_update (C03_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C02[simp]: + "liftS (read_reg C02_ref) = readS (C02 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C02[simp]: + "liftS (write_reg C02_ref v) = updateS (regstate_update (C02_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C01[simp]: + "liftS (read_reg C01_ref) = readS (C01 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C01[simp]: + "liftS (write_reg C01_ref v) = updateS (regstate_update (C01_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C00[simp]: + "liftS (read_reg C00_ref) = readS (C00 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C00[simp]: + "liftS (write_reg C00_ref v) = updateS (regstate_update (C00_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inCCallDelay[simp]: + "liftS (read_reg inCCallDelay_ref) = readS (inCCallDelay \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inCCallDelay[simp]: + "liftS (write_reg inCCallDelay_ref v) = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPCC[simp]: + "liftS (read_reg nextPCC_ref) = readS (nextPCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPCC[simp]: + "liftS (write_reg nextPCC_ref v) = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPCC[simp]: + "liftS (read_reg delayedPCC_ref) = readS (delayedPCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPCC[simp]: + "liftS (write_reg delayedPCC_ref v) = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PCC[simp]: + "liftS (read_reg PCC_ref) = readS (PCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PCC[simp]: + "liftS (write_reg PCC_ref v) = updateS (regstate_update (PCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C31[simp]: + "liftS (read_reg C31_ref) = readS (C31 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C31[simp]: + "liftS (write_reg C31_ref v) = updateS (regstate_update (C31_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C29[simp]: + "liftS (read_reg C29_ref) = readS (C29 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C29[simp]: + "liftS (write_reg C29_ref v) = updateS (regstate_update (C29_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RVALID[simp]: + "liftS (read_reg UART_RVALID_ref) = readS (UART_RVALID \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RVALID[simp]: + "liftS (write_reg UART_RVALID_ref v) = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RDATA[simp]: + "liftS (read_reg UART_RDATA_ref) = readS (UART_RDATA \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RDATA[simp]: + "liftS (write_reg UART_RDATA_ref v) = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WRITTEN[simp]: + "liftS (read_reg UART_WRITTEN_ref) = readS (UART_WRITTEN \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WRITTEN[simp]: + "liftS (write_reg UART_WRITTEN_ref v) = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WDATA[simp]: + "liftS (read_reg UART_WDATA_ref) = readS (UART_WDATA \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WDATA[simp]: + "liftS (write_reg UART_WDATA_ref v) = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_GPR[simp]: + "liftS (read_reg GPR_ref) = readS (GPR \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_GPR[simp]: + "liftS (write_reg GPR_ref v) = updateS (regstate_update (GPR_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_LO[simp]: + "liftS (read_reg LO_ref) = readS (LO \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_LO[simp]: + "liftS (write_reg LO_ref v) = updateS (regstate_update (LO_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HI[simp]: + "liftS (read_reg HI_ref) = readS (HI \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HI[simp]: + "liftS (write_reg HI_ref v) = updateS (regstate_update (HI_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPC[simp]: + "liftS (read_reg delayedPC_ref) = readS (delayedPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPC[simp]: + "liftS (write_reg delayedPC_ref v) = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inBranchDelay[simp]: + "liftS (read_reg inBranchDelay_ref) = readS (inBranchDelay \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inBranchDelay[simp]: + "liftS (write_reg inBranchDelay_ref v) = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_branchPending[simp]: + "liftS (read_reg branchPending_ref) = readS (branchPending \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_branchPending[simp]: + "liftS (write_reg branchPending_ref v) = updateS (regstate_update (branchPending_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Status[simp]: + "liftS (read_reg CP0Status_ref) = readS (CP0Status \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Status[simp]: + "liftS (write_reg CP0Status_ref v) = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0UserLocal[simp]: + "liftS (read_reg CP0UserLocal_ref) = readS (CP0UserLocal \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0UserLocal[simp]: + "liftS (write_reg CP0UserLocal_ref v) = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0HWREna[simp]: + "liftS (read_reg CP0HWREna_ref) = readS (CP0HWREna \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0HWREna[simp]: + "liftS (write_reg CP0HWREna_ref v) = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Count[simp]: + "liftS (read_reg CP0Count_ref) = readS (CP0Count \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Count[simp]: + "liftS (write_reg CP0Count_ref v) = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0BadVAddr[simp]: + "liftS (read_reg CP0BadVAddr_ref) = readS (CP0BadVAddr \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0BadVAddr[simp]: + "liftS (write_reg CP0BadVAddr_ref v) = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLAddr[simp]: + "liftS (read_reg CP0LLAddr_ref) = readS (CP0LLAddr \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLAddr[simp]: + "liftS (write_reg CP0LLAddr_ref v) = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLBit[simp]: + "liftS (read_reg CP0LLBit_ref) = readS (CP0LLBit \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLBit[simp]: + "liftS (write_reg CP0LLBit_ref v) = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0ErrorEPC[simp]: + "liftS (read_reg CP0ErrorEPC_ref) = readS (CP0ErrorEPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0ErrorEPC[simp]: + "liftS (write_reg CP0ErrorEPC_ref v) = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0EPC[simp]: + "liftS (read_reg CP0EPC_ref) = readS (CP0EPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0EPC[simp]: + "liftS (write_reg CP0EPC_ref v) = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Cause[simp]: + "liftS (read_reg CP0Cause_ref) = readS (CP0Cause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Cause[simp]: + "liftS (write_reg CP0Cause_ref v) = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Compare[simp]: + "liftS (read_reg CP0Compare_ref) = readS (CP0Compare \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Compare[simp]: + "liftS (write_reg CP0Compare_ref v) = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry63[simp]: + "liftS (read_reg TLBEntry63_ref) = readS (TLBEntry63 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry63[simp]: + "liftS (write_reg TLBEntry63_ref v) = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry62[simp]: + "liftS (read_reg TLBEntry62_ref) = readS (TLBEntry62 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry62[simp]: + "liftS (write_reg TLBEntry62_ref v) = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry61[simp]: + "liftS (read_reg TLBEntry61_ref) = readS (TLBEntry61 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry61[simp]: + "liftS (write_reg TLBEntry61_ref v) = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry60[simp]: + "liftS (read_reg TLBEntry60_ref) = readS (TLBEntry60 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry60[simp]: + "liftS (write_reg TLBEntry60_ref v) = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry59[simp]: + "liftS (read_reg TLBEntry59_ref) = readS (TLBEntry59 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry59[simp]: + "liftS (write_reg TLBEntry59_ref v) = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry58[simp]: + "liftS (read_reg TLBEntry58_ref) = readS (TLBEntry58 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry58[simp]: + "liftS (write_reg TLBEntry58_ref v) = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry57[simp]: + "liftS (read_reg TLBEntry57_ref) = readS (TLBEntry57 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry57[simp]: + "liftS (write_reg TLBEntry57_ref v) = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry56[simp]: + "liftS (read_reg TLBEntry56_ref) = readS (TLBEntry56 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry56[simp]: + "liftS (write_reg TLBEntry56_ref v) = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry55[simp]: + "liftS (read_reg TLBEntry55_ref) = readS (TLBEntry55 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry55[simp]: + "liftS (write_reg TLBEntry55_ref v) = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry54[simp]: + "liftS (read_reg TLBEntry54_ref) = readS (TLBEntry54 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry54[simp]: + "liftS (write_reg TLBEntry54_ref v) = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry53[simp]: + "liftS (read_reg TLBEntry53_ref) = readS (TLBEntry53 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry53[simp]: + "liftS (write_reg TLBEntry53_ref v) = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry52[simp]: + "liftS (read_reg TLBEntry52_ref) = readS (TLBEntry52 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry52[simp]: + "liftS (write_reg TLBEntry52_ref v) = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry51[simp]: + "liftS (read_reg TLBEntry51_ref) = readS (TLBEntry51 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry51[simp]: + "liftS (write_reg TLBEntry51_ref v) = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry50[simp]: + "liftS (read_reg TLBEntry50_ref) = readS (TLBEntry50 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry50[simp]: + "liftS (write_reg TLBEntry50_ref v) = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry49[simp]: + "liftS (read_reg TLBEntry49_ref) = readS (TLBEntry49 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry49[simp]: + "liftS (write_reg TLBEntry49_ref v) = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry48[simp]: + "liftS (read_reg TLBEntry48_ref) = readS (TLBEntry48 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry48[simp]: + "liftS (write_reg TLBEntry48_ref v) = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry47[simp]: + "liftS (read_reg TLBEntry47_ref) = readS (TLBEntry47 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry47[simp]: + "liftS (write_reg TLBEntry47_ref v) = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry46[simp]: + "liftS (read_reg TLBEntry46_ref) = readS (TLBEntry46 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry46[simp]: + "liftS (write_reg TLBEntry46_ref v) = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry45[simp]: + "liftS (read_reg TLBEntry45_ref) = readS (TLBEntry45 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry45[simp]: + "liftS (write_reg TLBEntry45_ref v) = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry44[simp]: + "liftS (read_reg TLBEntry44_ref) = readS (TLBEntry44 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry44[simp]: + "liftS (write_reg TLBEntry44_ref v) = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry43[simp]: + "liftS (read_reg TLBEntry43_ref) = readS (TLBEntry43 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry43[simp]: + "liftS (write_reg TLBEntry43_ref v) = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry42[simp]: + "liftS (read_reg TLBEntry42_ref) = readS (TLBEntry42 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry42[simp]: + "liftS (write_reg TLBEntry42_ref v) = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry41[simp]: + "liftS (read_reg TLBEntry41_ref) = readS (TLBEntry41 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry41[simp]: + "liftS (write_reg TLBEntry41_ref v) = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry40[simp]: + "liftS (read_reg TLBEntry40_ref) = readS (TLBEntry40 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry40[simp]: + "liftS (write_reg TLBEntry40_ref v) = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry39[simp]: + "liftS (read_reg TLBEntry39_ref) = readS (TLBEntry39 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry39[simp]: + "liftS (write_reg TLBEntry39_ref v) = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry38[simp]: + "liftS (read_reg TLBEntry38_ref) = readS (TLBEntry38 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry38[simp]: + "liftS (write_reg TLBEntry38_ref v) = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry37[simp]: + "liftS (read_reg TLBEntry37_ref) = readS (TLBEntry37 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry37[simp]: + "liftS (write_reg TLBEntry37_ref v) = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry36[simp]: + "liftS (read_reg TLBEntry36_ref) = readS (TLBEntry36 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry36[simp]: + "liftS (write_reg TLBEntry36_ref v) = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry35[simp]: + "liftS (read_reg TLBEntry35_ref) = readS (TLBEntry35 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry35[simp]: + "liftS (write_reg TLBEntry35_ref v) = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry34[simp]: + "liftS (read_reg TLBEntry34_ref) = readS (TLBEntry34 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry34[simp]: + "liftS (write_reg TLBEntry34_ref v) = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry33[simp]: + "liftS (read_reg TLBEntry33_ref) = readS (TLBEntry33 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry33[simp]: + "liftS (write_reg TLBEntry33_ref v) = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry32[simp]: + "liftS (read_reg TLBEntry32_ref) = readS (TLBEntry32 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry32[simp]: + "liftS (write_reg TLBEntry32_ref v) = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry31[simp]: + "liftS (read_reg TLBEntry31_ref) = readS (TLBEntry31 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry31[simp]: + "liftS (write_reg TLBEntry31_ref v) = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry30[simp]: + "liftS (read_reg TLBEntry30_ref) = readS (TLBEntry30 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry30[simp]: + "liftS (write_reg TLBEntry30_ref v) = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry29[simp]: + "liftS (read_reg TLBEntry29_ref) = readS (TLBEntry29 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry29[simp]: + "liftS (write_reg TLBEntry29_ref v) = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry28[simp]: + "liftS (read_reg TLBEntry28_ref) = readS (TLBEntry28 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry28[simp]: + "liftS (write_reg TLBEntry28_ref v) = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry27[simp]: + "liftS (read_reg TLBEntry27_ref) = readS (TLBEntry27 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry27[simp]: + "liftS (write_reg TLBEntry27_ref v) = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry26[simp]: + "liftS (read_reg TLBEntry26_ref) = readS (TLBEntry26 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry26[simp]: + "liftS (write_reg TLBEntry26_ref v) = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry25[simp]: + "liftS (read_reg TLBEntry25_ref) = readS (TLBEntry25 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry25[simp]: + "liftS (write_reg TLBEntry25_ref v) = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry24[simp]: + "liftS (read_reg TLBEntry24_ref) = readS (TLBEntry24 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry24[simp]: + "liftS (write_reg TLBEntry24_ref v) = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry23[simp]: + "liftS (read_reg TLBEntry23_ref) = readS (TLBEntry23 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry23[simp]: + "liftS (write_reg TLBEntry23_ref v) = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry22[simp]: + "liftS (read_reg TLBEntry22_ref) = readS (TLBEntry22 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry22[simp]: + "liftS (write_reg TLBEntry22_ref v) = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry21[simp]: + "liftS (read_reg TLBEntry21_ref) = readS (TLBEntry21 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry21[simp]: + "liftS (write_reg TLBEntry21_ref v) = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry20[simp]: + "liftS (read_reg TLBEntry20_ref) = readS (TLBEntry20 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry20[simp]: + "liftS (write_reg TLBEntry20_ref v) = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry19[simp]: + "liftS (read_reg TLBEntry19_ref) = readS (TLBEntry19 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry19[simp]: + "liftS (write_reg TLBEntry19_ref v) = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry18[simp]: + "liftS (read_reg TLBEntry18_ref) = readS (TLBEntry18 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry18[simp]: + "liftS (write_reg TLBEntry18_ref v) = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry17[simp]: + "liftS (read_reg TLBEntry17_ref) = readS (TLBEntry17 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry17[simp]: + "liftS (write_reg TLBEntry17_ref v) = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry16[simp]: + "liftS (read_reg TLBEntry16_ref) = readS (TLBEntry16 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry16[simp]: + "liftS (write_reg TLBEntry16_ref v) = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry15[simp]: + "liftS (read_reg TLBEntry15_ref) = readS (TLBEntry15 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry15[simp]: + "liftS (write_reg TLBEntry15_ref v) = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry14[simp]: + "liftS (read_reg TLBEntry14_ref) = readS (TLBEntry14 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry14[simp]: + "liftS (write_reg TLBEntry14_ref v) = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry13[simp]: + "liftS (read_reg TLBEntry13_ref) = readS (TLBEntry13 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry13[simp]: + "liftS (write_reg TLBEntry13_ref v) = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry12[simp]: + "liftS (read_reg TLBEntry12_ref) = readS (TLBEntry12 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry12[simp]: + "liftS (write_reg TLBEntry12_ref v) = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry11[simp]: + "liftS (read_reg TLBEntry11_ref) = readS (TLBEntry11 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry11[simp]: + "liftS (write_reg TLBEntry11_ref v) = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry10[simp]: + "liftS (read_reg TLBEntry10_ref) = readS (TLBEntry10 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry10[simp]: + "liftS (write_reg TLBEntry10_ref v) = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry09[simp]: + "liftS (read_reg TLBEntry09_ref) = readS (TLBEntry09 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry09[simp]: + "liftS (write_reg TLBEntry09_ref v) = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry08[simp]: + "liftS (read_reg TLBEntry08_ref) = readS (TLBEntry08 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry08[simp]: + "liftS (write_reg TLBEntry08_ref v) = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry07[simp]: + "liftS (read_reg TLBEntry07_ref) = readS (TLBEntry07 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry07[simp]: + "liftS (write_reg TLBEntry07_ref v) = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry06[simp]: + "liftS (read_reg TLBEntry06_ref) = readS (TLBEntry06 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry06[simp]: + "liftS (write_reg TLBEntry06_ref v) = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry05[simp]: + "liftS (read_reg TLBEntry05_ref) = readS (TLBEntry05 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry05[simp]: + "liftS (write_reg TLBEntry05_ref v) = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry04[simp]: + "liftS (read_reg TLBEntry04_ref) = readS (TLBEntry04 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry04[simp]: + "liftS (write_reg TLBEntry04_ref v) = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry03[simp]: + "liftS (read_reg TLBEntry03_ref) = readS (TLBEntry03 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry03[simp]: + "liftS (write_reg TLBEntry03_ref v) = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry02[simp]: + "liftS (read_reg TLBEntry02_ref) = readS (TLBEntry02 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry02[simp]: + "liftS (write_reg TLBEntry02_ref v) = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry01[simp]: + "liftS (read_reg TLBEntry01_ref) = readS (TLBEntry01 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry01[simp]: + "liftS (write_reg TLBEntry01_ref v) = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry00[simp]: + "liftS (read_reg TLBEntry00_ref) = readS (TLBEntry00 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry00[simp]: + "liftS (write_reg TLBEntry00_ref v) = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBXContext[simp]: + "liftS (read_reg TLBXContext_ref) = readS (TLBXContext \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBXContext[simp]: + "liftS (write_reg TLBXContext_ref v) = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryHi[simp]: + "liftS (read_reg TLBEntryHi_ref) = readS (TLBEntryHi \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryHi[simp]: + "liftS (write_reg TLBEntryHi_ref v) = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBWired[simp]: + "liftS (read_reg TLBWired_ref) = readS (TLBWired \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBWired[simp]: + "liftS (write_reg TLBWired_ref v) = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBPageMask[simp]: + "liftS (read_reg TLBPageMask_ref) = readS (TLBPageMask \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBPageMask[simp]: + "liftS (write_reg TLBPageMask_ref v) = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBContext[simp]: + "liftS (read_reg TLBContext_ref) = readS (TLBContext \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBContext[simp]: + "liftS (write_reg TLBContext_ref v) = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo1[simp]: + "liftS (read_reg TLBEntryLo1_ref) = readS (TLBEntryLo1 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo1[simp]: + "liftS (write_reg TLBEntryLo1_ref v) = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo0[simp]: + "liftS (read_reg TLBEntryLo0_ref) = readS (TLBEntryLo0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo0[simp]: + "liftS (write_reg TLBEntryLo0_ref v) = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBRandom[simp]: + "liftS (read_reg TLBRandom_ref) = readS (TLBRandom \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBRandom[simp]: + "liftS (write_reg TLBRandom_ref v) = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBIndex[simp]: + "liftS (read_reg TLBIndex_ref) = readS (TLBIndex \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBIndex[simp]: + "liftS (write_reg TLBIndex_ref v) = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBProbe[simp]: + "liftS (read_reg TLBProbe_ref) = readS (TLBProbe \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBProbe[simp]: + "liftS (write_reg TLBProbe_ref v) = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/cheri/Cheri_types.thy b/snapshots/isabelle/cheri/Cheri_types.thy new file mode 100644 index 00000000..4139164a --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_types.thy @@ -0,0 +1,2432 @@ +chapter \<open>Generated by Lem from cheri_types.lem.\<close> + +theory "Cheri_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +datatype exception = + ISAException " (unit)" + | Error_not_implemented " (string)" + | Error_misaligned_access " (unit)" + | Error_EBREAK " (unit)" + | Error_internal_error " (unit)" + + + +datatype CauseReg = Mk_CauseReg " ( 32 Word.word)" + + + +datatype CapCauseReg = Mk_CapCauseReg " ( 16 Word.word)" + + + +datatype TLBEntryLoReg = Mk_TLBEntryLoReg " ( 64 Word.word)" + + + +datatype TLBEntryHiReg = Mk_TLBEntryHiReg " ( 64 Word.word)" + + + +datatype ContextReg = Mk_ContextReg " ( 64 Word.word)" + + + +datatype XContextReg = Mk_XContextReg " ( 64 Word.word)" + + + +type_synonym TLBIndexT =" 6 bits " + +datatype TLBEntry = Mk_TLBEntry " ( 117 Word.word)" + + + +datatype StatusReg = Mk_StatusReg " ( 32 Word.word)" + + + +datatype Exception = + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck + + + +type_synonym CapReg =" 257 bits " + +record CapStruct = + + CapStruct_tag ::" bool " + + CapStruct_padding ::" 8 bits " + + CapStruct_otype ::" 24 bits " + + CapStruct_uperms ::" 16 bits " + + CapStruct_perm_reserved11_14 ::" 4 bits " + + CapStruct_access_system_regs ::" bool " + + CapStruct_permit_unseal ::" bool " + + CapStruct_permit_ccall ::" bool " + + CapStruct_permit_seal ::" bool " + + CapStruct_permit_store_local_cap ::" bool " + + CapStruct_permit_store_cap ::" bool " + + CapStruct_permit_load_cap ::" bool " + + CapStruct_permit_store ::" bool " + + CapStruct_permit_load ::" bool " + + CapStruct_permit_execute ::" bool " + + CapStruct_global ::" bool " + + CapStruct_sealed ::" bool " + + CapStruct_address ::" 64 bits " + + CapStruct_base ::" 64 bits " + + CapStruct_length ::" 64 bits " + + + +datatype MemAccessType = Instruction | LoadData | StoreData + + + +datatype AccessLevel = User | Supervisor | Kernel + + + +type_synonym regno =" 5 bits " + +type_synonym imm16 =" 16 bits " + +type_synonym regregreg =" (regno * regno * regno)" + +type_synonym regregimm16 =" (regno * regno * imm16)" + +datatype decode_failure = + No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error + + + +datatype Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU + + + +datatype WordType = B | H | W | D + + + +type_synonym CapLen =" int " + +type_synonym uint64 =" int " + +datatype CPtrCmpOp = CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ + + + +datatype ClearRegSet = GPLo | GPHi | CLo | CHi + + + +datatype (plugins only: size) ast = + DADDIU " ((regno * regno * imm16))" + | DADDU " ((regno * regno * regno))" + | DADDI " ((regno * regno * 16 bits))" + | DADD " ((regno * regno * regno))" + | ADD " ((regno * regno * regno))" + | ADDI " ((regno * regno * 16 bits))" + | ADDU " ((regno * regno * regno))" + | ADDIU " ((regno * regno * 16 bits))" + | DSUBU " ((regno * regno * regno))" + | DSUB " ((regno * regno * regno))" + | SUB " ((regno * regno * regno))" + | SUBU " ((regno * regno * regno))" + | AND0 " ((regno * regno * regno))" + | ANDI " ((regno * regno * 16 bits))" + | OR0 " ((regno * regno * regno))" + | ORI " ((regno * regno * 16 bits))" + | NOR " ((regno * regno * regno))" + | XOR0 " ((regno * regno * regno))" + | XORI " ((regno * regno * 16 bits))" + | LUI " ((regno * imm16))" + | DSLL " ((regno * regno * regno))" + | DSLL32 " ((regno * regno * regno))" + | DSLLV " ((regno * regno * regno))" + | DSRA " ((regno * regno * regno))" + | DSRA32 " ((regno * regno * regno))" + | DSRAV " ((regno * regno * regno))" + | DSRL " ((regno * regno * regno))" + | DSRL32 " ((regno * regno * regno))" + | DSRLV " ((regno * regno * regno))" + | SLL " ((regno * regno * regno))" + | SLLV " ((regno * regno * regno))" + | SRA " ((regno * regno * regno))" + | SRAV " ((regno * regno * regno))" + | SRL " ((regno * regno * regno))" + | SRLV " ((regno * regno * regno))" + | SLT " ((regno * regno * regno))" + | SLTI " ((regno * regno * 16 bits))" + | SLTU " ((regno * regno * regno))" + | SLTIU " ((regno * regno * 16 bits))" + | MOVN " ((regno * regno * regno))" + | MOVZ " ((regno * regno * regno))" + | MFHI " (regno)" + | MFLO " (regno)" + | MTHI " (regno)" + | MTLO " (regno)" + | MUL " ((regno * regno * regno))" + | MULT " ((regno * regno))" + | MULTU " ((regno * regno))" + | DMULT " ((regno * regno))" + | DMULTU " ((regno * regno))" + | MADD " ((regno * regno))" + | MADDU " ((regno * regno))" + | MSUB " ((regno * regno))" + | MSUBU " ((regno * regno))" + | DIV " ((regno * regno))" + | DIVU " ((regno * regno))" + | DDIV " ((regno * regno))" + | DDIVU " ((regno * regno))" + | J " ( 26 bits)" + | JAL " ( 26 bits)" + | JR " (regno)" + | JALR " ((regno * regno))" + | BEQ " ((regno * regno * imm16 * bool * bool))" + | BCMPZ " ((regno * imm16 * Comparison * bool * bool))" + | SYSCALL_THREAD_START " (unit)" + | ImplementationDefinedStopFetching " (unit)" + | SYSCALL " (unit)" + | BREAK " (unit)" + | WAIT " (unit)" + | TRAPREG " ((regno * regno * Comparison))" + | TRAPIMM " ((regno * imm16 * Comparison))" + | Load " ((WordType * bool * bool * regno * regno * imm16))" + | Store " ((WordType * bool * regno * regno * imm16))" + | LWL " ((regno * regno * 16 bits))" + | LWR " ((regno * regno * 16 bits))" + | SWL " ((regno * regno * 16 bits))" + | SWR " ((regno * regno * 16 bits))" + | LDL " ((regno * regno * 16 bits))" + | LDR " ((regno * regno * 16 bits))" + | SDL " ((regno * regno * 16 bits))" + | SDR " ((regno * regno * 16 bits))" + | CACHE " ((regno * regno * 16 bits))" + | PREF " ((regno * regno * 16 bits))" + | SYNC " (unit)" + | MFC0 " ((regno * regno * 3 bits * bool))" + | HCF " (unit)" + | MTC0 " ((regno * regno * 3 bits * bool))" + | TLBWI " (unit)" + | TLBWR " (unit)" + | TLBR " (unit)" + | TLBP " (unit)" + | RDHWR " ((regno * regno))" + | ERET " (unit)" + | CGetPerm " ((regno * regno))" + | CGetType " ((regno * regno))" + | CGetBase " ((regno * regno))" + | CGetLen " ((regno * regno))" + | CGetTag " ((regno * regno))" + | CGetSealed " ((regno * regno))" + | CGetOffset " ((regno * regno))" + | CGetAddr " ((regno * regno))" + | CGetPCC " (regno)" + | CGetPCCSetOffset " ((regno * regno))" + | CGetCause " (regno)" + | CSetCause " (regno)" + | CReadHwr " ((regno * regno))" + | CWriteHwr " ((regno * regno))" + | CAndPerm " ((regno * regno * regno))" + | CToPtr " ((regno * regno * regno))" + | CSub " ((regno * regno * regno))" + | CPtrCmp " ((regno * regno * regno * CPtrCmpOp))" + | CIncOffset " ((regno * regno * regno))" + | CIncOffsetImmediate " ((regno * regno * 11 bits))" + | CSetOffset " ((regno * regno * regno))" + | CSetBounds " ((regno * regno * regno))" + | CSetBoundsImmediate " ((regno * regno * 11 bits))" + | CSetBoundsExact " ((regno * regno * regno))" + | CClearTag " ((regno * regno))" + | CMOVX " ((regno * regno * regno * bool))" + | ClearRegs " ((ClearRegSet * 16 bits))" + | CFromPtr " ((regno * regno * regno))" + | CBuildCap " ((regno * regno * regno))" + | CCopyType " ((regno * regno * regno))" + | CCheckPerm " ((regno * regno))" + | CCheckType " ((regno * regno))" + | CTestSubset " ((regno * regno * regno))" + | CSeal " ((regno * regno * regno))" + | CCSeal " ((regno * regno * regno))" + | CUnseal " ((regno * regno * regno))" + | CCall " ((regno * regno * 11 bits))" + | CReturn " (unit)" + | CBX " ((regno * 16 bits * bool))" + | CBZ " ((regno * 16 bits * bool))" + | CJALR " ((regno * regno * bool))" + | CLoad " ((regno * regno * regno * 8 bits * bool * WordType * bool))" + | CStore " ((regno * regno * regno * regno * 8 bits * WordType * bool))" + | CSC " ((regno * regno * regno * regno * 11 bits * bool))" + | CLC " ((regno * regno * regno * 11 bits * bool))" + | C2Dump " (regno)" + | RI " (unit)" + + + +datatype CapEx = + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_CapCauseReg " (CapCauseReg)" + | Regval_CauseReg " (CauseReg)" + | Regval_ContextReg " (ContextReg)" + | Regval_StatusReg " (StatusReg)" + | Regval_TLBEntry " (TLBEntry)" + | Regval_TLBEntryHiReg " (TLBEntryHiReg)" + | Regval_TLBEntryLoReg " (TLBEntryLoReg)" + | Regval_XContextReg " (XContextReg)" + | Regval_int " (ii)" + | Regval_vector_16_dec_bit " ( 16 Word.word)" + | Regval_vector_1_dec_bit " ( 1 Word.word)" + | Regval_vector_257_dec_bit " ( 257 Word.word)" + | Regval_vector_32_dec_bit " ( 32 Word.word)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + | Regval_vector_6_dec_bit " ( 6 Word.word)" + | Regval_vector_8_dec_bit " ( 8 Word.word)" + + + +record regstate = + + instCount ::" ii " + + CapCause ::" CapCauseReg " + + CTLSP ::" 257 Word.word " + + CTLSU ::" 257 Word.word " + + C31 ::" 257 Word.word " + + C30 ::" 257 Word.word " + + C29 ::" 257 Word.word " + + C28 ::" 257 Word.word " + + C27 ::" 257 Word.word " + + C26 ::" 257 Word.word " + + C25 ::" 257 Word.word " + + C24 ::" 257 Word.word " + + C23 ::" 257 Word.word " + + C22 ::" 257 Word.word " + + C21 ::" 257 Word.word " + + C20 ::" 257 Word.word " + + C19 ::" 257 Word.word " + + C18 ::" 257 Word.word " + + C17 ::" 257 Word.word " + + C16 ::" 257 Word.word " + + C15 ::" 257 Word.word " + + C14 ::" 257 Word.word " + + C13 ::" 257 Word.word " + + C12 ::" 257 Word.word " + + C11 ::" 257 Word.word " + + C10 ::" 257 Word.word " + + C09 ::" 257 Word.word " + + C08 ::" 257 Word.word " + + C07 ::" 257 Word.word " + + C06 ::" 257 Word.word " + + C05 ::" 257 Word.word " + + C04 ::" 257 Word.word " + + C03 ::" 257 Word.word " + + C02 ::" 257 Word.word " + + C01 ::" 257 Word.word " + + C00 ::" 257 Word.word " + + inCCallDelay ::" 1 Word.word " + + delayedPCC ::" 257 Word.word " + + nextPCC ::" 257 Word.word " + + PCC ::" 257 Word.word " + + UART_RVALID ::" 1 Word.word " + + UART_RDATA ::" 8 Word.word " + + UART_WRITTEN ::" 1 Word.word " + + UART_WDATA ::" 8 Word.word " + + GPR ::" ( 64 Word.word) list " + + LO ::" 64 Word.word " + + HI ::" 64 Word.word " + + delayedPC ::" 64 Word.word " + + inBranchDelay ::" 1 Word.word " + + branchPending ::" 1 Word.word " + + CP0Status ::" StatusReg " + + CP0UserLocal ::" 64 Word.word " + + CP0HWREna ::" 32 Word.word " + + CP0Count ::" 32 Word.word " + + CP0BadVAddr ::" 64 Word.word " + + CP0LLAddr ::" 64 Word.word " + + CP0LLBit ::" 1 Word.word " + + CP0ErrorEPC ::" 64 Word.word " + + CP0EPC ::" 64 Word.word " + + CP0Cause ::" CauseReg " + + CP0Compare ::" 32 Word.word " + + TLBEntry63 ::" TLBEntry " + + TLBEntry62 ::" TLBEntry " + + TLBEntry61 ::" TLBEntry " + + TLBEntry60 ::" TLBEntry " + + TLBEntry59 ::" TLBEntry " + + TLBEntry58 ::" TLBEntry " + + TLBEntry57 ::" TLBEntry " + + TLBEntry56 ::" TLBEntry " + + TLBEntry55 ::" TLBEntry " + + TLBEntry54 ::" TLBEntry " + + TLBEntry53 ::" TLBEntry " + + TLBEntry52 ::" TLBEntry " + + TLBEntry51 ::" TLBEntry " + + TLBEntry50 ::" TLBEntry " + + TLBEntry49 ::" TLBEntry " + + TLBEntry48 ::" TLBEntry " + + TLBEntry47 ::" TLBEntry " + + TLBEntry46 ::" TLBEntry " + + TLBEntry45 ::" TLBEntry " + + TLBEntry44 ::" TLBEntry " + + TLBEntry43 ::" TLBEntry " + + TLBEntry42 ::" TLBEntry " + + TLBEntry41 ::" TLBEntry " + + TLBEntry40 ::" TLBEntry " + + TLBEntry39 ::" TLBEntry " + + TLBEntry38 ::" TLBEntry " + + TLBEntry37 ::" TLBEntry " + + TLBEntry36 ::" TLBEntry " + + TLBEntry35 ::" TLBEntry " + + TLBEntry34 ::" TLBEntry " + + TLBEntry33 ::" TLBEntry " + + TLBEntry32 ::" TLBEntry " + + TLBEntry31 ::" TLBEntry " + + TLBEntry30 ::" TLBEntry " + + TLBEntry29 ::" TLBEntry " + + TLBEntry28 ::" TLBEntry " + + TLBEntry27 ::" TLBEntry " + + TLBEntry26 ::" TLBEntry " + + TLBEntry25 ::" TLBEntry " + + TLBEntry24 ::" TLBEntry " + + TLBEntry23 ::" TLBEntry " + + TLBEntry22 ::" TLBEntry " + + TLBEntry21 ::" TLBEntry " + + TLBEntry20 ::" TLBEntry " + + TLBEntry19 ::" TLBEntry " + + TLBEntry18 ::" TLBEntry " + + TLBEntry17 ::" TLBEntry " + + TLBEntry16 ::" TLBEntry " + + TLBEntry15 ::" TLBEntry " + + TLBEntry14 ::" TLBEntry " + + TLBEntry13 ::" TLBEntry " + + TLBEntry12 ::" TLBEntry " + + TLBEntry11 ::" TLBEntry " + + TLBEntry10 ::" TLBEntry " + + TLBEntry09 ::" TLBEntry " + + TLBEntry08 ::" TLBEntry " + + TLBEntry07 ::" TLBEntry " + + TLBEntry06 ::" TLBEntry " + + TLBEntry05 ::" TLBEntry " + + TLBEntry04 ::" TLBEntry " + + TLBEntry03 ::" TLBEntry " + + TLBEntry02 ::" TLBEntry " + + TLBEntry01 ::" TLBEntry " + + TLBEntry00 ::" TLBEntry " + + TLBXContext ::" XContextReg " + + TLBEntryHi ::" TLBEntryHiReg " + + TLBWired ::" 6 Word.word " + + TLBPageMask ::" 16 Word.word " + + TLBContext ::" ContextReg " + + TLBEntryLo1 ::" TLBEntryLoReg " + + TLBEntryLo0 ::" TLBEntryLoReg " + + TLBRandom ::" 6 Word.word " + + TLBIndex ::" 6 Word.word " + + TLBProbe ::" 1 Word.word " + + nextPC ::" 64 Word.word " + + PC ::" 64 Word.word " + + + + + +(*val CapCauseReg_of_regval : register_value -> maybe CapCauseReg*) + +fun CapCauseReg_of_regval :: " register_value \<Rightarrow>(CapCauseReg)option " where + " CapCauseReg_of_regval (Regval_CapCauseReg (v)) = ( Some v )" +|" CapCauseReg_of_regval g__114 = ( None )" + + +(*val regval_of_CapCauseReg : CapCauseReg -> register_value*) + +definition regval_of_CapCauseReg :: " CapCauseReg \<Rightarrow> register_value " where + " regval_of_CapCauseReg v = ( Regval_CapCauseReg v )" + + +(*val CauseReg_of_regval : register_value -> maybe CauseReg*) + +fun CauseReg_of_regval :: " register_value \<Rightarrow>(CauseReg)option " where + " CauseReg_of_regval (Regval_CauseReg (v)) = ( Some v )" +|" CauseReg_of_regval g__113 = ( None )" + + +(*val regval_of_CauseReg : CauseReg -> register_value*) + +definition regval_of_CauseReg :: " CauseReg \<Rightarrow> register_value " where + " regval_of_CauseReg v = ( Regval_CauseReg v )" + + +(*val ContextReg_of_regval : register_value -> maybe ContextReg*) + +fun ContextReg_of_regval :: " register_value \<Rightarrow>(ContextReg)option " where + " ContextReg_of_regval (Regval_ContextReg (v)) = ( Some v )" +|" ContextReg_of_regval g__112 = ( None )" + + +(*val regval_of_ContextReg : ContextReg -> register_value*) + +definition regval_of_ContextReg :: " ContextReg \<Rightarrow> register_value " where + " regval_of_ContextReg v = ( Regval_ContextReg v )" + + +(*val StatusReg_of_regval : register_value -> maybe StatusReg*) + +fun StatusReg_of_regval :: " register_value \<Rightarrow>(StatusReg)option " where + " StatusReg_of_regval (Regval_StatusReg (v)) = ( Some v )" +|" StatusReg_of_regval g__111 = ( None )" + + +(*val regval_of_StatusReg : StatusReg -> register_value*) + +definition regval_of_StatusReg :: " StatusReg \<Rightarrow> register_value " where + " regval_of_StatusReg v = ( Regval_StatusReg v )" + + +(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*) + +fun TLBEntry_of_regval :: " register_value \<Rightarrow>(TLBEntry)option " where + " TLBEntry_of_regval (Regval_TLBEntry (v)) = ( Some v )" +|" TLBEntry_of_regval g__110 = ( None )" + + +(*val regval_of_TLBEntry : TLBEntry -> register_value*) + +definition regval_of_TLBEntry :: " TLBEntry \<Rightarrow> register_value " where + " regval_of_TLBEntry v = ( Regval_TLBEntry v )" + + +(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*) + +fun TLBEntryHiReg_of_regval :: " register_value \<Rightarrow>(TLBEntryHiReg)option " where + " TLBEntryHiReg_of_regval (Regval_TLBEntryHiReg (v)) = ( Some v )" +|" TLBEntryHiReg_of_regval g__109 = ( None )" + + +(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) + +definition regval_of_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow> register_value " where + " regval_of_TLBEntryHiReg v = ( Regval_TLBEntryHiReg v )" + + +(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*) + +fun TLBEntryLoReg_of_regval :: " register_value \<Rightarrow>(TLBEntryLoReg)option " where + " TLBEntryLoReg_of_regval (Regval_TLBEntryLoReg (v)) = ( Some v )" +|" TLBEntryLoReg_of_regval g__108 = ( None )" + + +(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) + +definition regval_of_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow> register_value " where + " regval_of_TLBEntryLoReg v = ( Regval_TLBEntryLoReg v )" + + +(*val XContextReg_of_regval : register_value -> maybe XContextReg*) + +fun XContextReg_of_regval :: " register_value \<Rightarrow>(XContextReg)option " where + " XContextReg_of_regval (Regval_XContextReg (v)) = ( Some v )" +|" XContextReg_of_regval g__107 = ( None )" + + +(*val regval_of_XContextReg : XContextReg -> register_value*) + +definition regval_of_XContextReg :: " XContextReg \<Rightarrow> register_value " where + " regval_of_XContextReg v = ( Regval_XContextReg v )" + + +(*val int_of_regval : register_value -> maybe ii*) + +fun int_of_regval :: " register_value \<Rightarrow>(int)option " where + " int_of_regval (Regval_int (v)) = ( Some v )" +|" int_of_regval g__106 = ( None )" + + +(*val regval_of_int : ii -> register_value*) + +definition regval_of_int :: " int \<Rightarrow> register_value " where + " regval_of_int v = ( Regval_int v )" + + +(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*) + +fun vector_16_dec_bit_of_regval :: " register_value \<Rightarrow>((16)Word.word)option " where + " vector_16_dec_bit_of_regval (Regval_vector_16_dec_bit (v)) = ( Some v )" +|" vector_16_dec_bit_of_regval g__105 = ( None )" + + +(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) + +definition regval_of_vector_16_dec_bit :: "(16)Word.word \<Rightarrow> register_value " where + " regval_of_vector_16_dec_bit v = ( Regval_vector_16_dec_bit v )" + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +fun vector_1_dec_bit_of_regval :: " register_value \<Rightarrow>((1)Word.word)option " where + " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" +|" vector_1_dec_bit_of_regval g__104 = ( None )" + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +definition regval_of_vector_1_dec_bit :: "(1)Word.word \<Rightarrow> register_value " where + " regval_of_vector_1_dec_bit v = ( Regval_vector_1_dec_bit v )" + + +(*val vector_257_dec_bit_of_regval : register_value -> maybe (mword ty257)*) + +fun vector_257_dec_bit_of_regval :: " register_value \<Rightarrow>((257)Word.word)option " where + " vector_257_dec_bit_of_regval (Regval_vector_257_dec_bit (v)) = ( Some v )" +|" vector_257_dec_bit_of_regval g__103 = ( None )" + + +(*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) + +definition regval_of_vector_257_dec_bit :: "(257)Word.word \<Rightarrow> register_value " where + " regval_of_vector_257_dec_bit v = ( Regval_vector_257_dec_bit v )" + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where + " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" +|" vector_32_dec_bit_of_regval g__102 = ( None )" + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register_value " where + " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__101 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + +(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*) + +fun vector_6_dec_bit_of_regval :: " register_value \<Rightarrow>((6)Word.word)option " where + " vector_6_dec_bit_of_regval (Regval_vector_6_dec_bit (v)) = ( Some v )" +|" vector_6_dec_bit_of_regval g__100 = ( None )" + + +(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) + +definition regval_of_vector_6_dec_bit :: "(6)Word.word \<Rightarrow> register_value " where + " regval_of_vector_6_dec_bit v = ( Regval_vector_6_dec_bit v )" + + +(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*) + +fun vector_8_dec_bit_of_regval :: " register_value \<Rightarrow>((8)Word.word)option " where + " vector_8_dec_bit_of_regval (Regval_vector_8_dec_bit (v)) = ( Some v )" +|" vector_8_dec_bit_of_regval g__99 = ( None )" + + +(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) + +definition regval_of_vector_8_dec_bit :: "(8)Word.word \<Rightarrow> register_value " where + " regval_of_vector_8_dec_bit v = ( Regval_vector_8_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " vector_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " list_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where + " option_of_regval of_regval1 = ( \<lambda>x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition instCount_ref :: "((regstate),(register_value),(int))register_ref " where + " instCount_ref = ( (| + name = (''instCount''), + read_from = (\<lambda> s . (instCount s)), + write_to = (\<lambda> v s . (( s (| instCount := v |)))), + of_regval = (\<lambda> v . int_of_regval v), + regval_of = (\<lambda> v . regval_of_int v) |) )" + + +definition CapCause_ref :: "((regstate),(register_value),(CapCauseReg))register_ref " where + " CapCause_ref = ( (| + name = (''CapCause''), + read_from = (\<lambda> s . (CapCause s)), + write_to = (\<lambda> v s . (( s (| CapCause := v |)))), + of_regval = (\<lambda> v . CapCauseReg_of_regval v), + regval_of = (\<lambda> v . regval_of_CapCauseReg v) |) )" + + +definition CTLSP_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSP_ref = ( (| + name = (''CTLSP''), + read_from = (\<lambda> s . (CTLSP s)), + write_to = (\<lambda> v s . (( s (| CTLSP := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition CTLSU_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSU_ref = ( (| + name = (''CTLSU''), + read_from = (\<lambda> s . (CTLSU s)), + write_to = (\<lambda> v s . (( s (| CTLSU := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C30_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C30_ref = ( (| + name = (''C30''), + read_from = (\<lambda> s . (C30 s)), + write_to = (\<lambda> v s . (( s (| C30 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C28_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C28_ref = ( (| + name = (''C28''), + read_from = (\<lambda> s . (C28 s)), + write_to = (\<lambda> v s . (( s (| C28 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C27_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C27_ref = ( (| + name = (''C27''), + read_from = (\<lambda> s . (C27 s)), + write_to = (\<lambda> v s . (( s (| C27 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C26_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C26_ref = ( (| + name = (''C26''), + read_from = (\<lambda> s . (C26 s)), + write_to = (\<lambda> v s . (( s (| C26 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C25_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C25_ref = ( (| + name = (''C25''), + read_from = (\<lambda> s . (C25 s)), + write_to = (\<lambda> v s . (( s (| C25 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C24_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C24_ref = ( (| + name = (''C24''), + read_from = (\<lambda> s . (C24 s)), + write_to = (\<lambda> v s . (( s (| C24 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C23_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C23_ref = ( (| + name = (''C23''), + read_from = (\<lambda> s . (C23 s)), + write_to = (\<lambda> v s . (( s (| C23 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C22_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C22_ref = ( (| + name = (''C22''), + read_from = (\<lambda> s . (C22 s)), + write_to = (\<lambda> v s . (( s (| C22 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C21_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C21_ref = ( (| + name = (''C21''), + read_from = (\<lambda> s . (C21 s)), + write_to = (\<lambda> v s . (( s (| C21 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C20_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C20_ref = ( (| + name = (''C20''), + read_from = (\<lambda> s . (C20 s)), + write_to = (\<lambda> v s . (( s (| C20 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C19_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C19_ref = ( (| + name = (''C19''), + read_from = (\<lambda> s . (C19 s)), + write_to = (\<lambda> v s . (( s (| C19 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C18_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C18_ref = ( (| + name = (''C18''), + read_from = (\<lambda> s . (C18 s)), + write_to = (\<lambda> v s . (( s (| C18 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C17_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C17_ref = ( (| + name = (''C17''), + read_from = (\<lambda> s . (C17 s)), + write_to = (\<lambda> v s . (( s (| C17 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C16_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C16_ref = ( (| + name = (''C16''), + read_from = (\<lambda> s . (C16 s)), + write_to = (\<lambda> v s . (( s (| C16 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C15_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C15_ref = ( (| + name = (''C15''), + read_from = (\<lambda> s . (C15 s)), + write_to = (\<lambda> v s . (( s (| C15 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C14_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C14_ref = ( (| + name = (''C14''), + read_from = (\<lambda> s . (C14 s)), + write_to = (\<lambda> v s . (( s (| C14 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C13_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C13_ref = ( (| + name = (''C13''), + read_from = (\<lambda> s . (C13 s)), + write_to = (\<lambda> v s . (( s (| C13 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C12_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C12_ref = ( (| + name = (''C12''), + read_from = (\<lambda> s . (C12 s)), + write_to = (\<lambda> v s . (( s (| C12 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C11_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C11_ref = ( (| + name = (''C11''), + read_from = (\<lambda> s . (C11 s)), + write_to = (\<lambda> v s . (( s (| C11 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C10_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C10_ref = ( (| + name = (''C10''), + read_from = (\<lambda> s . (C10 s)), + write_to = (\<lambda> v s . (( s (| C10 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C09_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C09_ref = ( (| + name = (''C09''), + read_from = (\<lambda> s . (C09 s)), + write_to = (\<lambda> v s . (( s (| C09 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C08_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C08_ref = ( (| + name = (''C08''), + read_from = (\<lambda> s . (C08 s)), + write_to = (\<lambda> v s . (( s (| C08 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C07_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C07_ref = ( (| + name = (''C07''), + read_from = (\<lambda> s . (C07 s)), + write_to = (\<lambda> v s . (( s (| C07 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C06_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C06_ref = ( (| + name = (''C06''), + read_from = (\<lambda> s . (C06 s)), + write_to = (\<lambda> v s . (( s (| C06 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C05_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C05_ref = ( (| + name = (''C05''), + read_from = (\<lambda> s . (C05 s)), + write_to = (\<lambda> v s . (( s (| C05 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C04_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C04_ref = ( (| + name = (''C04''), + read_from = (\<lambda> s . (C04 s)), + write_to = (\<lambda> v s . (( s (| C04 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C03_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C03_ref = ( (| + name = (''C03''), + read_from = (\<lambda> s . (C03 s)), + write_to = (\<lambda> v s . (( s (| C03 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C02_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C02_ref = ( (| + name = (''C02''), + read_from = (\<lambda> s . (C02 s)), + write_to = (\<lambda> v s . (( s (| C02 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C01_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C01_ref = ( (| + name = (''C01''), + read_from = (\<lambda> s . (C01 s)), + write_to = (\<lambda> v s . (( s (| C01 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C00_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C00_ref = ( (| + name = (''C00''), + read_from = (\<lambda> s . (C00 s)), + write_to = (\<lambda> v s . (( s (| C00 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition inCCallDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inCCallDelay_ref = ( (| + name = (''inCCallDelay''), + read_from = (\<lambda> s . (inCCallDelay s)), + write_to = (\<lambda> v s . (( s (| inCCallDelay := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " nextPCC_ref = ( (| + name = (''nextPCC''), + read_from = (\<lambda> s . (nextPCC s)), + write_to = (\<lambda> v s . (( s (| nextPCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition delayedPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " delayedPCC_ref = ( (| + name = (''delayedPCC''), + read_from = (\<lambda> s . (delayedPCC s)), + write_to = (\<lambda> v s . (( s (| delayedPCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition PCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " PCC_ref = ( (| + name = (''PCC''), + read_from = (\<lambda> s . (PCC s)), + write_to = (\<lambda> v s . (( s (| PCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C31_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C31_ref = ( (| + name = (''C31''), + read_from = (\<lambda> s . (C31 s)), + write_to = (\<lambda> v s . (( s (| C31 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C29_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C29_ref = ( (| + name = (''C29''), + read_from = (\<lambda> s . (C29 s)), + write_to = (\<lambda> v s . (( s (| C29 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition UART_RVALID_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_RVALID_ref = ( (| + name = (''UART_RVALID''), + read_from = (\<lambda> s . (UART_RVALID s)), + write_to = (\<lambda> v s . (( s (| UART_RVALID := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_RDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_RDATA_ref = ( (| + name = (''UART_RDATA''), + read_from = (\<lambda> s . (UART_RDATA s)), + write_to = (\<lambda> v s . (( s (| UART_RDATA := v |)))), + of_regval = (\<lambda> v . vector_8_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_8_dec_bit v) |) )" + + +definition UART_WRITTEN_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_WRITTEN_ref = ( (| + name = (''UART_WRITTEN''), + read_from = (\<lambda> s . (UART_WRITTEN s)), + write_to = (\<lambda> v s . (( s (| UART_WRITTEN := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_WDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_WDATA_ref = ( (| + name = (''UART_WDATA''), + read_from = (\<lambda> s . (UART_WDATA s)), + write_to = (\<lambda> v s . (( s (| UART_WDATA := v |)))), + of_regval = (\<lambda> v . vector_8_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_8_dec_bit v) |) )" + + +definition GPR_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " GPR_ref = ( (| + name = (''GPR''), + read_from = (\<lambda> s . (GPR s)), + write_to = (\<lambda> v s . (( s (| GPR := v |)))), + of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v), + regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition LO_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " LO_ref = ( (| + name = (''LO''), + read_from = (\<lambda> s . (LO s)), + write_to = (\<lambda> v s . (( s (| LO := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition HI_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " HI_ref = ( (| + name = (''HI''), + read_from = (\<lambda> s . (HI s)), + write_to = (\<lambda> v s . (( s (| HI := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition delayedPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " delayedPC_ref = ( (| + name = (''delayedPC''), + read_from = (\<lambda> s . (delayedPC s)), + write_to = (\<lambda> v s . (( s (| delayedPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition inBranchDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inBranchDelay_ref = ( (| + name = (''inBranchDelay''), + read_from = (\<lambda> s . (inBranchDelay s)), + write_to = (\<lambda> v s . (( s (| inBranchDelay := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition branchPending_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " branchPending_ref = ( (| + name = (''branchPending''), + read_from = (\<lambda> s . (branchPending s)), + write_to = (\<lambda> v s . (( s (| branchPending := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0Status_ref :: "((regstate),(register_value),(StatusReg))register_ref " where + " CP0Status_ref = ( (| + name = (''CP0Status''), + read_from = (\<lambda> s . (CP0Status s)), + write_to = (\<lambda> v s . (( s (| CP0Status := v |)))), + of_regval = (\<lambda> v . StatusReg_of_regval v), + regval_of = (\<lambda> v . regval_of_StatusReg v) |) )" + + +definition CP0UserLocal_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0UserLocal_ref = ( (| + name = (''CP0UserLocal''), + read_from = (\<lambda> s . (CP0UserLocal s)), + write_to = (\<lambda> v s . (( s (| CP0UserLocal := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0HWREna_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0HWREna_ref = ( (| + name = (''CP0HWREna''), + read_from = (\<lambda> s . (CP0HWREna s)), + write_to = (\<lambda> v s . (( s (| CP0HWREna := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0Count_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Count_ref = ( (| + name = (''CP0Count''), + read_from = (\<lambda> s . (CP0Count s)), + write_to = (\<lambda> v s . (( s (| CP0Count := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0BadVAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0BadVAddr_ref = ( (| + name = (''CP0BadVAddr''), + read_from = (\<lambda> s . (CP0BadVAddr s)), + write_to = (\<lambda> v s . (( s (| CP0BadVAddr := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0LLAddr_ref = ( (| + name = (''CP0LLAddr''), + read_from = (\<lambda> s . (CP0LLAddr s)), + write_to = (\<lambda> v s . (( s (| CP0LLAddr := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLBit_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " CP0LLBit_ref = ( (| + name = (''CP0LLBit''), + read_from = (\<lambda> s . (CP0LLBit s)), + write_to = (\<lambda> v s . (( s (| CP0LLBit := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0ErrorEPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0ErrorEPC_ref = ( (| + name = (''CP0ErrorEPC''), + read_from = (\<lambda> s . (CP0ErrorEPC s)), + write_to = (\<lambda> v s . (( s (| CP0ErrorEPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0EPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0EPC_ref = ( (| + name = (''CP0EPC''), + read_from = (\<lambda> s . (CP0EPC s)), + write_to = (\<lambda> v s . (( s (| CP0EPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0Cause_ref :: "((regstate),(register_value),(CauseReg))register_ref " where + " CP0Cause_ref = ( (| + name = (''CP0Cause''), + read_from = (\<lambda> s . (CP0Cause s)), + write_to = (\<lambda> v s . (( s (| CP0Cause := v |)))), + of_regval = (\<lambda> v . CauseReg_of_regval v), + regval_of = (\<lambda> v . regval_of_CauseReg v) |) )" + + +definition CP0Compare_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Compare_ref = ( (| + name = (''CP0Compare''), + read_from = (\<lambda> s . (CP0Compare s)), + write_to = (\<lambda> v s . (( s (| CP0Compare := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition TLBEntry63_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry63_ref = ( (| + name = (''TLBEntry63''), + read_from = (\<lambda> s . (TLBEntry63 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry63 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry62_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry62_ref = ( (| + name = (''TLBEntry62''), + read_from = (\<lambda> s . (TLBEntry62 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry62 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry61_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry61_ref = ( (| + name = (''TLBEntry61''), + read_from = (\<lambda> s . (TLBEntry61 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry61 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry60_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry60_ref = ( (| + name = (''TLBEntry60''), + read_from = (\<lambda> s . (TLBEntry60 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry60 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry59_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry59_ref = ( (| + name = (''TLBEntry59''), + read_from = (\<lambda> s . (TLBEntry59 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry59 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry58_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry58_ref = ( (| + name = (''TLBEntry58''), + read_from = (\<lambda> s . (TLBEntry58 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry58 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry57_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry57_ref = ( (| + name = (''TLBEntry57''), + read_from = (\<lambda> s . (TLBEntry57 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry57 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry56_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry56_ref = ( (| + name = (''TLBEntry56''), + read_from = (\<lambda> s . (TLBEntry56 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry56 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry55_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry55_ref = ( (| + name = (''TLBEntry55''), + read_from = (\<lambda> s . (TLBEntry55 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry55 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry54_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry54_ref = ( (| + name = (''TLBEntry54''), + read_from = (\<lambda> s . (TLBEntry54 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry54 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry53_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry53_ref = ( (| + name = (''TLBEntry53''), + read_from = (\<lambda> s . (TLBEntry53 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry53 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry52_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry52_ref = ( (| + name = (''TLBEntry52''), + read_from = (\<lambda> s . (TLBEntry52 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry52 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry51_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry51_ref = ( (| + name = (''TLBEntry51''), + read_from = (\<lambda> s . (TLBEntry51 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry51 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry50_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry50_ref = ( (| + name = (''TLBEntry50''), + read_from = (\<lambda> s . (TLBEntry50 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry50 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry49_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry49_ref = ( (| + name = (''TLBEntry49''), + read_from = (\<lambda> s . (TLBEntry49 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry49 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry48_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry48_ref = ( (| + name = (''TLBEntry48''), + read_from = (\<lambda> s . (TLBEntry48 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry48 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry47_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry47_ref = ( (| + name = (''TLBEntry47''), + read_from = (\<lambda> s . (TLBEntry47 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry47 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry46_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry46_ref = ( (| + name = (''TLBEntry46''), + read_from = (\<lambda> s . (TLBEntry46 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry46 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry45_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry45_ref = ( (| + name = (''TLBEntry45''), + read_from = (\<lambda> s . (TLBEntry45 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry45 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry44_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry44_ref = ( (| + name = (''TLBEntry44''), + read_from = (\<lambda> s . (TLBEntry44 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry44 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry43_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry43_ref = ( (| + name = (''TLBEntry43''), + read_from = (\<lambda> s . (TLBEntry43 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry43 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry42_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry42_ref = ( (| + name = (''TLBEntry42''), + read_from = (\<lambda> s . (TLBEntry42 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry42 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry41_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry41_ref = ( (| + name = (''TLBEntry41''), + read_from = (\<lambda> s . (TLBEntry41 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry41 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry40_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry40_ref = ( (| + name = (''TLBEntry40''), + read_from = (\<lambda> s . (TLBEntry40 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry40 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry39_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry39_ref = ( (| + name = (''TLBEntry39''), + read_from = (\<lambda> s . (TLBEntry39 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry39 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry38_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry38_ref = ( (| + name = (''TLBEntry38''), + read_from = (\<lambda> s . (TLBEntry38 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry38 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry37_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry37_ref = ( (| + name = (''TLBEntry37''), + read_from = (\<lambda> s . (TLBEntry37 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry37 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry36_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry36_ref = ( (| + name = (''TLBEntry36''), + read_from = (\<lambda> s . (TLBEntry36 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry36 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry35_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry35_ref = ( (| + name = (''TLBEntry35''), + read_from = (\<lambda> s . (TLBEntry35 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry35 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry34_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry34_ref = ( (| + name = (''TLBEntry34''), + read_from = (\<lambda> s . (TLBEntry34 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry34 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry33_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry33_ref = ( (| + name = (''TLBEntry33''), + read_from = (\<lambda> s . (TLBEntry33 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry33 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry32_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry32_ref = ( (| + name = (''TLBEntry32''), + read_from = (\<lambda> s . (TLBEntry32 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry32 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry31_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry31_ref = ( (| + name = (''TLBEntry31''), + read_from = (\<lambda> s . (TLBEntry31 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry31 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry30_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry30_ref = ( (| + name = (''TLBEntry30''), + read_from = (\<lambda> s . (TLBEntry30 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry30 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry29_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry29_ref = ( (| + name = (''TLBEntry29''), + read_from = (\<lambda> s . (TLBEntry29 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry29 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry28_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry28_ref = ( (| + name = (''TLBEntry28''), + read_from = (\<lambda> s . (TLBEntry28 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry28 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry27_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry27_ref = ( (| + name = (''TLBEntry27''), + read_from = (\<lambda> s . (TLBEntry27 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry27 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry26_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry26_ref = ( (| + name = (''TLBEntry26''), + read_from = (\<lambda> s . (TLBEntry26 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry26 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry25_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry25_ref = ( (| + name = (''TLBEntry25''), + read_from = (\<lambda> s . (TLBEntry25 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry25 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry24_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry24_ref = ( (| + name = (''TLBEntry24''), + read_from = (\<lambda> s . (TLBEntry24 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry24 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry23_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry23_ref = ( (| + name = (''TLBEntry23''), + read_from = (\<lambda> s . (TLBEntry23 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry23 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry22_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry22_ref = ( (| + name = (''TLBEntry22''), + read_from = (\<lambda> s . (TLBEntry22 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry22 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry21_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry21_ref = ( (| + name = (''TLBEntry21''), + read_from = (\<lambda> s . (TLBEntry21 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry21 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry20_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry20_ref = ( (| + name = (''TLBEntry20''), + read_from = (\<lambda> s . (TLBEntry20 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry20 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry19_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry19_ref = ( (| + name = (''TLBEntry19''), + read_from = (\<lambda> s . (TLBEntry19 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry19 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry18_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry18_ref = ( (| + name = (''TLBEntry18''), + read_from = (\<lambda> s . (TLBEntry18 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry18 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry17_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry17_ref = ( (| + name = (''TLBEntry17''), + read_from = (\<lambda> s . (TLBEntry17 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry17 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry16_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry16_ref = ( (| + name = (''TLBEntry16''), + read_from = (\<lambda> s . (TLBEntry16 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry16 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry15_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry15_ref = ( (| + name = (''TLBEntry15''), + read_from = (\<lambda> s . (TLBEntry15 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry15 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry14_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry14_ref = ( (| + name = (''TLBEntry14''), + read_from = (\<lambda> s . (TLBEntry14 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry14 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry13_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry13_ref = ( (| + name = (''TLBEntry13''), + read_from = (\<lambda> s . (TLBEntry13 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry13 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry12_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry12_ref = ( (| + name = (''TLBEntry12''), + read_from = (\<lambda> s . (TLBEntry12 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry12 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry11_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry11_ref = ( (| + name = (''TLBEntry11''), + read_from = (\<lambda> s . (TLBEntry11 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry11 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry10_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry10_ref = ( (| + name = (''TLBEntry10''), + read_from = (\<lambda> s . (TLBEntry10 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry10 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry09_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry09_ref = ( (| + name = (''TLBEntry09''), + read_from = (\<lambda> s . (TLBEntry09 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry09 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry08_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry08_ref = ( (| + name = (''TLBEntry08''), + read_from = (\<lambda> s . (TLBEntry08 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry08 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry07_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry07_ref = ( (| + name = (''TLBEntry07''), + read_from = (\<lambda> s . (TLBEntry07 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry07 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry06_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry06_ref = ( (| + name = (''TLBEntry06''), + read_from = (\<lambda> s . (TLBEntry06 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry06 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry05_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry05_ref = ( (| + name = (''TLBEntry05''), + read_from = (\<lambda> s . (TLBEntry05 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry05 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry04_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry04_ref = ( (| + name = (''TLBEntry04''), + read_from = (\<lambda> s . (TLBEntry04 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry04 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry03_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry03_ref = ( (| + name = (''TLBEntry03''), + read_from = (\<lambda> s . (TLBEntry03 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry03 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry02_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry02_ref = ( (| + name = (''TLBEntry02''), + read_from = (\<lambda> s . (TLBEntry02 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry02 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry01_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry01_ref = ( (| + name = (''TLBEntry01''), + read_from = (\<lambda> s . (TLBEntry01 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry01 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry00_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry00_ref = ( (| + name = (''TLBEntry00''), + read_from = (\<lambda> s . (TLBEntry00 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry00 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBXContext_ref :: "((regstate),(register_value),(XContextReg))register_ref " where + " TLBXContext_ref = ( (| + name = (''TLBXContext''), + read_from = (\<lambda> s . (TLBXContext s)), + write_to = (\<lambda> v s . (( s (| TLBXContext := v |)))), + of_regval = (\<lambda> v . XContextReg_of_regval v), + regval_of = (\<lambda> v . regval_of_XContextReg v) |) )" + + +definition TLBEntryHi_ref :: "((regstate),(register_value),(TLBEntryHiReg))register_ref " where + " TLBEntryHi_ref = ( (| + name = (''TLBEntryHi''), + read_from = (\<lambda> s . (TLBEntryHi s)), + write_to = (\<lambda> v s . (( s (| TLBEntryHi := v |)))), + of_regval = (\<lambda> v . TLBEntryHiReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryHiReg v) |) )" + + +definition TLBWired_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBWired_ref = ( (| + name = (''TLBWired''), + read_from = (\<lambda> s . (TLBWired s)), + write_to = (\<lambda> v s . (( s (| TLBWired := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBPageMask_ref :: "((regstate),(register_value),((16)Word.word))register_ref " where + " TLBPageMask_ref = ( (| + name = (''TLBPageMask''), + read_from = (\<lambda> s . (TLBPageMask s)), + write_to = (\<lambda> v s . (( s (| TLBPageMask := v |)))), + of_regval = (\<lambda> v . vector_16_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_16_dec_bit v) |) )" + + +definition TLBContext_ref :: "((regstate),(register_value),(ContextReg))register_ref " where + " TLBContext_ref = ( (| + name = (''TLBContext''), + read_from = (\<lambda> s . (TLBContext s)), + write_to = (\<lambda> v s . (( s (| TLBContext := v |)))), + of_regval = (\<lambda> v . ContextReg_of_regval v), + regval_of = (\<lambda> v . regval_of_ContextReg v) |) )" + + +definition TLBEntryLo1_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo1_ref = ( (| + name = (''TLBEntryLo1''), + read_from = (\<lambda> s . (TLBEntryLo1 s)), + write_to = (\<lambda> v s . (( s (| TLBEntryLo1 := v |)))), + of_regval = (\<lambda> v . TLBEntryLoReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBEntryLo0_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo0_ref = ( (| + name = (''TLBEntryLo0''), + read_from = (\<lambda> s . (TLBEntryLo0 s)), + write_to = (\<lambda> v s . (( s (| TLBEntryLo0 := v |)))), + of_regval = (\<lambda> v . TLBEntryLoReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBRandom_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBRandom_ref = ( (| + name = (''TLBRandom''), + read_from = (\<lambda> s . (TLBRandom s)), + write_to = (\<lambda> v s . (( s (| TLBRandom := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBIndex_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBIndex_ref = ( (| + name = (''TLBIndex''), + read_from = (\<lambda> s . (TLBIndex s)), + write_to = (\<lambda> v s . (( s (| TLBIndex := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBProbe_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " TLBProbe_ref = ( (| + name = (''TLBProbe''), + read_from = (\<lambda> s . (TLBProbe s)), + write_to = (\<lambda> v s . (( s (| TLBProbe := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\<lambda> s . (nextPC s)), + write_to = (\<lambda> v s . (( s (| nextPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\<lambda> s . (PC s)), + write_to = (\<lambda> v s . (( s (| PC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''instCount'') then Some ((regval_of instCount_ref) ((read_from instCount_ref) s)) else + if reg_name = (''CapCause'') then Some ((regval_of CapCause_ref) ((read_from CapCause_ref) s)) else + if reg_name = (''CTLSP'') then Some ((regval_of CTLSP_ref) ((read_from CTLSP_ref) s)) else + if reg_name = (''CTLSU'') then Some ((regval_of CTLSU_ref) ((read_from CTLSU_ref) s)) else + if reg_name = (''C30'') then Some ((regval_of C30_ref) ((read_from C30_ref) s)) else + if reg_name = (''C28'') then Some ((regval_of C28_ref) ((read_from C28_ref) s)) else + if reg_name = (''C27'') then Some ((regval_of C27_ref) ((read_from C27_ref) s)) else + if reg_name = (''C26'') then Some ((regval_of C26_ref) ((read_from C26_ref) s)) else + if reg_name = (''C25'') then Some ((regval_of C25_ref) ((read_from C25_ref) s)) else + if reg_name = (''C24'') then Some ((regval_of C24_ref) ((read_from C24_ref) s)) else + if reg_name = (''C23'') then Some ((regval_of C23_ref) ((read_from C23_ref) s)) else + if reg_name = (''C22'') then Some ((regval_of C22_ref) ((read_from C22_ref) s)) else + if reg_name = (''C21'') then Some ((regval_of C21_ref) ((read_from C21_ref) s)) else + if reg_name = (''C20'') then Some ((regval_of C20_ref) ((read_from C20_ref) s)) else + if reg_name = (''C19'') then Some ((regval_of C19_ref) ((read_from C19_ref) s)) else + if reg_name = (''C18'') then Some ((regval_of C18_ref) ((read_from C18_ref) s)) else + if reg_name = (''C17'') then Some ((regval_of C17_ref) ((read_from C17_ref) s)) else + if reg_name = (''C16'') then Some ((regval_of C16_ref) ((read_from C16_ref) s)) else + if reg_name = (''C15'') then Some ((regval_of C15_ref) ((read_from C15_ref) s)) else + if reg_name = (''C14'') then Some ((regval_of C14_ref) ((read_from C14_ref) s)) else + if reg_name = (''C13'') then Some ((regval_of C13_ref) ((read_from C13_ref) s)) else + if reg_name = (''C12'') then Some ((regval_of C12_ref) ((read_from C12_ref) s)) else + if reg_name = (''C11'') then Some ((regval_of C11_ref) ((read_from C11_ref) s)) else + if reg_name = (''C10'') then Some ((regval_of C10_ref) ((read_from C10_ref) s)) else + if reg_name = (''C09'') then Some ((regval_of C09_ref) ((read_from C09_ref) s)) else + if reg_name = (''C08'') then Some ((regval_of C08_ref) ((read_from C08_ref) s)) else + if reg_name = (''C07'') then Some ((regval_of C07_ref) ((read_from C07_ref) s)) else + if reg_name = (''C06'') then Some ((regval_of C06_ref) ((read_from C06_ref) s)) else + if reg_name = (''C05'') then Some ((regval_of C05_ref) ((read_from C05_ref) s)) else + if reg_name = (''C04'') then Some ((regval_of C04_ref) ((read_from C04_ref) s)) else + if reg_name = (''C03'') then Some ((regval_of C03_ref) ((read_from C03_ref) s)) else + if reg_name = (''C02'') then Some ((regval_of C02_ref) ((read_from C02_ref) s)) else + if reg_name = (''C01'') then Some ((regval_of C01_ref) ((read_from C01_ref) s)) else + if reg_name = (''C00'') then Some ((regval_of C00_ref) ((read_from C00_ref) s)) else + if reg_name = (''inCCallDelay'') then Some ((regval_of inCCallDelay_ref) ((read_from inCCallDelay_ref) s)) else + if reg_name = (''nextPCC'') then Some ((regval_of nextPCC_ref) ((read_from nextPCC_ref) s)) else + if reg_name = (''delayedPCC'') then Some ((regval_of delayedPCC_ref) ((read_from delayedPCC_ref) s)) else + if reg_name = (''PCC'') then Some ((regval_of PCC_ref) ((read_from PCC_ref) s)) else + if reg_name = (''C31'') then Some ((regval_of C31_ref) ((read_from C31_ref) s)) else + if reg_name = (''C29'') then Some ((regval_of C29_ref) ((read_from C29_ref) s)) else + if reg_name = (''UART_RVALID'') then Some ((regval_of UART_RVALID_ref) ((read_from UART_RVALID_ref) s)) else + if reg_name = (''UART_RDATA'') then Some ((regval_of UART_RDATA_ref) ((read_from UART_RDATA_ref) s)) else + if reg_name = (''UART_WRITTEN'') then Some ((regval_of UART_WRITTEN_ref) ((read_from UART_WRITTEN_ref) s)) else + if reg_name = (''UART_WDATA'') then Some ((regval_of UART_WDATA_ref) ((read_from UART_WDATA_ref) s)) else + if reg_name = (''GPR'') then Some ((regval_of GPR_ref) ((read_from GPR_ref) s)) else + if reg_name = (''LO'') then Some ((regval_of LO_ref) ((read_from LO_ref) s)) else + if reg_name = (''HI'') then Some ((regval_of HI_ref) ((read_from HI_ref) s)) else + if reg_name = (''delayedPC'') then Some ((regval_of delayedPC_ref) ((read_from delayedPC_ref) s)) else + if reg_name = (''inBranchDelay'') then Some ((regval_of inBranchDelay_ref) ((read_from inBranchDelay_ref) s)) else + if reg_name = (''branchPending'') then Some ((regval_of branchPending_ref) ((read_from branchPending_ref) s)) else + if reg_name = (''CP0Status'') then Some ((regval_of CP0Status_ref) ((read_from CP0Status_ref) s)) else + if reg_name = (''CP0UserLocal'') then Some ((regval_of CP0UserLocal_ref) ((read_from CP0UserLocal_ref) s)) else + if reg_name = (''CP0HWREna'') then Some ((regval_of CP0HWREna_ref) ((read_from CP0HWREna_ref) s)) else + if reg_name = (''CP0Count'') then Some ((regval_of CP0Count_ref) ((read_from CP0Count_ref) s)) else + if reg_name = (''CP0BadVAddr'') then Some ((regval_of CP0BadVAddr_ref) ((read_from CP0BadVAddr_ref) s)) else + if reg_name = (''CP0LLAddr'') then Some ((regval_of CP0LLAddr_ref) ((read_from CP0LLAddr_ref) s)) else + if reg_name = (''CP0LLBit'') then Some ((regval_of CP0LLBit_ref) ((read_from CP0LLBit_ref) s)) else + if reg_name = (''CP0ErrorEPC'') then Some ((regval_of CP0ErrorEPC_ref) ((read_from CP0ErrorEPC_ref) s)) else + if reg_name = (''CP0EPC'') then Some ((regval_of CP0EPC_ref) ((read_from CP0EPC_ref) s)) else + if reg_name = (''CP0Cause'') then Some ((regval_of CP0Cause_ref) ((read_from CP0Cause_ref) s)) else + if reg_name = (''CP0Compare'') then Some ((regval_of CP0Compare_ref) ((read_from CP0Compare_ref) s)) else + if reg_name = (''TLBEntry63'') then Some ((regval_of TLBEntry63_ref) ((read_from TLBEntry63_ref) s)) else + if reg_name = (''TLBEntry62'') then Some ((regval_of TLBEntry62_ref) ((read_from TLBEntry62_ref) s)) else + if reg_name = (''TLBEntry61'') then Some ((regval_of TLBEntry61_ref) ((read_from TLBEntry61_ref) s)) else + if reg_name = (''TLBEntry60'') then Some ((regval_of TLBEntry60_ref) ((read_from TLBEntry60_ref) s)) else + if reg_name = (''TLBEntry59'') then Some ((regval_of TLBEntry59_ref) ((read_from TLBEntry59_ref) s)) else + if reg_name = (''TLBEntry58'') then Some ((regval_of TLBEntry58_ref) ((read_from TLBEntry58_ref) s)) else + if reg_name = (''TLBEntry57'') then Some ((regval_of TLBEntry57_ref) ((read_from TLBEntry57_ref) s)) else + if reg_name = (''TLBEntry56'') then Some ((regval_of TLBEntry56_ref) ((read_from TLBEntry56_ref) s)) else + if reg_name = (''TLBEntry55'') then Some ((regval_of TLBEntry55_ref) ((read_from TLBEntry55_ref) s)) else + if reg_name = (''TLBEntry54'') then Some ((regval_of TLBEntry54_ref) ((read_from TLBEntry54_ref) s)) else + if reg_name = (''TLBEntry53'') then Some ((regval_of TLBEntry53_ref) ((read_from TLBEntry53_ref) s)) else + if reg_name = (''TLBEntry52'') then Some ((regval_of TLBEntry52_ref) ((read_from TLBEntry52_ref) s)) else + if reg_name = (''TLBEntry51'') then Some ((regval_of TLBEntry51_ref) ((read_from TLBEntry51_ref) s)) else + if reg_name = (''TLBEntry50'') then Some ((regval_of TLBEntry50_ref) ((read_from TLBEntry50_ref) s)) else + if reg_name = (''TLBEntry49'') then Some ((regval_of TLBEntry49_ref) ((read_from TLBEntry49_ref) s)) else + if reg_name = (''TLBEntry48'') then Some ((regval_of TLBEntry48_ref) ((read_from TLBEntry48_ref) s)) else + if reg_name = (''TLBEntry47'') then Some ((regval_of TLBEntry47_ref) ((read_from TLBEntry47_ref) s)) else + if reg_name = (''TLBEntry46'') then Some ((regval_of TLBEntry46_ref) ((read_from TLBEntry46_ref) s)) else + if reg_name = (''TLBEntry45'') then Some ((regval_of TLBEntry45_ref) ((read_from TLBEntry45_ref) s)) else + if reg_name = (''TLBEntry44'') then Some ((regval_of TLBEntry44_ref) ((read_from TLBEntry44_ref) s)) else + if reg_name = (''TLBEntry43'') then Some ((regval_of TLBEntry43_ref) ((read_from TLBEntry43_ref) s)) else + if reg_name = (''TLBEntry42'') then Some ((regval_of TLBEntry42_ref) ((read_from TLBEntry42_ref) s)) else + if reg_name = (''TLBEntry41'') then Some ((regval_of TLBEntry41_ref) ((read_from TLBEntry41_ref) s)) else + if reg_name = (''TLBEntry40'') then Some ((regval_of TLBEntry40_ref) ((read_from TLBEntry40_ref) s)) else + if reg_name = (''TLBEntry39'') then Some ((regval_of TLBEntry39_ref) ((read_from TLBEntry39_ref) s)) else + if reg_name = (''TLBEntry38'') then Some ((regval_of TLBEntry38_ref) ((read_from TLBEntry38_ref) s)) else + if reg_name = (''TLBEntry37'') then Some ((regval_of TLBEntry37_ref) ((read_from TLBEntry37_ref) s)) else + if reg_name = (''TLBEntry36'') then Some ((regval_of TLBEntry36_ref) ((read_from TLBEntry36_ref) s)) else + if reg_name = (''TLBEntry35'') then Some ((regval_of TLBEntry35_ref) ((read_from TLBEntry35_ref) s)) else + if reg_name = (''TLBEntry34'') then Some ((regval_of TLBEntry34_ref) ((read_from TLBEntry34_ref) s)) else + if reg_name = (''TLBEntry33'') then Some ((regval_of TLBEntry33_ref) ((read_from TLBEntry33_ref) s)) else + if reg_name = (''TLBEntry32'') then Some ((regval_of TLBEntry32_ref) ((read_from TLBEntry32_ref) s)) else + if reg_name = (''TLBEntry31'') then Some ((regval_of TLBEntry31_ref) ((read_from TLBEntry31_ref) s)) else + if reg_name = (''TLBEntry30'') then Some ((regval_of TLBEntry30_ref) ((read_from TLBEntry30_ref) s)) else + if reg_name = (''TLBEntry29'') then Some ((regval_of TLBEntry29_ref) ((read_from TLBEntry29_ref) s)) else + if reg_name = (''TLBEntry28'') then Some ((regval_of TLBEntry28_ref) ((read_from TLBEntry28_ref) s)) else + if reg_name = (''TLBEntry27'') then Some ((regval_of TLBEntry27_ref) ((read_from TLBEntry27_ref) s)) else + if reg_name = (''TLBEntry26'') then Some ((regval_of TLBEntry26_ref) ((read_from TLBEntry26_ref) s)) else + if reg_name = (''TLBEntry25'') then Some ((regval_of TLBEntry25_ref) ((read_from TLBEntry25_ref) s)) else + if reg_name = (''TLBEntry24'') then Some ((regval_of TLBEntry24_ref) ((read_from TLBEntry24_ref) s)) else + if reg_name = (''TLBEntry23'') then Some ((regval_of TLBEntry23_ref) ((read_from TLBEntry23_ref) s)) else + if reg_name = (''TLBEntry22'') then Some ((regval_of TLBEntry22_ref) ((read_from TLBEntry22_ref) s)) else + if reg_name = (''TLBEntry21'') then Some ((regval_of TLBEntry21_ref) ((read_from TLBEntry21_ref) s)) else + if reg_name = (''TLBEntry20'') then Some ((regval_of TLBEntry20_ref) ((read_from TLBEntry20_ref) s)) else + if reg_name = (''TLBEntry19'') then Some ((regval_of TLBEntry19_ref) ((read_from TLBEntry19_ref) s)) else + if reg_name = (''TLBEntry18'') then Some ((regval_of TLBEntry18_ref) ((read_from TLBEntry18_ref) s)) else + if reg_name = (''TLBEntry17'') then Some ((regval_of TLBEntry17_ref) ((read_from TLBEntry17_ref) s)) else + if reg_name = (''TLBEntry16'') then Some ((regval_of TLBEntry16_ref) ((read_from TLBEntry16_ref) s)) else + if reg_name = (''TLBEntry15'') then Some ((regval_of TLBEntry15_ref) ((read_from TLBEntry15_ref) s)) else + if reg_name = (''TLBEntry14'') then Some ((regval_of TLBEntry14_ref) ((read_from TLBEntry14_ref) s)) else + if reg_name = (''TLBEntry13'') then Some ((regval_of TLBEntry13_ref) ((read_from TLBEntry13_ref) s)) else + if reg_name = (''TLBEntry12'') then Some ((regval_of TLBEntry12_ref) ((read_from TLBEntry12_ref) s)) else + if reg_name = (''TLBEntry11'') then Some ((regval_of TLBEntry11_ref) ((read_from TLBEntry11_ref) s)) else + if reg_name = (''TLBEntry10'') then Some ((regval_of TLBEntry10_ref) ((read_from TLBEntry10_ref) s)) else + if reg_name = (''TLBEntry09'') then Some ((regval_of TLBEntry09_ref) ((read_from TLBEntry09_ref) s)) else + if reg_name = (''TLBEntry08'') then Some ((regval_of TLBEntry08_ref) ((read_from TLBEntry08_ref) s)) else + if reg_name = (''TLBEntry07'') then Some ((regval_of TLBEntry07_ref) ((read_from TLBEntry07_ref) s)) else + if reg_name = (''TLBEntry06'') then Some ((regval_of TLBEntry06_ref) ((read_from TLBEntry06_ref) s)) else + if reg_name = (''TLBEntry05'') then Some ((regval_of TLBEntry05_ref) ((read_from TLBEntry05_ref) s)) else + if reg_name = (''TLBEntry04'') then Some ((regval_of TLBEntry04_ref) ((read_from TLBEntry04_ref) s)) else + if reg_name = (''TLBEntry03'') then Some ((regval_of TLBEntry03_ref) ((read_from TLBEntry03_ref) s)) else + if reg_name = (''TLBEntry02'') then Some ((regval_of TLBEntry02_ref) ((read_from TLBEntry02_ref) s)) else + if reg_name = (''TLBEntry01'') then Some ((regval_of TLBEntry01_ref) ((read_from TLBEntry01_ref) s)) else + if reg_name = (''TLBEntry00'') then Some ((regval_of TLBEntry00_ref) ((read_from TLBEntry00_ref) s)) else + if reg_name = (''TLBXContext'') then Some ((regval_of TLBXContext_ref) ((read_from TLBXContext_ref) s)) else + if reg_name = (''TLBEntryHi'') then Some ((regval_of TLBEntryHi_ref) ((read_from TLBEntryHi_ref) s)) else + if reg_name = (''TLBWired'') then Some ((regval_of TLBWired_ref) ((read_from TLBWired_ref) s)) else + if reg_name = (''TLBPageMask'') then Some ((regval_of TLBPageMask_ref) ((read_from TLBPageMask_ref) s)) else + if reg_name = (''TLBContext'') then Some ((regval_of TLBContext_ref) ((read_from TLBContext_ref) s)) else + if reg_name = (''TLBEntryLo1'') then Some ((regval_of TLBEntryLo1_ref) ((read_from TLBEntryLo1_ref) s)) else + if reg_name = (''TLBEntryLo0'') then Some ((regval_of TLBEntryLo0_ref) ((read_from TLBEntryLo0_ref) s)) else + if reg_name = (''TLBRandom'') then Some ((regval_of TLBRandom_ref) ((read_from TLBRandom_ref) s)) else + if reg_name = (''TLBIndex'') then Some ((regval_of TLBIndex_ref) ((read_from TLBIndex_ref) s)) else + if reg_name = (''TLBProbe'') then Some ((regval_of TLBProbe_ref) ((read_from TLBProbe_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''instCount'') then map_option (\<lambda> v . (write_to instCount_ref) v s) ((of_regval instCount_ref) v) else + if reg_name = (''CapCause'') then map_option (\<lambda> v . (write_to CapCause_ref) v s) ((of_regval CapCause_ref) v) else + if reg_name = (''CTLSP'') then map_option (\<lambda> v . (write_to CTLSP_ref) v s) ((of_regval CTLSP_ref) v) else + if reg_name = (''CTLSU'') then map_option (\<lambda> v . (write_to CTLSU_ref) v s) ((of_regval CTLSU_ref) v) else + if reg_name = (''C30'') then map_option (\<lambda> v . (write_to C30_ref) v s) ((of_regval C30_ref) v) else + if reg_name = (''C28'') then map_option (\<lambda> v . (write_to C28_ref) v s) ((of_regval C28_ref) v) else + if reg_name = (''C27'') then map_option (\<lambda> v . (write_to C27_ref) v s) ((of_regval C27_ref) v) else + if reg_name = (''C26'') then map_option (\<lambda> v . (write_to C26_ref) v s) ((of_regval C26_ref) v) else + if reg_name = (''C25'') then map_option (\<lambda> v . (write_to C25_ref) v s) ((of_regval C25_ref) v) else + if reg_name = (''C24'') then map_option (\<lambda> v . (write_to C24_ref) v s) ((of_regval C24_ref) v) else + if reg_name = (''C23'') then map_option (\<lambda> v . (write_to C23_ref) v s) ((of_regval C23_ref) v) else + if reg_name = (''C22'') then map_option (\<lambda> v . (write_to C22_ref) v s) ((of_regval C22_ref) v) else + if reg_name = (''C21'') then map_option (\<lambda> v . (write_to C21_ref) v s) ((of_regval C21_ref) v) else + if reg_name = (''C20'') then map_option (\<lambda> v . (write_to C20_ref) v s) ((of_regval C20_ref) v) else + if reg_name = (''C19'') then map_option (\<lambda> v . (write_to C19_ref) v s) ((of_regval C19_ref) v) else + if reg_name = (''C18'') then map_option (\<lambda> v . (write_to C18_ref) v s) ((of_regval C18_ref) v) else + if reg_name = (''C17'') then map_option (\<lambda> v . (write_to C17_ref) v s) ((of_regval C17_ref) v) else + if reg_name = (''C16'') then map_option (\<lambda> v . (write_to C16_ref) v s) ((of_regval C16_ref) v) else + if reg_name = (''C15'') then map_option (\<lambda> v . (write_to C15_ref) v s) ((of_regval C15_ref) v) else + if reg_name = (''C14'') then map_option (\<lambda> v . (write_to C14_ref) v s) ((of_regval C14_ref) v) else + if reg_name = (''C13'') then map_option (\<lambda> v . (write_to C13_ref) v s) ((of_regval C13_ref) v) else + if reg_name = (''C12'') then map_option (\<lambda> v . (write_to C12_ref) v s) ((of_regval C12_ref) v) else + if reg_name = (''C11'') then map_option (\<lambda> v . (write_to C11_ref) v s) ((of_regval C11_ref) v) else + if reg_name = (''C10'') then map_option (\<lambda> v . (write_to C10_ref) v s) ((of_regval C10_ref) v) else + if reg_name = (''C09'') then map_option (\<lambda> v . (write_to C09_ref) v s) ((of_regval C09_ref) v) else + if reg_name = (''C08'') then map_option (\<lambda> v . (write_to C08_ref) v s) ((of_regval C08_ref) v) else + if reg_name = (''C07'') then map_option (\<lambda> v . (write_to C07_ref) v s) ((of_regval C07_ref) v) else + if reg_name = (''C06'') then map_option (\<lambda> v . (write_to C06_ref) v s) ((of_regval C06_ref) v) else + if reg_name = (''C05'') then map_option (\<lambda> v . (write_to C05_ref) v s) ((of_regval C05_ref) v) else + if reg_name = (''C04'') then map_option (\<lambda> v . (write_to C04_ref) v s) ((of_regval C04_ref) v) else + if reg_name = (''C03'') then map_option (\<lambda> v . (write_to C03_ref) v s) ((of_regval C03_ref) v) else + if reg_name = (''C02'') then map_option (\<lambda> v . (write_to C02_ref) v s) ((of_regval C02_ref) v) else + if reg_name = (''C01'') then map_option (\<lambda> v . (write_to C01_ref) v s) ((of_regval C01_ref) v) else + if reg_name = (''C00'') then map_option (\<lambda> v . (write_to C00_ref) v s) ((of_regval C00_ref) v) else + if reg_name = (''inCCallDelay'') then map_option (\<lambda> v . (write_to inCCallDelay_ref) v s) ((of_regval inCCallDelay_ref) v) else + if reg_name = (''nextPCC'') then map_option (\<lambda> v . (write_to nextPCC_ref) v s) ((of_regval nextPCC_ref) v) else + if reg_name = (''delayedPCC'') then map_option (\<lambda> v . (write_to delayedPCC_ref) v s) ((of_regval delayedPCC_ref) v) else + if reg_name = (''PCC'') then map_option (\<lambda> v . (write_to PCC_ref) v s) ((of_regval PCC_ref) v) else + if reg_name = (''C31'') then map_option (\<lambda> v . (write_to C31_ref) v s) ((of_regval C31_ref) v) else + if reg_name = (''C29'') then map_option (\<lambda> v . (write_to C29_ref) v s) ((of_regval C29_ref) v) else + if reg_name = (''UART_RVALID'') then map_option (\<lambda> v . (write_to UART_RVALID_ref) v s) ((of_regval UART_RVALID_ref) v) else + if reg_name = (''UART_RDATA'') then map_option (\<lambda> v . (write_to UART_RDATA_ref) v s) ((of_regval UART_RDATA_ref) v) else + if reg_name = (''UART_WRITTEN'') then map_option (\<lambda> v . (write_to UART_WRITTEN_ref) v s) ((of_regval UART_WRITTEN_ref) v) else + if reg_name = (''UART_WDATA'') then map_option (\<lambda> v . (write_to UART_WDATA_ref) v s) ((of_regval UART_WDATA_ref) v) else + if reg_name = (''GPR'') then map_option (\<lambda> v . (write_to GPR_ref) v s) ((of_regval GPR_ref) v) else + if reg_name = (''LO'') then map_option (\<lambda> v . (write_to LO_ref) v s) ((of_regval LO_ref) v) else + if reg_name = (''HI'') then map_option (\<lambda> v . (write_to HI_ref) v s) ((of_regval HI_ref) v) else + if reg_name = (''delayedPC'') then map_option (\<lambda> v . (write_to delayedPC_ref) v s) ((of_regval delayedPC_ref) v) else + if reg_name = (''inBranchDelay'') then map_option (\<lambda> v . (write_to inBranchDelay_ref) v s) ((of_regval inBranchDelay_ref) v) else + if reg_name = (''branchPending'') then map_option (\<lambda> v . (write_to branchPending_ref) v s) ((of_regval branchPending_ref) v) else + if reg_name = (''CP0Status'') then map_option (\<lambda> v . (write_to CP0Status_ref) v s) ((of_regval CP0Status_ref) v) else + if reg_name = (''CP0UserLocal'') then map_option (\<lambda> v . (write_to CP0UserLocal_ref) v s) ((of_regval CP0UserLocal_ref) v) else + if reg_name = (''CP0HWREna'') then map_option (\<lambda> v . (write_to CP0HWREna_ref) v s) ((of_regval CP0HWREna_ref) v) else + if reg_name = (''CP0Count'') then map_option (\<lambda> v . (write_to CP0Count_ref) v s) ((of_regval CP0Count_ref) v) else + if reg_name = (''CP0BadVAddr'') then map_option (\<lambda> v . (write_to CP0BadVAddr_ref) v s) ((of_regval CP0BadVAddr_ref) v) else + if reg_name = (''CP0LLAddr'') then map_option (\<lambda> v . (write_to CP0LLAddr_ref) v s) ((of_regval CP0LLAddr_ref) v) else + if reg_name = (''CP0LLBit'') then map_option (\<lambda> v . (write_to CP0LLBit_ref) v s) ((of_regval CP0LLBit_ref) v) else + if reg_name = (''CP0ErrorEPC'') then map_option (\<lambda> v . (write_to CP0ErrorEPC_ref) v s) ((of_regval CP0ErrorEPC_ref) v) else + if reg_name = (''CP0EPC'') then map_option (\<lambda> v . (write_to CP0EPC_ref) v s) ((of_regval CP0EPC_ref) v) else + if reg_name = (''CP0Cause'') then map_option (\<lambda> v . (write_to CP0Cause_ref) v s) ((of_regval CP0Cause_ref) v) else + if reg_name = (''CP0Compare'') then map_option (\<lambda> v . (write_to CP0Compare_ref) v s) ((of_regval CP0Compare_ref) v) else + if reg_name = (''TLBEntry63'') then map_option (\<lambda> v . (write_to TLBEntry63_ref) v s) ((of_regval TLBEntry63_ref) v) else + if reg_name = (''TLBEntry62'') then map_option (\<lambda> v . (write_to TLBEntry62_ref) v s) ((of_regval TLBEntry62_ref) v) else + if reg_name = (''TLBEntry61'') then map_option (\<lambda> v . (write_to TLBEntry61_ref) v s) ((of_regval TLBEntry61_ref) v) else + if reg_name = (''TLBEntry60'') then map_option (\<lambda> v . (write_to TLBEntry60_ref) v s) ((of_regval TLBEntry60_ref) v) else + if reg_name = (''TLBEntry59'') then map_option (\<lambda> v . (write_to TLBEntry59_ref) v s) ((of_regval TLBEntry59_ref) v) else + if reg_name = (''TLBEntry58'') then map_option (\<lambda> v . (write_to TLBEntry58_ref) v s) ((of_regval TLBEntry58_ref) v) else + if reg_name = (''TLBEntry57'') then map_option (\<lambda> v . (write_to TLBEntry57_ref) v s) ((of_regval TLBEntry57_ref) v) else + if reg_name = (''TLBEntry56'') then map_option (\<lambda> v . (write_to TLBEntry56_ref) v s) ((of_regval TLBEntry56_ref) v) else + if reg_name = (''TLBEntry55'') then map_option (\<lambda> v . (write_to TLBEntry55_ref) v s) ((of_regval TLBEntry55_ref) v) else + if reg_name = (''TLBEntry54'') then map_option (\<lambda> v . (write_to TLBEntry54_ref) v s) ((of_regval TLBEntry54_ref) v) else + if reg_name = (''TLBEntry53'') then map_option (\<lambda> v . (write_to TLBEntry53_ref) v s) ((of_regval TLBEntry53_ref) v) else + if reg_name = (''TLBEntry52'') then map_option (\<lambda> v . (write_to TLBEntry52_ref) v s) ((of_regval TLBEntry52_ref) v) else + if reg_name = (''TLBEntry51'') then map_option (\<lambda> v . (write_to TLBEntry51_ref) v s) ((of_regval TLBEntry51_ref) v) else + if reg_name = (''TLBEntry50'') then map_option (\<lambda> v . (write_to TLBEntry50_ref) v s) ((of_regval TLBEntry50_ref) v) else + if reg_name = (''TLBEntry49'') then map_option (\<lambda> v . (write_to TLBEntry49_ref) v s) ((of_regval TLBEntry49_ref) v) else + if reg_name = (''TLBEntry48'') then map_option (\<lambda> v . (write_to TLBEntry48_ref) v s) ((of_regval TLBEntry48_ref) v) else + if reg_name = (''TLBEntry47'') then map_option (\<lambda> v . (write_to TLBEntry47_ref) v s) ((of_regval TLBEntry47_ref) v) else + if reg_name = (''TLBEntry46'') then map_option (\<lambda> v . (write_to TLBEntry46_ref) v s) ((of_regval TLBEntry46_ref) v) else + if reg_name = (''TLBEntry45'') then map_option (\<lambda> v . (write_to TLBEntry45_ref) v s) ((of_regval TLBEntry45_ref) v) else + if reg_name = (''TLBEntry44'') then map_option (\<lambda> v . (write_to TLBEntry44_ref) v s) ((of_regval TLBEntry44_ref) v) else + if reg_name = (''TLBEntry43'') then map_option (\<lambda> v . (write_to TLBEntry43_ref) v s) ((of_regval TLBEntry43_ref) v) else + if reg_name = (''TLBEntry42'') then map_option (\<lambda> v . (write_to TLBEntry42_ref) v s) ((of_regval TLBEntry42_ref) v) else + if reg_name = (''TLBEntry41'') then map_option (\<lambda> v . (write_to TLBEntry41_ref) v s) ((of_regval TLBEntry41_ref) v) else + if reg_name = (''TLBEntry40'') then map_option (\<lambda> v . (write_to TLBEntry40_ref) v s) ((of_regval TLBEntry40_ref) v) else + if reg_name = (''TLBEntry39'') then map_option (\<lambda> v . (write_to TLBEntry39_ref) v s) ((of_regval TLBEntry39_ref) v) else + if reg_name = (''TLBEntry38'') then map_option (\<lambda> v . (write_to TLBEntry38_ref) v s) ((of_regval TLBEntry38_ref) v) else + if reg_name = (''TLBEntry37'') then map_option (\<lambda> v . (write_to TLBEntry37_ref) v s) ((of_regval TLBEntry37_ref) v) else + if reg_name = (''TLBEntry36'') then map_option (\<lambda> v . (write_to TLBEntry36_ref) v s) ((of_regval TLBEntry36_ref) v) else + if reg_name = (''TLBEntry35'') then map_option (\<lambda> v . (write_to TLBEntry35_ref) v s) ((of_regval TLBEntry35_ref) v) else + if reg_name = (''TLBEntry34'') then map_option (\<lambda> v . (write_to TLBEntry34_ref) v s) ((of_regval TLBEntry34_ref) v) else + if reg_name = (''TLBEntry33'') then map_option (\<lambda> v . (write_to TLBEntry33_ref) v s) ((of_regval TLBEntry33_ref) v) else + if reg_name = (''TLBEntry32'') then map_option (\<lambda> v . (write_to TLBEntry32_ref) v s) ((of_regval TLBEntry32_ref) v) else + if reg_name = (''TLBEntry31'') then map_option (\<lambda> v . (write_to TLBEntry31_ref) v s) ((of_regval TLBEntry31_ref) v) else + if reg_name = (''TLBEntry30'') then map_option (\<lambda> v . (write_to TLBEntry30_ref) v s) ((of_regval TLBEntry30_ref) v) else + if reg_name = (''TLBEntry29'') then map_option (\<lambda> v . (write_to TLBEntry29_ref) v s) ((of_regval TLBEntry29_ref) v) else + if reg_name = (''TLBEntry28'') then map_option (\<lambda> v . (write_to TLBEntry28_ref) v s) ((of_regval TLBEntry28_ref) v) else + if reg_name = (''TLBEntry27'') then map_option (\<lambda> v . (write_to TLBEntry27_ref) v s) ((of_regval TLBEntry27_ref) v) else + if reg_name = (''TLBEntry26'') then map_option (\<lambda> v . (write_to TLBEntry26_ref) v s) ((of_regval TLBEntry26_ref) v) else + if reg_name = (''TLBEntry25'') then map_option (\<lambda> v . (write_to TLBEntry25_ref) v s) ((of_regval TLBEntry25_ref) v) else + if reg_name = (''TLBEntry24'') then map_option (\<lambda> v . (write_to TLBEntry24_ref) v s) ((of_regval TLBEntry24_ref) v) else + if reg_name = (''TLBEntry23'') then map_option (\<lambda> v . (write_to TLBEntry23_ref) v s) ((of_regval TLBEntry23_ref) v) else + if reg_name = (''TLBEntry22'') then map_option (\<lambda> v . (write_to TLBEntry22_ref) v s) ((of_regval TLBEntry22_ref) v) else + if reg_name = (''TLBEntry21'') then map_option (\<lambda> v . (write_to TLBEntry21_ref) v s) ((of_regval TLBEntry21_ref) v) else + if reg_name = (''TLBEntry20'') then map_option (\<lambda> v . (write_to TLBEntry20_ref) v s) ((of_regval TLBEntry20_ref) v) else + if reg_name = (''TLBEntry19'') then map_option (\<lambda> v . (write_to TLBEntry19_ref) v s) ((of_regval TLBEntry19_ref) v) else + if reg_name = (''TLBEntry18'') then map_option (\<lambda> v . (write_to TLBEntry18_ref) v s) ((of_regval TLBEntry18_ref) v) else + if reg_name = (''TLBEntry17'') then map_option (\<lambda> v . (write_to TLBEntry17_ref) v s) ((of_regval TLBEntry17_ref) v) else + if reg_name = (''TLBEntry16'') then map_option (\<lambda> v . (write_to TLBEntry16_ref) v s) ((of_regval TLBEntry16_ref) v) else + if reg_name = (''TLBEntry15'') then map_option (\<lambda> v . (write_to TLBEntry15_ref) v s) ((of_regval TLBEntry15_ref) v) else + if reg_name = (''TLBEntry14'') then map_option (\<lambda> v . (write_to TLBEntry14_ref) v s) ((of_regval TLBEntry14_ref) v) else + if reg_name = (''TLBEntry13'') then map_option (\<lambda> v . (write_to TLBEntry13_ref) v s) ((of_regval TLBEntry13_ref) v) else + if reg_name = (''TLBEntry12'') then map_option (\<lambda> v . (write_to TLBEntry12_ref) v s) ((of_regval TLBEntry12_ref) v) else + if reg_name = (''TLBEntry11'') then map_option (\<lambda> v . (write_to TLBEntry11_ref) v s) ((of_regval TLBEntry11_ref) v) else + if reg_name = (''TLBEntry10'') then map_option (\<lambda> v . (write_to TLBEntry10_ref) v s) ((of_regval TLBEntry10_ref) v) else + if reg_name = (''TLBEntry09'') then map_option (\<lambda> v . (write_to TLBEntry09_ref) v s) ((of_regval TLBEntry09_ref) v) else + if reg_name = (''TLBEntry08'') then map_option (\<lambda> v . (write_to TLBEntry08_ref) v s) ((of_regval TLBEntry08_ref) v) else + if reg_name = (''TLBEntry07'') then map_option (\<lambda> v . (write_to TLBEntry07_ref) v s) ((of_regval TLBEntry07_ref) v) else + if reg_name = (''TLBEntry06'') then map_option (\<lambda> v . (write_to TLBEntry06_ref) v s) ((of_regval TLBEntry06_ref) v) else + if reg_name = (''TLBEntry05'') then map_option (\<lambda> v . (write_to TLBEntry05_ref) v s) ((of_regval TLBEntry05_ref) v) else + if reg_name = (''TLBEntry04'') then map_option (\<lambda> v . (write_to TLBEntry04_ref) v s) ((of_regval TLBEntry04_ref) v) else + if reg_name = (''TLBEntry03'') then map_option (\<lambda> v . (write_to TLBEntry03_ref) v s) ((of_regval TLBEntry03_ref) v) else + if reg_name = (''TLBEntry02'') then map_option (\<lambda> v . (write_to TLBEntry02_ref) v s) ((of_regval TLBEntry02_ref) v) else + if reg_name = (''TLBEntry01'') then map_option (\<lambda> v . (write_to TLBEntry01_ref) v s) ((of_regval TLBEntry01_ref) v) else + if reg_name = (''TLBEntry00'') then map_option (\<lambda> v . (write_to TLBEntry00_ref) v s) ((of_regval TLBEntry00_ref) v) else + if reg_name = (''TLBXContext'') then map_option (\<lambda> v . (write_to TLBXContext_ref) v s) ((of_regval TLBXContext_ref) v) else + if reg_name = (''TLBEntryHi'') then map_option (\<lambda> v . (write_to TLBEntryHi_ref) v s) ((of_regval TLBEntryHi_ref) v) else + if reg_name = (''TLBWired'') then map_option (\<lambda> v . (write_to TLBWired_ref) v s) ((of_regval TLBWired_ref) v) else + if reg_name = (''TLBPageMask'') then map_option (\<lambda> v . (write_to TLBPageMask_ref) v s) ((of_regval TLBPageMask_ref) v) else + if reg_name = (''TLBContext'') then map_option (\<lambda> v . (write_to TLBContext_ref) v s) ((of_regval TLBContext_ref) v) else + if reg_name = (''TLBEntryLo1'') then map_option (\<lambda> v . (write_to TLBEntryLo1_ref) v s) ((of_regval TLBEntryLo1_ref) v) else + if reg_name = (''TLBEntryLo0'') then map_option (\<lambda> v . (write_to TLBEntryLo0_ref) v s) ((of_regval TLBEntryLo0_ref) v) else + if reg_name = (''TLBRandom'') then map_option (\<lambda> v . (write_to TLBRandom_ref) v s) ((of_regval TLBRandom_ref) v) else + if reg_name = (''TLBIndex'') then map_option (\<lambda> v . (write_to TLBIndex_ref) v s) ((of_regval TLBIndex_ref) v) else + if reg_name = (''TLBProbe'') then map_option (\<lambda> v . (write_to TLBProbe_ref) v s) ((of_regval TLBProbe_ref) v) else + if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end diff --git a/snapshots/isabelle/cheri/Mips_extras.thy b/snapshots/isabelle/cheri/Mips_extras.thy new file mode 100644 index 00000000..c0379d3a --- /dev/null +++ b/snapshots/isabelle/cheri/Mips_extras.thy @@ -0,0 +1,251 @@ +chapter \<open>Generated by Lem from /auto/homes/tb592/REMS/rems/sail/mips/mips_extras.lem.\<close> + +theory "Mips_extras" + +imports + Main + "Lem_pervasives" + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Prompt_monad" + "Prompt" + "Sail_operators" + +begin + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) + +definition MEMr :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where + " MEMr dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 )" + +definition MEMr_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where + " MEMr_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1 )" + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +definition read_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regval,(bool),'e)monad " where + " read_tag_bool dict_Sail_values_Bitvector_a addr = ( + read_tag dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + maybe_fail (''read_tag_bool'') (bool_of_bitU t)))" + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +definition write_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow>('regval,(unit),'e)monad " where + " write_tag_bool dict_Sail_values_Bitvector_a addr t = ( write_tag + dict_Sail_values_Bitvector_a addr (bitU_of_bool t) \<bind> + (\<lambda>x . (case x of _ => return () )) )" + + +definition MEMr_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where + " MEMr_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + return (t, v))))" + + +definition MEMr_tag_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where + " MEMr_tag_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + return (t, v))))" + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) + +definition MEMea :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + +definition MEMea_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_tag dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_tag_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) + +definition MEMval :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where + " MEMval dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of _ => return () )) )" + +definition MEMval_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where + " MEMval_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . return (if b then True else False)))" + +definition MEMval_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where + " MEMval_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of + _ => write_tag_bool dict_Sail_values_Bitvector_a addr t + \<bind> + (\<lambda>x . (case x of _ => return () )) + )) )" + +definition MEMval_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where + " MEMval_tag_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . write_tag_bool + dict_Sail_values_Bitvector_a addr t \<bind> (\<lambda>x . (case x of _ => return (if b then True else False) ))))" + + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +definition MEM_sync :: " unit \<Rightarrow>('regval,(unit),'e)monad " where + " MEM_sync _ = ( barrier Barrier_MIPS_SYNC )" + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +definition get_slice_int_bl :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bool)list " where + " get_slice_int_bl len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + subrange_list False bs hi lo)))" + + +(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +definition get_slice_int0 :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where + " get_slice_int0 dict_Sail_values_Bitvector_a len n lo = ( + (of_bools_method dict_Sail_values_Bitvector_a) (get_slice_int_bl len n lo))" + + +definition write_ram :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'b \<Rightarrow> 'a \<Rightarrow>('d,(unit),'c)monad " where + " write_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data = ( + MEMea dict_Sail_values_Bitvector_b addr size1 \<then> + MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data )" + + +definition read_ram :: " 'a Bitvector_class \<Rightarrow> 'c Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'a \<Rightarrow>('d,'c,'b)monad " where + " read_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr = ( MEMr + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1 )" + + +definition string_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where + " string_of_bits dict_Sail_values_Bitvector_a bs = ( string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ((bits_of_method dict_Sail_values_Bitvector_a) bs))" + +definition string_of_int :: " 'a Show_class \<Rightarrow> 'a \<Rightarrow> string " where + " string_of_int dict_Show_Show_a = ((show_method dict_Show_Show_a))" + + +definition sign_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where + " sign_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (exts_bv dict_Sail_values_Bitvector_a len bits)))" + +definition zero_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where + " zero_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (extz_bv dict_Sail_values_Bitvector_a len bits)))" + + +definition shift_bits_left :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_left dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_left'') r))" + +definition shift_bits_right :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_right dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right'') r))" + +definition shift_bits_right_arith :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_right_arith dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right_arith'') r))" + + +(* Use constants for undefined values for now *) +definition internal_pick :: " 'a list \<Rightarrow>('c,'a,'b)monad " where + " internal_pick vs = ( return (List.hd vs))" + +definition undefined_string :: " unit \<Rightarrow>('b,(string),'a)monad " where + " undefined_string _ = ( return (''''))" + +definition undefined_unit :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " undefined_unit _ = ( return () )" + +definition undefined_int :: " unit \<Rightarrow>('b,(int),'a)monad " where + " undefined_int _ = ( return (( 0 :: int)::ii))" + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +definition undefined_vector :: " int \<Rightarrow> 'a \<Rightarrow>('rv,('a list),'e)monad " where + " undefined_vector len u = ( return (repeat [u] len))" + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bitvector :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where + " undefined_bitvector dict_Sail_values_Bitvector_a len = ( return ( + (of_bools_method dict_Sail_values_Bitvector_a) (repeat [False] len)))" + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bits :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where + " undefined_bits dict_Sail_values_Bitvector_a = ( + undefined_bitvector dict_Sail_values_Bitvector_a )" + +definition undefined_bit :: " unit \<Rightarrow>('b,(bitU),'a)monad " where + " undefined_bit _ = ( return B0 )" + +definition undefined_real :: " unit \<Rightarrow>('b,(real),'a)monad " where + " undefined_real _ = ( return (realFromFrac(( 0 :: int))(( 1 :: int))))" + +definition undefined_range :: " 'a \<Rightarrow> 'd \<Rightarrow>('c,'a,'b)monad " where + " undefined_range i j = ( return i )" + +definition undefined_atom :: " 'a \<Rightarrow>('c,'a,'b)monad " where + " undefined_atom i = ( return i )" + +definition undefined_nat :: " unit \<Rightarrow>('b,(int),'a)monad " where + " undefined_nat _ = ( return (( 0 :: int)::ii))" + + +definition skip :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " skip _ = ( return () )" + + +(*val elf_entry : unit -> integer*) +definition elf_entry :: " unit \<Rightarrow> int " where + " elf_entry _ = (( 0 :: int))" + + +definition print_bits :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit " where + " print_bits dict_Sail_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bits + dict_Sail_values_Bitvector_a bs)))" + + +(*val get_time_ns : unit -> integer*) +definition get_time_ns :: " unit \<Rightarrow> int " where + " get_time_ns _ = (( 0 :: int))" + +end diff --git a/snapshots/isabelle/cheri/ROOT b/snapshots/isabelle/cheri/ROOT new file mode 100644 index 00000000..244413d5 --- /dev/null +++ b/snapshots/isabelle/cheri/ROOT @@ -0,0 +1,4 @@ +session "Sail-CHERI" = "Sail" + + options [document = false] + theories + Cheri_lemmas |