diff options
Diffstat (limited to 'snapshots/isabelle/cheri/Cheri.thy')
| -rw-r--r-- | snapshots/isabelle/cheri/Cheri.thy | 6536 |
1 files changed, 3285 insertions, 3251 deletions
diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy index eed49a23..af6852b6 100644 --- a/snapshots/isabelle/cheri/Cheri.thy +++ b/snapshots/isabelle/cheri/Cheri.thy @@ -5,12 +5,12 @@ theory "Cheri" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_string" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" "Cheri_types" "Mips_extras" @@ -18,12 +18,12 @@ begin (*Generated by Sail from cheri.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Cheri_types*) (*open import Mips_extras*) @@ -31,12 +31,6 @@ definition cap_size :: " int " where " cap_size = ( (( 32 :: int)::ii))" -(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) - -definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where - " undefined_option typ_a = ( undefined_unit () \<then> internal_pick [None,Some typ_a])" - - @@ -49,15 +43,39 @@ definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where " neq_bool x y = ( \<not> (((x = y))))" +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where + " undefined_option typ_a = ( + undefined_unit () \<bind> (\<lambda> (u_0 :: unit) . + (let (u_1 :: 'a) = typ_a in + internal_pick [Some u_1,None])))" + + +(*val is_none : forall 'a. maybe 'a -> bool*) + +fun is_none :: " 'a option \<Rightarrow> bool " where + " is_none (Some (_)) = ( False )" +|" is_none None = ( True )" + +(*val is_some : forall 'a. maybe 'a -> bool*) +fun is_some :: " 'a option \<Rightarrow> bool " where + " is_some (Some (_)) = ( True )" +|" is_some None = ( False )" -(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) +(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*) + +definition sail_mask :: "('len::len)itself \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word " where + " sail_mask len v = ( + (let len = (size_itself_int len) in + if ((len \<le> ((int (size v))))) then (vector_truncate v len :: ( 'len::len)Word.word) + else (zero_extend v len :: ( 'len::len)Word.word)))" -(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) @@ -65,29 +83,25 @@ definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" -|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" - +|" cast_unit_vec0 _ = ( (vec_of_bits [B1] :: 1 Word.word))" -(*val DecStr : ii -> string*) - -(*val HexStr : ii -> string*) (*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) definition MIPS_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " MIPS_write addr width data = ( - write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word) addr data )" -(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where " MIPS_read addr width = ( - (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] @@ -101,27 +115,22 @@ definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((registe definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where " undefined_exception _ = ( - (undefined_unit () \<then> - undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . - ((undefined_unit () \<then> - undefined_unit () ) \<then> - undefined_unit () ) \<then> + undefined_string () \<bind> (\<lambda> (u_0 :: string) . + undefined_unit () \<bind> (\<lambda> (u_1 :: unit) . internal_pick - [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))" + [ISAException u_1,Error_not_implemented u_0,Error_misaligned_access u_1,Error_EBREAK u_1,Error_internal_error u_1])))" -(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) -(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) -definition sign_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " sign_extend1 (m__tv :: int) v = ( (sign_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" +definition mips_sign_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " mips_sign_extend (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" -definition zero_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " zero_extend1 (m__tv :: int) v = ( (zero_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" +definition mips_zero_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " mips_zero_extend (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" (*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) @@ -136,13 +145,13 @@ definition ones :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" -(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" @@ -170,7 +179,7 @@ definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where fun bit_to_bool :: " bitU \<Rightarrow> bool " where " bit_to_bool B1 = ( True )" -|" bit_to_bool B0 = ( False )" +|" bit_to_bool _ = ( False )" (*val bits_to_bool : mword ty1 -> bool*) @@ -182,12 +191,12 @@ definition bits_to_bool :: "(1)Word.word \<Rightarrow> bool " where (* function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. *) -(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) +(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*) definition to_bits :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where " to_bits l n = ( (let l = (size_itself_int l) in - (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" + (get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" (*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) @@ -197,333 +206,245 @@ definition mask0 :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))" -(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" - - -(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" - - -(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) - -definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " slice_mask (n__tv :: int) i l = ( - (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in - (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" - - -(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) - -definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " is_zero_subrange xs i j = ( - (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" - - -(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) - -definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " is_ones_subrange xs i j = ( - (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in - (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" - - -(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) - -definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where - " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' - :: ( 'm::len)Word.word)) in - (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) - :: ( 'r::len)Word.word))))" - - -(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) - -definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where - " slice_zeros_concat (r__tv :: int) xs i l l' = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" - - -(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) - -definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " subrange_subrange_eq xs i j ys i' j' = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr - ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) - j' - :: ( 'n::len)Word.word)) in - (xs = ys))))" - - -(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) - -definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where - " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr - ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) - j' - :: ( 'm::len)Word.word)) in - (or_vec - ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) - ((j' - (( 1 :: int)::ii))) - :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) - :: ( 's::len)Word.word))))" - - -(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) - -definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " place_subrange (m__tv :: int) xs i j shift = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" - - -(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) - -definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " place_slice (m__tv :: int) xs i l shift = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" - - -(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) - -definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " zext_slice (m__tv :: int) xs i l = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (extzv m__tv xs :: ( 'm::len)Word.word)))" - - -(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) +(*val undefined_CauseReg : unit -> M CauseReg*) -definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " sext_slice (m__tv :: int) xs i l = ( - (let xs = - ((arith_shiftr - ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) - ((((((int (size xs))) - i)) - l)) - :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) - :: ( 'n::len)Word.word)) in - (extsv m__tv xs :: ( 'm::len)Word.word)))" +definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where + " undefined_CauseReg _ = ( + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + return ((| CauseReg_CauseReg_chunk_0 = w__0 |))))" -(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) +(*val Mk_CauseReg : mword ty32 -> CauseReg*) -definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where - " unsigned_slice xs i l = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - Word.uint xs))" +definition Mk_CauseReg :: "(32)Word.word \<Rightarrow> CauseReg " where + " Mk_CauseReg v = ( + (| CauseReg_CauseReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )" -(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) +(*val _get_CauseReg_bits : CauseReg -> mword ty32*) -definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where - " unsigned_subrange xs i j = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i - :: ( 'n::len)Word.word)) in - Word.uint xs))" - - -(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) +definition get_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word " where + " get_CauseReg_bits v = ( + (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))" -definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " zext_ones (n__tv :: int) m = ( - (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in - (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" - - -(*val undefined_CauseReg : unit -> M CauseReg*) - -definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where - " undefined_CauseReg _ = ( - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - internal_pick [Mk_CauseReg w__0]))" +(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) -(*val _get_CauseReg : CauseReg -> mword ty32*) +definition set_CauseReg_bits :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" -fun get_CauseReg :: " CauseReg \<Rightarrow>(32)Word.word " where - " get_CauseReg (Mk_CauseReg (v)) = ( v )" +(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*) -(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) +definition update_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_bits v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|)))" -definition set_CauseReg :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_CauseReg r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_CauseReg v) in - write_reg r_ref r)))" +(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*) -(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) +(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*) -(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) +(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) (*val _get_CauseReg_BD : CauseReg -> mword ty1*) -fun get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_BD v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_BD r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_BD (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_BD v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_CE : CauseReg -> mword ty2*) -fun get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where - " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" +definition get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where + " get_CauseReg_CE v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" (*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_CE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 29 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) -fun update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_CE (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_CE v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_IV : CauseReg -> mword ty1*) -fun get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_IV v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_IV r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_IV (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IV v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_WP : CauseReg -> mword ty1*) -fun get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_WP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_WP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_WP (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_WP v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_IP : CauseReg -> mword ty8*) -fun get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where - " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where + " get_CauseReg_IP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" (*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_IP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) -fun update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_IP (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IP v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) -fun get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where - " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" +definition get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where + " get_CauseReg_ExcCode v = ( + (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" (*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_ExcCode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 6 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) -fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_ExcCode v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word))|)))" (*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) @@ -537,187 +458,271 @@ fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarro definition undefined_TLBEntryLoReg :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad " where " undefined_TLBEntryLoReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_TLBEntryLoReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = w__0 |))))" + + +(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*) + +definition Mk_TLBEntryLoReg :: "(64)Word.word \<Rightarrow> TLBEntryLoReg " where + " Mk_TLBEntryLoReg v = ( + (| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) +(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*) -fun get_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where - " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )" +definition get_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryLoReg_bits v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) +(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) -definition set_TLBEntryLoReg :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntryLoReg r_ref v = ( +definition set_TLBEntryLoReg_bits :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntryLoReg v) in + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*) + +definition update_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_bits v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapS v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_CapS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapS v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapL v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_CapL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapL v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) -fun get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where - " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where + " get_TLBEntryLoReg_PFN v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_PFN r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 29 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_PFN v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) -fun get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where - " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where + " get_TLBEntryLoReg_C v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_C r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 5 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_C v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_D v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_D r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_D v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_V v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_V r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_V v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_G v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_G r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_G v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) @@ -725,93 +730,143 @@ fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Right definition undefined_TLBEntryHiReg :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad " where " undefined_TLBEntryHiReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_TLBEntryHiReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = w__0 |))))" + + +(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*) +definition Mk_TLBEntryHiReg :: "(64)Word.word \<Rightarrow> TLBEntryHiReg " where + " Mk_TLBEntryHiReg v = ( + (| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) -fun get_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where - " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )" +(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*) +definition get_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryHiReg_bits v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) -definition set_TLBEntryHiReg :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntryHiReg r_ref v = ( +(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +definition set_TLBEntryHiReg_bits :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntryHiReg v) in + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*) + +definition update_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_bits v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) -fun get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where - " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" +definition get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where + " get_TLBEntryHiReg_R v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" (*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_R r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_R v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) -fun get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where - " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = ( - (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" +definition get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where + " get_TLBEntryHiReg_VPN2 v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" (*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_VPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 39 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_VPN2 v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) -fun get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where - " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" +definition get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where + " get_TLBEntryHiReg_ASID v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_ASID r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_ASID v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|)))" (*val undefined_ContextReg : unit -> M ContextReg*) @@ -819,69 +874,111 @@ fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Ri definition undefined_ContextReg :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad " where " undefined_ContextReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_ContextReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| ContextReg_ContextReg_chunk_0 = w__0 |))))" + +(*val Mk_ContextReg : mword ty64 -> ContextReg*) -(*val _get_ContextReg : ContextReg -> mword ty64*) +definition Mk_ContextReg :: "(64)Word.word \<Rightarrow> ContextReg " where + " Mk_ContextReg v = ( + (| ContextReg_ContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -fun get_ContextReg :: " ContextReg \<Rightarrow>(64)Word.word " where - " get_ContextReg (Mk_ContextReg (v)) = ( v )" +(*val _get_ContextReg_bits : ContextReg -> mword ty64*) -(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) +definition get_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word " where + " get_ContextReg_bits v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -definition set_ContextReg :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_ContextReg r_ref v = ( + +(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +definition set_ContextReg_bits :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_ContextReg v) in + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*) + +definition update_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_bits v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) -fun get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where - " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" +definition get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where + " get_ContextReg_PTEBase v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" (*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_ContextReg_PTEBase r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . - (let r = ((get_ContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_ContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec v (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) -fun update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where - " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = ( - Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" +definition update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_PTEBase v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec x (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word)) + :: 64 Word.word))|)))" (*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) -fun get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where - " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" +definition get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where + " get_ContextReg_BadVPN2 v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" (*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_ContextReg_BadVPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . - (let r = ((get_ContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_ContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 22 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) -fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where - " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = ( - Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_BadVPN2 v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word)) + :: 64 Word.word))|)))" (*val undefined_XContextReg : unit -> M XContextReg*) @@ -889,94 +986,143 @@ fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Righ definition undefined_XContextReg :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad " where " undefined_XContextReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_XContextReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| XContextReg_XContextReg_chunk_0 = w__0 |))))" + + +(*val Mk_XContextReg : mword ty64 -> XContextReg*) +definition Mk_XContextReg :: "(64)Word.word \<Rightarrow> XContextReg " where + " Mk_XContextReg v = ( + (| XContextReg_XContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_XContextReg : XContextReg -> mword ty64*) -fun get_XContextReg :: " XContextReg \<Rightarrow>(64)Word.word " where - " get_XContextReg (Mk_XContextReg (v)) = ( v )" +(*val _get_XContextReg_bits : XContextReg -> mword ty64*) +definition get_XContextReg_bits :: " XContextReg \<Rightarrow>(64)Word.word " where + " get_XContextReg_bits v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) -definition set_XContextReg :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_XContextReg r_ref v = ( +(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +definition set_XContextReg_bits :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_XContextReg v) in + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*) + +definition update_XContextReg_bits :: " XContextReg \<Rightarrow>(64)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_bits v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) -fun get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where - " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = ( - (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" +definition get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where + " get_XContextReg_XPTEBase v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" (*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) definition set_XContextReg_XPTEBase :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XPTEBase r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 63 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec v (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) -fun update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XPTEBase v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec x (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) + :: 64 Word.word))|)))" (*val _get_XContextReg_XR : XContextReg -> mword ty2*) -fun get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where - " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" +definition get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where + " get_XContextReg_XR v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" (*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) definition set_XContextReg_XR :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XR r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 32 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) -fun update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XR (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XR v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 32 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) -fun get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where - " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = ( - (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" +definition get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where + " get_XContextReg_XBadVPN2 v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" (*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) definition set_XContextReg_XBadVPN2 :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XBadVPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 30 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) -fun update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XBadVPN2 v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 30 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|)))" definition TLBNumEntries :: " int " where @@ -1010,437 +1156,632 @@ definition MAX_PA :: " int " where definition undefined_TLBEntry :: " unit \<Rightarrow>((register_value),(TLBEntry),(exception))monad " where " undefined_TLBEntry _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii) :: ( 117 Word.word) M) \<bind> (\<lambda> (w__0 :: 117 Word.word) . - internal_pick [Mk_TLBEntry w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 :: int)::ii) :: ( 53 Word.word) M) \<bind> (\<lambda> (w__0 :: 53 Word.word) . + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + return ((| TLBEntry_TLBEntry_chunk_1 = w__0, + TLBEntry_TLBEntry_chunk_0 = w__1 |)))))" + +(*val Mk_TLBEntry : mword ty117 -> TLBEntry*) -(*val _get_TLBEntry : TLBEntry -> mword ty117*) +definition Mk_TLBEntry :: "(117)Word.word \<Rightarrow> TLBEntry " where + " Mk_TLBEntry v = ( + (| TLBEntry_TLBEntry_chunk_1 = ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -fun get_TLBEntry :: " TLBEntry \<Rightarrow>(117)Word.word " where - " get_TLBEntry (Mk_TLBEntry (v)) = ( v )" +(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*) -(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) +definition get_TLBEntry_bits :: " TLBEntry \<Rightarrow>(117)Word.word " where + " get_TLBEntry_bits v = ( + (concat_vec ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 0 :: int)::ii) :: 53 Word.word)) + ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 117 Word.word))" -definition set_TLBEntry :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntry r_ref v = ( + +(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +definition set_TLBEntry_bits :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntry v) in - write_reg r_ref r)))" + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 52 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)) + :: 53 Word.word))|))) in + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r))))" + + +(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*) + +definition update_TLBEntry_bits :: " TLBEntry \<Rightarrow>(117)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_bits v x = ( + (let v = + ((v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)) + :: 53 Word.word))|))) in + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))))" (*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) -fun get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where - " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) :: 16 Word.word))" +definition get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where + " get_TLBEntry_pagemask v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 37 :: int)::ii) :: 16 Word.word))" (*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) definition set_TLBEntry_pagemask :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pagemask r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 52 :: int)::ii) (( 37 :: int)::ii) + ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) -fun update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pagemask v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 37 :: int)::ii) + ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_r : TLBEntry -> mword ty2*) -fun get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where - " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) :: 2 Word.word))" +definition get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where + " get_TLBEntry_r v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 36 :: int)::ii) (( 35 :: int)::ii) :: 2 Word.word))" (*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) definition set_TLBEntry_r :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_r r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 36 :: int)::ii) (( 35 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) -fun update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_r (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_r v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 36 :: int)::ii) (( 35 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) -fun get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where - " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) :: 27 Word.word))" +definition get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where + " get_TLBEntry_vpn2 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 34 :: int)::ii) (( 8 :: int)::ii) :: 27 Word.word))" (*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) definition set_TLBEntry_vpn2 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_vpn2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 34 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) -fun update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_vpn2 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 34 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) -fun get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where - " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) :: 8 Word.word))" +definition get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where + " get_TLBEntry_asid v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) definition set_TLBEntry_asid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_asid r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) -fun update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_asid (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_asid v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_g : TLBEntry -> mword ty1*) -fun get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_g v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_g :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_g r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_g (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_g v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) -fun get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_valid v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_valid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_valid r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_valid (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_valid v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_caps1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_caps1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 61 :: int)::ii) (( 61 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 61 :: int)::ii) (( 61 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_capl1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_capl1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 60 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 60 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) -fun get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where - " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) definition set_TLBEntry_pfn1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pfn1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 59 :: int)::ii) (( 36 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) -fun update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 59 :: int)::ii) (( 36 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) -fun get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where - " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) definition set_TLBEntry_c1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_c1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 35 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) -fun update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 35 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_d1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_d1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 32 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 32 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_v1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_v1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_caps0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_caps0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 30 :: int)::ii) (( 30 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 30 :: int)::ii) (( 30 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_capl0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_capl0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 29 :: int)::ii) (( 29 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 29 :: int)::ii) (( 29 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) -fun get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where - " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) definition set_TLBEntry_pfn0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pfn0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 28 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) -fun update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 28 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) -fun get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where - " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) definition set_TLBEntry_c0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_c0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 4 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) -fun update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 4 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_d0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_d0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_v0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_v0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref)list " where @@ -1463,253 +1804,367 @@ definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref definition undefined_StatusReg :: " unit \<Rightarrow>((register_value),(StatusReg),(exception))monad " where " undefined_StatusReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - internal_pick [Mk_StatusReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + return ((| StatusReg_StatusReg_chunk_0 = w__0 |))))" + + +(*val Mk_StatusReg : mword ty32 -> StatusReg*) + +definition Mk_StatusReg :: "(32)Word.word \<Rightarrow> StatusReg " where + " Mk_StatusReg v = ( + (| StatusReg_StatusReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )" -(*val _get_StatusReg : StatusReg -> mword ty32*) +(*val _get_StatusReg_bits : StatusReg -> mword ty32*) -fun get_StatusReg :: " StatusReg \<Rightarrow>(32)Word.word " where - " get_StatusReg (Mk_StatusReg (v)) = ( v )" +definition get_StatusReg_bits :: " StatusReg \<Rightarrow>(32)Word.word " where + " get_StatusReg_bits v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))" -(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) +(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) -definition set_StatusReg :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_StatusReg r_ref v = ( +definition set_StatusReg_bits :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_StatusReg v) in + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|))) in write_reg r_ref r)))" +(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*) + +definition update_StatusReg_bits :: " StatusReg \<Rightarrow>(32)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_bits v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|)))" + + (*val _get_StatusReg_CU : StatusReg -> mword ty4*) -fun get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where - " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" +definition get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where + " get_StatusReg_CU v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" (*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) definition set_StatusReg_CU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_CU r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 31 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) -fun update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_CU (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_CU v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_BEV : StatusReg -> mword ty1*) -fun get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_BEV v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_BEV :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_BEV r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_BEV (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_BEV v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_IM : StatusReg -> mword ty8*) -fun get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where - " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where + " get_StatusReg_IM v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" (*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) definition set_StatusReg_IM :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_IM r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) -fun update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_IM (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IM v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_KX : StatusReg -> mword ty1*) -fun get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_KX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_KX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_KX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_KX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_SX : StatusReg -> mword ty1*) -fun get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_SX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_SX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_SX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_SX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_SX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_UX : StatusReg -> mword ty1*) -fun get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_UX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_UX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_UX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_UX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_UX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_KSU : StatusReg -> mword ty2*) -fun get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where - " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" +definition get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where + " get_StatusReg_KSU v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" (*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) definition set_StatusReg_KSU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_KSU r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 4 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) -fun update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_KSU (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KSU v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_ERL : StatusReg -> mword ty1*) -fun get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_ERL v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_ERL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_ERL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_ERL (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_ERL v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_EXL : StatusReg -> mword ty1*) -fun get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_EXL v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_EXL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_EXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_EXL (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_EXL v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_IE : StatusReg -> mword ty1*) -fun get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_IE v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_IE :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_IE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_IE (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IE v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val execute_branch : mword ty64 -> M unit*) @@ -1747,10 +2202,10 @@ definition rGPR :: "(5)Word.word \<Rightarrow>((register_value),((64)Word.word) definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " wGPR idx v = ( (let i = (Word.uint idx) in - if (((i = (( 0 :: int)::ii)))) then return () - else + if (((i \<noteq> (( 0 :: int)::ii)))) then read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . - write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list)))))" + write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list))) + else return () ))" @@ -1771,25 +2226,25 @@ definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((regi definition Exception_of_num :: " int \<Rightarrow> Exception " where " Exception_of_num arg0 = ( - (let l__81 = arg0 in - if (((l__81 = (( 0 :: int)::ii)))) then Interrupt - else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod - else if (((l__81 = (( 2 :: int)::ii)))) then TLBL - else if (((l__81 = (( 3 :: int)::ii)))) then TLBS - else if (((l__81 = (( 4 :: int)::ii)))) then AdEL - else if (((l__81 = (( 5 :: int)::ii)))) then AdES - else if (((l__81 = (( 6 :: int)::ii)))) then Sys - else if (((l__81 = (( 7 :: int)::ii)))) then Bp - else if (((l__81 = (( 8 :: int)::ii)))) then ResI - else if (((l__81 = (( 9 :: int)::ii)))) then CpU - else if (((l__81 = (( 10 :: int)::ii)))) then Ov - else if (((l__81 = (( 11 :: int)::ii)))) then Tr - else if (((l__81 = (( 12 :: int)::ii)))) then C2E - else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap - else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL - else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS - else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL - else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Interrupt + else if (((p00 = (( 1 :: int)::ii)))) then TLBMod + else if (((p00 = (( 2 :: int)::ii)))) then TLBL + else if (((p00 = (( 3 :: int)::ii)))) then TLBS + else if (((p00 = (( 4 :: int)::ii)))) then AdEL + else if (((p00 = (( 5 :: int)::ii)))) then AdES + else if (((p00 = (( 6 :: int)::ii)))) then Sys + else if (((p00 = (( 7 :: int)::ii)))) then Bp + else if (((p00 = (( 8 :: int)::ii)))) then ResI + else if (((p00 = (( 9 :: int)::ii)))) then CpU + else if (((p00 = (( 10 :: int)::ii)))) then Ov + else if (((p00 = (( 11 :: int)::ii)))) then Tr + else if (((p00 = (( 12 :: int)::ii)))) then C2E + else if (((p00 = (( 13 :: int)::ii)))) then C2Trap + else if (((p00 = (( 14 :: int)::ii)))) then XTLBRefillL + else if (((p00 = (( 15 :: int)::ii)))) then XTLBRefillS + else if (((p00 = (( 16 :: int)::ii)))) then XTLBInvL + else if (((p00 = (( 17 :: int)::ii)))) then XTLBInvS else MCheck))" @@ -1892,7 +2347,7 @@ definition SignalExceptionMIPS :: " Exception \<Rightarrow>(64)Word.word \<Righ ((write_reg nextPC_ref ((sub_vec - ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) + ((add_vec vectorBase ((mips_sign_extend (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) kccBase :: 64 Word.word)) \<then> set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex :: 5 Word.word))) \<then> @@ -2051,10 +2506,10 @@ definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(ex (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . (let pcc = (capRegToCapStruct w__1) in (let (success, epcc) = (setCapOffset pcc pc) in - if success then write_reg C31_ref ((capStructToCapReg epcc :: 257 Word.word)) + if success then write_reg EPCC_ref ((capStructToCapReg epcc :: 257 Word.word)) else write_reg - C31_ref + EPCC_ref ((capStructToCapReg ((int_to_cap ((add_vec_int @@ -2063,11 +2518,11 @@ definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(ex :: 64 Word.word)))) :: 257 Word.word)))))) else return () ) \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . (write_reg nextPCC_ref w__2 \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . (write_reg delayedPCC_ref w__3 \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . (let base = (getCapBase ((capRegToCapStruct w__4))) in SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) base :: 64 Word.word))))))))" @@ -2094,9 +2549,9 @@ definition SignalExceptionTLB :: " Exception \<Rightarrow>(64)Word.word \<Right definition MemAccessType_of_num :: " int \<Rightarrow> MemAccessType " where " MemAccessType_of_num arg0 = ( - (let l__79 = arg0 in - if (((l__79 = (( 0 :: int)::ii)))) then Instruction - else if (((l__79 = (( 1 :: int)::ii)))) then LoadData + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Instruction + else if (((p00 = (( 1 :: int)::ii)))) then LoadData else StoreData))" @@ -2118,9 +2573,9 @@ definition undefined_MemAccessType :: " unit \<Rightarrow>((register_value),(Me definition AccessLevel_of_num :: " int \<Rightarrow> AccessLevel " where " AccessLevel_of_num arg0 = ( - (let l__77 = arg0 in - if (((l__77 = (( 0 :: int)::ii)))) then User - else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then User + else if (((p00 = (( 1 :: int)::ii)))) then Supervisor else Kernel))" @@ -2171,8 +2626,8 @@ definition getAccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel if w__2 then return Kernel else read_reg CP0Status_ref \<bind> (\<lambda> (w__3 :: StatusReg) . - (let p__133 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in - (let b__0 = p__133 in + (let p__31 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in + (let b__0 = p__31 in return (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Kernel else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then User @@ -2234,10 +2689,10 @@ definition incrementCP0Count :: " unit \<Rightarrow>((register_value),(unit),(e definition decode_failure_of_num :: " int \<Rightarrow> decode_failure " where " decode_failure_of_num arg0 = ( - (let l__74 = arg0 in - if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern - else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction - else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then No_matching_pattern + else if (((p00 = (( 1 :: int)::ii)))) then Unsupported_instruction + else if (((p00 = (( 2 :: int)::ii)))) then Illegal_instruction else Internal_error))" @@ -2258,14 +2713,14 @@ definition undefined_decode_failure :: " unit \<Rightarrow>((register_value),(d definition Comparison_of_num :: " int \<Rightarrow> Comparison " where " Comparison_of_num arg0 = ( - (let l__67 = arg0 in - if (((l__67 = (( 0 :: int)::ii)))) then EQ' - else if (((l__67 = (( 1 :: int)::ii)))) then NE - else if (((l__67 = (( 2 :: int)::ii)))) then GE - else if (((l__67 = (( 3 :: int)::ii)))) then GEU - else if (((l__67 = (( 4 :: int)::ii)))) then GT' - else if (((l__67 = (( 5 :: int)::ii)))) then LE - else if (((l__67 = (( 6 :: int)::ii)))) then LT' + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then EQ' + else if (((p00 = (( 1 :: int)::ii)))) then NE + else if (((p00 = (( 2 :: int)::ii)))) then GE + else if (((p00 = (( 3 :: int)::ii)))) then GEU + else if (((p00 = (( 4 :: int)::ii)))) then GT' + else if (((p00 = (( 5 :: int)::ii)))) then LE + else if (((p00 = (( 6 :: int)::ii)))) then LT' else LTU))" @@ -2305,10 +2760,10 @@ fun compare :: " Comparison \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.wo definition WordType_of_num :: " int \<Rightarrow> WordType " where " WordType_of_num arg0 = ( - (let l__64 = arg0 in - if (((l__64 = (( 0 :: int)::ii)))) then B - else if (((l__64 = (( 1 :: int)::ii)))) then H - else if (((l__64 = (( 2 :: int)::ii)))) then W + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then B + else if (((p00 = (( 1 :: int)::ii)))) then H + else if (((p00 = (( 2 :: int)::ii)))) then W else D))" @@ -2327,6 +2782,32 @@ definition undefined_WordType :: " unit \<Rightarrow>((register_value),(WordTyp " undefined_WordType _ = ( internal_pick [B,H,W,D])" +(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*) + +definition WordTypeUnaligned_of_num :: " int \<Rightarrow> WordTypeUnaligned " where + " WordTypeUnaligned_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then WL + else if (((p00 = (( 1 :: int)::ii)))) then WR + else if (((p00 = (( 2 :: int)::ii)))) then DL + else DR))" + + +(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*) + +fun num_of_WordTypeUnaligned :: " WordTypeUnaligned \<Rightarrow> int " where + " num_of_WordTypeUnaligned WL = ( (( 0 :: int)::ii))" +|" num_of_WordTypeUnaligned WR = ( (( 1 :: int)::ii))" +|" num_of_WordTypeUnaligned DL = ( (( 2 :: int)::ii))" +|" num_of_WordTypeUnaligned DR = ( (( 3 :: int)::ii))" + + +(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*) + +definition undefined_WordTypeUnaligned :: " unit \<Rightarrow>((register_value),(WordTypeUnaligned),(exception))monad " where + " undefined_WordTypeUnaligned _ = ( internal_pick [WL,WR,DL,DR])" + + (*val wordWidthBytes : WordType -> integer*) fun wordWidthBytes :: " WordType \<Rightarrow> int " where @@ -2349,19 +2830,52 @@ definition isAddressAligned :: "(64)Word.word \<Rightarrow> WordType \<Rightarr alignment_width)))))" -(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*) -definition MEMr_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where - " MEMr_wrapper addr size1 = ( - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . - return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" +definition MEMr_wrapper :: " int \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_wrapper (p8_times_n___tv :: int) addr size1 = ( + if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (read_reg UART_RVALID_ref :: ( 1 Word.word) M) \<bind> (\<lambda> rvalid . + (write_reg UART_RVALID_ref (vec_of_bits [B0] :: 1 Word.word) \<then> + (read_reg UART_RDATA_ref :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__0 :: 8 bits) . + return ((mask0 p8_times_n___tv + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec w__0 + ((concat_vec rvalid + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 16 Word.word) + :: 23 Word.word)) + :: 24 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + :: ( 'p8_times_n_::len)Word.word)))) + else if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] + :: 64 Word.word)))) then + return ((mask0 p8_times_n___tv + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word) + :: ( 'p8_times_n_::len)Word.word)) + else + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__1 . + return ((reverse_endianness w__1 :: ( 'p8_times_n_::len)Word.word))))" (*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) definition MEMr_reserve_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where " MEMr_reserve_wrapper addr size1 = ( - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" @@ -2377,6 +2891,181 @@ definition init_cp0_state :: " unit \<Rightarrow>((register_value),(unit),(exce (*val dump_cp2_state : unit -> M unit*) +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = + ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys + ((slice_mask ((int (size xs))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys + ((slice_mask ((int (size ys))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'm::len)Word.word)) + :: ( 'm::len)Word.word)) j' + :: ( 'm::len)Word.word)) in + (or_vec + ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) ((((i' - j')) + (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + (*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry \<Rightarrow> bool " where @@ -2388,7 +3077,7 @@ definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarr (let entryASID = ((get_TLBEntry_asid entry :: 8 Word.word)) in (let entryG = ((get_TLBEntry_g entry :: 1 Word.word)) in (let (vpnMask :: 27 bits) = - ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in + ((not_vec ((mips_zero_extend (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in (((bits_to_bool entryValid)) \<and> ((((((r = entryR))) \<and> ((((((((and_vec vpn2 vpnMask :: 27 Word.word)) = ((and_vec entryVPN vpnMask :: 27 Word.word))))) \<and> ((((((asid = entryASID))) \<or> ((bits_to_bool entryG))))))))))))))))))))" @@ -2470,7 +3159,7 @@ definition TLBTranslate2 :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta (SignalExceptionTLB TLBMod vAddr :: (( 64 Word.word * bool)) M) else (let (res :: 64 bits) = - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) ((subrange_subrange_concat (((((((( 23 :: int)::ii) - ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii))))) @@ -2514,7 +3203,7 @@ definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) :: 32 Word.word)) :: 64 Word.word))) - else + else if (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (Kernel, Some ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -2524,7 +3213,8 @@ definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) :: 32 Word.word)) :: 64 Word.word))) - | (g__131, g__132) => (Kernel, None) + else (case (True, b__1) of (g__29, g__30) => (Kernel, None) ) + | (g__29, g__30) => (Kernel, None) ) else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then (Kernel, @@ -2563,14 +3253,14 @@ definition TLBTranslate :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightar definition CPtrCmpOp_of_num :: " int \<Rightarrow> CPtrCmpOp " where " CPtrCmpOp_of_num arg0 = ( - (let l__57 = arg0 in - if (((l__57 = (( 0 :: int)::ii)))) then CEQ - else if (((l__57 = (( 1 :: int)::ii)))) then CNE - else if (((l__57 = (( 2 :: int)::ii)))) then CLT - else if (((l__57 = (( 3 :: int)::ii)))) then CLE - else if (((l__57 = (( 4 :: int)::ii)))) then CLTU - else if (((l__57 = (( 5 :: int)::ii)))) then CLEU - else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CEQ + else if (((p00 = (( 1 :: int)::ii)))) then CNE + else if (((p00 = (( 2 :: int)::ii)))) then CLT + else if (((p00 = (( 3 :: int)::ii)))) then CLE + else if (((p00 = (( 4 :: int)::ii)))) then CLTU + else if (((p00 = (( 5 :: int)::ii)))) then CLEU + else if (((p00 = (( 6 :: int)::ii)))) then CEXEQ else CNEXEQ))" @@ -2597,10 +3287,10 @@ definition undefined_CPtrCmpOp :: " unit \<Rightarrow>((register_value),(CPtrCm definition ClearRegSet_of_num :: " int \<Rightarrow> ClearRegSet " where " ClearRegSet_of_num arg0 = ( - (let l__54 = arg0 in - if (((l__54 = (( 0 :: int)::ii)))) then GPLo - else if (((l__54 = (( 1 :: int)::ii)))) then GPHi - else if (((l__54 = (( 2 :: int)::ii)))) then CLo + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then GPLo + else if (((p00 = (( 1 :: int)::ii)))) then GPHi + else if (((p00 = (( 2 :: int)::ii)))) then CLo else CHi))" @@ -2625,13 +3315,13 @@ definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStr " undefined_CapStruct _ = ( undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . undefined_bool () \<bind> (\<lambda> (w__5 :: bool) . undefined_bool () \<bind> (\<lambda> (w__6 :: bool) . undefined_bool () \<bind> (\<lambda> (w__7 :: bool) . @@ -2645,11 +3335,11 @@ definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStr undefined_bool () \<bind> (\<lambda> (w__15 :: bool) . undefined_bool () \<bind> (\<lambda> (w__16 :: bool) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . return ((| CapStruct_tag = w__0, CapStruct_padding = w__1, CapStruct_otype = w__2, @@ -2678,7 +3368,7 @@ definition default_cap :: " CapStruct " where CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), CapStruct_uperms = ((ones (( 16 :: int)::ii) () :: 16 Word.word)), - CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) () :: 4 Word.word)), CapStruct_access_system_regs = True, CapStruct_permit_unseal = True, CapStruct_permit_ccall = True, @@ -2724,8 +3414,7 @@ definition memBitsToCapBits :: " bool \<Rightarrow>(256)Word.word \<Rightarrow> definition setCapPerms :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct " where " setCapPerms cap perms = ( (cap (| - CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_perm_reserved11_14 := - ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii) :: 4 Word.word)), CapStruct_access_system_regs := + CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal := @@ -2801,738 +3490,70 @@ definition setCapBounds :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> definition undefined_ast :: " unit \<Rightarrow>((register_value),(ast),(exception))monad " where " undefined_ast _ = ( + undefined_CPtrCmpOp () \<bind> (\<lambda> (u_0 :: CPtrCmpOp) . + undefined_ClearRegSet () \<bind> (\<lambda> (u_1 :: ClearRegSet) . + undefined_Comparison () \<bind> (\<lambda> (u_2 :: Comparison) . + undefined_WordType () \<bind> (\<lambda> (u_3 :: WordType) . + undefined_bool () \<bind> (\<lambda> (u_5 :: bool) . + undefined_bool () \<bind> (\<lambda> (u_4 :: bool) . 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5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__351 :: 5 Word.word) . - undefined_unit () \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \<bind> (\<lambda> (u_16 :: 26 bits) . internal_pick - [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL 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(w__180,w__181,w__182,w__183,w__184),LWL (w__185,w__186,w__187),LWR (w__188,w__189,w__190),SWL (w__191,w__192,w__193),SWR (w__194,w__195,w__196),LDL (w__197,w__198,w__199),LDR (w__200,w__201,w__202),SDL (w__203,w__204,w__205),SDR (w__206,w__207,w__208),CACHE (w__209,w__210,w__211),PREF (w__212,w__213,w__214),SYNC () ,MFC0 (w__215,w__216,w__217,w__218),HCF () ,MTC0 (w__219,w__220,w__221,w__222),TLBWI () ,TLBWR () ,TLBR () ,TLBP () ,RDHWR (w__223,w__224),ERET () ,CGetPerm (w__225,w__226),CGetType (w__227,w__228),CGetBase (w__229,w__230),CGetLen (w__231,w__232),CGetTag (w__233,w__234),CGetSealed (w__235,w__236),CGetOffset (w__237,w__238),CGetAddr (w__239,w__240),CGetPCC w__241,CGetPCCSetOffset (w__242,w__243),CGetCause w__244,CSetCause w__245,CReadHwr (w__246,w__247),CWriteHwr (w__248,w__249),CAndPerm (w__250,w__251,w__252),CToPtr (w__253,w__254,w__255),CSub (w__256,w__257,w__258),CPtrCmp (w__259,w__260,w__261,w__262),CIncOffset (w__263,w__264,w__265),CIncOffsetImmediate (w__266,w__267,w__268),CSetOffset (w__269,w__270,w__271),CSetBounds (w__272,w__273,w__274),CSetBoundsImmediate (w__275,w__276,w__277),CSetBoundsExact (w__278,w__279,w__280),CClearTag (w__281,w__282),CMOVX (w__283,w__284,w__285,w__286),ClearRegs (w__287,w__288),CFromPtr (w__289,w__290,w__291),CBuildCap (w__292,w__293,w__294),CCopyType (w__295,w__296,w__297),CCheckPerm (w__298,w__299),CCheckType (w__300,w__301),CTestSubset (w__302,w__303,w__304),CSeal (w__305,w__306,w__307),CCSeal (w__308,w__309,w__310),CUnseal (w__311,w__312,w__313),CCall (w__314,w__315,w__316),CReturn () ,CBX (w__317,w__318,w__319),CBZ (w__320,w__321,w__322),CJALR (w__323,w__324,w__325),CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332),CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339),CSC (w__340,w__341,w__342,w__343,w__344,w__345),CLC (w__346,w__347,w__348,w__349,w__350),C2Dump w__351,RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + [DADDIU (u_8,u_7,u_6),DADDU (u_9,u_8,u_7),DADDI (u_8,u_7,u_15),DADD (u_9,u_8,u_7),ADD (u_9,u_8,u_7),ADDI (u_8,u_7,u_15),ADDU (u_9,u_8,u_7),ADDIU (u_8,u_7,u_15),DSUBU (u_9,u_8,u_7),DSUB (u_9,u_8,u_7),SUB (u_9,u_8,u_7),SUBU (u_9,u_8,u_7),AND0 (u_9,u_8,u_7),ANDI (u_8,u_7,u_15),OR0 (u_9,u_8,u_7),ORI (u_8,u_7,u_15),NOR (u_9,u_8,u_7),XOR0 (u_9,u_8,u_7),XORI (u_8,u_7,u_15),LUI (u_7,u_6),DSLL (u_9,u_8,u_7),DSLL32 (u_9,u_8,u_7),DSLLV (u_9,u_8,u_7),DSRA (u_9,u_8,u_7),DSRA32 (u_9,u_8,u_7),DSRAV (u_9,u_8,u_7),DSRL (u_9,u_8,u_7),DSRL32 (u_9,u_8,u_7),DSRLV (u_9,u_8,u_7),SLL (u_9,u_8,u_7),SLLV (u_9,u_8,u_7),SRA (u_9,u_8,u_7),SRAV (u_9,u_8,u_7),SRL (u_9,u_8,u_7),SRLV (u_9,u_8,u_7),SLT (u_9,u_8,u_7),SLTI (u_8,u_7,u_15),SLTU (u_9,u_8,u_7),SLTIU (u_8,u_7,u_15),MOVN (u_9,u_8,u_7),MOVZ (u_9,u_8,u_7),MFHI u_7,MFLO u_7,MTHI u_7,MTLO u_7,MUL (u_9,u_8,u_7),MULT (u_8,u_7),MULTU (u_8,u_7),DMULT (u_8,u_7),DMULTU (u_8,u_7),MADD (u_8,u_7),MADDU (u_8,u_7),MSUB (u_8,u_7),MSUBU (u_8,u_7),DIV (u_8,u_7),DIVU (u_8,u_7),DDIV (u_8,u_7),DDIVU (u_8,u_7),J u_16,JAL u_16,JR u_7,JALR (u_8,u_7),BEQ (u_8,u_7,u_6,u_5,u_4),BCMPZ (u_7,u_6,u_2,u_5,u_4),SYSCALL u_11,BREAK u_11,WAIT u_11,TRAPREG (u_8,u_7,u_2),TRAPIMM (u_7,u_6,u_2),Load (u_3,u_5,u_4,u_8,u_7,u_6),Store (u_3,u_4,u_8,u_7,u_6),LWL (u_8,u_7,u_15),LWR (u_8,u_7,u_15),SWL (u_8,u_7,u_15),SWR (u_8,u_7,u_15),LDL (u_8,u_7,u_15),LDR (u_8,u_7,u_15),SDL (u_8,u_7,u_15),SDR (u_8,u_7,u_15),CACHE (u_8,u_7,u_15),SYNC u_11,MFC0 (u_8,u_7,u_12,u_4),HCF u_11,MTC0 (u_8,u_7,u_12,u_4),TLBWI u_11,TLBWR u_11,TLBR u_11,TLBP u_11,RDHWR (u_8,u_7),ERET u_11,CGetPerm (u_8,u_7),CGetType (u_8,u_7),CGetBase (u_8,u_7),CGetLen (u_8,u_7),CGetTag (u_8,u_7),CGetSealed (u_8,u_7),CGetOffset (u_8,u_7),CGetAddr (u_8,u_7),CGetPCC u_7,CGetPCCSetOffset (u_8,u_7),CGetCause u_7,CSetCause u_7,CReadHwr (u_8,u_7),CWriteHwr (u_8,u_7),CAndPerm (u_9,u_8,u_7),CToPtr (u_9,u_8,u_7),CSub (u_9,u_8,u_7),CPtrCmp (u_9,u_8,u_7,u_0),CIncOffset (u_9,u_8,u_7),CIncOffsetImmediate (u_8,u_7,u_14),CSetOffset (u_9,u_8,u_7),CSetBounds (u_9,u_8,u_7),CSetBoundsImmediate (u_8,u_7,u_14),CSetBoundsExact (u_9,u_8,u_7),CClearTag (u_8,u_7),CMOVX (u_9,u_8,u_7,u_4),ClearRegs (u_1,u_15),CFromPtr (u_9,u_8,u_7),CBuildCap (u_9,u_8,u_7),CCopyType (u_9,u_8,u_7),CCheckPerm (u_8,u_7),CCheckType (u_8,u_7),CTestSubset (u_9,u_8,u_7),CSeal (u_9,u_8,u_7),CCSeal (u_9,u_8,u_7),CUnseal (u_9,u_8,u_7),CCall (u_8,u_7,u_14),CReturn u_11,CBX (u_7,u_15,u_4),CBZ (u_7,u_15,u_4),CJALR (u_8,u_7,u_4),CLoad (u_9,u_8,u_7,u_13,u_5,u_3,u_4),CStore (u_10,u_9,u_8,u_7,u_13,u_3,u_4),CSC (u_10,u_9,u_8,u_7,u_14,u_4),CLC (u_9,u_8,u_7,u_15,u_4),C2Dump u_7,RI u_11]))))))))))))))))))" (*val execute : ast -> M unit*) (*val decode : mword ty32 -> maybe ast*) -definition DDC :: "(5)Word.word " where - " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" - +definition IDCNO :: "(5)Word.word " where + " IDCNO = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" -definition IDC :: "(5)Word.word " where - " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" +definition KR1CNO :: "(5)Word.word " where + " KR1CNO = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" -definition KR1C :: "(5)Word.word " where - " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" +definition KR2CNO :: "(5)Word.word " where + " KR2CNO = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" -definition KR2C :: "(5)Word.word " where - " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" +definition KCCNO :: "(5)Word.word " where + " KCCNO = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" -definition KCC :: "(5)Word.word " where - " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" +definition KDCNO :: "(5)Word.word " where + " KDCNO = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" -definition KDC :: "(5)Word.word " where - " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" - -definition EPCC :: "(5)Word.word " where - " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" +definition EPCCNO :: "(5)Word.word " where + " EPCCNO = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" definition CapRegs :: "(((regstate),(register_value),((257)Word.word))register_ref)list " where " CapRegs = ( [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref, C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref, - C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])" + C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,DDC_ref])" definition max_otype :: " int " where @@ -3545,11 +3566,29 @@ definition have_cp2 :: " bool " where (* This function reads a given capability register and returns its contents converted to a CapStruct. +If the argument is zero then the null capability is returned. *) (*val readCapReg : mword ty5 -> M CapStruct*) definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where " readCapReg n = ( + if (((n = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then return null_cap + else + (let i = (Word.uint n) in + (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + return ((capRegToCapStruct w__0)))))" + + +(* +This is the same as readCapReg except that when the argument is zero the value of DDC is returned +instead of the null capability. This is used for instructions that expect an address, where using +null would always generate an exception. +*) +(*val readCapRegDDC : mword ty5 -> M CapStruct*) + +definition readCapRegDDC :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " readCapRegDDC n = ( (let i = (Word.uint n) in (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . @@ -3560,39 +3599,41 @@ definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruc definition writeCapReg :: "(5)Word.word \<Rightarrow> CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where " writeCapReg n cap = ( - (let i = (Word.uint n) in - write_reg - ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) - ((capStructToCapReg cap :: 257 Word.word))))" + if (((n = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then return () + else + (let i = (Word.uint n) in + write_reg + ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((capStructToCapReg cap :: 257 Word.word))))" (*val CapEx_of_num : integer -> CapEx*) definition CapEx_of_num :: " int \<Rightarrow> CapEx " where " CapEx_of_num arg0 = ( - (let l__32 = arg0 in - if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None - else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation - else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation - else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation - else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation - else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap - else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap - else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow - else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation - else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap - else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds - else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation - else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation - else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation - else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation - else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation - else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation - else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation - else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation - else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation - else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation - else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CapEx_None + else if (((p00 = (( 1 :: int)::ii)))) then CapEx_LengthViolation + else if (((p00 = (( 2 :: int)::ii)))) then CapEx_TagViolation + else if (((p00 = (( 3 :: int)::ii)))) then CapEx_SealViolation + else if (((p00 = (( 4 :: int)::ii)))) then CapEx_TypeViolation + else if (((p00 = (( 5 :: int)::ii)))) then CapEx_CallTrap + else if (((p00 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap + else if (((p00 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow + else if (((p00 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation + else if (((p00 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap + else if (((p00 = (( 10 :: int)::ii)))) then CapEx_InexactBounds + else if (((p00 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation + else if (((p00 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation + else if (((p00 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation + else if (((p00 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation + else if (((p00 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation + else if (((p00 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation + else if (((p00 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((p00 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation + else if (((p00 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation + else if (((p00 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation + else if (((p00 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation else CapEx_PermitUnsealViolation))" @@ -3665,59 +3706,99 @@ fun CapExCode :: " CapEx \<Rightarrow>(8)Word.word " where definition undefined_CapCauseReg :: " unit \<Rightarrow>((register_value),(CapCauseReg),(exception))monad " where " undefined_CapCauseReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . - internal_pick [Mk_CapCauseReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . + return ((| CapCauseReg_CapCauseReg_chunk_0 = w__0 |))))" + +(*val Mk_CapCauseReg : mword ty16 -> CapCauseReg*) -fun get_CapCauseReg :: " CapCauseReg \<Rightarrow>(16)Word.word " where - " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )" +definition Mk_CapCauseReg :: "(16)Word.word \<Rightarrow> CapCauseReg " where + " Mk_CapCauseReg v = ( + (| CapCauseReg_CapCauseReg_chunk_0 = ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) |) )" -definition set_CapCauseReg :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_CapCauseReg r_ref v = ( +definition get_CapCauseReg_bits :: " CapCauseReg \<Rightarrow>(16)Word.word " where + " get_CapCauseReg_bits v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))" + + +definition set_CapCauseReg_bits :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_CapCauseReg v) in + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 15 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 16 Word.word))|))) in write_reg r_ref r)))" -fun get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where - " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition update_CapCauseReg_bits :: " CapCauseReg \<Rightarrow>(16)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_bits v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 16 Word.word))|)))" + + +definition get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_ExcCode v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" definition set_CapCauseReg_ExcCode :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CapCauseReg_ExcCode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . - (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 16 Word.word)) in - write_reg r_ref (Mk_CapCauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|))) in + write_reg r_ref r)))" -fun update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where - " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = ( - Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 16 Word.word)))" +definition update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_ExcCode v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|)))" (*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) -fun get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where - " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" +definition get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_RegNum v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) definition set_CapCauseReg_RegNum :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CapCauseReg_RegNum r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . - (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 16 Word.word)) in - write_reg r_ref (Mk_CapCauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) -fun update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where - " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = ( - Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 16 Word.word)))" +definition update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_RegNum v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|)))" (*val execute_branch_pcc : CapStruct -> M unit*) @@ -3735,9 +3816,9 @@ definition execute_branch_pcc :: " CapStruct \<Rightarrow>((register_value),(un definition ERETHook :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " ERETHook _ = ( - (read_reg C31_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . (write_reg nextPCC_ref w__0 \<then> - (read_reg C31_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" + (read_reg EPCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" (*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) @@ -3757,7 +3838,7 @@ definition raise_c2_exception8 :: " CapEx \<Rightarrow>(8)Word.word \<Rightarro definition raise_c2_exception :: " CapEx \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where " raise_c2_exception capEx regnum = ( (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) regnum :: 8 Word.word)) in - if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDC)))))) then + if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDCNO)))))) then raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 else raise_c2_exception8 capEx reg8))" @@ -3786,11 +3867,11 @@ The following function should be called before reading or writing any capability definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " register_inaccessible r = ( or_boolM - (and_boolM (return (((r = IDC)))) + (and_boolM (return (((r = IDCNO)))) ((read_reg inCCallDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 Word.word) . return ((bits_to_bool w__0))))) (and_boolM - (return ((((((r = KR1C))) \<or> ((((((r = KR2C))) \<or> ((((((r = KDC))) \<or> ((((((r = KCC))) \<or> (((r = EPCC)))))))))))))))) + (return ((((((r = KR1CNO))) \<or> ((((((r = KR2CNO))) \<or> ((((((r = KDCNO))) \<or> ((((((r = KCCNO))) \<or> (((r = EPCCNO)))))))))))))))) (pcc_access_system_regs () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))))" @@ -3798,44 +3879,42 @@ definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value definition MEMr_tagged :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where " MEMr_tagged addr = ( - (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . - (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in - return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + return (tag, (reverse_endianness data :: 256 Word.word)))))" (*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) definition MEMr_tagged_reserve :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where " MEMr_tagged_reserve addr = ( - (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . - (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in - return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + return (tag, (reverse_endianness data :: 256 Word.word)))))" (*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) definition MEMw_tagged :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " MEMw_tagged addr tag data = ( - ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> - MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )" + ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag )" (*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) definition MEMw_tagged_conditional :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " MEMw_tagged_conditional addr tag data = ( - ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" definition cap_addr_mask :: "(64)Word.word " where @@ -3863,9 +3942,9 @@ definition MEMw_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_t :: 64 Word.word)) :: 64 Word.word)) cap_addr_mask :: 64 Word.word))))) ('''') \<then> - MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> - MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" + MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" (*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) @@ -3879,47 +3958,87 @@ definition MEMw_conditional_wrapper :: "(64)Word.word \<Rightarrow> int \<Right :: 64 Word.word)) :: 64 Word.word)) cap_addr_mask :: 64 Word.word))))) ('''') \<then> - MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then> MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False else return () ) \<then> return success))" -(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) +(*val checkDDCPerms : CapStruct -> MemAccessType -> M unit*) -definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where - " addrWrapper addr accessType width = ( - (let capno = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) in - readCapReg capno \<bind> (\<lambda> cap . - ((if ((\<not>(CapStruct_tag cap))) then raise_c2_exception CapEx_TagViolation capno - else if(CapStruct_sealed cap) then raise_c2_exception CapEx_SealViolation capno +definition checkDDCPerms :: " CapStruct \<Rightarrow> MemAccessType \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkDDCPerms (ddc :: CapStruct) (accessType :: MemAccessType) = ( + (if ((\<not>(CapStruct_tag ddc))) then + raise_c2_exception CapEx_TagViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + else if(CapStruct_sealed ddc) then + raise_c2_exception CapEx_SealViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () ) \<then> (case accessType of - Instruction => - if ((\<not>(CapStruct_permit_execute cap))) then - raise_c2_exception CapEx_PermitExecuteViolation capno - else return () + Instruction => assert_exp False ('''') | LoadData => - if ((\<not>(CapStruct_permit_load cap))) then raise_c2_exception CapEx_PermitLoadViolation capno + if ((\<not>(CapStruct_permit_load ddc))) then + raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () | StoreData => - if ((\<not>(CapStruct_permit_store cap))) then raise_c2_exception CapEx_PermitStoreViolation capno + if ((\<not>(CapStruct_permit_store ddc))) then + raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () - )) \<then> - ((let cursor = (getCapCursor cap) in - (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in + ))" + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapper addr accessType width = ( + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let ddc = (capRegToCapStruct w__0) in + checkDDCPerms ddc accessType \<then> + ((let cursor = (getCapCursor ddc) in + (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in (let size1 = (wordWidthBytes width) in - (let base = (getCapBase cap) in - (let top1 = (getCapTop cap) in + (let base = (getCapBase ddc) in + (let top1 = (getCapTop ddc) in if ((((vAddr + size1)) > top1)) then - (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) - else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else if ((vAddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))" +(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> M (mword ty64)*) + +definition addrWrapperUnaligned :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordTypeUnaligned \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapperUnaligned addr accessType width = ( + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let ddc = (capRegToCapStruct w__0) in + checkDDCPerms ddc accessType \<then> + ((let cursor = (getCapCursor ddc) in + (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in + (let woffset = (vAddr mod (( 4 :: int)::ii)) in + (let doffset = (vAddr mod (( 8 :: int)::ii)) in + (let ((waddr :: ii), (size1 :: ii)) = + ((case width of + WL => (vAddr, (( 4 :: int)::ii) - woffset) + | WR => (vAddr - woffset, woffset + (( 1 :: int)::ii)) + | DL => (vAddr, (( 8 :: int)::ii) - doffset) + | DR => (vAddr - doffset, doffset + (( 1 :: int)::ii)) + )) in + (let base = (getCapBase ddc) in + (let top1 = (getCapTop ddc) in + if ((((waddr + size1)) > top1)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else if ((waddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))))" + + (*val TranslatePC : mword ty64 -> M (mword ty64)*) definition TranslatePC :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where @@ -3964,13 +4083,22 @@ definition checkCP2usable :: " unit \<Rightarrow>((register_value),(unit),(exce definition init_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " init_cp2_state _ = ( (let defaultBits = ((capStructToCapReg default_cap :: 257 Word.word)) in - ((write_reg PCC_ref defaultBits \<then> + (let nullBits = ((capStructToCapReg null_cap :: 257 Word.word)) in + ((((((((((write_reg PCC_ref defaultBits \<then> write_reg nextPCC_ref defaultBits) \<then> write_reg delayedPCC_ref defaultBits) \<then> - (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + write_reg DDC_ref defaultBits) \<then> + write_reg KCC_ref defaultBits) \<then> + write_reg EPCC_ref defaultBits) \<then> + write_reg KDC_ref nullBits) \<then> + write_reg KR1C_ref nullBits) \<then> + write_reg KR2C_ref nullBits) \<then> + write_reg CTLSP_ref nullBits) \<then> + write_reg CTLSU_ref nullBits) \<then> + (foreachM (index_list (( 1 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) in - writeCapReg idx default_cap)))))" + writeCapReg idx null_cap))))))" definition cp2_next_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where @@ -3995,34 +4123,29 @@ definition capToString :: " CapStruct \<Rightarrow>((register_value),(string),( (((op@) (if(CapStruct_sealed cap) then (''1'') else (''0'')) (((op@) ('' perms:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((concat_vec (vec_of_bits [B0] :: 1 Word.word) ((getCapPerms cap :: 31 Word.word)) :: 32 Word.word)))) (((op@) ('' type:'') - (((op@) ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype cap))) + (((op@) ((string_of_bits(CapStruct_otype cap))) (((op@) ('' offset:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset cap)) :: 64 Word.word)))) (((op@) ('' base:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cap)) :: 64 Word.word)))) (((op@) ('' length:'') - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) @@ -4035,24 +4158,48 @@ definition dump_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exce " dump_cp2_state _ = ( (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . capToString ((capRegToCapStruct w__0)) \<bind> (\<lambda> (w__1 :: string) . - (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in - (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP PCC'') w__1))) in + ((foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) \<bind> (\<lambda> (w__2 :: CapStruct) . capToString w__2 \<bind> (\<lambda> (w__3 :: string) . return ((let _ = - (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int + (print_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int instance_Show_Show_Num_integer_dict i)) w__3))))) in - () ))))))))))" + () )))))) \<then> + (read_reg DDC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + capToString ((capRegToCapStruct w__4)) \<bind> (\<lambda> (w__5 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 00'') w__5))) in + (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__6 :: 257 Word.word) . + capToString ((capRegToCapStruct w__6)) \<bind> (\<lambda> (w__7 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 01'') w__7))) in + (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__8 :: 257 Word.word) . + capToString ((capRegToCapStruct w__8)) \<bind> (\<lambda> (w__9 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 08'') w__9))) in + (read_reg KR1C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__10 :: 257 Word.word) . + capToString ((capRegToCapStruct w__10)) \<bind> (\<lambda> (w__11 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 22'') w__11))) in + (read_reg KR2C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__12 :: 257 Word.word) . + capToString ((capRegToCapStruct w__12)) \<bind> (\<lambda> (w__13 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 23'') w__13))) in + (read_reg KCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . + capToString ((capRegToCapStruct w__14)) \<bind> (\<lambda> (w__15 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 29'') w__15))) in + (read_reg KDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 :: 257 Word.word) . + capToString ((capRegToCapStruct w__16)) \<bind> (\<lambda> (w__17 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 30'') w__17))) in + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 :: 257 Word.word) . + capToString ((capRegToCapStruct w__18)) \<bind> (\<lambda> (w__19 :: string) . + return ((print_endline (((op@) (''DEBUG CAP HWREG 31'') w__19)))))))))))))))))))))))))))))))" (*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) definition extendLoad :: "('sz::len)Word.word \<Rightarrow> bool \<Rightarrow>(64)Word.word " where " extendLoad memResult sign = ( - if sign then (sign_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word) - else (zero_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word))" + if sign then (mips_sign_extend (( 64 :: int)::ii) memResult :: 64 Word.word) + else (mips_zero_extend (( 64 :: int)::ii) memResult :: 64 Word.word))" (*val TLBWriteEntry : mword ty6 -> M unit*) @@ -4489,10 +4636,6 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in Some (BCMPZ (rs,imm,LE,False,True)))) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, - B1,B1,B0,B0,B1,B1,B0,B0] - :: 32 Word.word)))) then - Some (SYSCALL_THREAD_START () ) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then Some (SYSCALL () ) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then @@ -4669,11 +4812,6 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in Some (CACHE (base,op1,imm))))) - else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word)))) then - (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in - (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in - (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in - Some (PREF (base,op1,imm))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then Some (SYNC () ) @@ -5267,13 +5405,19 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in - Some (CLC (cd1,cb,rt,offset,False)))))) + Some (CLC (cd1,cb,rt,(mips_sign_extend (( 16 :: int)::ii) offset :: 16 Word.word),False)))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 11 Word.word),True)))) + B0,B0,B0,B0,B0,B0,B0, + B0,B0] + :: 16 Word.word),True)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,False))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 16 Word.word))))))) then (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in @@ -5286,7 +5430,7 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where definition execute_XORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_XORI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5301,7 +5445,7 @@ definition execute_XOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (*val execute_WAIT : unit -> M unit*) definition execute_WAIT :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_WAIT g__121 = ( + " execute_WAIT g__19 = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg nextPC_ref w__0))" @@ -5321,7 +5465,7 @@ definition execute_TRAPREG :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_TRAPIMM rs imm cmp = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . - (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (imm_val :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in (let condition = (compare cmp rs_val imm_val) in if condition then SignalException Tr else return () ))))" @@ -5330,7 +5474,7 @@ definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Righta (*val execute_TLBWR : unit -> M unit*) definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBWR g__125 = ( + " execute_TLBWR g__23 = ( (checkCP0Access () \<then> (read_reg TLBRandom_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" @@ -5338,7 +5482,7 @@ definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(excep (*val execute_TLBWI : unit -> M unit*) definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBWI g__124 = ( + " execute_TLBWI g__22 = ( (checkCP0Access () \<then> (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" @@ -5346,7 +5490,7 @@ definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(excep (*val execute_TLBR : unit -> M unit*) definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBR g__126 = ( + " execute_TLBR g__24 = ( (checkCP0Access () \<then> (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: TLBIndexT) . (let i = (Word.uint w__0) in @@ -5374,10 +5518,10 @@ definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(except (*val execute_TLBP : unit -> M unit*) definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBP g__127 = ( + " execute_TLBP g__25 = ( (checkCP0Access () \<then> read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (tlbSearch ((get_TLBEntryHiReg w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . + (tlbSearch ((get_TLBEntryHiReg_bits w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . (case result of Some (idx) => write_reg TLBProbe_ref (vec_of_bits [B0] :: 1 Word.word) \<then> write_reg TLBIndex_ref idx @@ -5392,7 +5536,7 @@ definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(except definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_Store width conditional base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData width :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . @@ -5403,19 +5547,14 @@ definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word. (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then (case width of - B => - MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) - ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) - | H => - MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) - ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) - | W => + W => MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val + | _ => throw (Error_internal_error () ) ) else return False) \<bind> (\<lambda> (success :: bool) . - wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rt ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else (case width of B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) @@ -5425,22 +5564,16 @@ definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word. ))))))" -(*val execute_SYSCALL_THREAD_START : unit -> unit*) - -definition execute_SYSCALL_THREAD_START :: " unit \<Rightarrow> unit " where - " execute_SYSCALL_THREAD_START g__117 = ( () )" - - (*val execute_SYSCALL : unit -> M unit*) definition execute_SYSCALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_SYSCALL g__119 = ( SignalException Sys )" + " execute_SYSCALL g__17 = ( SignalException Sys )" (*val execute_SYNC : unit -> M unit*) definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_SYNC g__122 = ( MEM_sync () )" + " execute_SYNC g__20 = ( MEM_sync () )" (*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -5448,8 +5581,8 @@ definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(except definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SWR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData WR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (let wordAddr = @@ -5472,8 +5605,8 @@ definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SWL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData WL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5495,10 +5628,10 @@ definition execute_SUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) @@ -5513,19 +5646,21 @@ definition execute_SUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let (temp33 :: 33 bits) = ((sub_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" @@ -5538,12 +5673,12 @@ definition execute_SRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5553,12 +5688,12 @@ definition execute_SRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5570,12 +5705,12 @@ definition execute_SRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5585,12 +5720,12 @@ definition execute_SRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5600,7 +5735,7 @@ definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5611,9 +5746,9 @@ definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_SLTIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SLTIU rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . - (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (immext :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in wGPR rt - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5627,7 +5762,7 @@ definition execute_SLTI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs_val = (Word.sint w__0) in wGPR rt - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((rs_val < imm_val)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word))))))" @@ -5640,7 +5775,7 @@ definition execute_SLT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5654,8 +5789,8 @@ definition execute_SLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5664,8 +5799,8 @@ definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> " execute_SLL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -5673,8 +5808,8 @@ definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SDR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData DR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5705,8 +5840,8 @@ definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SDL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData DL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5731,7 +5866,7 @@ definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (*val execute_RI : unit -> M unit*) definition execute_RI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_RI g__130 = ( SignalException ResI )" + " execute_RI g__28 = ( SignalException ResI )" (*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) @@ -5741,7 +5876,8 @@ definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro getAccessLevel () \<bind> (\<lambda> accessLevel . (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in + (let (haveCU0 :: bool) = + (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in (let rdi = (Word.uint rd) in (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in @@ -5749,32 +5885,26 @@ definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro else return () ) \<then> ((let b__146 = rd in (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) then (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . - return ((zero_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))) + return ((mips_zero_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))) else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) then (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else (SignalException ResI :: ( 64 Word.word) M)) \<bind> (\<lambda> (temp :: 64 bits) . wGPR rt temp)))))))))))" -(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) - -definition execute_PREF :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> unit " where - " execute_PREF base op1 imm = ( () )" - - (*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) definition execute_ORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_ORI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5803,17 +5933,19 @@ definition execute_MULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" (*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) @@ -5824,17 +5956,19 @@ definition execute_MULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" (*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5844,16 +5978,16 @@ definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (let (result :: 64 bits) = - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) :: 64 Word.word)) in (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else - return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + return ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" @@ -5877,204 +6011,93 @@ definition execute_MTHI :: "(5)Word.word \<Rightarrow>((register_value),(unit), definition execute_MTC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_MTC0 rt rd sel double = ( (checkCP0Access () \<then> - (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . - (case (rd, sel) of - (b__108, b__109) => - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBIndex_ref - ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_TLBEntryLoReg TLBEntryLo0_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_TLBEntryLoReg TLBEntryLo1_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_ContextReg_PTEBase TLBContext_ref - ((subrange_vec_dec reg_val (( 63 :: int):: ii) - (( 23 :: int):: ii) :: 41 Word.word)) else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then - write_reg CP0UserLocal_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBPageMask_ref - ((subrange_vec_dec reg_val (( 28 :: int):: ii) - (( 13 :: int):: ii) :: 16 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBWired_ref - ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) - \<then> write_reg TLBRandom_ref TLBIndexMax else - if ((((((b__108 = - (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0HWREna_ref - ((concat_vec - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 29 :: int):: ii) :: 3 Word.word)) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0] :: 25 Word.word) - ((subrange_vec_dec reg_val (( 3 :: int):: ii) - (( 0 :: int):: ii) :: 4 Word.word)) - :: 29 Word.word)) :: 32 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0Count_ref - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 0 :: int):: ii) :: 32 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (set_TLBEntryHiReg_R TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 63 :: int):: ii) - (( 62 :: int):: ii) :: 2 Word.word)) \<then> - set_TLBEntryHiReg_VPN2 TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 39 :: int):: ii) - (( 13 :: int):: ii) :: 27 Word.word))) - \<then> - set_TLBEntryHiReg_ASID TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 7 :: int):: ii) - (( 0 :: int):: ii) :: 8 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (write_reg CP0Compare_ref - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 0 :: int):: ii) :: 32 Word.word)) - \<then> read_reg CP0Cause_ref) \<bind> - (\<lambda> (w__0 :: CauseReg) . - set_CauseReg_IP CP0Cause_ref - ((and_vec - ((get_CauseReg_IP w__0 :: 8 Word.word)) - (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) - :: 8 Word.word))) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - ((((((((set_StatusReg_CU CP0Status_ref - ((subrange_vec_dec reg_val - (( 31 :: int):: ii) - (( 28 :: int):: ii) :: 4 Word.word)) - \<then> - set_StatusReg_BEV CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 22 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_IM CP0Status_ref - ((subrange_vec_dec reg_val - (( 15 :: int):: ii) - (( 8 :: int):: ii) :: 8 Word.word))) - \<then> - set_StatusReg_KX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 7 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_SX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 6 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_UX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 5 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_KSU CP0Status_ref - ((subrange_vec_dec reg_val - (( 4 :: int):: ii) - (( 3 :: int):: ii) :: 2 Word.word))) - \<then> - set_StatusReg_ERL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 2 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_EXL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 1 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_IE CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 0 :: int):: ii))) :: 1 Word.word)) - else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (set_CauseReg_IV CP0Cause_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 23 :: int):: ii))) :: 1 Word.word)) - \<then> read_reg CP0Cause_ref) \<bind> - (\<lambda> (w__1 :: CauseReg) . - (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in - set_CauseReg_IP CP0Cause_ref - ((concat_vec - ((subrange_vec_dec ip - (( 7 :: int):: ii) - (( 2 :: int):: ii) :: 6 Word.word)) - ((subrange_vec_dec reg_val - (( 9 :: int):: ii) - (( 8 :: int):: ii) :: 2 Word.word)) - :: 8 Word.word)))) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0EPC_ref reg_val else - if ((((((b__108 = - (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = - (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_XContextReg_XPTEBase - TLBXContext_ref - ((subrange_vec_dec reg_val - (( 63 :: int):: ii) - (( 33 :: int):: ii) :: 31 Word.word)) - else write_reg CP0ErrorEPC_ref reg_val - )))" + (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBIndex_ref ((mask0 (( 6 :: int)::ii) reg_val :: 6 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + write_reg CP0UserLocal_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 :: int)::ii) (( 13 :: int)::ii) :: 16 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBWired_ref ((mask0 (( 6 :: int)::ii) reg_val :: 6 Word.word)) \<then> + write_reg TLBRandom_ref TLBIndexMax + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg + CP0HWREna_ref + ((concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 29 :: int)::ii) :: 3 Word.word)) + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0] + :: 25 Word.word) ((subrange_vec_dec reg_val (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 29 Word.word)) + :: 32 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0Count_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (write_reg CP0Compare_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) \<then> + read_reg CP0Cause_ref) \<bind> (\<lambda> (w__0 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec ((get_CauseReg_IP w__0 :: 8 Word.word)) + (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) + :: 8 Word.word))) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + ((((((((set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) \<then> + set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) \<then> + set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))) \<then> + set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 :: int)::ii))) :: 1 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 :: int)::ii))) :: 1 Word.word)) \<then> + read_reg CP0Cause_ref) \<bind> (\<lambda> (w__1 :: CauseReg) . + (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec ((subrange_vec_dec ip (( 7 :: int)::ii) (( 2 :: int)::ii) :: 6 Word.word)) + ((subrange_vec_dec reg_val (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word)) + :: 8 Word.word)))) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0EPC_ref reg_val + else if ((((((b__108 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + else if ((((((b__108 = (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_XContextReg_XPTEBase TLBXContext_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word)) + else if ((((((b__108 = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0ErrorEPC_ref reg_val + else SignalException ResI + )))" (*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) @@ -6085,7 +6108,7 @@ definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6100,10 +6123,12 @@ definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) @@ -6114,7 +6139,7 @@ definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6129,10 +6154,12 @@ definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -6179,483 +6206,184 @@ definition execute_MFHI :: "(5)Word.word \<Rightarrow>((register_value),(unit), definition execute_MFC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_MFC0 rt rd sel double = ( - (checkCP0Access () \<then> - (case (rd, sel) of - (b__48, b__49) => - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__0 :: TLBIndexT) . - (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in - (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> - (\<lambda> (w__1 :: 1 bits) . - return - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word) - ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word))))) - else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__2 :: TLBIndexT) . - return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word))) - else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryLo0_ref \<bind> - (\<lambda> (w__3 :: TLBEntryLoReg) . - return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryLo1_ref \<bind> - (\<lambda> (w__4 :: TLBEntryLoReg) . - return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBContext_ref \<bind> - (\<lambda> (w__5 :: ContextReg) . - return ((get_ContextReg w__5 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then - (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> - (\<lambda> (w__7 :: 16 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((concat_vec w__7 - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) - :: 28 Word.word)) :: 64 Word.word))) else - if ((((((b__48 = - (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__8 :: TLBIndexT) . - return - ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__9 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0Count_ref :: ( 32 Word.word) M) - \<bind> - (\<lambda> (w__11 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryHi_ref \<bind> - (\<lambda> (w__12 :: TLBEntryHiReg) . - return - ((get_TLBEntryHiReg w__12 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0Compare_ref :: ( 32 Word.word) M) - \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg CP0Status_ref \<bind> - (\<lambda> (w__14 :: StatusReg) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg CP0Cause_ref \<bind> - (\<lambda> (w__15 :: CauseReg) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0EPC_ref :: ( 64 Word.word) M) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) - ((concat_vec - (vec_of_bits - [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B1,B0] :: 2 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B1] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - :: 7 Word.word)) - :: 10 Word.word)) - :: 13 Word.word)) - :: 15 Word.word)) - :: 16 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - TLBIndexMax - ((concat_vec - (vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - ( - bool_to_bits - have_cp2 :: 1 Word.word)) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - :: 1 Word.word) - ( - vec_of_bits - [B0] - :: 1 Word.word) - :: 2 Word.word)) - :: 3 Word.word)) - :: 4 Word.word)) - :: 5 Word.word)) - :: 6 Word.word)) - :: 7 Word.word)) - :: 10 Word.word)) - :: 13 Word.word)) - :: 16 Word.word)) - :: 19 Word.word)) - :: 22 Word.word)) - :: 25 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B1,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - :: 8 Word.word)) - :: 12 Word.word)) - :: 16 Word.word)) - :: 20 Word.word)) - :: 24 Word.word)) - :: 28 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B1,B1] :: 3 Word.word))))))) then - return - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B1,B0,B1] :: 3 Word.word))))))) then - return - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits - [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits - [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - ( - vec_of_bits - [B1,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - ((( - b__49 = - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - read_reg - TLBXContext_ref - \<bind> - (\<lambda> (w__18 :: XContextReg) . - return - ((get_XContextReg - w__18 :: 64 Word.word))) - else - (read_reg - CP0ErrorEPC_ref :: ( 64 Word.word) M) - )) \<bind> (\<lambda> (result :: 64 bits) . + (checkCP0Access () \<then> + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (let (idx :: 31 bits) = ((mips_zero_extend (( 31 :: int)::ii) w__0 :: 31 Word.word)) in + (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + return ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) ((concat_vec w__1 idx :: 32 Word.word)) + :: 64 Word.word))))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__2 :: TLBIndexT) . + return ((mips_zero_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo0_ref \<bind> (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg_bits w__3 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo1_ref \<bind> (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg_bits w__4 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBContext_ref \<bind> (\<lambda> (w__5 :: ContextReg) . + return ((get_ContextReg_bits w__5 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec w__7 + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 28 Word.word)) + :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__8 :: TLBIndexT) . + return ((mips_zero_extend (( 64 :: int)::ii) w__8 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__9 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__11 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryHi_ref \<bind> (\<lambda> (w__12 :: TLBEntryHiReg) . + return ((get_TLBEntryHiReg_bits w__12 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Compare_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__13 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Status_ref \<bind> (\<lambda> (w__14 :: StatusReg) . + return ((mips_zero_extend (( 64 :: int)::ii) ((get_StatusReg_bits w__14 :: 32 Word.word)) :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Cause_ref \<bind> (\<lambda> (w__15 :: CauseReg) . + return ((mips_zero_extend (( 64 :: int)::ii) ((get_CauseReg_bits w__15 :: 32 Word.word)) :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0EPC_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0ConfigK0_ref :: ( 3 Word.word) M) \<bind> (\<lambda> (w__17 :: 3 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + w__17 + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 16 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec TLBIndexMax + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec + ((bool_to_bits have_cp2 :: 1 Word.word)) + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] + :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] + :: 1 Word.word) + (vec_of_bits [B0] + :: 1 Word.word) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 16 Word.word)) + :: 19 Word.word)) + :: 22 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 16 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBXContext_ref \<bind> (\<lambda> (w__19 :: XContextReg) . + return ((get_XContextReg_bits w__19 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0ErrorEPC_ref :: ( 64 Word.word) M) + else (SignalException ResI :: ( 64 Word.word) M) + )) \<bind> (\<lambda> (result :: 64 bits) . wGPR rt (if double then result else - (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))" + (mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))" (*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) @@ -6666,7 +6394,7 @@ definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6681,10 +6409,12 @@ definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) @@ -6695,7 +6425,7 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6710,10 +6440,12 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -6721,8 +6453,8 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_Load width sign linked base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - width + (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + LoadData width :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr else @@ -6731,33 +6463,28 @@ definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R (write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> write_reg CP0LLAddr_ref pAddr) \<then> (case width of - B => - (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . + W => + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . return ((extendLoad w__1 sign :: 64 Word.word))) - | H => - (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . - return ((extendLoad w__2 sign :: 64 Word.word))) - | W => - (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . - return ((extendLoad w__3 sign :: 64 Word.word))) | D => - (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . - return ((extendLoad w__4 sign :: 64 Word.word))) + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + return ((extendLoad w__2 sign :: 64 Word.word))) + | _ => throw (Error_internal_error () ) ) else (case width of B => - (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__6 :: 8 Word.word) . - return ((extendLoad w__6 sign :: 64 Word.word))) + (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__5 :: 8 Word.word) . + return ((extendLoad w__5 sign :: 64 Word.word))) | H => - (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . - return ((extendLoad w__7 sign :: 64 Word.word))) + (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . + return ((extendLoad w__6 sign :: 64 Word.word))) | W => - (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . - return ((extendLoad w__8 sign :: 64 Word.word))) + (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) . + return ((extendLoad w__7 sign :: 64 Word.word))) | D => - (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . - return ((extendLoad w__9 sign :: 64 Word.word))) + (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) . + return ((extendLoad w__8 sign :: 64 Word.word))) )) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rt memResult)))))" @@ -6767,11 +6494,11 @@ definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LWR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData WR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (MEMr_wrapper (( 32 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) (( 4 :: int)::ii) @@ -6792,7 +6519,7 @@ definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) :: 32 Word.word) else mem_val) in - wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))" (*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -6800,11 +6527,11 @@ definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LWL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData WL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (MEMr_wrapper (( 32 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) (( 4 :: int)::ii) @@ -6825,7 +6552,7 @@ definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) :: 32 Word.word)) in - wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))" (*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) @@ -6833,7 +6560,7 @@ definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LUI rt imm = ( wGPR rt - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) :: 32 Word.word)) @@ -6845,11 +6572,11 @@ definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LDR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData DR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . - (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper (( 64 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 64 Word.word)) (( 8 :: int)::ii) @@ -6893,11 +6620,11 @@ definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LDL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData DL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . - (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper (( 64 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 64 Word.word)) (( 8 :: int)::ii) @@ -6978,22 +6705,16 @@ definition execute_J :: "(26)Word.word \<Rightarrow>((register_value),(unit),(e :: 64 Word.word))))" -(*val execute_ImplementationDefinedStopFetching : unit -> unit*) - -definition execute_ImplementationDefinedStopFetching :: " unit \<Rightarrow> unit " where - " execute_ImplementationDefinedStopFetching g__118 = ( () )" - - (*val execute_HCF : unit -> unit*) definition execute_HCF :: " unit \<Rightarrow> unit " where - " execute_HCF g__123 = ( () )" + " execute_HCF g__21 = ( () )" (*val execute_ERET : unit -> M unit*) definition execute_ERET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_ERET g__128 = ( + " execute_ERET g__26 = ( (((checkCP0Access () \<then> ERETHook () ) \<then> write_reg CP0LLBit_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> @@ -7022,7 +6743,8 @@ definition execute_DSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (temp65 :: 65 bits) = - ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + ((sub_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) w__1 :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then @@ -7037,7 +6759,7 @@ definition execute_DSRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" (*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7046,7 +6768,7 @@ definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr " execute_DSRL32 rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" (*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7054,7 +6776,7 @@ definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_DSRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSRL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" (*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7065,7 +6787,7 @@ definition execute_DSRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" (*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7075,7 +6797,7 @@ definition execute_DSRA32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" (*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7084,7 +6806,7 @@ definition execute_DSRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow " execute_DSRA rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" (*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7093,7 +6815,7 @@ definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro " execute_DSLLV rs rt rd = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . wGPR rd w__2))))" @@ -7103,7 +6825,7 @@ definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSLL32 rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" @@ -7113,7 +6835,7 @@ definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_DSLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSLL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" (*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) @@ -7149,9 +6871,9 @@ definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)))))))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . return (w__0, w__1))) else (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in @@ -7160,8 +6882,8 @@ definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let ri = (hardware_mod si ti) in return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in - write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> - write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q :: 64 Word.word)))))))" (*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) @@ -7175,9 +6897,9 @@ definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)))))))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . return (w__0, w__1))) else (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in @@ -7186,8 +6908,8 @@ definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let ri = (si - ((ti * qi))) in return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in - write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> - write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q :: 64 Word.word)))))))" (*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) @@ -7200,9 +6922,9 @@ definition execute_DDIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let rtVal = (Word.uint w__1) in (if (((rtVal = (( 0 :: int)::ii)))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . return (w__2, w__3))) else (let qi = (hardware_quot rsVal rtVal) in @@ -7222,9 +6944,9 @@ definition execute_DDIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let rtVal = (Word.sint w__1) in (if (((rtVal = (( 0 :: int)::ii)))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . return (w__2, w__3))) else (let qi = (hardware_quot rsVal rtVal) in @@ -7248,7 +6970,7 @@ definition execute_DADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro definition execute_DADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DADDIU rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -7257,7 +6979,8 @@ definition execute_DADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro " execute_DADDI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let (sum65 :: 65 bits) = - ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm :: 65 Word.word)) + ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) imm :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then @@ -7272,7 +6995,8 @@ definition execute_DADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (sum65 :: 65 bits) = - ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) w__1 :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then @@ -7308,7 +7032,10 @@ definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) :: 5 Word.word)) ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) | CLo => - writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) null_cap + if (((i = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg null_cap :: 257 Word.word)) + else + writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) + null_cap | CHi => writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) @@ -7322,15 +7049,15 @@ definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CWriteHwr cb sel = ( checkCP2usable () \<then> - ((let l__24 = (Word.uint sel) in - (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False) - else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False) - else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True) - else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False) - else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False) - else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True) - else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True) - else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True) + ((let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 1 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 8 :: int)::ii)))) then return (False, True) + else if (((p00 = (( 22 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 23 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 29 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 30 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 31 :: int)::ii)))) then return (True, True) else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in register_inaccessible cb \<bind> (\<lambda> (w__8 :: bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb @@ -7346,17 +7073,22 @@ definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Right if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel else readCapReg cb \<bind> (\<lambda> capVal . - (let l__16 = (Word.uint sel) in - if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal - else if (((l__16 = (( 1 :: int)::ii)))) then + (let p00 = (Word.uint sel) in + if (((p00 = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 1 :: int)::ii)))) then write_reg CTLSU_ref ((capStructToCapReg capVal :: 257 Word.word)) - else if (((l__16 = (( 8 :: int)::ii)))) then + else if (((p00 = (( 8 :: int)::ii)))) then write_reg CTLSP_ref ((capStructToCapReg capVal :: 257 Word.word)) - else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal - else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal - else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal - else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal - else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal + else if (((p00 = (( 22 :: int)::ii)))) then + write_reg KR1C_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 23 :: int)::ii)))) then + write_reg KR2C_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 29 :: int)::ii)))) then + write_reg KCC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 30 :: int)::ii)))) then + write_reg KDC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 31 :: int)::ii)))) then + write_reg EPCC_ref ((capStructToCapReg capVal :: 257 Word.word)) else assert_exp False (''should be unreachable code'')))))))))))" @@ -7400,7 +7132,7 @@ definition execute_CUnseal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CToPtr rd cb ct = ( (checkCP2usable () \<then> - readCapReg ct) \<bind> (\<lambda> ct_val . + readCapRegDDC ct) \<bind> (\<lambda> ct_val . readCapReg cb \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb @@ -7429,7 +7161,7 @@ definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CTestSubset rd cb ct = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . readCapReg ct \<bind> (\<lambda> ct_val . (let ct_top = (getCapTop ct_val) in (let ct_base = (getCapBase ct_val) in @@ -7451,7 +7183,7 @@ definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rig else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) in - wGPR rd ((zero_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" (*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7478,7 +7210,7 @@ definition execute_CSub :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CStore rs cb rt rd offset width conditional = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7490,8 +7222,8 @@ definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + size1)) > ((getCapTop cb_val)))) then @@ -7517,7 +7249,7 @@ definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val ) else return False) \<bind> (\<lambda> (success :: bool) . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else (case width of B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) @@ -7694,7 +7426,7 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> " execute_CSC cs cb rt rd offset conditional = ( (checkCP2usable () \<then> readCapReg cs) \<bind> (\<lambda> cs_val . - readCapReg cb \<bind> (\<lambda> cb_val . + readCapRegDDC cb \<bind> (\<lambda> cb_val . register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs else @@ -7712,15 +7444,14 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then - SignalExceptionBadAddr AdES vAddr64 + else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdES vAddr64 else (TLBTranslateC vAddr64 StoreData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, noStoreCap) = varstup in if ((((CapStruct_tag cs_val) \<and> noStoreCap))) then @@ -7731,14 +7462,14 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> MEMw_tagged_conditional pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)) else return False) \<bind> (\<lambda> success . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else MEMw_tagged pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)))))))))))))" (*val execute_CReturn : unit -> M unit*) definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_CReturn g__129 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" + " execute_CReturn g__27 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" (*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) @@ -7746,15 +7477,15 @@ definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exc definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CReadHwr cd1 sel = ( checkCP2usable () \<then> - ((let l__8 = (Word.uint sel) in - (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False) - else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False) - else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True) - else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False) - else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False) - else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True) - else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True) - else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True) + ((let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 1 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 8 :: int)::ii)))) then return (False, True) + else if (((p00 = (( 22 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 23 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 29 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 30 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 31 :: int)::ii)))) then return (True, True) else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in register_inaccessible cd1 \<bind> (\<lambda> (w__8 :: bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 @@ -7769,19 +7500,31 @@ definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel else - (let l__0 = (Word.uint sel) in - (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC - else if (((l__0 = (( 1 :: int)::ii)))) then + (let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__13 :: 257 Word.word) . + return ((capRegToCapStruct w__13))) + else if (((p00 = (( 1 :: int)::ii)))) then (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . return ((capRegToCapStruct w__14))) - else if (((l__0 = (( 8 :: int)::ii)))) then + else if (((p00 = (( 8 :: int)::ii)))) then (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__15 :: 257 Word.word) . return ((capRegToCapStruct w__15))) - else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C - else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C - else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC - else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC - else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC + else if (((p00 = (( 22 :: int)::ii)))) then + (read_reg KR1C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 :: 257 Word.word) . + return ((capRegToCapStruct w__16))) + else if (((p00 = (( 23 :: int)::ii)))) then + (read_reg KR2C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__17 :: 257 Word.word) . + return ((capRegToCapStruct w__17))) + else if (((p00 = (( 29 :: int)::ii)))) then + (read_reg KCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 :: 257 Word.word) . + return ((capRegToCapStruct w__18))) + else if (((p00 = (( 30 :: int)::ii)))) then + (read_reg KDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__19 :: 257 Word.word) . + return ((capRegToCapStruct w__19))) + else if (((p00 = (( 31 :: int)::ii)))) then + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__20 :: 257 Word.word) . + return ((capRegToCapStruct w__20))) else assert_exp False (''should be unreachable code'') \<then> undefined_CapStruct () ) \<bind> (\<lambda> (capVal :: CapStruct) . writeCapReg cd1 capVal))))))))))" @@ -7832,7 +7575,7 @@ definition execute_CPtrCmp :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar | CEXEQ => (cb_val = ct_val) | CNEXEQ => (cb_val \<noteq> ct_val) )) in - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" (*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) @@ -7864,7 +7607,7 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (case merge_var of (rd, cb, rt, offset, signext, B, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7875,8 +7618,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7891,12 +7634,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__2 :: 8 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . + (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, D, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7907,8 +7650,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7923,12 +7666,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, H, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7939,8 +7682,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7955,12 +7698,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__2 :: 16 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . + (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, W, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7971,8 +7714,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7987,18 +7730,18 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) )))" -(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty16 -> bool -> M unit*) -definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CLC cd1 cb rt offset linked = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else @@ -8012,15 +7755,14 @@ definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then - SignalExceptionBadAddr AdEL vAddr64 + else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdEL vAddr64 else (TLBTranslateC vAddr64 LoadData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, suppressTag) = varstup in (let cd1 = (Word.uint cd1) in @@ -8065,7 +7807,7 @@ definition execute_CJALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL + else if (((((cb_ptr mod (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL else (if link then (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__3 :: 257 Word.word) . @@ -8084,7 +7826,7 @@ definition execute_CIncOffsetImmediate :: "(5)Word.word \<Rightarrow>(5)Word.wo " execute_CIncOffsetImmediate cd1 cb imm = ( (checkCP2usable () \<then> readCapReg cb) \<bind> (\<lambda> cb_val . - (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (imm64 :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else @@ -8144,7 +7886,8 @@ definition execute_CGetType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - (if(CapStruct_sealed capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) + (if(CapStruct_sealed capVal) then + (mips_zero_extend (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) else (replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))" @@ -8158,7 +7901,7 @@ definition execute_CGetTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" + ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" (*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) @@ -8171,7 +7914,8 @@ definition execute_CGetSealed :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) :: 64 Word.word)))))" + ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) + :: 64 Word.word)))))" (*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) @@ -8183,7 +7927,7 @@ definition execute_CGetPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else readCapReg cb \<bind> (\<lambda> capVal . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" (*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) @@ -8256,7 +8000,7 @@ definition execute_CGetCause :: "(5)Word.word \<Rightarrow>((register_value),(u if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation else read_reg CapCause_ref \<bind> (\<lambda> (w__1 :: CapCauseReg) . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1 :: 16 Word.word)) :: 64 Word.word)))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((get_CapCauseReg_bits w__1 :: 16 Word.word)) :: 64 Word.word)))))" (*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) @@ -8290,14 +8034,18 @@ definition execute_CGetAddr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta definition execute_CFromPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CFromPtr cd1 cb rt = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then writeCapReg cd1 null_cap + else if (((rt_val = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + writeCapReg cd1 null_cap else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb else @@ -8387,7 +8135,7 @@ definition execute_CCheckPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ (checkCP2usable () \<then> readCapReg cs) \<bind> (\<lambda> cs_val . (let (cs_perms :: 64 bits) = - ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in + ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_perms . register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs @@ -8509,7 +8257,7 @@ definition execute_CCSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_CBuildCap :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CBuildCap cd1 cb ct = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . readCapReg ct \<bind> (\<lambda> ct_val . (let cb_base = (getCapBase cb_val) in (let ct_base = (getCapBase ct_val) in @@ -8560,7 +8308,7 @@ definition execute_CBZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in @@ -8584,7 +8332,7 @@ definition execute_CBX :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in @@ -8630,7 +8378,7 @@ definition execute_C2Dump :: "(5)Word.word \<Rightarrow> unit " where (*val execute_BREAK : unit -> M unit*) definition execute_BREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_BREAK g__120 = ( SignalException Bp )" + " execute_BREAK g__18 = ( SignalException Bp )" (*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) @@ -8645,7 +8393,8 @@ definition execute_BEQ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . @@ -8664,11 +8413,12 @@ definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii) :: 64 Word.word)) in (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> regVal . (let condition = - (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (compare cmp regVal ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in (if condition then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . @@ -8686,7 +8436,7 @@ definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr definition execute_ANDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_ANDI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -8706,10 +8456,10 @@ definition execute_ADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) @@ -8723,12 +8473,12 @@ definition execute_ADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . if ((NotWordVal opA)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) else wGPR rt - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) - ((sign_extend1 (( 32 :: int)::ii) imm :: 32 Word.word)) + ((mips_sign_extend (( 32 :: int)::ii) imm :: 32 Word.word)) :: 32 Word.word)) :: 64 Word.word))))" @@ -8740,19 +8490,20 @@ definition execute_ADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . if ((NotWordVal opA)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) else (let (sum33 :: 33 bits) = ((add_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) imm :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) ((mips_sign_extend (( 33 :: int)::ii) imm :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rt - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))" (*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -8763,19 +8514,22 @@ definition execute_ADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (opB :: 64 bits) . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let (sum33 :: 33 bits) = ((add_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where @@ -8843,12 +8597,9 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (JALR (rs,rd)) = ( execute_JALR rs rd )" |" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )" |" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )" -|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))" -|" execute (ImplementationDefinedStopFetching (g__118)) = ( - return ((execute_ImplementationDefinedStopFetching g__118)))" -|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )" -|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )" -|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )" +|" execute (SYSCALL (g__17)) = ( execute_SYSCALL g__17 )" +|" execute (BREAK (g__18)) = ( execute_BREAK g__18 )" +|" execute (WAIT (g__19)) = ( execute_WAIT g__19 )" |" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )" |" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )" |" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )" @@ -8862,17 +8613,16 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )" |" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )" |" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )" -|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))" -|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )" +|" execute (SYNC (g__20)) = ( execute_SYNC g__20 )" |" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )" -|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))" +|" execute (HCF (g__21)) = ( return ((execute_HCF g__21)))" |" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )" -|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )" -|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )" -|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )" -|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )" +|" execute (TLBWI (g__22)) = ( execute_TLBWI g__22 )" +|" execute (TLBWR (g__23)) = ( execute_TLBWR g__23 )" +|" execute (TLBR (g__24)) = ( execute_TLBR g__24 )" +|" execute (TLBP (g__25)) = ( execute_TLBP g__25 )" |" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )" -|" execute (ERET (g__128)) = ( execute_ERET g__128 )" +|" execute (ERET (g__26)) = ( execute_ERET g__26 )" |" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )" |" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )" |" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )" @@ -8910,7 +8660,7 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )" |" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )" |" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )" -|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )" +|" execute (CReturn (g__27)) = ( execute_CReturn g__27 )" |" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )" |" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )" |" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )" @@ -8921,7 +8671,7 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )" |" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )" |" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))" -|" execute (RI (g__130)) = ( execute_RI g__130 )" +|" execute (RI (g__28)) = ( execute_RI g__28 )" (*val supported_instructions : ast -> maybe ast*) @@ -8930,50 +8680,62 @@ definition supported_instructions :: " ast \<Rightarrow>(ast)option " where " supported_instructions instr = ( Some instr )" -(*val fetch_and_execute : unit -> M unit*) +(*val cycle_limit_reached : unit -> bool*) -definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " fetch_and_execute _ = ( - catch_early_return - (((whileM () - (\<lambda> unit_var . return True) - (\<lambda> unit_var . - liftR ((read_reg nextPC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . - (liftR (write_reg PC_ref w__0) \<then> - liftR ((read_reg branchPending_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__1 :: 1 bits) . - ((liftR (write_reg inBranchDelay_ref w__1) \<then> - liftR (write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word))) \<then> - liftR ((read_reg inBranchDelay_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__2 :: 1 Word.word) . - (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref :: ( 64 Word.word) M)) - else - liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 Word.word) . - return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . - ((liftR (write_reg nextPC_ref w__5) \<then> - liftR (cp2_next_pc () )) \<then> - liftR (read_reg instCount_ref)) \<bind> (\<lambda> (w__6 :: ii) . - (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \<then> - liftR ((read_reg PC_ref :: ( 64 Word.word) M))) \<bind> (\<lambda> (w__7 :: 64 bits) . - (let (_ :: unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in - try_catchR (liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 Word.word) . - liftR ((TranslatePC w__8 :: ( 64 Word.word) M)) \<bind> (\<lambda> pc_pa . - liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> instr . - (let instr_ast = (decode instr) in - (case instr_ast of - Some ((HCF (_))) => - (let (_ :: unit) = - (prerr_endline (''simulation stopped due to halt instruction.'')) in - (early_return () :: (unit, unit) MR)) - | Some (ast) => liftR (execute ast) - | None => - (let (_ :: unit) = (prerr_endline (''Decode failed'')) in - liftR (exit0 () )) - )))))) (\<lambda>x . - (case x of ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \<then> - liftR (skip () )) \<then> liftR (skip () )))" +definition cycle_limit_reached :: " unit \<Rightarrow> bool " where + " cycle_limit_reached _ = ( False )" -(*val main : unit -> M unit*) +(*val fetch_and_execute : unit -> M bool*) + +definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " fetch_and_execute _ = ( + (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (write_reg PC_ref w__0 \<then> + (read_reg branchPending_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__1 :: 1 bits) . + ((write_reg inBranchDelay_ref w__1 \<then> + write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> + (read_reg inBranchDelay_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (if ((bits_to_bool w__2)) then (read_reg delayedPC_ref :: ( 64 Word.word) M) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . + ((write_reg nextPC_ref w__5 \<then> + cp2_next_pc () ) \<then> + read_reg instCount_ref) \<bind> (\<lambda> (w__6 :: ii) . + (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii))) \<then> + (read_reg UART_WRITTEN_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__7 :: 1 Word.word) . + (((if ((bits_to_bool w__7)) then + (read_reg UART_WDATA_ref :: ( 8 Word.word) M) \<bind> (\<lambda> (w__8 :: 8 bits) . + (let (_ :: unit) = (putchar ((Word.uint w__8))) in + write_reg UART_WRITTEN_ref (vec_of_bits [B0] :: 1 Word.word))) + else return () ) \<then> + skip () ) \<then> + skip () ) \<then> + ((let loop_again = True in + try_catch ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . + (TranslatePC w__9 :: ( 64 Word.word) M) \<bind> (\<lambda> pc_pa . + (MEMr_wrapper (( 32 :: int)::ii) pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> instr . + (let instr_ast = (decode instr) in + (case instr_ast of + Some ((HCF (_))) => + (let (_ :: unit) = (print_endline (''simulation stopped due to halt instruction.'')) in + return False) + | Some (ast) => execute ast \<then> return loop_again + | None => + (let (_ :: unit) = (print_endline (''Decode failed'')) in + return False) + )))))) (\<lambda>x . + (case x of ISAException (_) => return loop_again )) \<bind> (\<lambda> (loop_again :: bool) . + return (((loop_again \<and> ((\<not> ((cycle_limit_reached () )))))))))))))))))" + + +(*val init_registers : mword ty64 -> M unit*) + +definition init_registers :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_registers initialPC = ( + (init_cp0_state () \<then> init_cp2_state () ) \<then> write_reg nextPC_ref initialPC )" + (*val dump_mips_state : unit -> M unit*) @@ -8981,38 +8743,36 @@ definition dump_mips_state :: " unit \<Rightarrow>((register_value),(unit),(exc " dump_mips_state _ = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (let (_ :: unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in + instance_Sail2_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> idx unit_var . (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) idx :: 5 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . return ((let _ = - (prerr_endline + (print_endline (((op@) (''DEBUG MIPS REG '') (((op@) ((string_of_int - instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits w__1))))))))) in () ))))))))" +(*val main : unit -> M unit*) + definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " main _ = ( - ((init_cp0_state () \<then> - init_cp2_state () ) \<then> - write_reg - nextPC_ref - ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word))) \<then> + init_registers + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word)) \<then> ((let startTime = (get_time_ns () ) in - fetch_and_execute () \<then> + (whileM () (\<lambda> unit_var . fetch_and_execute () ) (\<lambda> unit_var . return () )) \<then> ((let endTime = (get_time_ns () ) in (let elapsed = (endTime - startTime) in - read_reg instCount_ref \<bind> (\<lambda> (w__0 :: ii) . - (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in + read_reg instCount_ref \<bind> (\<lambda> (w__1 :: ii) . + (let inst_1e9 = (w__1 * (( 1000000000 :: int)::ii)) in (let ips = (inst_1e9 div elapsed) in ((dump_mips_state () \<then> dump_cp2_state () ) \<then> - read_reg instCount_ref) \<bind> (\<lambda> (w__1 :: ii) . - (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in + read_reg instCount_ref) \<bind> (\<lambda> (w__2 :: ii) . + (let (_ :: unit) = (print_int (''Executed instructions: '') w__2) in (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in return ((print_int (''Instructions per second: '') ips))))))))))))))" @@ -9022,19 +8782,19 @@ definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))mon definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " initialize_registers _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (write_reg PC_ref w__0 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . (write_reg nextPC_ref w__1 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . (write_reg TLBProbe_ref w__2 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . (write_reg TLBIndex_ref w__3 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . (write_reg TLBRandom_ref w__4 \<then> undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__5 :: TLBEntryLoReg) . (write_reg TLBEntryLo0_ref w__5 \<then> @@ -9043,10 +8803,10 @@ definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit) undefined_ContextReg () ) \<bind> (\<lambda> (w__7 :: ContextReg) . (write_reg TLBContext_ref w__7 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . (write_reg TLBPageMask_ref w__8 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . (write_reg TLBWired_ref w__9 \<then> undefined_TLBEntryHiReg () ) \<bind> (\<lambda> (w__10 :: TLBEntryHiReg) . (write_reg TLBEntryHi_ref w__10 \<then> @@ -9181,191 +8941,270 @@ definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit) undefined_TLBEntry () ) \<bind> (\<lambda> (w__75 :: TLBEntry) . (write_reg TLBEntry63_ref w__75 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . (write_reg CP0Compare_ref w__76 \<then> undefined_CauseReg () ) \<bind> (\<lambda> (w__77 :: CauseReg) . (write_reg CP0Cause_ref w__77 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . (write_reg CP0EPC_ref w__78 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . (write_reg CP0ErrorEPC_ref w__79 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . (write_reg CP0LLBit_ref w__80 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . (write_reg CP0LLAddr_ref w__81 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . (write_reg CP0BadVAddr_ref w__82 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . (write_reg CP0Count_ref w__83 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . (write_reg CP0HWREna_ref w__84 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . (write_reg CP0UserLocal_ref w__85 \<then> - undefined_StatusReg () ) \<bind> (\<lambda> (w__86 :: StatusReg) . - (write_reg CP0Status_ref w__86 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__87 :: 1 bits) . - (write_reg branchPending_ref w__87 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M)) \<bind> (\<lambda> (w__86 :: 3 bits) . + (write_reg CP0ConfigK0_ref w__86 \<then> + undefined_StatusReg () ) \<bind> (\<lambda> (w__87 :: StatusReg) . + (write_reg CP0Status_ref w__87 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . + (write_reg branchPending_ref w__88 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__89 :: 1 bits) . + (write_reg inBranchDelay_ref w__89 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . + (write_reg delayedPC_ref w__90 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . + (write_reg HI_ref w__91 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . - (write_reg inBranchDelay_ref w__88 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 bits) . + (write_reg LO_ref w__92 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . - (write_reg delayedPC_ref w__89 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__93 :: 64 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__93 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__94 :: ( 64 bits) list) . + (write_reg GPR_ref w__94 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . - (write_reg HI_ref w__90 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__95 :: 8 bits) . + (write_reg UART_WDATA_ref w__95 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . - (write_reg LO_ref w__91 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__96 :: 1 bits) . + (write_reg UART_WRITTEN_ref w__96 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 Word.word) . - (undefined_vector (( 32 :: int)::ii) w__92 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__93 :: ( 64 bits) list) . - (write_reg GPR_ref w__93 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__97 :: 8 bits) . + (write_reg UART_RDATA_ref w__97 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__94 :: 8 bits) . - (write_reg UART_WDATA_ref w__94 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__98 :: 1 bits) . + (write_reg UART_RVALID_ref w__98 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__95 :: 1 bits) . - (write_reg UART_WRITTEN_ref w__95 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . + (write_reg PCC_ref w__99 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__96 :: 8 bits) . - (write_reg UART_RDATA_ref w__96 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . + (write_reg nextPCC_ref w__100 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__97 :: 1 bits) . - (write_reg UART_RVALID_ref w__97 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__101 :: CapReg) . + (write_reg delayedPCC_ref w__101 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__98 :: CapReg) . - (write_reg PCC_ref w__98 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__102 :: 1 bits) . + (write_reg inCCallDelay_ref w__102 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . - (write_reg nextPCC_ref w__99 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . + (write_reg DDC_ref w__103 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . - (write_reg delayedPCC_ref w__100 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . + (write_reg C01_ref w__104 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__101 :: 1 bits) . - (write_reg inCCallDelay_ref w__101 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . + (write_reg C02_ref w__105 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__102 :: CapReg) . - (write_reg C00_ref w__102 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . + (write_reg C03_ref w__106 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . - (write_reg C01_ref w__103 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . + (write_reg C04_ref w__107 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . - (write_reg C02_ref w__104 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . + (write_reg C05_ref w__108 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . - (write_reg C03_ref w__105 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . + (write_reg C06_ref w__109 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . - (write_reg C04_ref w__106 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . + (write_reg C07_ref w__110 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . - (write_reg C05_ref w__107 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . + (write_reg C08_ref w__111 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . - (write_reg C06_ref w__108 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . + (write_reg C09_ref w__112 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . - (write_reg C07_ref w__109 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . + (write_reg C10_ref w__113 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . - (write_reg C08_ref w__110 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . + (write_reg C11_ref w__114 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . - (write_reg C09_ref w__111 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . + (write_reg C12_ref w__115 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . - (write_reg C10_ref w__112 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . + (write_reg C13_ref w__116 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . - (write_reg C11_ref w__113 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . + (write_reg C14_ref w__117 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . - (write_reg C12_ref w__114 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . + (write_reg C15_ref w__118 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . - (write_reg C13_ref w__115 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . + (write_reg C16_ref w__119 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . - (write_reg C14_ref w__116 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . + (write_reg C17_ref w__120 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . - (write_reg C15_ref w__117 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . + (write_reg C18_ref w__121 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . - (write_reg C16_ref w__118 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . + (write_reg C19_ref w__122 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . - (write_reg C17_ref w__119 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . + (write_reg C20_ref w__123 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . - (write_reg C18_ref w__120 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . + (write_reg C21_ref w__124 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . - (write_reg C19_ref w__121 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . + (write_reg C22_ref w__125 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . - (write_reg C20_ref w__122 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . + (write_reg C23_ref w__126 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . - (write_reg C21_ref w__123 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . + (write_reg C24_ref w__127 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . - (write_reg C22_ref w__124 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . + (write_reg C25_ref w__128 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . - (write_reg C23_ref w__125 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . + (write_reg C26_ref w__129 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . - (write_reg C24_ref w__126 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . + (write_reg C27_ref w__130 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . - (write_reg C25_ref w__127 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . + (write_reg C28_ref w__131 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . - (write_reg C26_ref w__128 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . + (write_reg C29_ref w__132 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . - (write_reg C27_ref w__129 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . + (write_reg C30_ref w__133 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . - (write_reg C28_ref w__130 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . + (write_reg C31_ref w__134 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . - (write_reg C29_ref w__131 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . + (write_reg CTLSU_ref w__135 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . - (write_reg C30_ref w__132 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__136 :: CapReg) . + (write_reg CTLSP_ref w__136 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . - (write_reg C31_ref w__133 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__137 :: CapReg) . + (write_reg KR1C_ref w__137 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . - (write_reg CTLSU_ref w__134 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__138 :: CapReg) . + (write_reg KR2C_ref w__138 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . - (write_reg CTLSP_ref w__135 \<then> - undefined_CapCauseReg () ) \<bind> (\<lambda> (w__136 :: CapCauseReg) . - (write_reg CapCause_ref w__136 \<then> - undefined_int () ) \<bind> (\<lambda> (w__137 :: ii) . write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__139 :: CapReg) . + (write_reg KCC_ref w__139 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__140 :: CapReg) . + (write_reg KDC_ref w__140 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__141 :: CapReg) . + (write_reg EPCC_ref w__141 \<then> + undefined_CapCauseReg () ) \<bind> (\<lambda> (w__142 :: CapCauseReg) . + (write_reg CapCause_ref w__142 \<then> + undefined_int () ) \<bind> (\<lambda> (w__143 :: ii) . write_reg instCount_ref w__143)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" definition initial_regstate :: " regstate " where " initial_regstate = ( (| instCount = ((( 0 :: int)::ii)), CapCause = - (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + ((| CapCauseReg_CapCauseReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)) |)), + EPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KDC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KR2C = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KR1C = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), CTLSP = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -9762,7 +9601,7 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 257 Word.word)), - C00 = + DDC = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -9962,9 +9801,11 @@ definition initial_regstate :: " regstate " where inBranchDelay = ((vec_of_bits [B0] :: 1 Word.word)), branchPending = ((vec_of_bits [B0] :: 1 Word.word)), CP0Status = - (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word)), + ((| StatusReg_StatusReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), + CP0ConfigK0 = ((vec_of_bits [B0,B0,B0] :: 3 Word.word)), CP0UserLocal = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -10000,557 +9841,750 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), CP0Cause = - (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word)), + ((| CauseReg_CauseReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), CP0Compare = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0] :: 32 Word.word)), TLBEntry63 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry62 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry61 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry60 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry59 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry58 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry57 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry56 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry55 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry54 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry53 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry52 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry51 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry50 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry49 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry48 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry47 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry46 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry45 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry44 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry43 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry42 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry41 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry40 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry39 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry38 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry37 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry36 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry35 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry34 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry33 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry32 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry31 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry30 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry29 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry28 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry27 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry26 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry25 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry24 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry23 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry22 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry21 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry20 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry19 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry18 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry17 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry16 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry15 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry14 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry13 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry12 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry11 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry10 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry09 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry08 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry07 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry06 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry05 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry04 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry03 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry02 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry01 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry00 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBXContext = - (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| XContextReg_XContextReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryHi = - (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), TLBContext = - (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| ContextReg_ContextReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryLo1 = - (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryLo0 = - (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBProbe = ((vec_of_bits [B0] :: 1 Word.word)), |